369 lines
15 KiB
Plaintext
369 lines
15 KiB
Plaintext
--
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-- Copyright (C) 2015-2018 secunet Security Networks AG
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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private package HW.GFX.GMA.Config is
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Gen : constant Generation := <<GEN>>;
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CPU_First : constant CPU_Type :=
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(case Gen is
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when G45 => G45,
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when Ironlake => Ironlake,
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when Haswell => Haswell,
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when Broxton => Broxton,
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when Skylake => Skylake);
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CPU_Last : constant CPU_Type :=
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(case Gen is
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when G45 => G45,
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when Ironlake => Ivybridge,
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when Haswell => Broadwell,
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when Broxton => Broxton,
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when Skylake => Skylake);
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CPU_Var_Last : constant CPU_Variant :=
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(case Gen is
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when Haswell | Skylake => ULT,
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when others => Normal);
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subtype Gen_CPU_Type is CPU_Type range CPU_First .. CPU_Last;
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subtype Gen_CPU_Variant is CPU_Variant range Normal .. CPU_Var_Last;
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CPU : constant Gen_CPU_Type := <<CPU>>;
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CPU_Var : constant Gen_CPU_Variant := <<CPU_VARIANT>>;
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Internal_Display : constant Internal_Type := <<INTERNAL_PORT>>;
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Analog_I2C_Port : constant PCH_Port := <<ANALOG_I2C_PORT>>;
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EDP_Low_Voltage_Swing : constant Boolean := False;
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DDI_HDMI_Buffer_Translation : constant Integer := -1;
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Default_MMIO_Base : constant := <<DEFAULT_MMIO_BASE>>;
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LVDS_Dual_Threshold : constant := 95_000_000;
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----------------------------------------------------------------------------
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type Valid_Port_Array is array (Port_Type) of Boolean;
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type Variable_Config is record
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Valid_Port : Valid_Port_Array;
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Raw_Clock : Frequency_Type;
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Dyn_CPU : Gen_CPU_Type;
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Dyn_CPU_Var : Gen_CPU_Variant;
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end record;
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Initial_Settings : constant Variable_Config :=
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(Valid_Port => (others => False),
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Raw_Clock => Frequency_Type'First,
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Dyn_CPU => Gen_CPU_Type'First,
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Dyn_CPU_Var => Gen_CPU_Variant'First);
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Variable : Variable_Config with Part_Of => GMA.Config_State;
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Valid_Port : Valid_Port_Array renames Variable.Valid_Port;
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Raw_Clock : Frequency_Type renames Variable.Raw_Clock;
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CPU : Gen_CPU_Type renames Variable.Dyn_CPU;
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CPU_Var : Gen_CPU_Variant renames Variable.Dyn_CPU_Var;
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----------------------------------------------------------------------------
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-- To support both static configurations, that are compiled for a
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-- fixed CPU, and dynamic configurations, where the CPU and its
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-- variant are detected at runtime, all derived config values are
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-- tagged based on their dependencies.
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--
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-- Booleans that only depend on the generation should be tagged
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-- <genbool>. Those that may depend on the CPU are tagged with the
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-- generations where that is the case. For instance `CPU_Ivybridge`
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-- can be decided purely based on the generation unless the gene-
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-- ration is Ironlake, thus, it is tagged <ilkbool>.
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--
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-- For non-boolean constants, per generation tags <...var> are
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-- used (e.g. <ilkvar>).
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--
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-- To ease parsing, all multiline expressions of tagged config
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-- values start after a line break.
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Gen_G45 : <genbool> := Gen = G45;
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Gen_Ironlake : <genbool> := Gen = Ironlake;
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Gen_Haswell : <genbool> := Gen = Haswell;
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Gen_Broxton : <genbool> := Gen = Broxton;
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Gen_Skylake : <genbool> := Gen = Skylake;
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Up_To_Ironlake : <genbool> := Gen <= Ironlake;
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Ironlake_On : <genbool> := Gen >= Ironlake;
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Haswell_On : <genbool> := Gen >= Haswell;
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Broxton_On : <genbool> := Gen >= Broxton;
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Skylake_On : <genbool> := Gen >= Skylake;
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CPU_Ironlake : <ilkbool> := Gen_Ironlake and then CPU = Ironlake;
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CPU_Sandybridge : <ilkbool> := Gen_Ironlake and then CPU = Sandybridge;
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CPU_Ivybridge : <ilkbool> := Gen_Ironlake and then CPU = Ivybridge;
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CPU_Haswell : <hswbool> := Gen_Haswell and then CPU = Haswell;
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CPU_Broadwell : <hswbool> := Gen_Haswell and then CPU = Broadwell;
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Sandybridge_On : <ilkbool> :=
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((Gen_Ironlake and then CPU >= Sandybridge) or Haswell_On);
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Ivybridge_On : <ilkbool> :=
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((Gen_Ironlake and then CPU >= Ivybridge) or Haswell_On);
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Broadwell_On : <hswbool> :=
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((Gen_Haswell and then CPU >= Broadwell) or Broxton_On);
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----------------------------------------------------------------------------
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Have_HDMI_Buf_Override : constant Boolean := DDI_HDMI_Buffer_Translation >= 0;
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Default_MMIO_Base_Set : constant Boolean := Default_MMIO_Base /= 0;
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Has_Internal_Display : constant Boolean := Internal_Display /= None;
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Internal_Is_LVDS : constant Boolean := Internal_Display = LVDS;
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Internal_Is_EDP : constant Boolean := Internal_Display = DP;
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Have_DVI_I : constant Boolean := Analog_I2C_Port /= PCH_DAC;
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Has_Presence_Straps : <genbool> := not Gen_Broxton;
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Is_ULT : <hswsklbool> :=
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((Gen_Haswell or Gen_Skylake) and then CPU_Var = ULT);
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---------- CPU pipe: ---------
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Has_Tertiary_Pipe : <ilkbool> := Ivybridge_On;
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Disable_Trickle_Feed : <genbool> := not Gen_Haswell;
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Pipe_Enabled_Workaround : <hswbool> := CPU_Broadwell;
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Has_EDP_Transcoder : <genbool> := Haswell_On;
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Use_PDW_For_EDP_Scaling : <hswbool> := CPU_Haswell;
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Has_Pipe_DDI_Func : <genbool> := Haswell_On;
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Has_Trans_Clk_Sel : <genbool> := Haswell_On;
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Has_Pipe_MSA_Misc : <genbool> := Haswell_On;
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Has_Pipeconf_Misc : <hswbool> := Broadwell_On;
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Has_Pipeconf_BPC : <hswbool> := not CPU_Haswell;
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Has_Plane_Control : <genbool> := Broxton_On;
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Has_DSP_Linoff : <genbool> := Up_To_Ironlake;
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Has_PF_Pipe_Select : <ilkhswbool> := CPU_Ivybridge or CPU_Haswell;
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Has_Cursor_FBC_Control : <ilkbool> := Ivybridge_On;
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VGA_Plane_Workaround : <ilkbool> := CPU_Ivybridge;
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Has_GMCH_DP_Transcoder : <genbool> := Gen_G45;
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Has_GMCH_VGACNTRL : <genbool> := Gen_G45;
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Has_GMCH_PFIT_CONTROL : <genbool> := Gen_G45;
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--------- Panel power: -------
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Has_PP_Write_Protection : <genbool> := Up_To_Ironlake;
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Has_PP_Port_Select : <genbool> := Up_To_Ironlake;
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Use_PP_VDD_Override : <genbool> := Up_To_Ironlake;
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Has_PCH_Panel_Power : <genbool> := Ironlake_On;
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----------- PCH/FDI: ---------
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Has_PCH : <genbool> := not Gen_Broxton and not Gen_G45;
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Has_PCH_DAC : <hswbool> :=
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(Gen_Ironlake or (Gen_Haswell and then not Is_ULT));
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Has_PCH_Aux_Channels : <genbool> := Gen_Ironlake or Gen_Haswell;
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VGA_Has_Sync_Disable : <genbool> := Up_To_Ironlake;
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Has_Trans_Timing_Ovrrde : <ilkbool> := Sandybridge_On;
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Has_DPLL_SEL : <genbool> := Gen_Ironlake;
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Has_FDI_BPC : <genbool> := Gen_Ironlake;
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Has_FDI_Composite_Sel : <ilkbool> := CPU_Ivybridge;
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Has_New_FDI_Sink : <ilkbool> := Sandybridge_On;
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Has_New_FDI_Source : <ilkbool> := Ivybridge_On;
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Has_Trans_DP_Ctl : <ilkbool> := CPU_Sandybridge or CPU_Ivybridge;
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Has_FDI_C : <ilkbool> := CPU_Ivybridge;
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Has_FDI_RX_Power_Down : <genbool> := Gen_Haswell;
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Has_GMCH_RawClk : <genbool> := Gen_G45;
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----------- DDI: -------------
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End_EDP_Training_Late : <genbool> := Gen_Haswell;
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Has_Per_DDI_Clock_Sel : <genbool> := Gen_Haswell;
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Has_HOTPLUG_CTL : <genbool> := Gen_Haswell;
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Has_SHOTPLUG_CTL_A : <hswbool> :=
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((Gen_Haswell and then Is_ULT) or Skylake_On);
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Has_DDI_PHYs : <genbool> := Gen_Broxton;
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Has_DDI_D : <hswsklbool> :=
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((Gen_Haswell or Gen_Skylake) and then not Is_ULT);
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-- might be disabled by x4 eDP:
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Has_DDI_E : <hswsklbool> := Has_DDI_D;
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Has_DDI_Buffer_Trans : <genbool> := Haswell_On and not Has_DDI_PHYs;
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Has_Low_Voltage_Swing : <genbool> := Broxton_On;
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Has_Iboost_Config : <genbool> := Skylake_On;
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Need_DP_Aux_Mutex : <genbool> := False; -- Skylake & (PSR | GTC)
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----------- GMBUS: -----------
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Ungate_GMBUS_Unit_Level : <genbool> := Skylake_On;
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GMBUS_Alternative_Pins : <genbool> := Gen_Broxton;
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Has_PCH_GMBUS : <genbool> := Ironlake_On;
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----------- Power: -----------
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Has_IPS : <hswbool> :=
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(Gen_Haswell and then
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((CPU_Haswell and Is_ULT) or CPU_Broadwell));
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Has_IPS_CTL_Mailbox : <hswbool> := CPU_Broadwell;
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Has_Per_Pipe_SRD : <hswbool> := Broadwell_On;
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----------- GTT: -------------
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Has_64bit_GTT : <hswbool> := Broadwell_On;
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----------------------------------------------------------------------------
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Max_Pipe : <ilkvar> Pipe_Index :=
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(if Has_Tertiary_Pipe then Tertiary else Secondary);
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Last_Digital_Port : <hswsklvar> Digital_Port :=
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(if Has_DDI_E then DIGI_E else DIGI_C);
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----------------------------------------------------------------------------
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type FDI_Per_Port is array (Port_Type) of Boolean;
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Is_FDI_Port : <hswvar> FDI_Per_Port :=
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(Disabled => False,
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Internal => Gen_Ironlake and Internal_Is_LVDS,
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DP1 .. HDMI3 => Gen_Ironlake,
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Analog => Has_PCH_DAC);
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type FDI_Lanes_Per_Port is array (GPU_Port) of DP_Lane_Count;
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FDI_Lane_Count : constant FDI_Lanes_Per_Port :=
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(DIGI_D => DP_Lane_Count_2,
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others => (if Gen_Ironlake then DP_Lane_Count_4 else DP_Lane_Count_2));
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FDI_Training : <ilkvar> FDI_Training_Type :=
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(if CPU_Ironlake then Simple_Training
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elsif CPU_Sandybridge then Full_Training
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else Auto_Training);
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----------------------------------------------------------------------------
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Default_DDI_HDMI_Buffer_Translation : <hswvar> DDI_HDMI_Buf_Trans_Range :=
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(if CPU_Haswell then 6
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elsif CPU_Broadwell then 7
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elsif Broxton_On then 8
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else 0);
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----------------------------------------------------------------------------
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Default_CDClk_Freq : <ilkvar> Frequency_Type :=
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(if Gen_G45 then 320_000_000 -- unused
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elsif CPU_Ironlake or Gen_Haswell then 450_000_000
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elsif CPU_Sandybridge or CPU_Ivybridge then 400_000_000
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elsif Gen_Broxton then 288_000_000
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elsif Gen_Skylake then 337_500_000
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else Frequency_Type'First);
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Default_RawClk_Freq : <hswvar> Frequency_Type :=
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(if Gen_G45 then 100_000_000 -- unused, depends on FSB
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elsif Gen_Ironlake then 125_000_000
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elsif Gen_Haswell then (if Is_ULT then 24_000_000 else 125_000_000)
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elsif Gen_Broxton then Frequency_Type'First -- none needed
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elsif Gen_Skylake then 24_000_000
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else Frequency_Type'First);
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----------------------------------------------------------------------------
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-- Maximum source width with enabled scaler. This only accounts
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-- for simple 1:1 pipe:scaler mappings.
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type Width_Per_Pipe is array (Pipe_Index) of Width_Type;
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Maximum_Scalable_Width : <hswvar> Width_Per_Pipe :=
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(if Gen_G45 then -- TODO: Is this true?
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(Primary => 4096,
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Secondary => 2048,
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Tertiary => Pos32'First)
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elsif Gen_Ironlake or CPU_Haswell then
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(Primary => 4096,
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Secondary => 2048,
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Tertiary => 2048)
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else
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(Primary => 4096,
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Secondary => 4096,
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Tertiary => 4096));
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-- Maximum X position of hardware cursors
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Maximum_Cursor_X : constant :=
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(case Gen is
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when G45 .. Ironlake => 4095,
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when Haswell .. Skylake => 8191);
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Maximum_Cursor_Y : constant := 4095;
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----------------------------------------------------------------------------
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-- FIXME: Unknown for Broxton, Linux' i915 contains a fixme too :-D
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HDMI_Max_Clock_24bpp : constant Frequency_Type :=
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(if Haswell_On then 300_000_000 else 225_000_000);
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----------------------------------------------------------------------------
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GTT_PTE_Size : <hswvar> Natural := (if Has_64bit_GTT then 8 else 4);
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Fence_Base : <ilkvar> Natural :=
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(if not Sandybridge_On then 16#0000_3000# else 16#0010_0000#);
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Fence_Count : <ilkvar> Natural :=
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(if not Ivybridge_On then 16 else 32);
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----------------------------------------------------------------------------
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use type HW.Word16;
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function Is_Broadwell_H (Device_Id : Word16) return Boolean is
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(Device_Id = 16#1612# or Device_Id = 16#1622# or Device_Id = 16#162a#);
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function Is_Skylake_U (Device_Id : Word16) return Boolean is
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(Device_Id = 16#1906# or Device_Id = 16#1916# or Device_Id = 16#1923# or
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Device_Id = 16#1926# or Device_Id = 16#1927#);
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-- Rather catch too much here than too little,
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-- it's only used to distinguish generations.
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function Is_GPU (Device_Id : Word16; CPU : CPU_Type; CPU_Var : CPU_Variant)
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return Boolean is
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(case CPU is
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when G45 => (Device_Id and 16#ff02#) = 16#2e02# or
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(Device_Id and 16#fffe#) = 16#2a42#,
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when Ironlake => (Device_Id and 16#fff3#) = 16#0042#,
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when Sandybridge => (Device_Id and 16#ffc2#) = 16#0102#,
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when Ivybridge => (Device_Id and 16#ffc3#) = 16#0142#,
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when Haswell =>
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(case CPU_Var is
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when Normal => (Device_Id and 16#ffc3#) = 16#0402# or
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(Device_Id and 16#ffc3#) = 16#0d02#,
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when ULT => (Device_Id and 16#ffc3#) = 16#0a02#),
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when Broadwell => ((Device_Id and 16#ffc3#) = 16#1602# or
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(Device_Id and 16#ffcf#) = 16#160b# or
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(Device_Id and 16#ffcf#) = 16#160d#) and
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(case CPU_Var is
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when Normal => Is_Broadwell_H (Device_Id),
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when ULT => not Is_Broadwell_H (Device_Id)),
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when Broxton => (Device_Id and 16#fffe#) = 16#5a84#,
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when Skylake => ((Device_Id and 16#ffc3#) = 16#1902# or
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(Device_Id and 16#ffcf#) = 16#190b# or
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(Device_Id and 16#ffcf#) = 16#190d# or
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(Device_Id and 16#fff9#) = 16#1921#) and
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(case CPU_Var is
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when Normal => not Is_Skylake_U (Device_Id),
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when ULT => Is_Skylake_U (Device_Id)));
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function Compatible_GPU (Device_Id : Word16) return Boolean is
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(Is_GPU (Device_Id, CPU, CPU_Var));
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pragma Warnings (GNATprove, Off, "subprogram ""Detect_CPU"" has no effect",
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Reason => "only effective in dynamic cpu config");
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procedure Detect_CPU (Device : Word16)<cpunull>;
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end HW.GFX.GMA.Config;
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