gma: Begin Alder Lake (ADL) integration

Alder Lake uses the same generation of igfx engine as Tiger Lake,
therefore the changes required to support ADL-P are minor. This patch
starts with PCI device detection.

Change-Id: Ia9ab283b388735c4dd01c710251057c12b90b18e
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/libgfxinit/+/70888
Tested-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Tim Wawrzynczak 2022-09-09 12:26:32 -06:00 committed by Nico Huber
parent 605660bb21
commit e9631d8360
3 changed files with 57 additions and 6 deletions

View File

@ -31,7 +31,7 @@ private package HW.GFX.GMA.Config is
when Haswell => Broadwell,
when Broxton => Broxton,
when Skylake => Kabylake,
when Tigerlake => Tigerlake);
when Tigerlake => Alderlake);
CPU_Var_Last : constant CPU_Variant :=
(case Gen is
when Haswell | Skylake | Tigerlake => ULX,
@ -58,7 +58,7 @@ private package HW.GFX.GMA.Config is
when Haswell => Lynx_Point,
when Broxton => No_PCH,
when Skylake => Cannon_Point,
when Tigerlake => Tiger_Point);
when Tigerlake => Alder_Point);
subtype Gen_PCH_Type is PCH_Type range PCH_First .. PCH_Last;
PCH : constant Gen_PCH_Type := <<PCH>>;
@ -159,7 +159,8 @@ private package HW.GFX.GMA.Config is
CPU_Broadwell : <hswbool> := Gen_Haswell and then CPU = Broadwell;
CPU_Skylake : <sklbool> := Gen_Skylake and then CPU = Skylake;
CPU_Kabylake : <sklbool> := Gen_Skylake and then CPU = Kabylake;
CPU_Tigerlake : <tglbool> := Gen_Tigerlake;
CPU_Tigerlake : <tglbool> := Gen_Tigerlake and then CPU = Tigerlake;
CPU_Alderlake : <tglbool> := Gen_Tigerlake and then CPU = Alderlake;
Sandybridge_On : <ilkbool> :=
((Gen_Ironlake and then CPU >= Sandybridge) or Haswell_On);
@ -167,6 +168,8 @@ private package HW.GFX.GMA.Config is
((Gen_Ironlake and then CPU >= Ivybridge) or Haswell_On);
Broadwell_On : <hswbool> :=
((Gen_Haswell and then CPU >= Broadwell) or Broxton_On);
Alderlake_On : <tglbool> :=
(Gen_Tigerlake and then CPU >= Alderlake);
PCH_Cougar_Point : <genbool> := Gen_Ironlake and then PCH = Cougar_Point;
@ -502,6 +505,41 @@ private package HW.GFX.GMA.Config is
Device_Id = 16#9a68# or
Device_Id = 16#9a70#);
function Is_Alder_Lake_P (Device_ID : Word16) return Boolean is
(Device_Id = 16#46a0# or
Device_Id = 16#46a1# or
Device_Id = 16#46a2# or
Device_Id = 16#46a3# or
Device_Id = 16#46a6# or
Device_Id = 16#46a8# or
Device_Id = 16#46aa# or
Device_Id = 16#462a# or
Device_Id = 16#4626# or
Device_Id = 16#4628# or
Device_Id = 16#46b0# or
Device_Id = 16#46b1# or
Device_Id = 16#46b2# or
Device_Id = 16#46b3# or
Device_Id = 16#46c0# or
Device_Id = 16#46c1# or
Device_Id = 16#46c2# or
Device_Id = 16#46c3#);
function Is_Alder_Lake_N (Device_ID : Word16) return Boolean is
(Device_Id = 16#46d0# or
Device_Id = 16#46d1# or
Device_Id = 16#46d2#);
function Is_Raptor_Lake_P (Device_ID : Word16) return Boolean is
(Device_Id = 16#a720# or
Device_Id = 16#a721# or
Device_Id = 16#a7a0# or
Device_Id = 16#a7a1# or
Device_Id = 16#a7a8# or
Device_Id = 16#a7a9#);
function Is_Alder_Lake (Device_Id : Word16) return Boolean is
(Is_Alder_Lake_P (Device_Id) or
Is_Alder_Lake_N (Device_Id) or
Is_Raptor_Lake_P (Device_Id));
function Is_GPU (Device_Id : Word16; CPU : CPU_Type; CPU_Var : CPU_Variant)
return Boolean is
(case CPU is
@ -540,7 +578,12 @@ private package HW.GFX.GMA.Config is
when Normal =>
Is_Tiger_Lake_H (Device_Id),
when ULT | ULX =>
Is_Tiger_Lake_U (Device_Id)));
Is_Tiger_Lake_U (Device_Id)),
when Alderlake => (case CPU_Var is
when Normal =>
False,
when ULT | ULX =>
Is_Alder_Lake (Device_ID)));
function Compatible_GPU (Device_Id : Word16) return Boolean is
(Is_GPU (Device_Id, CPU, CPU_Var));

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@ -48,7 +48,8 @@ is
Broxton,
Skylake,
Kabylake,
Tigerlake);
Tigerlake,
Alderlake);
type CPU_Variant is (Normal, ULT, ULX);
@ -59,7 +60,8 @@ is
Lynx_Point, -- Wildcat Point compatible
Sunrise_Point, -- Union Point compatible
Cannon_Point,
Tiger_Point);
Tiger_Point,
Alder_Point);
type Port_Type is
(Disabled,

6
configs/alderlake Normal file
View File

@ -0,0 +1,6 @@
CONFIG_GFX_GMA_DYN_CPU = y
CONFIG_GFX_GMA_GENERATION = Tigerlake
CONFIG_GFX_GMA_PCH = Alder_Point
CONFIG_GFX_GMA_PANEL_1_PORT = eDP
CONFIG_GFX_GMA_ANALOG_I2C_PORT = PCH_DAC # N/A
CONFIG_GFX_GMA_DEFAULT_MMIO = 16\#e000_0000\#