gma: Update transcoder setup for TGL
Tiger Lake requires configuration (but not enablement) of the transcoder during the modeset sequence itself, so this patch adds a new Config option to accommodate that and refactors the transcoder setup into two new procedures. There should be no functional differences for other generations. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Change-Id: I4d7e2a24c54fcd9994f44bb0b10924dce48068e5 Reviewed-on: https://review.coreboot.org/c/libgfxinit/+/67493 Tested-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Tim Wawrzynczak
Nico Huber
parent
87469f2ec0
commit
4be2e75658
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@ -196,7 +196,7 @@ private package HW.GFX.GMA.Config is
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Has_Tertiary_Pipe : <ilkbool> := Ivybridge_On;
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Disable_Trickle_Feed : <genbool> := not Gen_Haswell;
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Pipe_Enabled_Workaround : <hswbool> := CPU_Broadwell;
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Has_EDP_Transcoder : <genbool> := Haswell_On;
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Has_EDP_Transcoder : <genbool> := Haswell_On and not Tigerlake_On;
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Use_PDW_For_EDP_Scaling : <hswbool> := CPU_Haswell;
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Has_Pipe_DDI_Func : <genbool> := Haswell_On;
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Has_Trans_Clk_Sel : <genbool> := Haswell_On;
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@ -212,6 +212,9 @@ private package HW.GFX.GMA.Config is
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Has_GMCH_VGACNTRL : <genbool> := Gen_G45;
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Has_GMCH_PFIT_CONTROL : <genbool> := Gen_G45;
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----------- Transcoder -------
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Need_Early_Transcoder_Setup : <genbool> := Tigerlake_On;
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--------- Panel power: -------
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Has_PP_Write_Protection : <genbool> := Up_To_Ironlake;
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Has_PP_Port_Select : <genbool> := Up_To_Ironlake;
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@ -263,6 +266,8 @@ private package HW.GFX.GMA.Config is
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-- might be disabled by x4 eDP:
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Has_DDI_E : <hswsklbool> := Has_DDI_D;
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Has_TGL_DDI_Select : <genbool> := Tigerlake_On;
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Has_DDI_Buffer_Trans : <genbool> := Haswell_On and not Has_DDI_PHYs;
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Has_Low_Voltage_Swing : <genbool> := Broxton_On;
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Has_Iboost_Config : <genbool> := Skylake_On;
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@ -15,6 +15,7 @@
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with HW.Debug;
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with GNAT.Source_Info;
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with HW.GFX.GMA.Config_Helpers;
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with HW.GFX.GMA.DP_Info;
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package body HW.GFX.GMA.Transcoder is
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@ -38,6 +39,7 @@ package body HW.GFX.GMA.Transcoder is
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----------------------------------------------------------------------------
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TRANS_CLK_SEL_PORT_NONE : constant := 0 * 2 ** 29;
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TRANS_CLK_SEL_MASK : constant := 16#f000_0000#;
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type TRANS_CLK_SEL_PORT_Array is
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array (Digital_Port) of Word32;
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@ -48,6 +50,19 @@ package body HW.GFX.GMA.Transcoder is
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DIGI_D => 4 * 2 ** 29,
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DIGI_E => 5 * 2 ** 29);
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function TGL_TRANS_CLK_SEL_PORT (Port : TGL_Digital_Port) return Word32 is
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(case Port is
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when DIGI_A => 1 * 2 ** 28,
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when DIGI_B => 2 * 2 ** 28,
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when DIGI_C => 3 * 2 ** 28,
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when DDI_TC1 => 4 * 2 ** 28,
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when DDI_TC2 => 5 * 2 ** 28,
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when DDI_TC3 => 6 * 2 ** 28,
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when DDI_TC4 => 7 * 2 ** 28,
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when DDI_TC5 => 8 * 2 ** 28,
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when DDI_TC6 => 9 * 2 ** 28,
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when others => 0);
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TRANS_CONF_ENABLE : constant := 1 * 2 ** 31;
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TRANS_CONF_ENABLED_STATUS : constant := 1 * 2 ** 30;
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TRANS_CONF_ENABLE_DITHER : constant := 1 * 2 ** 4;
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@ -85,6 +100,21 @@ package body HW.GFX.GMA.Transcoder is
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DIGI_D => 3 * 2 ** 28,
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DIGI_E => 4 * 2 ** 28);
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function TGL_DDI_FUNC_CTL_DDI_SELECT (Port : TGL_Digital_Port)
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return Word32
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is
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(case Port is
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when DIGI_A => 1 * 2 ** 27,
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when DIGI_B => 2 * 2 ** 27,
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when DIGI_C => 3 * 2 ** 27,
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when DDI_TC1 => 4 * 2 ** 27,
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when DDI_TC2 => 5 * 2 ** 27,
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when DDI_TC3 => 6 * 2 ** 27,
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when DDI_TC4 => 7 * 2 ** 27,
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when DDI_TC5 => 8 * 2 ** 27,
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when DDI_TC6 => 9 * 2 ** 27,
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when others => 0);
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type DDI_Mode_Array is array (Display_Type) of Word32;
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DDI_FUNC_CTL_MODE_SELECT : constant DDI_Mode_Array :=
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(VGA => DDI_FUNC_CTL_MODE_SELECT_FDI,
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@ -204,6 +234,7 @@ package body HW.GFX.GMA.Transcoder is
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pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
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if Config.Has_Trans_Clk_Sel and then
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not Config.Need_Early_Transcoder_Setup and then
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Trans.CLK_SEL /= Registers.Invalid_Register and then
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Port_Cfg.Port in Digital_Port
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then
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@ -228,6 +259,69 @@ package body HW.GFX.GMA.Transcoder is
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----------------------------------------------------------------------------
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procedure Enable_Pipe_Clock (Pipe : Pipe_Index; Port_Cfg : Port_Config)
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is
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use type HW.GFX.GMA.Registers.Registers_Invalid_Index;
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Trans : Transcoder_Regs renames
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Transcoders (Get_Idx (Pipe, Port_Cfg.Port));
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begin
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if Config.Need_Early_Transcoder_Setup and then
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Trans.CLK_SEL /= Registers.Invalid_Register and then
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Port_Cfg.Port in TGL_Digital_Port
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then
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Registers.Unset_And_Set_Mask
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(Register => Trans.CLK_SEL,
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Mask_Unset => TRANS_CLK_SEL_MASK,
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Mask_Set => TGL_TRANS_CLK_SEL_PORT (Port_Cfg.Port));
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end if;
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end Enable_Pipe_Clock;
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----------------------------------------------------------------------------
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procedure Configure (Pipe : Pipe_Index; Port_Cfg : Port_Config; Scale : Boolean)
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is
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Trans : Transcoder_Regs renames
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Transcoders (Get_Idx (Pipe, Port_Cfg.Port));
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Lane_Count : constant DP_Lane_Count :=
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(if Port_Cfg.Is_FDI then Port_Cfg.FDI.Lane_Count else Port_Cfg.DP.Lane_Count);
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EDP_Select : constant Word32 :=
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(if Config.Has_TGL_DDI_Select
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then 0
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else
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(if Pipe = Primary and
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(not Config.Use_PDW_For_EDP_Scaling or else not Scale)
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then
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DDI_FUNC_CTL_EDP_SELECT_ALWAYS_ON
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else
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DDI_FUNC_CTL_EDP_SELECT (Pipe)));
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DDI_Select : constant Word32 :=
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(if Config.Has_TGL_DDI_Select and Port_Cfg.Port in TGL_Digital_Port then
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TGL_DDI_FUNC_CTL_DDI_SELECT (Port_Cfg.Port)
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else
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(if Port_Cfg.Port in Digital_Port
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then
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DDI_FUNC_CTL_DDI_SELECT (Port_Cfg.Port)
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else 0));
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begin
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pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
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if Config.Has_Pipe_DDI_Func then
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if Is_Digital_Port (Port_Cfg.Port) then
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Registers.Write
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(Register => Trans.DDI_FUNC_CTL,
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Value => DDI_Select or
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DDI_FUNC_CTL_MODE_SELECT (Port_Cfg.Display) or
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DDI_FUNC_CTL_BPC (Port_Cfg.Mode.BPC) or
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DDI_FUNC_CTL_VSYNC (Port_Cfg.Mode.V_Sync_Active_High) or
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DDI_FUNC_CTL_HSYNC (Port_Cfg.Mode.H_Sync_Active_High) or
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EDP_Select or
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DDI_FUNC_CTL_PORT_WIDTH (Lane_Count));
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end if;
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end if;
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end Configure;
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----------------------------------------------------------------------------
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procedure On
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(Pipe : Pipe_Index;
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Port_Cfg : Port_Config;
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@ -236,27 +330,16 @@ package body HW.GFX.GMA.Transcoder is
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is
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Trans : Transcoder_Regs renames
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Transcoders (Get_Idx (Pipe, Port_Cfg.Port));
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Lane_Count : constant DP_Lane_Count :=
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(if Port_Cfg.Is_FDI then Port_Cfg.FDI.Lane_Count else Port_Cfg.DP.Lane_Count);
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EDP_Select : constant Word32 :=
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(if Pipe = Primary and
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(not Config.Use_PDW_For_EDP_Scaling or else not Scale)
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then
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DDI_FUNC_CTL_EDP_SELECT_ALWAYS_ON
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else
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DDI_FUNC_CTL_EDP_SELECT (Pipe));
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begin
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if Config.Has_Pipe_DDI_Func and Port_Cfg.Port in Digital_Port then
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Registers.Write
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pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
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if not Config.Need_Early_Transcoder_Setup then
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Configure (Pipe, Port_Cfg, Scale);
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end if;
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if Config.Has_Pipe_DDI_Func and Is_Digital_Port (Port_Cfg.Port) then
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Registers.Set_Mask
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(Register => Trans.DDI_FUNC_CTL,
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Value => DDI_FUNC_CTL_ENABLE or
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DDI_FUNC_CTL_DDI_SELECT (Port_Cfg.Port) or
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DDI_FUNC_CTL_MODE_SELECT (Port_Cfg.Display) or
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DDI_FUNC_CTL_BPC (Port_Cfg.Mode.BPC) or
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DDI_FUNC_CTL_VSYNC (Port_Cfg.Mode.V_Sync_Active_High) or
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DDI_FUNC_CTL_HSYNC (Port_Cfg.Mode.H_Sync_Active_High) or
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EDP_Select or
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DDI_FUNC_CTL_PORT_WIDTH (Lane_Count));
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Mask => DDI_FUNC_CTL_ENABLE);
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end if;
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Registers.Write
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@ -360,15 +443,20 @@ package body HW.GFX.GMA.Transcoder is
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pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
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if Config.Has_Per_Pipe_SRD then
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for P in Transcoder_Index loop
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Registers.Is_Set_Mask (SRD (P).CTL, SRD_CTL_ENABLE, Enabled);
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if Enabled then
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Registers.Unset_Mask (SRD (P).CTL, SRD_CTL_ENABLE);
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Registers.Wait_Unset_Mask (SRD (P).STATUS, SRD_STATUS_STATE_MASK);
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declare
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First_Transcoder : constant Transcoder_Index :=
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(if Config.Has_EDP_Transcoder then Trans_EDP else Trans_A);
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begin
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for P in Transcoder_Index range First_Transcoder .. Transcoder_Index'Last loop
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Registers.Is_Set_Mask (SRD (P).CTL, SRD_CTL_ENABLE, Enabled);
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if Enabled then
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Registers.Unset_Mask (SRD (P).CTL, SRD_CTL_ENABLE);
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Registers.Wait_Unset_Mask (SRD (P).STATUS, SRD_STATUS_STATE_MASK);
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pragma Debug (Debug.Put_Line ("Disabled PSR."));
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end if;
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end loop;
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pragma Debug (Debug.Put_Line ("Disabled PSR."));
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end if;
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end loop;
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end;
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else
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Registers.Is_Set_Mask (Registers.SRD_CTL, SRD_CTL_ENABLE, Enabled);
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if Enabled then
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@ -18,6 +18,8 @@ with HW.GFX.GMA.Config;
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private package HW.GFX.GMA.Transcoder
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is
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procedure Enable_Pipe_Clock (Pipe : Pipe_Index; Port_Cfg : Port_Config);
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procedure Configure (Pipe : Pipe_Index; Port_Cfg : Port_Config; Scale : Boolean);
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procedure Setup (Pipe : Pipe_Index; Port_Cfg : Port_Config);
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procedure On
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(Pipe : Pipe_Index;
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@ -52,6 +54,7 @@ private
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DDI_FUNC_CTL : Registers.Registers_Index;
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MSA_MISC : Registers.Registers_Index;
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CLK_SEL : Registers.Registers_Invalid_Index;
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PIPE_ARB_CTL : Registers.Registers_Invalid_Index;
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end record;
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type Transcoder_Array is array (Transcoder_Index) of Transcoder_Regs;
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@ -100,7 +103,8 @@ private
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LINK_N1 => Registers.PIPE_EDP_LINK_N1,
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DDI_FUNC_CTL => Registers.PIPE_EDP_DDI_FUNC_CTL,
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MSA_MISC => Registers.PIPE_EDP_MSA_MISC,
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CLK_SEL => Registers.Invalid_Register),
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CLK_SEL => Registers.Invalid_Register,
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PIPE_ARB_CTL => Registers.Invalid_Register),
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Trans_A =>
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(HTOTAL => Registers.HTOTAL_A,
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HBLANK => Registers.HBLANK_A,
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@ -115,7 +119,8 @@ private
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LINK_N1 => PIPE_LINK_N1 (0),
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DDI_FUNC_CTL => Registers.PIPEA_DDI_FUNC_CTL,
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MSA_MISC => Registers.PIPEA_MSA_MISC,
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CLK_SEL => Registers.TRANSA_CLK_SEL),
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CLK_SEL => Registers.TRANSA_CLK_SEL,
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PIPE_ARB_CTL => Registers.PIPEA_ARB_CTL),
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Trans_B =>
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(HTOTAL => Registers.HTOTAL_B,
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HBLANK => Registers.HBLANK_B,
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@ -130,7 +135,8 @@ private
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LINK_N1 => PIPE_LINK_N1 (1),
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DDI_FUNC_CTL => Registers.PIPEB_DDI_FUNC_CTL,
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MSA_MISC => Registers.PIPEB_MSA_MISC,
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CLK_SEL => Registers.TRANSB_CLK_SEL),
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CLK_SEL => Registers.TRANSB_CLK_SEL,
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PIPE_ARB_CTL => Registers.PIPEB_ARB_CTL),
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Trans_C =>
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(HTOTAL => Registers.HTOTAL_C,
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HBLANK => Registers.HBLANK_C,
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@ -145,6 +151,7 @@ private
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LINK_N1 => Registers.PIPEC_LINK_N1,
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DDI_FUNC_CTL => Registers.PIPEC_DDI_FUNC_CTL,
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MSA_MISC => Registers.PIPEC_MSA_MISC,
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CLK_SEL => Registers.TRANSC_CLK_SEL));
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CLK_SEL => Registers.TRANSC_CLK_SEL,
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PIPE_ARB_CTL => Registers.PIPEC_ARB_CTL));
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end HW.GFX.GMA.Transcoder;
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