421 lines
12 KiB
C
421 lines
12 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2005 Yinghai Lu <yinghailu@gmail.com>
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* Copyright (C) 2009 coresystems GmbH
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* Copyright (C) 2013 Vladimir Serbinenko
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include <console/console.h>
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#include <device/smbus_def.h>
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#include <stdlib.h>
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#include "smbus.h"
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#if IS_ENABLED(CONFIG_DEBUG_SMBUS)
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#define dprintk(args...) printk(BIOS_DEBUG, ##args)
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#else
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#define dprintk(args...) do {} while (0)
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#endif
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/* I801 command constants */
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#define I801_QUICK (0 << 2)
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#define I801_BYTE (1 << 2)
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#define I801_BYTE_DATA (2 << 2)
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#define I801_WORD_DATA (3 << 2)
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#define I801_BLOCK_DATA (5 << 2)
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#define I801_I2C_BLOCK_DATA (6 << 2) /* ICH5 and later */
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/* I801 Host Control register bits */
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#define SMBHSTCNT_INTREN (1 << 0)
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#define SMBHSTCNT_KILL (1 << 1)
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#define SMBHSTCNT_LAST_BYTE (1 << 5)
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#define SMBHSTCNT_START (1 << 6)
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#define SMBHSTCNT_PEC_EN (1 << 7) /* ICH3 and later */
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/* I801 Hosts Status register bits */
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#define SMBHSTSTS_BYTE_DONE (1 << 7)
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#define SMBHSTSTS_INUSE_STS (1 << 6)
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#define SMBHSTSTS_SMBALERT_STS (1 << 5)
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#define SMBHSTSTS_FAILED (1 << 4)
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#define SMBHSTSTS_BUS_ERR (1 << 3)
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#define SMBHSTSTS_DEV_ERR (1 << 2)
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#define SMBHSTSTS_INTR (1 << 1)
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#define SMBHSTSTS_HOST_BUSY (1 << 0)
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#define SMBUS_TIMEOUT (10 * 1000 * 100)
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#define SMBUS_BLOCK_MAXLEN 32
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static void smbus_delay(void)
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{
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inb(0x80);
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}
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static int smbus_wait_until_ready(u16 smbus_base)
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{
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unsigned int loops = SMBUS_TIMEOUT;
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unsigned char byte;
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do {
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smbus_delay();
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if (--loops == 0)
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break;
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byte = inb(smbus_base + SMBHSTSTAT);
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} while (byte & SMBHSTSTS_HOST_BUSY);
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return loops ? 0 : -1;
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}
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static int smbus_wait_until_done(u16 smbus_base)
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{
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unsigned int loops = SMBUS_TIMEOUT;
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unsigned char byte;
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do {
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smbus_delay();
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if (--loops == 0)
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break;
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byte = inb(smbus_base + SMBHSTSTAT);
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} while ((byte & SMBHSTSTS_HOST_BUSY)
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|| (byte & ~(SMBHSTSTS_INUSE_STS | SMBHSTSTS_HOST_BUSY)) == 0);
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return loops ? 0 : -1;
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}
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static int smbus_wait_until_active(u16 smbus_base)
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{
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unsigned long loops;
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loops = SMBUS_TIMEOUT;
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do {
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unsigned char val;
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smbus_delay();
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val = inb(smbus_base + SMBHSTSTAT);
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if ((val & SMBHSTSTS_HOST_BUSY)) {
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break;
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}
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} while (--loops);
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return loops ? 0 : -1;
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}
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int do_smbus_read_byte(unsigned int smbus_base, u8 device,
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unsigned int address)
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{
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unsigned char status;
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unsigned char byte;
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if (smbus_wait_until_ready(smbus_base) < 0)
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return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
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/* Set up transaction */
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/* Disable interrupts */
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outb(inb(smbus_base + SMBHSTCTL) & ~SMBHSTCNT_INTREN,
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smbus_base + SMBHSTCTL);
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/* Set the device I'm talking to */
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outb(((device & 0x7f) << 1) | 1, smbus_base + SMBXMITADD);
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/* Set the command/address... */
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outb(address & 0xff, smbus_base + SMBHSTCMD);
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/* Set up for a byte data read */
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outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | I801_BYTE_DATA,
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(smbus_base + SMBHSTCTL));
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/* Clear any lingering errors, so the transaction will run */
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outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT);
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/* Clear the data byte... */
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outb(0, smbus_base + SMBHSTDAT0);
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/* Start the command */
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outb((inb(smbus_base + SMBHSTCTL) | SMBHSTCNT_START),
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smbus_base + SMBHSTCTL);
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/* poll for it to start */
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if (smbus_wait_until_active(smbus_base) < 0)
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return SMBUS_WAIT_UNTIL_ACTIVE_TIMEOUT;
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/* Poll for transaction completion */
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if (smbus_wait_until_done(smbus_base) < 0)
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return SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
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status = inb(smbus_base + SMBHSTSTAT);
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/* Ignore the "In Use" status... */
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status &= ~(SMBHSTSTS_SMBALERT_STS | SMBHSTSTS_INUSE_STS);
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/* Read results of transaction */
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byte = inb(smbus_base + SMBHSTDAT0);
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if (status != SMBHSTSTS_INTR)
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return SMBUS_ERROR;
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return byte;
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}
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int do_smbus_write_byte(unsigned int smbus_base, u8 device,
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unsigned int address, unsigned int data)
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{
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unsigned char status;
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if (smbus_wait_until_ready(smbus_base) < 0)
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return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
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/* Set up transaction */
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/* Disable interrupts */
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outb(inb(smbus_base + SMBHSTCTL) & ~SMBHSTCNT_INTREN,
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smbus_base + SMBHSTCTL);
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/* Set the device I'm talking to */
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outb(((device & 0x7f) << 1) & ~0x01, smbus_base + SMBXMITADD);
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/* Set the command/address... */
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outb(address & 0xff, smbus_base + SMBHSTCMD);
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/* Set up for a byte data read */
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outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | I801_BYTE_DATA,
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(smbus_base + SMBHSTCTL));
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/* Clear any lingering errors, so the transaction will run */
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outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT);
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/* Clear the data byte... */
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outb(data, smbus_base + SMBHSTDAT0);
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/* Start the command */
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outb((inb(smbus_base + SMBHSTCTL) | SMBHSTCNT_START),
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smbus_base + SMBHSTCTL);
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/* poll for it to start */
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if (smbus_wait_until_active(smbus_base) < 0)
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return SMBUS_WAIT_UNTIL_ACTIVE_TIMEOUT;
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/* Poll for transaction completion */
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if (smbus_wait_until_done(smbus_base) < 0)
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return SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
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status = inb(smbus_base + SMBHSTSTAT);
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/* Ignore the "In Use" status... */
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status &= ~(SMBHSTSTS_SMBALERT_STS | SMBHSTSTS_INUSE_STS);
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/* Read results of transaction */
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if (status != SMBHSTSTS_INTR)
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return SMBUS_ERROR;
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return 0;
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}
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int do_smbus_block_read(unsigned int smbus_base, u8 device, u8 cmd,
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unsigned int max_bytes, u8 *buf)
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{
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u8 status;
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int slave_bytes;
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int bytes_read = 0;
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unsigned int loops = SMBUS_TIMEOUT;
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if (smbus_wait_until_ready(smbus_base) < 0)
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return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
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max_bytes = MIN(SMBUS_BLOCK_MAXLEN, max_bytes);
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/* Set up transaction */
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/* Disable interrupts */
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outb(inb(smbus_base + SMBHSTCTL) & ~SMBHSTCNT_INTREN,
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smbus_base + SMBHSTCTL);
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/* Set the device I'm talking to */
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outb(((device & 0x7f) << 1) | 1, smbus_base + SMBXMITADD);
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/* Set the command/address... */
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outb(cmd & 0xff, smbus_base + SMBHSTCMD);
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/* Set up for a block data read */
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outb((inb(smbus_base + SMBHSTCTL) & 0xc3) | I801_BLOCK_DATA,
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(smbus_base + SMBHSTCTL));
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/* Clear any lingering errors, so the transaction will run */
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outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT);
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/* Reset number of bytes to transfer so we notice later it
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* was really updated with the transaction. */
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outb(0, smbus_base + SMBHSTDAT0);
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/* Start the command */
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outb((inb(smbus_base + SMBHSTCTL) | SMBHSTCNT_START),
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smbus_base + SMBHSTCTL);
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/* poll for it to start */
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if (smbus_wait_until_active(smbus_base) < 0)
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return SMBUS_WAIT_UNTIL_ACTIVE_TIMEOUT;
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/* Poll for transaction completion */
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do {
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loops--;
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status = inb(smbus_base + SMBHSTSTAT);
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if (status & (SMBHSTSTS_FAILED | /* FAILED */
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SMBHSTSTS_BUS_ERR | /* BUS ERR */
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SMBHSTSTS_DEV_ERR)) /* DEV ERR */
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return SMBUS_ERROR;
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if (status & SMBHSTSTS_BYTE_DONE) { /* Byte done */
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if (bytes_read < max_bytes) {
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*buf++ = inb(smbus_base + SMBBLKDAT);
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bytes_read++;
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}
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/* Engine internally completes the transaction
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* and clears HOST_BUSY flag once the byte count
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* from slave is reached.
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*/
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outb(status, smbus_base + SMBHSTSTAT);
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}
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} while ((status & SMBHSTSTS_HOST_BUSY) && loops);
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/* Post-check we received complete message. */
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slave_bytes = inb(smbus_base + SMBHSTDAT0);
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dprintk("%s: status = %02x, len = %d / %d, loops = %d\n",
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__func__, status, bytes_read, slave_bytes, loops);
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if (bytes_read < slave_bytes)
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return SMBUS_ERROR;
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return bytes_read;
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}
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int do_smbus_block_write(unsigned int smbus_base, u8 device, u8 cmd,
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const unsigned int bytes, const u8 *buf)
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{
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u8 status;
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int bytes_sent = 0;
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unsigned int loops = SMBUS_TIMEOUT;
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if (bytes > SMBUS_BLOCK_MAXLEN)
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return SMBUS_ERROR;
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if (smbus_wait_until_ready(smbus_base) < 0)
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return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
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/* Set up transaction */
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/* Disable interrupts */
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outb(inb(smbus_base + SMBHSTCTL) & ~SMBHSTCNT_INTREN,
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smbus_base + SMBHSTCTL);
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/* Set the device I'm talking to */
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outb(((device & 0x7f) << 1) & ~0x01, smbus_base + SMBXMITADD);
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/* Set the command/address... */
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outb(cmd & 0xff, smbus_base + SMBHSTCMD);
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/* Set up for a block data write */
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outb((inb(smbus_base + SMBHSTCTL) & 0xc3) | I801_BLOCK_DATA,
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(smbus_base + SMBHSTCTL));
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/* Clear any lingering errors, so the transaction will run */
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outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT);
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/* set number of bytes to transfer */
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outb(bytes, smbus_base + SMBHSTDAT0);
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/* Send first byte from buffer, bytes_sent increments after
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* hardware acknowledges it.
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*/
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outb(*buf++, smbus_base + SMBBLKDAT);
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/* Start the command */
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outb((inb(smbus_base + SMBHSTCTL) | SMBHSTCNT_START),
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smbus_base + SMBHSTCTL);
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/* poll for it to start */
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if (smbus_wait_until_active(smbus_base) < 0)
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return SMBUS_WAIT_UNTIL_ACTIVE_TIMEOUT;
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/* Poll for transaction completion */
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do {
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loops--;
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status = inb(smbus_base + SMBHSTSTAT);
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if (status & (SMBHSTSTS_FAILED | /* FAILED */
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SMBHSTSTS_BUS_ERR | /* BUS ERR */
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SMBHSTSTS_DEV_ERR)) /* DEV ERR */
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return SMBUS_ERROR;
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if (status & SMBHSTSTS_BYTE_DONE) {
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bytes_sent++;
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if (bytes_sent < bytes)
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outb(*buf++, smbus_base + SMBBLKDAT);
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/* Engine internally completes the transaction
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* and clears HOST_BUSY flag once the byte count
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* has been reached.
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*/
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outb(status, smbus_base + SMBHSTSTAT);
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}
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} while ((status & SMBHSTSTS_HOST_BUSY) && loops);
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dprintk("%s: status = %02x, len = %d / %d, loops = %d\n",
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__func__, status, bytes_sent, bytes, loops);
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if (bytes_sent < bytes)
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return SMBUS_ERROR;
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return bytes_sent;
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}
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/* Only since ICH5 */
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int do_i2c_block_read(unsigned int smbus_base, u8 device,
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unsigned int offset, const unsigned int bytes, u8 *buf)
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{
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u8 status;
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int bytes_read = 0;
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unsigned int loops = SMBUS_TIMEOUT;
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if (smbus_wait_until_ready(smbus_base) < 0)
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return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
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/* Set upp transaction */
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/* Disable interrupts */
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outb(inb(smbus_base + SMBHSTCTL) & SMBHSTCNT_INTREN,
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smbus_base + SMBHSTCTL);
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/* Set the device I'm talking to */
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outb((device & 0x7f) << 1, smbus_base + SMBXMITADD);
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/* device offset */
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outb(offset, smbus_base + SMBHSTDAT1);
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/* Set up for a i2c block data read */
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outb((inb(smbus_base + SMBHSTCTL) & 0xc3) | I801_I2C_BLOCK_DATA,
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(smbus_base + SMBHSTCTL));
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/* Clear any lingering errors, so the transaction will run */
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outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT);
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/* Start the command */
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outb((inb(smbus_base + SMBHSTCTL) | SMBHSTCNT_START),
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smbus_base + SMBHSTCTL);
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/* poll for it to start */
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if (smbus_wait_until_active(smbus_base) < 0)
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return SMBUS_WAIT_UNTIL_ACTIVE_TIMEOUT;
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/* Poll for transaction completion */
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do {
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loops--;
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status = inb(smbus_base + SMBHSTSTAT);
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if (status & (SMBHSTSTS_FAILED | /* FAILED */
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SMBHSTSTS_BUS_ERR | /* BUS ERR */
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SMBHSTSTS_DEV_ERR)) /* DEV ERR */
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return SMBUS_ERROR;
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if (status & SMBHSTSTS_BYTE_DONE) {
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if (bytes_read < bytes) {
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*buf++ = inb(smbus_base + SMBBLKDAT);
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bytes_read++;
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}
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if (bytes_read + 1 >= bytes) {
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/* indicate that next byte is the last one */
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outb(inb(smbus_base + SMBHSTCTL)
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| SMBHSTCNT_LAST_BYTE,
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smbus_base + SMBHSTCTL);
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}
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outb(status, smbus_base + SMBHSTSTAT);
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}
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} while ((status & SMBHSTSTS_HOST_BUSY) && loops);
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dprintk("%s: status = %02x, len = %d / %d, loops = %d\n",
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__func__, status, bytes_read, bytes, loops);
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if (bytes_read < bytes)
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return SMBUS_ERROR;
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return bytes_read;
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}
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