138 lines
3.8 KiB
C
138 lines
3.8 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2017 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include <device/smbus_def.h>
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#include <timer.h>
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#include "smbuslib.h"
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static int smbus_wait_till_ready(u16 smbus_base)
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{
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struct stopwatch sw;
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unsigned char byte;
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stopwatch_init_msecs_expire(&sw, SMBUS_TIMEOUT);
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do {
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byte = inb(smbus_base + SMBHSTSTAT);
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if (!(byte & 1))
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return 0;
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} while (!stopwatch_expired(&sw));
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return -1;
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}
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static int smbus_wait_till_done(u16 smbus_base)
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{
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struct stopwatch sw;
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unsigned char byte;
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stopwatch_init_msecs_expire(&sw, SMBUS_TIMEOUT);
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do {
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byte = inb(smbus_base + SMBHSTSTAT);
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if (!((byte & 1) || (byte & ~((1 << 6) | (1 << 0))) == 0))
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return 0;
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} while (!stopwatch_expired(&sw));
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return -1;
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}
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int smbus_read8(unsigned int smbus_base, unsigned int device,
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unsigned int address)
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{
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unsigned char global_status_register;
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unsigned char byte;
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if (smbus_wait_till_ready(smbus_base) < 0)
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return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
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/* Setup transaction */
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/* Disable interrupts */
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outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL);
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/* Set the device I'm talking to */
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outb(((device & 0x7f) << 1) | 1, smbus_base + SMBXMITADD);
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/* Set the command/address... */
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outb(address & 0xff, smbus_base + SMBHSTCMD);
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/* Set up for a byte data read */
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outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | (0x2 << 2),
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(smbus_base + SMBHSTCTL));
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/* Clear any lingering errors, so the transaction will run */
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outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT);
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/* Clear the data byte... */
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outb(0, smbus_base + SMBHSTDAT0);
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/* Start the command */
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outb((inb(smbus_base + SMBHSTCTL) | 0x40),
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smbus_base + SMBHSTCTL);
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/* Poll for transaction completion */
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if (smbus_wait_till_done(smbus_base) < 0)
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return SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
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global_status_register = inb(smbus_base + SMBHSTSTAT);
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/* Ignore the "In Use" status... */
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global_status_register &= ~(3 << 5);
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/* Read results of transaction */
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byte = inb(smbus_base + SMBHSTDAT0);
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if (global_status_register != (1 << 1))
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return SMBUS_ERROR;
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return byte;
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}
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int smbus_write8(unsigned int smbus_base, unsigned int device,
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unsigned int address, unsigned int data)
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{
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unsigned char global_status_register;
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if (smbus_wait_till_ready(smbus_base) < 0)
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return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
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/* Setup transaction */
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/* Disable interrupts */
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outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL);
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/* Set the device I'm talking to */
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outb(((device & 0x7f) << 1) & ~0x01, smbus_base + SMBXMITADD);
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/* Set the command/address... */
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outb(address & 0xff, smbus_base + SMBHSTCMD);
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/* Set up for a byte data read */
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outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | (0x2 << 2),
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(smbus_base + SMBHSTCTL));
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/* Clear any lingering errors, so the transaction will run */
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outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT);
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/* Clear the data byte... */
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outb(data, smbus_base + SMBHSTDAT0);
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/* Start the command */
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outb((inb(smbus_base + SMBHSTCTL) | 0x40),
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smbus_base + SMBHSTCTL);
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/* Poll for transaction completion */
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if (smbus_wait_till_done(smbus_base) < 0)
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return SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
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global_status_register = inb(smbus_base + SMBHSTSTAT);
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/* Ignore the "In Use" status... */
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global_status_register &= ~(3 << 5);
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/* Read results of transaction */
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if (global_status_register != (1 << 1))
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return SMBUS_ERROR;
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return 0;
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}
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