Commit Graph

22708 Commits (microserver)

Author SHA1 Message Date
Alexander Couzens 92fd4ffd0c NOT-FOR-MERGE: ignore soft cycle request of ME
no we dont reboot because the ME want to

Change-Id: I01da133425c7f6c31031082975ebb2c297b10c9b
2018-03-02 23:50:13 +01:00
Alexander Couzens 8ba927d1d6 NOT-FOR-MERGE: disable update_mrc_cache
Change-Id: Id13ad448587264a868bae2d7dbf83c989ef6c12e
2018-03-02 15:07:41 +01:00
Alexander Couzens 7b5ee9a169 NOT-FOR-MERGE: disable any mem test on boot
to reduce the time before ram stage. There seems to be
a hidden watchdog or real watch. maybe TCO is retriggering the
smm while init or so.

Change-Id: I320675b10938c65a381229a26e896e2ded4a2991
2018-03-02 15:00:33 +01:00
Alexander Couzens f7662b18ec NOT-FOR-MERGE: ignore all configs
Change-Id: I21cdc80a69b1524d5c74cdb4b901b345818c2f07
2018-03-02 14:33:47 +01:00
Alexander Couzens 0641651e5b working until smm
Change-Id: Ia3d6fe1d250571420b0303ffc191a6699910e16a
2018-03-02 14:20:46 +01:00
Alexander Couzens 0b2ef73350 correct spd - one lines zero to much in the middle
Change-Id: If32b5fef0d65def20d86fcdab8f420d44f012281
2018-03-02 14:01:21 +01:00
Alexander Couzens 7d24dd580b .gitignore: ignore fuzz-tests/jpeg-test binary
Change-Id: I1ec1709a206abcb684d3019afa813dbdaf3d3b3b
2018-03-02 12:57:14 +01:00
Alexander Couzens 166db8d8e1 .gitignore: ignore blobtool flex/bison artefacts
Change-Id: I09cfc78719830ee6bc396a3a6abb7139052a0e06
2018-03-02 12:55:42 +01:00
Patrick Rudolph edc51a9af2 nb/intel/sandybridge/raminit: Add ECC support
Add ECC support for native raminit on SandyBridge/IvyBridge.

Change-Id: I1206746332c9939a78b67e7b48d3098bdef8a2ed
Signed-off-by: Patrick Rudolph <>
2018-03-02 03:30:37 +01:00
Patrick Rudolph 8bd589d1b5 nb/intel/sandybridge/raminit: Add ECC detection support
Add support for detection ECC capability and forced ECC mode.
Print the ECC mode in verbose debugging mode.

Change-Id: I5b7599746195cfa996a48320404a8dbe6820483a
Signed-off-by: Patrick Rudolph <>
2018-03-02 03:13:55 +01:00
Alexander Couzens d1a76e3920 serialice: add check cpuinfo
Change-Id: If52d9e923ebca6f49b6124a01dc4323e96b97114
2017-10-29 07:18:36 +01:00
Alexander Couzens 40983ccaec serial ice before raminit
Change-Id: I9575525764bcd661a90d04d958de556b902386d6
2017-10-29 05:25:17 +01:00
Alexander Couzens 9a517ea710 UART_FOR_CONSOLE: set it default to 2
Change-Id: Ia37b14ffc9db00203eb4eb24f61a5cfacda72ba3
2017-10-29 05:24:39 +01:00
Alexander Couzens 92b0e5d8fb hp/mainboard_spd: read spds instead of static spd
Change-Id: I2eae26ae4b9542bd5b7a4e01bed73d3d8ba6b04c
2017-10-29 05:23:58 +01:00
Alexander Couzens a53c6fc5fc serial ice: fix puthex + put spd
Change-Id: Iaabc124eb870e176cb17e832c4aa0848a779e363
2017-10-29 05:23:16 +01:00
Alexander Couzens 7215ed3997 serial ice: remove debug output
Change-Id: Idf4ac799197790484daa20bdd7bc104a684cb2a0
2017-10-29 02:45:47 +01:00
Alexander Couzens a4468ea249 serial ice working after rework
Change-Id: I05e70ba1dfe5223040417742a18621d18b7431e8
2017-10-29 02:39:29 +01:00
Alexander Couzens e17cb22b97 rework sserialice
Change-Id: I3d61bd21589d7d8f5e23b28d6c86ffd2a23fde98
2017-10-29 02:51:44 +02:00
Alexander Couzens f00051b64a add help
Change-Id: Ie784a33f006491425bc94f8d6fbdd82334a109dd
2017-10-29 01:10:59 +02:00
Alexander Couzens d2b9852606 LDN0 -> 0x21 = 0x1
Change-Id: I3c3c9cd5c2030d1b8d12a855a6409a38eec215ff
2017-10-29 01:01:51 +02:00
Alexander Couzens 45bec1ce0b remove echo from serial ice
Change-Id: I8fb95fe7b85b31e9914446ee810698dbec78dc1a
2017-10-28 13:52:14 +02:00
Alexander Couzens 97a9680238 make serialice running
Change-Id: Ia8305c47473390bdd5249afeec064da3d82a65bc
2017-10-28 02:33:25 +02:00
Patrick Rudolph ae0f552f57 console/serialice: Add SerialICE
Add Kconfig Option to build SerialICE shell into coreboot stages.
You can select between romstage and ramstage.
The SerialICE shell will be launched instead of coreboot console.
As minimal system initialization is already done in coreboot, it
should work on all boards.

Tested with EHCI Debug on Lenovo T520 and Lenovo X60.

Needs tests:
 * Ramstage

Change-Id: I1fa6eb4f40e0f625c8c8302d1580bcd2664d670b
Signed-off-by: Patrick Rudolph <>
Signed-off-by: Antonello Dettori <>
2017-10-28 00:19:10 +02:00
Alexander Couzens 7079ee113e fix ramtest foo
Change-Id: Ib14b4258f872bbf7a7d2e4563c54b2ff49e3ca46
2017-10-27 19:48:28 +02:00
Patrick Rudolph 78d34c2a38 nb/intel/sandybridge/raminit: Add extended memtest
Run an regular or extended memtest on native raminit to make sure the DRAM
is usable. As it's very intrusive, the test is only run on cold-boot, but
not on S3 resume.

Change-Id: I31bcf8348c97b9461ee0aa792b3e53c0225d7d48
Signed-off-by: Patrick Rudolph <>
2017-10-27 14:44:11 +02:00
Alexander Couzens 8882b10681 Revert "add non-ecc ram"
This reverts commit 293229c7a2.
2017-10-26 01:45:10 +02:00
Alexander Couzens 293229c7a2 add non-ecc ram
Change-Id: I1ed8882dc079343d447413f91dbbb436d8233436
2017-10-26 01:45:06 +02:00
Alexander Couzens 9a66544dc7 add debug messages. might should be reverted
Change-Id: Ibdb8b635b22e3ce7cc6c901e6f3cc604173307e9
2017-10-26 01:44:45 +02:00
Alexander Couzens 4b63de1125 Revert "testing Memory Channel 0 Slot 0"
This reverts commit 5c5eca8d00.

It seems to be Channel 0 Slot 1

Change-Id: I678a279f69e28328bd2cdbd7fde88ebdf6671936
2017-10-22 04:23:38 +02:00
Alexander Couzens 5c5eca8d00 testing Memory Channel 0 Slot 0
Change-Id: Ib0014ae623ec1f79b6c9db48ac3362c67c19c652
2017-10-22 03:55:54 +02:00
Alexander Couzens 041181e6a8 use spd dump read via a different board
Change-Id: I3c0df329e4b5c3857f7021c900407c973943ac17
2017-10-22 03:34:22 +02:00
Alexander Couzens 2c6959c6eb add config for hp microserver
Change-Id: Ic7075c09941033c4dc893fcc36b6b19b1ee14154
2017-10-22 01:03:25 +02:00
Alexander Couzens d5ea03ddb8 add static memory init
Change-Id: I8072282a3271d0459cecb7979cf01b331341f72e
2017-10-21 06:47:12 +02:00
Alexander Couzens db1d912133 remove port 0
Change-Id: Ieff8055a6d23602e689c10d34c0f0657830bacdf
2017-10-21 04:56:27 +02:00
Alexander Couzens 459408183a disable rcba func disable
Change-Id: I8ceb869939b81f00fb17fe5da2962ed366c7beb1
2017-10-21 04:56:27 +02:00
Alexander Couzens dcae9d57ff enable serial
Change-Id: I1956dc03b2129384a017fa52ac514965c91cb396
2017-10-21 04:56:27 +02:00
Felix Held a94c884b23 add prolian_microserver_gen8
Change-Id: I51ca03a3337f1e4075cdd58784a4a99af2a9468a
2017-10-21 04:56:27 +02:00
Alexander Couzens dbab83c150 for-felix: pilot2 config
Change-Id: If6762453f27714edb6b9d9a8acbcd955525f2688
2017-10-21 04:56:27 +02:00
Marc Jones b6ac3a2997 kahlee: Set Kahlee GPEs
Add GPE configuration table.

Remove GPE3 from the power button ASL and set the EC to GPE3(AGPIO22).

Set the EC and PCIE/WLAN SCI GPIO signals.

Set GPE ASL methods for:
  PCIE/WLAN      8h
  EHCI          18h
  XHCI          1fh
Note EC GPE3 methods are in the EC ASL.

TEST=Test lidswitch powers the device on and off at the login screen.

Change-Id: I27c880ee84b6797d999d4d5951602b654ede948e
Signed-off-by: Marc Jones <>
Reviewed-by: Aaron Durbin <>
Tested-by: build bot (Jenkins) <>
2017-10-20 22:57:43 +00:00
Shelley Chen 794d222886 cr50_enable_update: Add printk before EC hibernate
Add printout before EC hibernates during a cr50 update to clarify that
failure is due to EC rather than cr50.  Ran into a situation where DUT
shut down during cr50 update and the EC was the culprit.


Change-Id: I54813fec123de69604d1da4dfc65eaeb77d1662e
Signed-off-by: Shelley Chen <>
Reviewed-by: Aaron Durbin <>
Tested-by: build bot (Jenkins) <>
Reviewed-by: Furquan Shaikh <>
2017-10-20 22:49:50 +00:00
Shelley Chen bdfc5f5790 google/fizz: Set PL2 value based on sku id/charge max power
Set PL2 based on either 90% of usb c charger's max power or sku id if
using a barrel jack.

TEST=output debug info for different skus and make sure
     PL2 set correctly.

Change-Id: I487fce4a5d0825a26488e71dee02400dbebbffb3
Signed-off-by: Shelley Chen <>
Tested-by: build bot (Jenkins) <>
Reviewed-by: Aaron Durbin <>
2017-10-20 22:49:42 +00:00
Shelley Chen ebd533065f chromeec: Add function to retrieve usb c charger info
Add google_chromeec_get_usb_pd_power_info(), which will
call the EC_CMD_USB_PD_POWER_INFO host command to retrieve
the current and voltage info of the usb c charger.
Returns power info in watts.

TEST=output debug info to make sure that correct power
     is returned.

Change-Id: Ie14a0a6163e1c2699cb20b4422c8062164d92076
Signed-off-by: Shelley Chen <>
Tested-by: build bot (Jenkins) <>
Reviewed-by: Aaron Durbin <>
2017-10-20 22:49:31 +00:00
Aaron Durbin bd885c5bac lib/gpio: constify array inputs
The arrays of gpio_t are not manipulated in any way within the
gpio library. Add const to indicate that.

Change-Id: Ie32ab9de967ece22317e2b97b62e85b0757b910d
Signed-off-by: Aaron Durbin <>
Tested-by: build bot (Jenkins) <>
Reviewed-by: Furquan Shaikh <>
Reviewed-by: Paul Menzel <>
2017-10-20 22:49:27 +00:00
Marc Jones e8e72bd0ca stoneyridge: Add SCI/GPE configuration
Add functions for configuring the GPE ACPI SCI events.

TEST=With the Kahlee GPE setup patch, test lidswitch powers
the device on and off at the login screen.

Change-Id: I5c282268edbd7b92a3f2ca7c72896406c8f8512f
Signed-off-by: Marc Jones <>
Tested-by: build bot (Jenkins) <>
Reviewed-by: Aaron Durbin <>
2017-10-20 21:32:29 +00:00
Marc Jones f1c8ea35b3 soc/stoneyridge: Remove _PRW ASL
Remove _PRW GPE settings from GPP and USB ASL. The mainboard sets
the GPEs.

In addition, Stoney Ridge GPPs don't generate a GPE/SCIs.

Change-Id: Ib6a07a997bc3508109a67867014210091efc0c99
Signed-off-by: Marc Jones <>
Tested-by: build bot (Jenkins) <>
Reviewed-by: Aaron Durbin <>
Reviewed-by: Paul Menzel <>
2017-10-20 21:32:23 +00:00
Marc Jones 2e8476c35d stoneyridge: Fix USB ASL
Stoney Ridge has one EHCI controller and one XHCI controller.
Also, update the Kahlee and Gardenia mainboards ASL to match.

Change-Id: I5749ca0640796732e74e551147f8c4446317b77e
Signed-off-by: Marc Jones <>
Tested-by: build bot (Jenkins) <>
Reviewed-by: Aaron Durbin <>
2017-10-20 21:32:16 +00:00
Lijian Zhao c866f878bc intel/cannonlake_rvp: Update board name
Change the board name from cannonlake U DDR4 to U LPDDR4 to match
actual platform.


Change-Id: Id350e3cbc299d49431197ef5f914ea9a7310a0a5
Signed-off-by: Lijian Zhao <>
Tested-by: build bot (Jenkins) <>
Reviewed-by: Aaron Durbin <>
Reviewed-by: Pratikkumar V Prajapati <>
2017-10-20 20:52:50 +00:00
Lijian Zhao 6a09eee4ad soc/intel/cannonlake: Add platform.asl
Include common platform.asl to have generic indication of power
transition state of system.

TEST=Enter and resume from S3, check the post code had been changed to
0096 and 0097.

Change-Id: Ic38ac6d7e60441caeba5c088c9dbe4d901355782
Signed-off-by: Lijian Zhao <>
Reviewed-by: Aaron Durbin <>
Tested-by: build bot (Jenkins) <>
Reviewed-by: Pratikkumar V Prajapati <>
2017-10-20 20:52:46 +00:00
Pratik Prajapati 418535e222 soc/intel/skylake: update GNVS with SGX data
- Call sgx_fill_gnvs to update GNVS data, if
- With this patch SGX ACPI device would get pached with enumaretd values
  of ECP device status, base address and length

Change-Id: Ief0531fbab34838a3f8adb9cdc7d3fe19203c432
Signed-off-by: Pratik Prajapati <>
Tested-by: build bot (Jenkins) <>
Reviewed-by: Aaron Durbin <>
2017-10-20 20:06:33 +00:00
Pratik Prajapati d06c7646ac soc/intel/apollolake: update GNVS with SGX data
Call sgx_fill_gnvs to update GNVS data, if

Change-Id: I692f466d2c6f537d44aa042c4890ee8055c982c8
Signed-off-by: Pratik Prajapati <>
Tested-by: build bot (Jenkins) <>
Reviewed-by: Aaron Durbin <>
2017-10-20 20:06:26 +00:00