vendor/intel/skykabylake: Update FSP header files to version 2.7.2
Update FSP header files to version 2.7.2. New UPDs added FspmUpd.h: *CleanMemory FspsUpd.h: *IslVrCmd *ThreeStrikeCounterDisable Structure member names used to specify memory configuration to MRC have been updated, SoC side romstage code is updated to handle this change. CQ-DEPEND=CL:*460573,CL:*460612,CL:*460592 BUG=b:65499724 BRANCH=None TEST= Build and boot soraka, basic sanity check and suspend resume checks. Change-Id: Ia4eca011bc9a3b1a50e49d6d86a09d05a0cbf151 Signed-off-by: Balaji Manigandan B <balaji.manigandan@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/21679 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Balaji Manigandan B
Martin Roth
parent
53b8a82e72
commit
bd55c02a23
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@ -80,11 +80,11 @@ static void save_dimm_info(void)
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dimm_max = ARRAY_SIZE(mem_info->dimm);
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ctrlr_info = &memory_info_hob->Controller[0];
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for (channel = 0; channel < MAX_CH && index < dimm_max; channel++) {
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channel_info = &ctrlr_info->Channel[channel];
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channel_info = &ctrlr_info->ChannelInfo[channel];
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if (channel_info->Status != 2)
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continue;
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for (dimm = 0; dimm < MAX_DIMM && index < dimm_max; dimm++) {
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src_dimm = &channel_info->Dimm[dimm];
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src_dimm = &channel_info->DimmInfo[dimm];
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dest_dimm = &mem_info->dimm[index];
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if (src_dimm->Status != DIMM_PRESENT)
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@ -93,8 +93,8 @@ static void save_dimm_info(void)
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/* Populate the DIMM information */
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dimm_info_fill(dest_dimm,
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src_dimm->DimmCapacity,
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memory_info_hob->DdrType,
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memory_info_hob->Frequency,
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memory_info_hob->MemoryType,
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memory_info_hob->ConfiguredMemoryClockSpeed,
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channel_info->ChannelId,
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src_dimm->DimmId,
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(const char *)src_dimm->ModulePartNum,
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@ -844,7 +844,7 @@ typedef struct {
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/** Offset 0x02E3 - Ring Downbin
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Ring Downbin enable/disable. When enabled, CPU will ensure the ring ratio is always
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lower than the core ratio.<b>0: Disable</b>; 1: Enable.
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lower than the core ratio. 0: Disable; <b>1: Enable.</b>
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$EN_DIS
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**/
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UINT8 RingDownBin;
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@ -1255,9 +1255,15 @@ typedef struct {
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**/
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UINT8 Avx3RatioOffset;
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/** Offset 0x051B
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/** Offset 0x051B - Ask MRC to clear memory content
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Ask MRC to clear memory content <b>0: Do not Clear Memory;</b> 1: Clear Memory.
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$EN_DIS
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**/
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UINT8 ReservedFspmUpd[5];
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UINT8 CleanMemory;
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/** Offset 0x051C
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**/
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UINT8 ReservedFspmUpd[4];
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} FSP_M_CONFIG;
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/** Fsp M Test Configuration
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@ -167,7 +167,7 @@ typedef struct {
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/** Offset 0x0036 - Flash Configuration Lock Down
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Enable/disable flash lock down. If platform decides to skip this programming, it
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must lock SPI flash register before end of post.
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must lock SPI flash register DLOCK, FLOCKDN, and WRSDIS before end of post.
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$EN_DIS
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**/
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UINT8 SpiFlashCfgLockDown;
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@ -484,7 +484,7 @@ typedef struct {
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/** Offset 0x020C - PCIe DeEmphasis control per root port
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0: -6dB, 1(Default): -3.5dB
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0:Disable, 2:L1
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0:-6dB, 1:-3.5dB
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**/
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UINT8 PegDeEmphasis[3];
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@ -2060,9 +2060,15 @@ typedef struct {
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**/
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UINT8 MeUnconfigIsValid;
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/** Offset 0x077A
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/** Offset 0x077A - Activates VR mailbox command for Intersil VR C-state issues.
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Intersil VR mailbox command. <b>0 - no mailbox command sent.</b> 1 - VR mailbox
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command sent for IA/GT rails only. 2 - VR mailbox command sent for IA/GT/SA rails.
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**/
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UINT8 ReservedFspsUpd[6];
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UINT8 IslVrCmd;
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/** Offset 0x077B
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**/
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UINT8 ReservedFspsUpd[5];
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} FSP_S_CONFIG;
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/** Fsp S Test Configuration
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@ -2107,7 +2113,7 @@ typedef struct {
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UINT8 DmiIot;
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/** Offset 0x0789 - PEG Max Payload size per root port
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0xFF(Default):Auto, 0x1: Force 128B, 0X2: Force 256B
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0xFF(Default):Auto, 0x1: Force 128B, 0x2: Force 256B
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0xFF: Auto, 0x1: Force 128B, 0x2: Force 256B
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**/
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UINT8 PegMaxPayload[3];
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@ -2520,25 +2526,25 @@ typedef struct {
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/** Offset 0x07DA - Enable or Disable Package C-State Demotion
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Enable or Disable Package C-State Demotion. 0: Disable; 1: Enable; <b>2: Auto</b>
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(Auto: Enabled for Skylake; Disabled for Kabylake)
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$EN_DIS
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0:Disable, 1:Enable, 2:Auto
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**/
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UINT8 PkgCStateDemotion;
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/** Offset 0x07DB - Enable or Disable Package C-State UnDemotion
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Enable or Disable Package C-State UnDemotion. 0: Disable; 1: Enable; <b>2: Auto</b>
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(Auto: Enabled for Skylake; Disabled for Kabylake)
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$EN_DIS
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0:Disable, 1:Enable, 2:Auto
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**/
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UINT8 PkgCStateUnDemotion;
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/** Offset 0x07DC - Enable or Disable CState-Pre wake
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Enable or Disable CState-Pre wake. Disable; <b>1: Enable</b>
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Enable or Disable CState-Pre wake. 0: Disable; <b>1: Enable</b>
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$EN_DIS
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**/
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UINT8 CStatePreWake;
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/** Offset 0x07DD - Enable or Disable TimedMwait Support.
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Enable or Disable TimedMwait Support. <b>Disable</b>; 1: Enable
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Enable or Disable TimedMwait Support. <b>0: Disable</b>; 1: Enable
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$EN_DIS
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**/
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UINT8 TimedMwait;
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@ -2606,7 +2612,7 @@ typedef struct {
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/** Offset 0x07E8 - Configuration for boot TDP selection
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Configuration for boot TDP selection; <b>0: TDP Nominal</b>; 1: TDP Down; 2: TDP
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Up;0xFF : Deactivate
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Up; 0xFF: Deactivate
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0:TDP Nominal, 1:TDP Down, 2:TDP Up, 0xFF:Deactivate
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**/
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UINT8 ConfigTdpLevel;
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@ -2632,12 +2638,14 @@ typedef struct {
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UINT16 StateRatio[40];
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/** Offset 0x083C - Interrupt Response Time Limit of C-State LatencyContol0
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Interrupt Response Time Limit of C-State LatencyContol0. Range of value 0 to 0x3FF
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Interrupt Response Time Limit of C-State LatencyContol0.Range of value 0 to 0x3FF,
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Default is 0x4E, Server Platform is 0x4B
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**/
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UINT16 CstateLatencyControl0Irtl;
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/** Offset 0x083E - Interrupt Response Time Limit of C-State LatencyContol1
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Interrupt Response Time Limit of C-State LatencyContol1.Range of value 0 to 0x3FF
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Interrupt Response Time Limit of C-State LatencyContol1.Range of value 0 to 0x3FF,
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Default is 0x76, Server Platform is 0x6B
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**/
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UINT16 CstateLatencyControl1Irtl;
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@ -2783,11 +2791,18 @@ typedef struct {
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**/
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UINT8 EightCoreRatioLimit;
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/** Offset 0x0888 - ReservedCpuPostMemTest
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/** Offset 0x0888 - Set Three Strike Counter Disable
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False (default): Three Strike counter will be incremented and True: Prevents Three
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Strike counter from incrementing; <b>0: False</b>; 1: True.
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0: False, 1: True
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**/
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UINT8 ThreeStrikeCounterDisable;
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/** Offset 0x0889 - ReservedCpuPostMemTest
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Reserved for CPU Post-Mem Test
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$EN_DIS
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**/
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UINT8 ReservedCpuPostMemTest[2];
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UINT8 ReservedCpuPostMemTest[1];
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/** Offset 0x088A - SgxSinitDataFromTpm
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SgxSinitDataFromTpm default values
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@ -2923,7 +2938,7 @@ typedef struct {
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UINT8 PchPmDisableEnergyReport;
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/** Offset 0x0A2F - PCH Pm Pmc Read Disable
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When set to true, this bit disallows host reads to PMC XRAM.
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Deprecated
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$EN_DIS
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**/
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UINT8 PchPmPmcReadDisable;
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@ -53,6 +53,25 @@ extern EFI_GUID gSiMemoryPlatformDataGuid;
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#define B_RANK2_PRS BIT4
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#define B_RANK3_PRS BIT5
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// @todo remove and use the MdePkg\Include\Pi\PiHob.h
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#if !defined(_PEI_HOB_H_) && !defined(__PI_HOB_H__)
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#ifndef __HOB__H__
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typedef struct _EFI_HOB_GENERIC_HEADER {
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UINT16 HobType;
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UINT16 HobLength;
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UINT32 Reserved;
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} EFI_HOB_GENERIC_HEADER;
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typedef struct _EFI_HOB_GUID_TYPE {
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EFI_HOB_GENERIC_HEADER Header;
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EFI_GUID Name;
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///
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/// Guid specific data goes here
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///
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} EFI_HOB_GUID_TYPE;
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#endif
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#endif
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///
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/// Defines taken from MRC so avoid having to include MrcInterface.h
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///
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@ -122,7 +141,7 @@ typedef struct {
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#define MRC_DDR_TYPE_UNKNOWN 3
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#endif
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#define MAX_PROFILE_NUM 4 // number of memory profiles supported
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#define MAX_PROFILE_NUM 4 // number of memory profiles supported
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#define MAX_XMP_PROFILE_NUM 2 // number of XMP profiles supported
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//
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@ -151,64 +170,102 @@ typedef struct {
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UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups.
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} MRC_CH_TIMING;
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typedef struct {
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UINT8 SG; ///< Number of tCK cycles between transactions in the same bank group.
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UINT8 DG; ///< Number of tCK cycles between transactions when switching bank groups.
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UINT8 DR; ///< Number of tCK cycles between transactions when switching between Ranks (in the same DIMM).
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UINT8 DD; ///< Number of tCK cycles between transactions when switching between DIMMs.
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} MRC_TA_TIMING;
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///
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/// Memory SMBIOS & OC Memory Data Hob
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///
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typedef struct {
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UINT8 Status; ///< See MrcDimmStatus for the definition of this field.
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UINT8 DimmId;
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UINT32 DimmCapacity; ///< DIMM size in MBytes.
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UINT16 MfgId;
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UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes
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UINT8 RankInDimm; ///< The number of ranks in this DIMM.
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UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation.
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UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation.
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UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation.
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UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation.
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UINT8 Status; ///< See MrcDimmStatus for the definition of this field.
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UINT8 DimmId;
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UINT32 DimmCapacity; ///< DIMM size in MBytes.
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UINT16 MfgId;
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UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes
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UINT8 RankInDimm; ///< The number of ranks in this DIMM.
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UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation.
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UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation.
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UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation.
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UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation.
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} DIMM_INFO;
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typedef struct {
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UINT8 Status; ///< Indicates whether this channel should be used.
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UINT8 ChannelId;
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UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel.
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MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values.
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DIMM_INFO Dimm[MAX_DIMM]; ///< Save the DIMM output characteristics.
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UINT8 Status; ///< Indicates whether this channel should be used.
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UINT8 ChannelId;
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UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel.
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MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values.
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DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output characteristics.
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} CHANNEL_INFO;
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typedef struct {
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UINT8 Status; ///< Indicates whether this controller should be used.
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UINT16 DeviceId; ///< The PCI device id of this memory controller.
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UINT8 RevisionId; ///< The PCI revision id of this memory controller.
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UINT8 ChannelCount; ///< Number of valid channels that exist on the controller.
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CHANNEL_INFO Channel[MAX_CH]; ///< The following are channel level definitions.
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UINT8 Status; ///< Indicates whether this controller should be used.
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UINT16 DeviceId; ///< The PCI device id of this memory controller.
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UINT8 RevisionId; ///< The PCI revision id of this memory controller.
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UINT8 ChannelCount; ///< Number of valid channels that exist on the controller.
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CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions.
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MRC_TA_TIMING tRd2Rd; ///< Read-to-Read Turn Around Timings
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MRC_TA_TIMING tRd2Wr; ///< Read-to-Write Turn Around Timings
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MRC_TA_TIMING tWr2Rd; ///< Write-to-Read Turn Around Timings
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MRC_TA_TIMING tWr2Wr; ///< Write-to-Write Turn Around Timings
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} CONTROLLER_INFO;
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typedef struct {
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UINT8 Revision;
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UINT16 DataWidth;
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UINT16 DataWidth; ///< Data width, in bits, of this memory device
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/** As defined in SMBIOS 3.0 spec
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Section 7.18.2 and Table 75
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**/
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UINT8 DdrType; ///< DDR type: DDR3, DDR4, or LPDDR3
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UINT32 Frequency; ///< The system's common memory controller frequency in MT/s.
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UINT8 MemoryType; ///< DDR type: DDR3, DDR4, or LPDDR3
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UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz)
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UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz)
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/** As defined in SMBIOS 3.0 spec
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Section 7.17.3 and Table 72
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**/
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UINT8 ErrorCorrectionType;
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SiMrcVersion Version;
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UINT32 FreqMax;
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BOOLEAN EccSupport;
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UINT8 MemoryProfile;
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UINT32 TotalPhysicalMemorySize;
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UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM]; // Stores the tCK value read from SPD XMP profiles if they exist.
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UINT8 XmpProfileEnable; // If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs.
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UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist.
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UINT8 XmpProfileEnable; ///< If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs.
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UINT8 Ratio;
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UINT8 RefClk;
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UINT32 VddVoltage[MAX_PROFILE_NUM];
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CONTROLLER_INFO Controller[MAX_NODE];
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} MEMORY_INFO_DATA_HOB;
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/**
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Memory Platform Data Hob
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<b>Revision 1:</b>
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- Initial version.
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<b>Revision 2:</b>
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- Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddress fields
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**/
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typedef struct {
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UINT8 Revision;
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UINT8 Reserved[3];
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UINT32 BootMode;
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UINT32 TsegSize;
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UINT32 TsegBase;
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UINT32 PrmrrSize;
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UINT32 PrmrrBase;
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UINT32 GttBase;
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UINT32 MmioSize;
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UINT32 PciEBaseAddress;
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} MEMORY_PLATFORM_DATA;
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typedef struct {
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EFI_HOB_GUID_TYPE EfiHobGuidType;
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MEMORY_PLATFORM_DATA Data;
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UINT8 *Buffer;
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} MEMORY_PLATFORM_DATA_HOB;
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#pragma pack (pop)
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#endif // _MEM_INFO_HOB_H_
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