soc/intel/cannonlake: Add all the SOC level DSDT tables
Add all the SOC level DSDT tables, reference from skylake/kabylake. Change-Id: Ia72bbe87b32d37db01f8768bd8447cb6ee1567a9 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21860 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Lijian Zhao
Aaron Durbin
parent
d347680995
commit
ae565463b6
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@ -0,0 +1,23 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2017 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/* IPU3 input system - Device 05, Function 0 */
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Device (IMGU)
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{
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Name (_ADR, 0x00050000)
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Name (_DDN, "Imaging Unit")
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Name (_CCA, ZERO)
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Name (CAMD, 0x01)
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}
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@ -0,0 +1,117 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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* Copyright (C) 2014 Google Inc.
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* Copyright (C) 2015 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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Device (LPCB)
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{
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Name (_ADR, 0x001f0000)
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Name (_DDN, "LPC Bus Device")
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Device (FWH)
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{
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Name (_HID, EISAID ("INT0800"))
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Name (_DDN, "Firmware Hub")
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Name (_CRS, ResourceTemplate ()
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{
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Memory32Fixed (ReadOnly, 0xff000000, 0x01000000)
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})
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}
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Device (HPET)
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{
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Name (_HID, EISAID ("PNP0103"))
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Name (_DDN, "High Precision Event Timer")
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Name (_CRS, ResourceTemplate ()
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{
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Memory32Fixed (ReadWrite, HPET_BASE_ADDRESS, 0x400)
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})
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Method (_STA, 0)
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{
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Return (0xf)
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}
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}
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Device (PIC)
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{
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Name (_HID, EISAID ("PNP0000"))
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Name (_DDN, "8259 Interrupt Controller")
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Name (_CRS, ResourceTemplate()
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{
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IO (Decode16, 0x20, 0x20, 0x01, 0x02)
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IO (Decode16, 0x24, 0x24, 0x01, 0x02)
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IO (Decode16, 0x28, 0x28, 0x01, 0x02)
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IO (Decode16, 0x2c, 0x2c, 0x01, 0x02)
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IO (Decode16, 0x30, 0x30, 0x01, 0x02)
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IO (Decode16, 0x34, 0x34, 0x01, 0x02)
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IO (Decode16, 0x38, 0x38, 0x01, 0x02)
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IO (Decode16, 0x3c, 0x3c, 0x01, 0x02)
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IO (Decode16, 0xa0, 0xa0, 0x01, 0x02)
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IO (Decode16, 0xa4, 0xa4, 0x01, 0x02)
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IO (Decode16, 0xa8, 0xa8, 0x01, 0x02)
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IO (Decode16, 0xac, 0xac, 0x01, 0x02)
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IO (Decode16, 0xb0, 0xb0, 0x01, 0x02)
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IO (Decode16, 0xb4, 0xb4, 0x01, 0x02)
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IO (Decode16, 0xb8, 0xb8, 0x01, 0x02)
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IO (Decode16, 0xbc, 0xbc, 0x01, 0x02)
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IO (Decode16, 0x4d0, 0x4d0, 0x01, 0x02)
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IRQNoFlags () { 2 }
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})
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}
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Device (LDRC)
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{
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Name (_HID, EISAID ("PNP0C02"))
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Name (_UID, 2)
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Name (_DDN, "Legacy Device Resources")
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Name (_CRS, ResourceTemplate ()
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{
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IO (Decode16, 0x2e, 0x2e, 0x1, 0x02) // First SuperIO
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IO (Decode16, 0x4e, 0x4e, 0x1, 0x02) // Second SuperIO
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IO (Decode16, 0x61, 0x61, 0x1, 0x01) // NMI Status
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IO (Decode16, 0x63, 0x63, 0x1, 0x01) // CPU Reserved
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IO (Decode16, 0x65, 0x65, 0x1, 0x01) // CPU Reserved
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IO (Decode16, 0x67, 0x67, 0x1, 0x01) // CPU Reserved
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IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post
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IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved
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IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI
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IO (Decode16, ACPI_BASE_ADDRESS, ACPI_BASE_ADDRESS,
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0x1, 0xff)
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})
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}
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Device (RTC)
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{
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Name (_HID, EISAID ("PNP0B00"))
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Name (_DDN, "Real Time Clock")
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Name (_CRS, ResourceTemplate ()
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{
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IO (Decode16, 0x70, 0x70, 1, 8)
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})
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}
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Device (TIMR)
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{
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Name (_HID, EISAID ("PNP0100"))
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Name (_DDN, "8254 Timer")
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Name (_CRS, ResourceTemplate ()
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{
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IO (Decode16, 0x40, 0x40, 0x01, 0x04)
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IO (Decode16, 0x50, 0x50, 0x10, 0x04)
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IRQNoFlags () {0}
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})
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}
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}
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@ -0,0 +1,84 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015 Google Inc.
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* Copyright (C) 2017 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/* Audio Controller - Device 31, Function 3 */
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Device (HDAS)
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{
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Name (_ADR, 0x001f0003)
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Name (_DDN, "Audio Controller")
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Name (UUID, ToUUID ("A69F886E-6CEB-4594-A41F-7B5DCE24C553"))
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/* Device is D3 wake capable */
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Name (_S0W, 3)
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/* NHLT Table Address populated from GNVS values */
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Name (NBUF, ResourceTemplate () {
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QWordMemory (ResourceConsumer, PosDecode, MinFixed,
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MaxFixed, NonCacheable, ReadOnly,
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0, 0, 0, 0, 1,,, NHLT, AddressRangeACPI)
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})
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/*
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* Device Specific Method
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* Arg0 - UUID
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* Arg1 - Revision
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* Arg2 - Function Index
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*/
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Method (_DSM, 4)
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{
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If (LEqual (Arg0, ^UUID)) {
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/*
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* Function 0: Function Support Query
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* Returns a bitmask of functions supported.
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*/
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If (LEqual (Arg2, Zero)) {
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/*
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* NHLT Query only supported for revision 1 and
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* if NHLT address and length are set in NVS.
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*/
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If (LAnd (LEqual (Arg1, One),
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LAnd (LNotEqual (NHLA, Zero),
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LNotEqual (NHLL, Zero)))) {
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Return (Buffer (One) { 0x03 })
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} Else {
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Return (Buffer (One) { 0x01 })
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}
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}
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/*
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* Function 1: Query NHLT memory address used by
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* Intel Offload Engine Driver to discover any non-HDA
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* devices that are supported by the DSP.
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*
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* Returns a pointer to NHLT table in memory.
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*/
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If (LEqual (Arg2, One)) {
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CreateQWordField (NBUF, ^NHLT._MIN, NBAS)
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CreateQWordField (NBUF, ^NHLT._MAX, NMAS)
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CreateQWordField (NBUF, ^NHLT._LEN, NLEN)
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Store (NHLA, NBAS)
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Store (NHLA, NMAS)
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Store (NHLL, NLEN)
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Return (NBUF)
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}
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}
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Return (Buffer (One) { 0x00 })
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}
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}
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@ -0,0 +1,66 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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* Copyright (C) 2014 Google Inc.
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* Copyright (C) 2017 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/* Enable ACPI _SWS methods */
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#include <soc/intel/common/acpi/acpi_wake_source.asl>
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/* The APM port can be used for generating software SMIs */
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OperationRegion (APMP, SystemIO, 0xb2, 2)
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Field (APMP, ByteAcc, NoLock, Preserve)
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{
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APMC, 8, // APM command
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APMS, 8 // APM status
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}
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/* Port 80 POST */
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OperationRegion (POST, SystemIO, 0x80, 1)
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Field (POST, ByteAcc, Lock, Preserve)
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{
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DBG0, 8
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}
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/*
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* The _PIC method is called by the OS to choose between interrupt
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* routing via the i8259 interrupt controller or the APIC.
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*
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* _PIC is called with a parameter of 0 for i8259 configuration and
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* with a parameter of 1 for Local Apic/IOAPIC configuration.
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*/
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Method (_PIC, 1)
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{
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/* Remember the OS' IRQ routing choice. */
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Store (Arg0, PICM)
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}
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/*
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* The _PTS method (Prepare To Sleep) is called before the OS is
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* entering a sleep state. The sleep state number is passed in Arg0
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*/
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Method (_PTS, 1)
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{
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}
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/* The _WAK method is called on system wakeup */
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Method (_WAK, 1)
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{
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Return (Package (){ 0, 0 })
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}
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@ -0,0 +1,89 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015 Google Inc.
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* Copyright (C) 2017 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
|
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/* Intel Serial IO Devices */
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Device (I2C0)
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{
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Name (_ADR, 0x00150000)
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Name (_DDN, "Serial IO I2C Controller 0")
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}
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Device (I2C1)
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{
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Name (_ADR, 0x00150001)
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Name (_DDN, "Serial IO I2C Controller 1")
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}
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Device (I2C2)
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{
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Name (_ADR, 0x00150002)
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Name (_DDN, "Serial IO I2C Controller 2")
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}
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Device (I2C3)
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{
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Name (_ADR, 0x00150003)
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Name (_DDN, "Serial IO I2C Controller 3")
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}
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Device (I2C4)
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{
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Name (_ADR, 0x00190000)
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Name (_DDN, "Serial IO I2C Controller 4")
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}
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Device (I2C5)
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{
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Name (_ADR, 0x00190001)
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Name (_DDN, "Serial IO I2C Controller 5")
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}
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Device (SPI0)
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{
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Name (_ADR, 0x001e0002)
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Name (_DDN, "Serial IO SPI Controller 0")
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}
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Device (SPI1)
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{
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Name (_ADR, 0x001e0003)
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Name (_DDN, "Serial IO SPI Controller 1")
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}
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Device (SPI2)
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{
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Name (_ADR, 0x00120006)
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Name (_DDN, "Serial IO SPI Controller 2")
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}
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Device (UAR0)
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{
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Name (_ADR, 0x001e0000)
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Name (_DDN, "Serial IO UART Controller 0")
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}
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Device (UAR1)
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{
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Name (_ADR, 0x001e0001)
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Name (_DDN, "Serial IO UART Controller 1")
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}
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|
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Device (UAR2)
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{
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Name (_ADR, 0x00190002)
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Name (_DDN, "Serial IO UART Controller 2")
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}
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@ -0,0 +1,23 @@
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/*
|
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* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2009 coresystems GmbH
|
||||
* Copyright (C) 2014 Google Inc.
|
||||
* Copyright (C) 2017 Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
// Intel SMBus Controller 0:1f.4
|
||||
|
||||
Device (SBUS)
|
||||
{
|
||||
Name (_ADR, 0x001f0004)
|
||||
}
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|
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@ -27,3 +27,21 @@
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|
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/* GPIO controller */
|
||||
#include "gpio.asl"
|
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|
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/* LPC 0:1f.0 */
|
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#include "lpc.asl"
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|
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/* PCH HDA */
|
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#include "pch_hda.asl"
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||||
|
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/* Serial IO */
|
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#include "serialio.asl"
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||||
|
||||
/* SMBus 0:1f.3 */
|
||||
#include "smbus.asl"
|
||||
|
||||
/* USB XHCI 0:14.0 */
|
||||
#include "xhci.asl"
|
||||
|
||||
/* PCI _OSC */
|
||||
#include <soc/intel/common/acpi/pci_osc.asl>
|
||||
|
|
|
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|
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@ -0,0 +1,215 @@
|
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/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2009 coresystems GmbH
|
||||
* Copyright (C) 2015 Google Inc.
|
||||
* Copyright (C) 2015 Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <soc/gpe.h>
|
||||
/*
|
||||
* USB Port Wake Enable (UPWE) on usb attach/detach
|
||||
* Arg0 - Port Number
|
||||
* Arg1 - Port 1 Status and control offset
|
||||
* Arg2 - xHCI Memory-mapped address
|
||||
*/
|
||||
Method (UPWE, 3, Serialized)
|
||||
{
|
||||
/* Local0 = Arg1 + ((Arg0 - 1) * 0x10) */
|
||||
Add (Arg1, Multiply (Subtract (Arg0, 1), 0x10), Local0)
|
||||
|
||||
/* Map ((XMEM << 16) + Local0 in PSCR */
|
||||
OperationRegion (PSCR, SystemMemory,
|
||||
Add (ShiftLeft (Arg2, 16), Local0), 0x10)
|
||||
Field (PSCR, AnyAcc, NoLock, Preserve)
|
||||
{
|
||||
, 25,
|
||||
UPCE, 1,
|
||||
UPDE, 1,
|
||||
}
|
||||
Store (One, UPCE)
|
||||
Store (One, UPDE)
|
||||
}
|
||||
|
||||
/*
|
||||
* USB Wake Enable Setup (UWES)
|
||||
* Arg0 - Port enable bitmap
|
||||
* Arg1 - Port 1 Status and control offset
|
||||
* Arg2 - xHCI Memory-mapped address
|
||||
*/
|
||||
Method (UWES, 3, Serialized)
|
||||
{
|
||||
Store (Arg0, Local0)
|
||||
|
||||
While (One) {
|
||||
FindSetRightBit (Local0, Local1)
|
||||
If (LEqual (Local1, Zero)) {
|
||||
Break
|
||||
}
|
||||
UPWE (Local1, Arg1, Arg2)
|
||||
/*
|
||||
* Clear the lowest set bit in Local0 since it was
|
||||
* processed.
|
||||
* Local0 = Local0 & (Local0 - 1)
|
||||
*/
|
||||
And (Local0, Subtract (Local0, 1), Local0)
|
||||
}
|
||||
}
|
||||
|
||||
/* XHCI Controller 0:14.0 */
|
||||
|
||||
Device (XHCI)
|
||||
{
|
||||
Name (_ADR, 0x00140000)
|
||||
|
||||
Name (_PRW, Package () { GPE0_PME_B0, 3 })
|
||||
|
||||
Method (_DSW, 3)
|
||||
{
|
||||
Store (Arg0, PMEE)
|
||||
UWES (And (\U2WE, 0x3FF), 0x480, XMEM)
|
||||
UWES (And (\U3WE, 0x3F), 0x540, XMEM)
|
||||
}
|
||||
|
||||
Name (_S3D, 3) /* D3 supported in S3 */
|
||||
Name (_S4D, 3) /* D3 supported in S4 */
|
||||
Name (_S0W, 3) /* D3 can wake device in S0 */
|
||||
Name (_S3W, 3) /* D3 can wake system from S3 */
|
||||
Name (_S4W, 3) /* D3 can wake system from S4 */
|
||||
|
||||
OperationRegion (XPRT, PCI_Config, 0x00, 0x100)
|
||||
Field (XPRT, AnyAcc, NoLock, Preserve)
|
||||
{
|
||||
Offset (0x0),
|
||||
DVID, 16, /* VENDORID */
|
||||
Offset (0x10),
|
||||
, 16,
|
||||
XMEM, 16, /* MEM_BASE */
|
||||
Offset (0x50), /* XHCLKGTEN */
|
||||
, 2,
|
||||
STGE, 1, /* SS Link Trunk clock gating enable */
|
||||
Offset (0x74),
|
||||
D0D3, 2, /* POWERSTATE */
|
||||
, 6,
|
||||
PMEE, 1, /* PME_EN */
|
||||
, 6,
|
||||
PMES, 1, /* PME_STS */
|
||||
Offset (0xA2),
|
||||
, 2,
|
||||
D3HE, 1, /* D3_hot_en */
|
||||
}
|
||||
|
||||
OperationRegion (XREG, SystemMemory,
|
||||
Add (ShiftLeft (XMEM, 16), 0x8000), 0x200)
|
||||
Field (XREG, DWordAcc, Lock, Preserve)
|
||||
{
|
||||
Offset (0x1c4), /* USB2PMCTRL */
|
||||
, 2,
|
||||
UPSW, 2, /* U2PSUSPGP */
|
||||
}
|
||||
|
||||
Method (_PSC, 0, Serialized)
|
||||
{
|
||||
Return (^D0D3)
|
||||
}
|
||||
|
||||
Method (_PS0, 0, Serialized)
|
||||
{
|
||||
If (LEqual (^DVID, 0xFFFF)) {
|
||||
Return
|
||||
}
|
||||
If (LOr (LEqual (^XMEM, 0xFFFF), LEqual (^XMEM, 0x0000))) {
|
||||
Return
|
||||
}
|
||||
|
||||
/* Disable d3hot and SS link trunk clock gating */
|
||||
Store(Zero, ^D3HE)
|
||||
Store(Zero, ^STGE)
|
||||
|
||||
/* If device is in D3, set back to D0 */
|
||||
If (LEqual (^D0D3, 3)) {
|
||||
Store (Zero, Local0)
|
||||
Store (Local0, ^D0D3)
|
||||
Store (^D0D3, Local0)
|
||||
}
|
||||
|
||||
/* Disable USB2 PHY SUS Well Power Gating */
|
||||
Store (Zero, ^UPSW)
|
||||
}
|
||||
|
||||
Method (_PS3, 0, Serialized)
|
||||
{
|
||||
If (LEqual (^DVID, 0xFFFF)) {
|
||||
Return
|
||||
}
|
||||
If (LOr (LEqual (^XMEM, 0xFFFF), LEqual (^XMEM, 0x0000))) {
|
||||
Return
|
||||
}
|
||||
|
||||
/* Clear PME Status */
|
||||
Store (1, ^PMES)
|
||||
|
||||
/* Enable PME */
|
||||
Store (1, ^PMEE)
|
||||
|
||||
/* If device is in D3, set back to D0 */
|
||||
If (LEqual (^D0D3, 3)) {
|
||||
Store (Zero, Local0)
|
||||
Store (Local0, ^D0D3)
|
||||
Store (^D0D3, Local0)
|
||||
}
|
||||
|
||||
/* Enable USB2 PHY SUS Well Power Gating in D0/D0i2/D0i3/D3 */
|
||||
Store (3, ^UPSW)
|
||||
|
||||
/* Enable d3hot and SS link trunk clock gating */
|
||||
Store(One, ^D3HE)
|
||||
Store(One, ^STGE)
|
||||
|
||||
/* Now put device in D3 */
|
||||
Store (3, Local0)
|
||||
Store (Local0, ^D0D3)
|
||||
Store (^D0D3, Local0)
|
||||
}
|
||||
|
||||
/* Root Hub for Cannonlake-LP PCH */
|
||||
Device (RHUB)
|
||||
{
|
||||
Name (_ADR, Zero)
|
||||
|
||||
/* USB2 */
|
||||
Device (HS01) { Name (_ADR, 1) }
|
||||
Device (HS02) { Name (_ADR, 2) }
|
||||
Device (HS03) { Name (_ADR, 3) }
|
||||
Device (HS04) { Name (_ADR, 4) }
|
||||
Device (HS05) { Name (_ADR, 5) }
|
||||
Device (HS06) { Name (_ADR, 6) }
|
||||
Device (HS07) { Name (_ADR, 7) }
|
||||
Device (HS08) { Name (_ADR, 8) }
|
||||
Device (HS09) { Name (_ADR, 9) }
|
||||
Device (HS10) { Name (_ADR, 10) }
|
||||
Device (HS11) { Name (_ADR, 11) }
|
||||
Device (HS12) { Name (_ADR, 12) }
|
||||
|
||||
/* USBr */
|
||||
Device (USR1) { Name (_ADR, 11) }
|
||||
Device (USR2) { Name (_ADR, 12) }
|
||||
|
||||
/* USB3 */
|
||||
Device (SS01) { Name (_ADR, 13) }
|
||||
Device (SS02) { Name (_ADR, 14) }
|
||||
Device (SS03) { Name (_ADR, 15) }
|
||||
Device (SS04) { Name (_ADR, 16) }
|
||||
Device (SS05) { Name (_ADR, 17) }
|
||||
Device (SS06) { Name (_ADR, 18) }
|
||||
}
|
||||
}
|
||||
Loading…
Reference in New Issue