soc/intel/cannonlake: Add lpc pci driver
1.Add common ITSS support as part of LPC driver init code. 2.Add LPC pci driver for CNL Change-Id: I6c810fd7158e1498664b77eecae22132e2f6878f Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21277 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Lijian Zhao
Aaron Durbin
parent
1483d1fcda
commit
a515849259
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@ -24,6 +24,7 @@ config CPU_SPECIFIC_OPTIONS
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select HAVE_MONOTONIC_TIMER
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select INTEL_CAR_NEM_ENHANCED
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select INTEL_GMA_ADD_VBT_DATA_FILE if RUN_FSP_GOP
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select IOAPIC
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select PARALLEL_MP
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select PARALLEL_MP_AP_WORK
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select PLATFORM_USES_FSP2_0
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@ -43,6 +44,8 @@ config CPU_SPECIFIC_OPTIONS
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select SOC_INTEL_COMMON_BLOCK_FAST_SPI
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select SOC_INTEL_COMMON_BLOCK_GPIO
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select SOC_INTEL_COMMON_BLOCK_GSPI
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select SOC_INTEL_COMMON_BLOCK_ITSS
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select SOC_INTEL_COMMON_BLOCK_LPC
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select SOC_INTEL_COMMON_BLOCK_LPSS
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select SOC_INTEL_COMMON_BLOCK_PCR
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select SOC_INTEL_COMMON_BLOCK_PMC
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@ -32,6 +32,7 @@ ramstage-y += cpu.c
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ramstage-y += gpio.c
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ramstage-y += gspi.c
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ramstage-y += gpio.c
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ramstage-y += lpc.c
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ramstage-y += memmap.c
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ramstage-y += pmc.c
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ramstage-y += pmutil.c
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@ -194,6 +194,9 @@ struct soc_intel_cannonlake_config {
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/* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */
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uint8_t eist_enable;
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/* Statically clock gate 8254 PIT. */
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uint8_t clock_gate_8254;
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/* Enable C6 DRAM */
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uint8_t enable_c6dram;
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/*
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@ -0,0 +1,106 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Google Inc.
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* Copyright (C) 2017 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _SOC_IRQ_H_
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#define _SOC_IRQ_H_
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#define GPIO_IRQ14 14
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#define GPIO_IRQ15 15
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#define PCH_IRQ10 10
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#define PCH_IRQ11 11
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#define SCI_IRQ9 9
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#define SCI_IRQ10 10
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#define SCI_IRQ11 11
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#define SCI_IRQ20 20
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#define SCI_IRQ21 21
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#define SCI_IRQ22 22
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#define SCI_IRQ23 23
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#define TCO_IRQ9 9
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#define TCO_IRQ10 10
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#define TCO_IRQ11 11
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#define TCO_IRQ20 20
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#define TCO_IRQ21 21
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#define TCO_IRQ22 22
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#define TCO_IRQ23 23
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#define LPSS_I2C0_IRQ 16
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#define LPSS_I2C1_IRQ 17
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#define LPSS_I2C2_IRQ 18
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#define LPSS_I2C3_IRQ 19
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#define LPSS_I2C4_IRQ 32
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#define LPSS_I2C5_IRQ 33
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#define LPSS_SPI0_IRQ 22
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#define LPSS_SPI1_IRQ 23
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#define LPSS_SPI2_IRQ 24
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#define LPSS_UART0_IRQ 20
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#define LPSS_UART1_IRQ 21
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#define LPSS_UART2_IRQ 34
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#define SDIO_IRQ 22
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#define cAVS_INTA_IRQ 16
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#define SMBUS_INTA_IRQ 16
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#define SMBUS_INTB_IRQ 17
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#define GbE_INTA_IRQ 16
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#define GbE_INTC_IRQ 18
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#define TRACE_HUB_INTA_IRQ 16
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#define TRACE_HUB_INTD_IRQ 19
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#define eMMC_IRQ 16
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#define SD_IRQ 19
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#define PCIE_1_IRQ 16
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#define PCIE_2_IRQ 17
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#define PCIE_3_IRQ 18
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#define PCIE_4_IRQ 19
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#define PCIE_5_IRQ 16
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#define PCIE_6_IRQ 17
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#define PCIE_7_IRQ 18
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#define PCIE_8_IRQ 19
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#define PCIE_9_IRQ 16
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#define PCIE_10_IRQ 17
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#define PCIE_11_IRQ 18
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#define PCIE_12_IRQ 19
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#define SATA_IRQ 16
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#define HECI_1_IRQ 16
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#define HECI_2_IRQ 17
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#define IDER_IRQ 18
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#define KT_IRQ 19
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#define HECI_3_IRQ 16
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#define XHCI_IRQ 16
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#define OTG_IRQ 17
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#define THRMAL_IRQ 16
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#define CNViWIFI_IRQ 16
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#define UFS_IRQ 16
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#define CIO_INTA_IRQ 16
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#define CIO_INTD_IRQ 19
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#define ISH_IRQ 20
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#define PEG_RP_INTA_IRQ 16
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#define PEG_RP_INTB_IRQ 17
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#define PEG_RP_INTC_IRQ 18
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#define PEG_RP_INTD_IRQ 19
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#define IGFX_IRQ 16
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#define SA_THERMAL_IRQ 16
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#define SKYCAM_IRQ 16
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#define GMM_IRQ 16
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#endif /* _SOC_IRQ_H_ */
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@ -0,0 +1,23 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2017 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef SOC_INTEL_CNL_ITSS_H
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#define SOC_INTEL_CNL_ITSS_H
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#define ITSS_MAX_IRQ 119
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#define IRQS_PER_IPC 32
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#define NUM_IPC_REGS ((ITSS_MAX_IRQ + IRQS_PER_IPC - 1)/IRQS_PER_IPC)
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#endif /* SOC_INTEL_CNL_ITSS_H */
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@ -0,0 +1,206 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008-2009 coresystems GmbH
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* Copyright (C) 2014 Google Inc.
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* Copyright (C) 2017 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include "chip.h"
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#include <console/console.h>
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#include <delay.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <pc80/isa-dma.h>
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#include <pc80/i8259.h>
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#include <arch/io.h>
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#include <arch/ioapic.h>
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#include <intelblocks/itss.h>
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#include <intelblocks/lpc_lib.h>
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#include <intelblocks/pcr.h>
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#include <reg_script.h>
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#include <soc/iomap.h>
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#include <soc/pci_devs.h>
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#include <soc/pcr_ids.h>
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/*
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* As per the BWG, Chapter 5.9.1. "PCH BIOS component will reserve
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* certain memory range as reserved range for BIOS usage.
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* For this SOC, the range will be from 0FC800000h till FE7FFFFFh"
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*/
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static const struct lpc_mmio_range cnl_lpc_fixed_mmio_ranges[] = {
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{ PCH_PRESERVED_BASE_ADDRESS, PCH_PRESERVED_BASE_SIZE },
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{ 0, 0 }
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};
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const struct lpc_mmio_range *soc_get_fixed_mmio_ranges()
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{
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return cnl_lpc_fixed_mmio_ranges;
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}
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static void pch_enable_ioapic(const struct device *dev)
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{
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u32 reg32;
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/* PCH-LP has 120 redirection entries */
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const int redir_entries = 120;
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set_ioapic_id((void *)IO_APIC_ADDR, 0x02);
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/* affirm full set of redirection table entries ("write once") */
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reg32 = io_apic_read((void *)IO_APIC_ADDR, 0x01);
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reg32 &= ~0x00ff0000;
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reg32 |= (redir_entries - 1) << 16;
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io_apic_write((void *)IO_APIC_ADDR, 0x01, reg32);
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/*
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* Select Boot Configuration register (0x03) and
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* use Processor System Bus (0x01) to deliver interrupts.
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*/
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io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01);
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}
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void soc_get_gen_io_dec_range(const struct device *dev, uint32_t *gen_io_dec)
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{
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const config_t *config = dev->chip_info;
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gen_io_dec[0] = config->gen1_dec;
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gen_io_dec[1] = config->gen2_dec;
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gen_io_dec[2] = config->gen3_dec;
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gen_io_dec[3] = config->gen4_dec;
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}
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void soc_setup_dmi_pcr_io_dec(uint32_t *gen_io_dec)
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{
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/* Mirror these same settings in DMI PCR */
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pcr_write32(PID_DMI, PCR_DMI_LPCLGIR1, gen_io_dec[0]);
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pcr_write32(PID_DMI, PCR_DMI_LPCLGIR2, gen_io_dec[1]);
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pcr_write32(PID_DMI, PCR_DMI_LPCLGIR3, gen_io_dec[2]);
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pcr_write32(PID_DMI, PCR_DMI_LPCLGIR4, gen_io_dec[3]);
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}
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/*
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* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
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* 0x00 - 0000 = Reserved
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* 0x01 - 0001 = Reserved
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* 0x02 - 0010 = Reserved
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* 0x03 - 0011 = IRQ3
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* 0x04 - 0100 = IRQ4
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* 0x05 - 0101 = IRQ5
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* 0x06 - 0110 = IRQ6
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* 0x07 - 0111 = IRQ7
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* 0x08 - 1000 = Reserved
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* 0x09 - 1001 = IRQ9
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* 0x0A - 1010 = IRQ10
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* 0x0B - 1011 = IRQ11
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* 0x0C - 1100 = IRQ12
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* 0x0D - 1101 = Reserved
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* 0x0E - 1110 = IRQ14
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* 0x0F - 1111 = IRQ15
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* PIRQ[n]_ROUT[7] - PIRQ Routing Control
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* 0x80 - The PIRQ is not routed.
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*/
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void soc_pch_pirq_init(const struct device *dev)
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{
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const config_t *config = dev->chip_info;
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uint8_t pch_interrupt_routing[MAX_PXRC_CONFIG];
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pch_interrupt_routing[0] = config->pirqa_routing;
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pch_interrupt_routing[1] = config->pirqb_routing;
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pch_interrupt_routing[2] = config->pirqc_routing;
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pch_interrupt_routing[3] = config->pirqd_routing;
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pch_interrupt_routing[4] = config->pirqe_routing;
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pch_interrupt_routing[5] = config->pirqf_routing;
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pch_interrupt_routing[6] = config->pirqg_routing;
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pch_interrupt_routing[7] = config->pirqh_routing;
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itss_irq_init(pch_interrupt_routing);
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device_t irq_dev;
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for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
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u8 int_pin = 0, int_line = 0;
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if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
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continue;
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int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);
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switch (int_pin) {
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case 1: /* INTA# */
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int_line = config->pirqa_routing;
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break;
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case 2: /* INTB# */
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int_line = config->pirqb_routing;
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break;
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case 3: /* INTC# */
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int_line = config->pirqc_routing;
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break;
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case 4: /* INTD# */
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int_line = config->pirqd_routing;
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break;
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}
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if (!int_line)
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continue;
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pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line);
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}
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}
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static void pch_misc_init(void)
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{
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uint8_t reg8;
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/* Setup NMI on errors, disable SERR */
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reg8 = (inb(0x61)) & 0xf0;
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outb(0x61, (reg8 | (1 << 2)));
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/* Disable NMI sources */
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outb(0x70, (1 << 7));
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};
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static void clock_gate_8254(const struct device *dev)
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{
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const config_t *config = dev->chip_info;
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if (!config->clock_gate_8254)
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return;
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itss_clock_gate_8254();
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}
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void lpc_init(struct device *dev)
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{
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/* Legacy initialization */
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isa_dma_init();
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pch_misc_init();
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/* Enable CLKRUN_EN for power gating LPC */
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lpc_enable_pci_clk_cntl();
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/* Set LPC Serial IRQ mode */
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if (IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE))
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lpc_set_serirq_mode(SERIRQ_CONTINUOUS);
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else
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lpc_set_serirq_mode(SERIRQ_QUIET);
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/* Interrupt configuration */
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pch_enable_ioapic(dev);
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soc_pch_pirq_init(dev);
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setup_i8259();
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i8259_configure_irq_trigger(9, 1);
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clock_gate_8254(dev);
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}
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