coreboot-mirror
/
hpcorebootfe80
mirror of https://code.fe80.eu/microserver/coreboot.git
1
0
Fork 0
Code Issues Releases Wiki Activity

nb/intel/sandybridge/raminit: Add ECC detection support 

Add support for detection ECC capability and forced ECC mode.
Print the ECC mode in verbose debugging mode.

Change-Id: I5b7599746195cfa996a48320404a8dbe6820483a
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
This commit is contained in:
Patrick Rudolph 2017-10-28 16:36:09 +02:00 committed by Alexander Couzens
parent d1a76e3920
commit 8bd589d1b5
3 changed files with 43 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
src/northbridge/intel/sandybridge/raminit.c
View File

@ -401,6 +401,13 @@ static void init_dram_ddr3(int mobile, int min_tck, int s3resume)
cpu = cpures.eax;
ctrl.sandybridge = IS_SANDY_CPU(cpu);
/* Get ECC support and mode */
ctrl.ecc_supported = get_host_ecc_cap();
ctrl.ecc_forced = ctrl.ecc_supported ? get_host_ecc_mode() : 0;
printk(BIOS_DEBUG, "ECC supported: %s ECC forced: %s\n",
ctrl.ecc_supported ? "yes" : "no",
ctrl.ecc_forced ? "yes" : "no");
/* Get DDR3 SPD data */
memset(spds, 0, sizeof(spds));
mainboard_get_spd(spds, 0);
@ -424,6 +431,13 @@ static void init_dram_ddr3(int mobile, int min_tck, int s3resume)
cpu = cpures.eax;
ctrl.sandybridge = IS_SANDY_CPU(cpu);
/* Get ECC support and mode */
ctrl.ecc_supported = get_host_ecc_cap();
ctrl.ecc_forced = ctrl.ecc_supported ? get_host_ecc_mode() : 0;
printk(BIOS_DEBUG, "ECC supported: %s ECC forced: %s\n",
ctrl.ecc_supported ? "yes" : "no",
ctrl.ecc_forced ? "yes" : "no");
/* Reset DDR3 frequency */
dram_find_spds_ddr3(spds, &ctrl);

24
src/northbridge/intel/sandybridge/raminit_common.c
View File

@ -463,6 +463,30 @@ static unsigned int get_mmio_size(void)
return cfg->pci_mmio_size;
}
/*
* Returns the ECC capability.
* Return 0: ECC isn't supported
* Return 1: ECC is supported
*/
size_t get_host_ecc_cap(void)
{
/* read Capabilities A Register */
const u32 reg32 = pci_read_config32(PCI_DEV(0, 0, 0), CAPID0_A);
return !!(reg32 & (1 << 25));
}
/*
* Returns the ECC mode the NB is running at.
* Return 0: ECC is optional
* Return 1: ECC is enabled and can't be disabled
*/
size_t get_host_ecc_mode(void)
{
/* read Capabilities A Register */
const u32 reg32 = pci_read_config32(PCI_DEV(0, 0, 0), CAPID0_A);
return !!(reg32 & (1 << 24));
}
void dram_memorymap(ramctr_timing * ctrl, int me_uma_size)
{
u32 reg, val, reclaim;

5
src/northbridge/intel/sandybridge/raminit_common.h
View File

@ -119,6 +119,8 @@ typedef struct ramctr_timing_st {
int reg_c14_offset;
int reg_320c_range_threshold;
int ecc_supported;
int ecc_forced;
int edge_offset[3];
int timC_offset[3];
@ -186,4 +188,7 @@ int try_init_dram_ddr3_sandy(ramctr_timing *ctrl, int fast_boot,
int try_init_dram_ddr3_ivy(ramctr_timing *ctrl, int fast_boot,
int s3_resume, int me_uma_size);
size_t get_host_ecc_cap(void);
size_t get_host_ecc_mode(void);
#endif