DIRTY COMMIT

Change-Id: I3df8449222317d2d8923606dba5c366b9d40e372

src/cpu/intel/model_206ax/bootblock.c

@@ -28,25 +28,24 @@
 #error "CPU must be paired with Intel BD82X6X or C216 southbridge"
 #endif
 
-static void set_flex_ratio_to_tdp_nominal(void)
+static int set_flex_ratio_to_tdp_nominal(void)
 {
 	msr_t flex_ratio, msr;
-	u32 soft_reset;
 	u8 nominal_ratio;
 
 	/* Minimum CPU revision for configurable TDP support */
 	if (cpuid_eax(1) < IVB_CONFIG_TDP_MIN_CPUID)
-		return;
+		return 0;
 
 	/* Check for Flex Ratio support */
 	flex_ratio = rdmsr(MSR_FLEX_RATIO);
 	if (!(flex_ratio.lo & FLEX_RATIO_EN))
-		return;
+		return 0;
 
 	/* Check for >0 configurable TDPs */
 	msr = rdmsr(MSR_PLATFORM_INFO);
 	if (((msr.hi >> 1) & 3) == 0)
-		return;
+		return 0;
 
 	/* Use nominal TDP ratio for flex ratio */
 	msr = rdmsr(MSR_CONFIG_TDP_NOMINAL);
@@ -54,7 +53,7 @@ static void set_flex_ratio_to_tdp_nominal(void)
 
 	/* See if flex ratio is already set to nominal TDP ratio */
 	if (((flex_ratio.lo >> 8) & 0xff) == nominal_ratio)
-		return;
+		return 0;
 
 	/* Set flex ratio to nominal TDP ratio */
 	flex_ratio.lo &= ~0xff00;
@@ -69,6 +68,30 @@ static void set_flex_ratio_to_tdp_nominal(void)
 	soft_reset |= (nominal_ratio & 0x3f) << 6;
 	RCBA32(SOFT_RESET_DATA) = soft_reset;
 
+	return 1;
+}
+
+static int set_others() {
+	u32 soft_reset;
+	
+	soft_reset = RCBA32(SOFT_RESET_DATA);
+	if (soft_reset == 0x000005c5)
+		return 0;
+	return 1;
+}
+
+static void set_soft_data_reset(void)
+{
+	int changed = 0;
+
+	if (set_flex_ratio_to_tdp_nominal())
+		changed = 1;
+	if (set_others())
+		changed = 1;
+
+	if (!changed)
+		return;
+
 	/* Set soft reset control to use register value */
 	RCBA32_OR(SOFT_RESET_CTRL, 1);
 
@@ -81,5 +104,5 @@ static void set_flex_ratio_to_tdp_nominal(void)
 void bootblock_early_cpu_init(void)
 {
 	/* Set flex ratio and reset if needed */
-	set_flex_ratio_to_tdp_nominal();
+	set_soft_data_reset();
 }

src/mainboard/hp/proliant_microserver_gen8/romstage.c

@@ -22,6 +22,8 @@
 #include <northbridge/intel/sandybridge/raminit_native.h>
 #include <device/pci.h>
 #include <device/pci_def.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/bd82x6x/pch.h>
 
 // void mainboard_get_spd(spd_raw_data *spd, bool id_only)
 // {
@@ -50,10 +52,14 @@
 
 void mainboard_early_init(int s3reumse)
 {
-	static u32 ilo0_base = 0x1000;
-	static u32 ilo2_base = 0x1400;
+	u32 ilo0_base = 0x1000;
+	u32 ilo2_base = 0x1400;
 
+	pci_devfn_t dev = PCI_DEV(0, 31, 0);
         pci_devfn_t bridge = PCI_DEV(0, 0x1c, 7);
+        uintptr_t rcba; /* Root Complex Register Block */
+        void *spibase;
+
 
         /* Setup base address on bridge */
         pci_write_config32(bridge, PCI_PRIMARY_BUS, 0x10100);
@@ -100,6 +106,39 @@ void mainboard_early_init(int s3reumse)
 
 	u32 back = pci_read_config32(PCI_DEVFN(0, 0), CAPID0_A);
 	printk(BIOS_ERR, "Reading CAPID0_A back %x\n", back);
+
+	/* check if cpu is configured correctly */
+        rcba = pci_read_config32(dev, RCBA);
+	spibase = (void *)((rcba & 0xffffc000) + 0x3800);
+
+	/* clear Set Stap Lock */
+	clrbits32(spibase + 0xf0, BIT(0));
+	write32(spibase + 0xf8, 0x000005c5);
+
+	/* enable our CPU configuration */
+	setbits32(spibase + 0xf4, BIT(0));
+
+	/* set Set Stap Lock */
+	setbits32(spibase + 0xf0, BIT(0));
+
+
+	printk(BIOS_ERR, "resetting\n");
+        u32 etr3 = pci_read_config32(PCH_LPC_DEV, ETR3);
+
+        /* Clear CF9 Without Resume Well Reset Enable */
+        etr3 &= ~ETR3_CWORWRE;
+
+        /* CF9GR indicates a Global Reset */
+        if (0)
+                etr3 |= ETR3_CF9GR;
+        else
+                etr3 &= ~ETR3_CF9GR;
+
+        pci_write_config32(PCH_LPC_DEV, ETR3, etr3);
+
+        outb(0x0, 0xcf9);
+        outb(0x6, 0xcf9);
+	halt();
 }
 
 void mainboard_get_spd(spd_raw_data *spd, bool id_only)

util/inteltool/spi.c

@@ -60,6 +60,10 @@ static const io_register_t spi_bar_registers[] = {
 	{ 0xc4, 4, "LVSCC - Host Lower Vendor Specific Component Capabilities" },
 	{ 0xc8, 4, "UVSCC - Host Upper Vendor Specific Component Capabilities" },
 	{ 0xd0, 4, "FPB - Flash Partition Boundary" },
+	{ 0xf0, 4, "SRDL - Soft Reset Data Lock Register" },
+	{ 0xf4, 4, "SRDC- Soft Reset Data Control Register" },
+	{ 0xf8, 4, "SRD - Soft Reset Data Register" },
+	{ 0xfc, 4, "UNK - Unknown SPI" },
 };
 
 static const io_register_t ich7_spi_bar_registers[] = {