serial ice before raminit

Change-Id: I9575525764bcd661a90d04d958de556b902386d6

src/northbridge/intel/sandybridge/romstage.c

@@ -31,6 +31,7 @@
 #include <tpm.h>
 #include <northbridge/intel/sandybridge/chip.h>
 #include "southbridge/intel/bd82x6x/pch.h"
+#include <console/serialice.h>
 #include <southbridge/intel/common/gpio.h>
 
 static void early_pch_init(void)
@@ -98,8 +99,12 @@ void mainboard_romstage_entry(unsigned long bist)
 	/* Enable SPD ROMs and DDR-III DRAM */
 	enable_smbus();
 
+    serialice_main();
+
 	post_code(0x39);
 
+    /* serial ice */
+
 	perform_raminit(s3resume);
 
 	timestamp_add_now(TS_AFTER_INITRAM);