flex ratio reset via spi sutf
Change-Id: I6bcdb397b3f967e7dd28aa21018c7f5d50d8be63
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@ -18,25 +18,24 @@
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#error "CPU must be paired with Intel BD82X6X or C216 southbridge"
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#endif
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static void set_flex_ratio_to_tdp_nominal(void)
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static int set_flex_ratio_to_tdp_nominal(void)
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{
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msr_t flex_ratio, msr;
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u32 soft_reset;
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u8 nominal_ratio;
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/* Minimum CPU revision for configurable TDP support */
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if (cpuid_eax(1) < IVB_CONFIG_TDP_MIN_CPUID)
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return;
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return 0;
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/* Check for Flex Ratio support */
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flex_ratio = rdmsr(MSR_FLEX_RATIO);
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if (!(flex_ratio.lo & FLEX_RATIO_EN))
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return;
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return 0;
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/* Check for >0 configurable TDPs */
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msr = rdmsr(MSR_PLATFORM_INFO);
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if (((msr.hi >> 1) & 3) == 0)
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return;
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return 0;
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/* Use nominal TDP ratio for flex ratio */
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msr = rdmsr(MSR_CONFIG_TDP_NOMINAL);
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@ -44,7 +43,7 @@ static void set_flex_ratio_to_tdp_nominal(void)
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/* See if flex ratio is already set to nominal TDP ratio */
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if (((flex_ratio.lo >> 8) & 0xff) == nominal_ratio)
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return;
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return 0;
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/* Set flex ratio to nominal TDP ratio */
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flex_ratio.lo &= ~0xff00;
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@ -59,6 +58,30 @@ static void set_flex_ratio_to_tdp_nominal(void)
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soft_reset |= (nominal_ratio & 0x3f) << 6;
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RCBA32(SOFT_RESET_DATA) = soft_reset;
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return 1;
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}
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static int set_others() {
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u32 soft_reset;
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soft_reset = RCBA32(SOFT_RESET_DATA);
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if (soft_reset == 0x000005c5)
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return 0;
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return 1;
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}
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static void set_soft_data_reset(void)
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{
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int changed = 0;
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if (set_flex_ratio_to_tdp_nominal())
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changed = 1;
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if (set_others())
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changed = 1;
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if (!changed)
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return;
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/* Set soft reset control to use register value */
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RCBA32_OR(SOFT_RESET_CTRL, 1);
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@ -71,5 +94,5 @@ static void set_flex_ratio_to_tdp_nominal(void)
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void bootblock_early_cpu_init(void)
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{
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/* Set flex ratio and reset if needed */
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set_flex_ratio_to_tdp_nominal();
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set_soft_data_reset();
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}
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@ -22,6 +22,8 @@
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#include <northbridge/intel/sandybridge/raminit_native.h>
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#include <device/pci.h>
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#include <device/pci_def.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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// void mainboard_get_spd(spd_raw_data *spd, bool id_only)
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// {
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@ -50,10 +52,14 @@
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void mainboard_early_init(int s3reumse)
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{
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static u32 ilo0_base = 0x1000;
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static u32 ilo2_base = 0x1400;
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u32 ilo0_base = 0x1000;
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u32 ilo2_base = 0x1400;
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pci_devfn_t dev = PCI_DEV(0, 31, 0);
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pci_devfn_t bridge = PCI_DEV(0, 0x1c, 7);
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uintptr_t rcba; /* Root Complex Register Block */
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void *spibase;
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/* Setup base address on bridge */
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pci_write_config32(bridge, PCI_PRIMARY_BUS, 0x10100);
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@ -100,6 +106,39 @@ void mainboard_early_init(int s3reumse)
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u32 back = pci_read_config32(PCI_DEVFN(0, 0), CAPID0_A);
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printk(BIOS_ERR, "Reading CAPID0_A back %x\n", back);
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/* check if cpu is configured correctly */
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rcba = pci_read_config32(dev, RCBA);
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spibase = (void *)((rcba & 0xffffc000) + 0x3800);
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/* clear Set Stap Lock */
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clrbits32(spibase + 0xf0, BIT(0));
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write32(spibase + 0xf8, 0x000005c5);
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/* enable our CPU configuration */
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setbits32(spibase + 0xf4, BIT(0));
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/* set Set Stap Lock */
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setbits32(spibase + 0xf0, BIT(0));
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printk(BIOS_ERR, "resetting\n");
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u32 etr3 = pci_read_config32(PCH_LPC_DEV, ETR3);
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/* Clear CF9 Without Resume Well Reset Enable */
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etr3 &= ~ETR3_CWORWRE;
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/* CF9GR indicates a Global Reset */
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if (0)
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etr3 |= ETR3_CF9GR;
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else
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etr3 &= ~ETR3_CF9GR;
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pci_write_config32(PCH_LPC_DEV, ETR3, etr3);
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outb(0x0, 0xcf9);
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outb(0x6, 0xcf9);
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halt();
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}
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void mainboard_get_spd(spd_raw_data *spd, bool id_only)
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