AGESA vendorcode: Add ENABLE_MRC_CACHE option

When selected, try to store and restore memory training
results from/to SPI flash. This change only pulls in
the required parts from vendorcode for the build.

Change-Id: I12880237be494c71e1d4836abd2d4b714ba87762
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/cpu/amd/agesa/Kconfig

@@ -72,6 +72,14 @@ config DCACHE_RAM_SIZE
 	hex
 	default 0x10000
 
+config ENABLE_MRC_CACHE
+	bool "Use cached memory configuration"
+	default n
+	select SPI_FLASH
+	help
+	  Try to restore memory training results
+	  from non-volatile memory.
+
 config S3_DATA_POS
 	hex
 	default 0xFFFF0000

src/vendorcode/amd/agesa/common/agesa-entry-cfg.h

@@ -24,7 +24,9 @@
 
 #define AGESA_ENTRY_INIT_MID		TRUE
 #define AGESA_ENTRY_INIT_LATE		TRUE
-#define AGESA_ENTRY_INIT_S3SAVE 	IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
+#define AGESA_ENTRY_INIT_S3SAVE \
+		(IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) || \
+		 IS_ENABLED(CONFIG_ENABLE_MRC_CACHE))
 
 #endif