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google/kahlee: Add mainboard GPIOs to ACPI 

Add the Google mainboard GPIOs to the ACPI table.

Change-Id: I9b5952ed3934b938cb50650890a7b434e6306fd1
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/20313
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Marc Jones 2017-06-22 22:22:20 -06:00 committed by Martin Roth
parent 8ab105d490
commit 0a15ed57c6
2 changed files with 17 additions and 1 deletions
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15
src/mainboard/google/kahlee/chromeos.c
View File

@ -18,7 +18,10 @@
#include <vendorcode/google/chromeos/chromeos.h>
#include <boot/coreboot_tables.h>
#include <console/console.h>
#include <soc/gpio.h>
/* SPI Write protect */
#define CROS_WP_GPIO GPIO_122
void fill_lb_gpios(struct lb_gpios *gpios)
{
@ -33,5 +36,15 @@ void fill_lb_gpios(struct lb_gpios *gpios)
int get_write_protect_state(void)
{
return 0;
return gpio_get(CROS_WP_GPIO);
}
static const struct cros_gpio cros_gpios[] = {
CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
CROS_GPIO_WP_AH(CROS_WP_GPIO, CROS_GPIO_DEVICE_NAME),
};
void mainboard_chromeos_acpi_generate(void)
{
chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
}

3
src/mainboard/google/kahlee/mainboard.c
View File

@ -19,6 +19,7 @@
#include <agesawrapper.h>
#include <amd_pci_util.h>
#include <ec.h>
#include <vendorcode/google/chromeos/chromeos.h>
/***********************************************************
* These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
@ -91,6 +92,8 @@ static void kahlee_enable(device_t dev)
/* Initialize the PIRQ data structures for consumption */
pirq_setup();
dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
}
struct chip_operations mainboard_ops = {