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SPD mux
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                      SP5100
                  GPIO 60 GPIO 59
Disabled             0       0
Normal operation     0       1
CPU 0 SPD            1       0
CPU 1 SPD            1       1

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W83795
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Sensor mappings:
CPU_FAN1:  FAN1
CPU_FAN2:  FAN2
FRNT_FAN1: FAN3
FRNT_FAN2: FAN4
FRNT_FAN3: FAN5
FRNT_FAN4: FAN6
FRNT_FAN5: FAN7
REAR_FAN1: FAN8

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Other hardware
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RECOVERY1 middle pin is connected to southbridge (AMD SP5100) GPIO 61
Normal is HIGH, recovery is LOW.

+12VSB is generated using a charge pump attached to pin 7 of PU24 (APW7145).

The +12VSB standby voltage to each bank of DIMMs is switched by a bank of small FETs located close to each RAM power regulator control chip.
The +12V primary voltage (lower left pin of the FET placed on the upper left of the control chip of the second node) is also connected to the 232GE located near the PCI slot.

The control line running to the gates of the +12VSB control FETs is connected to the +5VSB power for the USB ports.
That line in turn is connected to +5VSB via the lone P06P03G PMOS transistor on the reverse side of the board, near the center on the lower half.
The gate of that transistor is connected via a resistor to the source of the P06P03G PMOS transistor located adjacent to the unpopulated SMA clock header.
The gate of that transistor is connected directly to the drain of the small FET directly below it.
After that, there's a cascade of small FETs and resistors in that region, eventually leading to SuperIO pin 81.

SuperIO pin 81 (VSBGATE#) enables the standby voltage rails when set LOW.
VSBGATE# is reset on every assertion of PWRGOOD.

Setting SuperIO LDN 9 CRF4 bits 1 or 0 (or both) to 0 disables NICB.
