mirror of https://review.coreboot.org/fsp.git
Coffee Lake FSP 7.0.68.40
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@ -428,7 +428,8 @@ StructDef
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$gPlatformFspPkgTokenSpaceGuid_MrcTrainOnWarm 1 bytes $_DEFAULT_ = 0x0
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$gPlatformFspPkgTokenSpaceGuid_LpddrDramOdt 1 bytes $_DEFAULT_ = 0x2
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$gPlatformFspPkgTokenSpaceGuid_Ddr4SkipRefreshEn 1 bytes $_DEFAULT_ = 0x1
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Skip 11 bytes
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$gPlatformFspPkgTokenSpaceGuid_LctRelaxedReset 1 bytes $_DEFAULT_ = 0x0
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Skip 10 bytes
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$gPlatformFspPkgTokenSpaceGuid_SkipExtGfxScan 1 bytes $_DEFAULT_ = 0x0
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$gPlatformFspPkgTokenSpaceGuid_BdatEnable 1 bytes $_DEFAULT_ = 0x00
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$gPlatformFspPkgTokenSpaceGuid_ScanExtGfxForLegacyOpRom 1 bytes $_DEFAULT_ = 0x01
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@ -513,7 +514,8 @@ StructDef
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$gPlatformFspPkgTokenSpaceGuid_GraphicsConfigPtr 4 bytes $_DEFAULT_ = 0x00000000
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$gPlatformFspPkgTokenSpaceGuid_Device4Enable 1 bytes $_DEFAULT_ = 0x00
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$gPlatformFspPkgTokenSpaceGuid_PchHdaDspEnable 1 bytes $_DEFAULT_ = 0x01
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Skip 3 bytes
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$gPlatformFspPkgTokenSpaceGuid_ScsSdCardWpPinEnabled 1 bytes $_DEFAULT_ = 0x01
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Skip 2 bytes
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$gPlatformFspPkgTokenSpaceGuid_ScsEmmcEnabled 1 bytes $_DEFAULT_ = 0x01
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$gPlatformFspPkgTokenSpaceGuid_ScsEmmcHs400Enabled 1 bytes $_DEFAULT_ = 0x01
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$gPlatformFspPkgTokenSpaceGuid_ScsSdCardEnabled 1 bytes $_DEFAULT_ = 0x01
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@ -1659,6 +1661,11 @@ List &gPlatformFspPkgTokenSpaceGuid_Peg1MaxLinkWidth
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Selection 3 , "x4"
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EndList
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List &gPlatformFspPkgTokenSpaceGuid_LctRelaxedReset
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Selection 0 , "Disable"
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Selection 1 , "Enable"
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EndList
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List &gPlatformFspPkgTokenSpaceGuid_EdramTestMode
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Selection 0 , " EDRAM SW disable"
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Selection 1 , " EDRAM SW Enable"
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@ -2493,6 +2500,8 @@ Page "Memory Reference Code 1"
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Help "Override Enable/Disable for the ODT logic for LPDDR3 memory. Default is 2 (AUTO)"
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Combo $gPlatformFspPkgTokenSpaceGuid_Ddr4SkipRefreshEn, "DDR4 Skip Refresh Enable", &gPlatformFspPkgTokenSpaceGuid_Ddr4SkipRefreshEn,
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Help "Enable/Disable of DDR4 Temperature Controlled Refresh on DRAM. Default is 1 (Enabled)"
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Combo $gPlatformFspPkgTokenSpaceGuid_LctRelaxedReset, "Late Command Training Relaxed Reset", &gPlatformFspPkgTokenSpaceGuid_LctRelaxedReset,
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Help "Enable/Disable Relaxed JEDEC Reset during Late Command Training (Only for DDR4)"
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Combo $gPlatformFspPkgTokenSpaceGuid_SkipExtGfxScan, "Skip external display device scanning", &EN_DIS,
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Help "Enable: Do not scan for external display device, Disable (Default): Scan external display devices"
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Combo $gPlatformFspPkgTokenSpaceGuid_BdatEnable, "Generate BIOS Data ACPI Table", &EN_DIS,
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@ -2953,6 +2962,8 @@ EndPage
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Page "PCH 2"
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Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaDspEnable, "Enable HD Audio DSP", &EN_DIS,
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Help "Enable/disable HD Audio DSP feature."
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Combo $gPlatformFspPkgTokenSpaceGuid_ScsSdCardWpPinEnabled, "Enable Write Protect SD Card Pin", &EN_DIS,
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Help "Enable/disable Write Protect SD Card Pin."
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Combo $gPlatformFspPkgTokenSpaceGuid_ScsEmmcEnabled, "Enable eMMC Controller", &EN_DIS,
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Help "Enable/disable eMMC Controller."
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Combo $gPlatformFspPkgTokenSpaceGuid_ScsEmmcHs400Enabled, "Enable eMMC HS400 Mode", &EN_DIS,
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@ -0,0 +1,10 @@
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## @file
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# FSP description for DynamicEx PCDs.
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#
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# @copyright
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# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
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#
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# SPDX-License-Identifier: BSD-2-Clause-Patent
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#
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# @par Specification
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##
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@ -2333,9 +2333,15 @@ typedef struct {
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**/
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UINT8 Ddr4SkipRefreshEn;
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/** Offset 0x0519
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/** Offset 0x0519 - Late Command Training Relaxed Reset
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Enable/Disable Relaxed JEDEC Reset during Late Command Training (Only for DDR4)
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0:Disable, 1:Enable
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**/
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UINT8 ReservedFspmUpd[6];
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UINT8 LctRelaxedReset;
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/** Offset 0x051A
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**/
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UINT8 ReservedFspmUpd[5];
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} FSP_M_CONFIG;
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/** Fsp M Test Configuration
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@ -91,9 +91,15 @@ typedef struct {
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**/
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UINT8 PchHdaDspEnable;
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/** Offset 0x002E
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/** Offset 0x002E - Enable Write Protect SD Card Pin
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Enable/disable Write Protect SD Card Pin.
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$EN_DIS
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**/
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UINT8 UnusedUpdSpace0[3];
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UINT8 ScsSdCardWpPinEnabled;
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/** Offset 0x002F
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**/
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UINT8 UnusedUpdSpace0[2];
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/** Offset 0x0031 - Enable eMMC Controller
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Enable/disable eMMC Controller.
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