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Merge branch 'master' of https://github.com/intel/FSP

This commit is contained in:
Swee Ching Lim 2024-03-27 09:06:23 +08:00
parent aada6a55e1 61c069aa80
commit e5ceb0ba7a
43 changed files with 78892 additions and 961 deletions
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77
AlderLakeFspBinPkg/IoT/AlderLakeP/Fsp.bsf
View File

@ -336,7 +336,7 @@ StructDef
$gPlatformFspPkgTokenSpaceGuid_RingDownBin 1 bytes $_DEFAULT_ = 0x01
$gPlatformFspPkgTokenSpaceGuid_RingVoltageMode 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_TjMaxOffset 1 bytes $_DEFAULT_ = 0x00
Skip 1 bytes
$gPlatformFspPkgTokenSpaceGuid_FastThrottleThreshold 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_RingVoltageOverride 2 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_RingVoltageAdaptive 2 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_RingVoltageOffset 2 bytes $_DEFAULT_ = 0x00
@ -386,10 +386,10 @@ StructDef
$gPlatformFspPkgTokenSpaceGuid_SiSkipOverrideBootModeWhenFwUpdate 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_TscDisableHwFixup 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_IaIccUnlimitedMode 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_IaIccMax 2 bytes $_DEFAULT_ = 0x04
$gPlatformFspPkgTokenSpaceGuid_IaIccMax 2 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_GtIccUnlimitedMode 1 bytes $_DEFAULT_ = 0x00
Skip 1 bytes
$gPlatformFspPkgTokenSpaceGuid_GtIccMax 2 bytes $_DEFAULT_ = 0x04
$gPlatformFspPkgTokenSpaceGuid_GtIccMax 2 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_TvbDownBinsTempThreshold0 1 bytes $_DEFAULT_ = 0x01
$gPlatformFspPkgTokenSpaceGuid_TvbTempThreshold0 1 bytes $_DEFAULT_ = 0x46
$gPlatformFspPkgTokenSpaceGuid_TvbTempThreshold1 1 bytes $_DEFAULT_ = 0x64
@ -457,7 +457,7 @@ StructDef
Skip 7 bytes
$gPlatformFspPkgTokenSpaceGuid_SmbusArpEnable 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_PchNumRsvdSmbusAddresses 1 bytes $_DEFAULT_ = 0x00
Skip 1 bytes
$gPlatformFspPkgTokenSpaceGuid_PcieRefPllSsc 1 bytes $_DEFAULT_ = 0xFF
$gPlatformFspPkgTokenSpaceGuid_PchSmbusIoBase 2 bytes $_DEFAULT_ = 0xEFA0
$gPlatformFspPkgTokenSpaceGuid_PchSmbAlertEnable 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_PcieClkSrcUsage 18 bytes $_DEFAULT_ = 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF
@ -682,7 +682,8 @@ StructDef
$gPlatformFspPkgTokenSpaceGuid_PegGen3Rsvd 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_PanelPowerEnable 1 bytes $_DEFAULT_ = 0x01
$gPlatformFspPkgTokenSpaceGuid_BdatTestType 1 bytes $_DEFAULT_ = 0x00
Skip 3 bytes
$gPlatformFspPkgTokenSpaceGuid_DRAMEMPHASIS 1 bytes $_DEFAULT_ = 0x00
Skip 2 bytes
$gPlatformFspPkgTokenSpaceGuid_DmaBufferSize 4 bytes $_DEFAULT_ = 0x0400000
$gPlatformFspPkgTokenSpaceGuid_PreBootDmaMask 1 bytes $_DEFAULT_ = 0x0
Skip 1 bytes
@ -735,7 +736,9 @@ StructDef
$gPlatformFspPkgTokenSpaceGuid_DmiCdrRelock 1 bytes $_DEFAULT_ = 0x0
$gPlatformFspPkgTokenSpaceGuid_IbeccErrInjControl 1 bytes $_DEFAULT_ = 0x0
$gPlatformFspPkgTokenSpaceGuid_CpuPcieRpSlotImplemented 4 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01
Skip 6 bytes
$gPlatformFspPkgTokenSpaceGuid_PprRunOnce 1 bytes $_DEFAULT_ = 0x01
$gPlatformFspPkgTokenSpaceGuid_PPR 1 bytes $_DEFAULT_ = 0x00
Skip 4 bytes
$gPlatformFspPkgTokenSpaceGuid_IbeccErrInjAddress 8 bytes $_DEFAULT_ = 0x0
$gPlatformFspPkgTokenSpaceGuid_IbeccErrInjMask 8 bytes $_DEFAULT_ = 0x0
$gPlatformFspPkgTokenSpaceGuid_IbeccErrInjCount 4 bytes $_DEFAULT_ = 0x0
@ -782,8 +785,10 @@ StructDef
$gPlatformFspPkgTokenSpaceGuid_CsPiStartHighinEct 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_UserPowerWeightsEn 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_DisableFGRAndPBRWA 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_McParity 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_IbeccParity 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_McParity 1 bytes $_DEFAULT_ = 0x01
$gPlatformFspPkgTokenSpaceGuid_IbeccParity 1 bytes $_DEFAULT_ = 0x01
$gPlatformFspPkgTokenSpaceGuid_LowerBasicMemTestSize 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_DisableSagvReorder 1 bytes $_DEFAULT_ = 0x00
Find "ADLUPD_S"
$gPlatformFspPkgTokenSpaceGuid_Revision 1 bytes $_DEFAULT_ = 0x02
@ -970,10 +975,12 @@ StructDef
$gPlatformFspPkgTokenSpaceGuid_GnaEnable 1 bytes $_DEFAULT_ = 0x1
$gPlatformFspPkgTokenSpaceGuid_IomTypeCPortPadCfg 32 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x06,0x11,0x00,0x04,0x06,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
$gPlatformFspPkgTokenSpaceGuid_CpuUsb3OverCurrentPin 8 bytes $_DEFAULT_ = 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF
$gPlatformFspPkgTokenSpaceGuid_EnTcssUsbOcCurrentCrb 1 bytes $_DEFAULT_ = 0x0
$gPlatformFspPkgTokenSpaceGuid_D3ColdEnable 1 bytes $_DEFAULT_ = 0x01
$gPlatformFspPkgTokenSpaceGuid_ITbtPcieTunnelingForUsb4 1 bytes $_DEFAULT_ = 0x01
$gPlatformFspPkgTokenSpaceGuid_SkipFspGop 1 bytes $_DEFAULT_ = 0x0
$gPlatformFspPkgTokenSpaceGuid_TcCstateLimit 1 bytes $_DEFAULT_ = 0x0A
Skip 3 bytes
$gPlatformFspPkgTokenSpaceGuid_VbtSize 4 bytes $_DEFAULT_ = 0x00000000
$gPlatformFspPkgTokenSpaceGuid_LidStatus 1 bytes $_DEFAULT_ = 0x0
$gPlatformFspPkgTokenSpaceGuid_IomStayInTCColdSeconds 1 bytes $_DEFAULT_ = 0x32
@ -1279,7 +1286,7 @@ StructDef
$gPlatformFspPkgTokenSpaceGuid_CpuRootportUsedForHybridStorage 1 bytes $_DEFAULT_ = 0xFF
$gPlatformFspPkgTokenSpaceGuid_PchRootportUsedForCpuAttach 1 bytes $_DEFAULT_ = 0xFF
$gPlatformFspPkgTokenSpaceGuid_PchAcpiL6dPmeHandling 1 bytes $_DEFAULT_ = 0x0
Skip 5 bytes
Skip 1 bytes
$gPlatformFspPkgTokenSpaceGuid_BgpdtHash 32 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
$gPlatformFspPkgTokenSpaceGuid_BiosGuardAttr 4 bytes $_DEFAULT_ = 0xFFFFFFFF
Skip 4 bytes
@ -1488,7 +1495,9 @@ StructDef
$gPlatformFspPkgTokenSpaceGuid_StepDownMode 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_PlatformAtxTelemetryUnit 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_ProcHotDemotion 1 bytes $_DEFAULT_ = 0x01
$gPlatformFspPkgTokenSpaceGuid_ReservedCpuPostMemTest 13 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_TurboConfiguration 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_EnableHwpScalabilityTracking 1 bytes $_DEFAULT_ = 0x01
$gPlatformFspPkgTokenSpaceGuid_ReservedCpuPostMemTest 11 bytes $_DEFAULT_ = 0x00
Skip 16 bytes
$gPlatformFspPkgTokenSpaceGuid_EndOfPostMessage 1 bytes $_DEFAULT_ = 0x2
$gPlatformFspPkgTokenSpaceGuid_DisableD0I3SettingForHeci 1 bytes $_DEFAULT_ = 0x0
@ -1527,7 +1536,7 @@ StructDef
$gPlatformFspPkgTokenSpaceGuid_CpuPcieRpGen4Uptp 4 bytes $_DEFAULT_ = 0x08, 0x08, 0x08, 0x08
$gPlatformFspPkgTokenSpaceGuid_CpuPcieRpGen4Dptp 4 bytes $_DEFAULT_ = 0x09, 0x09, 0x09, 0x09
$gPlatformFspPkgTokenSpaceGuid_CpuPcieRpGen5Uptp 4 bytes $_DEFAULT_ = 0x07, 0x07, 0x07, 0x07
$gPlatformFspPkgTokenSpaceGuid_CpuPcieRpGen5Dptp 4 bytes $_DEFAULT_ = 0x07, 0x07, 0x07, 0x07
$gPlatformFspPkgTokenSpaceGuid_CpuPcieRpGen5Dptp 4 bytes $_DEFAULT_ = 0x05, 0x05, 0x05, 0x05
$gPlatformFspPkgTokenSpaceGuid_EnableTcssCovTypeA 4 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00
$gPlatformFspPkgTokenSpaceGuid_MappingPchXhciUsbA 4 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00
$gPlatformFspPkgTokenSpaceGuid_CpuPcieFomsCp 4 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00
@ -1576,7 +1585,8 @@ StructDef
$gPlatformFspPkgTokenSpaceGuid_ThcHidReadOpcode 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
$gPlatformFspPkgTokenSpaceGuid_ThcHidWriteOpcode 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
$gPlatformFspPkgTokenSpaceGuid_ThcHidFlags 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
Skip 8 bytes
$gPlatformFspPkgTokenSpaceGuid_CpuPcieRpTestForceLtrOverride 4 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00
Skip 4 bytes
$gPlatformFspPkgTokenSpaceGuid_MemoryBuffer 8 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_L2QosEnumerationEn 1 bytes $_DEFAULT_ = 0x0
Skip 3 bytes
@ -2333,6 +2343,11 @@ List &gPlatformFspPkgTokenSpaceGuid_IbeccErrInjControl
Selection 7 , "Inject Uncorrectable Error on insertion counter"
EndList
List &gPlatformFspPkgTokenSpaceGuid_PprRunOnce
Selection 0 , "Disable"
Selection 1 , "Enable"
EndList
List &gPlatformFspPkgTokenSpaceGuid_Lp5BankMode
Selection 0 , "Auto"
Selection 1 , "8 Bank Mode"
@ -2594,6 +2609,11 @@ List &gPlatformFspPkgTokenSpaceGuid_ThreeStrikeCounterDisable
Selection 1 , " True"
EndList
List &gPlatformFspPkgTokenSpaceGuid_TurboConfiguration
Selection 0 , " Max Transient Turbo"
Selection 1 , " 1.2 X TDP"
EndList
List &gPlatformFspPkgTokenSpaceGuid_EndOfPostMessage
Selection 0 , "Disable"
Selection 1 , "Send in PEI"
@ -3085,12 +3105,12 @@ Page "Memory Reference Code"
Combo $gPlatformFspPkgTokenSpaceGuid_IaIccUnlimitedMode, "Support IA Unlimited ICCMAX", &EN_DIS,
Help "Support IA Unlimited ICCMAX up to maximum value 512A; <b>0: Disabled</b>; 1: Enabled."
EditNum $gPlatformFspPkgTokenSpaceGuid_IaIccMax, "IA ICCMAX", HEX,
Help "IA ICCMAX value is represented in 1/4 A increments. A value of 400 = 100A. <b>4 </b>. Range is 4-2047."
Help "IA ICCMAX value is represented in 1/4 A increments. A value of 400 = 100A. <b>0 (HW default)</b>. Range is 4-2047."
"Valid range: 0x00 ~ 0x7FF"
Combo $gPlatformFspPkgTokenSpaceGuid_GtIccUnlimitedMode, "Support GT Unlimited ICCMAX", &EN_DIS,
Help "Support GT Unlimited ICCMAX up to maximum value 512A; <b>0: Disabled</b>; 1: Enabled."
EditNum $gPlatformFspPkgTokenSpaceGuid_GtIccMax, "GT ICCMAX", HEX,
Help "GT ICCMAX value is represented in 1/4 A increments. A value of 400 = 100A. <b>4 </b>. Range is 4-2047."
Help "GT ICCMAX value is represented in 1/4 A increments. A value of 400 = 100A. <b>0 (HW default)</b>. Range is 4-2047."
"Valid range: 0x00 ~ 0x7FF"
EditNum $gPlatformFspPkgTokenSpaceGuid_TvbDownBinsTempThreshold0, "TVB Down Bins for Temp Threshold 0", DEC,
Help "Down Bins (delta) for Temperature Threshold 0. When running above Temperature Threshold 0, the ratio will be clipped by MAX_RATIO[n]-This value, when TVB ratio clipping is enabled. Default is 1."
@ -3486,6 +3506,8 @@ Page "Memory Reference Code"
Help "Control for enabling/disabling VDD force bit (Required only for early enabling of eDP panel). 0=Disable, 1(Default)=Enable"
Combo $gPlatformFspPkgTokenSpaceGuid_BdatTestType, "BdatTestType", &gPlatformFspPkgTokenSpaceGuid_BdatTestType,
Help "Indicates the type of Memory Training data to populate into the BDAT ACPI table."
Combo $gPlatformFspPkgTokenSpaceGuid_DRAMEMPHASIS, "DRAMEMPHASIS Training", &EN_DIS,
Help "Enable/Disable DRAMEMPHASIS Training"
Combo $gPlatformFspPkgTokenSpaceGuid_ReuseAdlSDdr5Board, "Reuse Adl DDR5 Board or not", &gPlatformFspPkgTokenSpaceGuid_ReuseAdlSDdr5Board,
Help "Indicate whether adl ddr5 board is reused."
Combo $gPlatformFspPkgTokenSpaceGuid_OemT12DelayOverride, "Oem T12 Delay Override", &EN_DIS,
@ -3509,6 +3531,10 @@ Page "Memory Reference Code"
EditNum $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpSlotImplemented, "CPU PCIe root port connection type", HEX,
Help "0: built-in device, 1:slot"
"Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
Combo $gPlatformFspPkgTokenSpaceGuid_PprRunOnce, "Ppr Run Once", &gPlatformFspPkgTokenSpaceGuid_PprRunOnce,
Help "Enable PPR Run Once 0:Disable, <b>1:Enable<b>"
Combo $gPlatformFspPkgTokenSpaceGuid_PPR, "Post Package Repair", &EN_DIS,
Help "Enables/Disable Post Package Repair"
EditNum $gPlatformFspPkgTokenSpaceGuid_IbeccErrInjAddress, "IbeccErrInjAddress", HEX,
Help "Address to match against for ECC error injection"
"Valid range: 0x0 ~ 0x3FFFFFFFFFC0"
@ -3631,9 +3657,13 @@ Page "Memory Reference Code"
Combo $gPlatformFspPkgTokenSpaceGuid_DisableFGRAndPBRWA, "DisableFGRAndPBRWA", &EN_DIS,
Help "Disable FGR And PBR WA: 0(Default)=Disable, 1=Enable"
Combo $gPlatformFspPkgTokenSpaceGuid_McParity, "McParity", &EN_DIS,
Help "CMI/MC Parity Control"
Help "CMI/MC Parity Control: 1(Default)=Enable"
Combo $gPlatformFspPkgTokenSpaceGuid_IbeccParity, "IbeccParity", &EN_DIS,
Help "In-Band ECC Parity Control"
Help "In-Band ECC Parity Control: 1(Default)=Enable"
Combo $gPlatformFspPkgTokenSpaceGuid_LowerBasicMemTestSize, "LowerBasicMemTestSize", &EN_DIS,
Help "Reduce BasicMemoryTest size WA: 0(Default)=Disable, 1=Enable"
Combo $gPlatformFspPkgTokenSpaceGuid_DisableSagvReorder, "DisableSagvReorder", &EN_DIS,
Help "Disable Sagv reorder on warm boot: 0(Default)=Disable, 1=Enable"
EndPage
Page "CPU (Pre-Mem)"
@ -3708,6 +3738,9 @@ Page "CPU (Pre-Mem)"
EditNum $gPlatformFspPkgTokenSpaceGuid_TjMaxOffset, "TjMax Offset", HEX,
Help "TjMax offset.Specified value here is clipped by pCode (125 - TjMax Offset) to support TjMax in the range of 62 to 115 deg Celsius. Valid Range 10 - 63"
"Valid range: 0x0A ~ 0x3F"
EditNum $gPlatformFspPkgTokenSpaceGuid_FastThrottleThreshold, "FastThrottleThreshold", HEX,
Help "FastThrottleThreshold. Specified value for max allowed temperature when cores throttle. Support FastThrottleThreshold in the range of 63 to 115 deg Celsius."
"Valid range: 0x3F ~ 0x73"
EditNum $gPlatformFspPkgTokenSpaceGuid_RingVoltageOverride, "Ring voltage override", HEX,
Help "The ring voltage override which is applied to the entire range of cpu ring frequencies. Valid Range 0 to 2000"
"Valid range: 0x00 ~ 0x7D0"
@ -4269,6 +4302,10 @@ Page "CPU (Post-Mem)"
"Valid range: 0x00 ~ 0x1"
Combo $gPlatformFspPkgTokenSpaceGuid_ProcHotDemotion, "ProcHot Demotion Algorithm configuration", &EN_DIS,
Help "ProcHot Demotion Algorithm configuration. Hardware Default/Disable; 0: Disable;<b> 1: Hardware Default</b>"
Combo $gPlatformFspPkgTokenSpaceGuid_TurboConfiguration, "Turbo Configuration", &gPlatformFspPkgTokenSpaceGuid_TurboConfiguration,
Help "To change the PL2 and Tau. <b>0: Max Transient Turbo;</b> 1: 1.2 X TDP"
Combo $gPlatformFspPkgTokenSpaceGuid_EnableHwpScalabilityTracking, "Enable or Disable HwP Scalability Tracking", &EN_DIS,
Help "Enable or Disable HwP Scalability Tracking. 0: Disable; <b>1: Enable</b>"
Combo $gPlatformFspPkgTokenSpaceGuid_ReservedCpuPostMemTest, "ReservedCpuPostMemTest", &EN_DIS,
Help "Reserved for CPU Post-Mem Test"
EndPage
@ -4716,6 +4753,9 @@ Page "System Agent (Post-Mem)"
EditNum $gPlatformFspPkgTokenSpaceGuid_ThcHidFlags, "Touch Host Controller Hid Over Spi Flags", HEX,
Help "Hid Over Spi Flags 0x0:Single SPI Mode, 0x4000:Dual SPI Mode, 0x8000:Quad SPI Mode"
"Valid range: 0 ~ 0xFFFFFFFFFFFFFFFF"
EditNum $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpTestForceLtrOverride, "Force LTR Override", HEX,
Help "Force LTR Override."
"Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
EditNum $gPlatformFspPkgTokenSpaceGuid_MemoryBuffer, "MemoryBuffer", HEX,
Help "MemoryBuffer address"
"Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF"
@ -4842,12 +4882,15 @@ Page "PCH (Pre-Mem)"
Help "PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting."
"Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF"
Combo $gPlatformFspPkgTokenSpaceGuid_IotgPllSscEn, "Iotg Pll SscEn", &EN_DIS,
Help "Enable or disable CPU SSC. 0: Disable, <b>1: Enable</b>"
Help "<b>@deprecated</b> - Not used and has no effect, Please use Pcie Ref Pll SSC"
Combo $gPlatformFspPkgTokenSpaceGuid_SmbusArpEnable, "Enable SMBus ARP support", &EN_DIS,
Help "Enable SMBus ARP support."
EditNum $gPlatformFspPkgTokenSpaceGuid_PchNumRsvdSmbusAddresses, "Number of RsvdSmbusAddressTable.", HEX,
Help "The number of elements in the RsvdSmbusAddressTable."
"Valid range: 0x00 ~ 0xFF"
EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRefPllSsc, "Pcie Ref Pll SSC", HEX,
Help "Pcie Ref Pll SSC Percentatge. 0x0: 0.0%, 0x1: 0.1%, 0x2:0.2%, 0x3: 0.3%, 0x4: 0.4%, 0x5: 0.5%, 0xFE: Disable, 0xFF: Auto"
"Valid range: 0x00 ~ 0xFF"
EditNum $gPlatformFspPkgTokenSpaceGuid_PchSmbusIoBase, "SMBUS Base Address", HEX,
Help "SMBUS Base Address (IO space)."
"Valid range: 0x00 ~ 0xFFFF"

BIN
AlderLakeFspBinPkg/IoT/AlderLakeP/Fsp.fd
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Binary file not shown.

7
AlderLakeFspBinPkg/IoT/AlderLakeP/Include/FirmwareVersionInfoHob.h
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@ -2,12 +2,9 @@
Header file for Firmware Version Information
@copyright
Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2015 - 2023, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License which accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
SPDX-License-Identifier: BSD-2-Clause-Patent
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

27
AlderLakeFspBinPkg/IoT/AlderLakeP/Include/FspInfoHob.h
View File

@ -2,32 +2,9 @@
Header file for FSP Information HOB.
@copyright
Copyright 2017 - 2023 Intel Corporation.
Copyright (c) 2017 - 2023, Intel Corporation. All rights reserved.<BR>
The source code contained or described herein and all documents related to the
source code ("Material") are owned by Intel Corporation or its suppliers or
licensors. Title to the Material remains with Intel Corporation or its suppliers
and licensors. The Material may contain trade secrets and proprietary and
confidential information of Intel Corporation and its suppliers and licensors,
and is protected by worldwide copyright and trade secret laws and treaty
provisions. No part of the Material may be used, copied, reproduced, modified,
published, uploaded, posted, transmitted, distributed, or disclosed in any way
without Intel's prior express written permission.
No license under any patent, copyright, trade secret or other intellectual
property right is granted to or conferred upon you by disclosure or delivery
of the Materials, either expressly, by implication, inducement, estoppel or
otherwise. Any license under such intellectual property rights must be
express and approved by Intel in writing.
Unless otherwise agreed by Intel in writing, you may not remove or alter
this notice or any other notice embedded in Materials by Intel or
Intel's suppliers or licensors in any way.
This file contains an 'Intel Peripheral Driver' and is uniquely identified as
"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
the terms of your license agreement with Intel or your vendor. This file may
be modified by the user, subject to additional terms of the license agreement.
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Specification Reference:
**/

66
AlderLakeFspBinPkg/IoT/AlderLakeP/Include/FspmUpd.h
View File

@ -1611,9 +1611,11 @@ typedef struct {
**/
UINT8 TjMaxOffset;
/** Offset 0x03D1
/** Offset 0x03D1 - FastThrottleThreshold
FastThrottleThreshold. Specified value for max allowed temperature when cores throttle.
Support FastThrottleThreshold in the range of 63 to 115 deg Celsius.
**/
UINT8 Rsvd09;
UINT8 FastThrottleThreshold;
/** Offset 0x03D2 - Ring voltage override
The ring voltage override which is applied to the entire range of cpu ring frequencies.
@ -1911,8 +1913,8 @@ typedef struct {
UINT8 IaIccUnlimitedMode;
/** Offset 0x04B0 - IA ICCMAX
IA ICCMAX value is represented in 1/4 A increments. A value of 400 = 100A. <b>4
</b>. Range is 4-2047.
IA ICCMAX value is represented in 1/4 A increments. A value of 400 = 100A. <b>0
(HW default)</b>. Range is 4-2047.
**/
UINT16 IaIccMax;
@ -1927,8 +1929,8 @@ typedef struct {
UINT8 Rsvd13;
/** Offset 0x04B4 - GT ICCMAX
GT ICCMAX value is represented in 1/4 A increments. A value of 400 = 100A. <b>4
</b>. Range is 4-2047.
GT ICCMAX value is represented in 1/4 A increments. A value of 400 = 100A. <b>0
(HW default)</b>. Range is 4-2047.
**/
UINT16 GtIccMax;
@ -2272,7 +2274,7 @@ typedef struct {
UINT8 PchPort80Route;
/** Offset 0x0743 - Iotg Pll SscEn
Enable or disable CPU SSC. 0: Disable, <b>1: Enable</b>
<b>@deprecated</b> - Not used and has no effect, Please use Pcie Ref Pll SSC
$EN_DIS
**/
UINT8 IotgPllSscEn;
@ -2292,9 +2294,11 @@ typedef struct {
**/
UINT8 PchNumRsvdSmbusAddresses;
/** Offset 0x074D
/** Offset 0x074D - Pcie Ref Pll SSC
Pcie Ref Pll SSC Percentatge. 0x0: 0.0%, 0x1: 0.1%, 0x2:0.2%, 0x3: 0.3%, 0x4: 0.4%,
0x5: 0.5%, 0xFE: Disable, 0xFF: Auto
**/
UINT8 Rsvd16;
UINT8 PcieRefPllSsc;
/** Offset 0x074E - SMBUS Base Address
SMBUS Base Address (IO space).
@ -3587,9 +3591,15 @@ typedef struct {
**/
UINT8 BdatTestType;
/** Offset 0x0901
/** Offset 0x0901 - DRAMEMPHASIS Training
Enable/Disable DRAMEMPHASIS Training
$EN_DIS
**/
UINT8 Rsvd23[3];
UINT8 DRAMEMPHASIS;
/** Offset 0x0902
**/
UINT8 Rsvd23[2];
/** Offset 0x0904 - PMR Size
Size of PMR memory buffer. 0x400000 for normal boot and 0x200000 for S3 boot
@ -3885,9 +3895,17 @@ typedef struct {
**/
UINT8 CpuPcieRpSlotImplemented[4];
/** Offset 0x0AE2
/** Offset 0x0AE2 - Ppr Run Once
Enable PPR Run Once 0:Disable, <b>1:Enable<b>
0:Disable, 1:Enable
**/
UINT8 Rsvd28[2];
UINT8 PprRunOnce;
/** Offset 0x0AE3 - Post Package Repair
Enables/Disable Post Package Repair
$EN_DIS
**/
UINT8 PPR;
/** Offset 0x0AE4
**/
@ -4154,24 +4172,36 @@ typedef struct {
UINT8 DisableFGRAndPBRWA;
/** Offset 0x0B62 - McParity
CMI/MC Parity Control
CMI/MC Parity Control: 1(Default)=Enable
$EN_DIS
**/
UINT8 McParity;
/** Offset 0x0B63 - IbeccParity
In-Band ECC Parity Control
In-Band ECC Parity Control: 1(Default)=Enable
$EN_DIS
**/
UINT8 IbeccParity;
/** Offset 0x0B64
/** Offset 0x0B64 - LowerBasicMemTestSize
Reduce BasicMemoryTest size WA: 0(Default)=Disable, 1=Enable
$EN_DIS
**/
UINT8 LowerBasicMemTestSize;
/** Offset 0x0B65 - DisableSagvReorder
Disable Sagv reorder on warm boot: 0(Default)=Disable, 1=Enable
$EN_DIS
**/
UINT8 DisableSagvReorder;
/** Offset 0x0B66
**/
UINT8 Rsvd32[4];
/** Offset 0x0B68
/** Offset 0x0B6A
**/
UINT8 UnusedUpdSpace5[4];
UINT8 UnusedUpdSpace5[2];
/** Offset 0x0B6C
**/

668
AlderLakeFspBinPkg/IoT/AlderLakeP/Include/FspsUpd.h
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5
AlderLakeFspBinPkg/IoT/AlderLakeP/Include/MemInfoHob.h
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@ -4,12 +4,13 @@
data hobs.
@copyright
Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>
Copyright (c) 1999 - 2023, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Specification Reference:
**/
#ifndef _MEM_INFO_HOB_H_
#define _MEM_INFO_HOB_H_
@ -276,6 +277,8 @@ typedef struct {
BOOLEAN MemorySpeedReducedWrongDimmSlot; ///< Can be used by OEM BIOS to display a warning on the screen that DDR speed was reduced due to wrong DIMM population
BOOLEAN MemorySpeedReducedMixedConfig; ///< Can be used by OEM BIOS to display a warning on the screen that DDR speed was reduced due to mixed DIMM config
BOOLEAN DynamicMemoryBoostTrainingFailed; ///< TRUE if Dynamic Memory Boost failed to train and was force disabled on the last full training boot. FALSE otherwise.
UINT16 PprDetectedErrors; ///< PPR: Counts of detected bad rows.
UINT16 PprRepairFails; ///< PPR: Counts of repair failure.
} MEMORY_INFO_DATA_HOB;
/**

BIN
AlderLakeFspBinPkg/IoT/AlderLakeP/VBT/VbtAdlP.bin
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900
AlderLakeFspBinPkg/IoT/AlderLakeP/VBT/VbtAdlP.json
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91
AlderLakeFspBinPkg/IoT/AlderLakeS/Fsp.bsf
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@ -2,7 +2,7 @@
Boot Setting File for Platform Configuration.
Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -28,8 +28,8 @@ StructDef
$gPlatformFspPkgTokenSpaceGuid_Revision 1 bytes $_DEFAULT_ = 0x02
Skip 87 bytes
$gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartDebugEnable 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartNumber 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartMode 1 bytes $_DEFAULT_ = 0x01
$gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartNumber 1 bytes $_DEFAULT_ = 0x02
$gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartMode 1 bytes $_DEFAULT_ = 0x02
Skip 1 bytes
$gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartBaudRate 4 bytes $_DEFAULT_ = 115200
$gPlatformFspPkgTokenSpaceGuid_PcdPciExpressBaseAddress 8 bytes $_DEFAULT_ = 0xC0000000
@ -157,7 +157,7 @@ StructDef
$gPlatformFspPkgTokenSpaceGuid_UserBd 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_DisableMrcRetrainingOnRtcPowerLoss 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_DdrFreqLimit 2 bytes $_DEFAULT_ = 0
$gPlatformFspPkgTokenSpaceGuid_SaGv 1 bytes $_DEFAULT_ = 0x05
$gPlatformFspPkgTokenSpaceGuid_SaGv 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_MemTestOnWarmBoot 1 bytes $_DEFAULT_ = 0x01
$gPlatformFspPkgTokenSpaceGuid_DdrSpeedControl 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_RMT 1 bytes $_DEFAULT_ = 0x00
@ -226,7 +226,7 @@ StructDef
$gPlatformFspPkgTokenSpaceGuid_PcieMultipleSegmentEnabled 1 bytes $_DEFAULT_ = 0x0
$gPlatformFspPkgTokenSpaceGuid_SaIpuEnable 1 bytes $_DEFAULT_ = 0x1
$gPlatformFspPkgTokenSpaceGuid_IpuLaneUsed 8 bytes $_DEFAULT_ = 0x04, 0x01, 0x02, 0x04, 0x04, 0x04, 0x00, 0x00
$gPlatformFspPkgTokenSpaceGuid_CsiSpeed 8 bytes $_DEFAULT_ = 0x2, 0x1, 0x2, 0x2, 0x2, 0x2, 0x0, 0x0
$gPlatformFspPkgTokenSpaceGuid_CsiSpeed 8 bytes $_DEFAULT_ = 0x2, 0x2, 0x2, 0x2, 0x2, 0x2, 0x0, 0x0
$gPlatformFspPkgTokenSpaceGuid_ImguClkOutEn 6 bytes $_DEFAULT_ = 0x1, 0x1, 0x1, 0x1, 0x0, 0x0
$gPlatformFspPkgTokenSpaceGuid_CpuPcieRpEnableMask 4 bytes $_DEFAULT_ = 0x0
$gPlatformFspPkgTokenSpaceGuid_CpuPcieRpLinkDownGpios 1 bytes $_DEFAULT_ = 0x0
@ -336,7 +336,7 @@ StructDef
$gPlatformFspPkgTokenSpaceGuid_RingDownBin 1 bytes $_DEFAULT_ = 0x01
$gPlatformFspPkgTokenSpaceGuid_RingVoltageMode 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_TjMaxOffset 1 bytes $_DEFAULT_ = 0x00
Skip 1 bytes
$gPlatformFspPkgTokenSpaceGuid_FastThrottleThreshold 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_RingVoltageOverride 2 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_RingVoltageAdaptive 2 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_RingVoltageOffset 2 bytes $_DEFAULT_ = 0x00
@ -386,10 +386,10 @@ StructDef
$gPlatformFspPkgTokenSpaceGuid_SiSkipOverrideBootModeWhenFwUpdate 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_TscDisableHwFixup 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_IaIccUnlimitedMode 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_IaIccMax 2 bytes $_DEFAULT_ = 0x04
$gPlatformFspPkgTokenSpaceGuid_IaIccMax 2 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_GtIccUnlimitedMode 1 bytes $_DEFAULT_ = 0x00
Skip 1 bytes
$gPlatformFspPkgTokenSpaceGuid_GtIccMax 2 bytes $_DEFAULT_ = 0x04
$gPlatformFspPkgTokenSpaceGuid_GtIccMax 2 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_TvbDownBinsTempThreshold0 1 bytes $_DEFAULT_ = 0x01
$gPlatformFspPkgTokenSpaceGuid_TvbTempThreshold0 1 bytes $_DEFAULT_ = 0x46
$gPlatformFspPkgTokenSpaceGuid_TvbTempThreshold1 1 bytes $_DEFAULT_ = 0x64
@ -457,7 +457,7 @@ StructDef
Skip 7 bytes
$gPlatformFspPkgTokenSpaceGuid_SmbusArpEnable 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_PchNumRsvdSmbusAddresses 1 bytes $_DEFAULT_ = 0x00
Skip 1 bytes
$gPlatformFspPkgTokenSpaceGuid_PcieRefPllSsc 1 bytes $_DEFAULT_ = 0xFF
$gPlatformFspPkgTokenSpaceGuid_PchSmbusIoBase 2 bytes $_DEFAULT_ = 0xEFA0
$gPlatformFspPkgTokenSpaceGuid_PchSmbAlertEnable 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_PcieClkSrcUsage 18 bytes $_DEFAULT_ = 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF
@ -485,7 +485,7 @@ StructDef
$gPlatformFspPkgTokenSpaceGuid_PchHdaIDispCodecDisconnect 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_CnviDdrRfim 1 bytes $_DEFAULT_ = 0x01
$gPlatformFspPkgTokenSpaceGuid_PcdDebugInterfaceFlags 1 bytes $_DEFAULT_ = 0x32
$gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugControllerNumber 1 bytes $_DEFAULT_ = 0x0
$gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugControllerNumber 1 bytes $_DEFAULT_ = 0x2
$gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugAutoFlow 1 bytes $_DEFAULT_ = 0x0
Skip 3 bytes
$gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugBaudRate 4 bytes $_DEFAULT_ = 115200
@ -682,7 +682,8 @@ StructDef
$gPlatformFspPkgTokenSpaceGuid_PegGen3Rsvd 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_PanelPowerEnable 1 bytes $_DEFAULT_ = 0x01
$gPlatformFspPkgTokenSpaceGuid_BdatTestType 1 bytes $_DEFAULT_ = 0x00
Skip 3 bytes
$gPlatformFspPkgTokenSpaceGuid_DRAMEMPHASIS 1 bytes $_DEFAULT_ = 0x00
Skip 2 bytes
$gPlatformFspPkgTokenSpaceGuid_DmaBufferSize 4 bytes $_DEFAULT_ = 0x0400000
$gPlatformFspPkgTokenSpaceGuid_PreBootDmaMask 1 bytes $_DEFAULT_ = 0x0
Skip 1 bytes
@ -711,7 +712,7 @@ StructDef
$gPlatformFspPkgTokenSpaceGuid_CpuPcie3Rtd3Gpio 96 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
$gPlatformFspPkgTokenSpaceGuid_Avx2VoltageScaleFactor 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_Avx512VoltageScaleFactor 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugMode 1 bytes $_DEFAULT_ = 0x01
$gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugMode 1 bytes $_DEFAULT_ = 0x02
Skip 1 bytes
$gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugRxPinMux 4 bytes $_DEFAULT_ = 0x0
$gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugTxPinMux 4 bytes $_DEFAULT_ = 0x0
@ -735,7 +736,9 @@ StructDef
$gPlatformFspPkgTokenSpaceGuid_DmiCdrRelock 1 bytes $_DEFAULT_ = 0x0
$gPlatformFspPkgTokenSpaceGuid_IbeccErrInjControl 1 bytes $_DEFAULT_ = 0x0
$gPlatformFspPkgTokenSpaceGuid_CpuPcieRpSlotImplemented 4 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01
Skip 6 bytes
$gPlatformFspPkgTokenSpaceGuid_PprRunOnce 1 bytes $_DEFAULT_ = 0x01
$gPlatformFspPkgTokenSpaceGuid_PPR 1 bytes $_DEFAULT_ = 0x00
Skip 4 bytes
$gPlatformFspPkgTokenSpaceGuid_IbeccErrInjAddress 8 bytes $_DEFAULT_ = 0x0
$gPlatformFspPkgTokenSpaceGuid_IbeccErrInjMask 8 bytes $_DEFAULT_ = 0x0
$gPlatformFspPkgTokenSpaceGuid_IbeccErrInjCount 4 bytes $_DEFAULT_ = 0x0
@ -782,8 +785,10 @@ StructDef
$gPlatformFspPkgTokenSpaceGuid_CsPiStartHighinEct 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_UserPowerWeightsEn 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_DisableFGRAndPBRWA 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_McParity 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_IbeccParity 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_McParity 1 bytes $_DEFAULT_ = 0x01
$gPlatformFspPkgTokenSpaceGuid_IbeccParity 1 bytes $_DEFAULT_ = 0x01
$gPlatformFspPkgTokenSpaceGuid_LowerBasicMemTestSize 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_DisableSagvReorder 1 bytes $_DEFAULT_ = 0x00
Find "ADLUPD_S"
$gPlatformFspPkgTokenSpaceGuid_Revision 1 bytes $_DEFAULT_ = 0x02
@ -844,7 +849,7 @@ StructDef
$gPlatformFspPkgTokenSpaceGuid_SerialIoUartCtsPinMuxPolicy 28 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
$gPlatformFspPkgTokenSpaceGuid_SerialIoUartRxPinMuxPolicy 28 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
$gPlatformFspPkgTokenSpaceGuid_SerialIoUartTxPinMuxPolicy 28 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
$gPlatformFspPkgTokenSpaceGuid_SerialIoDebugUartNumber 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_SerialIoDebugUartNumber 1 bytes $_DEFAULT_ = 0x02
$gPlatformFspPkgTokenSpaceGuid_SerialIoUartDbg2 7 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
$gPlatformFspPkgTokenSpaceGuid_SerialIoI2cMode 8 bytes $_DEFAULT_ = 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
$gPlatformFspPkgTokenSpaceGuid_PchSerialIoI2cSdaPinMux 32 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
@ -1488,7 +1493,9 @@ StructDef
$gPlatformFspPkgTokenSpaceGuid_StepDownMode 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_PlatformAtxTelemetryUnit 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_ProcHotDemotion 1 bytes $_DEFAULT_ = 0x01
$gPlatformFspPkgTokenSpaceGuid_ReservedCpuPostMemTest 13 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_TurboConfiguration 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_EnableHwpScalabilityTracking 1 bytes $_DEFAULT_ = 0x01
$gPlatformFspPkgTokenSpaceGuid_ReservedCpuPostMemTest 11 bytes $_DEFAULT_ = 0x00
Skip 16 bytes
$gPlatformFspPkgTokenSpaceGuid_EndOfPostMessage 1 bytes $_DEFAULT_ = 0x2
$gPlatformFspPkgTokenSpaceGuid_DisableD0I3SettingForHeci 1 bytes $_DEFAULT_ = 0x0
@ -1513,7 +1520,7 @@ StructDef
$gPlatformFspPkgTokenSpaceGuid_PchPmDisableEnergyReport 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_SataTestMode 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_PchXhciOcLock 1 bytes $_DEFAULT_ = 0x01
$gPlatformFspPkgTokenSpaceGuid_PmcLpmS0ixSubStateEnableMask 1 bytes $_DEFAULT_ = 0x9
$gPlatformFspPkgTokenSpaceGuid_PmcLpmS0ixSubStateEnableMask 1 bytes $_DEFAULT_ = 0x3
$gPlatformFspPkgTokenSpaceGuid_CpuPcieRpLtrMaxSnoopLatency 8 bytes $_DEFAULT_ = 0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10
$gPlatformFspPkgTokenSpaceGuid_CpuPcieRpLtrMaxNoSnoopLatency 8 bytes $_DEFAULT_ = 0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10
$gPlatformFspPkgTokenSpaceGuid_CpuPcieRpSnoopLatencyOverrideMode 4 bytes $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02
@ -1527,7 +1534,7 @@ StructDef
$gPlatformFspPkgTokenSpaceGuid_CpuPcieRpGen4Uptp 4 bytes $_DEFAULT_ = 0x08, 0x08, 0x08, 0x08
$gPlatformFspPkgTokenSpaceGuid_CpuPcieRpGen4Dptp 4 bytes $_DEFAULT_ = 0x09, 0x09, 0x09, 0x09
$gPlatformFspPkgTokenSpaceGuid_CpuPcieRpGen5Uptp 4 bytes $_DEFAULT_ = 0x07, 0x07, 0x07, 0x07
$gPlatformFspPkgTokenSpaceGuid_CpuPcieRpGen5Dptp 4 bytes $_DEFAULT_ = 0x07, 0x07, 0x07, 0x07
$gPlatformFspPkgTokenSpaceGuid_CpuPcieRpGen5Dptp 4 bytes $_DEFAULT_ = 0x05, 0x05, 0x05, 0x05
$gPlatformFspPkgTokenSpaceGuid_EnableTcssCovTypeA 4 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00
$gPlatformFspPkgTokenSpaceGuid_MappingPchXhciUsbA 4 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00
$gPlatformFspPkgTokenSpaceGuid_CpuPcieFomsCp 4 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00
@ -1576,7 +1583,8 @@ StructDef
$gPlatformFspPkgTokenSpaceGuid_ThcHidReadOpcode 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
$gPlatformFspPkgTokenSpaceGuid_ThcHidWriteOpcode 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
$gPlatformFspPkgTokenSpaceGuid_ThcHidFlags 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
Skip 8 bytes
$gPlatformFspPkgTokenSpaceGuid_CpuPcieRpTestForceLtrOverride 4 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00
Skip 4 bytes
$gPlatformFspPkgTokenSpaceGuid_MemoryBuffer 8 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_L2QosEnumerationEn 1 bytes $_DEFAULT_ = 0x0
Skip 3 bytes
@ -2333,6 +2341,11 @@ List &gPlatformFspPkgTokenSpaceGuid_IbeccErrInjControl
Selection 7 , "Inject Uncorrectable Error on insertion counter"
EndList
List &gPlatformFspPkgTokenSpaceGuid_PprRunOnce
Selection 0 , "Disable"
Selection 1 , "Enable"
EndList
List &gPlatformFspPkgTokenSpaceGuid_Lp5BankMode
Selection 0 , "Auto"
Selection 1 , "8 Bank Mode"
@ -2594,6 +2607,11 @@ List &gPlatformFspPkgTokenSpaceGuid_ThreeStrikeCounterDisable
Selection 1 , " True"
EndList
List &gPlatformFspPkgTokenSpaceGuid_TurboConfiguration
Selection 0 , " Max Transient Turbo"
Selection 1 , " 1.2 X TDP"
EndList
List &gPlatformFspPkgTokenSpaceGuid_EndOfPostMessage
Selection 0 , "Disable"
Selection 1 , "Send in PEI"
@ -3085,12 +3103,12 @@ Page "Memory Reference Code"
Combo $gPlatformFspPkgTokenSpaceGuid_IaIccUnlimitedMode, "Support IA Unlimited ICCMAX", &EN_DIS,
Help "Support IA Unlimited ICCMAX up to maximum value 512A; <b>0: Disabled</b>; 1: Enabled."
EditNum $gPlatformFspPkgTokenSpaceGuid_IaIccMax, "IA ICCMAX", HEX,
Help "IA ICCMAX value is represented in 1/4 A increments. A value of 400 = 100A. <b>4 </b>. Range is 4-2047."
Help "IA ICCMAX value is represented in 1/4 A increments. A value of 400 = 100A. <b>0 (HW default)</b>. Range is 4-2047."
"Valid range: 0x00 ~ 0x7FF"
Combo $gPlatformFspPkgTokenSpaceGuid_GtIccUnlimitedMode, "Support GT Unlimited ICCMAX", &EN_DIS,
Help "Support GT Unlimited ICCMAX up to maximum value 512A; <b>0: Disabled</b>; 1: Enabled."
EditNum $gPlatformFspPkgTokenSpaceGuid_GtIccMax, "GT ICCMAX", HEX,
Help "GT ICCMAX value is represented in 1/4 A increments. A value of 400 = 100A. <b>4 </b>. Range is 4-2047."
Help "GT ICCMAX value is represented in 1/4 A increments. A value of 400 = 100A. <b>0 (HW default)</b>. Range is 4-2047."
"Valid range: 0x00 ~ 0x7FF"
EditNum $gPlatformFspPkgTokenSpaceGuid_TvbDownBinsTempThreshold0, "TVB Down Bins for Temp Threshold 0", DEC,
Help "Down Bins (delta) for Temperature Threshold 0. When running above Temperature Threshold 0, the ratio will be clipped by MAX_RATIO[n]-This value, when TVB ratio clipping is enabled. Default is 1."
@ -3486,6 +3504,8 @@ Page "Memory Reference Code"
Help "Control for enabling/disabling VDD force bit (Required only for early enabling of eDP panel). 0=Disable, 1(Default)=Enable"
Combo $gPlatformFspPkgTokenSpaceGuid_BdatTestType, "BdatTestType", &gPlatformFspPkgTokenSpaceGuid_BdatTestType,
Help "Indicates the type of Memory Training data to populate into the BDAT ACPI table."
Combo $gPlatformFspPkgTokenSpaceGuid_DRAMEMPHASIS, "DRAMEMPHASIS Training", &EN_DIS,
Help "Enable/Disable DRAMEMPHASIS Training"
Combo $gPlatformFspPkgTokenSpaceGuid_ReuseAdlSDdr5Board, "Reuse Adl DDR5 Board or not", &gPlatformFspPkgTokenSpaceGuid_ReuseAdlSDdr5Board,
Help "Indicate whether adl ddr5 board is reused."
Combo $gPlatformFspPkgTokenSpaceGuid_OemT12DelayOverride, "Oem T12 Delay Override", &EN_DIS,
@ -3509,6 +3529,10 @@ Page "Memory Reference Code"
EditNum $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpSlotImplemented, "CPU PCIe root port connection type", HEX,
Help "0: built-in device, 1:slot"
"Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
Combo $gPlatformFspPkgTokenSpaceGuid_PprRunOnce, "Ppr Run Once", &gPlatformFspPkgTokenSpaceGuid_PprRunOnce,
Help "Enable PPR Run Once 0:Disable, <b>1:Enable<b>"
Combo $gPlatformFspPkgTokenSpaceGuid_PPR, "Post Package Repair", &EN_DIS,
Help "Enables/Disable Post Package Repair"
EditNum $gPlatformFspPkgTokenSpaceGuid_IbeccErrInjAddress, "IbeccErrInjAddress", HEX,
Help "Address to match against for ECC error injection"
"Valid range: 0x0 ~ 0x3FFFFFFFFFC0"
@ -3631,9 +3655,13 @@ Page "Memory Reference Code"
Combo $gPlatformFspPkgTokenSpaceGuid_DisableFGRAndPBRWA, "DisableFGRAndPBRWA", &EN_DIS,
Help "Disable FGR And PBR WA: 0(Default)=Disable, 1=Enable"
Combo $gPlatformFspPkgTokenSpaceGuid_McParity, "McParity", &EN_DIS,
Help "CMI/MC Parity Control"
Help "CMI/MC Parity Control: 1(Default)=Enable"
Combo $gPlatformFspPkgTokenSpaceGuid_IbeccParity, "IbeccParity", &EN_DIS,
Help "In-Band ECC Parity Control"
Help "In-Band ECC Parity Control: 1(Default)=Enable"
Combo $gPlatformFspPkgTokenSpaceGuid_LowerBasicMemTestSize, "LowerBasicMemTestSize", &EN_DIS,
Help "Reduce BasicMemoryTest size WA: 0(Default)=Disable, 1=Enable"
Combo $gPlatformFspPkgTokenSpaceGuid_DisableSagvReorder, "DisableSagvReorder", &EN_DIS,
Help "Disable Sagv reorder on warm boot: 0(Default)=Disable, 1=Enable"
EndPage
Page "CPU (Pre-Mem)"
@ -3708,6 +3736,9 @@ Page "CPU (Pre-Mem)"
EditNum $gPlatformFspPkgTokenSpaceGuid_TjMaxOffset, "TjMax Offset", HEX,
Help "TjMax offset.Specified value here is clipped by pCode (125 - TjMax Offset) to support TjMax in the range of 62 to 115 deg Celsius. Valid Range 10 - 63"
"Valid range: 0x0A ~ 0x3F"
EditNum $gPlatformFspPkgTokenSpaceGuid_FastThrottleThreshold, "FastThrottleThreshold", HEX,
Help "FastThrottleThreshold. Specified value for max allowed temperature when cores throttle. Support FastThrottleThreshold in the range of 63 to 115 deg Celsius."
"Valid range: 0x3F ~ 0x73"
EditNum $gPlatformFspPkgTokenSpaceGuid_RingVoltageOverride, "Ring voltage override", HEX,
Help "The ring voltage override which is applied to the entire range of cpu ring frequencies. Valid Range 0 to 2000"
"Valid range: 0x00 ~ 0x7D0"
@ -4269,6 +4300,10 @@ Page "CPU (Post-Mem)"
"Valid range: 0x00 ~ 0x1"
Combo $gPlatformFspPkgTokenSpaceGuid_ProcHotDemotion, "ProcHot Demotion Algorithm configuration", &EN_DIS,
Help "ProcHot Demotion Algorithm configuration. Hardware Default/Disable; 0: Disable;<b> 1: Hardware Default</b>"
Combo $gPlatformFspPkgTokenSpaceGuid_TurboConfiguration, "Turbo Configuration", &gPlatformFspPkgTokenSpaceGuid_TurboConfiguration,
Help "To change the PL2 and Tau. <b>0: Max Transient Turbo;</b> 1: 1.2 X TDP"
Combo $gPlatformFspPkgTokenSpaceGuid_EnableHwpScalabilityTracking, "Enable or Disable HwP Scalability Tracking", &EN_DIS,
Help "Enable or Disable HwP Scalability Tracking. 0: Disable; <b>1: Enable</b>"
Combo $gPlatformFspPkgTokenSpaceGuid_ReservedCpuPostMemTest, "ReservedCpuPostMemTest", &EN_DIS,
Help "Reserved for CPU Post-Mem Test"
EndPage
@ -4716,6 +4751,9 @@ Page "System Agent (Post-Mem)"
EditNum $gPlatformFspPkgTokenSpaceGuid_ThcHidFlags, "Touch Host Controller Hid Over Spi Flags", HEX,
Help "Hid Over Spi Flags 0x0:Single SPI Mode, 0x4000:Dual SPI Mode, 0x8000:Quad SPI Mode"
"Valid range: 0 ~ 0xFFFFFFFFFFFFFFFF"
EditNum $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpTestForceLtrOverride, "Force LTR Override", HEX,
Help "Force LTR Override."
"Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
EditNum $gPlatformFspPkgTokenSpaceGuid_MemoryBuffer, "MemoryBuffer", HEX,
Help "MemoryBuffer address"
"Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF"
@ -4842,12 +4880,15 @@ Page "PCH (Pre-Mem)"
Help "PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting."
"Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF"
Combo $gPlatformFspPkgTokenSpaceGuid_IotgPllSscEn, "Iotg Pll SscEn", &EN_DIS,
Help "Enable or disable CPU SSC. 0: Disable, <b>1: Enable</b>"
Help "<b>@deprecated</b> - Not used and has no effect, Please use Pcie Ref Pll SSC"
Combo $gPlatformFspPkgTokenSpaceGuid_SmbusArpEnable, "Enable SMBus ARP support", &EN_DIS,
Help "Enable SMBus ARP support."
EditNum $gPlatformFspPkgTokenSpaceGuid_PchNumRsvdSmbusAddresses, "Number of RsvdSmbusAddressTable.", HEX,
Help "The number of elements in the RsvdSmbusAddressTable."
"Valid range: 0x00 ~ 0xFF"
EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRefPllSsc, "Pcie Ref Pll SSC", HEX,
Help "Pcie Ref Pll SSC Percentatge. 0x0: 0.0%, 0x1: 0.1%, 0x2:0.2%, 0x3: 0.3%, 0x4: 0.4%, 0x5: 0.5%, 0xFE: Disable, 0xFF: Auto"
"Valid range: 0x00 ~ 0xFF"
EditNum $gPlatformFspPkgTokenSpaceGuid_PchSmbusIoBase, "SMBUS Base Address", HEX,
Help "SMBUS Base Address (IO space)."
"Valid range: 0x00 ~ 0xFFFF"

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@ -2,12 +2,9 @@
Header file for Firmware Version Information
@copyright
Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2015 - 2023, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License which accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
SPDX-License-Identifier: BSD-2-Clause-Patent
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

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@ -2,32 +2,9 @@
Header file for FSP Information HOB.
@copyright
Copyright 2017 - 2023 Intel Corporation.
Copyright (c) 2017 - 2023, Intel Corporation. All rights reserved.<BR>
The source code contained or described herein and all documents related to the
source code ("Material") are owned by Intel Corporation or its suppliers or
licensors. Title to the Material remains with Intel Corporation or its suppliers
and licensors. The Material may contain trade secrets and proprietary and
confidential information of Intel Corporation and its suppliers and licensors,
and is protected by worldwide copyright and trade secret laws and treaty
provisions. No part of the Material may be used, copied, reproduced, modified,
published, uploaded, posted, transmitted, distributed, or disclosed in any way
without Intel's prior express written permission.
No license under any patent, copyright, trade secret or other intellectual
property right is granted to or conferred upon you by disclosure or delivery
of the Materials, either expressly, by implication, inducement, estoppel or
otherwise. Any license under such intellectual property rights must be
express and approved by Intel in writing.
Unless otherwise agreed by Intel in writing, you may not remove or alter
this notice or any other notice embedded in Materials by Intel or
Intel's suppliers or licensors in any way.
This file contains an 'Intel Peripheral Driver' and is uniquely identified as
"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
the terms of your license agreement with Intel or your vendor. This file may
be modified by the user, subject to additional terms of the license agreement.
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Specification Reference:
**/

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@ -1,6 +1,6 @@
/** @file
Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:

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@ -1,6 +1,6 @@
/** @file
Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
@ -1611,9 +1611,11 @@ typedef struct {
**/
UINT8 TjMaxOffset;
/** Offset 0x03D1
/** Offset 0x03D1 - FastThrottleThreshold
FastThrottleThreshold. Specified value for max allowed temperature when cores throttle.
Support FastThrottleThreshold in the range of 63 to 115 deg Celsius.
**/
UINT8 Rsvd09;
UINT8 FastThrottleThreshold;
/** Offset 0x03D2 - Ring voltage override
The ring voltage override which is applied to the entire range of cpu ring frequencies.
@ -1911,8 +1913,8 @@ typedef struct {
UINT8 IaIccUnlimitedMode;
/** Offset 0x04B0 - IA ICCMAX
IA ICCMAX value is represented in 1/4 A increments. A value of 400 = 100A. <b>4
</b>. Range is 4-2047.
IA ICCMAX value is represented in 1/4 A increments. A value of 400 = 100A. <b>0
(HW default)</b>. Range is 4-2047.
**/
UINT16 IaIccMax;
@ -1927,8 +1929,8 @@ typedef struct {
UINT8 Rsvd13;
/** Offset 0x04B4 - GT ICCMAX
GT ICCMAX value is represented in 1/4 A increments. A value of 400 = 100A. <b>4
</b>. Range is 4-2047.
GT ICCMAX value is represented in 1/4 A increments. A value of 400 = 100A. <b>0
(HW default)</b>. Range is 4-2047.
**/
UINT16 GtIccMax;
@ -2272,7 +2274,7 @@ typedef struct {
UINT8 PchPort80Route;
/** Offset 0x0743 - Iotg Pll SscEn
Enable or disable CPU SSC. 0: Disable, <b>1: Enable</b>
<b>@deprecated</b> - Not used and has no effect, Please use Pcie Ref Pll SSC
$EN_DIS
**/
UINT8 IotgPllSscEn;
@ -2292,9 +2294,11 @@ typedef struct {
**/
UINT8 PchNumRsvdSmbusAddresses;
/** Offset 0x074D
/** Offset 0x074D - Pcie Ref Pll SSC
Pcie Ref Pll SSC Percentatge. 0x0: 0.0%, 0x1: 0.1%, 0x2:0.2%, 0x3: 0.3%, 0x4: 0.4%,
0x5: 0.5%, 0xFE: Disable, 0xFF: Auto
**/
UINT8 Rsvd16;
UINT8 PcieRefPllSsc;
/** Offset 0x074E - SMBUS Base Address
SMBUS Base Address (IO space).
@ -3587,9 +3591,15 @@ typedef struct {
**/
UINT8 BdatTestType;
/** Offset 0x0901
/** Offset 0x0901 - DRAMEMPHASIS Training
Enable/Disable DRAMEMPHASIS Training
$EN_DIS
**/
UINT8 Rsvd23[3];
UINT8 DRAMEMPHASIS;
/** Offset 0x0902
**/
UINT8 Rsvd23[2];
/** Offset 0x0904 - PMR Size
Size of PMR memory buffer. 0x400000 for normal boot and 0x200000 for S3 boot
@ -3885,9 +3895,17 @@ typedef struct {
**/
UINT8 CpuPcieRpSlotImplemented[4];
/** Offset 0x0AE2
/** Offset 0x0AE2 - Ppr Run Once
Enable PPR Run Once 0:Disable, <b>1:Enable<b>
0:Disable, 1:Enable
**/
UINT8 Rsvd28[2];
UINT8 PprRunOnce;
/** Offset 0x0AE3 - Post Package Repair
Enables/Disable Post Package Repair
$EN_DIS
**/
UINT8 PPR;
/** Offset 0x0AE4
**/
@ -4154,24 +4172,36 @@ typedef struct {
UINT8 DisableFGRAndPBRWA;
/** Offset 0x0B62 - McParity
CMI/MC Parity Control
CMI/MC Parity Control: 1(Default)=Enable
$EN_DIS
**/
UINT8 McParity;
/** Offset 0x0B63 - IbeccParity
In-Band ECC Parity Control
In-Band ECC Parity Control: 1(Default)=Enable
$EN_DIS
**/
UINT8 IbeccParity;
/** Offset 0x0B64
/** Offset 0x0B64 - LowerBasicMemTestSize
Reduce BasicMemoryTest size WA: 0(Default)=Disable, 1=Enable
$EN_DIS
**/
UINT8 LowerBasicMemTestSize;
/** Offset 0x0B65 - DisableSagvReorder
Disable Sagv reorder on warm boot: 0(Default)=Disable, 1=Enable
$EN_DIS
**/
UINT8 DisableSagvReorder;
/** Offset 0x0B66
**/
UINT8 Rsvd32[4];
/** Offset 0x0B68
/** Offset 0x0B6A
**/
UINT8 UnusedUpdSpace5[4];
UINT8 UnusedUpdSpace5[2];
/** Offset 0x0B6C
**/

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@ -1,6 +1,6 @@
/** @file
Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
@ -4161,11 +4161,23 @@ typedef struct {
**/
UINT8 ProcHotDemotion;
/** Offset 0x0DEF - ReservedCpuPostMemTest
/** Offset 0x0DEF - Turbo Configuration
To change the PL2 and Tau. <b>0: Max Transient Turbo;</b> 1: 1.2 X TDP
0: Max Transient Turbo, 1: 1.2 X TDP
**/
UINT8 TurboConfiguration;
/** Offset 0x0DF0 - Enable or Disable HwP Scalability Tracking
Enable or Disable HwP Scalability Tracking. 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 EnableHwpScalabilityTracking;
/** Offset 0x0DF1 - ReservedCpuPostMemTest
Reserved for CPU Post-Mem Test
$EN_DIS
**/
UINT8 ReservedCpuPostMemTest[13];
UINT8 ReservedCpuPostMemTest[11];
/** Offset 0x0DFC
**/
@ -4651,9 +4663,10 @@ typedef struct {
**/
UINT32 ThcHidFlags[2];
/** Offset 0x10E0
/** Offset 0x10E0 - Force LTR Override
Force LTR Override.
**/
UINT8 Rsvd39[4];
UINT8 CpuPcieRpTestForceLtrOverride[4];
/** Offset 0x10E4
**/

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@ -1,6 +1,6 @@
/** @file
Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:

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@ -4,12 +4,13 @@
data hobs.
@copyright
Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>
Copyright (c) 1999 - 2023, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Specification Reference:
**/
#ifndef _MEM_INFO_HOB_H_
#define _MEM_INFO_HOB_H_
@ -276,6 +277,8 @@ typedef struct {
BOOLEAN MemorySpeedReducedWrongDimmSlot; ///< Can be used by OEM BIOS to display a warning on the screen that DDR speed was reduced due to wrong DIMM population
BOOLEAN MemorySpeedReducedMixedConfig; ///< Can be used by OEM BIOS to display a warning on the screen that DDR speed was reduced due to mixed DIMM config
BOOLEAN DynamicMemoryBoostTrainingFailed; ///< TRUE if Dynamic Memory Boost failed to train and was force disabled on the last full training boot. FALSE otherwise.
UINT16 PprDetectedErrors; ///< PPR: Counts of detected bad rows.
UINT16 PprRepairFails; ///< PPR: Counts of repair failure.
} MEMORY_INFO_DATA_HOB;
/**

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@ -0,0 +1,48 @@
/** @file
Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
This file is automatically generated. Please do NOT modify !!!
**/
#ifndef __FSPUPD_H__
#define __FSPUPD_H__
#include <FspEas.h>
#pragma pack(1)
#define FSPT_UPD_SIGNATURE 0x545F4450554C544D /* 'MTLUPD_T' */
#define FSPM_UPD_SIGNATURE 0x4D5F4450554C544D /* 'MTLUPD_M' */
#define FSPS_UPD_SIGNATURE 0x535F4450554C544D /* 'MTLUPD_S' */
#pragma pack()
#endif

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@ -0,0 +1,420 @@
/** @file
Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
This file is automatically generated. Please do NOT modify !!!
**/
#ifndef __FSPTUPD_H__
#define __FSPTUPD_H__
#include <FspUpd.h>
#pragma pack(1)
/** Fsp T Core UPD
**/
typedef struct {
/** Offset 0x0040
**/
UINT32 MicrocodeRegionBase;
/** Offset 0x0044
**/
UINT32 MicrocodeRegionSize;
/** Offset 0x0048
**/
UINT32 CodeRegionBase;
/** Offset 0x004C
**/
UINT32 CodeRegionSize;
/** Offset 0x0050
**/
UINT8 Reserved[16];
} FSPT_CORE_UPD;
/** Fsp T Configuration
**/
typedef struct {
/** Offset 0x0060 - PcdSerialIoUartDebugEnable
Enable SerialIo Uart debug library with/without initializing SerialIo Uart device in FSP.
0:Disable, 1:Enable and Initialize, 2:Enable without Initializing
**/
UINT8 PcdSerialIoUartDebugEnable;
/** Offset 0x0061 - PcdSerialIoUartNumber
Select SerialIo Uart Controller for debug.
0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2
**/
UINT8 PcdSerialIoUartNumber;
/** Offset 0x0062 - PcdSerialIoUartMode - FSPT
Select SerialIo Uart Controller mode
0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom,
4:SerialIoUartSkipInit
**/
UINT8 PcdSerialIoUartMode;
/** Offset 0x0063 - PcdSerialIoUartPowerGating - FSPT
Select SerialIo Uart Controller Powergating mode
0:Disabled, 1:Enabled, 2:Auto
**/
UINT8 PcdSerialIoUartPowerGating;
/** Offset 0x0064 - PcdSerialIoUartBaudRate - FSPT
Set default BaudRate Supported from 0 - default to 6000000
**/
UINT32 PcdSerialIoUartBaudRate;
/** Offset 0x0068 - Pci Express Base Address
Base address to be programmed for Pci Express
**/
UINT64 PcdPciExpressBaseAddress;
/** Offset 0x0070 - Pci Express Region Length
Region Length to be programmed for Pci Express
**/
UINT32 PcdPciExpressRegionLength;
/** Offset 0x0074 - PcdSerialIoUartParity - FSPT
Set default Parity.
0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity
**/
UINT8 PcdSerialIoUartParity;
/** Offset 0x0075 - PcdSerialIoUartDataBits - FSPT
Set default word length. 0: Default, 5,6,7,8
**/
UINT8 PcdSerialIoUartDataBits;
/** Offset 0x0076 - PcdSerialIoUartStopBits - FSPT
Set default stop bits.
0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits
**/
UINT8 PcdSerialIoUartStopBits;
/** Offset 0x0077 - PcdSerialIoUartAutoFlow - FSPT
Enables UART hardware flow control, CTS and RTS lines.
0: Disable, 1:Enable
**/
UINT8 PcdSerialIoUartAutoFlow;
/** Offset 0x0078 - PcdSerialIoUartRxPinMux - FSPT
Select RX pin muxing for SerialIo UART used for debug
**/
UINT32 PcdSerialIoUartRxPinMux;
/** Offset 0x007C - PcdSerialIoUartTxPinMux - FSPT
Select TX pin muxing for SerialIo UART used for debug
**/
UINT32 PcdSerialIoUartTxPinMux;
/** Offset 0x0080 - PcdSerialIoUartRtsPinMux - FSPT
Select SerialIo Uart used for debug Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS*
for possible values.
**/
UINT32 PcdSerialIoUartRtsPinMux;
/** Offset 0x0084 - PcdSerialIoUartCtsPinMux - FSPT
Select SerialIo Uart used for debug Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS*
for possible values.
**/
UINT32 PcdSerialIoUartCtsPinMux;
/** Offset 0x0088 - PcdSerialIoUartDebugMmioBase - FSPT
Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIoUartMode
= SerialIoUartPci.
**/
UINT32 PcdSerialIoUartDebugMmioBase;
/** Offset 0x008C - PcdSerialIoUartDebugPciCfgBase - FSPT
Specify PciCfgBase address. Allows for SerialIO UART functionality outside Bus 0
**/
UINT32 PcdSerialIoUartDebugPciCfgBase;
/** Offset 0x0090 - PcdLpcUartDebugEnable
Enable to initialize LPC Uart device in FSP.
0:Disable, 1:Enable
**/
UINT8 PcdLpcUartDebugEnable;
/** Offset 0x0091 - Debug Interfaces
Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub,
BIT2 - Not used.
**/
UINT8 PcdDebugInterfaceFlags;
/** Offset 0x0092 - PcdSerialDebugLevel
Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load,
Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings,
Info & Verbose.
0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load
Error Warnings and Info, 5:Load Error Warnings Info and Verbose
**/
UINT8 PcdSerialDebugLevel;
/** Offset 0x0093 - ISA Serial Base selection
Select ISA Serial Base address. Default is 0x3F8.
0:0x3F8, 1:0x2F8
**/
UINT8 PcdIsaSerialUartBase;
/** Offset 0x0094 - PcdSerialIo2ndUartEnable
Enable Additional SerialIo Uart device in FSP.
0:Disable, 1:Enable and Initialize, 2:Enable without Initializing
**/
UINT8 PcdSerialIo2ndUartEnable;
/** Offset 0x0095 - PcdSerialIo2ndUartNumber
Select SerialIo Uart Controller Number
0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2
**/
UINT8 PcdSerialIo2ndUartNumber;
/** Offset 0x0096 - PcdSerialIo2ndUartMode - FSPT
Select SerialIo Uart Controller mode
0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom,
4:SerialIoUartSkipInit
**/
UINT8 PcdSerialIo2ndUartMode;
/** Offset 0x0097
**/
UINT8 Rsvd020[1];
/** Offset 0x0098 - PcdSerialIo2ndUartBaudRate - FSPT
Set default BaudRate Supported from 0 - default to 6000000
**/
UINT32 PcdSerialIo2ndUartBaudRate;
/** Offset 0x009C - PcdSerialIo2ndUartParity - FSPT
Set default Parity.
0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity
**/
UINT8 PcdSerialIo2ndUartParity;
/** Offset 0x009D - PcdSerialIo2ndUartDataBits - FSPT
Set default word length. 0: Default, 5,6,7,8
**/
UINT8 PcdSerialIo2ndUartDataBits;
/** Offset 0x009E - PcdSerialIo2ndUartStopBits - FSPT
Set default stop bits.
0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits
**/
UINT8 PcdSerialIo2ndUartStopBits;
/** Offset 0x009F - PcdSerialIo2ndUartAutoFlow - FSPT
Enables UART hardware flow control, CTS and RTS lines.
0: Disable, 1:Enable
**/
UINT8 PcdSerialIo2ndUartAutoFlow;
/** Offset 0x00A0 - PcdSerialIo2ndUartRxPinMux - FSPT
Select RX pin muxing for SerialIo UART
**/
UINT32 PcdSerialIo2ndUartRxPinMux;
/** Offset 0x00A4 - PcdSerialIo2ndUartTxPinMux - FSPT
Select TX pin muxing for SerialIo UART
**/
UINT32 PcdSerialIo2ndUartTxPinMux;
/** Offset 0x00A8 - PcdSerialIo2ndUartRtsPinMux - FSPT
Select SerialIo Uart Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS*
for possible values.
**/
UINT32 PcdSerialIo2ndUartRtsPinMux;
/** Offset 0x00AC - PcdSerialIo2ndUartCtsPinMux - FSPT
Select SerialIo Uart Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS*
for possible values.
**/
UINT32 PcdSerialIo2ndUartCtsPinMux;
/** Offset 0x00B0 - PcdSerialIo2ndUartMmioBase - FSPT
Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIo2ndUartMode
= SerialIoUartPci.
**/
UINT32 PcdSerialIo2ndUartMmioBase;
/** Offset 0x00B4 - PcdSerialIo2ndUartPciCfgBase - FSPT
Specify PciCfgBase address. Allows for SerialIO UART functionality outside Bus 0
**/
UINT32 PcdSerialIo2ndUartPciCfgBase;
/** Offset 0x00B8
**/
UINT32 TopMemoryCacheSize;
/** Offset 0x00BC - FspDebugHandler
<b>Optional</b> pointer to the boot loader's implementation of FSP_DEBUG_HANDLER.
**/
UINT32 FspDebugHandler;
/** Offset 0x00C0 - Serial Io SPI Chip Select Polarity
Sets polarity for each chip Select. Available options: 0:SerialIoSpiCsActiveLow,
1:SerialIoSpiCsActiveHigh
**/
UINT8 PcdSerialIoSpiCsPolarity[2];
/** Offset 0x00C2 - Serial Io SPI Chip Select Enable
0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled
**/
UINT8 PcdSerialIoSpiCsEnable[2];
/** Offset 0x00C4 - Serial Io SPI Device Mode
When mode is set to Pci, controller is initalized in early stage. Available modes:
0:SerialIoSpiDisabled, 1:SerialIoSpiPci.
**/
UINT8 PcdSerialIoSpiMode;
/** Offset 0x00C5 - Serial Io SPI Default Chip Select Output
Sets Default CS as Output. Available options: 0:CS0, 1:CS1
**/
UINT8 PcdSerialIoSpiDefaultCsOutput;
/** Offset 0x00C6 - Serial Io SPI Default Chip Select Mode HW/SW
Sets Default CS Mode Hardware or Software. Available options: 0:HW, 1:SW
**/
UINT8 PcdSerialIoSpiCsMode;
/** Offset 0x00C7 - Serial Io SPI Default Chip Select State Low/High
Sets Default CS State Low or High. Available options: 0:Low, 1:High
**/
UINT8 PcdSerialIoSpiCsState;
/** Offset 0x00C8 - Serial Io SPI Device Number
Select which Serial Io SPI controller is initalized in early stage.
**/
UINT8 PcdSerialIoSpiNumber;
/** Offset 0x00C9
**/
UINT8 Rsvd030[3];
/** Offset 0x00CC - Serial Io SPI Device MMIO Base
Assigns MMIO for Serial Io SPI controller usage in early stage.
**/
UINT32 PcdSerialIoSpiMmioBase;
/** Offset 0x00D0 - Serial IO SPI CS Pin Muxing
Select SerialIo SPI CS pin muxing. Refer to GPIO_*_MUXING_SERIALIO_SPIx_CS* for
possible values.
**/
UINT32 PcdSerialIoSpiCsPinMux[2];
/** Offset 0x00D8 - Serial IO SPI CLK Pin Muxing
Select SerialIo SPI CLK pin muxing. Refer to GPIO_*_MUXING_SERIALIO_SPIx_CLK* for
possible values.
**/
UINT32 PcdSerialIoSpiClkPinMux;
/** Offset 0x00DC - Serial IO SPI MISO Pin Muxing
Select SerialIo SPI MISO pin muxing. Refer to GPIO_*_MUXING_SERIALIO_SPIx_MISO*
for possible values.
**/
UINT32 PcdSerialIoSpiMisoPinMux;
/** Offset 0x00E0 - Serial IO SPI MOSI Pin Muxing
Select SerialIo SPI MOSI pin muxing. Refer to GPIO_*_MUXING_SERIALIO_SPIx_MOSI*
for possible values.
**/
UINT32 PcdSerialIoSpiMosiPinMux;
/** Offset 0x00E4 - Serial Io I2C Device MMIO Base
Assigns MMIO for Serial Io I2C controller usage in early stage.
**/
UINT32 PcdSerialIoI2cMmioBase;
/** Offset 0x00E8 - Serial Io I2C Sda Gpio Pin
Select SerialIo I2C Rts pin. Refer to GPIO_*_MUXING_SERIALIO_I2C*_SDA* for possible values.
**/
UINT32 PcdSerialIoI2cSdaPin;
/** Offset 0x00EC - Serial Io I2C Scl Gpio Pin
Select SerialIo I2C Cts pin. Refer to GPIO_*_MUXING_SERIALIO_I2C*_SCL* for possible values.
**/
UINT32 PcdSerialIoI2cSclPin;
/** Offset 0x00F0 - Serial Io I2C Gpio Pad termination
0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C0,I2C1,... pads termination
respectively. One byte for each controller, byte0 for I2C0, byte1 for I2C1, and so on.
**/
UINT8 PcdSerialIoI2cPadsTerm;
/** Offset 0x00F1 - Serial Io I2c Controller Number
Select SerialIo I2C Controller number to be intilizaed during early boot. Default is 0xFF
0:SerialIoI2c0, 1:SerialIoI2c1, 2:SerialIoI2c2, 0xFF:Disable
**/
UINT8 PcdSerialIoI2cNumber;
/** Offset 0x00F2
**/
UINT8 ReservedFsptUpd1[6];
} FSP_T_CONFIG;
/** Fsp T UPD Configuration
**/
typedef struct {
/** Offset 0x0000
**/
FSP_UPD_HEADER FspUpdHeader;
/** Offset 0x0020
**/
FSPT_ARCH_UPD FsptArchUpd;
/** Offset 0x0040
**/
FSPT_CORE_UPD FsptCoreUpd;
/** Offset 0x0060
**/
FSP_T_CONFIG FsptConfig;
/** Offset 0x00F8
**/
UINT8 Rsvd3[6];
/** Offset 0x00FE
**/
UINT16 UpdTerminator;
} FSPT_UPD;
#pragma pack()
#endif

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/**@file
This file contains definitions required for creation of
Memory S3 Save data, Memory Info data and Memory Platform
data hobs.
Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _MEM_INFO_HOB_H_
#define _MEM_INFO_HOB_H_
#pragma pack (push, 1)
extern EFI_GUID gSiMemoryS3DataGuid;
extern EFI_GUID gSiMemoryInfoDataGuid;
extern EFI_GUID gSiMemoryPlatformDataGuid;
#define MAX_NODE 2
#define MAX_CH 4
#define MAX_DIMM 2
// Must match definitions in
#define HOB_MAX_SAGV_POINTS 4
///
/// Host reset states from MRC.
///
#define WARM_BOOT 2
#define R_MC_CHNL_RANK_PRESENT 0x7C
#define B_RANK0_PRS BIT0
#define B_RANK1_PRS BIT1
#define B_RANK2_PRS BIT4
#define B_RANK3_PRS BIT5
#if !defined(_PEI_HOB_H_) && !defined(__PI_HOB_H__)
#ifndef __HOB__H__
typedef struct _EFI_HOB_GENERIC_HEADER {
UINT16 HobType;
UINT16 HobLength;
UINT32 Reserved;
} EFI_HOB_GENERIC_HEADER;
typedef struct _EFI_HOB_GUID_TYPE {
EFI_HOB_GENERIC_HEADER Header;
EFI_GUID Name;
///
/// Guid specific data goes here
///
} EFI_HOB_GUID_TYPE;
#endif
#endif
//
// Matches MAX_SPD_SAVE define in MRC
//
#ifndef MAX_SPD_SAVE
#define MAX_SPD_SAVE 29
#endif
//
// MRC version description.
//
typedef struct {
UINT8 Major; ///< Major version number
UINT8 Minor; ///< Minor version number
UINT8 Rev; ///< Revision number
UINT8 Build; ///< Build number
} SiMrcVersion;
//
// Matches MrcChannelSts enum in MRC
//
#ifndef CHANNEL_NOT_PRESENT
#define CHANNEL_NOT_PRESENT 0 // There is no channel present on the controller.
#endif
#ifndef CHANNEL_DISABLED
#define CHANNEL_DISABLED 1 // There is a channel present but it is disabled.
#endif
#ifndef CHANNEL_PRESENT
#define CHANNEL_PRESENT 2 // There is a channel present and it is enabled.
#endif
//
// Matches MrcDimmSts enum in MRC
//
#ifndef DIMM_ENABLED
#define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be detected.
#endif
#ifndef DIMM_DISABLED
#define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of presence.
#endif
#ifndef DIMM_PRESENT
#define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pair and it will be used.
#endif
#ifndef DIMM_NOT_PRESENT
#define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank pair.
#endif
//
// Matches MrcBootMode enum in MRC
//
#ifndef __MRC_BOOT_MODE__
#define __MRC_BOOT_MODE__ //The below values are originated from MrcCommonTypes.h
#ifndef INT32_MAX
#define INT32_MAX (0x7FFFFFFF)
#endif //INT32_MAX
typedef enum {
bmCold, ///< Cold boot
bmWarm, ///< Warm boot
bmS3, ///< S3 resume
bmFast, ///< Fast boot
MrcBootModeMax, ///< MRC_BOOT_MODE enumeration maximum value.
MrcBootModeDelim = INT32_MAX ///< This value ensures the enum size is consistent on both sides of the PPI.
} MRC_BOOT_MODE;
#endif //__MRC_BOOT_MODE__
//
// Matches MrcDdrType enum in MRC
//
#ifndef MRC_DDR_TYPE_DDR5
#define MRC_DDR_TYPE_DDR5 1
#endif
#ifndef MRC_DDR_TYPE_LPDDR5
#define MRC_DDR_TYPE_LPDDR5 2
#endif
#ifndef MRC_DDR_TYPE_LPDDR4
#define MRC_DDR_TYPE_LPDDR4 3
#endif
#ifndef MRC_DDR_TYPE_UNKNOWN
#define MRC_DDR_TYPE_UNKNOWN 4
#endif
#define MAX_PROFILE_NUM 4 // number of memory profiles supported
#define MAX_XMP_PROFILE_NUM 2 // number of XMP profiles supported
#define MAX_TRACE_REGION 5
#define MAX_TRACE_CACHE_TYPE 2
//
// DIMM timings
//
typedef struct {
UINT32 tCK; ///< Memory cycle time, in femtoseconds.
UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's command rate mode.
UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS latency.
UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time.
UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time.
UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time.
UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time.
UINT16 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval.
UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
UINT16 tRFCpb; ///< Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time.
UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks.
UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time.
UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups.
UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups.
UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time.
UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time.
UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time.
UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups.
UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups.
UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group.
} MRC_CH_TIMING;
typedef struct {
UINT16 tRDPRE; ///< Read CAS to Precharge cmd delay
} MRC_IP_TIMING;
///
/// Memory SMBIOS & OC Memory Data Hob
///
typedef struct {
UINT8 Status; ///< See MrcDimmStatus for the definition of this field.
UINT8 DimmId;
UINT32 DimmCapacity; ///< DIMM size in MBytes.
UINT16 MfgId;
UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes
UINT8 RankInDimm; ///< The number of ranks in this DIMM.
UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation.
UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation.
UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation.
UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation.
UINT16 Speed; ///< The maximum capable speed of the device, in MHz
UINT8 MdSocket; ///< MdSocket: 0 = Memory Down, 1 = Socketed. Needed for SMBIOS structure creation.
} DIMM_INFO;
typedef struct {
UINT8 Status; ///< Indicates whether this channel should be used.
UINT8 ChannelId;
UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel.
MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values.
DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output characteristics.
} CHANNEL_INFO;
typedef struct {
UINT8 Status; ///< Indicates whether this controller should be used.
UINT16 DeviceId; ///< The PCI device id of this memory controller.
UINT8 RevisionId; ///< The PCI revision id of this memory controller.
UINT8 ChannelCount; ///< Number of valid channels that exist on the controller.
CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions.
} CONTROLLER_INFO;
typedef struct {
UINT64 BaseAddress; ///< Trace Base Address
UINT64 TotalSize; ///< Total Trace Region of Same Cache type
UINT8 CacheType; ///< Trace Cache Type
UINT8 ErrorCode; ///< Trace Region Allocation Fail Error code
UINT8 Rsvd[2];
} PSMI_MEM_INFO;
typedef struct {
UINT32 DataRate; ///< The memory rate for the current SaGv Point in units of MT/s
MRC_CH_TIMING JedecTiming; ///< Timings used for this entry's corresponding SaGv Point - derived from JEDEC SPD spec
MRC_IP_TIMING IpTiming; ///< Timings used for this entry's corresponding SaGv Point - IP specific
} HOB_SAGV_TIMING_OUT;
typedef struct {
UINT32 NumSaGvPointsEnabled; ///< Count of the total number of SAGV Points enabled.
UINT32 SaGvPointMask; ///< Bit mask where each bit indicates an enabled SAGV point.
HOB_SAGV_TIMING_OUT SaGvTiming[HOB_MAX_SAGV_POINTS];
} HOB_SAGV_INFO;
typedef struct {
UINT8 Revision;
UINT16 DataWidth; ///< Data width, in bits, of this memory device
/** As defined in SMBIOS 3.0 spec
Section 7.18.2 and Table 75
**/
UINT8 MemoryType; ///< DDR type: DDR3, DDR4, or LPDDR3
UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz)
UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz)
/** As defined in SMBIOS 3.0 spec
Section 7.17.3 and Table 72
**/
UINT8 ErrorCorrectionType;
SiMrcVersion Version;
BOOLEAN EccSupport;
UINT8 MemoryProfile;
UINT32 TotalPhysicalMemorySize;
UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist.
UINT8 XmpProfileEnable; ///< If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs.
UINT8 XmpConfigWarning; ///< If XMP capable DIMMs config support only 1DPC, but 2DPC is installed
UINT8 Ratio;
UINT8 RefClk;
UINT32 VddVoltage[MAX_PROFILE_NUM];
UINT32 VddqVoltage[MAX_PROFILE_NUM];
UINT32 VppVoltage[MAX_PROFILE_NUM];
CONTROLLER_INFO Controller[MAX_NODE];
UINT16 Ratio_UINT16; ///< DDR Frequency Ratio, used for programs that require ratios higher then 255
UINT32 NumPopulatedChannels; ///< Total number of memory channels populated
HOB_SAGV_INFO SagvConfigInfo; ///< This data structure contains SAGV config values that are considered output by the MRC.
BOOLEAN IsIbeccEnabled;
UINT16 TotalMemWidth; ///< Total Memory Width in bits from all populated channels
} MEMORY_INFO_DATA_HOB;
/**
Memory Platform Data Hob
<b>Revision 1:</b>
- Initial version.
<b>Revision 2:</b>
- Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddress fields
**/
typedef struct {
UINT8 Revision;
UINT8 Reserved[3];
UINT32 BootMode;
UINT32 TsegSize;
UINT32 TsegBase;
UINT32 PrmrrSize;
UINT64 PrmrrBase;
UINT32 GttBase;
UINT32 MmioSize;
UINT32 PciEBaseAddress;
PSMI_MEM_INFO PsmiInfo[MAX_TRACE_CACHE_TYPE];
PSMI_MEM_INFO PsmiRegionInfo[MAX_TRACE_REGION];
BOOLEAN MrcBasicMemoryTestPass;
} MEMORY_PLATFORM_DATA;
typedef struct {
EFI_HOB_GUID_TYPE EfiHobGuidType;
MEMORY_PLATFORM_DATA Data;
UINT8 *Buffer;
} MEMORY_PLATFORM_DATA_HOB;
#pragma pack (pop)
#endif // _MEM_INFO_HOB_H_

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# MeteorLakeFspBinPkg/IoT/MeteorLake
These FSP binaries are intended to be used with IoT SKUs of the Intel® Core™ Ultra Processors for IoT Edge (Formerly known as Meteor Lake-UH and Meteor Lake-PS). Please consult RaptorLakeFspBinPkg/README.md for more information on how to select the correct FSP binary to use.

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# MeteorLakeFspBinPkg/IoT/MeteorLake
These FSP binaries are intended to be used with IoT SKUs of the Intel® Core™ Ultra processors (formerly known as Meteor Lake) platforms. Please consult MeteorLakeFspBinPkg/README.md for more information on how to select the correct FSP binary to use.

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# MeteorLakeFspBinPkg
These FSP binaries are intended to be used Intel® Core™ Ultra Processors Family (Products formerly Meteor Lake).
## Meteor Lake Binary
For descriptions of the Intel® Core™ Ultra Processors Family (Products formerly Meteor Lake) SKU(s). Please consult the table below:
Directory Name | 13th Generation Intel® Core™ (formerly Raptor Lake) SKU Description
:------------- | :-------------------------
IoT/MeteorLake | U/H-Series and PS-Series Embedded processors for IoT and Edge platforms

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@ -2,7 +2,7 @@
Boot Setting File for Platform Configuration.
Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -1583,7 +1583,8 @@ StructDef
$gPlatformFspPkgTokenSpaceGuid_ThcHidReadOpcode 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
$gPlatformFspPkgTokenSpaceGuid_ThcHidWriteOpcode 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
$gPlatformFspPkgTokenSpaceGuid_ThcHidFlags 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
Skip 8 bytes
$gPlatformFspPkgTokenSpaceGuid_CpuPcieRpTestForceLtrOverride 4 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00
Skip 4 bytes
$gPlatformFspPkgTokenSpaceGuid_MemoryBuffer 8 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_L2QosEnumerationEn 1 bytes $_DEFAULT_ = 0x0
Skip 3 bytes
@ -4750,6 +4751,9 @@ Page "System Agent (Post-Mem)"
EditNum $gPlatformFspPkgTokenSpaceGuid_ThcHidFlags, "Touch Host Controller Hid Over Spi Flags", HEX,
Help "Hid Over Spi Flags 0x0:Single SPI Mode, 0x4000:Dual SPI Mode, 0x8000:Quad SPI Mode"
"Valid range: 0 ~ 0xFFFFFFFFFFFFFFFF"
EditNum $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpTestForceLtrOverride, "Force LTR Override", HEX,
Help "Force LTR Override."
"Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
EditNum $gPlatformFspPkgTokenSpaceGuid_MemoryBuffer, "MemoryBuffer", HEX,
Help "MemoryBuffer address"
"Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF"

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@ -2,12 +2,9 @@
Header file for Firmware Version Information
@copyright
Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2015 - 2023, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License which accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
SPDX-License-Identifier: BSD-2-Clause-Patent
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

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@ -2,32 +2,9 @@
Header file for FSP Information HOB.
@copyright
Copyright 2017 - 2023 Intel Corporation.
Copyright (c) 2017 - 2023, Intel Corporation. All rights reserved.<BR>
The source code contained or described herein and all documents related to the
source code ("Material") are owned by Intel Corporation or its suppliers or
licensors. Title to the Material remains with Intel Corporation or its suppliers
and licensors. The Material may contain trade secrets and proprietary and
confidential information of Intel Corporation and its suppliers and licensors,
and is protected by worldwide copyright and trade secret laws and treaty
provisions. No part of the Material may be used, copied, reproduced, modified,
published, uploaded, posted, transmitted, distributed, or disclosed in any way
without Intel's prior express written permission.
No license under any patent, copyright, trade secret or other intellectual
property right is granted to or conferred upon you by disclosure or delivery
of the Materials, either expressly, by implication, inducement, estoppel or
otherwise. Any license under such intellectual property rights must be
express and approved by Intel in writing.
Unless otherwise agreed by Intel in writing, you may not remove or alter
this notice or any other notice embedded in Materials by Intel or
Intel's suppliers or licensors in any way.
This file contains an 'Intel Peripheral Driver' and is uniquely identified as
"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
the terms of your license agreement with Intel or your vendor. This file may
be modified by the user, subject to additional terms of the license agreement.
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Specification Reference:
**/

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/** @file
Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:

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@ -1,6 +1,6 @@
/** @file
Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:

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/** @file
Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
@ -4663,9 +4663,10 @@ typedef struct {
**/
UINT32 ThcHidFlags[2];
/** Offset 0x10E0
/** Offset 0x10E0 - Force LTR Override
Force LTR Override.
**/
UINT8 Rsvd39[4];
UINT8 CpuPcieRpTestForceLtrOverride[4];
/** Offset 0x10E4
**/

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@ -1,6 +1,6 @@
/** @file
Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:

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/** @file
Header file for Firmware Version Information
@copyright
Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _FIRMWARE_VERSION_INFO_HOB_H_
#define _FIRMWARE_VERSION_INFO_HOB_H_
#include <Uefi/UefiMultiPhase.h>
#include <Pi/PiBootMode.h>
#include <Pi/PiHob.h>
#pragma pack(1)
///
/// Firmware Version Structure
///
typedef struct {
UINT8 MajorVersion;
UINT8 MinorVersion;
UINT8 Revision;
UINT16 BuildNumber;
} FIRMWARE_VERSION;
///
/// Firmware Version Information Structure
///
typedef struct {
UINT8 ComponentNameIndex; ///< Offset 0 Index of Component Name
UINT8 VersionStringIndex; ///< Offset 1 Index of Version String
FIRMWARE_VERSION Version; ///< Offset 2-6 Firmware version
} FIRMWARE_VERSION_INFO;
#ifndef __SMBIOS_STANDARD_H__
///
/// The Smbios structure header.
///
typedef struct {
UINT8 Type;
UINT8 Length;
UINT16 Handle;
} SMBIOS_STRUCTURE;
#endif
///
/// Firmware Version Information HOB Structure
///
typedef struct {
EFI_HOB_GUID_TYPE Header; ///< Offset 0-23 The header of FVI HOB
SMBIOS_STRUCTURE SmbiosData; ///< Offset 24-27 The SMBIOS header of FVI HOB
UINT8 Count; ///< Offset 28 Number of FVI elements included.
///
/// FIRMWARE_VERSION_INFO structures followed by the null terminated string buffer
///
} FIRMWARE_VERSION_INFO_HOB;
#pragma pack()
#endif // _FIRMWARE_VERSION_INFO_HOB_H_