mirror of https://review.coreboot.org/fsp.git
IoT MTL-UH & MTL-PS PV (3471_49) FSP
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swong23
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/** @file
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Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
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Redistribution and use in source and binary forms, with or without modification,
|
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are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
* Redistributions in binary form must reproduce the above copyright notice, this
|
||||
list of conditions and the following disclaimer in the documentation and/or
|
||||
other materials provided with the distribution.
|
||||
* Neither the name of Intel Corporation nor the names of its contributors may
|
||||
be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
|
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THE POSSIBILITY OF SUCH DAMAGE.
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This file is automatically generated. Please do NOT modify !!!
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**/
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#ifndef __FSPUPD_H__
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#define __FSPUPD_H__
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#include <FspEas.h>
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#pragma pack(1)
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#define FSPT_UPD_SIGNATURE 0x545F4450554C544D /* 'MTLUPD_T' */
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#define FSPM_UPD_SIGNATURE 0x4D5F4450554C544D /* 'MTLUPD_M' */
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#define FSPS_UPD_SIGNATURE 0x535F4450554C544D /* 'MTLUPD_S' */
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#pragma pack()
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#endif
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/** @file
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Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
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Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
* Redistributions in binary form must reproduce the above copyright notice, this
|
||||
list of conditions and the following disclaimer in the documentation and/or
|
||||
other materials provided with the distribution.
|
||||
* Neither the name of Intel Corporation nor the names of its contributors may
|
||||
be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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THE POSSIBILITY OF SUCH DAMAGE.
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||||
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This file is automatically generated. Please do NOT modify !!!
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**/
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#ifndef __FSPTUPD_H__
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#define __FSPTUPD_H__
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#include <FspUpd.h>
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#pragma pack(1)
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/** Fsp T Core UPD
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**/
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typedef struct {
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/** Offset 0x0040
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**/
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UINT32 MicrocodeRegionBase;
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/** Offset 0x0044
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**/
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UINT32 MicrocodeRegionSize;
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/** Offset 0x0048
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**/
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UINT32 CodeRegionBase;
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/** Offset 0x004C
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**/
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UINT32 CodeRegionSize;
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/** Offset 0x0050
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**/
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UINT8 Reserved[16];
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} FSPT_CORE_UPD;
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/** Fsp T Configuration
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**/
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typedef struct {
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/** Offset 0x0060 - PcdSerialIoUartDebugEnable
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Enable SerialIo Uart debug library with/without initializing SerialIo Uart device in FSP.
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0:Disable, 1:Enable and Initialize, 2:Enable without Initializing
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**/
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UINT8 PcdSerialIoUartDebugEnable;
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/** Offset 0x0061 - PcdSerialIoUartNumber
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Select SerialIo Uart Controller for debug.
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0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2
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**/
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UINT8 PcdSerialIoUartNumber;
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/** Offset 0x0062 - PcdSerialIoUartMode - FSPT
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Select SerialIo Uart Controller mode
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0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom,
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4:SerialIoUartSkipInit
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**/
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UINT8 PcdSerialIoUartMode;
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/** Offset 0x0063 - PcdSerialIoUartPowerGating - FSPT
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Select SerialIo Uart Controller Powergating mode
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0:Disabled, 1:Enabled, 2:Auto
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**/
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UINT8 PcdSerialIoUartPowerGating;
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/** Offset 0x0064 - PcdSerialIoUartBaudRate - FSPT
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Set default BaudRate Supported from 0 - default to 6000000
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**/
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UINT32 PcdSerialIoUartBaudRate;
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/** Offset 0x0068 - Pci Express Base Address
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Base address to be programmed for Pci Express
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**/
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UINT64 PcdPciExpressBaseAddress;
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/** Offset 0x0070 - Pci Express Region Length
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Region Length to be programmed for Pci Express
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**/
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UINT32 PcdPciExpressRegionLength;
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/** Offset 0x0074 - PcdSerialIoUartParity - FSPT
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Set default Parity.
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0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity
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**/
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UINT8 PcdSerialIoUartParity;
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/** Offset 0x0075 - PcdSerialIoUartDataBits - FSPT
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Set default word length. 0: Default, 5,6,7,8
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**/
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UINT8 PcdSerialIoUartDataBits;
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/** Offset 0x0076 - PcdSerialIoUartStopBits - FSPT
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Set default stop bits.
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0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits
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**/
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UINT8 PcdSerialIoUartStopBits;
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/** Offset 0x0077 - PcdSerialIoUartAutoFlow - FSPT
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Enables UART hardware flow control, CTS and RTS lines.
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0: Disable, 1:Enable
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**/
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UINT8 PcdSerialIoUartAutoFlow;
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/** Offset 0x0078 - PcdSerialIoUartRxPinMux - FSPT
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Select RX pin muxing for SerialIo UART used for debug
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**/
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UINT32 PcdSerialIoUartRxPinMux;
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/** Offset 0x007C - PcdSerialIoUartTxPinMux - FSPT
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Select TX pin muxing for SerialIo UART used for debug
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**/
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UINT32 PcdSerialIoUartTxPinMux;
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/** Offset 0x0080 - PcdSerialIoUartRtsPinMux - FSPT
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Select SerialIo Uart used for debug Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS*
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for possible values.
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**/
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UINT32 PcdSerialIoUartRtsPinMux;
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/** Offset 0x0084 - PcdSerialIoUartCtsPinMux - FSPT
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Select SerialIo Uart used for debug Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS*
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for possible values.
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**/
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UINT32 PcdSerialIoUartCtsPinMux;
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/** Offset 0x0088 - PcdSerialIoUartDebugMmioBase - FSPT
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Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIoUartMode
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= SerialIoUartPci.
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**/
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UINT32 PcdSerialIoUartDebugMmioBase;
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/** Offset 0x008C - PcdSerialIoUartDebugPciCfgBase - FSPT
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Specify PciCfgBase address. Allows for SerialIO UART functionality outside Bus 0
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**/
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UINT32 PcdSerialIoUartDebugPciCfgBase;
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/** Offset 0x0090 - PcdLpcUartDebugEnable
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Enable to initialize LPC Uart device in FSP.
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0:Disable, 1:Enable
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**/
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UINT8 PcdLpcUartDebugEnable;
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/** Offset 0x0091 - Debug Interfaces
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Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub,
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BIT2 - Not used.
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**/
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UINT8 PcdDebugInterfaceFlags;
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/** Offset 0x0092 - PcdSerialDebugLevel
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Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load,
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Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings,
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Info & Verbose.
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0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load
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Error Warnings and Info, 5:Load Error Warnings Info and Verbose
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**/
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UINT8 PcdSerialDebugLevel;
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/** Offset 0x0093 - ISA Serial Base selection
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Select ISA Serial Base address. Default is 0x3F8.
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0:0x3F8, 1:0x2F8
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**/
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UINT8 PcdIsaSerialUartBase;
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/** Offset 0x0094 - PcdSerialIo2ndUartEnable
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Enable Additional SerialIo Uart device in FSP.
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0:Disable, 1:Enable and Initialize, 2:Enable without Initializing
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**/
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UINT8 PcdSerialIo2ndUartEnable;
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/** Offset 0x0095 - PcdSerialIo2ndUartNumber
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Select SerialIo Uart Controller Number
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0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2
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**/
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UINT8 PcdSerialIo2ndUartNumber;
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/** Offset 0x0096 - PcdSerialIo2ndUartMode - FSPT
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Select SerialIo Uart Controller mode
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0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom,
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4:SerialIoUartSkipInit
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**/
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UINT8 PcdSerialIo2ndUartMode;
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/** Offset 0x0097
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**/
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UINT8 Rsvd020[1];
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/** Offset 0x0098 - PcdSerialIo2ndUartBaudRate - FSPT
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Set default BaudRate Supported from 0 - default to 6000000
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**/
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UINT32 PcdSerialIo2ndUartBaudRate;
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/** Offset 0x009C - PcdSerialIo2ndUartParity - FSPT
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Set default Parity.
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0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity
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**/
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UINT8 PcdSerialIo2ndUartParity;
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/** Offset 0x009D - PcdSerialIo2ndUartDataBits - FSPT
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Set default word length. 0: Default, 5,6,7,8
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**/
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UINT8 PcdSerialIo2ndUartDataBits;
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/** Offset 0x009E - PcdSerialIo2ndUartStopBits - FSPT
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Set default stop bits.
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0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits
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**/
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UINT8 PcdSerialIo2ndUartStopBits;
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/** Offset 0x009F - PcdSerialIo2ndUartAutoFlow - FSPT
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Enables UART hardware flow control, CTS and RTS lines.
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0: Disable, 1:Enable
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**/
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UINT8 PcdSerialIo2ndUartAutoFlow;
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/** Offset 0x00A0 - PcdSerialIo2ndUartRxPinMux - FSPT
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Select RX pin muxing for SerialIo UART
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**/
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UINT32 PcdSerialIo2ndUartRxPinMux;
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/** Offset 0x00A4 - PcdSerialIo2ndUartTxPinMux - FSPT
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Select TX pin muxing for SerialIo UART
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**/
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UINT32 PcdSerialIo2ndUartTxPinMux;
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/** Offset 0x00A8 - PcdSerialIo2ndUartRtsPinMux - FSPT
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Select SerialIo Uart Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS*
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for possible values.
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**/
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UINT32 PcdSerialIo2ndUartRtsPinMux;
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/** Offset 0x00AC - PcdSerialIo2ndUartCtsPinMux - FSPT
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Select SerialIo Uart Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS*
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for possible values.
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**/
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UINT32 PcdSerialIo2ndUartCtsPinMux;
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/** Offset 0x00B0 - PcdSerialIo2ndUartMmioBase - FSPT
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Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIo2ndUartMode
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= SerialIoUartPci.
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**/
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UINT32 PcdSerialIo2ndUartMmioBase;
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/** Offset 0x00B4 - PcdSerialIo2ndUartPciCfgBase - FSPT
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Specify PciCfgBase address. Allows for SerialIO UART functionality outside Bus 0
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**/
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UINT32 PcdSerialIo2ndUartPciCfgBase;
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/** Offset 0x00B8
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**/
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UINT32 TopMemoryCacheSize;
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/** Offset 0x00BC - FspDebugHandler
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<b>Optional</b> pointer to the boot loader's implementation of FSP_DEBUG_HANDLER.
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**/
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UINT32 FspDebugHandler;
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/** Offset 0x00C0 - Serial Io SPI Chip Select Polarity
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Sets polarity for each chip Select. Available options: 0:SerialIoSpiCsActiveLow,
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1:SerialIoSpiCsActiveHigh
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**/
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UINT8 PcdSerialIoSpiCsPolarity[2];
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/** Offset 0x00C2 - Serial Io SPI Chip Select Enable
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0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled
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**/
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UINT8 PcdSerialIoSpiCsEnable[2];
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/** Offset 0x00C4 - Serial Io SPI Device Mode
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When mode is set to Pci, controller is initalized in early stage. Available modes:
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0:SerialIoSpiDisabled, 1:SerialIoSpiPci.
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**/
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UINT8 PcdSerialIoSpiMode;
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/** Offset 0x00C5 - Serial Io SPI Default Chip Select Output
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Sets Default CS as Output. Available options: 0:CS0, 1:CS1
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**/
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UINT8 PcdSerialIoSpiDefaultCsOutput;
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/** Offset 0x00C6 - Serial Io SPI Default Chip Select Mode HW/SW
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Sets Default CS Mode Hardware or Software. Available options: 0:HW, 1:SW
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**/
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UINT8 PcdSerialIoSpiCsMode;
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/** Offset 0x00C7 - Serial Io SPI Default Chip Select State Low/High
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Sets Default CS State Low or High. Available options: 0:Low, 1:High
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**/
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UINT8 PcdSerialIoSpiCsState;
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/** Offset 0x00C8 - Serial Io SPI Device Number
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Select which Serial Io SPI controller is initalized in early stage.
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**/
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UINT8 PcdSerialIoSpiNumber;
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/** Offset 0x00C9
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**/
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UINT8 Rsvd030[3];
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/** Offset 0x00CC - Serial Io SPI Device MMIO Base
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Assigns MMIO for Serial Io SPI controller usage in early stage.
|
||||
**/
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UINT32 PcdSerialIoSpiMmioBase;
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|
||||
/** Offset 0x00D0 - Serial IO SPI CS Pin Muxing
|
||||
Select SerialIo SPI CS pin muxing. Refer to GPIO_*_MUXING_SERIALIO_SPIx_CS* for
|
||||
possible values.
|
||||
**/
|
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UINT32 PcdSerialIoSpiCsPinMux[2];
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||||
|
||||
/** Offset 0x00D8 - Serial IO SPI CLK Pin Muxing
|
||||
Select SerialIo SPI CLK pin muxing. Refer to GPIO_*_MUXING_SERIALIO_SPIx_CLK* for
|
||||
possible values.
|
||||
**/
|
||||
UINT32 PcdSerialIoSpiClkPinMux;
|
||||
|
||||
/** Offset 0x00DC - Serial IO SPI MISO Pin Muxing
|
||||
Select SerialIo SPI MISO pin muxing. Refer to GPIO_*_MUXING_SERIALIO_SPIx_MISO*
|
||||
for possible values.
|
||||
**/
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UINT32 PcdSerialIoSpiMisoPinMux;
|
||||
|
||||
/** Offset 0x00E0 - Serial IO SPI MOSI Pin Muxing
|
||||
Select SerialIo SPI MOSI pin muxing. Refer to GPIO_*_MUXING_SERIALIO_SPIx_MOSI*
|
||||
for possible values.
|
||||
**/
|
||||
UINT32 PcdSerialIoSpiMosiPinMux;
|
||||
|
||||
/** Offset 0x00E4 - Serial Io I2C Device MMIO Base
|
||||
Assigns MMIO for Serial Io I2C controller usage in early stage.
|
||||
**/
|
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UINT32 PcdSerialIoI2cMmioBase;
|
||||
|
||||
/** Offset 0x00E8 - Serial Io I2C Sda Gpio Pin
|
||||
Select SerialIo I2C Rts pin. Refer to GPIO_*_MUXING_SERIALIO_I2C*_SDA* for possible values.
|
||||
**/
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UINT32 PcdSerialIoI2cSdaPin;
|
||||
|
||||
/** Offset 0x00EC - Serial Io I2C Scl Gpio Pin
|
||||
Select SerialIo I2C Cts pin. Refer to GPIO_*_MUXING_SERIALIO_I2C*_SCL* for possible values.
|
||||
**/
|
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UINT32 PcdSerialIoI2cSclPin;
|
||||
|
||||
/** Offset 0x00F0 - Serial Io I2C Gpio Pad termination
|
||||
0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
|
||||
0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C0,I2C1,... pads termination
|
||||
respectively. One byte for each controller, byte0 for I2C0, byte1 for I2C1, and so on.
|
||||
**/
|
||||
UINT8 PcdSerialIoI2cPadsTerm;
|
||||
|
||||
/** Offset 0x00F1 - Serial Io I2c Controller Number
|
||||
Select SerialIo I2C Controller number to be intilizaed during early boot. Default is 0xFF
|
||||
0:SerialIoI2c0, 1:SerialIoI2c1, 2:SerialIoI2c2, 0xFF:Disable
|
||||
**/
|
||||
UINT8 PcdSerialIoI2cNumber;
|
||||
|
||||
/** Offset 0x00F2
|
||||
**/
|
||||
UINT8 ReservedFsptUpd1[6];
|
||||
} FSP_T_CONFIG;
|
||||
|
||||
/** Fsp T UPD Configuration
|
||||
**/
|
||||
typedef struct {
|
||||
|
||||
/** Offset 0x0000
|
||||
**/
|
||||
FSP_UPD_HEADER FspUpdHeader;
|
||||
|
||||
/** Offset 0x0020
|
||||
**/
|
||||
FSPT_ARCH_UPD FsptArchUpd;
|
||||
|
||||
/** Offset 0x0040
|
||||
**/
|
||||
FSPT_CORE_UPD FsptCoreUpd;
|
||||
|
||||
/** Offset 0x0060
|
||||
**/
|
||||
FSP_T_CONFIG FsptConfig;
|
||||
|
||||
/** Offset 0x00F8
|
||||
**/
|
||||
UINT8 Rsvd3[6];
|
||||
|
||||
/** Offset 0x00FE
|
||||
**/
|
||||
UINT16 UpdTerminator;
|
||||
} FSPT_UPD;
|
||||
|
||||
#pragma pack()
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,290 @@
|
|||
/**@file
|
||||
This file contains definitions required for creation of
|
||||
Memory S3 Save data, Memory Info data and Memory Platform
|
||||
data hobs.
|
||||
|
||||
Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
|
||||
SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||
**/
|
||||
|
||||
#ifndef _MEM_INFO_HOB_H_
|
||||
#define _MEM_INFO_HOB_H_
|
||||
|
||||
#pragma pack (push, 1)
|
||||
|
||||
extern EFI_GUID gSiMemoryS3DataGuid;
|
||||
extern EFI_GUID gSiMemoryInfoDataGuid;
|
||||
extern EFI_GUID gSiMemoryPlatformDataGuid;
|
||||
|
||||
|
||||
#define MAX_NODE 2
|
||||
#define MAX_CH 4
|
||||
#define MAX_DIMM 2
|
||||
// Must match definitions in
|
||||
#define HOB_MAX_SAGV_POINTS 4
|
||||
|
||||
///
|
||||
/// Host reset states from MRC.
|
||||
///
|
||||
#define WARM_BOOT 2
|
||||
|
||||
#define R_MC_CHNL_RANK_PRESENT 0x7C
|
||||
#define B_RANK0_PRS BIT0
|
||||
#define B_RANK1_PRS BIT1
|
||||
#define B_RANK2_PRS BIT4
|
||||
#define B_RANK3_PRS BIT5
|
||||
|
||||
#if !defined(_PEI_HOB_H_) && !defined(__PI_HOB_H__)
|
||||
#ifndef __HOB__H__
|
||||
typedef struct _EFI_HOB_GENERIC_HEADER {
|
||||
UINT16 HobType;
|
||||
UINT16 HobLength;
|
||||
UINT32 Reserved;
|
||||
} EFI_HOB_GENERIC_HEADER;
|
||||
|
||||
typedef struct _EFI_HOB_GUID_TYPE {
|
||||
EFI_HOB_GENERIC_HEADER Header;
|
||||
EFI_GUID Name;
|
||||
///
|
||||
/// Guid specific data goes here
|
||||
///
|
||||
} EFI_HOB_GUID_TYPE;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
//
|
||||
// Matches MAX_SPD_SAVE define in MRC
|
||||
//
|
||||
#ifndef MAX_SPD_SAVE
|
||||
#define MAX_SPD_SAVE 29
|
||||
#endif
|
||||
|
||||
//
|
||||
// MRC version description.
|
||||
//
|
||||
typedef struct {
|
||||
UINT8 Major; ///< Major version number
|
||||
UINT8 Minor; ///< Minor version number
|
||||
UINT8 Rev; ///< Revision number
|
||||
UINT8 Build; ///< Build number
|
||||
} SiMrcVersion;
|
||||
|
||||
//
|
||||
// Matches MrcChannelSts enum in MRC
|
||||
//
|
||||
#ifndef CHANNEL_NOT_PRESENT
|
||||
#define CHANNEL_NOT_PRESENT 0 // There is no channel present on the controller.
|
||||
#endif
|
||||
#ifndef CHANNEL_DISABLED
|
||||
#define CHANNEL_DISABLED 1 // There is a channel present but it is disabled.
|
||||
#endif
|
||||
#ifndef CHANNEL_PRESENT
|
||||
#define CHANNEL_PRESENT 2 // There is a channel present and it is enabled.
|
||||
#endif
|
||||
|
||||
//
|
||||
// Matches MrcDimmSts enum in MRC
|
||||
//
|
||||
#ifndef DIMM_ENABLED
|
||||
#define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be detected.
|
||||
#endif
|
||||
#ifndef DIMM_DISABLED
|
||||
#define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of presence.
|
||||
#endif
|
||||
#ifndef DIMM_PRESENT
|
||||
#define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pair and it will be used.
|
||||
#endif
|
||||
#ifndef DIMM_NOT_PRESENT
|
||||
#define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank pair.
|
||||
#endif
|
||||
|
||||
//
|
||||
// Matches MrcBootMode enum in MRC
|
||||
//
|
||||
#ifndef __MRC_BOOT_MODE__
|
||||
#define __MRC_BOOT_MODE__ //The below values are originated from MrcCommonTypes.h
|
||||
#ifndef INT32_MAX
|
||||
#define INT32_MAX (0x7FFFFFFF)
|
||||
#endif //INT32_MAX
|
||||
typedef enum {
|
||||
bmCold, ///< Cold boot
|
||||
bmWarm, ///< Warm boot
|
||||
bmS3, ///< S3 resume
|
||||
bmFast, ///< Fast boot
|
||||
MrcBootModeMax, ///< MRC_BOOT_MODE enumeration maximum value.
|
||||
MrcBootModeDelim = INT32_MAX ///< This value ensures the enum size is consistent on both sides of the PPI.
|
||||
} MRC_BOOT_MODE;
|
||||
#endif //__MRC_BOOT_MODE__
|
||||
|
||||
//
|
||||
// Matches MrcDdrType enum in MRC
|
||||
//
|
||||
#ifndef MRC_DDR_TYPE_DDR5
|
||||
#define MRC_DDR_TYPE_DDR5 1
|
||||
#endif
|
||||
#ifndef MRC_DDR_TYPE_LPDDR5
|
||||
#define MRC_DDR_TYPE_LPDDR5 2
|
||||
#endif
|
||||
#ifndef MRC_DDR_TYPE_LPDDR4
|
||||
#define MRC_DDR_TYPE_LPDDR4 3
|
||||
#endif
|
||||
#ifndef MRC_DDR_TYPE_UNKNOWN
|
||||
#define MRC_DDR_TYPE_UNKNOWN 4
|
||||
#endif
|
||||
|
||||
#define MAX_PROFILE_NUM 4 // number of memory profiles supported
|
||||
#define MAX_XMP_PROFILE_NUM 2 // number of XMP profiles supported
|
||||
#define MAX_TRACE_REGION 5
|
||||
#define MAX_TRACE_CACHE_TYPE 2
|
||||
|
||||
//
|
||||
// DIMM timings
|
||||
//
|
||||
typedef struct {
|
||||
UINT32 tCK; ///< Memory cycle time, in femtoseconds.
|
||||
UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's command rate mode.
|
||||
UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS latency.
|
||||
UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time.
|
||||
UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time.
|
||||
UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time.
|
||||
UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time.
|
||||
UINT16 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval.
|
||||
UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
|
||||
UINT16 tRFCpb; ///< Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time.
|
||||
UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
|
||||
UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
|
||||
UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks.
|
||||
UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time.
|
||||
UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups.
|
||||
UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups.
|
||||
UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time.
|
||||
UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time.
|
||||
UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time.
|
||||
UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups.
|
||||
UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups.
|
||||
UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group.
|
||||
} MRC_CH_TIMING;
|
||||
typedef struct {
|
||||
UINT16 tRDPRE; ///< Read CAS to Precharge cmd delay
|
||||
} MRC_IP_TIMING;
|
||||
|
||||
///
|
||||
/// Memory SMBIOS & OC Memory Data Hob
|
||||
///
|
||||
typedef struct {
|
||||
UINT8 Status; ///< See MrcDimmStatus for the definition of this field.
|
||||
UINT8 DimmId;
|
||||
UINT32 DimmCapacity; ///< DIMM size in MBytes.
|
||||
UINT16 MfgId;
|
||||
UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes
|
||||
UINT8 RankInDimm; ///< The number of ranks in this DIMM.
|
||||
UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation.
|
||||
UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation.
|
||||
UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation.
|
||||
UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation.
|
||||
UINT16 Speed; ///< The maximum capable speed of the device, in MHz
|
||||
UINT8 MdSocket; ///< MdSocket: 0 = Memory Down, 1 = Socketed. Needed for SMBIOS structure creation.
|
||||
} DIMM_INFO;
|
||||
|
||||
typedef struct {
|
||||
UINT8 Status; ///< Indicates whether this channel should be used.
|
||||
UINT8 ChannelId;
|
||||
UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel.
|
||||
MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values.
|
||||
DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output characteristics.
|
||||
} CHANNEL_INFO;
|
||||
|
||||
typedef struct {
|
||||
UINT8 Status; ///< Indicates whether this controller should be used.
|
||||
UINT16 DeviceId; ///< The PCI device id of this memory controller.
|
||||
UINT8 RevisionId; ///< The PCI revision id of this memory controller.
|
||||
UINT8 ChannelCount; ///< Number of valid channels that exist on the controller.
|
||||
CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions.
|
||||
} CONTROLLER_INFO;
|
||||
|
||||
typedef struct {
|
||||
UINT64 BaseAddress; ///< Trace Base Address
|
||||
UINT64 TotalSize; ///< Total Trace Region of Same Cache type
|
||||
UINT8 CacheType; ///< Trace Cache Type
|
||||
UINT8 ErrorCode; ///< Trace Region Allocation Fail Error code
|
||||
UINT8 Rsvd[2];
|
||||
} PSMI_MEM_INFO;
|
||||
|
||||
typedef struct {
|
||||
UINT32 DataRate; ///< The memory rate for the current SaGv Point in units of MT/s
|
||||
MRC_CH_TIMING JedecTiming; ///< Timings used for this entry's corresponding SaGv Point - derived from JEDEC SPD spec
|
||||
MRC_IP_TIMING IpTiming; ///< Timings used for this entry's corresponding SaGv Point - IP specific
|
||||
} HOB_SAGV_TIMING_OUT;
|
||||
typedef struct {
|
||||
UINT32 NumSaGvPointsEnabled; ///< Count of the total number of SAGV Points enabled.
|
||||
UINT32 SaGvPointMask; ///< Bit mask where each bit indicates an enabled SAGV point.
|
||||
HOB_SAGV_TIMING_OUT SaGvTiming[HOB_MAX_SAGV_POINTS];
|
||||
} HOB_SAGV_INFO;
|
||||
typedef struct {
|
||||
UINT8 Revision;
|
||||
UINT16 DataWidth; ///< Data width, in bits, of this memory device
|
||||
/** As defined in SMBIOS 3.0 spec
|
||||
Section 7.18.2 and Table 75
|
||||
**/
|
||||
UINT8 MemoryType; ///< DDR type: DDR3, DDR4, or LPDDR3
|
||||
UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz)
|
||||
UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz)
|
||||
/** As defined in SMBIOS 3.0 spec
|
||||
Section 7.17.3 and Table 72
|
||||
**/
|
||||
UINT8 ErrorCorrectionType;
|
||||
|
||||
SiMrcVersion Version;
|
||||
BOOLEAN EccSupport;
|
||||
UINT8 MemoryProfile;
|
||||
UINT32 TotalPhysicalMemorySize;
|
||||
UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist.
|
||||
UINT8 XmpProfileEnable; ///< If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs.
|
||||
UINT8 XmpConfigWarning; ///< If XMP capable DIMMs config support only 1DPC, but 2DPC is installed
|
||||
UINT8 Ratio;
|
||||
UINT8 RefClk;
|
||||
UINT32 VddVoltage[MAX_PROFILE_NUM];
|
||||
UINT32 VddqVoltage[MAX_PROFILE_NUM];
|
||||
UINT32 VppVoltage[MAX_PROFILE_NUM];
|
||||
CONTROLLER_INFO Controller[MAX_NODE];
|
||||
UINT16 Ratio_UINT16; ///< DDR Frequency Ratio, used for programs that require ratios higher then 255
|
||||
UINT32 NumPopulatedChannels; ///< Total number of memory channels populated
|
||||
HOB_SAGV_INFO SagvConfigInfo; ///< This data structure contains SAGV config values that are considered output by the MRC.
|
||||
BOOLEAN IsIbeccEnabled;
|
||||
UINT16 TotalMemWidth; ///< Total Memory Width in bits from all populated channels
|
||||
} MEMORY_INFO_DATA_HOB;
|
||||
|
||||
/**
|
||||
Memory Platform Data Hob
|
||||
|
||||
<b>Revision 1:</b>
|
||||
- Initial version.
|
||||
<b>Revision 2:</b>
|
||||
- Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddress fields
|
||||
**/
|
||||
typedef struct {
|
||||
UINT8 Revision;
|
||||
UINT8 Reserved[3];
|
||||
UINT32 BootMode;
|
||||
UINT32 TsegSize;
|
||||
UINT32 TsegBase;
|
||||
UINT32 PrmrrSize;
|
||||
UINT64 PrmrrBase;
|
||||
UINT32 GttBase;
|
||||
UINT32 MmioSize;
|
||||
UINT32 PciEBaseAddress;
|
||||
PSMI_MEM_INFO PsmiInfo[MAX_TRACE_CACHE_TYPE];
|
||||
PSMI_MEM_INFO PsmiRegionInfo[MAX_TRACE_REGION];
|
||||
BOOLEAN MrcBasicMemoryTestPass;
|
||||
} MEMORY_PLATFORM_DATA;
|
||||
|
||||
typedef struct {
|
||||
EFI_HOB_GUID_TYPE EfiHobGuidType;
|
||||
MEMORY_PLATFORM_DATA Data;
|
||||
UINT8 *Buffer;
|
||||
} MEMORY_PLATFORM_DATA_HOB;
|
||||
|
||||
#pragma pack (pop)
|
||||
|
||||
#endif // _MEM_INFO_HOB_H_
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
# MeteorLakeFspBinPkg/IoT/MeteorLake
|
||||
These FSP binaries are intended to be used with IoT SKUs of the Intel® Core™ Ultra Processors for IoT Edge (Formerly known as Meteor Lake-UH and Meteor Lake-PS). Please consult RaptorLakeFspBinPkg/README.md for more information on how to select the correct FSP binary to use.
|
||||
File diff suppressed because it is too large
Load Diff
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
|
|
@ -0,0 +1,2 @@
|
|||
# MeteorLakeFspBinPkg/IoT/MeteorLake
|
||||
These FSP binaries are intended to be used with IoT SKUs of the Intel® Core™ Ultra processors (formerly known as Meteor Lake) platforms. Please consult MeteorLakeFspBinPkg/README.md for more information on how to select the correct FSP binary to use.
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
# MeteorLakeFspBinPkg
|
||||
These FSP binaries are intended to be used Intel® Core™ Ultra Processors Family (Products formerly Meteor Lake).
|
||||
|
||||
## Meteor Lake Binary
|
||||
For descriptions of the Intel® Core™ Ultra Processors Family (Products formerly Meteor Lake) SKU(s). Please consult the table below:
|
||||
|
||||
Directory Name | 13th Generation Intel® Core™ (formerly Raptor Lake) SKU Description
|
||||
:------------- | :-------------------------
|
||||
IoT/MeteorLake | U/H-Series and PS-Series Embedded processors for IoT and Edge platforms
|
||||
|
||||
Loading…
Reference in New Issue