mirror of https://review.coreboot.org/fsp.git
Updated to Denverton-NS FSP Production Validated 003
This commit is contained in:
Vanessa Eusebio
parent
e5dfd6f61e
commit
c439a4d240
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@ -118,6 +118,14 @@ StructDef
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$gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort5Aspm 1 bytes $_DEFAULT_ = 0x02
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$gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort6Aspm 1 bytes $_DEFAULT_ = 0x02
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$gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort7Aspm 1 bytes $_DEFAULT_ = 0x02
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$gHarrisonvilleFspPkgTokenSpaceGuid_PcdRootPort0LaneReversal 1 bytes $_DEFAULT_ = 0
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$gHarrisonvilleFspPkgTokenSpaceGuid_PcdRootPort1LaneReversal 1 bytes $_DEFAULT_ = 0
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$gHarrisonvilleFspPkgTokenSpaceGuid_PcdRootPort2LaneReversal 1 bytes $_DEFAULT_ = 0
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$gHarrisonvilleFspPkgTokenSpaceGuid_PcdRootPort3LaneReversal 1 bytes $_DEFAULT_ = 0
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$gHarrisonvilleFspPkgTokenSpaceGuid_PcdRootPort4LaneReversal 1 bytes $_DEFAULT_ = 0
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$gHarrisonvilleFspPkgTokenSpaceGuid_PcdRootPort5LaneReversal 1 bytes $_DEFAULT_ = 0
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$gHarrisonvilleFspPkgTokenSpaceGuid_PcdRootPort6LaneReversal 1 bytes $_DEFAULT_ = 0
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$gHarrisonvilleFspPkgTokenSpaceGuid_PcdRootPort7LaneReversal 1 bytes $_DEFAULT_ = 0
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EndStruct
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@ -180,6 +188,11 @@ List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdActiveCoreCount
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Selection 15 , "15"
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EndList
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List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdRootPort2LaneReversal
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Selection 0 , "Disabled"
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Selection 1 , "Enabled"
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EndList
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List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort1Aspm
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Selection 0 , "Disabled"
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Selection 2 , "L1"
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@ -243,11 +256,21 @@ List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort3LinkSpeed
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Selection 3 , "GEN3"
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EndList
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List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdRootPort0LaneReversal
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Selection 0 , "Disabled"
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Selection 1 , "Enabled"
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EndList
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List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort3DeEmphasis
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Selection 0 , "6dB"
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Selection 1 , "3.5dB"
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EndList
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List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdRootPort3LaneReversal
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Selection 0 , "Disabled"
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Selection 1 , "Enabled"
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EndList
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List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort2Aspm
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Selection 0 , "Disabled"
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Selection 2 , "L1"
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@ -292,6 +315,16 @@ List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdDdrFreq
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Selection 6 , "2400"
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EndList
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List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdRootPort6LaneReversal
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Selection 0 , "Disabled"
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Selection 1 , "Enabled"
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EndList
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List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdRootPort4LaneReversal
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Selection 0 , "Disabled"
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Selection 1 , "Enabled"
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EndList
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List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdMrcRmtCpgcNumBursts
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Selection 1 , "1"
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Selection 2 , "2"
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@ -326,6 +359,11 @@ List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdUsb3Port2Pin
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Selection 8 , "No pin mapped"
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EndList
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List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdRootPort1LaneReversal
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Selection 0 , "Disabled"
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Selection 1 , "Enabled"
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EndList
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List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdFsptPort80RouteDisable
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Selection 0 , "VPD-Style"
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Selection 1 , "Enable Port80 Output[Default]"
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@ -362,6 +400,11 @@ List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdUsb3Port1Pin
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Selection 8 , "No pin mapped"
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EndList
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List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdRootPort5LaneReversal
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Selection 0 , "Disabled"
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Selection 1 , "Enabled"
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EndList
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List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort7Aspm
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Selection 0 , "Disabled"
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Selection 2 , "L1"
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@ -414,6 +457,11 @@ List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdUsb2Port3Pin
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Selection 8 , "No pin mapped"
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EndList
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List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdRootPort7LaneReversal
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Selection 0 , "Disabled"
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Selection 1 , "Enabled"
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EndList
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List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdEnableGbE
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Selection 0 , "Disable LAN 0 & LAN 1"
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Selection 1 , "Enable LAN 0 & LAN 1"
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@ -502,6 +550,22 @@ Page "SoC"
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Help "Enable PCI Express Active State Power Management settings"
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Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort7Aspm, "PCIe Root Port 7 ASPM", &gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort7Aspm,
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Help "Enable PCI Express Active State Power Management settings"
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Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdRootPort0LaneReversal, "PCIe Root Port 0 Lane Reversal", &gHarrisonvilleFspPkgTokenSpaceGuid_PcdRootPort0LaneReversal,
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Help "Enable / Disable Dynamic Lane reversal on PCI Express RootPort"
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Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdRootPort1LaneReversal, "PCIe Root Port 1 Lane Reversal", &gHarrisonvilleFspPkgTokenSpaceGuid_PcdRootPort1LaneReversal,
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Help "Enable / Disable Dynamic Lane reversal on PCI Express RootPort"
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Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdRootPort2LaneReversal, "PCIe Root Port 2 Lane Reversal", &gHarrisonvilleFspPkgTokenSpaceGuid_PcdRootPort2LaneReversal,
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Help "Enable / Disable Dynamic Lane reversal on PCI Express RootPort"
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Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdRootPort3LaneReversal, "PCIe Root Port 3 Lane Reversal", &gHarrisonvilleFspPkgTokenSpaceGuid_PcdRootPort3LaneReversal,
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Help "Enable / Disable Dynamic Lane reversal on PCI Express RootPort"
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Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdRootPort4LaneReversal, "PCIe Root Port 4 Lane Reversal", &gHarrisonvilleFspPkgTokenSpaceGuid_PcdRootPort4LaneReversal,
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Help "Enable / Disable Dynamic Lane reversal on PCI Express RootPort"
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Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdRootPort5LaneReversal, "PCIe Root Port 5 Lane Reversal", &gHarrisonvilleFspPkgTokenSpaceGuid_PcdRootPort5LaneReversal,
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Help "Enable / Disable Dynamic Lane reversal on PCI Express RootPort"
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Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdRootPort6LaneReversal, "PCIe Root Port 6 Lane Reversal", &gHarrisonvilleFspPkgTokenSpaceGuid_PcdRootPort6LaneReversal,
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Help "Enable / Disable Dynamic Lane reversal on PCI Express RootPort"
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Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdRootPort7LaneReversal, "PCIe Root Port 7 Lane Reversal", &gHarrisonvilleFspPkgTokenSpaceGuid_PcdRootPort7LaneReversal,
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Help "Enable / Disable Dynamic Lane reversal on PCI Express RootPort"
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EndPage
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Page "Platform Specific"
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@ -253,9 +253,57 @@ typedef struct {
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**/
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UINT8 PcdPcieRootPort7Aspm;
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/** Offset 0x0054
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/** Offset 0x0054 - PCIe Root Port 0 Lane Reversal
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Enable / Disable Dynamic Lane reversal on PCI Express RootPort
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0:Disabled, 1:Enabled
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**/
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UINT8 UnusedUpdSpace2[140];
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UINT8 PcdRootPort0LaneReversal;
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/** Offset 0x0055 - PCIe Root Port 1 Lane Reversal
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Enable / Disable Dynamic Lane reversal on PCI Express RootPort
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0:Disabled, 1:Enabled
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**/
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UINT8 PcdRootPort1LaneReversal;
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/** Offset 0x0056 - PCIe Root Port 2 Lane Reversal
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Enable / Disable Dynamic Lane reversal on PCI Express RootPort
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0:Disabled, 1:Enabled
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**/
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UINT8 PcdRootPort2LaneReversal;
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/** Offset 0x0057 - PCIe Root Port 3 Lane Reversal
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Enable / Disable Dynamic Lane reversal on PCI Express RootPort
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0:Disabled, 1:Enabled
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**/
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UINT8 PcdRootPort3LaneReversal;
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/** Offset 0x0058 - PCIe Root Port 4 Lane Reversal
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Enable / Disable Dynamic Lane reversal on PCI Express RootPort
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0:Disabled, 1:Enabled
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**/
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UINT8 PcdRootPort4LaneReversal;
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/** Offset 0x0059 - PCIe Root Port 5 Lane Reversal
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Enable / Disable Dynamic Lane reversal on PCI Express RootPort
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0:Disabled, 1:Enabled
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**/
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UINT8 PcdRootPort5LaneReversal;
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/** Offset 0x005A - PCIe Root Port 6 Lane Reversal
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Enable / Disable Dynamic Lane reversal on PCI Express RootPort
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0:Disabled, 1:Enabled
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**/
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UINT8 PcdRootPort6LaneReversal;
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/** Offset 0x005B - PCIe Root Port 7 Lane Reversal
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Enable / Disable Dynamic Lane reversal on PCI Express RootPort
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0:Disabled, 1:Enabled
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**/
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UINT8 PcdRootPort7LaneReversal;
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/** Offset 0x005C
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**/
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UINT8 UnusedUpdSpace2[132];
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/** Offset 0x00E0
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**/
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