mirror of https://review.coreboot.org/fsp.git
Comet Lake FSP 9.3.7B.20
This commit is contained in:
Nate DeSimone
parent
cd99eca86d
commit
b24086682c
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@ -2,7 +2,7 @@
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Boot Setting File for Platform Configuration.
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Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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@ -226,7 +226,8 @@ StructDef
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$gPlatformFspPkgTokenSpaceGuid_TxtLcpPdSize 8 bytes $_DEFAULT_ = 0x0000000000000000
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$gPlatformFspPkgTokenSpaceGuid_IsTPMPresence 1 bytes $_DEFAULT_ = 0x0
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$gPlatformFspPkgTokenSpaceGuid_AutoEasyOverclock 1 bytes $_DEFAULT_ = 0x00
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$gPlatformFspPkgTokenSpaceGuid_ReservedSecurityPreMem 2 bytes $_DEFAULT_ = 0x00
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$gPlatformFspPkgTokenSpaceGuid_VmaxStress 1 bytes $_DEFAULT_ = 0x01
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$gPlatformFspPkgTokenSpaceGuid_ReservedSecurityPreMem 1 bytes $_DEFAULT_ = 0x00
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$gPlatformFspPkgTokenSpaceGuid_VtdBaseAddress 12 bytes $_DEFAULT_ = 0x00,0x00,0xD9,0xFE,0x00,0x20,0xD9,0xFE,0x00,0x10,0xD9,0xFE
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$gPlatformFspPkgTokenSpaceGuid_SmbusEnable 1 bytes $_DEFAULT_ = 0x01
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$gPlatformFspPkgTokenSpaceGuid_PlatformDebugConsent 1 bytes $_DEFAULT_ = 0x00
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@ -469,7 +470,11 @@ StructDef
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$gPlatformFspPkgTokenSpaceGuid_CoreVfPointOffsetPrefix 15 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
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$gPlatformFspPkgTokenSpaceGuid_CoreVfPointRatio 15 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
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$gPlatformFspPkgTokenSpaceGuid_CoreVfPointCount 1 bytes $_DEFAULT_ = 0x00
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Skip 9 bytes
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$gPlatformFspPkgTokenSpaceGuid_RefreshPanicWm 1 bytes $_DEFAULT_ = 0x09
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$gPlatformFspPkgTokenSpaceGuid_RefreshHpWm 1 bytes $_DEFAULT_ = 0x08
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$gPlatformFspPkgTokenSpaceGuid_RetrainOnFastFail 1 bytes $_DEFAULT_ = 0x01
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$gPlatformFspPkgTokenSpaceGuid_DllBwEnOverride 1 bytes $_DEFAULT_ = 0x00
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Skip 5 bytes
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$gPlatformFspPkgTokenSpaceGuid_SkipExtGfxScan 1 bytes $_DEFAULT_ = 0x0
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$gPlatformFspPkgTokenSpaceGuid_BdatEnable 1 bytes $_DEFAULT_ = 0x00
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$gPlatformFspPkgTokenSpaceGuid_ScanExtGfxForLegacyOpRom 1 bytes $_DEFAULT_ = 0x01
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@ -509,7 +514,8 @@ StructDef
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Skip 1 bytes
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$gPlatformFspPkgTokenSpaceGuid_DeltaT12PowerCycleDelayPreMem 2 bytes $_DEFAULT_ = 0x0
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$gPlatformFspPkgTokenSpaceGuid_OemT12DelayOverride 1 bytes $_DEFAULT_ = 0x0
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$gPlatformFspPkgTokenSpaceGuid_SaPreMemTestRsvd 9 bytes $_DEFAULT_ = 0x00
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$gPlatformFspPkgTokenSpaceGuid_DmaControlGuarantee 1 bytes $_DEFAULT_ = 0x1
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$gPlatformFspPkgTokenSpaceGuid_SaPreMemTestRsvd 8 bytes $_DEFAULT_ = 0x00
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$gPlatformFspPkgTokenSpaceGuid_TotalFlashSize 2 bytes $_DEFAULT_ = 0x0000
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$gPlatformFspPkgTokenSpaceGuid_BiosSize 2 bytes $_DEFAULT_ = 0x2800
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$gPlatformFspPkgTokenSpaceGuid_TxtAcheckRequest 1 bytes $_DEFAULT_ = 0x0
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@ -517,7 +523,9 @@ StructDef
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$gPlatformFspPkgTokenSpaceGuid_SmbusDynamicPowerGating 1 bytes $_DEFAULT_ = 0x01
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$gPlatformFspPkgTokenSpaceGuid_WdtDisableAndLock 1 bytes $_DEFAULT_ = 0x00
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$gPlatformFspPkgTokenSpaceGuid_SmbusSpdWriteDisable 1 bytes $_DEFAULT_ = 0x01
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$gPlatformFspPkgTokenSpaceGuid_ReservedPchPreMemTest 16 bytes $_DEFAULT_ = 0x00
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$gPlatformFspPkgTokenSpaceGuid_PerCoreRatioOverride 1 bytes $_DEFAULT_ = 0x00
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$gPlatformFspPkgTokenSpaceGuid_PerCoreRatio 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
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$gPlatformFspPkgTokenSpaceGuid_ReservedPchPreMemTest 5 bytes $_DEFAULT_ = 0x00
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$gPlatformFspPkgTokenSpaceGuid_DidInitStat 1 bytes $_DEFAULT_ = 0x0
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$gPlatformFspPkgTokenSpaceGuid_DisableCpuReplacedPolling 1 bytes $_DEFAULT_ = 0x0
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$gPlatformFspPkgTokenSpaceGuid_SendDidMsg 1 bytes $_DEFAULT_ = 0x1
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@ -546,6 +554,7 @@ StructDef
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$gPlatformFspPkgTokenSpaceGuid_tWTR_L 1 bytes $_DEFAULT_ = 0x00
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$gPlatformFspPkgTokenSpaceGuid_tWTR_S 1 bytes $_DEFAULT_ = 0x00
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$gPlatformFspPkgTokenSpaceGuid_SkipCpuReplacementCheck 1 bytes $_DEFAULT_ = 0x00
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$gPlatformFspPkgTokenSpaceGuid_PcieRpHotPlug 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
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Find "CMLUPD_S"
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$gPlatformFspPkgTokenSpaceGuid_Revision 1 bytes $_DEFAULT_ = 0x01
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@ -1142,7 +1151,8 @@ StructDef
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$gPlatformFspPkgTokenSpaceGuid_PchPmDisableEnergyReport 1 bytes $_DEFAULT_ = 0x00
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$gPlatformFspPkgTokenSpaceGuid_SataTestMode 1 bytes $_DEFAULT_ = 0x00
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$gPlatformFspPkgTokenSpaceGuid_PchXhciOcLock 1 bytes $_DEFAULT_ = 0x01
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$gPlatformFspPkgTokenSpaceGuid_ReservedPchPostMemTest 16 bytes $_DEFAULT_ = 0x00
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$gPlatformFspPkgTokenSpaceGuid_Usb3HsioRxCtrlCompMult 10 bytes $_DEFAULT_ = 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C
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$gPlatformFspPkgTokenSpaceGuid_ReservedPchPostMemTest 6 bytes $_DEFAULT_ = 0x00
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$gCannonLakeFspPkgTokenSpaceGuid_MctpBroadcastCycle 1 bytes $_DEFAULT_ = 0x0
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$gPlatformFspPkgTokenSpaceGuid_EmmcUseCustomDlls 1 bytes $_DEFAULT_ = 0x0
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Skip 1 bytes
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@ -2450,7 +2460,9 @@ Page "System Agent 1"
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Help "IsTPMPresence default values"
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"Valid range: 0x00 ~ 0xFF"
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Combo $gPlatformFspPkgTokenSpaceGuid_AutoEasyOverclock, "Intel Speed Optimizer Enable", &EN_DIS,
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Help "When enabled this feature automatically overclocks your processor. It changes the All Core Frequency along with PL1, PL2, and IccMax. </b>0: Disable;<b> 1: Enable"
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Help "@Deprecated: CML won't support BIOS ISO. And XTU ISO supported depends on Board thermal design. When enabled this feature automatically overclocks your processor. It changes the All Core Frequency along with PL1, PL2, and IccMax. </b>0: Disable;<b> 1: Enable"
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Combo $gPlatformFspPkgTokenSpaceGuid_VmaxStress, "Vmax Stress", &EN_DIS,
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Help "Vmax Stress enable/disable. When enabled, frequency may be clipped the effective max voltage on the silicon is too high.0: Disable; <b>1: Enable.</b>"
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Combo $gPlatformFspPkgTokenSpaceGuid_ReservedSecurityPreMem, "ReservedSecurityPreMem", &EN_DIS,
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Help "Reserved for Security Pre-Mem"
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EditNum $gPlatformFspPkgTokenSpaceGuid_VtdBaseAddress, "Base addresses for VT-d function MMIO access", HEX,
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@ -2476,6 +2488,8 @@ Page "System Agent 1"
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Help "Select the value for delay required. 0(Default)= No delay, 0xFFFF = Auto calculate T12 Delay to max 500ms"
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Combo $gPlatformFspPkgTokenSpaceGuid_OemT12DelayOverride, "Oem T12 Dealy Override", &EN_DIS,
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Help "Oem T12 Dealy Override. 0(Default)=Disable 1=Enable "
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Combo $gPlatformFspPkgTokenSpaceGuid_DmaControlGuarantee, "State of DMA_CONTROL_GUARANTEE bit in the DMAR table", &EN_DIS,
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Help "0=Disable/Clear, 1=Enable/Set"
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EndPage
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Page "System Agent 2"
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@ -3614,6 +3628,17 @@ Page "Memory Reference Code 1"
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EditNum $gPlatformFspPkgTokenSpaceGuid_CoreVfPointCount, "Core VF Point Count", HEX,
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Help "Number of supported Core Voltage & Frequency Point Offset"
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"Valid range: 0x0 ~ 0xFF"
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EditNum $gPlatformFspPkgTokenSpaceGuid_RefreshPanicWm, "REFRESH_PANIC_WM", HEX,
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Help "Refresh Panic Watermark, range 1-9"
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"Valid range: 0x01 ~ 0x9"
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EditNum $gPlatformFspPkgTokenSpaceGuid_RefreshHpWm, "REFRESH_HP_WM", HEX,
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Help "Refresh High Priority Watermark, range 1-9"
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"Valid range: 0x01 ~ 0x9"
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EditNum $gPlatformFspPkgTokenSpaceGuid_RetrainOnFastFail, "Retrain On Fast Fail", HEX,
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Help "Restart MRC in Cold mode if SW MemTest fails during Fast flow. Default = Enabled"
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"Valid range: 0x0 ~ 0xFF"
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Combo $gPlatformFspPkgTokenSpaceGuid_DllBwEnOverride, "DllBwEnOverride", &EN_DIS,
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Help "DllBwEnOverride 0: Disable(Default), 1: Enable"
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Combo $gPlatformFspPkgTokenSpaceGuid_SkipExtGfxScan, "Skip external display device scanning", &EN_DIS,
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Help "Enable: Do not scan for external display device, Disable (Default): Scan external display devices"
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Combo $gPlatformFspPkgTokenSpaceGuid_BdatEnable, "Generate BIOS Data ACPI Table", &EN_DIS,
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@ -4181,7 +4206,7 @@ Page "PCH 1"
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Combo $gPlatformFspPkgTokenSpaceGuid_PchLockDownRtcMemoryLock, "RTC CMOS MEMORY LOCK", &EN_DIS,
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Help "Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper and and lower 128-byte bank of RTC RAM."
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EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpHotPlug, "Enable PCIE RP HotPlug", HEX,
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Help "Indicate whether the root port is hot plug available."
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Help "DEPRECATED"
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"Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
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EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen2EqBoostMagEnable, "Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override", HEX,
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Help "0: Disable; 1: Enable."
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@ -4351,7 +4376,7 @@ Page "PCH 1"
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Help "Bits 7:3 are for Signed Magnatude number added to the CTLE code, Bits 2:0 are for controlling the input offset"
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"Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF"
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EditNum $gPlatformFspPkgTokenSpaceGuid_PchUsbHsioRxTuningEnable, "PCH USB3 HSIO Rx Tuning Enable", HEX,
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Help "Mask for enabling tuning of HSIO Rx signals of USB3 ports. Bits: 0 - HsioCtrlAdaptOffsetCfgEnable, 1 - HsioFilterSelNEnable, 2 - HsioFilterSelPEnable, 3 - HsioOlfpsCfgPullUpDwnResEnable"
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Help "Mask for enabling tuning of HSIO Rx signals of USB3 ports. Bits: 0 - HsioCtrlAdaptOffsetCfgEnable, 1 - HsioFilterSelNEnable, 2 - HsioFilterSelPEnable, 3 - HsioOlfpsCfgPullUpDwnResEnable, 4 - HsioCtrlCompMultEnable"
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"Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF"
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EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpPcieSpeed, "PCIE RP Pcie Speed", HEX,
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Help "Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see: PCH_PCIE_SPEED)."
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@ -4393,11 +4418,16 @@ Page "PCH 1"
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Help "Set 1 to clear WDT status, then disable and lock WDT registers."
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Combo $gPlatformFspPkgTokenSpaceGuid_SmbusSpdWriteDisable, "SMBUS SPD Write Disable", &EN_DIS,
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Help "Set/Clear Smbus SPD Write Disable. 0: leave SPD Write Disable bit; 1: set SPD Write Disable bit. For security recommendations, SPD write disable bit must be set."
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Combo $gPlatformFspPkgTokenSpaceGuid_ReservedPchPreMemTest, "ReservedPchPreMemTest", &EN_DIS,
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Help "Reserved for Pch Pre-Mem Test"
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Combo $gPlatformFspPkgTokenSpaceGuid_PerCoreRatioOverride, "Per Core Max Ratio override", &EN_DIS,
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Help "Enable or disable Per Core PState OC supported by writing OCMB 0x1D to program new favored core ratio to each Core. <b>0: Disable</b>, 1: enable"
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EditNum $gPlatformFspPkgTokenSpaceGuid_PerCoreRatio, "Per Core Current Max Ratio", HEX,
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Help "Array for the Per Core Max Ratio"
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"Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF"
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EditNum $gPlatformFspPkgTokenSpaceGuid_PcieEqPh3LaneParamCm, "PCIE Eq Ph3 Lane Param Cm", HEX,
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Help "PCH_PCIE_EQ_LANE_PARAM. Coefficient C-1."
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"Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
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Combo $gPlatformFspPkgTokenSpaceGuid_ReservedPchPreMemTest, "ReservedPchPreMemTest", &EN_DIS,
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Help "Reserved for Pch Pre-Mem Test"
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Combo $gPlatformFspPkgTokenSpaceGuid_DidInitStat, "Force ME DID Init Status", &EN_DIS,
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Help "Test, 0: disable, 1: Success, 2: No Memory in Channels, 3: Memory Init Error, Set ME DID init stat value"
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Combo $gPlatformFspPkgTokenSpaceGuid_DisableCpuReplacedPolling, "CPU Replaced Polling Disable", &EN_DIS,
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@ -4415,6 +4445,9 @@ Page "PCH 1"
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EditNum $gPlatformFspPkgTokenSpaceGuid_PcieEqPh3LaneParamCp, "PCIE Eq Ph3 Lane Param Cp", HEX,
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Help "PCH_PCIE_EQ_LANE_PARAM. Coefficient C+1."
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"Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
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EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpHotPlug, "Enable PCIE RP HotPlug", HEX,
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Help "Indicate whether the root port is hot plug available"
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"Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
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EditNum $gPlatformFspPkgTokenSpaceGuid_PcieSwEqCoeffListCm, "PCIE Sw Eq CoeffList Cm", HEX,
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Help "PCH_PCIE_EQ_PARAM. Coefficient C-1. The values depend on PcieNumOfCoefficients, the default value of PcieNumOfCoefficients is 3 hence only first 3 values are considered."
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"Valid range: 0x00 ~ 0xFFFFFFFFFF"
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@ -4795,6 +4828,9 @@ Page "PCH 1"
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Help "Allow entrance to the PCH SATA test modes."
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Combo $gPlatformFspPkgTokenSpaceGuid_PchXhciOcLock, "PCH USB OverCurrent mapping lock enable", &EN_DIS,
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Help "If this policy option is enabled then BIOS will program OCCFDONE bit in xHCI meaning that OC mapping data will be consumed by xHCI and OC mapping registers will be locked."
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EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioRxCtrlCompMult, "CTLE Rate control CPR RCOMP multiplier (Double Rate)", HEX,
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Help "CTLE Rate control CPR RCOMP multiplier (Double Rate), HSIO_RX_DWORD27 [31:24], One byte for each port."
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"Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF"
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Combo $gPlatformFspPkgTokenSpaceGuid_ReservedPchPostMemTest, "ReservedPchPostMemTest", &EN_DIS,
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Help "Reserved for Pch Post-Mem Test"
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Combo $gCannonLakeFspPkgTokenSpaceGuid_MctpBroadcastCycle, "Mctp Broadcast Cycle", &EN_DIS,
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Binary file not shown.
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@ -1,6 +1,6 @@
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/** @file
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Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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@ -1116,17 +1116,25 @@ typedef struct {
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UINT8 IsTPMPresence;
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/** Offset 0x0241 - Intel Speed Optimizer Enable
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When enabled this feature automatically overclocks your processor. It changes the
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All Core Frequency along with PL1, PL2, and IccMax. </b>0: Disable;<b> 1: Enable
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@Deprecated: CML won't support BIOS ISO. And XTU ISO supported depends on Board
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thermal design. When enabled this feature automatically overclocks your processor.
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It changes the All Core Frequency along with PL1, PL2, and IccMax. </b>0: Disable;<b> 1: Enable
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$EN_DIS
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**/
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UINT8 AutoEasyOverclock;
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/** Offset 0x0242 - ReservedSecurityPreMem
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/** Offset 0x0242 - Vmax Stress
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Vmax Stress enable/disable. When enabled, frequency may be clipped the effective
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max voltage on the silicon is too high.0: Disable; <b>1: Enable.</b>
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$EN_DIS
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**/
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UINT8 VmaxStress;
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/** Offset 0x0243 - ReservedSecurityPreMem
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Reserved for Security Pre-Mem
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$EN_DIS
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**/
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UINT8 ReservedSecurityPreMem[2];
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UINT8 ReservedSecurityPreMem[1];
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/** Offset 0x0244 - Base addresses for VT-d function MMIO access
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Base addresses for VT-d MMIO access per VT-d engine
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@ -2518,9 +2526,26 @@ typedef struct {
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**/
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UINT8 CoreVfPointCount;
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/** Offset 0x0553
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/** Offset 0x0553 - REFRESH_PANIC_WM
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Refresh Panic Watermark, range 1-9
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**/
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UINT8 UnusedUpdSpace8[4];
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UINT8 RefreshPanicWm;
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/** Offset 0x0554 - REFRESH_HP_WM
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Refresh High Priority Watermark, range 1-9
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**/
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UINT8 RefreshHpWm;
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/** Offset 0x0555 - Retrain On Fast Fail
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Restart MRC in Cold mode if SW MemTest fails during Fast flow. Default = Enabled
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**/
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UINT8 RetrainOnFastFail;
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/** Offset 0x0556 - DllBwEnOverride
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DllBwEnOverride 0: Disable(Default), 1: Enable
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$EN_DIS
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**/
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UINT8 DllBwEnOverride;
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/** Offset 0x0557
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**/
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@ -2749,7 +2774,7 @@ typedef struct {
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/** Offset 0x05B1
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**/
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UINT8 UnusedUpdSpace9;
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UINT8 UnusedUpdSpace8;
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/** Offset 0x05B2 - Jitter Dwell Time for PCIe Gen3 Software Equalization
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Range: 0-65535, default is 1000. @warning Do not change from the default
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@ -2792,7 +2817,7 @@ typedef struct {
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/** Offset 0x05BD
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**/
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UINT8 UnusedUpdSpace10;
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UINT8 UnusedUpdSpace9;
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/** Offset 0x05BE - Delta T12 Power Cycle Delay required in ms
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Select the value for delay required. 0(Default)= No delay, 0xFFFF = Auto calculate
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@ -2807,11 +2832,17 @@ typedef struct {
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**/
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UINT8 OemT12DelayOverride;
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/** Offset 0x05C1 - SaPreMemTestRsvd
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/** Offset 0x05C1 - State of DMA_CONTROL_GUARANTEE bit in the DMAR table
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0=Disable/Clear, 1=Enable/Set
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$EN_DIS
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**/
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UINT8 DmaControlGuarantee;
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/** Offset 0x05C2 - SaPreMemTestRsvd
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Reserved for SA Pre-Mem Test
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$EN_DIS
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**/
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UINT8 SaPreMemTestRsvd[9];
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UINT8 SaPreMemTestRsvd[8];
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/** Offset 0x05CA - TotalFlashSize
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Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable
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@ -2854,11 +2885,23 @@ typedef struct {
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**/
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UINT8 SmbusSpdWriteDisable;
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/** Offset 0x05D5 - ReservedPchPreMemTest
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/** Offset 0x05D5 - Per Core Max Ratio override
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Enable or disable Per Core PState OC supported by writing OCMB 0x1D to program new
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favored core ratio to each Core. <b>0: Disable</b>, 1: enable
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$EN_DIS
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**/
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UINT8 PerCoreRatioOverride;
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/** Offset 0x05D6 - Per Core Current Max Ratio
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Array for the Per Core Max Ratio
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**/
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UINT8 PerCoreRatio[10];
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/** Offset 0x05E0 - ReservedPchPreMemTest
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Reserved for Pch Pre-Mem Test
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$EN_DIS
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**/
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UINT8 ReservedPchPreMemTest[16];
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UINT8 ReservedPchPreMemTest[5];
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|
||||
/** Offset 0x05E5 - Force ME DID Init Status
|
||||
Test, 0: disable, 1: Success, 2: No Memory in Channels, 3: Memory Init Error, Set
|
||||
|
|
@ -3017,7 +3060,12 @@ typedef struct {
|
|||
**/
|
||||
UINT8 SkipCpuReplacementCheck;
|
||||
|
||||
/** Offset 0x0601
|
||||
/** Offset 0x0601 - Enable PCIE RP HotPlug
|
||||
Indicate whether the root port is hot plug available
|
||||
**/
|
||||
UINT8 PcieRpHotPlug[24];
|
||||
|
||||
/** Offset 0x0619
|
||||
**/
|
||||
UINT8 ReservedFspmTestUpd[7];
|
||||
} FSP_M_TEST_CONFIG;
|
||||
|
|
@ -3042,11 +3090,11 @@ typedef struct {
|
|||
**/
|
||||
FSP_M_TEST_CONFIG FspmTestConfig;
|
||||
|
||||
/** Offset 0x0608
|
||||
/** Offset 0x0620
|
||||
**/
|
||||
UINT8 UnusedUpdSpace11[6];
|
||||
UINT8 UnusedUpdSpace10[6];
|
||||
|
||||
/** Offset 0x060E
|
||||
/** Offset 0x0626
|
||||
**/
|
||||
UINT16 UpdTerminator;
|
||||
} FSPM_UPD;
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
/** @file
|
||||
|
||||
Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
|
||||
Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.<BR>
|
||||
|
||||
SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||
|
||||
|
|
@ -1512,7 +1512,7 @@ typedef struct {
|
|||
UINT8 PchLockDownRtcMemoryLock;
|
||||
|
||||
/** Offset 0x03B6 - Enable PCIE RP HotPlug
|
||||
Indicate whether the root port is hot plug available.
|
||||
DEPRECATED
|
||||
**/
|
||||
UINT8 PcieRpHotPlug[24];
|
||||
|
||||
|
|
@ -1589,7 +1589,8 @@ typedef struct {
|
|||
|
||||
/** Offset 0x0510 - PCH USB3 HSIO Rx Tuning Enable
|
||||
Mask for enabling tuning of HSIO Rx signals of USB3 ports. Bits: 0 - HsioCtrlAdaptOffsetCfgEnable,
|
||||
1 - HsioFilterSelNEnable, 2 - HsioFilterSelPEnable, 3 - HsioOlfpsCfgPullUpDwnResEnable
|
||||
1 - HsioFilterSelNEnable, 2 - HsioFilterSelPEnable, 3 - HsioOlfpsCfgPullUpDwnResEnable,
|
||||
4 - HsioCtrlCompMultEnable
|
||||
**/
|
||||
UINT8 PchUsbHsioRxTuningEnable[10];
|
||||
|
||||
|
|
@ -3529,11 +3530,17 @@ typedef struct {
|
|||
**/
|
||||
UINT8 PchXhciOcLock;
|
||||
|
||||
/** Offset 0x0A79 - ReservedPchPostMemTest
|
||||
/** Offset 0x0A79 - CTLE Rate control CPR RCOMP multiplier (Double Rate)
|
||||
CTLE Rate control CPR RCOMP multiplier (Double Rate), HSIO_RX_DWORD27 [31:24], One
|
||||
byte for each port.
|
||||
**/
|
||||
UINT8 Usb3HsioRxCtrlCompMult[10];
|
||||
|
||||
/** Offset 0x0A83 - ReservedPchPostMemTest
|
||||
Reserved for Pch Post-Mem Test
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 ReservedPchPostMemTest[16];
|
||||
UINT8 ReservedPchPostMemTest[6];
|
||||
|
||||
/** Offset 0x0A89 - Mctp Broadcast Cycle
|
||||
Test, Determine if MCTP Broadcast is enabled <b>0: Disable</b>; 1: Enable.
|
||||
|
|
|
|||
Loading…
Reference in New Issue