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+/Limits [(struct_f_s_p___m___c_o_n_f_i_g_a01bd1efab62cde4b6e53937f5a665c1f) (struct_f_s_p___m___c_o_n_f_i_g_a03e49ab802096813ee93324538d1e30e)]
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-/Limits [(struct_f_s_p___m___c_o_n_f_i_g_a5c267eac238bd35ae72f483c4bcd9686) (struct_f_s_p___m___c_o_n_f_i_g_a61511c77388eb87a076ffb66925b0652)]
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+/Limits [(struct_f_s_p___m___c_o_n_f_i_g_a043d61ae8997e8e291180abc70bef881) (struct_f_s_p___m___c_o_n_f_i_g_a061fa1db93a9ad0a267f0fd0c7ed1edb)]
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-/Limits [(struct_f_s_p___m___c_o_n_f_i_g_a616276b64e4d67d21c97f2f07e6aebf3) (struct_f_s_p___m___c_o_n_f_i_g_a640a93a0c2d98d5b530f1ee83c3f731f)]
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+/Limits [(struct_f_s_p___m___c_o_n_f_i_g_a06a2820d9974c6878c9a6bcfe3d3aeee) (struct_f_s_p___m___c_o_n_f_i_g_a0871e1ef1c74074a9d2a9a8d8fc6eb9a)]
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-/Limits [(struct_f_s_p___m___c_o_n_f_i_g_a642e2e769b0d1e6da2af452fc580d082) (struct_f_s_p___m___c_o_n_f_i_g_a65d0f4d6b8e4073c18043c8640a4b7d9)]
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-/Limits [(struct_f_s_p___m___c_o_n_f_i_g_a65fbcbdbd7d6f7a3e877eb9117214a63) (struct_f_s_p___m___c_o_n_f_i_g_a6a18e2c93b8fa6fa3e4722db5126f9f2)]
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-/Limits [(struct_f_s_p___m___c_o_n_f_i_g_a6a1e19aac69d5fb0177b98f20ac6ac17) (struct_f_s_p___m___c_o_n_f_i_g_a6be1d589d79e3990731de9cd9bb36b7a)]
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-/Limits [(struct_f_s_p___m___c_o_n_f_i_g_a7d08dd3a8a22a17b2572c0c40d5f2c80) (struct_f_s_p___m___c_o_n_f_i_g_a82fdafe37e3da27fb6c2e151dd015f25)]
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-/Limits [(struct_f_s_p___m___c_o_n_f_i_g_a845bc870512198e0eb53f9b37cdb1252) (struct_f_s_p___m___c_o_n_f_i_g_a86892f584fe45b8a42d9f348f516340f)]
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-/Limits [(struct_f_s_p___m___c_o_n_f_i_g_a86fa3fda4843cfbc90ffb2323b7ea495) (struct_f_s_p___m___c_o_n_f_i_g_a88ccf2e8539d292a69d90bda029b37fe)]
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-/Limits [(struct_f_s_p___m___c_o_n_f_i_g_a988064510fcdebbbaa990eacb094a933) (struct_f_s_p___m___c_o_n_f_i_g_a9af717d041fb655deadc0ab6cd8900c7)]
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+/Limits [(struct_f_s_p___m___c_o_n_f_i_g_a3c1e684d554a95d2af834956174dff6f) (struct_f_s_p___m___c_o_n_f_i_g_a3e3382a2b7e38ad678bfc4583698dd54)]
 >>
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-/Limits [(struct_f_s_p___m___c_o_n_f_i_g_a9b45dd220a151482af8c7d49b5cf78d4) (struct_f_s_p___m___c_o_n_f_i_g_a9c89df31e9f38abed6e4220214226ed1)]
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+/Limits [(struct_f_s_p___m___c_o_n_f_i_g_a3e5c2076f5d142b8e13803ff9c504f94) (struct_f_s_p___m___c_o_n_f_i_g_a3f1a73391b0eaaf88144cad38da55b2d)]
 >>
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-/Limits [(struct_f_s_p___m___c_o_n_f_i_g_a9d3bed899e9bcca0928c1cf89e463c04) (struct_f_s_p___m___c_o_n_f_i_g_aa15e9847eeb50ee156c160020d84e889)]
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+/Limits [(struct_f_s_p___m___c_o_n_f_i_g_a3f43b956bfa8b22e5ddb1f9117b382ee) (struct_f_s_p___m___c_o_n_f_i_g_a407d6dcc3269cdf874a4a8f5cf8e2dc3)]
 >>
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-/Limits [(struct_f_s_p___m___c_o_n_f_i_g_aa15fb2fe57af2804940905570212e236) (struct_f_s_p___m___c_o_n_f_i_g_aa362cab26092984b546759ad2f13a88e)]
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 >>
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-/Limits [(struct_f_s_p___m___c_o_n_f_i_g_aa3e5ee43d47e95ca46dc9ceba72abb9e) (struct_f_s_p___m___c_o_n_f_i_g_aa8a3d27600d397f619ee5cd07f128045)]
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 >>
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-/Limits [(struct_f_s_p___m___c_o_n_f_i_g_aa9759c4c8dea2f8429bc9b4004eaa3ca) (struct_f_s_p___m___c_o_n_f_i_g_aab5660c78267c66e19a07251e6284217)]
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 >>
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-/Limits [(struct_f_s_p___m___c_o_n_f_i_g_aabb0e3bbebfe52ef4ebb349cef1ae0eb) (struct_f_s_p___m___c_o_n_f_i_g_aaf1bcbd264f1af587ff9528f3c6dc53c)]
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 >>
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-/Limits [(struct_f_s_p___m___c_o_n_f_i_g_ab15e70ff46f439e12a0d1994cf80a2c2) (struct_f_s_p___m___c_o_n_f_i_g_ab32f3eee75e2296ac8f1f716e99b7916)]
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 >>
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 >>
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-/Limits [(struct_f_s_p___m___c_o_n_f_i_g_ab80945c8fe0166b353f8cb430cc812c7) (struct_f_s_p___m___c_o_n_f_i_g_abc7c5284dc2bbae0ffc2a7f3f7453255)]
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+/Limits [(struct_f_s_p___m___c_o_n_f_i_g_a530cfe419acd9d155e248ab8c16093f4) (struct_f_s_p___m___c_o_n_f_i_g_a5661255164b5d02b089720913b130a7c)]
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-/Limits [(struct_f_s_p___m___c_o_n_f_i_g_abca425fa7373c382c5b5554d03d379a3) (struct_f_s_p___m___c_o_n_f_i_g_abe243f066804fc0ba7bada486a86e88f)]
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+/Limits [(struct_f_s_p___m___c_o_n_f_i_g_a568fb88a82ea595d6905297184f2cefb) (struct_f_s_p___m___c_o_n_f_i_g_a5796a69884a2b79a5ff7a17a036a2bee)]
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-/Limits [(struct_f_s_p___m___c_o_n_f_i_g_abeaf4aa8679427141c45988d43bb72c8) (struct_f_s_p___m___c_o_n_f_i_g_ac029fa929dd54ce52827318be231f517)]
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+/Limits [(struct_f_s_p___m___c_o_n_f_i_g_a57bdbe00c4b27b35157fab3c6e86c640) (struct_f_s_p___m___c_o_n_f_i_g_a5beefce76d863b94aba5e93f2316cf42)]
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-/Limits [(struct_f_s_p___m___c_o_n_f_i_g_ac053e643ebca7b23b986ee9a40512ee4) (struct_f_s_p___m___c_o_n_f_i_g_ac1fac6a53dedaec5418e67dc46749dc4)]
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+/Limits [(struct_f_s_p___m___c_o_n_f_i_g_a5c267eac238bd35ae72f483c4bcd9686) (struct_f_s_p___m___c_o_n_f_i_g_a61511c77388eb87a076ffb66925b0652)]
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-/Limits [(struct_f_s_p___m___c_o_n_f_i_g_ac279c8f64ef0206cb30dc1aa7d172d21) (struct_f_s_p___m___c_o_n_f_i_g_ac4ed724d1004c86b9917467529b173e0)]
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-/Limits [(struct_f_s_p___m___c_o_n_f_i_g_ac66036223e4418bfa2d770e83cf17027) (struct_f_s_p___m___c_o_n_f_i_g_ac7cb1bfc1dec9c9921ebe1c27f9e06c9)]
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-/Limits [(struct_f_s_p___m___c_o_n_f_i_g_ad353d3036f003ee3a05e7deb26940866) (struct_f_s_p___m___c_o_n_f_i_g_ad51d269770cf7a4531b9989a13408cb5)]
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+/Limits [(struct_f_s_p___m___c_o_n_f_i_g_a706cd3799ab3a353f3e0937cefcd08e6) (struct_f_s_p___m___c_o_n_f_i_g_a72d59e9c7decbad5881d3639e97f6e2b)]
 >>
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-/Limits [(struct_f_s_p___m___c_o_n_f_i_g_ad537c6b8d10f9c02ce62839e52b15392) (struct_f_s_p___m___c_o_n_f_i_g_ad72734deb39a28036db02a03fa5f589a)]
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 >>
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-/Limits [(struct_f_s_p___m___c_o_n_f_i_g_ad73079c634b1b8b558910a266904bca0) (struct_f_s_p___m___c_o_n_f_i_g_ad81e6977abcb92e14bd0fb76da15e31e)]
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 >>
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-/Limits [(struct_f_s_p___m___c_o_n_f_i_g_ad8a8f21e825485b47e5690891265b3df) (struct_f_s_p___m___c_o_n_f_i_g_adb451c45c7bd97b289247a92db584174)]
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 >>
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 >>
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-/Limits [(struct_f_s_p___m___c_o_n_f_i_g_ade8223ca590f0ce986a4054b19bac3d6) (struct_f_s_p___m___c_o_n_f_i_g_ae029a455f3e6b859cdcd8d4e9b5a7fdf)]
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 >>
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 >>
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 >>
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 >>
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-/Limits [(struct_f_s_p___m___c_o_n_f_i_g_aeca0469e4f3c0277e588b0928bc8523d) (struct_f_s_p___m___c_o_n_f_i_g_af0b66f1fb077a3495670ccc0ef787b05)]
+/Names [(struct_f_s_p___m___c_o_n_f_i_g_a92ac6c1428a0df1ad4caebb5fc15ad1a) 4466 0 R (struct_f_s_p___m___c_o_n_f_i_g_a92c41b402341c760c75d320444cd1dcc) 4745 0 R (struct_f_s_p___m___c_o_n_f_i_g_a9474643db748d60f60a477565698c241) 4901 0 R (struct_f_s_p___m___c_o_n_f_i_g_a9534bd9a4e3b135c45a6993477f38dfe) 4629 0 R (struct_f_s_p___m___c_o_n_f_i_g_a9540ca2f6a1bbd720a135685a1f9c7f7) 5152 0 R (struct_f_s_p___m___c_o_n_f_i_g_a957a69afeaf0c7ebb83ad09b71b54aa8) 4324 0 R]
+/Limits [(struct_f_s_p___m___c_o_n_f_i_g_a92ac6c1428a0df1ad4caebb5fc15ad1a) (struct_f_s_p___m___c_o_n_f_i_g_a957a69afeaf0c7ebb83ad09b71b54aa8)]
 >>
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 9983 0 obj
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-/Names [(struct_f_s_p___m___c_o_n_f_i_g_af1a5d0727af61d5e83685386d70a877a) 5245 0 R (struct_f_s_p___m___c_o_n_f_i_g_af1eb09d13b271d726e444df05bb51006) 4922 0 R (struct_f_s_p___m___c_o_n_f_i_g_af273e957ea9339082f4d99dd2b9bdf6f) 5372 0 R (struct_f_s_p___m___c_o_n_f_i_g_af27b2c14b9f8177623ac4ce555ec183f) 4724 0 R (struct_f_s_p___m___c_o_n_f_i_g_af2f7ba62aa35837178b59e139af48056) 4349 0 R (struct_f_s_p___m___c_o_n_f_i_g_af39e908434363c237c2e2a4f85869d24) 4775 0 R]
-/Limits [(struct_f_s_p___m___c_o_n_f_i_g_af1a5d0727af61d5e83685386d70a877a) (struct_f_s_p___m___c_o_n_f_i_g_af39e908434363c237c2e2a4f85869d24)]
+/Names [(struct_f_s_p___m___c_o_n_f_i_g_a96018e1edffe20c4f689144e988e45ed) 4482 0 R (struct_f_s_p___m___c_o_n_f_i_g_a9645162d3e43119d5d4e32b12aa58e1f) 5169 0 R (struct_f_s_p___m___c_o_n_f_i_g_a968b6384447575f9736528894379ce8e) 5260 0 R (struct_f_s_p___m___c_o_n_f_i_g_a97f76c37a58939c89893beea50ae54f0) 4315 0 R (struct_f_s_p___m___c_o_n_f_i_g_a981250037b759a86bab1a9a3e42c4849) 5108 0 R (struct_f_s_p___m___c_o_n_f_i_g_a988064510fcdebbbaa990eacb094a933) 5104 0 R]
+/Limits [(struct_f_s_p___m___c_o_n_f_i_g_a96018e1edffe20c4f689144e988e45ed) (struct_f_s_p___m___c_o_n_f_i_g_a988064510fcdebbbaa990eacb094a933)]
 >>
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 9984 0 obj
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-/Names [(struct_f_s_p___m___c_o_n_f_i_g_af3a604c3655184833d7a129aec3e738b) 4362 0 R (struct_f_s_p___m___c_o_n_f_i_g_af3d8afc15495d4f387d1af3b1710ab84) 5339 0 R (struct_f_s_p___m___c_o_n_f_i_g_af6fbce838682fec9e96dd6f8ecf657b6) 4263 0 R (struct_f_s_p___m___c_o_n_f_i_g_af71930a1b5dfba8f5875934bdd7a3178) 4563 0 R (struct_f_s_p___m___c_o_n_f_i_g_af78e12f231ab7980aff7ac2a9a899ce3) 4413 0 R (struct_f_s_p___m___c_o_n_f_i_g_af848c42419b6aab30a1a14f3e64e28a3) 4716 0 R]
-/Limits [(struct_f_s_p___m___c_o_n_f_i_g_af3a604c3655184833d7a129aec3e738b) (struct_f_s_p___m___c_o_n_f_i_g_af848c42419b6aab30a1a14f3e64e28a3)]
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+/Limits [(struct_f_s_p___m___c_o_n_f_i_g_a989b898866af9314c13ccc1c9d1e1481) (struct_f_s_p___m___c_o_n_f_i_g_a9b45dd220a151482af8c7d49b5cf78d4)]
 >>
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 9985 0 obj
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-/Names [(struct_f_s_p___m___c_o_n_f_i_g_af931b3436b66211ed6a0f00db98fcdf8) 5243 0 R (struct_f_s_p___m___c_o_n_f_i_g_af987599a959626a11fcdb9e18d030510) 5094 0 R (struct_f_s_p___m___c_o_n_f_i_g_af9b41e2a6eb1b393e310d028782d548f) 4567 0 R (struct_f_s_p___m___c_o_n_f_i_g_afad239d83b6d75fd168a3a3ec995faad) 4268 0 R (struct_f_s_p___m___c_o_n_f_i_g_afc1da26819e93a4f8ec1985d57c0eb05) 4410 0 R (struct_f_s_p___m___c_o_n_f_i_g_afc7d27f330df9933ee14c3e314d0dc53) 4315 0 R]
-/Limits [(struct_f_s_p___m___c_o_n_f_i_g_af931b3436b66211ed6a0f00db98fcdf8) (struct_f_s_p___m___c_o_n_f_i_g_afc7d27f330df9933ee14c3e314d0dc53)]
+/Names [(struct_f_s_p___m___c_o_n_f_i_g_a9bb45cce70d8673a5a23b1ee01078131) 5015 0 R (struct_f_s_p___m___c_o_n_f_i_g_a9be4db29a54c49dc2ba8b03045174124) 4980 0 R (struct_f_s_p___m___c_o_n_f_i_g_a9c40d687aa776a1434a699d3d8e1cf95) 4747 0 R (struct_f_s_p___m___c_o_n_f_i_g_a9c58a01b8bc360a12674feb664dd7fd1) 4316 0 R (struct_f_s_p___m___c_o_n_f_i_g_a9c89df31e9f38abed6e4220214226ed1) 5296 0 R (struct_f_s_p___m___c_o_n_f_i_g_a9d3bed899e9bcca0928c1cf89e463c04) 5018 0 R]
+/Limits [(struct_f_s_p___m___c_o_n_f_i_g_a9bb45cce70d8673a5a23b1ee01078131) (struct_f_s_p___m___c_o_n_f_i_g_a9d3bed899e9bcca0928c1cf89e463c04)]
 >>
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 9986 0 obj
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-/Names [(struct_f_s_p___m___c_o_n_f_i_g_afca7bf84fb26d7c2b3f43d782a03dbb4) 4316 0 R (struct_f_s_p___m___c_o_n_f_i_g_afccd4cc63f74c510407863b42c7dcb2b) 5144 0 R (struct_f_s_p___m___c_o_n_f_i_g_afd1df35cec594dcd39f2ed6847d8f0a7) 4631 0 R (struct_f_s_p___m___c_o_n_f_i_g_afd4ccbc22a56b2326db537ab056b014b) 4620 0 R (struct_f_s_p___m___c_o_n_f_i_g_afd5c705a145e6142f4b574dd055ed7a6) 4507 0 R (struct_f_s_p___m___c_o_n_f_i_g_afdb6533761b7a234665bcc117515ec65) 4558 0 R]
-/Limits [(struct_f_s_p___m___c_o_n_f_i_g_afca7bf84fb26d7c2b3f43d782a03dbb4) (struct_f_s_p___m___c_o_n_f_i_g_afdb6533761b7a234665bcc117515ec65)]
+/Names [(struct_f_s_p___m___c_o_n_f_i_g_a9e1792741b9ed3eb517f673bc46c0f74) 5162 0 R (struct_f_s_p___m___c_o_n_f_i_g_a9fc76c48bcfb572ee1dc15478ba332c9) 4797 0 R (struct_f_s_p___m___c_o_n_f_i_g_aa093ea09b4968f3debdd3b4c1e93e028) 4985 0 R (struct_f_s_p___m___c_o_n_f_i_g_aa0d5ed483b27eddc22ab0a7cb5e10c01) 5312 0 R (struct_f_s_p___m___c_o_n_f_i_g_aa15e9847eeb50ee156c160020d84e889) 4973 0 R (struct_f_s_p___m___c_o_n_f_i_g_aa15fb2fe57af2804940905570212e236) 5302 0 R]
+/Limits [(struct_f_s_p___m___c_o_n_f_i_g_a9e1792741b9ed3eb517f673bc46c0f74) (struct_f_s_p___m___c_o_n_f_i_g_aa15fb2fe57af2804940905570212e236)]
 >>
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 9987 0 obj
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-/Limits [(struct_f_s_p___m___c_o_n_f_i_g_afdf5891fb2de815fc3fceed7d71d7639) (struct_f_s_p___m___c_o_n_f_i_g_afef8d4146c888ecff96ececdefd5c3d5)]
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+/Limits [(struct_f_s_p___m___c_o_n_f_i_g_aa1b7ebc01bf46e5f74fde8afa86b2132) (struct_f_s_p___m___c_o_n_f_i_g_aa3e5ee43d47e95ca46dc9ceba72abb9e)]
 >>
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-/Limits [(struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g) (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a07b6fbb40bb96cde3ec1b9c216274524)]
+/Names [(struct_f_s_p___m___c_o_n_f_i_g_aa465b6b7ea1cfa094bf4f98ec35c5f80) 5165 0 R (struct_f_s_p___m___c_o_n_f_i_g_aa61301b54ad9e2a34fc8fa62a812654d) 5338 0 R (struct_f_s_p___m___c_o_n_f_i_g_aa6760cf0850246783b725937332e5b1f) 4378 0 R (struct_f_s_p___m___c_o_n_f_i_g_aa85a9db5873195190bbb535b8145b389) 4380 0 R (struct_f_s_p___m___c_o_n_f_i_g_aa8a3d27600d397f619ee5cd07f128045) 4487 0 R (struct_f_s_p___m___c_o_n_f_i_g_aa9759c4c8dea2f8429bc9b4004eaa3ca) 4634 0 R]
+/Limits [(struct_f_s_p___m___c_o_n_f_i_g_aa465b6b7ea1cfa094bf4f98ec35c5f80) (struct_f_s_p___m___c_o_n_f_i_g_aa9759c4c8dea2f8429bc9b4004eaa3ca)]
 >>
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-/Names [(struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a07ea574ca464aa2f22aaac35c4646464) 5761 0 R (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a097f065cee26d2793244522cd3aeb242) 5768 0 R (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a0998f79185f91846cf7a44b14f161335) 5834 0 R (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a0c125a2115e58185aaef770ce1adf50e) 5615 0 R (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a0d7f777f3b17948010f6bb92f83b470b) 5854 0 R (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a0e7b758a5e0d27686e3d25a896dc93eb) 5819 0 R]
-/Limits [(struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a07ea574ca464aa2f22aaac35c4646464) (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a0e7b758a5e0d27686e3d25a896dc93eb)]
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+/Limits [(struct_f_s_p___m___c_o_n_f_i_g_aa9c6463fdc6b44c6ee7b89f479d991db) (struct_f_s_p___m___c_o_n_f_i_g_aabb0e3bbebfe52ef4ebb349cef1ae0eb)]
 >>
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-/Limits [(struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a10b4ae7cd46fdb5463c6dd74bae42414) (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a17315b0ee3d81803c11e4f37257835b1)]
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+/Limits [(struct_f_s_p___m___c_o_n_f_i_g_aad37967969ab91b39f318c5d6f43c9f1) (struct_f_s_p___m___c_o_n_f_i_g_ab15e70ff46f439e12a0d1994cf80a2c2)]
 >>
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-/Limits [(struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a1c71fe20c82df5dbe0c0188bfbdb7b69) (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a25403d3de7ec064ddf2e08bfea4ec871)]
+/Names [(struct_f_s_p___m___c_o_n_f_i_g_ab17f0a1c02ff5cb51d6911f665f71793) 4732 0 R (struct_f_s_p___m___c_o_n_f_i_g_ab1b0560c1427a20ed852319f16087a4a) 4696 0 R (struct_f_s_p___m___c_o_n_f_i_g_ab1ca6fc90ee8700daaf4c4384b5b01ab) 5060 0 R (struct_f_s_p___m___c_o_n_f_i_g_ab279dce9e21a772cfde248a14ad597f1) 5262 0 R (struct_f_s_p___m___c_o_n_f_i_g_ab2a44fcb43e1074bdb54ce414c2a06b7) 5214 0 R (struct_f_s_p___m___c_o_n_f_i_g_ab32f3eee75e2296ac8f1f716e99b7916) 5119 0 R]
+/Limits [(struct_f_s_p___m___c_o_n_f_i_g_ab17f0a1c02ff5cb51d6911f665f71793) (struct_f_s_p___m___c_o_n_f_i_g_ab32f3eee75e2296ac8f1f716e99b7916)]
 >>
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-/Names [(struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a2625547588bc85eb6ce7adbd11792848) 5825 0 R (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a286d20056d021035437b1cd2723b051a) 5623 0 R (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a29173c1f4b99c705248ab5ce06b1b743) 5620 0 R (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a294a1d7aef5dc5595fd7c79b17dd5a65) 5848 0 R (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a364a9cd61692a4a34531b2eea7c4764c) 5722 0 R (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a3719bfaa0ed7eb3b40dfb35b29d7b152) 5584 0 R]
-/Limits [(struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a2625547588bc85eb6ce7adbd11792848) (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a3719bfaa0ed7eb3b40dfb35b29d7b152)]
+/Names [(struct_f_s_p___m___c_o_n_f_i_g_ab43bc63c19fb635af9ed7dcaceb94ec5) 5217 0 R (struct_f_s_p___m___c_o_n_f_i_g_ab4853657992729bbf07f260d310b0f5b) 5102 0 R (struct_f_s_p___m___c_o_n_f_i_g_ab488cbc95f3b675232ceceb4a4652399) 4939 0 R (struct_f_s_p___m___c_o_n_f_i_g_ab49bc70af9f998c55f647c42ebf548de) 4363 0 R (struct_f_s_p___m___c_o_n_f_i_g_ab4b17a6166006cf0a8e5c0dc777f48a5) 4326 0 R (struct_f_s_p___m___c_o_n_f_i_g_ab4ead122d348d65d8eb461f4119f4a37) 5076 0 R]
+/Limits [(struct_f_s_p___m___c_o_n_f_i_g_ab43bc63c19fb635af9ed7dcaceb94ec5) (struct_f_s_p___m___c_o_n_f_i_g_ab4ead122d348d65d8eb461f4119f4a37)]
 >>
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-/Names [(struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a39266f2cca73f9289cf00cae6f538962) 5853 0 R (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a3b471603c344603bcb7ceeff18f574d5) 5712 0 R (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a3c0042558953a433c6b1e373bd7ccbce) 5706 0 R (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a3ef6faef455f0cfb6148836f3b486356) 5763 0 R (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a405ea2b0c8c988fc867fc2050f28570e) 5719 0 R (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a411f4f68c13b471fd6409fd498f15401) 5814 0 R]
-/Limits [(struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a39266f2cca73f9289cf00cae6f538962) (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a411f4f68c13b471fd6409fd498f15401)]
+/Names [(struct_f_s_p___m___c_o_n_f_i_g_ab626399f60caf4943eadfe3f4181fb87) 4934 0 R (struct_f_s_p___m___c_o_n_f_i_g_ab66817f9337e423fc61d9346e748377b) 4733 0 R (struct_f_s_p___m___c_o_n_f_i_g_ab66f4b3c2882a85ed79429b373a69a83) 5310 0 R (struct_f_s_p___m___c_o_n_f_i_g_ab6c5443fa707b27b8da19e53f82e1604) 4370 0 R (struct_f_s_p___m___c_o_n_f_i_g_ab6cbe90a7dd338adc16b71fb624a5e18) 4522 0 R (struct_f_s_p___m___c_o_n_f_i_g_ab702d8bc2224547e5c50d9aa8238044b) 4360 0 R]
+/Limits [(struct_f_s_p___m___c_o_n_f_i_g_ab626399f60caf4943eadfe3f4181fb87) (struct_f_s_p___m___c_o_n_f_i_g_ab702d8bc2224547e5c50d9aa8238044b)]
 >>
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-/Names [(struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a484ca42093a5f341d71b3604b4bf08ba) 5780 0 R (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a486714ce414e4167ef66b5eb9d7567cd) 5632 0 R (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a48e9315da03a2f6b013c5ba1d4df80f5) 5770 0 R (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a49940c052b4ae486b4f5017457afbcf7) 5710 0 R (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a4bd8c941d081bd1ce1e9222b55f6c768) 5820 0 R (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a4ecc853cd62ee40685202a4bfdece5b1) 5830 0 R]
-/Limits [(struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a484ca42093a5f341d71b3604b4bf08ba) (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a4ecc853cd62ee40685202a4bfdece5b1)]
+/Names [(struct_f_s_p___m___c_o_n_f_i_g_ab80945c8fe0166b353f8cb430cc812c7) 4331 0 R (struct_f_s_p___m___c_o_n_f_i_g_ab926c06396ad6257d47c8d2fbf65a5c6) 4741 0 R (struct_f_s_p___m___c_o_n_f_i_g_ab9de26b12af293e94d0cb7de5b53877d) 5024 0 R (struct_f_s_p___m___c_o_n_f_i_g_aba0efd0422143dbca8a30f126337d73b) 4377 0 R (struct_f_s_p___m___c_o_n_f_i_g_aba479fd69def0687b968ecadb3e9d853) 5308 0 R (struct_f_s_p___m___c_o_n_f_i_g_abc7c5284dc2bbae0ffc2a7f3f7453255) 4529 0 R]
+/Limits [(struct_f_s_p___m___c_o_n_f_i_g_ab80945c8fe0166b353f8cb430cc812c7) (struct_f_s_p___m___c_o_n_f_i_g_abc7c5284dc2bbae0ffc2a7f3f7453255)]
 >>
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-/Names [(struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a4ed0a6e5a7bf49d4fda50d6453a84b6c) 5629 0 R (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a50dcccfbb60f0a30dcf90db9990df066) 5587 0 R (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a55fe565e5b1b1e1ed36b1e2f83bab7b5) 5667 0 R (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a5774cc8dde036a854dc5057bcb13a99b) 5718 0 R (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a584e78037d0fa1e55c747ae62e5d5dec) 5758 0 R (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a5870e629fa5655fdfb47fb0dc1c5d6cf) 5769 0 R]
-/Limits [(struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a4ed0a6e5a7bf49d4fda50d6453a84b6c) (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a5870e629fa5655fdfb47fb0dc1c5d6cf)]
+/Names [(struct_f_s_p___m___c_o_n_f_i_g_abca425fa7373c382c5b5554d03d379a3) 4787 0 R (struct_f_s_p___m___c_o_n_f_i_g_abcbdb0bf7e788099ba5fe46257a87807) 5164 0 R (struct_f_s_p___m___c_o_n_f_i_g_abce9af3bb4b148653bd322b8006554aa) 4429 0 R (struct_f_s_p___m___c_o_n_f_i_g_abd42211a08d7a8f2dcb336fa623a85bd) 4943 0 R (struct_f_s_p___m___c_o_n_f_i_g_abd808532f3640264b4e153124de8844e) 4976 0 R (struct_f_s_p___m___c_o_n_f_i_g_abe243f066804fc0ba7bada486a86e88f) 4473 0 R]
+/Limits [(struct_f_s_p___m___c_o_n_f_i_g_abca425fa7373c382c5b5554d03d379a3) (struct_f_s_p___m___c_o_n_f_i_g_abe243f066804fc0ba7bada486a86e88f)]
 >>
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-/Limits [(struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a5a518f00ac3855fc668a8662fab3f195) (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a615081aeacd7bdfea152581d90abcba9)]
+/Names [(struct_f_s_p___m___c_o_n_f_i_g_abeaf4aa8679427141c45988d43bb72c8) 4314 0 R (struct_f_s_p___m___c_o_n_f_i_g_abee59909b5469782ed69c2668c4b0ad1) 4594 0 R (struct_f_s_p___m___c_o_n_f_i_g_abf3ddc1982b5b334e5a22cc2a8b88e6d) 5016 0 R (struct_f_s_p___m___c_o_n_f_i_g_abf5b17f63c07cb54860f5e05eb94cd77) 5075 0 R (struct_f_s_p___m___c_o_n_f_i_g_abfabc08d06cd0efaa4f4280836024464) 5210 0 R (struct_f_s_p___m___c_o_n_f_i_g_ac029fa929dd54ce52827318be231f517) 4648 0 R]
+/Limits [(struct_f_s_p___m___c_o_n_f_i_g_abeaf4aa8679427141c45988d43bb72c8) (struct_f_s_p___m___c_o_n_f_i_g_ac029fa929dd54ce52827318be231f517)]
 >>
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-/Limits [(struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a63e77b1748016092f5ea060ba5e1df74) (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a679962723b07f244fcf13753594318f9)]
+/Names [(struct_f_s_p___m___c_o_n_f_i_g_ac053e643ebca7b23b986ee9a40512ee4) 5073 0 R (struct_f_s_p___m___c_o_n_f_i_g_ac07d5ca8f4d9a73ac37b546745f5a7d1) 4898 0 R (struct_f_s_p___m___c_o_n_f_i_g_ac0d74b331d2a8603203101f4d73e7350) 4422 0 R (struct_f_s_p___m___c_o_n_f_i_g_ac14ec4f08c5c560da4427beb864445f6) 5012 0 R (struct_f_s_p___m___c_o_n_f_i_g_ac1b8cf583a21d8f511f3f35917d33cda) 4596 0 R (struct_f_s_p___m___c_o_n_f_i_g_ac1fac6a53dedaec5418e67dc46749dc4) 4848 0 R]
+/Limits [(struct_f_s_p___m___c_o_n_f_i_g_ac053e643ebca7b23b986ee9a40512ee4) (struct_f_s_p___m___c_o_n_f_i_g_ac1fac6a53dedaec5418e67dc46749dc4)]
 >>
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-/Limits [(struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a67d30322216c22e5d68f1a8093c9ed34) (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a6e7d046185cf0b8c64d6b3923e9ef347)]
+/Names [(struct_f_s_p___m___c_o_n_f_i_g_ac279c8f64ef0206cb30dc1aa7d172d21) 5069 0 R (struct_f_s_p___m___c_o_n_f_i_g_ac2dd013b5f93a8c1827d3b4fc397dc31) 4322 0 R (struct_f_s_p___m___c_o_n_f_i_g_ac37a258b7506cc2e769e1c365bf0e934) 4699 0 R (struct_f_s_p___m___c_o_n_f_i_g_ac3dbc8993712f1c521a70bbaa9673baa) 5201 0 R (struct_f_s_p___m___c_o_n_f_i_g_ac43fd212fa92a578454b59b3f0a24bd7) 5066 0 R (struct_f_s_p___m___c_o_n_f_i_g_ac4ed724d1004c86b9917467529b173e0) 5113 0 R]
+/Limits [(struct_f_s_p___m___c_o_n_f_i_g_ac279c8f64ef0206cb30dc1aa7d172d21) (struct_f_s_p___m___c_o_n_f_i_g_ac4ed724d1004c86b9917467529b173e0)]
 >>
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-/Limits [(struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a6ea5eb47596c3a4acd8c77177310eaa6) (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a71377219c9dd9117ed2de72839312e22)]
+/Names [(struct_f_s_p___m___c_o_n_f_i_g_ac66036223e4418bfa2d770e83cf17027) 4940 0 R (struct_f_s_p___m___c_o_n_f_i_g_ac6a32b4b7be59dc04a77621242fb297e) 5299 0 R (struct_f_s_p___m___c_o_n_f_i_g_ac6c394d90acc084088b0a061f3abb21f) 4946 0 R (struct_f_s_p___m___c_o_n_f_i_g_ac748df58ce73716e8dad873eadc0a432) 4833 0 R (struct_f_s_p___m___c_o_n_f_i_g_ac7cb1bfc1dec9c9921ebe1c27f9e06c9) 5071 0 R (struct_f_s_p___m___c_o_n_f_i_g_ac84e05e159d7f7e56e47c2df8926c5a4) 4683 0 R]
+/Limits [(struct_f_s_p___m___c_o_n_f_i_g_ac66036223e4418bfa2d770e83cf17027) (struct_f_s_p___m___c_o_n_f_i_g_ac84e05e159d7f7e56e47c2df8926c5a4)]
 >>
 endobj
 10000 0 obj
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-/Names [(struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a747a7b8c25c32ab0ca31a3cd666f022f) 5628 0 R (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a75788229762d7f6cfc80516175a89ca8) 5658 0 R (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a7608857d3efc50b1033b15887d1559b7) 5716 0 R (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a7632da7dcec0b2a60e83dff95f2190a1) 5626 0 R (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a769bdf6ae9f6fdd4e924b405bfee2f3d) 5852 0 R (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a77e3d7424a25387eab88727194ecabdd) 5827 0 R]
-/Limits [(struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a747a7b8c25c32ab0ca31a3cd666f022f) (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a77e3d7424a25387eab88727194ecabdd)]
+/Names [(struct_f_s_p___m___c_o_n_f_i_g_ac8cf8c8ceb72ed3afa974da838f6bc7c) 4590 0 R (struct_f_s_p___m___c_o_n_f_i_g_ac969c20fd07f2ed148fc6472c01d6c5a) 4570 0 R (struct_f_s_p___m___c_o_n_f_i_g_ac9f138aa65b6411d3b5bfa9da15f05ff) 5116 0 R (struct_f_s_p___m___c_o_n_f_i_g_ac9fca34a81f4b64ee1de94dc5486b153) 4981 0 R (struct_f_s_p___m___c_o_n_f_i_g_aca19c953a88f9b0bb07dacfc7b06c679) 5103 0 R (struct_f_s_p___m___c_o_n_f_i_g_acbb514a413b5e0d37cf24934b2324ccf) 5272 0 R]
+/Limits [(struct_f_s_p___m___c_o_n_f_i_g_ac8cf8c8ceb72ed3afa974da838f6bc7c) (struct_f_s_p___m___c_o_n_f_i_g_acbb514a413b5e0d37cf24934b2324ccf)]
 >>
 endobj
 10001 0 obj
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-/Names [(struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a784b313e71ce97db25f359f33849f049) 5669 0 R (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a79f7b16fcdf09e2b85f63deaf1673093) 5590 0 R (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a7adc8e3776465f4a370c3cc7dfbe78ba) 5782 0 R (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a7b0612863346c236aebdaefe8f52add3) 5728 0 R (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a7f6f412fb97763a02e555c200d9c8db1) 5672 0 R (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a8af6a6295b9a944c0dc3aef1815d05bb) 5773 0 R]
-/Limits [(struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a784b313e71ce97db25f359f33849f049) (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a8af6a6295b9a944c0dc3aef1815d05bb)]
+/Names [(struct_f_s_p___m___c_o_n_f_i_g_acc65b699f5d33508681fedb85066b5e3) 4381 0 R (struct_f_s_p___m___c_o_n_f_i_g_acd6907d9c36b58fa32bb46ee15da67c7) 5117 0 R (struct_f_s_p___m___c_o_n_f_i_g_acd7ef4b2d9d63088189148d83e1f060e) 4313 0 R (struct_f_s_p___m___c_o_n_f_i_g_acd8f250dcfb2e862fa95225a95f99ff3) 4691 0 R (struct_f_s_p___m___c_o_n_f_i_g_acda7a4f0d07e4e6934985e0bc531870a) 5212 0 R (struct_f_s_p___m___c_o_n_f_i_g_acdc59fe80d1cbf49fa4969abcda7c38f) 4749 0 R]
+/Limits [(struct_f_s_p___m___c_o_n_f_i_g_acc65b699f5d33508681fedb85066b5e3) (struct_f_s_p___m___c_o_n_f_i_g_acdc59fe80d1cbf49fa4969abcda7c38f)]
 >>
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 10002 0 obj
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-/Names [(struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a8b78a9f9aa9e7bca9df6aac22f25bc35) 5821 0 R (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a8bd24abcb8f687245be348546807700a) 5588 0 R (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a8f92c147ac8315622aef56c686c9620d) 5762 0 R (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a93e37cd7ce3a3e2ba6394ea7866e7ee0) 5766 0 R (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a944d74268a9bb1c00a009a84d056d787) 5815 0 R (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a959a8c89d7af832058890e4c42c67b3c) 5724 0 R]
-/Limits [(struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a8b78a9f9aa9e7bca9df6aac22f25bc35) (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a959a8c89d7af832058890e4c42c67b3c)]
+/Names [(struct_f_s_p___m___c_o_n_f_i_g_ace85291438d0e16e661fb149bdc8cba4) 4642 0 R (struct_f_s_p___m___c_o_n_f_i_g_aceb31bffe7bc9a6ac759316ad922f63a) 4694 0 R (struct_f_s_p___m___c_o_n_f_i_g_acf1da7545e17c056c3474dff4b7f6731) 4320 0 R (struct_f_s_p___m___c_o_n_f_i_g_acf242ad735711bc0f216d75b67a2b06f) 4536 0 R (struct_f_s_p___m___c_o_n_f_i_g_acfeed957fb01d787032d13c484d89fcf) 5349 0 R (struct_f_s_p___m___c_o_n_f_i_g_ad052098e1d5b17160ad75c2d97b40708) 4587 0 R]
+/Limits [(struct_f_s_p___m___c_o_n_f_i_g_ace85291438d0e16e661fb149bdc8cba4) (struct_f_s_p___m___c_o_n_f_i_g_ad052098e1d5b17160ad75c2d97b40708)]
 >>
 endobj
 10003 0 obj
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-/Names [(struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a96c12860e912d8f0a7589eb02b41495d) 5661 0 R (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a9a7d74c15892f9b8835a2dd112faf842) 5677 0 R (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a9dbe3f3cbdeec650d9f7ae6507832538) 5586 0 R (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a9ebb97444c6e93bae46a2ec66d0a9d46) 5675 0 R (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_aa0e3245c5747c5bb8404bb465f3df578) 5616 0 R (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_aa16e8119f825fdca7f0e41438115101e) 5831 0 R]
-/Limits [(struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a96c12860e912d8f0a7589eb02b41495d) (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_aa16e8119f825fdca7f0e41438115101e)]
+/Names [(struct_f_s_p___m___c_o_n_f_i_g_ad0a47964ff490b9f0aaf58cc19e69b92) 5154 0 R (struct_f_s_p___m___c_o_n_f_i_g_ad199a9d6960afcc0129165ca3ab63896) 4523 0 R (struct_f_s_p___m___c_o_n_f_i_g_ad1ed5188881af1b8a49a8e5880cbf662) 4275 0 R (struct_f_s_p___m___c_o_n_f_i_g_ad20a077b4738273c23010fe936f730c3) 4479 0 R (struct_f_s_p___m___c_o_n_f_i_g_ad25b3b800dd679d24fa1d32702e111c8) 4750 0 R (struct_f_s_p___m___c_o_n_f_i_g_ad287c0f935c3283978b5a01bd707f167) 5167 0 R]
+/Limits [(struct_f_s_p___m___c_o_n_f_i_g_ad0a47964ff490b9f0aaf58cc19e69b92) (struct_f_s_p___m___c_o_n_f_i_g_ad287c0f935c3283978b5a01bd707f167)]
 >>
 endobj
 10004 0 obj
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-/Names [(struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_aa4e05b1a1012ec830a98ac0799db924f) 5663 0 R (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_aa890308e9b2e0fde0c05388c5bcb25d7) 5711 0 R (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_aaa0c920049bf80d6975a4dd13063f458) 5847 0 R (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_aab56fb62f8837a72bdaee5e73f53d072) 5727 0 R (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_aabd702c0f9fa11360cd17f10493931c4) 5826 0 R (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_aaf2b094722307e7a4fce8e082b9b3531) 5812 0 R]
-/Limits [(struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_aa4e05b1a1012ec830a98ac0799db924f) (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_aaf2b094722307e7a4fce8e082b9b3531)]
+/Names [(struct_f_s_p___m___c_o_n_f_i_g_ad353d3036f003ee3a05e7deb26940866) 5204 0 R (struct_f_s_p___m___c_o_n_f_i_g_ad3bac7ae82392e83af40c112aefaa3db) 5311 0 R (struct_f_s_p___m___c_o_n_f_i_g_ad4284bdd8d1af9e22f1e465e220340c9) 4321 0 R (struct_f_s_p___m___c_o_n_f_i_g_ad45c634ab3d62162561957b8d99b05bd) 4882 0 R (struct_f_s_p___m___c_o_n_f_i_g_ad463788dd058ae0d60ba1c342e665dc4) 5106 0 R (struct_f_s_p___m___c_o_n_f_i_g_ad51d269770cf7a4531b9989a13408cb5) 4532 0 R]
+/Limits [(struct_f_s_p___m___c_o_n_f_i_g_ad353d3036f003ee3a05e7deb26940866) (struct_f_s_p___m___c_o_n_f_i_g_ad51d269770cf7a4531b9989a13408cb5)]
 >>
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 10005 0 obj
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-/Names [(struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_abd0659c8ff70e4337cfe8678c8922a3e) 5833 0 R (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_ac31acd50be1b6e737f8a7819e198a403) 5717 0 R (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_ac45a48e105300c451f1c69a6bd35f039) 5774 0 R (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_ac4f61f2aa2a5bbb6c93ed81db0bac2a5) 5705 0 R (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_ac9e0e42bb8cc7e93268e6b7a3816d239) 5671 0 R (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_acb0f0dc6509d9b00aaba97ca7aad32b3) 5664 0 R]
-/Limits [(struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_abd0659c8ff70e4337cfe8678c8922a3e) (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_acb0f0dc6509d9b00aaba97ca7aad32b3)]
+/Names [(struct_f_s_p___m___c_o_n_f_i_g_ad537c6b8d10f9c02ce62839e52b15392) 4793 0 R (struct_f_s_p___m___c_o_n_f_i_g_ad539485bf638d4254eb9d15b98a6b0aa) 4984 0 R (struct_f_s_p___m___c_o_n_f_i_g_ad5e987a91bc3edd8ec9b1dec2e95ac07) 4739 0 R (struct_f_s_p___m___c_o_n_f_i_g_ad632e845789afda4dcf4f74208c0fa92) 5216 0 R (struct_f_s_p___m___c_o_n_f_i_g_ad6ef4abdcb978469fb5422efba6ee796) 4778 0 R (struct_f_s_p___m___c_o_n_f_i_g_ad72734deb39a28036db02a03fa5f589a) 4645 0 R]
+/Limits [(struct_f_s_p___m___c_o_n_f_i_g_ad537c6b8d10f9c02ce62839e52b15392) (struct_f_s_p___m___c_o_n_f_i_g_ad72734deb39a28036db02a03fa5f589a)]
 >>
 endobj
 10006 0 obj
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-/Names [(struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_acd07a58f717ffbf95b8e4ec9918cf264) 5659 0 R (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_acdb0c1d109fa7eb73f3ded823642c652) 5625 0 R (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_ace3233e947aa4d641ec6909f3db4c788) 5771 0 R (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_acf771a2082fd23b316d294760a865a6b) 5660 0 R (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_ad2a915a9152cfee49a8cdb40b222d0ed) 5624 0 R (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_ad7993e54150f32e4708bff0ddce0f8bf) 5818 0 R]
-/Limits [(struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_acd07a58f717ffbf95b8e4ec9918cf264) (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_ad7993e54150f32e4708bff0ddce0f8bf)]
+/Names [(struct_f_s_p___m___c_o_n_f_i_g_ad73079c634b1b8b558910a266904bca0) 4595 0 R (struct_f_s_p___m___c_o_n_f_i_g_ad734372a2f03b3b157870c162cf07496) 5309 0 R (struct_f_s_p___m___c_o_n_f_i_g_ad73479a945618a85c2fd7d48510ee0cc) 4584 0 R (struct_f_s_p___m___c_o_n_f_i_g_ad78066687760b98425256f03e562675f) 4433 0 R (struct_f_s_p___m___c_o_n_f_i_g_ad7bd50d4cae3dd53edd2e129b4c2b0d1) 4540 0 R (struct_f_s_p___m___c_o_n_f_i_g_ad81e6977abcb92e14bd0fb76da15e31e) 4744 0 R]
+/Limits [(struct_f_s_p___m___c_o_n_f_i_g_ad73079c634b1b8b558910a266904bca0) (struct_f_s_p___m___c_o_n_f_i_g_ad81e6977abcb92e14bd0fb76da15e31e)]
 >>
 endobj
 10007 0 obj
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-/Limits [(struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_ad7d199a30661bae30d7752704b1e2c1e) (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_ae2a2b0f5eacd99e3ca83ca5da0e0bf0d)]
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+/Limits [(struct_f_s_p___m___c_o_n_f_i_g_ad8a8f21e825485b47e5690891265b3df) (struct_f_s_p___m___c_o_n_f_i_g_adb451c45c7bd97b289247a92db584174)]
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-/Limits [(struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_ae77815b736269b79f3ef412484331603) (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_af71deb7dd655a5bd08d817b62502fd11)]
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-/Limits [(struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_afbe66a8268afdc01f5365226f6647d12) (struct_f_s_p___s___c_o_n_f_i_g_a0152356163d38d974cb1ea64bd8bf2cf)]
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-/Limits [(struct_f_s_p___s___c_o_n_f_i_g_a01b1f85f2651d2bf36ecf09668fc1f6b) (struct_f_s_p___s___c_o_n_f_i_g_a03138128234dbb359744dead3409d84a)]
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-/Limits [(struct_f_s_p___s___c_o_n_f_i_g_a037e8f5c73d8ecf5b1f07cd2128e0300) (struct_f_s_p___s___c_o_n_f_i_g_a057c9e78559acb3249c3ce9474676a08)]
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+/Limits [(struct_f_s_p___m___c_o_n_f_i_g_af3a604c3655184833d7a129aec3e738b) (struct_f_s_p___m___c_o_n_f_i_g_af848c42419b6aab30a1a14f3e64e28a3)]
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-/Limits [(struct_f_s_p___s___c_o_n_f_i_g_a11184d3f7368db5d23b5b6038df6bfcd) (struct_f_s_p___s___c_o_n_f_i_g_a13485c09f9d30c71e863214f97a77963)]
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+/Limits [(struct_f_s_p___m___c_o_n_f_i_g_af931b3436b66211ed6a0f00db98fcdf8) (struct_f_s_p___m___c_o_n_f_i_g_afc7d27f330df9933ee14c3e314d0dc53)]
 >>
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-/Limits [(struct_f_s_p___s___c_o_n_f_i_g_a162086652cc3b31c9315d305020eacd6) (struct_f_s_p___s___c_o_n_f_i_g_a180552c3db85afd0199394df9c555594)]
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+/Limits [(struct_f_s_p___m___c_o_n_f_i_g_afca7bf84fb26d7c2b3f43d782a03dbb4) (struct_f_s_p___m___c_o_n_f_i_g_afdb6533761b7a234665bcc117515ec65)]
 >>
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-/Limits [(struct_f_s_p___s___c_o_n_f_i_g_a18481752c4f951d496b17758ba49160b) (struct_f_s_p___s___c_o_n_f_i_g_a1a9634864387580c886b5128a06151ca)]
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+/Limits [(struct_f_s_p___m___c_o_n_f_i_g_afdf5891fb2de815fc3fceed7d71d7639) (struct_f_s_p___m___c_o_n_f_i_g_afef8d4146c888ecff96ececdefd5c3d5)]
 >>
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-/Limits [(struct_f_s_p___s___c_o_n_f_i_g_a1ae27157027e8c1715dc037f1858712b) (struct_f_s_p___s___c_o_n_f_i_g_a1c92dc6fd5bbefd62353e088221568a4)]
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+/Limits [(struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g) (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a07b6fbb40bb96cde3ec1b9c216274524)]
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-/Limits [(struct_f_s_p___s___c_o_n_f_i_g_a1d7468869534d6b92ee718ee7f310ce6) (struct_f_s_p___s___c_o_n_f_i_g_a1e56a5a5072434acf1376189a45a6595)]
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+/Limits [(struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a07ea574ca464aa2f22aaac35c4646464) (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a0e7b758a5e0d27686e3d25a896dc93eb)]
 >>
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-/Limits [(struct_f_s_p___s___c_o_n_f_i_g_a1e6b136a17d7163d7d012ddaad4ecf12) (struct_f_s_p___s___c_o_n_f_i_g_a2017fbc729c351af9b996c5c2e6f2ed0)]
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 >>
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-/Limits [(struct_f_s_p___s___c_o_n_f_i_g_a2069e577fa2425512de2448780a51030) (struct_f_s_p___s___c_o_n_f_i_g_a23eac96ff8944aed5320d500945f73b4)]
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 >>
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-/Limits [(struct_f_s_p___s___c_o_n_f_i_g_a24d9e25038b36e25014ec07087095d27) (struct_f_s_p___s___c_o_n_f_i_g_a2626fabeb9c8806ac902bee91a49b2e5)]
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 >>
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 10025 0 obj
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-/Limits [(struct_f_s_p___s___c_o_n_f_i_g_a26a93736d7611a48878817560bf8b243) (struct_f_s_p___s___c_o_n_f_i_g_a27ce6c17eb3398f8cd4e355bc891c72b)]
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+/Limits [(struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a3b471603c344603bcb7ceeff18f574d5) (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a484ca42093a5f341d71b3604b4bf08ba)]
 >>
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-/Limits [(struct_f_s_p___s___c_o_n_f_i_g_a27f66e35d01a4ccd67930e84122becb0) (struct_f_s_p___s___c_o_n_f_i_g_a2928c5a122e6cec65328f67b1c82d25c)]
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+/Limits [(struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a486714ce414e4167ef66b5eb9d7567cd) (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a4ed0a6e5a7bf49d4fda50d6453a84b6c)]
 >>
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-/Limits [(struct_f_s_p___s___c_o_n_f_i_g_a2995b65eba71d20318cdcf363bc9ad7b) (struct_f_s_p___s___c_o_n_f_i_g_a2df97e2aa36c0d2d71f67b274ea5996d)]
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+/Limits [(struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a50dcccfbb60f0a30dcf90db9990df066) (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a5a518f00ac3855fc668a8662fab3f195)]
 >>
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-/Limits [(struct_f_s_p___s___c_o_n_f_i_g_a2e1774eeeccc95d9b83b4960e0f5b71c) (struct_f_s_p___s___c_o_n_f_i_g_a30425aeb417f496bd1735bd70b092384)]
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+/Limits [(struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a5cc034e0d1d559e466f987ab6bb9e493) (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a63e77b1748016092f5ea060ba5e1df74)]
 >>
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-/Limits [(struct_f_s_p___s___c_o_n_f_i_g_a318f65d78026fd3d6bc5410c4fe949c1) (struct_f_s_p___s___c_o_n_f_i_g_a34c81cc9daad21fe7a62d9eb16ffab85)]
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+/Limits [(struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a66439a2f2e54a40ba7f2a056a9a28caa) (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a67d30322216c22e5d68f1a8093c9ed34)]
 >>
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-/Limits [(struct_f_s_p___s___c_o_n_f_i_g_a35268f25768d69d0c4e04aada077c145) (struct_f_s_p___s___c_o_n_f_i_g_a37bc9e23143a50a7bd9e4dd7f207cc0d)]
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+/Limits [(struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a69b10a21892048fd40ece9267f0644ce) (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a6fa8dd247b77e0533e9e80485eb642e0)]
 >>
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-/Limits [(struct_f_s_p___s___c_o_n_f_i_g_a386271178601c0e21ed058937ddd16ae) (struct_f_s_p___s___c_o_n_f_i_g_a3956614027d6db4f9c1e8d45eaf4ca5e)]
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+/Limits [(struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a7040caf32ef7a010f00eb3b552ab4148) (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a747a7b8c25c32ab0ca31a3cd666f022f)]
 >>
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-/Limits [(struct_f_s_p___s___c_o_n_f_i_g_a39f7a4fd58f89ad79b2acb52b28f31f3) (struct_f_s_p___s___c_o_n_f_i_g_a3cac88ff422c9aa4af1f7b1482166e82)]
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 >>
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-/Limits [(struct_f_s_p___s___c_o_n_f_i_g_a3d2ee702d86026966ce1fb8ed43a4524) (struct_f_s_p___s___c_o_n_f_i_g_a3eb1e42a253777b420f5aec5b716e7e7)]
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+/Limits [(struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a79f7b16fcdf09e2b85f63deaf1673093) (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a8af6a6295b9a944c0dc3aef1815d05bb)]
 >>
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 10034 0 obj
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-/Limits [(struct_f_s_p___s___c_o_n_f_i_g_a3eb9dd6b2ece938320292a9da882dc9e) (struct_f_s_p___s___c_o_n_f_i_g_a414f9b19847933581b9125a766636562)]
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+/Limits [(struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a8b78a9f9aa9e7bca9df6aac22f25bc35) (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a96c12860e912d8f0a7589eb02b41495d)]
 >>
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 10035 0 obj
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-/Limits [(struct_f_s_p___s___c_o_n_f_i_g_a41add56e62567f44064e2cd4fb6eedf7) (struct_f_s_p___s___c_o_n_f_i_g_a42ef6e97566dc6766dae501c18b9c5fd)]
+/Names [(struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a9a7d74c15892f9b8835a2dd112faf842) 5696 0 R (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a9dbe3f3cbdeec650d9f7ae6507832538) 5605 0 R (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a9ebb97444c6e93bae46a2ec66d0a9d46) 5694 0 R (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_aa0e3245c5747c5bb8404bb465f3df578) 5635 0 R (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_aa16e8119f825fdca7f0e41438115101e) 5850 0 R (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_aa4e05b1a1012ec830a98ac0799db924f) 5682 0 R]
+/Limits [(struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a9a7d74c15892f9b8835a2dd112faf842) (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_aa4e05b1a1012ec830a98ac0799db924f)]
 >>
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 10036 0 obj
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-/Limits [(struct_f_s_p___s___c_o_n_f_i_g_a43e8d4d2b1f2d97ff8fa6faf6bbc63fe) (struct_f_s_p___s___c_o_n_f_i_g_a45d19f709f1ba9dc6742b93af0866c87)]
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+/Limits [(struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_aa890308e9b2e0fde0c05388c5bcb25d7) (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_abe13c6dedb6fc99b15d9be66a08e3336)]
 >>
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-/Limits [(struct_f_s_p___s___c_o_n_f_i_g_a467ca53708f888de60142604df333643) (struct_f_s_p___s___c_o_n_f_i_g_a4855ccbf9db030ddaef65e93c85361a3)]
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+/Limits [(struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_ac31acd50be1b6e737f8a7819e198a403) (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_acd07a58f717ffbf95b8e4ec9918cf264)]
 >>
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-/Limits [(struct_f_s_p___s___c_o_n_f_i_g_a48a26d1036183d03905295c3717fd67f) (struct_f_s_p___s___c_o_n_f_i_g_a4a7154fc9b18a24f195b735e4fa3cadf)]
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+/Limits [(struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_acdb0c1d109fa7eb73f3ded823642c652) (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_ad7d199a30661bae30d7752704b1e2c1e)]
 >>
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 10039 0 obj
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-/Limits [(struct_f_s_p___s___c_o_n_f_i_g_a4a7ef6358e0a34d3a1f03e600b3d0d08) (struct_f_s_p___s___c_o_n_f_i_g_a4d6aa433cb70b049711ff8a9476b77e2)]
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+/Limits [(struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_adb34d7413dc9c5440da8871d7b5e42f3) (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_ae77815b736269b79f3ef412484331603)]
 >>
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-/Limits [(struct_f_s_p___s___c_o_n_f_i_g_a4e43c710385d612de08ed99b7092123f) (struct_f_s_p___s___c_o_n_f_i_g_a50733ac800f6468b81ea27221bfc9640)]
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+/Limits [(struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_ae991b500f999c1a3ddc55d552a2170c1) (struct_f_s_p___m___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_afbe66a8268afdc01f5365226f6647d12)]
 >>
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-/Limits [(struct_f_s_p___s___c_o_n_f_i_g_ae5f5ea0c0ac36dacb24beb8dd91257c6) (struct_f_s_p___s___c_o_n_f_i_g_ae83e55e771ff119098fd34385bae3623)]
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-/Limits [(struct_f_s_p___s___c_o_n_f_i_g_ae9c76604c2a39d5241dc54effa8b994c) (struct_f_s_p___s___c_o_n_f_i_g_aea9dc2d599b291c9dbfb2e1b604a05d7)]
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-/Limits [(struct_f_s_p___s___c_o_n_f_i_g_afd68354c293a3088a3fb7554bd51b508) (struct_f_s_p___s___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g)]
+/Names [(struct_f_s_p___s___c_o_n_f_i_g_aaccdcaae4d755b323815a10d0b133dd1) 6460 0 R (struct_f_s_p___s___c_o_n_f_i_g_aad12cb2a0c653804dbe6206a290760c1) 6471 0 R (struct_f_s_p___s___c_o_n_f_i_g_aad2ff88df295ed146412429e0ad38993) 7012 0 R (struct_f_s_p___s___c_o_n_f_i_g_aad4c342c9f6fab39908412e64367af7f) 6427 0 R (struct_f_s_p___s___c_o_n_f_i_g_aae92b596fa76b3e8ba4b8106fb9fe8fe) 7119 0 R (struct_f_s_p___s___c_o_n_f_i_g_aaeacca58ded85d4764de66b6a5b07bec) 6408 0 R]
+/Limits [(struct_f_s_p___s___c_o_n_f_i_g_aaccdcaae4d755b323815a10d0b133dd1) (struct_f_s_p___s___c_o_n_f_i_g_aaeacca58ded85d4764de66b6a5b07bec)]
 >>
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 10112 0 obj
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-/Names [(struct_f_s_p___s___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a01244f106b7aea65ec79a68cfbe6e6f0) 7707 0 R (struct_f_s_p___s___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a01ba0912c055964fffad05c8a1f96aa4) 7609 0 R (struct_f_s_p___s___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a02fb6e44b8b0d27a9546943f62e89d81) 7751 0 R (struct_f_s_p___s___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a0336ae34b0a92ca716130325835f8f34) 7791 0 R (struct_f_s_p___s___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a03ce1e20aa1b70efa74ed6e09b1beac2) 7653 0 R (struct_f_s_p___s___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a08f2cd0c9010831d87d51c90251c8a05) 7783 0 R]
-/Limits [(struct_f_s_p___s___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a01244f106b7aea65ec79a68cfbe6e6f0) (struct_f_s_p___s___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a08f2cd0c9010831d87d51c90251c8a05)]
+/Names [(struct_f_s_p___s___c_o_n_f_i_g_aaecaf69781ac2d136112d73427430762) 6667 0 R (struct_f_s_p___s___c_o_n_f_i_g_aaedb9c57143e47ada20a2857fa7d8b5e) 6429 0 R (struct_f_s_p___s___c_o_n_f_i_g_aaf0249341f7ccc89111203ddede364be) 7022 0 R (struct_f_s_p___s___c_o_n_f_i_g_aafb3f182af4ea027fbabc26f859f81cf) 6834 0 R (struct_f_s_p___s___c_o_n_f_i_g_ab008304a77748b00308f01fb4020914a) 7125 0 R (struct_f_s_p___s___c_o_n_f_i_g_ab05d866d16bc35a6a860b715d8e5d38f) 6099 0 R]
+/Limits [(struct_f_s_p___s___c_o_n_f_i_g_aaecaf69781ac2d136112d73427430762) (struct_f_s_p___s___c_o_n_f_i_g_ab05d866d16bc35a6a860b715d8e5d38f)]
 >>
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 10113 0 obj
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-/Limits [(struct_f_s_p___s___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a09ce10c727d35d70ffbe7c3a944a923e) (struct_f_s_p___s___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a12462c33281618a8b1d0b646ca6efff3)]
+/Names [(struct_f_s_p___s___c_o_n_f_i_g_ab06a036fa5312fe57df7d07872a7ca41) 7130 0 R (struct_f_s_p___s___c_o_n_f_i_g_ab0845f6c6f3172ebefe229ed4ec04ba3) 6672 0 R (struct_f_s_p___s___c_o_n_f_i_g_ab0b82260d257e8eaba64686dcdf160ba) 6237 0 R (struct_f_s_p___s___c_o_n_f_i_g_ab0edcbdee605791370a21d739674d1a3) 7031 0 R (struct_f_s_p___s___c_o_n_f_i_g_ab100fb7f1399893957b12f7da475b002) 7014 0 R (struct_f_s_p___s___c_o_n_f_i_g_ab1733ae4d28869474736bcff06948939) 6630 0 R]
+/Limits [(struct_f_s_p___s___c_o_n_f_i_g_ab06a036fa5312fe57df7d07872a7ca41) (struct_f_s_p___s___c_o_n_f_i_g_ab1733ae4d28869474736bcff06948939)]
 >>
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-/Limits [(struct_f_s_p___s___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a15a3039424ac2fd75009fa68e3d75499) (struct_f_s_p___s___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a19d312d13dee188f702c619bb1b97a32)]
+/Names [(struct_f_s_p___s___c_o_n_f_i_g_ab18688001b472cb10fa0e64ac2edd5b9) 7017 0 R (struct_f_s_p___s___c_o_n_f_i_g_ab1a79ddcdfe4bd5e9c14ee15baa0f21f) 6509 0 R (struct_f_s_p___s___c_o_n_f_i_g_ab1cfba998807975a5911ccaf60121b20) 5964 0 R (struct_f_s_p___s___c_o_n_f_i_g_ab21097317aa79a5c2d8f7bc266672e91) 7075 0 R (struct_f_s_p___s___c_o_n_f_i_g_ab2793a697034426ce30cbdcc76ea749a) 7172 0 R (struct_f_s_p___s___c_o_n_f_i_g_ab2e3e35f2313f30c6ee2f81474214e94) 6819 0 R]
+/Limits [(struct_f_s_p___s___c_o_n_f_i_g_ab18688001b472cb10fa0e64ac2edd5b9) (struct_f_s_p___s___c_o_n_f_i_g_ab2e3e35f2313f30c6ee2f81474214e94)]
 >>
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 10115 0 obj
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-/Limits [(struct_f_s_p___s___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a1b4f4250992bfb1703e83cca49cc075b) (struct_f_s_p___s___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a2270043c7cba8b7008699c91bd2ee884)]
+/Names [(struct_f_s_p___s___c_o_n_f_i_g_ab3951b3113194eeff5348c39924bdbb5) 7029 0 R (struct_f_s_p___s___c_o_n_f_i_g_ab3db6564c1a4f52cc1ee06342277623c) 6044 0 R (struct_f_s_p___s___c_o_n_f_i_g_ab56ae9db6819f9e61d8a28dcfeb91454) 7170 0 R (struct_f_s_p___s___c_o_n_f_i_g_ab6d6c9a6967334f7515eb7a38a2e7e26) 6473 0 R (struct_f_s_p___s___c_o_n_f_i_g_ab6dff5aaabbf9299115653c49f158465) 5951 0 R (struct_f_s_p___s___c_o_n_f_i_g_ab70061990e812ce26c771a4ee8c46b7b) 7181 0 R]
+/Limits [(struct_f_s_p___s___c_o_n_f_i_g_ab3951b3113194eeff5348c39924bdbb5) (struct_f_s_p___s___c_o_n_f_i_g_ab70061990e812ce26c771a4ee8c46b7b)]
 >>
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 10116 0 obj
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-/Limits [(struct_f_s_p___s___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a23cd875bc3c597d5387cd09dd341d044) (struct_f_s_p___s___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a2e6e34b2735ec62497d5e9e3c924504d)]
+/Names [(struct_f_s_p___s___c_o_n_f_i_g_ab88c38293f05011c55edf86b6a04bca1) 6789 0 R (struct_f_s_p___s___c_o_n_f_i_g_ab8d35df3bc139fbd267c4f59a4c6fc4a) 6087 0 R (struct_f_s_p___s___c_o_n_f_i_g_ab967cabf28d82d52277a04ad588f3696) 7080 0 R (struct_f_s_p___s___c_o_n_f_i_g_ab9860abae5fe9a78bf67a3b541bb1e06) 7064 0 R (struct_f_s_p___s___c_o_n_f_i_g_ab998ff06c65c1118cfa182896546c565) 7111 0 R (struct_f_s_p___s___c_o_n_f_i_g_ab9aa8abfbd77a02f0894a9b80df75b44) 7015 0 R]
+/Limits [(struct_f_s_p___s___c_o_n_f_i_g_ab88c38293f05011c55edf86b6a04bca1) (struct_f_s_p___s___c_o_n_f_i_g_ab9aa8abfbd77a02f0894a9b80df75b44)]
 >>
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-/Limits [(struct_f_s_p___s___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a33189608dc4005e180b9544e2322e008) (struct_f_s_p___s___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a39b07c192e52adb6435ce61153dff0a9)]
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+/Limits [(struct_f_s_p___s___c_o_n_f_i_g_abb5a783ade2cee07ce1901e033100f7f) (struct_f_s_p___s___c_o_n_f_i_g_abd026761ecd67efcfb19ee36862f0205)]
 >>
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-/Limits [(struct_f_s_p___s___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a3b793f8591e69ba72aed9c91c65254e0) (struct_f_s_p___s___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a47913d253d002731834eaeedb1189a39)]
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+/Limits [(struct_f_s_p___s___c_o_n_f_i_g_abd4a7f1cc0c1b4c2ccf8c0bcf94837f1) (struct_f_s_p___s___c_o_n_f_i_g_ac0e8a832d06e0441e9562891ecb12e22)]
 >>
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 10119 0 obj
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-/Limits [(struct_f_s_p___s___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a48b9206d486366026e38d82d221a3271) (struct_f_s_p___s___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a4ea5ecfcabe1d68e8bdb22d1d9f334c3)]
+/Names [(struct_f_s_p___s___c_o_n_f_i_g_ac15c365c500b7f5a7d0398511397bd1c) 6722 0 R (struct_f_s_p___s___c_o_n_f_i_g_ac2063ea2fe141d29b95df8b7f30a75cd) 5963 0 R (struct_f_s_p___s___c_o_n_f_i_g_ac2ef2848696463affb3d9f94388420a3) 6766 0 R (struct_f_s_p___s___c_o_n_f_i_g_ac34b402aa31304a108e9a05eb20bd37b) 6975 0 R (struct_f_s_p___s___c_o_n_f_i_g_ac3c62e22ccbda6a58a7a62317f8ea807) 6049 0 R (struct_f_s_p___s___c_o_n_f_i_g_ac47d3152a6952c1bb221c08aca1e98be) 6457 0 R]
+/Limits [(struct_f_s_p___s___c_o_n_f_i_g_ac15c365c500b7f5a7d0398511397bd1c) (struct_f_s_p___s___c_o_n_f_i_g_ac47d3152a6952c1bb221c08aca1e98be)]
 >>
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 10120 0 obj
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-/Names [(struct_f_s_p___s___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a507c333fbacc3fb31954ed03ca73a0c9) 7642 0 R (struct_f_s_p___s___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a5170725d9a853cf16dd263581ea0f99e) 7652 0 R (struct_f_s_p___s___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a51a1f55c27119b16dd7c039f84951139) 7780 0 R (struct_f_s_p___s___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a535ee072041421fb08cb009b5155c22e) 7689 0 R (struct_f_s_p___s___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a56a4e36bd05bb4da133b8e043df1256f) 7650 0 R (struct_f_s_p___s___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a56c6610a41f9677e4e66d81094d6b303) 7752 0 R]
-/Limits [(struct_f_s_p___s___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a507c333fbacc3fb31954ed03ca73a0c9) (struct_f_s_p___s___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a56c6610a41f9677e4e66d81094d6b303)]
+/Names [(struct_f_s_p___s___c_o_n_f_i_g_ac4bea5e777db4bc028d463ab539d007f) 6768 0 R (struct_f_s_p___s___c_o_n_f_i_g_ac54190a7b67c76158e2950f7bce17a73) 5960 0 R (struct_f_s_p___s___c_o_n_f_i_g_ac55c0ad2ec699c636c8bd8c7b4bc46c8) 6369 0 R (struct_f_s_p___s___c_o_n_f_i_g_ac5912ad700a95182ba9ca3e379f93c5f) 6827 0 R (struct_f_s_p___s___c_o_n_f_i_g_ac5965696828ea1c6b881d47915004bf7) 6414 0 R (struct_f_s_p___s___c_o_n_f_i_g_ac5d35e14029bb3825bca5c390daabaae) 5967 0 R]
+/Limits [(struct_f_s_p___s___c_o_n_f_i_g_ac4bea5e777db4bc028d463ab539d007f) (struct_f_s_p___s___c_o_n_f_i_g_ac5d35e14029bb3825bca5c390daabaae)]
 >>
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 10121 0 obj
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-/Names [(struct_f_s_p___s___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a59bef1f99419a0bb9cdd81acbdcba32a) 7703 0 R (struct_f_s_p___s___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a5b5d36235e5d428b9f00180cda9119ab) 7603 0 R (struct_f_s_p___s___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a5b6a8fa289e21fda7db2e63ba660fd86) 7789 0 R (struct_f_s_p___s___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a5f2ff6978ac28cbcbf5cb54e5c74ad27) 7600 0 R (struct_f_s_p___s___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a62f03ea8d14192c24b4d6a6e11aad3ab) 7754 0 R (struct_f_s_p___s___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a64357fcdf003518a12ec40fe23bc79f8) 7645 0 R]
-/Limits [(struct_f_s_p___s___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a59bef1f99419a0bb9cdd81acbdcba32a) (struct_f_s_p___s___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a64357fcdf003518a12ec40fe23bc79f8)]
+/Names [(struct_f_s_p___s___c_o_n_f_i_g_ac70ad0c4e9e9984a2343e75bb26c2ad6) 6279 0 R (struct_f_s_p___s___c_o_n_f_i_g_ac823253479a1fbdaf83da106d28edf92) 6832 0 R (struct_f_s_p___s___c_o_n_f_i_g_ac8b2b9738054afdb3c815dd961b003a6) 7070 0 R (struct_f_s_p___s___c_o_n_f_i_g_ac9fe41bd3cd62cdd06f76dc0084f5ada) 6377 0 R (struct_f_s_p___s___c_o_n_f_i_g_acaacc8c59cac6d06704e026855a59fda) 6936 0 R (struct_f_s_p___s___c_o_n_f_i_g_acb9ec60ac0e3dbf8f8a1d5e281882d38) 6379 0 R]
+/Limits [(struct_f_s_p___s___c_o_n_f_i_g_ac70ad0c4e9e9984a2343e75bb26c2ad6) (struct_f_s_p___s___c_o_n_f_i_g_acb9ec60ac0e3dbf8f8a1d5e281882d38)]
 >>
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-/Names [(struct_f_s_p___s___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a66153382b73360e1755f7c32b427390b) 7787 0 R (struct_f_s_p___s___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a687f5d8fa99391fd737cc587ffec79e7) 7551 0 R (struct_f_s_p___s___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a6aca6083aa475a5afa3c3a30269ee5ec) 7557 0 R (struct_f_s_p___s___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a6c5c744b1d378a31f3b5a3701eb6a4b2) 7547 0 R (struct_f_s_p___s___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a6e10310516eb7b52a3d830243618c491) 7597 0 R (struct_f_s_p___s___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a6ef3d65624bf39c3b52842fe139a4e97) 7589 0 R]
-/Limits [(struct_f_s_p___s___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a66153382b73360e1755f7c32b427390b) (struct_f_s_p___s___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a6ef3d65624bf39c3b52842fe139a4e97)]
+/Names [(struct_f_s_p___s___c_o_n_f_i_g_acbe1b7bab7c486197b7df1f97ed25b5d) 6415 0 R (struct_f_s_p___s___c_o_n_f_i_g_acc3f20dd3c8739f4e91b724abfd263fe) 6570 0 R (struct_f_s_p___s___c_o_n_f_i_g_acc3fea439a6b57a397c03664e9aa8171) 6523 0 R (struct_f_s_p___s___c_o_n_f_i_g_acc79a8e057297a2bc2578db5b53f10ab) 7169 0 R (struct_f_s_p___s___c_o_n_f_i_g_acd04e9bb72c274b4d14ca130d022d6a0) 6129 0 R (struct_f_s_p___s___c_o_n_f_i_g_acd6b6d34a63842db5c3e920333c1d401) 5912 0 R]
+/Limits [(struct_f_s_p___s___c_o_n_f_i_g_acbe1b7bab7c486197b7df1f97ed25b5d) (struct_f_s_p___s___c_o_n_f_i_g_acd6b6d34a63842db5c3e920333c1d401)]
 >>
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 10123 0 obj
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-/Names [(struct_f_s_p___s___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a7030f7b6f619636b0501ac6ac48100bf) 7790 0 R (struct_f_s_p___s___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a726c4130c5f691ac911414346c0a810f) 7658 0 R (struct_f_s_p___s___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a72ad4a67661cd90b7acab20fe4669b80) 7612 0 R (struct_f_s_p___s___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a73502629bee545d3e448a850adde0d12) 7602 0 R (struct_f_s_p___s___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a73ddba9c7572a7d19db6b56204a301a3) 7758 0 R (struct_f_s_p___s___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a771bcf89197cc90dc851ae4765112d0b) 7785 0 R]
-/Limits [(struct_f_s_p___s___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a7030f7b6f619636b0501ac6ac48100bf) (struct_f_s_p___s___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a771bcf89197cc90dc851ae4765112d0b)]
+/Names [(struct_f_s_p___s___c_o_n_f_i_g_ace0cc8ab0d19901716be666511f4d581) 6561 0 R (struct_f_s_p___s___c_o_n_f_i_g_ace180765178f066c51dc3086d488bfab) 6312 0 R (struct_f_s_p___s___c_o_n_f_i_g_ace45c1a6588ea74b76fb5c4af3bf5fbd) 6838 0 R (struct_f_s_p___s___c_o_n_f_i_g_acee27db856183bd7050f7db6289bf682) 6268 0 R (struct_f_s_p___s___c_o_n_f_i_g_acf849b21b25d2cc1988ed669f59d0d28) 6131 0 R (struct_f_s_p___s___c_o_n_f_i_g_acfe04248400693b6efa8e36a96e49cc7) 6271 0 R]
+/Limits [(struct_f_s_p___s___c_o_n_f_i_g_ace0cc8ab0d19901716be666511f4d581) (struct_f_s_p___s___c_o_n_f_i_g_acfe04248400693b6efa8e36a96e49cc7)]
 >>
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 10124 0 obj
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-/Limits [(struct_f_s_p___s___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a7a9130a3194a9643c003cc950ca01a69) (struct_f_s_p___s___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a8453f8f00c46358a4ee7c343933e8015)]
+/Names [(struct_f_s_p___s___c_o_n_f_i_g_ad086527d628dd6dd4c92691e51f3738e) 6234 0 R (struct_f_s_p___s___c_o_n_f_i_g_ad09e440138ebba30f62d1729ff3650c8) 6974 0 R (struct_f_s_p___s___c_o_n_f_i_g_ad138c00b0ab70ac184f19e05e9d42b5e) 7177 0 R (struct_f_s_p___s___c_o_n_f_i_g_ad1892eedb7792ce7e2efcde03995fd43) 6128 0 R (struct_f_s_p___s___c_o_n_f_i_g_ad1c1b0f27f599601cc7372833cc29ff8) 6138 0 R (struct_f_s_p___s___c_o_n_f_i_g_ad1f6fb9eaab3c4defc6bde61f6ccaed3) 6040 0 R]
+/Limits [(struct_f_s_p___s___c_o_n_f_i_g_ad086527d628dd6dd4c92691e51f3738e) (struct_f_s_p___s___c_o_n_f_i_g_ad1f6fb9eaab3c4defc6bde61f6ccaed3)]
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-/Limits [(struct_f_s_p___s___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a867eb05b160f8211f0defcf258522e57) (struct_f_s_p___s___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a9d6cf39e3d2cbd3d46bbe7b50d595754)]
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+/Limits [(struct_f_s_p___s___c_o_n_f_i_g_ad2d22aacfa31002109a623a628dad05d) (struct_f_s_p___s___c_o_n_f_i_g_ad424b45ce91115562627165de73b27e9)]
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-/Limits [(struct_f_s_p___s___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a9dee8a4ac666eefe0877e46b950189f1) (struct_f_s_p___s___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_aa3ae8538f44b6bae42b82b8f96180277)]
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 >>
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 10127 0 obj
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-/Limits [(struct_f_s_p___s___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_aa7a4854279733877c456c0721052ea85) (struct_f_s_p___s___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_ab35e272efc652bb3564bf912c5f7b13d)]
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+/Limits [(struct_f_s_p___s___c_o_n_f_i_g_ad672e2be44210d3de4ab8e326e24062d) (struct_f_s_p___s___c_o_n_f_i_g_ad906ee6a0ab928a5a55834f1d2f1ccf4)]
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-/Limits [(struct_f_s_p___s___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_ab73ce6647afe1320c531a4a63f23109c) (struct_f_s_p___s___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_ac4c54cbcfdba36a8139f89c47e81827d)]
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+/Limits [(struct_f_s_p___s___c_o_n_f_i_g_ad9a0e895e4e4fe5c92f88044aeaae389) (struct_f_s_p___s___c_o_n_f_i_g_adbb85fb924e716b39dd4af62814736fa)]
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-/Limits [(struct_f_s_p___s___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_ac588205caa4fc8bc2c8e2b63387962ba) (struct_f_s_p___s___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_aca8528ca166a103be51127b5c7d74141)]
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+/Limits [(struct_f_s_p___s___c_o_n_f_i_g_addc10955a52fe5a3f3c25d6c0de5efc1) (struct_f_s_p___s___c_o_n_f_i_g_ae0c9f3238beec1ed59503e6faae5ade7)]
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-/Limits [(struct_f_s_p___t___c_o_n_f_i_g_ab8689f5836a4dc89ab425a2e31d19333) (struct_f_s_p___t___c_o_n_f_i_g_afdb472d64a41d58de954a50843a82f08)]
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+/Limits [(struct_f_s_p___s___c_o_n_f_i_g_aeb3fd1d43a42e6d6ec7ead228503c9bc) (struct_f_s_p___s___c_o_n_f_i_g_aef982ab1a112e6011c1f57037d26af98)]
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-/Limits [(struct_f_s_p___t___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g) (struct_f_s_p_m___u_p_d_a683c2240b7196d7fbe9c911fe4e38474)]
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+/Limits [(struct_f_s_p___s___c_o_n_f_i_g_aefd0234059c6cab518d0c90cf2cca8bf) (struct_f_s_p___s___c_o_n_f_i_g_af0771637cef8167208327728ee6bac74)]
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-/Names [(struct_f_s_p_m___u_p_d_a74c247ddff97be41e56b7cc5acc7118a) 7891 0 R (struct_f_s_p_m___u_p_d_a8f40d855549bf522f4ed819906c7e680) 7892 0 R (struct_f_s_p_m___u_p_d_ac8e22d7fa209f037c7257e9fe2f8ddf5) 7893 0 R (struct_f_s_p_m___u_p_d_acc4344b32148c74e3bccf70c2311d0e6) 7896 0 R (struct_f_s_p_s___u_p_d) 3873 0 R (struct_f_s_p_s___u_p_d_a15e53b400d8d8f1b2a0e21a511add694) 7924 0 R]
-/Limits [(struct_f_s_p_m___u_p_d_a74c247ddff97be41e56b7cc5acc7118a) (struct_f_s_p_s___u_p_d_a15e53b400d8d8f1b2a0e21a511add694)]
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+/Limits [(struct_f_s_p___s___c_o_n_f_i_g_af078b946b394c50ea7dab0ce1ebcdc32) (struct_f_s_p___s___c_o_n_f_i_g_af2b42e43bb219e88a7814cd0e56d60bb)]
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-/Limits [(struct_f_s_p_s___u_p_d_a1bc8364f530bfebe3486766e8705de16) (struct_f_s_p_t___c_o_r_e___u_p_d_a3503895c6438192627d8e99a18dacf96)]
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+/Limits [(struct_f_s_p___s___c_o_n_f_i_g_af2ee2e5f44466ce798fb3615b310454e) (struct_f_s_p___s___c_o_n_f_i_g_af44cab66ddc91e974458ff56a2eb5f7a)]
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-/Limits [(struct_f_s_p_t___c_o_r_e___u_p_d_a48856e3dd5193f0bd1418a5fb3892544) (struct_f_s_p_t___u_p_d_a4ffcdd72630dbd96f7f4799fb192684b)]
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+/Limits [(struct_f_s_p___s___c_o_n_f_i_g_af45b240a448b284b2ad5fbfc0a340a5b) (struct_f_s_p___s___c_o_n_f_i_g_af686595c1791dd586ea2205a1845de82)]
 >>
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-/Limits [(struct_f_s_p_t___u_p_d_a5c28e2fdcf313257642eebfbc06f39ae) (struct_g_p_i_o___c_o_n_f_i_g)]
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-/Limits [(struct_g_p_i_o___c_o_n_f_i_g_a048d02cd4ae012f5dc0b71fd1c02fc5c) (struct_g_p_i_o___c_o_n_f_i_g_a7a061f3477ff4c839b851aa2fcf72ede)]
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 >>
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-/Limits [(struct_g_p_i_o___c_o_n_f_i_g_a880efd24e29953586e35110f4cdf2312) (struct_s_i___p_c_h___d_e_v_i_c_e___i_n_t_e_r_r_u_p_t___c_o_n_f_i_g_a22cbd90b14547cfb73cbfd8736d60914)]
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-/Limits [(struct_s_i___p_c_h___d_e_v_i_c_e___i_n_t_e_r_r_u_p_t___c_o_n_f_i_g_a61f6e2b4aa4323289b336be74a12b090) (subsection.12.10.1)]
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 >>
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+/Limits [(struct_f_s_p___s___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a09ce10c727d35d70ffbe7c3a944a923e) (struct_f_s_p___s___r_e_s_t_r_i_c_t_e_d___c_o_n_f_i_g_a12462c33281618a8b1d0b646ca6efff3)]
+>>
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-<< /Size 10360
-/Root 10358 0 R
-/Info 10359 0 R
-/ID [<FA5D8D3C256442D61973B87E95DF3F5A> <FA5D8D3C256442D61973B87E95DF3F5A>] >>
+<< /Size 10393
+/Root 10391 0 R
+/Info 10392 0 R
+/ID [<2815EA2801C29A183E145ACB030D4B91> <2815EA2801C29A183E145ACB030D4B91>] >>
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 %%EOF
diff --git a/IceLakeFspBinPkg/Fsp.bsf b/IceLakeFspBinPkg/Fsp.bsf
index fb48572..ffb7c47 100644
--- a/IceLakeFspBinPkg/Fsp.bsf
+++ b/IceLakeFspBinPkg/Fsp.bsf
@@ -320,7 +320,7 @@ StructDef
         $gPlatformFspPkgTokenSpaceGuid_EnableC6Dram                    1 bytes    $_DEFAULT_ = 0x01
         $gPlatformFspPkgTokenSpaceGuid_BiosGuard                       1 bytes    $_DEFAULT_ = 0x01
         Skip 1 bytes
-        $gPlatformFspPkgTokenSpaceGuid_EnableSgx                       1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_EnableSgx                       1 bytes    $_DEFAULT_ = 0x02
         $gPlatformFspPkgTokenSpaceGuid_Txt                             1 bytes    $_DEFAULT_ = 0x00
         Skip 3 bytes
         $gPlatformFspPkgTokenSpaceGuid_PrmrrSize                       4 bytes    $_DEFAULT_ = 0x00000000
@@ -463,7 +463,8 @@ StructDef
         $gPlatformFspPkgTokenSpaceGuid_PegImrSize                      2 bytes    $_DEFAULT_ = 0x01
         $gPlatformFspPkgTokenSpaceGuid_EnableAbove4GBMmio              1 bytes    $_DEFAULT_ = 0x01
         $gPlatformFspPkgTokenSpaceGuid_LoadMgUcFw                      1 bytes    $_DEFAULT_ = 0x00
-        Skip 30 bytes
+        $gPlatformFspPkgTokenSpaceGuid_ITbtVtdEnable                   1 bytes    $_DEFAULT_ = 0x0
+        Skip 29 bytes
         $gPlatformFspPkgTokenSpaceGuid_HeciTimeouts                    1 bytes    $_DEFAULT_ = 0x01
         $gPlatformFspPkgTokenSpaceGuid_DidInitStat                     1 bytes    $_DEFAULT_ = 0x0
         $gPlatformFspPkgTokenSpaceGuid_DisableCpuReplacedPolling       1 bytes    $_DEFAULT_ = 0x0
@@ -2019,6 +2020,11 @@ List &gPlatformFspPkgTokenSpaceGuid_Peg3Enable
     Selection 2 , "AUTO"
 EndList
 
+List &gPlatformFspPkgTokenSpaceGuid_ITbtVtdEnable
+    Selection 0 , "Disable"
+    Selection 1 , "Enable"
+EndList
+
 List &gPlatformFspPkgTokenSpaceGuid_DmiTS1TW
     Selection 0 , "x1"
     Selection 1 , "x2"
@@ -3095,6 +3101,8 @@ Page "System Agent 1"
         Help "Enable/disable above 4GB MMIO resource support"
     Combo $gPlatformFspPkgTokenSpaceGuid_LoadMgUcFw, "Control Load MG uC FW", &EN_DIS,
         Help "Enable/disable Load MG uC FW"
+    Combo $gPlatformFspPkgTokenSpaceGuid_ITbtVtdEnable, "Enable/Disable ITbtVtd", &gPlatformFspPkgTokenSpaceGuid_ITbtVtdEnable,
+        Help "Disabled(0x0): Disable ITbtVtd, Enabled(0x1): Enable ITbtVtd"
 EndPage
 
 Page "PCH 2"
@@ -3873,7 +3881,7 @@ Page "PCH 2"
         Help "Decides the temperature."
              "Valid range: 0x00 ~ 0xFFFF"
     EditNum $gPlatformFspPkgTokenSpaceGuid_PchFivrExtV1p05RailEnabledStates, "Mask to enable the usage of external V1p05 VR rail in specific S0ix or Sx states", HEX,
-        Help "Enable External V1P05 Rail in: BIT0:S0i1/S0i2, BIT1:S0i3, BIT2:S3, BIT3:S4, BIT5:S5, Default is set to 0x1F for ICL-YN and 0 for all other skus."
+        Help "Enable External V1P05 Rail in: BIT0:S0i1/S0i2, BIT1:S0i3, BIT2:S3, BIT3:S4, BIT5:S5, Default is set to 0x1F for ICL-UN/YN and 0 for all other skus."
              "Valid range: 0x00 ~ 0x1F"
     EditNum $gPlatformFspPkgTokenSpaceGuid_PchFivrExtV1p05RailVoltage, "External V1P05 Voltage Value that will be used in S0i2/S0i3 states", HEX,
         Help "Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...)"
@@ -3882,7 +3890,7 @@ Page "PCH 2"
         Help "Granularity of this setting is 1mA and maximal possible value is 200mA"
              "Valid range: 0x0 ~ 0xC8"
     EditNum $gPlatformFspPkgTokenSpaceGuid_PchFivrExtVnnRailEnabledStates, "Mask to enable the usage of external Vnn VR rail in specific S0ix or Sx states", HEX,
-        Help "Enable External Vnn Rail in: BIT0:S0i1/S0i2, BIT1:S0i3, BIT2:S3, BIT3:S4, BIT5:S5, Default is set to 0x1F for ICL-YN and 0 for all other skus."
+        Help "Enable External Vnn Rail in: BIT0:S0i1/S0i2, BIT1:S0i3, BIT2:S3, BIT3:S4, BIT5:S5, Default is set to 0x1F for ICL-UN/YN and 0 for all other skus."
              "Valid range: 0x00 ~ 0x1F"
     EditNum $gPlatformFspPkgTokenSpaceGuid_PchFivrExtVnnRailVoltage, "External Vnn Voltage Value that will be used in S0ix/Sx states", HEX,
         Help "Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...), Default is set to 420"
@@ -3891,7 +3899,7 @@ Page "PCH 2"
         Help "Granularity of this setting is 1mA and maximal possible value is 200mA"
              "Valid range: 0x0 ~ 0xC8"
     EditNum $gPlatformFspPkgTokenSpaceGuid_PchFivrExtVnnRailSxEnabledStates, "Mask to enable the usage of external Vnn VR rail in Sx states", HEX,
-        Help "Use only if Ext Vnn Rail config is different in Sx. Enable External Vnn Rail in Sx: BIT0-1:Reserved, BIT2:S3, BIT3:S4, BIT5:S5, Default is set to 0x1C for ICL-YN and 0 for all other skus."
+        Help "Use only if Ext Vnn Rail config is different in Sx. Enable External Vnn Rail in Sx: BIT0-1:Reserved, BIT2:S3, BIT3:S4, BIT5:S5, Default is set to 0x1C for ICL-UN/YN and 0 for all other skus."
              "Valid range: 0x00 ~ 0x1F"
     EditNum $gPlatformFspPkgTokenSpaceGuid_PchFivrExtVnnRailSxVoltage, "External Vnn Voltage Value that will be used in Sx states", HEX,
         Help "Use only if Ext Vnn Rail config is different in Sx. Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...)"
diff --git a/IceLakeFspBinPkg/Fsp.fd b/IceLakeFspBinPkg/Fsp.fd
index 9171ff8..017d9a1 100644
Binary files a/IceLakeFspBinPkg/Fsp.fd and b/IceLakeFspBinPkg/Fsp.fd differ
diff --git a/IceLakeFspBinPkg/Include/FspmUpd.h b/IceLakeFspBinPkg/Include/FspmUpd.h
index 2d55739..d5ae2ed 100644
--- a/IceLakeFspBinPkg/Include/FspmUpd.h
+++ b/IceLakeFspBinPkg/Include/FspmUpd.h
@@ -2521,9 +2521,15 @@ typedef struct {
 **/
   UINT8                       LoadMgUcFw;
 
-/** Offset 0x04E6
+/** Offset 0x04E6 - Enable/Disable ITbtVtd
+  Disabled(0x0): Disable ITbtVtd, Enabled(0x1): Enable ITbtVtd
+  0:Disable, 1:Enable
 **/
-  UINT8                       SaPreMemRsvd[30];
+  UINT8                       ITbtVtdEnable;
+
+/** Offset 0x04E7
+**/
+  UINT8                       SaPreMemRsvd[29];
 
 /** Offset 0x0504 - HECI Timeouts
   0: Disable, 1: Enable (Default) timeout check for HECI
diff --git a/IceLakeFspBinPkg/Include/FspsUpd.h b/IceLakeFspBinPkg/Include/FspsUpd.h
index 6b58caa..d0cb4e0 100644
--- a/IceLakeFspBinPkg/Include/FspsUpd.h
+++ b/IceLakeFspBinPkg/Include/FspsUpd.h
@@ -3459,7 +3459,7 @@ typedef struct {
 
 /** Offset 0x0A3E - Mask to enable the usage of external V1p05 VR rail in specific S0ix or Sx states
   Enable External V1P05 Rail in: BIT0:S0i1/S0i2, BIT1:S0i3, BIT2:S3, BIT3:S4, BIT5:S5,
-  Default is set to 0x1F for ICL-YN and 0 for all other skus.
+  Default is set to 0x1F for ICL-UN/YN and 0 for all other skus.
 **/
   UINT8                       PchFivrExtV1p05RailEnabledStates;
 
@@ -3479,7 +3479,7 @@ typedef struct {
 
 /** Offset 0x0A43 - Mask to enable the usage of external Vnn VR rail in specific S0ix or Sx states
   Enable External Vnn Rail in: BIT0:S0i1/S0i2, BIT1:S0i3, BIT2:S3, BIT3:S4, BIT5:S5,
-  Default is set to 0x1F for ICL-YN and 0 for all other skus.
+  Default is set to 0x1F for ICL-UN/YN and 0 for all other skus.
 **/
   UINT8                       PchFivrExtVnnRailEnabledStates;
 
@@ -3495,7 +3495,7 @@ typedef struct {
 
 /** Offset 0x0A47 - Mask to enable the usage of external Vnn VR rail in Sx states
   Use only if Ext Vnn Rail config is different in Sx. Enable External Vnn Rail in
-  Sx: BIT0-1:Reserved, BIT2:S3, BIT3:S4, BIT5:S5, Default is set to 0x1C for ICL-YN
+  Sx: BIT0-1:Reserved, BIT2:S3, BIT3:S4, BIT5:S5, Default is set to 0x1C for ICL-UN/YN
   and 0 for all other skus.
 **/
   UINT8                       PchFivrExtVnnRailSxEnabledStates;
diff --git a/IceLakeFspBinPkg/SampleCode/Vbt/Vbt.bin b/IceLakeFspBinPkg/SampleCode/Vbt/Vbt.bin
index 9bd5f2f..de08e07 100644
Binary files a/IceLakeFspBinPkg/SampleCode/Vbt/Vbt.bin and b/IceLakeFspBinPkg/SampleCode/Vbt/Vbt.bin differ
diff --git a/IceLakeFspBinPkg/SampleCode/Vbt/Vbt.bsf b/IceLakeFspBinPkg/SampleCode/Vbt/Vbt.bsf
index 6032d93..f63dac8 100644
--- a/IceLakeFspBinPkg/SampleCode/Vbt/Vbt.bsf
+++ b/IceLakeFspBinPkg/SampleCode/Vbt/Vbt.bsf
@@ -94,7 +94,7 @@ ALIGN
 
 ; bmp_Bits_3
 SKIP                                      2 bits      ; Skip 2 bits
-$180_Deg_Rotation_Enable                  1 bit       ; 180 degree rotation enable for LFP in GOP driver.
+SKIP                                      1 bit       ; Obsolete.
 SKIP                                      5 bits      ; Skip remaining bits.
 ALIGN
 
@@ -884,20 +884,20 @@ ALIGN
 $VBT_Customization_Version                1 byte      ; Customization VBT version number
 
 ; bmp_Driver_Feature_Flags
-$PM_RMPM_Enable                           1 bit       ; Intel Rapid Memory Power Management (RMPM) Enable/Disable Flag.
-$PM_S2DDT_Enable                          1 bit       ; Intel Smart 2D Display Technology (S2DDT) Enable/Disable Flag.
-$PM_DPST_Enable                           1 bit       ; Intel Display Power Saving Technology (DPST) Enable/Disable Flag.
+$PM_RMPM_Enable                           1 bit       ; Intel® Rapid Memory Power Management (RMPM) Enable/Disable Flag.
+$PM_S2DDT_Enable                          1 bit       ; Intel® Smart 2D Display Technology (S2DDT) Enable/Disable Flag.
+SKIP                                      1 bit       ; Obsolete.
 $PM_BLC_Enable                            1 bit       ; Backlight Control (BLC) Enable/Disable Flag.
-$PM_ADB_Enable                            1 bit       ; Intel Automatic Display Brightness (ADB) Enable/Disable Flag.
-$PM_DRRS_Enable                           1 bit       ; Intel Display Refresh Rate Switching (DRRS) Enable/Disable Flag.
+SKIP                                      1 bit       ; Obsolete.
+SKIP                                      1 bit       ; Obsolete.
 $PM_RS_Enable                             1 bit       ; Graphics Render Standby (RS) Enable/Disable Flag.
 $PM_GPMT_Enable                           1 bit       ; Obsolete
 $PM_Turbo_Enable                          1 bit       ; Intel Turbo Boost Technology Enable/Disable Flag.
-$Panel_Self_Refresh                       1 bit       ; Panel Self refresh feature (PSR)
+SKIP                                      1 bit       ; Obsolete.
 $Inter_Pixel_Storage                      1 bit       ; Hidden feature.
 $Dynamic_FPS_Enable                       1 bit       ; Dynamic Frames per second(DFPS) feature Enable/Disable Flag.
-$DMRRS                                    1 bit       ; Dynamic media refresh rate enable/disable
-$ADT                                      1 bit       ; Assertive display technology enable/disable
+SKIP                                      1 bit       ; Obsolete.
+SKIP                                      1 bit       ; Obsolete.
 $HPD_Wake                                 1 bit       ; HPD events routing to display driver when system is in S0ix/DC9, enable/disable
 $PC_Fields_Enable                         1 bit       ; PC Feature field's validity Flag.
 ALIGN
@@ -1626,6 +1626,23 @@ $LcdVcc_On_During_S0_State_14             1 bit       ; Enable flag to keep LCDV
 $LcdVcc_On_During_S0_State_15             1 bit       ; Enable flag to keep LCDVCC on during S0 state bit for panel #15
 $LcdVcc_On_During_S0_State_16             1 bit       ; Enable flag to keep LCDVCC on during S0 state bit for panel #16
 
+$Panel_Rotation_01                        2 bits      ;  00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree.
+$Panel_Rotation_02                        2 bits      ;  00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree.
+$Panel_Rotation_03                        2 bits      ;  00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree.
+$Panel_Rotation_04                        2 bits      ;  00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree.
+$Panel_Rotation_05                        2 bits      ;  00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree.
+$Panel_Rotation_06                        2 bits      ;  00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree.
+$Panel_Rotation_07                        2 bits      ;  00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree.
+$Panel_Rotation_08                        2 bits      ;  00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree.
+$Panel_Rotation_09                        2 bits      ;  00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree.
+$Panel_Rotation_10                        2 bits      ;  00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree.
+$Panel_Rotation_11                        2 bits      ;  00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree.
+$Panel_Rotation_12                        2 bits      ;  00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree.
+$Panel_Rotation_13                        2 bits      ;  00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree.
+$Panel_Rotation_14                        2 bits      ;  00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree.
+$Panel_Rotation_15                        2 bits      ;  00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree.
+$Panel_Rotation_16                        2 bits      ;  00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree.
+
 ;==============================================================================
 ; Block 41 - Flat Panel Data Tables Pointers
 ;------------------------------------------------------------------------------
@@ -2236,18 +2253,200 @@ $Lfp_Pwm_Controller_Selection_16          4 bits      ; Pwm Controller Selection
 
 SKIP                                      3 bytes     ; Skip block ID and size
 
-SKIP                                      1 bit       ; Reserved
-$BIA_Aggress_Level                        3 bits      ; Power Conservation Preference level
-SKIP                                      1 bit       ; Reserved
-$LACE_Enabled_Status                      1 bit       ; Default Display LACE enabled status
-$Display_LACE_Support                     1 bit       ; Display LACE support
-SKIP                                      1 bit
+SKIP                                      1 byte      ; Obsolete.
+
 ALIGN
 
 $ALS_Response_Data                        20 bytes    ; ALS Response Data
 
-$Agressiveness_Profile                    3 bits      ; Display LACE aggressiveness level profile
+SKIP                                      3 bits      ; Obsolete.
 SKIP                                      5 bits      ; Reserved
+
+$DPST_Enable_01                           1 bit       ; Intel® Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #01.
+$DPST_Enable_02                           1 bit       ; Intel® Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #02.
+$DPST_Enable_03                           1 bit       ; Intel® Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #03.
+$DPST_Enable_04                           1 bit       ; Intel® Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #04.
+$DPST_Enable_05                           1 bit       ; Intel® Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #05.
+$DPST_Enable_06                           1 bit       ; Intel® Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #06.
+$DPST_Enable_07                           1 bit       ; Intel® Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #07.
+$DPST_Enable_08                           1 bit       ; Intel® Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #08.
+$DPST_Enable_09                           1 bit       ; Intel® Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #09.
+$DPST_Enable_10                           1 bit       ; Intel® Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #10.
+$DPST_Enable_11                           1 bit       ; Intel® Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #11.
+$DPST_Enable_12                           1 bit       ; Intel® Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #12.
+$DPST_Enable_13                           1 bit       ; Intel® Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #13.
+$DPST_Enable_14                           1 bit       ; Intel® Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #14.
+$DPST_Enable_15                           1 bit       ; Intel® Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #15.
+$DPST_Enable_16                           1 bit       ; Intel® Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #16.
+
+$PSR_Enable_01                            1 bit       ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #01.
+$PSR_Enable_02                            1 bit       ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #02.
+$PSR_Enable_03                            1 bit       ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #03.
+$PSR_Enable_04                            1 bit       ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #04.
+$PSR_Enable_05                            1 bit       ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #05.
+$PSR_Enable_06                            1 bit       ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #06.
+$PSR_Enable_07                            1 bit       ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #07.
+$PSR_Enable_08                            1 bit       ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #08.
+$PSR_Enable_09                            1 bit       ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #09.
+$PSR_Enable_10                            1 bit       ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #10.
+$PSR_Enable_11                            1 bit       ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #11.
+$PSR_Enable_12                            1 bit       ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #12.
+$PSR_Enable_13                            1 bit       ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #13.
+$PSR_Enable_14                            1 bit       ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #14.
+$PSR_Enable_15                            1 bit       ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #15.
+$PSR_Enable_16                            1 bit       ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #16.
+
+$DRRS_Enable_01                           1 bit       ; Intel® Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #01.
+$DRRS_Enable_02                           1 bit       ; Intel® Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #02.
+$DRRS_Enable_03                           1 bit       ; Intel® Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #03.
+$DRRS_Enable_04                           1 bit       ; Intel® Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #04.
+$DRRS_Enable_05                           1 bit       ; Intel® Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #05.
+$DRRS_Enable_06                           1 bit       ; Intel® Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #06.
+$DRRS_Enable_07                           1 bit       ; Intel® Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #07.
+$DRRS_Enable_08                           1 bit       ; Intel® Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #08.
+$DRRS_Enable_09                           1 bit       ; Intel® Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #09.
+$DRRS_Enable_10                           1 bit       ; Intel® Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #10.
+$DRRS_Enable_11                           1 bit       ; Intel® Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #11.
+$DRRS_Enable_12                           1 bit       ; Intel® Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #12.
+$DRRS_Enable_13                           1 bit       ; Intel® Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #13.
+$DRRS_Enable_14                           1 bit       ; Intel® Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #14.
+$DRRS_Enable_15                           1 bit       ; Intel® Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #15.
+$DRRS_Enable_16                           1 bit       ; Intel® Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #16.
+
+$LACE_Enable_01                           1 bit       ; Display LACE Support Feature Enable/Disable Flag for Panel #01.
+$LACE_Enable_02                           1 bit       ; Display LACE Support Feature Enable/Disable Flag for Panel #02.
+$LACE_Enable_03                           1 bit       ; Display LACE Support Feature Enable/Disable Flag for Panel #03.
+$LACE_Enable_04                           1 bit       ; Display LACE Support Feature Enable/Disable Flag for Panel #04.
+$LACE_Enable_05                           1 bit       ; Display LACE Support Feature Enable/Disable Flag for Panel #05.
+$LACE_Enable_06                           1 bit       ; Display LACE Support Feature Enable/Disable Flag for Panel #06.
+$LACE_Enable_07                           1 bit       ; Display LACE Support Feature Enable/Disable Flag for Panel #07.
+$LACE_Enable_08                           1 bit       ; Display LACE Support Feature Enable/Disable Flag for Panel #08.
+$LACE_Enable_09                           1 bit       ; Display LACE Support Feature Enable/Disable Flag for Panel #09.
+$LACE_Enable_10                           1 bit       ; Display LACE Support Feature Enable/Disable Flag for Panel #10.
+$LACE_Enable_11                           1 bit       ; Display LACE Support Feature Enable/Disable Flag for Panel #11.
+$LACE_Enable_12                           1 bit       ; Display LACE Support Feature Enable/Disable Flag for Panel #12.
+$LACE_Enable_13                           1 bit       ; Display LACE Support Feature Enable/Disable Flag for Panel #13.
+$LACE_Enable_14                           1 bit       ; Display LACE Support Feature Enable/Disable Flag for Panel #14.
+$LACE_Enable_15                           1 bit       ; Display LACE Support Feature Enable/Disable Flag for Panel #15.
+$LACE_Enable_16                           1 bit       ; Display LACE Support Feature Enable/Disable Flag for Panel #16.
+
+
+$ADT_Enable_01                            1 bit       ; Assertive display technology enable/disable for Panel #01.
+$ADT_Enable_02                            1 bit       ; Assertive display technology enable/disable for Panel #02.
+$ADT_Enable_03                            1 bit       ; Assertive display technology enable/disable for Panel #03.
+$ADT_Enable_04                            1 bit       ; Assertive display technology enable/disable for Panel #04.
+$ADT_Enable_05                            1 bit       ; Assertive display technology enable/disable for Panel #05.
+$ADT_Enable_06                            1 bit       ; Assertive display technology enable/disable for Panel #06.
+$ADT_Enable_07                            1 bit       ; Assertive display technology enable/disable for Panel #07.
+$ADT_Enable_08                            1 bit       ; Assertive display technology enable/disable for Panel #08.
+$ADT_Enable_09                            1 bit       ; Assertive display technology enable/disable for Panel #09.
+$ADT_Enable_10                            1 bit       ; Assertive display technology enable/disable for Panel #10.
+$ADT_Enable_11                            1 bit       ; Assertive display technology enable/disable for Panel #11.
+$ADT_Enable_12                            1 bit       ; Assertive display technology enable/disable for Panel #12.
+$ADT_Enable_13                            1 bit       ; Assertive display technology enable/disable for Panel #13.
+$ADT_Enable_14                            1 bit       ; Assertive display technology enable/disable for Panel #14.
+$ADT_Enable_15                            1 bit       ; Assertive display technology enable/disable for Panel #15.
+$ADT_Enable_16                            1 bit       ; Assertive display technology enable/disable for Panel #16.
+
+$DMRRS_Enable_01                          1 bit       ; Dynamic media refresh rate enable/disable for Panel #01.
+$DMRRS_Enable_02                          1 bit       ; Dynamic media refresh rate enable/disable for Panel #02.
+$DMRRS_Enable_03                          1 bit       ; Dynamic media refresh rate enable/disable for Panel #03.
+$DMRRS_Enable_04                          1 bit       ; Dynamic media refresh rate enable/disable for Panel #04.
+$DMRRS_Enable_05                          1 bit       ; Dynamic media refresh rate enable/disable for Panel #05.
+$DMRRS_Enable_06                          1 bit       ; Dynamic media refresh rate enable/disable for Panel #06.
+$DMRRS_Enable_07                          1 bit       ; Dynamic media refresh rate enable/disable for Panel #07.
+$DMRRS_Enable_08                          1 bit       ; Dynamic media refresh rate enable/disable for Panel #08.
+$DMRRS_Enable_09                          1 bit       ; Dynamic media refresh rate enable/disable for Panel #09.
+$DMRRS_Enable_10                          1 bit       ; Dynamic media refresh rate enable/disable for Panel #10.
+$DMRRS_Enable_11                          1 bit       ; Dynamic media refresh rate enable/disable for Panel #11.
+$DMRRS_Enable_12                          1 bit       ; Dynamic media refresh rate enable/disable for Panel #12.
+$DMRRS_Enable_13                          1 bit       ; Dynamic media refresh rate enable/disable for Panel #13.
+$DMRRS_Enable_14                          1 bit       ; Dynamic media refresh rate enable/disable for Panel #14.
+$DMRRS_Enable_15                          1 bit       ; Dynamic media refresh rate enable/disable for Panel #15.
+$DMRRS_Enable_16                          1 bit       ; Dynamic media refresh rate enable/disable for Panel #16.
+
+$ADB_Enable_01                            1 bit       ; Intel® Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #01.
+$ADB_Enable_02                            1 bit       ; Intel® Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #02.
+$ADB_Enable_03                            1 bit       ; Intel® Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #03.
+$ADB_Enable_04                            1 bit       ; Intel® Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #04.
+$ADB_Enable_05                            1 bit       ; Intel® Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #05.
+$ADB_Enable_06                            1 bit       ; Intel® Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #06.
+$ADB_Enable_07                            1 bit       ; Intel® Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #07.
+$ADB_Enable_08                            1 bit       ; Intel® Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #08.
+$ADB_Enable_09                            1 bit       ; Intel® Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #09.
+$ADB_Enable_10                            1 bit       ; Intel® Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #10.
+$ADB_Enable_11                            1 bit       ; Intel® Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #11.
+$ADB_Enable_12                            1 bit       ; Intel® Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #12.
+$ADB_Enable_13                            1 bit       ; Intel® Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #13.
+$ADB_Enable_14                            1 bit       ; Intel® Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #14.
+$ADB_Enable_15                            1 bit       ; Intel® Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #15.
+$ADB_Enable_16                            1 bit       ; Intel® Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #16.
+
+$LACE_Status_01                           1 bit       ;Default Display LACE Status  enable/disable Flag for Panel #01.
+$LACE_Status_02                           1 bit       ;Default Display LACE Status  enable/disable Flag for Panel #02.
+$LACE_Status_03                           1 bit       ;Default Display LACE Status  enable/disable Flag for Panel #03.
+$LACE_Status_04                           1 bit       ;Default Display LACE Status  enable/disable Flag for Panel #04.
+$LACE_Status_05                           1 bit       ;Default Display LACE Status  enable/disable Flag for Panel #05.
+$LACE_Status_06                           1 bit       ;Default Display LACE Status  enable/disable Flag for Panel #06.
+$LACE_Status_07                           1 bit       ;Default Display LACE Status  enable/disable Flag for Panel #07.
+$LACE_Status_08                           1 bit       ;Default Display LACE Status  enable/disable Flag for Panel #08.
+$LACE_Status_09                           1 bit       ;Default Display LACE Status  enable/disable Flag for Panel #09.
+$LACE_Status_10                           1 bit       ;Default Display LACE Status  enable/disable Flag for Panel #10.
+$LACE_Status_11                           1 bit       ;Default Display LACE Status  enable/disable Flag for Panel #11.
+$LACE_Status_12                           1 bit       ;Default Display LACE Status  enable/disable Flag for Panel #12.
+$LACE_Status_13                           1 bit       ;Default Display LACE Status  enable/disable Flag for Panel #13.
+$LACE_Status_14                           1 bit       ;Default Display LACE Status  enable/disable Flag for Panel #14.
+$LACE_Status_15                           1 bit       ;Default Display LACE Status  enable/disable Flag for Panel #15.
+$LACE_Status_16                           1 bit       ;Default Display LACE Status  enable/disable Flag for Panel #16.
+
+$DPST_Aggressiveness_Profile_01           4 bits      ;DPST Aggressiveness profile Input Selection for Panel #01.
+$LACE_Aggressiveness_Profile_01           4 bits      ;Lace Aggressiveness profile Input Selection for Panel #01.
+
+$DPST_Aggressiveness_Profile_02           4 bits      ;DPST Aggressiveness profile Input Selection for Panel #02.
+$LACE_Aggressiveness_Profile_02           4 bits      ;Lace Aggressiveness profile Input Selection for Panel #02.
+
+$DPST_Aggressiveness_Profile_03           4 bits      ;DPST Aggressiveness profile Input Selection for Panel #03.
+$LACE_Aggressiveness_Profile_03           4 bits      ;Lace Aggressiveness profile Input Selection for Panel #03.
+
+$DPST_Aggressiveness_Profile_04           4 bits      ;DPST Aggressiveness profile Input Selection for Panel #04.
+$LACE_Aggressiveness_Profile_04           4 bits      ;Lace Aggressiveness profile Input Selection for Panel #04.
+
+$DPST_Aggressiveness_Profile_05           4 bits      ;DPST Aggressiveness profile Input Selection for Panel #05.
+$LACE_Aggressiveness_Profile_05           4 bits      ;Lace Aggressiveness profile Input Selection for Panel #05.
+
+$DPST_Aggressiveness_Profile_06           4 bits      ;DPST Aggressiveness profile Input Selection for Panel #06.
+$LACE_Aggressiveness_Profile_06           4 bits      ;Lace Aggressiveness profile Input Selection for Panel #06.
+
+$DPST_Aggressiveness_Profile_07           4 bits      ;DPST Aggressiveness profile Input Selection for Panel #07.
+$LACE_Aggressiveness_Profile_07           4 bits      ;Lace Aggressiveness profile Input Selection for Panel #07.
+
+$DPST_Aggressiveness_Profile_08           4 bits      ;DPST Aggressiveness profile Input Selection for Panel #08.
+$LACE_Aggressiveness_Profile_08           4 bits      ;Lace Aggressiveness profile Input Selection for Panel #08.
+
+$DPST_Aggressiveness_Profile_09           4 bits      ;DPST Aggressiveness profile Input Selection for Panel #09.
+$LACE_Aggressiveness_Profile_09           4 bits      ;Lace Aggressiveness profile Input Selection for Panel #09.
+
+$DPST_Aggressiveness_Profile_10           4 bits      ;DPST Aggressiveness profile Input Selection for Panel #10.
+$LACE_Aggressiveness_Profile_10           4 bits      ;Lace Aggressiveness profile Input Selection for Panel #10.
+
+$DPST_Aggressiveness_Profile_11           4 bits      ;DPST Aggressiveness profile Input Selection for Panel #11.
+$LACE_Aggressiveness_Profile_11           4 bits      ;Lace Aggressiveness profile Input Selection for Panel #11.
+
+$DPST_Aggressiveness_Profile_12           4 bits      ;DPST Aggressiveness profile Input Selection for Panel #12.
+$LACE_Aggressiveness_Profile_12           4 bits      ;Lace Aggressiveness profile Input Selection for Panel #12.
+
+$DPST_Aggressiveness_Profile_13           4 bits      ;DPST Aggressiveness profile Input Selection for Panel #13.
+$LACE_Aggressiveness_Profile_13           4 bits      ;Lace Aggressiveness profile Input Selection for Panel #13.
+
+$DPST_Aggressiveness_Profile_14           4 bits      ;DPST Aggressiveness profile Input Selection for Panel #14.
+$LACE_Aggressiveness_Profile_14           4 bits      ;Lace Aggressiveness profile Input Selection for Panel #14.
+
+$DPST_Aggressiveness_Profile_15           4 bits      ;DPST Aggressiveness profile Input Selection for Panel #15.
+$LACE_Aggressiveness_Profile_15           4 bits      ;Lace Aggressiveness profile Input Selection for Panel #15.
+
+$DPST_Aggressiveness_Profile_16           4 bits      ;DPST Aggressiveness profile Input Selection for Panel #16.
+$LACE_Aggressiveness_Profile_16           4 bits      ;Lace Aggressiveness profile Input Selection for Panel #16.
+
 ;==============================================================================
 ; Block 46 - Chromaticity  Support
 ;------------------------------------------------------------------------------
@@ -2856,6 +3055,7 @@ List    &Panel_List
   Selection       0x0D,       "PANEL #14"
   Selection       0x0E,       "PANEL #15"
   Selection       0x0F,       "PANEL #16"
+  Selection       0xFF,       "PANEL #FF"
 EndList
 
 List    &eDP_VSwing_Preemph_table_List
@@ -2930,7 +3130,7 @@ EndList
 
 List    &wait_line_link
   Selection       0x00,       "0 lines to wait"
-  Selection       0x01,       "2 lines to wait"
+  Selection       0x01,       "1 lines to wait"
   Selection       0x02,       "4 lines to wait"
   Selection       0x03,       "8 lines to wait"
 EndList
@@ -2987,7 +3187,7 @@ EndInfoBlock
 ;------------------------------------------------------------------------------
 Page      "VBT Information"
   Title     "PLATFORM : Icelake U/Y"
-  Title     "VBT version: 224"
+  Title     "VBT version: 228"
 
   #IF       ($LFP_Device_Class == 0x1806)
     Title     "Supported LFP type: eDP"
@@ -3241,17 +3441,12 @@ Page      "OS Graphics driver Configuration"
 
     Combo     $PC_Fields_Enable, "  PC Features Control Options", &Disabled_Enabled_List,
     Help      "This feature determines the validity of the following PC Features Control Options.\r\n\r\n"
-              "1.  Intel Rapid Memory Power Management (RMPM)\r\n"
-              "2.  Intel Smart 2D Display Technology (S2DDT)\r\n"
-              "3.  Intel Display Power Saving Technology (DPST) (Mobile only)\r\n"
-              "4.  DxgkDDI Backlight Control (DxgkDdiBLC) (Mobile only)\r\n"
-              "5.  Intel Automatic Display Brightness (ADB) (Mobile only)\r\n"
-              "6.  Intel Display Refresh Rate Switching (DRRS) (Mobile only)\r\n"
-              "7.  Graphics Render Standby (RS)\r\n"
-              "8.  Intel Turbo Boost Technology\r\n"
-              "9.  Dynamic Frames Per Second (DFPS)\r\n"
-              "10. Dynamic Media Refresh Rate Switching (DMRRS)\r\n"
-              "11. Assertive Display Technology (ADT)\r\n\r\n"
+              "1.  Intel® Rapid Memory Power Management (RMPM)\r\n"
+              "2.  Intel® Smart 2D Display Technology (S2DDT)\r\n"
+              "3.  DxgkDDI Backlight Control (DxgkDdiBLC) (Mobile only)\r\n"
+              "4.  Graphics Render Standby (RS)\r\n"
+              "5.  Intel® Turbo Boost Technology\r\n"
+              "6.  Dynamic Frames Per Second (DFPS)\r\n"
               "Note: Enable and Save the changes to display all the PC Features Control Options\r\n"
 
     Combo     $PM_RMPM_Enable, "\tIntel Rapid Memory Power Management (RMPM)", &Disabled_Enabled_List,
@@ -3260,66 +3455,19 @@ Page      "OS Graphics driver Configuration"
     Combo     $PM_S2DDT_Enable, "\tIntel Smart 2D Display Technology (S2DDT)", &Disabled_Enabled_List,
     Help      "This feature determines whether Intel Smart 2D Display Technology (S2DDT) is to be enabled. "
 
-    Combo     $PM_DPST_Enable, "\tIntel Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List,
-    Help      "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled. "
-              "Intel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power."
-              "\r\n\r\nNote: This technology is only active when the system is running in battery mode and "
-              "the LFP is the only active display device."
-
-    Combo     $BIA_Aggress_Level, "\t\tDPST Aggressiveness Level (Mobile only)", &Pwr_Pref_List,
-    Help      "This feature defines the Intel Display Power Saving Technology aggressiveness level if and only if "
-              "the feature Intel Display Power Saving Technology is enabled."
-              "\r\n\r\nThe following are the definitions for each level:"
-              "\r\n1 - Maximum Quality - shall use no DPST "
-              "\r\n2 - Provides  the user the maximum brightness for their embedded Local Flat Panel (LFP)while DPST is in use"
-              "\r\n3 - This level defines maximum amount of brightness with minimal power savings"
-              "\r\n4 - This level defines an intermediate value for brightness amount"
-              "\r\n5 - This level defines an intermediate value for the brightness amount"
-              "\r\n6 - Maximum Battery - Provided the user with the minimum amount of "
-              "brightness capable for their LFP with the maximum power savings"
-
     Combo     $PM_BLC_Enable, "\tDxgkDDI Brightness Control Method (Mobile only)", &Disabled_Enabled_List,
     Help      "This option determines whether the Vista, Win7, and future version DxgkDDI LFP Brightness Control method is to be enabled. "
 
-    Combo     $PM_ADB_Enable, "\tIntel Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List,
-    Help      "This feature determines whether Intel Automatic Display Brightness is to be enabled. "
-              "Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) "
-              "depending on the current ambient light environment. "
-              "When enabled, the driver and VBIOS will control the backlight brightness of the LFP "
-              "depending on the ambient environment if and only if the LFP is the only active display. "
-              "When disabled, the driver will perform no action."
-
-    Link      "ADB Response Data (Mobile only)" , "ADB Response Data (Mobile only)"
-
-    Combo     $PM_DRRS_Enable, "\tIntel Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List,
-    Help      "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled."
-
     Combo     $PM_RS_Enable, "\tGraphics Render Standby (RS)", &Disabled_Enabled_List,
     Help      "This feature determines whether Graphics Render Standby (RS)is to be enabled."
 
     Combo     $PM_Turbo_Enable, "\tIntel Turbo Boost Technology", &Disabled_Enabled_List,
     Help      "This feature determines whether Intel Turbo Boost Technology is to be enabled."
 
-    Combo     $Panel_Self_Refresh, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List,
-    Help      "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled."
-
     Combo     $Dynamic_FPS_Enable, "\tDynamic Frames Per Second (DFPS)", &Disabled_Enabled_List,
     Help      "This feature determines whether Dynamic Frames Per Second is to be enabled."
 
-    Combo     $DMRRS, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List,
-    Help      "This feature determines whether Dynamic media refresh rate switching is to be enabled."
 
-    Combo     $ADT, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List,
-    Help      "This feature determines whether Assertive display technology is to be enabled. "
-
-    Combo     $Display_LACE_Support, "\tDisplay LACE support", &Supported_List,
-    Help      "This feature determines whether LACE is to be Supported."
-
-    Combo     $LACE_Enabled_Status, "\tDisplay LACE enabled status", &Disabled_Enabled_List,
-    Help      "This feature determines whether Display LACE is to be enabled. "
-
-    Combo     $Agressiveness_Profile, "\tLACE Aggressiveness Profile", &Aggressiveness_Level_Profile,
-    Help      "This field specifies the LACE Aggressiveness Profile Level. "
 
     Page      "ADB Response Data (Mobile only)"
       Link      "Close Table" , ".."
@@ -3369,8 +3517,9 @@ Page      "Integrated Display Configuration"
 
     Title     "    "
     Combo     $bmp_Panel_type, "Select Panel Type:", &Panel_List,
-    Help      "This feature selects the Local Flat Panel (LFP) the GOP and driver is to enable.\r\n\r\n"
-              "Default LFP parameter values:\r\n"
+    Help      "Select the Local Flat Panel (LFP) which display driver will enable.\r\n\r\n"
+              "If panel type is selected as 0xFF, Graphics Software will populate panel index by comparing actual PNP ID Data from panel to that of PNP ID Data for each panel in VBT."
+              "The panel index for which PNP ID Data matches with actual connected panel PNP ID Data is used by driver for all further references. EDID Read is assumed to be enabled if panel index is selected as 0xFF."
               "\tPANEL #01: 640x480 LFP\r\n"
               "\tPANEL #02: 800x600 LFP\r\n"
               "\tPANEL #03: 1024x768 LFP\r\n"
@@ -3395,10 +3544,6 @@ Page      "Integrated Display Configuration"
               "If disabled, there will be no attempt to read an EDID and "
               "other methods will be used to set panel timing."
 
-    Combo     $180_Deg_Rotation_Enable, "Enable 180 Degree Rotation:", &No_Yes_List,
-    Help      "This feature when set to yes, will enable 180 Degree rotation "
-              "otherwise, the rotation functionality will be disabled."
-
     Combo     $LFP_Lane_Reversal, "DDI Lane Reversal: ", &Disabled_Enabled_List,
     Help      "This feature, when enabled, will set lane reversal bit for Selected Port "
 
@@ -3482,6 +3627,9 @@ Page      "Integrated Display Configuration"
       Combo     $eDP_Panel_Color_Depth_01, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List,
       Help      "This feature specifies the color depth of eDP panel used. "
 
+      Combo     $Panel_Rotation_01, "Panel Rotation:", &Panel_Rotation_List,
+      Help      "This feature specifies the Panel Rotation of eDP panel used."
+
       Combo     $eDP_VswingPreEmph_1, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List,
       Help      "This feature selects the VSwing Pre-Emphasis setting table to be used. "
                 "For Icelake, based on the selection respective table will be used.\r\n"
@@ -3524,6 +3672,7 @@ Page      "Integrated Display Configuration"
       Title     " "
       Link      "PSR feature" ,"PSR feature"
       Link      "Apical Feature" , "Apical Feature"
+      Link      "Power Features" , "Power Features"
 
       Page      "eDP Panel Power Sequencing"
         Link      "Close Table", ".."
@@ -3603,7 +3752,7 @@ Page      "Integrated Display Configuration"
         Combo     $PSR_Lines2Wait_B4LinkS3_01, "Lines to wait before link standby:", &wait_line_link,
         Help      "This field determines Lines to wait before link standby \n"
                   " 0 lines to wait (Default)\r\n"
-                  " 2 lines to wait\r\n"
+                  " 1 lines to wait\r\n"
                   " 4 lines to wait\r\n"
                   " 8 lines to wait\r\n"
                   " Others Reserved"
@@ -3646,6 +3795,58 @@ Page      "Integrated Display Configuration"
         Help      "This field specifies the Apical IP specific backlight scale field."
       EndPage   ; Apical Feature
 
+      Page      "Power Features"
+        Link      "Close Table" , ".."
+
+        Combo     $DPST_Enable_01, "\tIntel® Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether the Intel® Display Power Savings Technology (DPST) is enabled or disabled. "
+                  "Intel® DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power."
+                  "\r\n\r\nNote: This technology is only active when the system is running in battery mode and "
+                  "the LFP is the only active display device."
+
+        Combo     $PSR_Enable_01, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled."
+
+        Combo     $DRRS_Enable_01, "\tIntel® Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Intel® Display Refresh Rate Switching (DRRS) is to be enabled."
+
+        Combo     $LACE_Enable_01, "\tEnable Display Lace Support", &Disabled_Enabled_List,
+        Help      "This feature, when enabled, will set Display Lace Support "
+                  "otherwise, the  functionality will be disabled."
+
+        Combo     $ADT_Enable_01, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List,
+        Help      "This feature determines whether Assertive display technology is to be enabled. "
+
+        Combo     $DMRRS_Enable_01, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List,
+        Help      "This feature determines whether Dynamic media refresh rate switching is to be enabled. "
+
+        Combo     $ADB_Enable_01, "\tIntel® Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Intel® Automatic Display Brightness is to be enabled. "
+                  "Intel® Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) "
+                  "depending on the current ambient light environment. "
+                  "When enabled, the driver and VBIOS will control the backlight brightness of the LFP "
+                  "depending on the ambient environment if and only if the LFP is the only active display. "
+                  "When disabled, the driver will perform no action."
+
+        Combo     $LACE_Status_01, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List,
+        Help      "This feature, when enabled, will set Default Display LACE Enabled status "
+                  "otherwise, the  functionality will be disabled."
+
+        Combo     $DPST_Aggressiveness_Profile_01, "\tDPST Aggressiveness Level", &Pwr_Pref_List,
+        Help      "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n"
+                  "1 (Maximum Quality with No DPST)\n"
+                  "2\n"
+                  "3\n"    
+                  "4\n"    
+                  "5\n"
+                  "6 (Maximum Battery)"     
+                  
+        Combo     $LACE_Aggressiveness_Profile_01, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile,
+        Help      "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n"
+                  "Minimum   0\n"
+                  "Moderate  1\n"
+                  "High      2"         
+      EndPage   ; Power Features
 
       Page      "DTD Timings"
         Link      "Close Table" , ".."
@@ -3860,6 +4061,9 @@ Page      "Integrated Display Configuration"
       Combo     $eDP_Panel_Color_Depth_02, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List,
       Help      "This feature specifies the color depth of eDP panel used. "
 
+      Combo     $Panel_Rotation_02, "Panel Rotation:", &Panel_Rotation_List,
+      Help      "This feature specifies the Panel Rotation of eDP panel used."
+
       Combo     $eDP_VswingPreEmph_2, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List,
       Help      "This feature selects the VSwing Pre-Emphasis setting table to be used. "
                 "For Icelake, based on the selection respective table will be used.\r\n"
@@ -3902,6 +4106,7 @@ Page      "Integrated Display Configuration"
       Title     " "
       Link      "PSR feature" ,"PSR feature"
       Link      "Apical Feature" , "Apical Feature"
+      Link      "Power Features" , "Power Features"
 
       Page      "eDP Panel Power Sequencing"
         Link      "Close Table", ".."
@@ -3982,7 +4187,7 @@ Page      "Integrated Display Configuration"
         Combo     $PSR_Lines2Wait_B4LinkS3_02, "Lines to wait before link standby:", &wait_line_link,
         Help      "This field determines Lines to wait before link standby \n"
                   " 0 lines to wait (Default)\r\n"
-                  " 2 lines to wait\r\n"
+                  " 1 lines to wait\r\n"
                   " 4 lines to wait\r\n"
                   " 8 lines to wait\r\n"
                   " Others Reserved"
@@ -4025,6 +4230,58 @@ Page      "Integrated Display Configuration"
         Help      "This field specifies the Apical IP specific backlight scale field."
       EndPage   ; Apical Feature
 
+      Page      "Power Features"
+        Link      "Close Table" , ".."
+
+        Combo     $DPST_Enable_02, "\tIntel® Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether the Intel® Display Power Savings Technology (DPST) is enabled or disabled. "
+                  "Intel® DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power."
+                  "\r\n\r\nNote: This technology is only active when the system is running in battery mode and "
+                  "the LFP is the only active display device."
+
+        Combo     $PSR_Enable_02, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled."
+
+        Combo     $DRRS_Enable_02, "\tIntel® Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Intel® Display Refresh Rate Switching (DRRS) is to be enabled."
+
+        Combo     $LACE_Enable_02, "\tEnable Display Lace Support", &Disabled_Enabled_List,
+        Help      "This feature, when enabled, will set Display Lace Support "
+                  "otherwise, the  functionality will be disabled."
+
+        Combo     $ADT_Enable_02, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List,
+        Help      "This feature determines whether Assertive display technology is to be enabled. "
+
+        Combo     $DMRRS_Enable_02, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List,
+        Help      "This feature determines whether Dynamic media refresh rate switching is to be enabled. "
+
+        Combo     $ADB_Enable_02, "\tIntel® Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Intel® Automatic Display Brightness is to be enabled. "
+                  "Intel® Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) "
+                  "depending on the current ambient light environment. "
+                  "When enabled, the driver and VBIOS will control the backlight brightness of the LFP "
+                  "depending on the ambient environment if and only if the LFP is the only active display. "
+                  "When disabled, the driver will perform no action." 
+
+        Combo     $LACE_Status_02, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List,
+        Help      "This feature, when enabled, will set Default Display LACE Enabled status "
+                  "otherwise, the  functionality will be disabled."
+
+        Combo     $DPST_Aggressiveness_Profile_02, "\tDPST Aggressiveness Level", &Pwr_Pref_List,
+        Help      "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n"
+                  "1 (Maximum Quality with No DPST)\n"
+                  "2\n"
+                  "3\n"    
+                  "4\n"    
+                  "5\n"
+                  "6 (Maximum Battery)"   
+                  
+        Combo     $LACE_Aggressiveness_Profile_02, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile,
+        Help      "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n"
+                  "Minimum   0\n"
+                  "Moderate  1\n"
+                  "High      2"   
+      EndPage   ; Power Features
 
       Page      "DTD Timings"
         Link      "Close Table" , ".."
@@ -4241,6 +4498,9 @@ Page      "Integrated Display Configuration"
       Combo     $eDP_Panel_Color_Depth_03, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List,
       Help      "This feature specifies the color depth of eDP panel used. "
 
+      Combo     $Panel_Rotation_03, "Panel Rotation:", &Panel_Rotation_List,
+      Help      "This feature specifies the Panel Rotation of eDP panel used."
+
       Combo     $eDP_VswingPreEmph_3, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List,
       Help      "This feature selects the VSwing Pre-Emphasis setting table to be used. "
                 "For Icelake, based on the selection respective table will be used.\r\n"
@@ -4284,6 +4544,7 @@ Page      "Integrated Display Configuration"
       Title     " "
       Link      "PSR feature" ,"PSR feature"
       Link      "Apical Feature" , "Apical Feature"
+      Link      "Power Features" , "Power Features"
 
       Page      "eDP Panel Power Sequencing"
         Link      "Close Table", ".."
@@ -4364,7 +4625,7 @@ Page      "Integrated Display Configuration"
         Combo     $PSR_Lines2Wait_B4LinkS3_03, "Lines to wait before link standby:", &wait_line_link,
         Help      "This field determines Lines to wait before link standby \n"
                   " 0 lines to wait (Default)\r\n"
-                  " 2 lines to wait\r\n"
+                  " 1 lines to wait\r\n"
                   " 4 lines to wait\r\n"
                   " 8 lines to wait\r\n"
                   " Others Reserved"
@@ -4407,6 +4668,59 @@ Page      "Integrated Display Configuration"
         Help      "This field specifies the Apical IP specific backlight scale field."
       EndPage   ; Apical Feature
 
+      Page      "Power Features"
+        Link      "Close Table" , ".."
+
+        Combo     $DPST_Enable_03, "\tIntel® Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether the Intel® Display Power Savings Technology (DPST) is enabled or disabled. "
+                  "Intel® DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power."
+                  "\r\n\r\nNote: This technology is only active when the system is running in battery mode and "
+                  "the LFP is the only active display device."
+
+        Combo     $PSR_Enable_03, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled."
+
+        Combo     $DRRS_Enable_03, "\tIntel® Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Intel® Display Refresh Rate Switching (DRRS) is to be enabled."
+
+        Combo     $LACE_Enable_03, "\tEnable Display Lace Support", &Disabled_Enabled_List,
+        Help      "This feature, when enabled, will set Display Lace Support "
+                  "otherwise, the  functionality will be disabled."
+
+        Combo     $ADT_Enable_03, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List,
+        Help      "This feature determines whether Assertive display technology is to be enabled. "
+
+        Combo     $DMRRS_Enable_03, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List,
+        Help      "This feature determines whether Dynamic media refresh rate switching is to be enabled. "
+
+        Combo     $ADB_Enable_03, "\tIntel® Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Intel® Automatic Display Brightness is to be enabled. "
+                  "Intel® Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) "
+                  "depending on the current ambient light environment. "
+                  "When enabled, the driver and VBIOS will control the backlight brightness of the LFP "
+                  "depending on the ambient environment if and only if the LFP is the only active display. "
+                  "When disabled, the driver will perform no action." 
+
+        Combo     $LACE_Status_03, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List,
+        Help      "This feature, when enabled, will set Default Display LACE Enabled status "
+                  "otherwise, the  functionality will be disabled."
+
+        Combo     $DPST_Aggressiveness_Profile_03, "\tDPST Aggressiveness Level", &Pwr_Pref_List,
+        Help      "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n"
+                  "1 (Maximum Quality with No DPST)\n"
+                  "2\n"
+                  "3\n"    
+                  "4\n"    
+                  "5\n"
+                  "6 (Maximum Battery)"    
+                  
+        Combo     $LACE_Aggressiveness_Profile_03, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile,
+        Help      "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n"
+                  "Minimum   0\n"
+                  "Moderate  1\n"
+                  "High      2"
+      EndPage   ; Power Features
+
       Page      "DTD Timings"
         Link      "Close Table" , ".."
 
@@ -4622,6 +4936,9 @@ Page      "Integrated Display Configuration"
       Combo     $eDP_Panel_Color_Depth_04, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List,
       Help      "This feature specifies the color depth of eDP panel used. "
 
+      Combo     $Panel_Rotation_04, "Panel Rotation:", &Panel_Rotation_List,
+      Help      "This feature specifies the Panel Rotation of eDP panel used."
+
       Combo     $eDP_VswingPreEmph_4, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List,
       Help      "This feature selects the VSwing Pre-Emphasis setting table to be used. "
                 "For Icelake, based on the selection respective table will be used.\r\n"
@@ -4665,6 +4982,7 @@ Page      "Integrated Display Configuration"
       Title     " "
       Link      "PSR feature" ,"PSR feature"
       Link      "Apical Feature" , "Apical Feature"
+      Link      "Power Features" , "Power Features"
 
       Page      "eDP Panel Power Sequencing"
         Link      "Close Table", ".."
@@ -4745,7 +5063,7 @@ Page      "Integrated Display Configuration"
         Combo     $PSR_Lines2Wait_B4LinkS3_04, "Lines to wait before link standby:", &wait_line_link,
         Help      "This field determines Lines to wait before link standby \n"
                   " 0 lines to wait (Default)\r\n"
-                  " 2 lines to wait\r\n"
+                  " 1 lines to wait\r\n"
                   " 4 lines to wait\r\n"
                   " 8 lines to wait\r\n"
                   " Others Reserved"
@@ -4788,6 +5106,59 @@ Page      "Integrated Display Configuration"
         Help      "This field specifies the Apical IP specific backlight scale field."
       EndPage   ; Apical Feature
 
+      Page      "Power Features"
+        Link      "Close Table" , ".."
+
+        Combo     $DPST_Enable_04, "\tIntel® Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether the Intel® Display Power Savings Technology (DPST) is enabled or disabled. "
+                  "Intel® DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power."
+                  "\r\n\r\nNote: This technology is only active when the system is running in battery mode and "
+                  "the LFP is the only active display device."
+
+        Combo     $PSR_Enable_04, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled."
+
+        Combo     $DRRS_Enable_04, "\tIntel® Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Intel® Display Refresh Rate Switching (DRRS) is to be enabled."
+
+        Combo     $LACE_Enable_04, "\tEnable Display Lace Support", &Disabled_Enabled_List,
+        Help      "This feature, when enabled, will set Display Lace Support "
+                  "otherwise, the  functionality will be disabled."
+
+        Combo     $ADT_Enable_04, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List,
+        Help      "This feature determines whether Assertive display technology is to be enabled. "
+
+        Combo     $DMRRS_Enable_04, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List,
+        Help      "This feature determines whether Dynamic media refresh rate switching is to be enabled. "
+
+        Combo     $ADB_Enable_04, "\tIntel® Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Intel® Automatic Display Brightness is to be enabled. "
+                  "Intel® Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) "
+                  "depending on the current ambient light environment. "
+                  "When enabled, the driver and VBIOS will control the backlight brightness of the LFP "
+                  "depending on the ambient environment if and only if the LFP is the only active display. "
+                  "When disabled, the driver will perform no action." 
+
+        Combo     $LACE_Status_04, "\tDefault Display LACE Enabled status :", &Disabled_Enabled_List,
+        Help      "This feature, when enabled, will set Default Display LACE Enabled status "
+                  "otherwise, the  functionality will be disabled."
+
+        Combo     $DPST_Aggressiveness_Profile_04, "\tDPST Aggressiveness Level", &Pwr_Pref_List,
+        Help      "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n"
+                  "1 (Maximum Quality with No DPST )\n"
+                  "2\n"
+                  "3\n"    
+                  "4\n"    
+                  "5\n"
+                  "6 (Maximum Battery)"                  
+                  
+        Combo     $LACE_Aggressiveness_Profile_04, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile,
+        Help      "This feature allows for the selection of LACE Agressiveness level for this Panel Type.\n"
+                  "Minimum   0\n"
+                  "Moderate  1\n"
+                  "High      2"
+      EndPage   ; Power Features
+
       Page      "DTD Timings"
         Link      "Close Table" , ".."
 
@@ -5003,6 +5374,9 @@ Page      "Integrated Display Configuration"
       Combo     $eDP_Panel_Color_Depth_05, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List,
       Help      "This feature specifies the color depth of eDP panel used. "
 
+      Combo     $Panel_Rotation_05, "Panel Rotation:", &Panel_Rotation_List,
+      Help      "This feature specifies the Panel Rotation of eDP panel used."
+
       Combo     $eDP_VswingPreEmph_5, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List,
       Help      "This feature selects the VSwing Pre-Emphasis setting table to be used. "
                 "For Icelake, based on the selection respective table will be used.\r\n"
@@ -5045,6 +5419,7 @@ Page      "Integrated Display Configuration"
       Title     " "
       Link      "PSR feature" ,"PSR feature"
       Link      "Apical Feature" , "Apical Feature"
+      Link      "Power Features" , "Power Features"
 
       Page      "eDP Panel Power Sequencing"
         Link      "Close Table", ".."
@@ -5125,7 +5500,7 @@ Page      "Integrated Display Configuration"
         Combo     $PSR_Lines2Wait_B4LinkS3_05, "Lines to wait before link standby:", &wait_line_link,
         Help      "This field determines Lines to wait before link standby \n"
                   " 0 lines to wait (Default)\r\n"
-                  " 2 lines to wait\r\n"
+                  " 1 lines to wait\r\n"
                   " 4 lines to wait\r\n"
                   " 8 lines to wait\r\n"
                   " Others Reserved"
@@ -5168,6 +5543,59 @@ Page      "Integrated Display Configuration"
         Help      "This field specifies the Apical IP specific backlight scale field."
       EndPage   ; Apical Feature
 
+      Page      "Power Features"
+        Link      "Close Table" , ".."
+
+        Combo     $DPST_Enable_05, "\tIntel® Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether the Intel® Display Power Savings Technology (DPST) is enabled or disabled. "
+                  "Intel® DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power."
+                  "\r\n\r\nNote: This technology is only active when the system is running in battery mode and "
+                  "the LFP is the only active display device."
+
+        Combo     $PSR_Enable_05, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled."
+
+        Combo     $DRRS_Enable_05, "\tIntel® Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Intel® Display Refresh Rate Switching (DRRS) is to be enabled."
+
+        Combo     $LACE_Enable_05, "\tEnable Display Lace Support", &Disabled_Enabled_List,
+        Help      "This feature, when enabled, will set Display Lace Support "
+                  "otherwise, the  functionality will be disabled."
+
+        Combo     $ADT_Enable_05, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List,
+        Help      "This feature determines whether Assertive display technology is to be enabled. "
+
+        Combo     $DMRRS_Enable_05, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List,
+        Help      "This feature determines whether Dynamic media refresh rate switching is to be enabled. "
+
+        Combo     $ADB_Enable_05, "\tIntel® Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Intel® Automatic Display Brightness is to be enabled. "
+                  "Intel® Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) "
+                  "depending on the current ambient light environment. "
+                  "When enabled, the driver and VBIOS will control the backlight brightness of the LFP "
+                  "depending on the ambient environment if and only if the LFP is the only active display. "
+                  "When disabled, the driver will perform no action." 
+
+        Combo     $LACE_Status_05, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List,
+        Help      "This feature, when enabled, will set Default Display LACE Enabled status "
+                  "otherwise, the  functionality will be disabled."
+
+        Combo     $DPST_Aggressiveness_Profile_05, "\tDPST Aggressiveness Level", &Pwr_Pref_List,
+        Help      "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n"
+                  "1 (Maximum Quality with No DPST)\n"
+                  "2\n"
+                  "3\n"    
+                  "4\n"    
+                  "5\n"
+                  "6 (Maximum Battery)"                      
+                  
+        Combo     $LACE_Aggressiveness_Profile_05, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile,
+        Help      "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n"
+                  "Minimum   0\n"
+                  "Moderate  1\n"
+                  "High      2"
+      EndPage   ; Power Features
+
       Page      "DTD Timings"
         Link      "Close Table" , ".."
 
@@ -5381,6 +5809,9 @@ Page      "Integrated Display Configuration"
       Combo     $eDP_Panel_Color_Depth_06, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List,
       Help      "This feature specifies the color depth of eDP panel used."
 
+      Combo     $Panel_Rotation_06, "Panel Rotation:", &Panel_Rotation_List,
+      Help      "This feature specifies the Panel Rotation of eDP panel used."
+
       Combo     $eDP_VswingPreEmph_6, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List,
       Help      "This feature selects the VSwing Pre-Emphasis setting table to be used. "
                 "For Icelake, based on the selection respective table will be used.\r\n"
@@ -5423,6 +5854,7 @@ Page      "Integrated Display Configuration"
       Title     " "
       Link      "PSR feature" ,"PSR feature"
       Link      "Apical Feature" , "Apical Feature"
+      Link      "Power Features" , "Power Features"
 
       Page      "eDP Panel Power Sequencing"
         Link      "Close Table", ".."
@@ -5503,7 +5935,7 @@ Page      "Integrated Display Configuration"
         Combo     $PSR_Lines2Wait_B4LinkS3_06, "Lines to wait before link standby:", &wait_line_link,
         Help      "This field determines Lines to wait before link standby \n"
                   " 0 lines to wait (Default)\r\n"
-                  " 2 lines to wait\r\n"
+                  " 1 lines to wait\r\n"
                   " 4 lines to wait\r\n"
                   " 8 lines to wait\r\n"
                   " Others Reserved"
@@ -5546,6 +5978,59 @@ Page      "Integrated Display Configuration"
         Help      "This field specifies the Apical IP specific backlight scale field."
       EndPage   ; Apical Feature
 
+      Page      "Power Features"
+        Link      "Close Table" , ".."
+
+        Combo     $DPST_Enable_06, "\tIntel® Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether the Intel® Display Power Savings Technology (DPST) is enabled or disabled. "
+                  "Intel® DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power."
+                  "\r\n\r\nNote: This technology is only active when the system is running in battery mode and "
+                  "the LFP is the only active display device."
+
+        Combo     $PSR_Enable_06, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled."
+
+        Combo     $DRRS_Enable_06, "\tIntel® Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Intel® Display Refresh Rate Switching (DRRS) is to be enabled."
+
+        Combo     $LACE_Enable_06, "\tEnable Display Lace Support", &Disabled_Enabled_List,
+        Help      "This feature, when enabled, will set Display Lace Support "
+                  "otherwise, the  functionality will be disabled."  
+
+        Combo     $ADT_Enable_06, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List,
+        Help      "This feature determines whether Assertive display technology is to be enabled. "
+
+        Combo     $DMRRS_Enable_06, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List,
+        Help      "This feature determines whether Dynamic media refresh rate switching is to be enabled. "
+
+        Combo     $ADB_Enable_06, "\tIntel® Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Intel® Automatic Display Brightness is to be enabled. "
+                  "Intel® Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) "
+                  "depending on the current ambient light environment. "
+                  "When enabled, the driver and VBIOS will control the backlight brightness of the LFP "
+                  "depending on the ambient environment if and only if the LFP is the only active display. "
+                  "When disabled, the driver will perform no action." 
+
+        Combo     $LACE_Status_06, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List,
+        Help      "This feature, when enabled, will set Default Display LACE Enabled status "
+                  "otherwise, the  functionality will be disabled."
+
+        Combo     $DPST_Aggressiveness_Profile_06, "\tDPST Aggressiveness Level", &Pwr_Pref_List,
+        Help      "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n"
+                  "1 (Maximum Quality with No DPST)\n"
+                  "2\n"
+                  "3\n"    
+                  "4\n"    
+                  "5\n"
+                  "6 (Maximum Battery)"   
+                  
+        Combo     $LACE_Aggressiveness_Profile_06, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile,
+        Help      "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n"
+                  "Minimum   0\n"
+                  "Moderate  1\n"
+                  "High      2"                   
+      EndPage   ; Power Features
+
       Page      "DTD Timings"
         Link      "Close Table" , ".."
 
@@ -5760,6 +6245,9 @@ Page      "Integrated Display Configuration"
       Combo     $eDP_Panel_Color_Depth_07, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List,
       Help      "This feature specifies the color depth of eDP panel used."
 
+      Combo     $Panel_Rotation_07, "Panel Rotation:", &Panel_Rotation_List,
+      Help      "This feature specifies the Panel Rotation of eDP panel used."
+
       Combo     $eDP_VswingPreEmph_7, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List,
       Help      "This feature selects the VSwing Pre-Emphasis setting table to be used. "
                 "For Icelake, based on the selection respective table will be used.\r\n"
@@ -5802,6 +6290,7 @@ Page      "Integrated Display Configuration"
       Title     " "
       Link      "PSR feature" ,"PSR feature"
       Link      "Apical Feature" , "Apical Feature"
+      Link      "Power Features" , "Power Features"
 
       Page      "eDP Panel Power Sequencing"
         Link      "Close Table", ".."
@@ -5882,7 +6371,7 @@ Page      "Integrated Display Configuration"
         Combo     $PSR_Lines2Wait_B4LinkS3_07, "Lines to wait before link standby:", &wait_line_link,
         Help      "This field determines Lines to wait before link standby \n"
                   " 0 lines to wait (Default)\r\n"
-                  " 2 lines to wait\r\n"
+                  " 1 lines to wait\r\n"
                   " 4 lines to wait\r\n"
                   " 8 lines to wait\r\n"
                   " Others Reserved"
@@ -5925,6 +6414,59 @@ Page      "Integrated Display Configuration"
         Help      "This field specifies the Apical IP specific backlight scale field."
       EndPage   ; Apical Feature
 
+      Page      "Power Features"
+        Link      "Close Table" , ".."
+
+        Combo     $DPST_Enable_07, "\tIntel® Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether the Intel® Display Power Savings Technology (DPST) is enabled or disabled. "
+                  "Intel® DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power."
+                  "\r\n\r\nNote: This technology is only active when the system is running in battery mode and "
+                  "the LFP is the only active display device."
+
+        Combo     $PSR_Enable_07, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled."
+
+        Combo     $DRRS_Enable_07, "\tIntel® Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Intel® Display Refresh Rate Switching (DRRS) is to be enabled."
+
+        Combo     $LACE_Enable_07, "\tEnable Display Lace Support", &Disabled_Enabled_List,
+        Help      "This feature, when enabled, will set Display Lace Support "
+                  "otherwise, the  functionality will be disabled. " 
+
+        Combo     $ADT_Enable_07, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List,
+        Help      "This feature determines whether Assertive display technology is to be enabled. "
+
+        Combo     $DMRRS_Enable_07, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List,
+        Help      "This feature determines whether Dynamic media refresh rate switching is to be enabled. "
+
+        Combo     $ADB_Enable_07, "\tIntel® Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Intel® Automatic Display Brightness is to be enabled. "
+                  "Intel® Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) "
+                  "depending on the current ambient light environment. "
+                  "When enabled, the driver and VBIOS will control the backlight brightness of the LFP "
+                  "depending on the ambient environment if and only if the LFP is the only active display. "
+                  "When disabled, the driver will perform no action." 
+
+        Combo     $LACE_Status_07, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List,
+        Help      "This feature, when enabled, will set Default Display LACE Enabled status "
+                  "otherwise, the  functionality will be disabled."
+
+        Combo     $DPST_Aggressiveness_Profile_07, "\tDPST Aggressiveness Level", &Pwr_Pref_List,
+        Help      "This feature allows for the selection of DPST Aggressiveness level for this Panel Type. \n"
+                  "1 (Maximum Quality with No DPST)\n"
+                  "2\n"
+                  "3\n"    
+                  "4\n"    
+                  "5\n"
+                  "6 (Maximum Battery) "                     
+                  
+        Combo     $LACE_Aggressiveness_Profile_07, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile,
+        Help      "This feature allows for the selection of LACE Agressiveness level for this Panel Type. \n"
+                  "Minimum   0\n"
+                  "Moderate  1\n"
+                  "High      2"
+      EndPage   ; Power Features
+
       Page      "DTD Timings"
         Link      "Close Table" , ".."
 
@@ -6137,6 +6679,9 @@ Page      "Integrated Display Configuration"
       Combo     $eDP_Panel_Color_Depth_08, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List,
       Help      "This feature specifies the color depth of eDP panel used."
 
+      Combo     $Panel_Rotation_08, "Panel Rotation:", &Panel_Rotation_List,
+      Help      "This feature specifies the Panel Rotation of eDP panel used."
+
       Combo     $eDP_VswingPreEmph_8, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List,
       Help      "This feature selects the VSwing Pre-Emphasis setting table to be used. "
                 "For Icelake, based on the selection respective table will be used.\r\n"
@@ -6179,6 +6724,7 @@ Page      "Integrated Display Configuration"
       Title     " "
       Link      "PSR feature" ,"PSR feature"
       Link      "Apical Feature" , "Apical Feature"
+      Link      "Power Features" , "Power Features"
 
       Page      "eDP Panel Power Sequencing"
         Link      "Close Table", ".."
@@ -6259,7 +6805,7 @@ Page      "Integrated Display Configuration"
         Combo     $PSR_Lines2Wait_B4LinkS3_08, "Lines to wait before link standby:", &wait_line_link,
         Help      "This field determines Lines to wait before link standby \n"
                   " 0 lines to wait (Default)\r\n"
-                  " 2 lines to wait\r\n"
+                  " 1 lines to wait\r\n"
                   " 4 lines to wait\r\n"
                   " 8 lines to wait\r\n"
                   " Others Reserved"
@@ -6302,6 +6848,59 @@ Page      "Integrated Display Configuration"
         Help      "This field specifies the Apical IP specific backlight scale field."
       EndPage   ; Apical Feature
 
+      Page      "Power Features"
+        Link      "Close Table" , ".."
+
+        Combo     $DPST_Enable_08, "\tIntel® Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether the Intel® Display Power Savings Technology (DPST) is enabled or disabled. "
+                  "Intel® DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power."
+                  "\r\n\r\nNote: This technology is only active when the system is running in battery mode and "
+                  "the LFP is the only active display device."
+
+        Combo     $PSR_Enable_08, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled."
+
+        Combo     $DRRS_Enable_08, "\tIntel® Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Intel® Display Refresh Rate Switching (DRRS) is to be enabled."
+
+        Combo     $LACE_Enable_08, "\tEnable Display Lace Support", &Disabled_Enabled_List,
+        Help      "This feature, when enabled, will set Display Lace Support "
+                  "otherwise, the  functionality will be disabled."
+
+        Combo     $ADT_Enable_08, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List,
+        Help      "This feature determines whether Assertive display technology is to be enabled. "
+
+        Combo     $DMRRS_Enable_08, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List,
+        Help      "This feature determines whether Dynamic media refresh rate switching is to be enabled. "
+
+        Combo     $ADB_Enable_08, "\tIntel® Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Intel® Automatic Display Brightness is to be enabled. "
+                  "Intel® Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) "
+                  "depending on the current ambient light environment. "
+                  "When enabled, the driver and VBIOS will control the backlight brightness of the LFP "
+                  "depending on the ambient environment if and only if the LFP is the only active display. "
+                  "When disabled, the driver will perform no action."   
+
+        Combo     $LACE_Status_08, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List,
+        Help      "This feature, when enabled, will set Default Display LACE Enabled status "
+                  "otherwise, the  functionality will be disabled."
+
+        Combo     $DPST_Aggressiveness_Profile_08, "\tDPST Aggressiveness Level", &Pwr_Pref_List,
+        Help      "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n"
+                  "1 (Maximum Quality with No DPST)\n"
+                  "2\n"
+                  "3\n"    
+                  "4\n"    
+                  "5\n"
+                  "6 (Maximum Battery)"
+
+        Combo     $LACE_Aggressiveness_Profile_08, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile,
+        Help      "This feature allows for the selection of LACE Agressiveness level for this Panel Type.\n"
+                  "Minimum   0\n"
+                  "Moderate  1\n"
+                  "High      2"
+      EndPage   ; Power Features
+
       Page      "DTD Timings"
         Link      "Close Table" , ".."
 
@@ -6515,6 +7114,9 @@ Page      "Integrated Display Configuration"
       Combo     $eDP_Panel_Color_Depth_09, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List,
       Help      "This feature specifies the color depth of eDP panel used."
 
+      Combo     $Panel_Rotation_09, "Panel Rotation:", &Panel_Rotation_List,
+      Help      "This feature specifies the Panel Rotation of eDP panel used."
+
       Combo     $eDP_VswingPreEmph_9, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List,
       Help      "This feature selects the VSwing Pre-Emphasis setting table to be used. "
                 "For Icelake, based on the selection respective table will be used.\r\n"
@@ -6557,6 +7159,7 @@ Page      "Integrated Display Configuration"
       Title     " "
       Link      "PSR feature" ,"PSR feature"
       Link      "Apical Feature" , "Apical Feature"
+      Link      "Power Features" , "Power Features"
 
       Page      "eDP Panel Power Sequencing"
         Link      "Close Table", ".."
@@ -6637,7 +7240,7 @@ Page      "Integrated Display Configuration"
         Combo     $PSR_Lines2Wait_B4LinkS3_09, "Lines to wait before link standby:", &wait_line_link,
         Help      "This field determines Lines to wait before link standby \n"
                   " 0 lines to wait (Default)\r\n"
-                  " 2 lines to wait\r\n"
+                  " 1 lines to wait\r\n"
                   " 4 lines to wait\r\n"
                   " 8 lines to wait\r\n"
                   " Others Reserved"
@@ -6680,6 +7283,59 @@ Page      "Integrated Display Configuration"
         Help      "This field specifies the Apical IP specific backlight scale field."
       EndPage   ; Apical Feature
 
+      Page      "Power Features"
+        Link      "Close Table" , ".."
+
+        Combo     $DPST_Enable_09, "\tIntel® Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether the Intel® Display Power Savings Technology (DPST) is enabled or disabled. "
+                  "Intel® DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power."
+                  "\r\n\r\nNote: This technology is only active when the system is running in battery mode and "
+                  "the LFP is the only active display device."
+
+        Combo     $PSR_Enable_09, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled."
+
+        Combo     $DRRS_Enable_09, "\tIntel® Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Intel® Display Refresh Rate Switching (DRRS) is to be enabled."
+
+        Combo     $LACE_Enable_09, "\tEnable Display Lace Support", &Disabled_Enabled_List,
+        Help      "This feature, when enabled, will set Display Lace Support "
+                  "otherwise, the  functionality will be disabled. "
+
+        Combo     $ADT_Enable_09, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List,
+        Help      "This feature determines whether Assertive display technology is to be enabled. "
+
+        Combo     $DMRRS_Enable_09, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List,
+        Help      "This feature determines whether Dynamic media refresh rate switching is to be enabled. "
+
+        Combo     $ADB_Enable_09, "\tIntel® Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Intel® Automatic Display Brightness is to be enabled. "
+                  "Intel® Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) "
+                  "depending on the current ambient light environment. "
+                  "When enabled, the driver and VBIOS will control the backlight brightness of the LFP "
+                  "depending on the ambient environment if and only if the LFP is the only active display. "
+                  "When disabled, the driver will perform no action."  
+
+        Combo     $LACE_Status_09, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List,
+        Help      "This feature, when enabled, will set Default Display LACE Enabled status "
+                  "otherwise, the  functionality will be disabled."
+
+        Combo     $DPST_Aggressiveness_Profile_09, "\tDPST Aggressiveness Level", &Pwr_Pref_List,
+        Help      "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n"
+                  "1 (Maximum Quality with No DPST)\n"
+                  "2\n"
+                  "3\n"    
+                  "4\n"    
+                  "5\n"
+                  "6 (Maximum Battery)"      
+                  
+        Combo     $LACE_Aggressiveness_Profile_09, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile,
+        Help      "This feature allows for the selection of LACE Agressiveness level for this Panel Type.\n"
+                  "Minimum   0\n"
+                  "Moderate  1\n"
+                  "High      2"            
+      EndPage   ; Power Features
+
       Page      "DTD Timings"
         Link      "Close Table" , ".."
 
@@ -6892,6 +7548,9 @@ Page      "Integrated Display Configuration"
       Combo     $eDP_Panel_Color_Depth_10, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List,
       Help      "This feature specifies the color depth of eDP panel used."
 
+      Combo     $Panel_Rotation_10, "Panel Rotation:", &Panel_Rotation_List,
+      Help      "This feature specifies the Panel Rotation of eDP panel used."
+
       Combo     $eDP_VswingPreEmph_10, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List,
       Help      "This feature selects the VSwing Pre-Emphasis setting table to be used. "
                 "For Icelake, based on the selection respective table will be used.\r\n"
@@ -6935,6 +7594,7 @@ Page      "Integrated Display Configuration"
       Title     " "
       Link      "PSR feature" ,"PSR feature"
       Link      "Apical Feature" , "Apical Feature"
+      Link      "Power Features" , "Power Features"
 
       Page      "eDP Panel Power Sequencing"
         Link      "Close Table", ".."
@@ -7015,7 +7675,7 @@ Page      "Integrated Display Configuration"
         Combo     $PSR_Lines2Wait_B4LinkS3_10, "Lines to wait before link standby:", &wait_line_link,
         Help      "This field determines Lines to wait before link standby \n"
                   " 0 lines to wait (Default)\r\n"
-                  " 2 lines to wait\r\n"
+                  " 1 lines to wait\r\n"
                   " 4 lines to wait\r\n"
                   " 8 lines to wait\r\n"
                   " Others Reserved"
@@ -7058,6 +7718,59 @@ Page      "Integrated Display Configuration"
         Help      "This field specifies the Apical IP specific backlight scale field."
       EndPage   ; Apical Feature
 
+      Page      "Power Features"
+        Link      "Close Table" , ".."
+
+        Combo     $DPST_Enable_10, "\tIntel® Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether the Intel® Display Power Savings Technology (DPST) is enabled or disabled. "
+                  "Intel® DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power."
+                  "\r\n\r\nNote: This technology is only active when the system is running in battery mode and "
+                  "the LFP is the only active display device."
+
+        Combo     $PSR_Enable_10, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled."
+
+        Combo     $DRRS_Enable_10, "\tIntel® Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Intel® Display Refresh Rate Switching (DRRS) is to be enabled."
+
+        Combo     $LACE_Enable_10, "\tEnable Display Lace Support", &Disabled_Enabled_List,
+        Help      "This feature, when enabled, will set Display Lace Support "
+                  "otherwise, the  functionality will be disabled. "
+
+        Combo     $ADT_Enable_10, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List,
+        Help      "This feature determines whether Assertive display technology is to be enabled. "
+
+        Combo     $DMRRS_Enable_10, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List,
+        Help      "This feature determines whether Dynamic media refresh rate switching is to be enabled. "
+
+        Combo     $ADB_Enable_10, "\tIntel® Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Intel® Automatic Display Brightness is to be enabled. "
+                  "Intel® Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) "
+                  "depending on the current ambient light environment. "
+                  "When enabled, the driver and VBIOS will control the backlight brightness of the LFP "
+                  "depending on the ambient environment if and only if the LFP is the only active display. "
+                  "When disabled, the driver will perform no action."   
+
+        Combo     $LACE_Status_10, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List,
+        Help      "This feature, when enabled, will set Default Display LACE Enabled status "
+                  "otherwise, the  functionality will be disabled."
+
+        Combo     $DPST_Aggressiveness_Profile_10, "\tDPST Aggressiveness Level", &Pwr_Pref_List,
+        Help      "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n"
+                  "1 (Maximum Quality with No DPST)\n"
+                  "2\n"
+                  "3\n"    
+                  "4\n"    
+                  "5\n"
+                  "6 (Maximum Battery)"
+                  
+        Combo     $LACE_Aggressiveness_Profile_10, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile,
+        Help      "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n"
+                  "Minimum   0\n"
+                  "Moderate  1\n"
+                  "High      2"                   
+      EndPage   ; Power Features
+
       Page      "DTD Timings"
         Link      "Close Table" , ".."
 
@@ -7270,6 +7983,9 @@ Page      "Integrated Display Configuration"
       Combo     $eDP_Panel_Color_Depth_11, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List,
       Help      "This feature specifies the color depth of eDP panel used."
 
+      Combo     $Panel_Rotation_11, "Panel Rotation:", &Panel_Rotation_List,
+      Help      "This feature specifies the Panel Rotation of eDP panel used."
+
       Combo     $eDP_VswingPreEmph_11, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List,
       Help      "This feature selects the VSwing Pre-Emphasis setting table to be used. "
                 "For Icelake, based on the selection respective table will be used.\r\n"
@@ -7313,6 +8029,7 @@ Page      "Integrated Display Configuration"
       Title     " "
       Link      "PSR feature" ,"PSR feature"
       Link      "Apical Feature" , "Apical Feature"
+      Link      "Power Features" , "Power Features"
 
       Page      "eDP Panel Power Sequencing"
         Link      "Close Table", ".."
@@ -7393,7 +8110,7 @@ Page      "Integrated Display Configuration"
         Combo     $PSR_Lines2Wait_B4LinkS3_11, "Lines to wait before link standby:", &wait_line_link,
         Help      "This field determines Lines to wait before link standby \n"
                   " 0 lines to wait (Default)\r\n"
-                  " 2 lines to wait\r\n"
+                  " 1 lines to wait\r\n"
                   " 4 lines to wait\r\n"
                   " 8 lines to wait\r\n"
                   " Others Reserved"
@@ -7436,6 +8153,59 @@ Page      "Integrated Display Configuration"
         Help      "This field specifies the Apical IP specific backlight scale field."
       EndPage   ; Apical Feature
 
+      Page      "Power Features"
+        Link      "Close Table" , ".."
+
+        Combo     $DPST_Enable_11, "\tIntel® Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether the Intel® Display Power Savings Technology (DPST) is enabled or disabled. "
+                  "Intel® DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power."
+                  "\r\n\r\nNote: This technology is only active when the system is running in battery mode and "
+                  "the LFP is the only active display device."
+
+        Combo     $PSR_Enable_11, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled."
+
+        Combo     $DRRS_Enable_11, "\tIntel® Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Intel® Display Refresh Rate Switching (DRRS) is to be enabled."
+
+        Combo     $LACE_Enable_11, "\tEnable Display Lace Support", &Disabled_Enabled_List,
+        Help      "This feature, when enabled, will set Display Lace Support "
+                  "otherwise, the  functionality will be disabled. " 
+
+        Combo     $ADT_Enable_11, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List,
+        Help      "This feature determines whether Assertive display technology is to be enabled. "
+
+        Combo     $DMRRS_Enable_11, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List,
+        Help      "This feature determines whether Dynamic media refresh rate switching is to be enabled. "
+
+        Combo     $ADB_Enable_11, "\tIntel® Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Intel® Automatic Display Brightness is to be enabled. "
+                  "Intel® Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) "
+                  "depending on the current ambient light environment. "
+                  "When enabled, the driver and VBIOS will control the backlight brightness of the LFP "
+                  "depending on the ambient environment if and only if the LFP is the only active display. "
+                  "When disabled, the driver will perform no action." 
+
+        Combo     $LACE_Status_11, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List,
+        Help      "This feature, when enabled, will set Default Display LACE Enabled status "
+                  "otherwise, the  functionality will be disabled."
+
+        Combo     $DPST_Aggressiveness_Profile_11, "\tDPST Aggressiveness Level", &Pwr_Pref_List,
+        Help      "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n"
+                  "1 (Maximum Quality with No DPST  )\n"
+                  "2\n"
+                  "3\n"    
+                  "4\n"    
+                  "5\n"
+                  "6 (Maximum Battery)"   
+                  
+        Combo     $LACE_Aggressiveness_Profile_11, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile,
+        Help      "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n"
+                  "Minimum   0\n"
+                  "Moderate  1\n"
+                  "High      2"
+      EndPage   ; Power Features
+
       Page      "DTD Timings"
         Link      "Close Table" , ".."
 
@@ -7647,6 +8417,9 @@ Page      "Integrated Display Configuration"
       Combo     $eDP_Panel_Color_Depth_12, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List,
       Help      "This feature specifies the color depth of eDP panel used."
 
+      Combo     $Panel_Rotation_12, "Panel Rotation:", &Panel_Rotation_List,
+      Help      "This feature specifies the Panel Rotation of eDP panel used."
+
       Combo     $eDP_VswingPreEmph_12, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List,
       Help      "This feature selects the VSwing Pre-Emphasis setting table to be used. "
                 "For Icelake, based on the selection respective table will be used.\r\n"
@@ -7689,6 +8462,7 @@ Page      "Integrated Display Configuration"
       Title     " "
       Link      "PSR feature" ,"PSR feature"
       Link      "Apical Feature" , "Apical Feature"
+      Link      "Power Features" , "Power Features"
 
       Page      "eDP Panel Power Sequencing"
         Link      "Close Table", ".."
@@ -7770,7 +8544,7 @@ Page      "Integrated Display Configuration"
         Combo     $PSR_Lines2Wait_B4LinkS3_12, "Lines to wait before link standby:", &wait_line_link,
         Help      "This field determines Lines to wait before link standby \n"
                   " 0 lines to wait (Default)\r\n"
-                  " 2 lines to wait\r\n"
+                  " 1 lines to wait\r\n"
                   " 4 lines to wait\r\n"
                   " 8 lines to wait\r\n"
                   " Others Reserved"
@@ -7813,6 +8587,59 @@ Page      "Integrated Display Configuration"
         Help      "This field specifies the Apical IP specific backlight scale field."
       EndPage   ; Apical Feature
 
+      Page      "Power Features"
+        Link      "Close Table" , ".."
+
+        Combo     $DPST_Enable_12, "\tIntel® Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether the Intel® Display Power Savings Technology (DPST) is enabled or disabled. "
+                  "Intel® DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power."
+                  "\r\n\r\nNote: This technology is only active when the system is running in battery mode and "
+                  "the LFP is the only active display device."
+
+        Combo     $PSR_Enable_12, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled."
+
+        Combo     $DRRS_Enable_12, "\tIntel® Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Intel® Display Refresh Rate Switching (DRRS) is to be enabled."
+
+        Combo     $LACE_Enable_12, "\tEnable Display Lace Support", &Disabled_Enabled_List,
+        Help      "This feature, when enabled, will set Display Lace Support "
+                  "otherwise, the  functionality will be disabled. "
+
+        Combo     $ADT_Enable_12, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List,
+        Help      "This feature determines whether Assertive display technology is to be enabled. "
+
+        Combo     $DMRRS_Enable_12, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List,
+        Help      "This feature determines whether Dynamic media refresh rate switching is to be enabled."
+
+        Combo     $ADB_Enable_12, "\tIntel® Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Intel® Automatic Display Brightness is to be enabled. "
+                  "Intel® Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) "
+                  "depending on the current ambient light environment. "
+                  "When enabled, the driver and VBIOS will control the backlight brightness of the LFP "
+                  "depending on the ambient environment if and only if the LFP is the only active display. "
+                  "When disabled, the driver will perform no action." 
+
+        Combo     $LACE_Status_12, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List,
+        Help      "This feature, when enabled, will set Default Display LACE Enabled status "
+                  "otherwise, the  functionality will be disabled."
+
+        Combo     $DPST_Aggressiveness_Profile_12, "\tDPST Aggressiveness Level", &Pwr_Pref_List,
+        Help      "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n"
+                  "1 (Maximum Quality with No DPST)\n"
+                  "2\n"
+                  "3\n"    
+                  "4\n"    
+                  "5\n"
+                  "6 (Maximum Battery)"    
+                  
+        Combo     $LACE_Aggressiveness_Profile_12, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile,
+        Help      "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n"
+                  "Minimum   0\n"
+                  "Moderate  1\n"
+                  "High      2"             
+      EndPage   ; Power Features
+
       Page      "DTD Timings"
         Link      "Close Table" , ".."
 
@@ -8024,6 +8851,9 @@ Page      "Integrated Display Configuration"
       Combo     $eDP_Panel_Color_Depth_13, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List,
       Help      "This feature specifies the color depth of eDP panel used."
 
+      Combo     $Panel_Rotation_13, "Panel Rotation:", &Panel_Rotation_List,
+      Help      "This feature specifies the Panel Rotation of eDP panel used."
+
       Combo     $eDP_VswingPreEmph_13, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List,
       Help      "This feature selects the VSwing Pre-Emphasis setting table to be used. "
                 "For Icelake, based on the selection respective table will be used.\r\n"
@@ -8067,6 +8897,7 @@ Page      "Integrated Display Configuration"
       Title     " "
       Link      "PSR feature" ,"PSR feature"
       Link      "Apical Feature" , "Apical Feature"
+      Link      "Power Features" , "Power Features"
 
       Page      "eDP Panel Power Sequencing"
         Link      "Close Table", ".."
@@ -8148,7 +8979,7 @@ Page      "Integrated Display Configuration"
         Combo     $PSR_Lines2Wait_B4LinkS3_13, "Lines to wait before link standby:", &wait_line_link,
         Help      "This field determines Lines to wait before link standby \n"
                   " 0 lines to wait (Default)\r\n"
-                  " 2 lines to wait\r\n"
+                  " 1 lines to wait\r\n"
                   " 4 lines to wait\r\n"
                   " 8 lines to wait\r\n"
                   " Others Reserved"
@@ -8191,6 +9022,59 @@ Page      "Integrated Display Configuration"
         Help      "This field specifies the Apical IP specific backlight scale field."
       EndPage   ; Apical Feature
 
+      Page      "Power Features"
+        Link      "Close Table" , ".."
+
+        Combo     $DPST_Enable_13, "\tIntel® Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether the Intel® Display Power Savings Technology (DPST) is enabled or disabled. "
+                  "Intel® DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power."
+                  "\r\n\r\nNote: This technology is only active when the system is running in battery mode and "
+                  "the LFP is the only active display device."
+
+        Combo     $PSR_Enable_13, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled."
+
+        Combo     $DRRS_Enable_13, "\tIntel® Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Intel® Display Refresh Rate Switching (DRRS) is to be enabled."
+
+        Combo     $LACE_Enable_13, "\tEnable Display Lace Support", &Disabled_Enabled_List,
+        Help      "This feature, when enabled, will set Display Lace Support "
+                  "otherwise, the  functionality will be disabled. "
+
+        Combo     $ADT_Enable_13, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List,
+        Help      "This feature determines whether Assertive display technology is to be enabled. "
+
+        Combo     $DMRRS_Enable_13, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List,
+        Help      "This feature determines whether Dynamic media refresh rate switching is to be enabled. "
+
+        Combo     $ADB_Enable_13, "\tIntel® Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Intel® Automatic Display Brightness is to be enabled. "
+                  "Intel® Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) "
+                  "depending on the current ambient light environment. "
+                  "When enabled, the driver and VBIOS will control the backlight brightness of the LFP "
+                  "depending on the ambient environment if and only if the LFP is the only active display. "
+                  "When disabled, the driver will perform no action." 
+
+        Combo     $LACE_Status_13, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List,
+        Help      "This feature, when enabled, will set Default Display LACE Enabled status "
+                  "otherwise, the  functionality will be disabled."
+
+        Combo     $DPST_Aggressiveness_Profile_13, "\tDPST Aggressiveness Level", &Pwr_Pref_List,
+        Help      "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n"
+                  "1 (Maximum Quality with No DPST)\n"
+                  "2\n"
+                  "3\n"    
+                  "4\n"    
+                  "5\n"
+                  "6 (Maximum Battery)"               
+                  
+        Combo     $LACE_Aggressiveness_Profile_13, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile,
+        Help      "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n"
+                  "Minimum   0\n"
+                  "Moderate  1\n"
+                  "High      2"
+      EndPage   ; Power Features
+
       Page      "DTD Timings"
         Link      "Close Table" , ".."
 
@@ -8402,6 +9286,9 @@ Page      "Integrated Display Configuration"
       Combo     $eDP_Panel_Color_Depth_14, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List,
       Help      "This feature specifies the color depth of eDP panel used."
 
+      Combo     $Panel_Rotation_14, "Panel Rotation:", &Panel_Rotation_List,
+      Help      "This feature specifies the Panel Rotation of eDP panel used."
+
       Combo     $eDP_VswingPreEmph_14, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List,
       Help      "This feature selects the VSwing Pre-Emphasis setting table to be used. "
                 "For Icelake, based on the selection respective table will be used.\r\n"
@@ -8445,6 +9332,7 @@ Page      "Integrated Display Configuration"
       Title     " "
       Link      "PSR feature" ,"PSR feature"
       Link      "Apical Feature" , "Apical Feature"
+      Link      "Power Features" , "Power Features"
 
       Page      "eDP Panel Power Sequencing"
         Link      "Close Table", ".."
@@ -8525,7 +9413,7 @@ Page      "Integrated Display Configuration"
         Combo     $PSR_Lines2Wait_B4LinkS3_14, "Lines to wait before link standby:", &wait_line_link,
         Help      "This field determines Lines to wait before link standby \n"
                   " 0 lines to wait (Default)\r\n"
-                  " 2 lines to wait\r\n"
+                  " 1 lines to wait\r\n"
                   " 4 lines to wait\r\n"
                   " 8 lines to wait\r\n"
                   " Others Reserved"
@@ -8568,6 +9456,59 @@ Page      "Integrated Display Configuration"
         Help      "This field specifies the Apical IP specific backlight scale field."
       EndPage   ; Apical Feature
 
+      Page      "Power Features"
+        Link      "Close Table" , ".."
+
+        Combo     $DPST_Enable_14, "\tIntel® Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether the Intel® Display Power Savings Technology (DPST) is enabled or disabled. "
+                  "Intel® DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power."
+                  "\r\n\r\nNote: This technology is only active when the system is running in battery mode and "
+                  "the LFP is the only active display device."
+
+        Combo     $PSR_Enable_14, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled."
+
+        Combo     $DRRS_Enable_14, "\tIntel® Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Intel® Display Refresh Rate Switching (DRRS) is to be enabled."
+
+        Combo     $LACE_Enable_14, "\tEnable Display Lace Support", &Disabled_Enabled_List,
+        Help      "This feature, when enabled, will set Display Lace Support "
+                  "otherwise, the  functionality will be disabled. "
+
+        Combo     $ADT_Enable_14, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List,
+        Help      "This feature determines whether Assertive display technology is to be enabled. "
+
+        Combo     $DMRRS_Enable_14, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List,
+        Help      "This feature determines whether Dynamic media refresh rate switching is to be enabled. "
+
+        Combo     $ADB_Enable_14, "\tIntel® Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Intel® Automatic Display Brightness is to be enabled. "
+                  "Intel® Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) "
+                  "depending on the current ambient light environment. "
+                  "When enabled, the driver and VBIOS will control the backlight brightness of the LFP "
+                  "depending on the ambient environment if and only if the LFP is the only active display. "
+                  "When disabled, the driver will perform no action." 
+
+        Combo     $LACE_Status_14, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List,
+        Help      "This feature, when enabled, will set Default Display LACE Enabled status "
+                  "otherwise, the  functionality will be disabled."
+
+        Combo     $DPST_Aggressiveness_Profile_14, "\tDPST Aggressiveness Level", &Pwr_Pref_List,
+        Help      "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n"
+                  "1 (Maximum Quality with No DPST)\n"
+                  "2\n"
+                  "3\n"    
+                  "4\n"    
+                  "5\n"
+                  "6 (Maximum Battery)"              
+                  
+        Combo     $LACE_Aggressiveness_Profile_14, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile,
+        Help      "This feature allows for the selection of LACE Agressiveness level for this Panel Type.\n"
+                  "Minimum   0\n"
+                  "Moderate  1\n"
+                  "High      2"
+      EndPage   ; Power Features
+
       Page      "DTD Timings"
         Link      "Close Table" , ".."
 
@@ -8779,6 +9720,9 @@ Page      "Integrated Display Configuration"
       Combo     $eDP_Panel_Color_Depth_15, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List,
       Help      "This feature specifies the color depth of eDP panel used."
 
+      Combo     $Panel_Rotation_15, "Panel Rotation:", &Panel_Rotation_List,
+      Help      "This feature specifies the Panel Rotation of eDP panel used."
+
       Combo     $eDP_VswingPreEmph_15, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List,
       Help      "This feature selects the VSwing Pre-Emphasis setting table to be used. "
                 "For Icelake, based on the selection respective table will be used.\r\n"
@@ -8821,6 +9765,7 @@ Page      "Integrated Display Configuration"
       Title     " "
       Link      "PSR feature" ,"PSR feature"
       Link      "Apical Feature" , "Apical Feature"
+      Link      "Power Features" , "Power Features"
 
       Page      "eDP Panel Power Sequencing"
         Link      "Close Table", ".."
@@ -8901,7 +9846,7 @@ Page      "Integrated Display Configuration"
         Combo     $PSR_Lines2Wait_B4LinkS3_15, "Lines to wait before link standby:", &wait_line_link,
         Help      "This field determines Lines to wait before link standby \n"
                   " 0 lines to wait (Default)\r\n"
-                  " 2 lines to wait\r\n"
+                  " 1 lines to wait\r\n"
                   " 4 lines to wait\r\n"
                   " 8 lines to wait\r\n"
                   " Others Reserved"
@@ -8944,6 +9889,59 @@ Page      "Integrated Display Configuration"
         Help      "This field specifies the Apical IP specific backlight scale field."
       EndPage   ; Apical Feature
 
+      Page      "Power Features"
+        Link      "Close Table" , ".."
+
+        Combo     $DPST_Enable_15, "\tIntel® Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether the Intel® Display Power Savings Technology (DPST) is enabled or disabled. "
+                  "Intel® DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power."
+                  "\r\n\r\nNote: This technology is only active when the system is running in battery mode and "
+                  "the LFP is the only active display device."
+
+        Combo     $PSR_Enable_15, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled."
+
+        Combo     $DRRS_Enable_15, "\tIntel® Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Intel® Display Refresh Rate Switching (DRRS) is to be enabled."
+
+        Combo     $LACE_Enable_15, "\tEnable Display Lace Support", &Disabled_Enabled_List,
+        Help      "This feature, when enabled, will set Display Lace Support "
+                  "otherwise, the  functionality will be disabled. "
+
+        Combo     $ADT_Enable_15, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List,
+        Help      "This feature determines whether Assertive display technology is to be enabled. "
+
+        Combo     $DMRRS_Enable_15, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List,
+        Help      "This feature determines whether Dynamic media refresh rate switching is to be enabled. "
+
+        Combo     $ADB_Enable_15, "\tIntel® Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Intel® Automatic Display Brightness is to be enabled. "
+                  "Intel® Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) "
+                  "depending on the current ambient light environment. "
+                  "When enabled, the driver and VBIOS will control the backlight brightness of the LFP "
+                  "depending on the ambient environment if and only if the LFP is the only active display. "
+                  "When disabled, the driver will perform no action." 
+
+        Combo     $LACE_Status_15, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List,
+        Help      "This feature, when enabled, will set Default Display LACE Enabled status "
+                  "otherwise, the  functionality will be disabled."
+
+        Combo     $DPST_Aggressiveness_Profile_15, "\tDPST Aggressiveness Level", &Pwr_Pref_List,
+        Help      "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n"
+                  "1 (Maximum Quality with No DPST)\n"
+                  "2\n"
+                  "3\n"    
+                  "4\n"    
+                  "5\n"
+                  "6 (Maximum Battery)"       
+                  
+        Combo     $LACE_Aggressiveness_Profile_15, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile,
+        Help      "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n"
+                  "Minimum   0\n"
+                  "Moderate  1\n"
+                  "High      2"
+      EndPage   ; Power Features
+
       Page      "DTD Timings"
         Link      "Close Table" , ".."
 
@@ -9154,6 +10152,9 @@ Page      "Integrated Display Configuration"
       Combo     $eDP_Panel_Color_Depth_16, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List,
       Help      "This feature specifies the color depth of eDP panel used."
 
+      Combo     $Panel_Rotation_16, "Panel Rotation:", &Panel_Rotation_List,
+      Help      "This feature specifies the Panel Rotation of eDP panel used."
+
       Combo     $eDP_VswingPreEmph_16, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List,
       Help      "This feature selects the VSwing Pre-Emphasis setting table to be used. "
                 "For Icelake, based on the selection respective table will be used.\r\n"
@@ -9196,6 +10197,7 @@ Page      "Integrated Display Configuration"
       Title     " "
       Link      "PSR feature" ,"PSR feature"
       Link      "Apical Feature" , "Apical Feature"
+      Link      "Power Features" , "Power Features"
 
       Page      "eDP Panel Power Sequencing"
         Link      "Close Table", ".."
@@ -9276,7 +10278,7 @@ Page      "Integrated Display Configuration"
         Combo     $PSR_Lines2Wait_B4LinkS3_16, "Lines to wait before link standby:", &wait_line_link,
         Help      "This field determines Lines to wait before link standby \n"
                   " 0 lines to wait (Default)\r\n"
-                  " 2 lines to wait\r\n"
+                  " 1 lines to wait\r\n"
                   " 4 lines to wait\r\n"
                   " 8 lines to wait\r\n"
                   " Others Reserved"
@@ -9319,6 +10321,59 @@ Page      "Integrated Display Configuration"
         Help      "This field specifies the Apical IP specific backlight scale field."
       EndPage   ; Apical Feature
 
+      Page      "Power Features"
+        Link      "Close Table" , ".."
+
+        Combo     $DPST_Enable_16, "\tIntel® Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether the Intel® Display Power Savings Technology (DPST) is enabled or disabled. "
+                  "Intel® DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power."
+                  "\r\n\r\nNote: This technology is only active when the system is running in battery mode and "
+                  "the LFP is the only active display device."
+
+        Combo     $PSR_Enable_16, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled."
+
+        Combo     $DRRS_Enable_16, "\tIntel® Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Intel® Display Refresh Rate Switching (DRRS) is to be enabled."
+
+        Combo     $LACE_Enable_16, "\tEnable Display Lace Support", &Disabled_Enabled_List,
+        Help      "This feature, when enabled, will set Display Lace Support "
+                  "otherwise, the  functionality will be disabled. "
+
+        Combo     $ADT_Enable_16, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List,
+        Help      "This feature determines whether Assertive display technology is to be enabled. "
+
+        Combo     $DMRRS_Enable_16, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List,
+        Help      "This feature determines whether Dynamic media refresh rate switching is to be enabled. "
+
+        Combo     $ADB_Enable_16, "\tIntel® Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Intel® Automatic Display Brightness is to be enabled. "
+                  "Intel® Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) "
+                  "depending on the current ambient light environment. "
+                  "When enabled, the driver and VBIOS will control the backlight brightness of the LFP "
+                  "depending on the ambient environment if and only if the LFP is the only active display. "
+                  "When disabled, the driver will perform no action." 
+
+        Combo     $LACE_Status_16, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List,
+        Help      "This feature, when enabled, will set Default Display LACE Enabled status "
+                  "otherwise, the  functionality will be disabled."
+
+        Combo     $DPST_Aggressiveness_Profile_16, "\tDPST Aggressiveness Level", &Pwr_Pref_List,
+        Help      "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n"
+                  "1 (Maximum Quality with No DPST)\n"
+                  "2\n"
+                  "3\n"    
+                  "4\n"    
+                  "5\n"
+                  "6 (Maximum Battery)"              
+                  
+        Combo     $LACE_Aggressiveness_Profile_16, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile,
+        Help      "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n"
+                  "Minimum   0\n"
+                  "Moderate  1\n"
+                  "High      2"
+      EndPage   ; Power Features
+
       Page      "DTD Timings"
         Link      "Close Table" , ".."