mirror of https://review.coreboot.org/fsp.git
Coffee Lake FSP 7.0.60.20
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ClientSysFWGit
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@ -3,13 +3,8 @@
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Boot Setting File for Platform Configuration.
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Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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SPDX-License-Identifier: BSD-2-Clause-Patent
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This file is automatically generated. Please do NOT modify !!!
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@ -760,7 +755,15 @@ StructDef
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$gPlatformFspPkgTokenSpaceGuid_PchUsbLtrHighIdleTimeOverride 4 bytes $_DEFAULT_ = 0x00000000
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$gPlatformFspPkgTokenSpaceGuid_PchUsbLtrMediumIdleTimeOverride 4 bytes $_DEFAULT_ = 0x00000000
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$gPlatformFspPkgTokenSpaceGuid_PchUsbLtrLowIdleTimeOverride 4 bytes $_DEFAULT_ = 0x00000000
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Skip 93 bytes
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$gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate3UniqTranEnable 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
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$gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate3UniqTran 10 bytes $_DEFAULT_ = 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C
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$gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate2UniqTranEnable 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
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$gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate2UniqTran 10 bytes $_DEFAULT_ = 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C
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$gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate1UniqTranEnable 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
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$gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate1UniqTran 10 bytes $_DEFAULT_ = 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C
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$gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate0UniqTranEnable 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
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$gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate0UniqTran 10 bytes $_DEFAULT_ = 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C
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Skip 13 bytes
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$gPlatformFspPkgTokenSpaceGuid_PcieRpAspm 24 bytes $_DEFAULT_ = 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04
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$gPlatformFspPkgTokenSpaceGuid_PcieRpL1Substates 24 bytes $_DEFAULT_ = 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03
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$gPlatformFspPkgTokenSpaceGuid_PcieRpLtrEnable 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
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@ -3302,6 +3305,30 @@ Page "PCH 2"
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EditNum $gPlatformFspPkgTokenSpaceGuid_PchUsbLtrLowIdleTimeOverride, "xHCI Low Idle Time LTR override", HEX,
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Help "Value used for overriding LTR recommendation for xHCI Low Idle Time LTR setting"
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"Valid range: 0x00 ~ 0xFFFFFFFF"
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EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate3UniqTranEnable, "Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3", HEX,
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Help "Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3, Each value in array can be between 0-1. One byte for each port."
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"Valid range: 0x00 ~ 0x01010101010101010101"
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EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate3UniqTran, "USB 3.0 TX Output Unique Transition Bit Scale for rate 3", HEX,
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Help "USB 3.0 TX Output Unique Transition Bit Scale for rate 3, HSIO_TX_DWORD9[6:0], <b>Default = 4Ch</b>. One byte for each port."
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"Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF"
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EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate2UniqTranEnable, "Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2", HEX,
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Help "Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2, Each value in array can be between 0-1. One byte for each port."
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"Valid range: 0x00 ~ 0x01010101010101010101"
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EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate2UniqTran, "USB 3.0 TX Output Unique Transition Bit Scale for rate 2", HEX,
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Help "USB 3.0 TX Output Unique Transition Bit Scale for rate 2, HSIO_TX_DWORD9[14:8], <b>Default = 4Ch</b>. One byte for each port."
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"Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF"
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EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate1UniqTranEnable, "Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1", HEX,
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Help "Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1, Each value in array can be between 0-1. One byte for each port."
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"Valid range: 0x00 ~ 0x01010101010101010101"
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EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate1UniqTran, "USB 3.0 TX Output Unique Transition Bit Scale for rate 1", HEX,
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Help "USB 3.0 TX Output Unique Transition Bit Scale for rate 1, HSIO_TX_DWORD9[22:16], <b>Default = 4Ch</b>. One byte for each port."
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"Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF"
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EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate0UniqTranEnable, "Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0", HEX,
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Help "Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0, Each value in array can be between 0-1. One byte for each port."
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"Valid range: 0x00 ~ 0x01010101010101010101"
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EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate0UniqTran, "USB 3.0 TX Output Unique Transition Bit Scale for rate 0", HEX,
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Help "USB 3.0 TX Output Unique Transition Bit Scale for rate 0, HSIO_TX_DWORD9[30:24], <b>Default = 4Ch</b>. One byte for each port."
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"Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF"
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EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpAspm, "PCIE RP Aspm", HEX,
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Help "The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is PchPcieAspmAutoConfig."
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"Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
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@ -1506,9 +1506,57 @@ typedef struct {
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**/
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UINT32 PchUsbLtrLowIdleTimeOverride;
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/** Offset 0x056B
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/** Offset 0x056B - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3
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Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3, Each
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value in array can be between 0-1. One byte for each port.
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**/
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UINT8 UnusedUpdSpace15[93];
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UINT8 Usb3HsioTxRate3UniqTranEnable[10];
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/** Offset 0x0575 - USB 3.0 TX Output Unique Transition Bit Scale for rate 3
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USB 3.0 TX Output Unique Transition Bit Scale for rate 3, HSIO_TX_DWORD9[6:0], <b>Default
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= 4Ch</b>. One byte for each port.
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**/
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UINT8 Usb3HsioTxRate3UniqTran[10];
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/** Offset 0x057F - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2
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Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2, Each
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value in array can be between 0-1. One byte for each port.
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**/
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UINT8 Usb3HsioTxRate2UniqTranEnable[10];
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/** Offset 0x0589 - USB 3.0 TX Output Unique Transition Bit Scale for rate 2
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USB 3.0 TX Output Unique Transition Bit Scale for rate 2, HSIO_TX_DWORD9[14:8],
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<b>Default = 4Ch</b>. One byte for each port.
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**/
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UINT8 Usb3HsioTxRate2UniqTran[10];
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/** Offset 0x0593 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1
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Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1, Each
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value in array can be between 0-1. One byte for each port.
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**/
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UINT8 Usb3HsioTxRate1UniqTranEnable[10];
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/** Offset 0x059D - USB 3.0 TX Output Unique Transition Bit Scale for rate 1
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USB 3.0 TX Output Unique Transition Bit Scale for rate 1, HSIO_TX_DWORD9[22:16],
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<b>Default = 4Ch</b>. One byte for each port.
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**/
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UINT8 Usb3HsioTxRate1UniqTran[10];
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/** Offset 0x05A7 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0
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Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0, Each
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value in array can be between 0-1. One byte for each port.
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**/
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UINT8 Usb3HsioTxRate0UniqTranEnable[10];
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/** Offset 0x05B1 - USB 3.0 TX Output Unique Transition Bit Scale for rate 0
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USB 3.0 TX Output Unique Transition Bit Scale for rate 0, HSIO_TX_DWORD9[30:24],
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<b>Default = 4Ch</b>. One byte for each port.
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**/
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UINT8 Usb3HsioTxRate0UniqTran[10];
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/** Offset 0x05BB
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**/
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UINT8 UnusedUpdSpace15[13];
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/** Offset 0x05C8 - PCIE RP Aspm
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The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is
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