mirror of https://review.coreboot.org/fsp.git
IoT ADL-N PV (4031_00)
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/** @file
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Header file for FSP Information HOB.
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@copyright
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INTEL CONFIDENTIAL
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||||
Copyright 2017 - 2019 Intel Corporation.
|
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|
||||
The source code contained or described herein and all documents related to the
|
||||
source code ("Material") are owned by Intel Corporation or its suppliers or
|
||||
licensors. Title to the Material remains with Intel Corporation or its suppliers
|
||||
and licensors. The Material may contain trade secrets and proprietary and
|
||||
confidential information of Intel Corporation and its suppliers and licensors,
|
||||
and is protected by worldwide copyright and trade secret laws and treaty
|
||||
provisions. No part of the Material may be used, copied, reproduced, modified,
|
||||
published, uploaded, posted, transmitted, distributed, or disclosed in any way
|
||||
without Intel's prior express written permission.
|
||||
|
||||
No license under any patent, copyright, trade secret or other intellectual
|
||||
property right is granted to or conferred upon you by disclosure or delivery
|
||||
of the Materials, either expressly, by implication, inducement, estoppel or
|
||||
otherwise. Any license under such intellectual property rights must be
|
||||
express and approved by Intel in writing.
|
||||
|
||||
Unless otherwise agreed by Intel in writing, you may not remove or alter
|
||||
this notice or any other notice embedded in Materials by Intel or
|
||||
Intel's suppliers or licensors in any way.
|
||||
|
||||
This file contains an 'Intel Peripheral Driver' and is uniquely identified as
|
||||
"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
|
||||
the terms of your license agreement with Intel or your vendor. This file may
|
||||
be modified by the user, subject to additional terms of the license agreement.
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@par Specification Reference:
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**/
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#ifndef _FSP_INFO_HOB_H_
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#define _FSP_INFO_HOB_H_
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extern EFI_GUID gFspInfoGuid;
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#pragma pack (push, 1)
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typedef struct {
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UINT8 SiliconInitVersionMajor;
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UINT8 SiliconInitVersionMinor;
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UINT8 SiliconInitVersionRevision;
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UINT8 SiliconInitVersionBuild;
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UINT8 FspVersionRevision;
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UINT8 FspVersionBuild;
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UINT8 TimeStamp [12];
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UINT8 FspVersionMinor;
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} FSP_INFO_HOB;
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#pragma pack (pop)
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#endif // _FSP_INFO_HOB_H_
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/** @file
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|
||||
Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
* Redistributions in binary form must reproduce the above copyright notice, this
|
||||
list of conditions and the following disclaimer in the documentation and/or
|
||||
other materials provided with the distribution.
|
||||
* Neither the name of Intel Corporation nor the names of its contributors may
|
||||
be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
|
||||
THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
This file is automatically generated. Please do NOT modify !!!
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||||
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**/
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#ifndef __FSPUPD_H__
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#define __FSPUPD_H__
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#include <FspEas.h>
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#pragma pack(1)
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#define FSPT_UPD_SIGNATURE 0x545F4450554C4441 /* 'ADLUPD_T' */
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#define FSPM_UPD_SIGNATURE 0x4D5F4450554C4441 /* 'ADLUPD_M' */
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#define FSPS_UPD_SIGNATURE 0x535F4450554C4441 /* 'ADLUPD_S' */
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#pragma pack()
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#endif
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/** @file
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|
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Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
* Redistributions in binary form must reproduce the above copyright notice, this
|
||||
list of conditions and the following disclaimer in the documentation and/or
|
||||
other materials provided with the distribution.
|
||||
* Neither the name of Intel Corporation nor the names of its contributors may
|
||||
be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
|
||||
THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
This file is automatically generated. Please do NOT modify !!!
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||||
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||||
**/
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#ifndef __FSPTUPD_H__
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#define __FSPTUPD_H__
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#include <FspUpd.h>
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#pragma pack(1)
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/** Fsp T Core UPD
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**/
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typedef struct {
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/** Offset 0x0040
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**/
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UINT32 MicrocodeRegionBase;
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/** Offset 0x0044
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**/
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UINT32 MicrocodeRegionSize;
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/** Offset 0x0048
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**/
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UINT32 CodeRegionBase;
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/** Offset 0x004C
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**/
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UINT32 CodeRegionSize;
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/** Offset 0x0050
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**/
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UINT8 Reserved[16];
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} FSPT_CORE_UPD;
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/** Fsp T Configuration
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**/
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typedef struct {
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/** Offset 0x0060 - PcdSerialIoUartDebugEnable
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Enable SerialIo Uart debug library with/without initializing SerialIo Uart device in FSP.
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0:Disable, 1:Enable and Initialize, 2:Enable without Initializing
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**/
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UINT8 PcdSerialIoUartDebugEnable;
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/** Offset 0x0061 - PcdSerialIoUartNumber
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Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT
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Core interface, it cannot be used for debug purpose.
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0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2
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**/
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UINT8 PcdSerialIoUartNumber;
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/** Offset 0x0062 - PcdSerialIoUartMode - FSPT
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Select SerialIo Uart Controller mode
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0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom,
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4:SerialIoUartSkipInit
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**/
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UINT8 PcdSerialIoUartMode;
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/** Offset 0x0063 - PcdSerialIoUartPowerGating - FSPT
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Select SerialIo Uart Controller Powergating mode
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0:Disabled, 1:Enabled, 2:Auto
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**/
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UINT8 PcdSerialIoUartPowerGating;
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/** Offset 0x0064 - PcdSerialIoUartBaudRate - FSPT
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Set default BaudRate Supported from 0 - default to 6000000
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**/
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UINT32 PcdSerialIoUartBaudRate;
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/** Offset 0x0068 - Pci Express Base Address
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Base address to be programmed for Pci Express
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**/
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UINT64 PcdPciExpressBaseAddress;
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/** Offset 0x0070 - Pci Express Region Length
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Region Length to be programmed for Pci Express
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**/
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UINT32 PcdPciExpressRegionLength;
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/** Offset 0x0074 - PcdSerialIoUartParity - FSPT
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Set default Parity.
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0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity
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**/
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UINT8 PcdSerialIoUartParity;
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/** Offset 0x0075 - PcdSerialIoUartDataBits - FSPT
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Set default word length. 0: Default, 5,6,7,8
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**/
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UINT8 PcdSerialIoUartDataBits;
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/** Offset 0x0076 - PcdSerialIoUartStopBits - FSPT
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Set default stop bits.
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0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits
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**/
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UINT8 PcdSerialIoUartStopBits;
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/** Offset 0x0077 - PcdSerialIoUartAutoFlow - FSPT
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Enables UART hardware flow control, CTS and RTS lines.
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0: Disable, 1:Enable
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**/
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UINT8 PcdSerialIoUartAutoFlow;
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/** Offset 0x0078 - PcdSerialIoUartRxPinMux - FSPT
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Select RX pin muxing for SerialIo UART used for debug
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**/
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UINT32 PcdSerialIoUartRxPinMux;
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/** Offset 0x007C - PcdSerialIoUartTxPinMux - FSPT
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Select TX pin muxing for SerialIo UART used for debug
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**/
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UINT32 PcdSerialIoUartTxPinMux;
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/** Offset 0x0080 - PcdSerialIoUartRtsPinMux - FSPT
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Select SerialIo Uart used for debug Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS*
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for possible values.
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||||
**/
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||||
UINT32 PcdSerialIoUartRtsPinMux;
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||||
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||||
/** Offset 0x0084 - PcdSerialIoUartCtsPinMux - FSPT
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||||
Select SerialIo Uart used for debug Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS*
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||||
for possible values.
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||||
**/
|
||||
UINT32 PcdSerialIoUartCtsPinMux;
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||||
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||||
/** Offset 0x0088 - PcdSerialIoUartDebugMmioBase - FSPT
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||||
Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIoUartMode
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= SerialIoUartPci.
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**/
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||||
UINT32 PcdSerialIoUartDebugMmioBase;
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/** Offset 0x008C - PcdLpcUartDebugEnable
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Enable to initialize LPC Uart device in FSP.
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0:Disable, 1:Enable
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**/
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||||
UINT8 PcdLpcUartDebugEnable;
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||||
/** Offset 0x008D - Debug Interfaces
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Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub,
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BIT2 - Not used.
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**/
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UINT8 PcdDebugInterfaceFlags;
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/** Offset 0x008E - PcdSerialDebugLevel
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Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load,
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Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings,
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Info & Verbose.
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0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load
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Error Warnings and Info, 5:Load Error Warnings Info and Verbose
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**/
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UINT8 PcdSerialDebugLevel;
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/** Offset 0x008F - ISA Serial Base selection
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Select ISA Serial Base address. Default is 0x3F8.
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0:0x3F8, 1:0x2F8
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**/
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UINT8 PcdIsaSerialUartBase;
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/** Offset 0x0090 - PcdSerialIo2ndUartEnable
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Enable Additional SerialIo Uart device in FSP.
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0:Disable, 1:Enable and Initialize, 2:Enable without Initializing
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**/
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||||
UINT8 PcdSerialIo2ndUartEnable;
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||||
/** Offset 0x0091 - PcdSerialIo2ndUartNumber
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Select SerialIo Uart Controller Number
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||||
0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2
|
||||
**/
|
||||
UINT8 PcdSerialIo2ndUartNumber;
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||||
|
||||
/** Offset 0x0092 - PcdSerialIo2ndUartMode - FSPT
|
||||
Select SerialIo Uart Controller mode
|
||||
0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom,
|
||||
4:SerialIoUartSkipInit
|
||||
**/
|
||||
UINT8 PcdSerialIo2ndUartMode;
|
||||
|
||||
/** Offset 0x0093
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||||
**/
|
||||
UINT8 UnusedUpdSpace0;
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||||
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||||
/** Offset 0x0094 - PcdSerialIo2ndUartBaudRate - FSPT
|
||||
Set default BaudRate Supported from 0 - default to 6000000
|
||||
**/
|
||||
UINT32 PcdSerialIo2ndUartBaudRate;
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||||
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||||
/** Offset 0x0098 - PcdSerialIo2ndUartParity - FSPT
|
||||
Set default Parity.
|
||||
0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity
|
||||
**/
|
||||
UINT8 PcdSerialIo2ndUartParity;
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||||
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||||
/** Offset 0x0099 - PcdSerialIo2ndUartDataBits - FSPT
|
||||
Set default word length. 0: Default, 5,6,7,8
|
||||
**/
|
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UINT8 PcdSerialIo2ndUartDataBits;
|
||||
|
||||
/** Offset 0x009A - PcdSerialIo2ndUartStopBits - FSPT
|
||||
Set default stop bits.
|
||||
0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits
|
||||
**/
|
||||
UINT8 PcdSerialIo2ndUartStopBits;
|
||||
|
||||
/** Offset 0x009B - PcdSerialIo2ndUartAutoFlow - FSPT
|
||||
Enables UART hardware flow control, CTS and RTS lines.
|
||||
0: Disable, 1:Enable
|
||||
**/
|
||||
UINT8 PcdSerialIo2ndUartAutoFlow;
|
||||
|
||||
/** Offset 0x009C - PcdSerialIo2ndUartRxPinMux - FSPT
|
||||
Select RX pin muxing for SerialIo UART
|
||||
**/
|
||||
UINT32 PcdSerialIo2ndUartRxPinMux;
|
||||
|
||||
/** Offset 0x00A0 - PcdSerialIo2ndUartTxPinMux - FSPT
|
||||
Select TX pin muxing for SerialIo UART
|
||||
**/
|
||||
UINT32 PcdSerialIo2ndUartTxPinMux;
|
||||
|
||||
/** Offset 0x00A4 - PcdSerialIo2ndUartRtsPinMux - FSPT
|
||||
Select SerialIo Uart Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS*
|
||||
for possible values.
|
||||
**/
|
||||
UINT32 PcdSerialIo2ndUartRtsPinMux;
|
||||
|
||||
/** Offset 0x00A8 - PcdSerialIo2ndUartCtsPinMux - FSPT
|
||||
Select SerialIo Uart Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS*
|
||||
for possible values.
|
||||
**/
|
||||
UINT32 PcdSerialIo2ndUartCtsPinMux;
|
||||
|
||||
/** Offset 0x00AC - PcdSerialIo2ndUartMmioBase - FSPT
|
||||
Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIo2ndUartMode
|
||||
= SerialIoUartPci.
|
||||
**/
|
||||
UINT32 PcdSerialIo2ndUartMmioBase;
|
||||
|
||||
/** Offset 0x00B0
|
||||
**/
|
||||
UINT32 TopMemoryCacheSize;
|
||||
|
||||
/** Offset 0x00B4 - FspDebugHandler
|
||||
<b>Optional</b> pointer to the boot loader's implementation of FSP_DEBUG_HANDLER.
|
||||
**/
|
||||
UINT32 FspDebugHandler;
|
||||
|
||||
/** Offset 0x00B8 - Serial Io SPI Chip Select Polarity
|
||||
Sets polarity for each chip Select. Available options: 0:SerialIoSpiCsActiveLow,
|
||||
1:SerialIoSpiCsActiveHigh
|
||||
**/
|
||||
UINT8 PcdSerialIoSpiCsPolarity[2];
|
||||
|
||||
/** Offset 0x00BA - Serial Io SPI Chip Select Enable
|
||||
0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled
|
||||
**/
|
||||
UINT8 PcdSerialIoSpiCsEnable[2];
|
||||
|
||||
/** Offset 0x00BC - Serial Io SPI Device Mode
|
||||
When mode is set to Pci, controller is initalized in early stage. Available modes:
|
||||
0:SerialIoSpiDisabled, 1:SerialIoSpiPci.
|
||||
**/
|
||||
UINT8 PcdSerialIoSpiMode;
|
||||
|
||||
/** Offset 0x00BD - Serial Io SPI Default Chip Select Output
|
||||
Sets Default CS as Output. Available options: 0:CS0, 1:CS1
|
||||
**/
|
||||
UINT8 PcdSerialIoSpiDefaultCsOutput;
|
||||
|
||||
/** Offset 0x00BE - Serial Io SPI Default Chip Select Mode HW/SW
|
||||
Sets Default CS Mode Hardware or Software. Available options: 0:HW, 1:SW
|
||||
**/
|
||||
UINT8 PcdSerialIoSpiCsMode;
|
||||
|
||||
/** Offset 0x00BF - Serial Io SPI Default Chip Select State Low/High
|
||||
Sets Default CS State Low or High. Available options: 0:Low, 1:High
|
||||
**/
|
||||
UINT8 PcdSerialIoSpiCsState;
|
||||
|
||||
/** Offset 0x00C0 - Serial Io SPI Device Number
|
||||
Select which Serial Io SPI controller is initalized in early stage.
|
||||
**/
|
||||
UINT8 PcdSerialIoSpiNumber;
|
||||
|
||||
/** Offset 0x00C1
|
||||
**/
|
||||
UINT8 UnusedUpdSpace1[3];
|
||||
|
||||
/** Offset 0x00C4 - Serial Io SPI Device MMIO Base
|
||||
Assigns MMIO for Serial Io SPI controller usage in early stage.
|
||||
**/
|
||||
UINT32 PcdSerialIoSpiMmioBase;
|
||||
|
||||
/** Offset 0x00C8
|
||||
**/
|
||||
UINT8 ReservedFsptUpd1[16];
|
||||
} FSP_T_CONFIG;
|
||||
|
||||
/** Fsp T UPD Configuration
|
||||
**/
|
||||
typedef struct {
|
||||
|
||||
/** Offset 0x0000
|
||||
**/
|
||||
FSP_UPD_HEADER FspUpdHeader;
|
||||
|
||||
/** Offset 0x0020
|
||||
**/
|
||||
FSPT_ARCH_UPD FsptArchUpd;
|
||||
|
||||
/** Offset 0x0040
|
||||
**/
|
||||
FSPT_CORE_UPD FsptCoreUpd;
|
||||
|
||||
/** Offset 0x0060
|
||||
**/
|
||||
FSP_T_CONFIG FsptConfig;
|
||||
|
||||
/** Offset 0x00D8
|
||||
**/
|
||||
UINT8 UnusedUpdSpace2[6];
|
||||
|
||||
/** Offset 0x00DE
|
||||
**/
|
||||
UINT16 UpdTerminator;
|
||||
} FSPT_UPD;
|
||||
|
||||
#pragma pack()
|
||||
|
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#endif
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@ -0,0 +1,2 @@
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# AlderLakeFspBinPkg/IoT/AlderLakeN
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These FSP binaries are intended to be used with IoT SKUs of the 12th Generation Intel® Core™ PS-Series processors and chipsets formerly known as Alder Lake - N.
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@ -11,6 +11,7 @@ Client/AlderLakeS | HX-Series & desktop processors for client platforms
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IoT/AlderLakeP | U-Series, P-Series, & H-Series processors for IoT platforms
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IoT/AlderLakePS | PS-Series processors for IoT platforms
|
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IoT/AlderLakeS | Desktop processors for IoT platforms
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IoT/AlderLakeN | N-Series processors for IoT platforms
|
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## Differentiating Client and IoT
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||||
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Loading…
Reference in New Issue