Reorganize the FSP repo to have all FSPs in the master branch instead of in platform branches

This commit is contained in:
Nate DeSimone 2018-08-22 17:05:06 -07:00
parent c65f7ee6e8
commit 667eb3edc5
177 changed files with 211912 additions and 0 deletions

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/** @file
Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
This file is automatically generated. Please do NOT modify !!!
**/
#ifndef __FSPUPD_H__
#define __FSPUPD_H__
#include <FspEas.h>
#pragma pack(1)
#define FSPT_UPD_SIGNATURE 0x545F4450554C5041 /* 'APLUPD_T' */
#define FSPM_UPD_SIGNATURE 0x4D5F4450554C5041 /* 'APLUPD_M' */
#define FSPS_UPD_SIGNATURE 0x535F4450554C5041 /* 'APLUPD_S' */
#pragma pack()
#endif

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/** @file
Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
This file is automatically generated. Please do NOT modify !!!
**/
#ifndef __FSPMUPD_H__
#define __FSPMUPD_H__
#include <FspUpd.h>
#pragma pack(1)
#define MAX_CHANNELS_NUM 4
#define MAX_DIMMS_NUM 1
typedef struct {
UINT8 DimmId;
UINT32 SizeInMb;
UINT16 MfgId;
/** Module part number for DRR3 is 18 bytes
but DRR4 is 20 bytes as per JEDEC Spec, so
reserving 20 bytes **/
UINT8 ModulePartNum[20];
} DIMM_INFO;
typedef struct {
UINT8 ChannelId;
UINT8 DimmCount;
DIMM_INFO DimmInfo[MAX_DIMMS_NUM];
} CHANNEL_INFO;
typedef struct {
UINT8 Revision;
UINT8 DataWidth;
/** As defined in SMBIOS 3.0 spec
Section 7.18.2 and Table 75
**/
UINT16 MemoryType;
UINT16 MemoryFrequencyInMHz;
/** As defined in SMBIOS 3.0 spec
Section 7.17.3 and Table 72
**/
UINT8 ErrorCorrectionType;
UINT8 ChannelCount;
CHANNEL_INFO ChannelInfo[MAX_CHANNELS_NUM];
} FSP_SMBIOS_MEMORY_INFO;
/** Fsp M Configuration
**/
typedef struct {
/** Offset 0x0040 - Debug Serial Port Base address
Debug serial port base address. This option will be used only when the 'Serial Port
Debug Device' option is set to 'External Device'. 0x00000000(Default).
**/
UINT32 SerialDebugPortAddress;
/** Offset 0x0044 - Debug Serial Port Type
16550 compatible debug serial port resource type. NONE means no serial port support.
0x02:MMIO(Default).
0:NONE, 1:I/O, 2:MMIO
**/
UINT8 SerialDebugPortType;
/** Offset 0x0045 - Serial Port Debug Device
Select active serial port device for debug. For SOC UART devices,'Debug Serial Port
Base' options will be ignored. 0x02:SOC UART2(Default).
0:SOC UART0, 1:SOC UART1, 2:SOC UART2, 3:External Device
**/
UINT8 SerialDebugPortDevice;
/** Offset 0x0046 - Debug Serial Port Stride Size
Debug serial port register map stride size in bytes. 0x00:1, 0x02:4(Default).
0:1, 2:4
**/
UINT8 SerialDebugPortStrideSize;
/** Offset 0x0047 - Memory Fast Boot
Enable/Disable MRC fast boot support. 0x00:Disable, 0x01:Enable(Default).
$EN_DIS
**/
UINT8 MrcFastBoot;
/** Offset 0x0048 - Integrated Graphics Device
Enable : Enable Integrated Graphics Device (IGD) when selected as the Primary Video
Adaptor. Disable: Always disable IGD. 0x00:Disable, 0x01:Enable(Default).
$EN_DIS
**/
UINT8 Igd;
/** Offset 0x0049 - DVMT Pre-Allocated
Select DVMT 5.0 Pre-Allocated (Fixed) Graphics Memory size used by the Internal
Graphics Device. 0x02:64 MB(Default).
0x02:64 MB, 0x03:96 MB, 0x04:128 MB, 0x05:160 MB, 0x06:192 MB, 0x07:224 MB, 0x08:256
MB, 0x09:288 MB, 0x0A:320 MB, 0x0B:352 MB, 0x0C:384 MB, 0x0D:416 MB, 0x0E:448 MB,
0x0F:480 MB, 0x10:512 MB
**/
UINT8 IgdDvmt50PreAlloc;
/** Offset 0x004A - Aperture Size
Select the Aperture Size used by the Internal Graphics Device. 0x1:128 MB(Default),
0x2:256 MB, 0x3:512 MB.
0x1:128 MB, 0x2:256 MB, 0x3:512 MB
**/
UINT8 IgdApertureSize;
/** Offset 0x004B - GTT Size
Select the GTT Size used by the Internal Graphics Device. 0x1:2 MB, 0x2:4 MB, 0x3:8
MB(Default).
0x1:2 MB, 0x2:4 MB, 0x3:8 MB
**/
UINT8 GttSize;
/** Offset 0x004C - Primary Display
Select which of IGD/PCI Graphics device should be Primary Display. 0x0:AUTO(Default),
0x2:IGD, 0x3:PCI
0x0:AUTO, 0x2:IGD, 0x3:PCI
**/
UINT8 PrimaryVideoAdaptor;
/** Offset 0x004D - Package
NOTE: Specifies CA Mapping for all technologies. Supported CA Mappings: 0 - SODIMM(Default);
1 - BGA; 2 - BGA mirrored (LPDDR3 only); 3 - SODIMM/UDIMM with Rank 1 Mirrored
(DDR3L); Refer to the IAFW spec for specific details about each CA mapping.
0x0:SODIMM, 0x1:BGA, 0x2:BGA mirrored (LPDDR3 only), 0x3:SODIMM/UDIMM with Rank
1 Mirrored (DDR3L)
**/
UINT8 Package;
/** Offset 0x004E - Profile
Profile list. 0x19(Default).
0x1:WIO2_800_7_8_8, 0x2:WIO2_1066_9_10_10, 0x3:LPDDR3_1066_8_10_10, 0x4:LPDDR3_1333_10_12_12,
0x5:LPDDR3_1600_12_15_15, 0x6:LPDDR3_1866_14_17_17, 0x7:LPDDR3_2133_16_20_20, 0x8:LPDDR4_1066_10_10_10,
0x9:LPDDR4_1600_14_15_15, 0xA:LPDDR4_2133_20_20_20, 0xB:LPDDR4_2400_24_22_22, 0xC:LPDDR4_2666_24_24_24,
0xD:LPDDR4_2933_28_27_27, 0xE:LPDDR4_3200_28_29_29, 0xF:DDR3_1066_6_6_6, 0x10:DDR3_1066_7_7_7,
0x11:DDR3_1066_8_8_8, 0x12:DDR3_1333_7_7_7, 0x13:DDR3_1333_8_8_8, 0x14:DDR3_1333_9_9_9,
0x15:DDR3_1333_10_10_10, 0x16:DDR3_1600_8_8_8, 0x17:DDR3_1600_9_9_9, 0x18:DDR3_1600_10_10_10,
0x19:DDR3_1600_11_11_11, 0x1A:DDR3_1866_10_10_10, 0x1B:DDR3_1866_11_11_11, 0x1C:DDR3_1866_12_12_12,
0x1D:DDR3_1866_13_13_13, 0x1E:DDR3_2133_11_11_11, 0x1F:DDR3_2133_12_12_12, 0x20:DDR3_2133_13_13_13,
0x21:DDR3_2133_14_14_14, 0x22:DDR4_1333_10_10_10, 0x23:DDR4_1600_10_10_10, 0x24:DDR4_1600_11_11_11,
0x25:DDR4_1600_12_12_12, 0x26:DDR4_1866_12_12_12, 0x27:DDR4_1866_13_13_13, 0x28:DDR4_1866_14_14_14,
0x29:DDR4_2133_14_14_14, 0x2A:DDR4_2133_15_15_15, 0x2B:DDR4_2133_16_16_16, 0x2C:DDR4_2400_15_15_15,
0x2D:DDR4_2400_16_16_16, 0x2E:DDR4_2400_17_17_17, 0x2F:DDR4_2400_18_18_18
**/
UINT8 Profile;
/** Offset 0x004F - MemoryDown
Memory Down. 0x0(Default).
0x0:No, 0x1:Yes, 0x2:1MD+SODIMM (for DDR3L only) ACRD, 0x3:1x32 LPDDR4
**/
UINT8 MemoryDown;
/** Offset 0x0050 - DDR3LPageSize
NOTE: Only for memory down (soldered down memory with no SPD). 0x01:1KB(Default), 0x02:2KB.
0x1:1KB, 0x2:2KB
**/
UINT8 DDR3LPageSize;
/** Offset 0x0051 - DDR3LASR
NOTE: Only for memory down. This is specific to ddr3l and used for refresh adjustment
in Self Refresh, does not affect LP4. 0x00:Not Supported(Default), 0x01:Supported.
0x0:Not Supported, 0x1:Supported
**/
UINT8 DDR3LASR;
/** Offset 0x0052 - ScramblerSupport
Scrambler Support - Enable or disable the memory scrambler. Data scrambling is
provided as a means to increase signal integrity/reduce RFI generated by the DRAM
interface. This is achieved by randomizing seed that encodes/decodes memory data
so repeating a worse case pattern is hard to repeat. 00: Disable Scrambler Support,
01: Enable Scrambler Support
$EN_DIS
**/
UINT8 ScramblerSupport;
/** Offset 0x0053 - InterleavedMode
This field is ignored if one of the PnP channel configurations is used. If the memory
configuration is different, then the field is used directly to populate. 0x00:Disable(Default),
0x02:Enable.
0x0:Disable, 0x2:Enable
**/
UINT8 InterleavedMode;
/** Offset 0x0054 - ChannelHashMask
ChannelHashMask and SliceHashMask allow for the channel hashing algorithm to be
modified. These inputs are not used for configurations where an optimized ChannelHashMask
has been provided by the PnP validation teams. 0x00(Default).
**/
UINT16 ChannelHashMask;
/** Offset 0x0056 - SliceHashMask
ChannelHashMask and SliceHashMask allow for the channel hashing algorithm to be
modified. These inputs are not used for configurations where an optimized ChannelHashMask
has been provided by the PnP validation teams. 0x00(Default).
**/
UINT16 SliceHashMask;
/** Offset 0x0058 - ChannelsSlicesEnable
ChannelSlicesEnable field is not used at all on BXTP. The Channel Slice Configuration
is calculated internally based on the enabled channel configuration. 0x00:Disable(Default),
0x01:Enable.
$EN_DIS
**/
UINT8 ChannelsSlicesEnable;
/** Offset 0x0059 - MinRefRate2xEnable
Provided as a means to defend against Row-Hammer attacks. 0x00:Disable(Default),
0x01:Enable.
$EN_DIS
**/
UINT8 MinRefRate2xEnable;
/** Offset 0x005A - DualRankSupportEnable
Dual Rank Support Enable. 0x00:Disable, 0x01:Enable(Default).
$EN_DIS
**/
UINT8 DualRankSupportEnable;
/** Offset 0x005B - RmtMode
Rank Margin Tool Mode. 0x00(Default), 0x3(Enabled).
0x0:Disabled, 0x3:Enabled
**/
UINT8 RmtMode;
/** Offset 0x005C - MemorySizeLimit
Memory Size Limit: This value is used to restrict the total amount of memory and
the calculations based on it. Value is in MB. Example encodings are: 0x400 = 1GB,
0x800 = 2GB, 0x1000 = 4GB, 0x2000 8GB. 0x0000(Default)
**/
UINT16 MemorySizeLimit;
/** Offset 0x005E - LowMemoryMaxValue
Low Memory Max Value: This value is used to restrict the amount of memory below
4GB and the calculations based on it. Value is in MB.Example encodings are: 0x400
= 1GB, 0x800 = 2GB, 0x1000 = 4GB, 0x2000 8GB. 0x0000(Default).
**/
UINT16 LowMemoryMaxValue;
/** Offset 0x0060 - HighMemoryMaxValue
High Memory Max Value: This value is used to restrict the amount of memory above
4GB and the calculations based on it. Value is in MB. Example encodings are: 0x0400:1GB,
0x0800:2GB, 0x1000:4GB, 0x2000:8GB. 0x00(Default).
**/
UINT16 HighMemoryMaxValue;
/** Offset 0x0062 - DisableFastBoot
00:Disabled; Use saved training data (if valid) after first boot(Default), 01:Enabled;
Full re-train of memory on every boot.
$EN_DIS
**/
UINT8 DisableFastBoot;
/** Offset 0x0063 - DIMM0SPDAddress
DIMM0 SPD Address (NOTE: Only for DDR3L only. Please put 0 for MemoryDown. 0xA0(Default).
**/
UINT8 DIMM0SPDAddress;
/** Offset 0x0064 - DIMM1SPDAddress
DIMM1 SPD Address (NOTE: Only for DDR3L only. Please put 0 for MemoryDown. 0xA4(Default).
**/
UINT8 DIMM1SPDAddress;
/** Offset 0x0065 - Ch0_RankEnable
NOTE: Only for memory down. This is a bit mask which specifies what ranks are enabled.
NOTE: Only for memory down (soldered down memory with no SPD): BIT[0] Enable Rank
0: Must be set to 1 to enable use of this rank; BIT1[1] Enable Rank 1: Must be
set to 1 to enable use of this rank.
**/
UINT8 Ch0_RankEnable;
/** Offset 0x0066 - Ch0_DeviceWidth
NOTE: Only for memory down. Must specify the DRAM device width per DRAM channel
(not to be confused with the SoC Memory Channel width which is always x32 for LPDDR3\LPDDR4
and x64 for DDR3L). LPDDR4 devices typically have two channels per die and a x16
device width: 00 - x8; 01 - x16; 10 - x32; 11 - x64
0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64
**/
UINT8 Ch0_DeviceWidth;
/** Offset 0x0067 - Ch0_DramDensity
NOTE: Only for memory down. For LPDDR3 and LPDDR4: Must specify the DRAM device
density per rank (per Chip Select). The simplest way of identifying the density
per rank is to divide the total SoC memory channel density by the number of ranks.
For DDR3L: Must specify the DRAM device density per DRAM device. For example, an
8GB 2Rx8 configuration will utilize sixteen 4Gb density DRAMS. In this configuration,
a 4Gb density setting would be selected in the MRC: 000 - 4Gb; 001 - 6Gb; 010 -
8Gb; 011 - 12Gb; 100 - 16Gb; 101 - 2Gb; 110-111 - Reserved
0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb
**/
UINT8 Ch0_DramDensity;
/** Offset 0x0068 - Ch0_Option
BIT[0] Rank Select Interleaving Enable. See Address Mapping section for full description:
0 - Rank Select Interleaving disabled; 1 - Rank Select Interleaving enabled. BIT[1]
Bank Address Hashing Enable. See Address Mapping section for full description:
0 - Bank Address Hashing disabled; 1 - Bank Address Hashing enabled. BIT[2] CH1
CLK Disable. Disables the CH1 CLK PHY Signal when set to 1. This is used on board
designs where the CH1 CLK is not routed and left floating or stubbed out: 0 - CH1
CLK is enabled; 1 - CH1 CLK is disabled. BIT[3] Reserved; BIT[5:4] This register
specifies the address mapping to be used: 00 - 1KB (A); 01 - 2KB (B)
**/
UINT8 Ch0_Option;
/** Offset 0x0069 - Ch0_OdtConfig
[0] RX ODT - DDR3L & LPDDR3 only: Change the READ ODT strength , for SOC termination
during a READ transaction, ON DQ BITs. STRONG ==> 60 OHMS roughly, WEAK ==> 120
OHMS or so roughly. Purpose: Save power on these technologies which burn power
directly proportional to ODT strength, because ODT looks like a PU and PD (e.g.
a resistor divider, which always burns power when ODT is ON). 0 - WEAK_ODT_CONFIG,
1 - STRONG_ODT_CONFIG. LPDDR4: X - Don't Care. [1] CA ODT - LPDDR4 Only: The
customer needs to choose this based on their actual board strapping (how they tie
the DRAM's ODT PINs). Effect: LPDDR4 MR11 will be set based on this setting. CAODT_A_B_HIGH_LOW
==> MR11 = 0x34, which is CA ODT = 80 ohms. CAODT_A_B_HIGH_HIGH ==> MR11 = 0x24,
which is CA ODT = 120 ohms (results in 60 ohm final effective impedance on CA/CLK/CS
signals). Purpose: To improve signal integrity and provide a much more optimized
CA VREF value during training. Not to save power. 0 - ODT_AB_HIGH_LOW (default),
1 - ODT_AB_HIGH_HIGH. DDR3L & LPDDR3: X - Don't Care. [4] TX ODT. DDR3L only:
0 = RZQ/4 (60 Ohms) = MRC_SMIP_DDR3L_TX_ODT_RTT_WR_60_OHMS, 1 = RZQ/2 (120
Ohms) = MRC_SMIP_DDR3L_TX_ODT_RTT_WR_120_OHMS. LPDDR3 & LPDDR4: X = Don't Care
**/
UINT8 Ch0_OdtConfig;
/** Offset 0x006A - Ch0_TristateClk1
Not used
**/
UINT8 Ch0_TristateClk1;
/** Offset 0x006B - Ch0_Mode2N
DDR3L Only: Configures the DDR3L command timing mode. 2N Mode is a stretched command
mode that provides more setup and hold time for DRAM commands on the DRAM command
bus. This is useful for platforms with unusual CMD bus routing or marginal signal
integrity: 0 - Auto (1N or 2N mode is automatically selected during Command and
Control training), 1 - Force 2N Mode
0x0:Auto, 0x1:Force 2N CMD Timing Mode
**/
UINT8 Ch0_Mode2N;
/** Offset 0x006C - Ch0_OdtLevels
Parameter used to determine if ODT will be held high or low: 0 - ODT Connected to
SoC, 1 - ODT held high
**/
UINT8 Ch0_OdtLevels;
/** Offset 0x006D - Ch1_RankEnable
NOTE: Only for memory down. This is a bit mask which specifies what ranks are enabled.
NOTE: Only for memory down (soldered down memory with no SPD): BIT[0] Enable Rank
0: Must be set to 1 to enable use of this rank; BIT1[1] Enable Rank 1: Must be
set to 1 to enable use of this rank.
**/
UINT8 Ch1_RankEnable;
/** Offset 0x006E - Ch1_DeviceWidth
NOTE: Only for memory down. Must specify the DRAM device width per DRAM channel
(not to be confused with the SoC Memory Channel width which is always x32 for LPDDR3\LPDDR4
and x64 for DDR3L). LPDDR4 devices typically have two channels per die and a x16
device width: 00 - x8; 01 - x16; 10 - x32; 11 - x64
0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64
**/
UINT8 Ch1_DeviceWidth;
/** Offset 0x006F - Ch1_DramDensity
NOTE: Only for memory down. For LPDDR3 and LPDDR4: Must specify the DRAM device
density per rank (per Chip Select). The simplest way of identifying the density
per rank is to divide the total SoC memory channel density by the number of ranks.
For DDR3L: Must specify the DRAM device density per DRAM device. For example, an
8GB 2Rx8 configuration will utilize sixteen 4Gb density DRAMS. In this configuration,
a 4Gb density setting would be selected in the MRC: 000 - 4Gb; 001 - 6Gb; 010 -
8Gb; 011 - 12Gb; 100 - 16Gb; 101 - 2Gb; 110-111 - Reserved
0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb
**/
UINT8 Ch1_DramDensity;
/** Offset 0x0070 - Ch1_Option
BIT[0] Rank Select Interleaving Enable. See Address Mapping section for full description:
0 - Rank Select Interleaving disabled; 1 - Rank Select Interleaving enabled. BIT[1]
Bank Address Hashing Enable. See Address Mapping section for full description:
0 - Bank Address Hashing disabled; 1 - Bank Address Hashing enabled. BIT[2] CH1
CLK Disable. Disables the CH1 CLK PHY Signal when set to 1. This is used on board
designs where the CH1 CLK is not routed and left floating or stubbed out: 0 - CH1
CLK is enabled; 1 - CH1 CLK is disabled. BIT[3] Reserved; BIT[5:4] This register
specifies the address mapping to be used: 00 - 1KB (A); 01 - 2KB (B)
**/
UINT8 Ch1_Option;
/** Offset 0x0071 - Ch1_OdtConfig
[0] RX ODT - DDR3L & LPDDR3 only: Change the READ ODT strength , for SOC termination
during a READ transaction, ON DQ BITs. STRONG ==> 60 OHMS roughly, WEAK ==> 120
OHMS or so roughly. Purpose: Save power on these technologies which burn power
directly proportional to ODT strength, because ODT looks like a PU and PD (e.g.
a resistor divider, which always burns power when ODT is ON). 0 - WEAK_ODT_CONFIG,
1 - STRONG_ODT_CONFIG. LPDDR4: X - Don't Care. [1] CA ODT - LPDDR4 Only: The
customer needs to choose this based on their actual board strapping (how they tie
the DRAM's ODT PINs). Effect: LPDDR4 MR11 will be set based on this setting. CAODT_A_B_HIGH_LOW
==> MR11 = 0x34, which is CA ODT = 80 ohms. CAODT_A_B_HIGH_HIGH ==> MR11 = 0x24,
which is CA ODT = 120 ohms (results in 60 ohm final effective impedance on CA/CLK/CS
signals). Purpose: To improve signal integrity and provide a much more optimized
CA VREF value during training. Not to save power. 0 - ODT_AB_HIGH_LOW (default),
1 - ODT_AB_HIGH_HIGH. DDR3L & LPDDR3: X - Don't Care. [4] TX ODT. DDR3L only:
0 = RZQ/4 (60 Ohms) = MRC_SMIP_DDR3L_TX_ODT_RTT_WR_60_OHMS, 1 = RZQ/2 (120
Ohms) = MRC_SMIP_DDR3L_TX_ODT_RTT_WR_120_OHMS. LPDDR3 & LPDDR4: X = Don't Care
**/
UINT8 Ch1_OdtConfig;
/** Offset 0x0072 - Ch1_TristateClk1
Not used
**/
UINT8 Ch1_TristateClk1;
/** Offset 0x0073 - Ch1_Mode2N
DDR3L Only: Configures the DDR3L command timing mode. 2N Mode is a stretched command
mode that provides more setup and hold time for DRAM commands on the DRAM command
bus. This is useful for platforms with unusual CMD bus routing or marginal signal
integrity: 0 - Auto (1N or 2N mode is automatically selected during Command and
Control training), 1 - Force 2N Mode
0x0:Auto, 0x1:Force 2N CMD Timing Mode
**/
UINT8 Ch1_Mode2N;
/** Offset 0x0074 - Ch1_OdtLevels
DDR3L Only: Parameter used to determine if ODT will be held high or low: 0 - ODT_AB_HIGH_LOW
(default), 1 - ODT_AB_HIGH_HIGH
**/
UINT8 Ch1_OdtLevels;
/** Offset 0x0075 - Ch2_RankEnable
NOTE: Only for memory down. This is a bit mask which specifies what ranks are enabled.
NOTE: Only for memory down (soldered down memory with no SPD): BIT[0] Enable Rank
0: Must be set to 1 to enable use of this rank; BIT1[1] Enable Rank 1: Must be
set to 1 to enable use of this rank.
**/
UINT8 Ch2_RankEnable;
/** Offset 0x0076 - Ch2_DeviceWidth
NOTE: Only for memory down. Must specify the DRAM device width per DRAM channel
(not to be confused with the SoC Memory Channel width which is always x32 for LPDDR3\LPDDR4
and x64 for DDR3L). LPDDR4 devices typically have two channels per die and a x16
device width: 00 - x8; 01 - x16; 10 - x32; 11 - x64
0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64
**/
UINT8 Ch2_DeviceWidth;
/** Offset 0x0077 - Ch2_DramDensity
NOTE: Only for memory down. For LPDDR3 and LPDDR4: Must specify the DRAM device
density per rank (per Chip Select). The simplest way of identifying the density
per rank is to divide the total SoC memory channel density by the number of ranks.
For DDR3L: Must specify the DRAM device density per DRAM device. For example, an
8GB 2Rx8 configuration will utilize sixteen 4Gb density DRAMS. In this configuration,
a 4Gb density setting would be selected in the MRC: 000 - 4Gb; 001 - 6Gb; 010 -
8Gb; 011 - 12Gb; 100 - 16Gb; 101 - 2Gb; 110-111 - Reserved
0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb
**/
UINT8 Ch2_DramDensity;
/** Offset 0x0078 - Ch2_Option
BIT[0] Rank Select Interleaving Enable. See Address Mapping section for full description:
0 - Rank Select Interleaving disabled; 1 - Rank Select Interleaving enabled. BIT[1]
Bank Address Hashing Enable. See Address Mapping section for full description:
0 - Bank Address Hashing disabled; 1 - Bank Address Hashing enabled. BIT[2] CH1
CLK Disable. Disables the CH1 CLK PHY Signal when set to 1. This is used on board
designs where the CH1 CLK is not routed and left floating or stubbed out: 0 - CH1
CLK is enabled; 1 - CH1 CLK is disabled. BIT[3] Reserved; BIT[5:4] This register
specifies the address mapping to be used: 00 - 1KB (A); 01 - 2KB (B)
**/
UINT8 Ch2_Option;
/** Offset 0x0079 - Ch2_OdtConfig
[0] RX ODT - DDR3L & LPDDR3 only: Change the READ ODT strength , for SOC termination
during a READ transaction, ON DQ BITs. STRONG ==> 60 OHMS roughly, WEAK ==> 120
OHMS or so roughly. Purpose: Save power on these technologies which burn power
directly proportional to ODT strength, because ODT looks like a PU and PD (e.g.
a resistor divider, which always burns power when ODT is ON). 0 - WEAK_ODT_CONFIG,
1 - STRONG_ODT_CONFIG. LPDDR4: X - Don't Care. [1] CA ODT - LPDDR4 Only: The
customer needs to choose this based on their actual board strapping (how they tie
the DRAM's ODT PINs). Effect: LPDDR4 MR11 will be set based on this setting. CAODT_A_B_HIGH_LOW
==> MR11 = 0x34, which is CA ODT = 80 ohms. CAODT_A_B_HIGH_HIGH ==> MR11 = 0x24,
which is CA ODT = 120 ohms (results in 60 ohm final effective impedance on CA/CLK/CS
signals). Purpose: To improve signal integrity and provide a much more optimized
CA VREF value during training. Not to save power. 0 - ODT_AB_HIGH_LOW (default),
1 - ODT_AB_HIGH_HIGH. DDR3L & LPDDR3: X - Don't Care. [4] TX ODT. DDR3L only:
0 = RZQ/4 (60 Ohms) = MRC_SMIP_DDR3L_TX_ODT_RTT_WR_60_OHMS, 1 = RZQ/2 (120
Ohms) = MRC_SMIP_DDR3L_TX_ODT_RTT_WR_120_OHMS. LPDDR3 & LPDDR4: X = Don't Care
**/
UINT8 Ch2_OdtConfig;
/** Offset 0x007A - Ch2_TristateClk1
Not used
**/
UINT8 Ch2_TristateClk1;
/** Offset 0x007B - Ch2_Mode2N
DDR3L Only: Configures the DDR3L command timing mode. 2N Mode is a stretched command
mode that provides more setup and hold time for DRAM commands on the DRAM command
bus. This is useful for platforms with unusual CMD bus routing or marginal signal
integrity: 0 - Auto (1N or 2N mode is automatically selected during Command and
Control training), 1 - Force 2N Mode
0x0:Auto, 0x1:Force 2N CMD Timing Mode
**/
UINT8 Ch2_Mode2N;
/** Offset 0x007C - Ch2_OdtLevels
DDR3L Only: Parameter used to determine if ODT will be held high or low: 0 - ODT_AB_HIGH_LOW
(default), 1 - ODT_AB_HIGH_HIGH
**/
UINT8 Ch2_OdtLevels;
/** Offset 0x007D - Ch3_RankEnable
NOTE: Only for memory down. This is a bit mask which specifies what ranks are enabled.
NOTE: Only for memory down (soldered down memory with no SPD): BIT[0] Enable Rank
0: Must be set to 1 to enable use of this rank; BIT1[1] Enable Rank 1: Must be
set to 1 to enable use of this rank.
**/
UINT8 Ch3_RankEnable;
/** Offset 0x007E - Ch3_DeviceWidth
NOTE: Only for memory down. Must specify the DRAM device width per DRAM channel
(not to be confused with the SoC Memory Channel width which is always x32 for LPDDR3\LPDDR4
and x64 for DDR3L). LPDDR4 devices typically have two channels per die and a x16
device width: 00 - x8; 01 - x16; 10 - x32; 11 - x64
0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64
**/
UINT8 Ch3_DeviceWidth;
/** Offset 0x007F - Ch3_DramDensity
NOTE: Only for memory down. For LPDDR3 and LPDDR4: Must specify the DRAM device
density per rank (per Chip Select). The simplest way of identifying the density
per rank is to divide the total SoC memory channel density by the number of ranks.
For DDR3L: Must specify the DRAM device density per DRAM device. For example, an
8GB 2Rx8 configuration will utilize sixteen 4Gb density DRAMS. In this configuration,
a 4Gb density setting would be selected in the MRC: 000 - 4Gb; 001 - 6Gb; 010 -
8Gb; 011 - 12Gb; 100 - 16Gb; 101 - 2Gb; 110-111 - Reserved
0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb
**/
UINT8 Ch3_DramDensity;
/** Offset 0x0080 - Ch3_Option
BIT[0] Rank Select Interleaving Enable. See Address Mapping section for full description:
0 - Rank Select Interleaving disabled; 1 - Rank Select Interleaving enabled. BIT[1]
Bank Address Hashing Enable. See Address Mapping section for full description:
0 - Bank Address Hashing disabled; 1 - Bank Address Hashing enabled. BIT[2] CH1
CLK Disable. Disables the CH1 CLK PHY Signal when set to 1. This is used on board
designs where the CH1 CLK is not routed and left floating or stubbed out: 0 - CH1
CLK is enabled; 1 - CH1 CLK is disabled. BIT[3] Reserved; BIT[5:4] This register
specifies the address mapping to be used: 00 - 1KB (A); 01 - 2KB (B)
**/
UINT8 Ch3_Option;
/** Offset 0x0081 - Ch3_OdtConfig
[0] RX ODT - DDR3L & LPDDR3 only: Change the READ ODT strength , for SOC termination
during a READ transaction, ON DQ BITs. STRONG ==> 60 OHMS roughly, WEAK ==> 120
OHMS or so roughly. Purpose: Save power on these technologies which burn power
directly proportional to ODT strength, because ODT looks like a PU and PD (e.g.
a resistor divider, which always burns power when ODT is ON). 0 - WEAK_ODT_CONFIG,
1 - STRONG_ODT_CONFIG. LPDDR4: X - Don't Care. [1] CA ODT - LPDDR4 Only: The
customer needs to choose this based on their actual board strapping (how they tie
the DRAM's ODT PINs). Effect: LPDDR4 MR11 will be set based on this setting. CAODT_A_B_HIGH_LOW
==> MR11 = 0x34, which is CA ODT = 80 ohms. CAODT_A_B_HIGH_HIGH ==> MR11 = 0x24,
which is CA ODT = 120 ohms (results in 60 ohm final effective impedance on CA/CLK/CS
signals). Purpose: To improve signal integrity and provide a much more optimized
CA VREF value during training. Not to save power. 0 - ODT_AB_HIGH_LOW (default),
1 - ODT_AB_HIGH_HIGH. DDR3L & LPDDR3: X - Don't Care. [4] TX ODT. DDR3L only:
0 = RZQ/4 (60 Ohms) = MRC_SMIP_DDR3L_TX_ODT_RTT_WR_60_OHMS, 1 = RZQ/2 (120
Ohms) = MRC_SMIP_DDR3L_TX_ODT_RTT_WR_120_OHMS. LPDDR3 & LPDDR4: X = Don't Care
**/
UINT8 Ch3_OdtConfig;
/** Offset 0x0082 - Ch3_TristateClk1
Not used
**/
UINT8 Ch3_TristateClk1;
/** Offset 0x0083 - Ch3_Mode2N
DDR3L Only: Configures the DDR3L command timing mode. 2N Mode is a stretched command
mode that provides more setup and hold time for DRAM commands on the DRAM command
bus. This is useful for platforms with unusual CMD bus routing or marginal signal
integrity: 0 - Auto (1N or 2N mode is automatically selected during Command and
Control training), 1 - Force 2N Mode
0x0:Auto, 0x1:Force 2N CMD Timing Mode
**/
UINT8 Ch3_Mode2N;
/** Offset 0x0084 - Ch3_OdtLevels
DDR3L Only: Parameter used to determine if ODT will be held high or low: 0 - ODT_AB_HIGH_LOW
(default), 1 - ODT_AB_HIGH_HIGH
**/
UINT8 Ch3_OdtLevels;
/** Offset 0x0085 - RmtCheckRun
Parameter used to determine whether to run the margin check. Bit 0 is used for MINIMUM
MARGIN CHECK and bit 1 is used for DEGRADE MARGIN CHECK
**/
UINT8 RmtCheckRun;
/** Offset 0x0086 - RmtMarginCheckScaleHighThreshold
Percentage used to determine the margin tolerances over the failing margin.
**/
UINT16 RmtMarginCheckScaleHighThreshold;
/** Offset 0x0088 - Ch0_Bit_swizzling
Channel 0 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32. Frequently
asked questions: Q: The DQS (strobes) need to go with the corresponding byte lanes
on the DDR module. Are the DQS being swapped around as well? Ans: Yes, DQ strobes
need to follow the DQ byte lane they correspond too. So for example if you have
DQ[7:0] swapped with DQ[15:8], DQS0 pair also need to be swapped with DQS1 pair.
Also, the spreadsheet used for Amenia is essentially a swizzle value lookup that
specifies what DRAM DQ bit a particular SoC DQ bit is connected to. Some confusion
can arrise from the fact that the indexes to the array do not necessarily map 1:1
to an SoC DQ pin. For example, the CH0 array at index 0 maps to SoC DQB8. The value
of 9 at index 0 tells us that SoC DQB8 is connected to DRAM DQA9. Q: The PDG indicates
a 2 physical channels need to be stuffed and operated together. Are the CHx_A and
CHx_B physical channels operated in tandem or completely separate? If separate,
why requirement of pairing them? Ans: We have 2 PHY instances on the SoC each supporting
up to 2 x32 LP4 channels. If you have 4 channels both PHYs are active, but if you
have 2 channels in order to power gate one PHY, those two channel populated must
be on one PHY instance. So yes all channels are independent of each other, but
there are some restrictions on how they need to be populated. Q: How is it that
an LPDDR4 device is identified as having a x16 width when all 32-bits are used
at the same time with a single chip select? That's effectively a x32 device. Ans:LPDDR4
DRAM devices are x16. Each die has 2 x16 devices on them. To make a x32 channel
the CS of the two devices in the same die are connected together to make a single
rank of one x32 channel (SDP). The second die in the DDP package makes the second rank.
**/
UINT8 Ch0_Bit_swizzling[32];
/** Offset 0x00A8 - Ch1_Bit_swizzling
Channel 1 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32.
**/
UINT8 Ch1_Bit_swizzling[32];
/** Offset 0x00C8 - Ch2_Bit_swizzling
Channel 2 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32.
**/
UINT8 Ch2_Bit_swizzling[32];
/** Offset 0x00E8 - Ch3_Bit_swizzling
Channel 3 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32.
**/
UINT8 Ch3_Bit_swizzling[32];
/** Offset 0x0108 - MsgLevelMask
32 bits used to mask out debug messages. Masking out bit 0 mask all other messages.
**/
UINT32 MsgLevelMask;
/** Offset 0x010C
**/
UINT8 UnusedUpdSpace0[4];
/** Offset 0x0110 - PreMem GPIO Pin Number for each table
Number of Pins in each PreMem GPIO Table. 0(Default).
**/
UINT8 PreMemGpioTablePinNum[4];
/** Offset 0x0114 - PreMem GPIO Table Pointer
Pointer to Array of pointers to PreMem GPIO Table. 0x00000000(Default).
**/
UINT32 PreMemGpioTablePtr;
/** Offset 0x0118 - PreMem GPIO Table Entry Number. Currently maximum entry number is 4
Number of Entries in PreMem GPIO Table. 0(Default).
**/
UINT8 PreMemGpioTableEntryNum;
/** Offset 0x0119 - Enhance the port 8xh decoding
Enable/Disable Enhance the port 8xh decoding. 0:Disable, 1:Enable(Default).
$EN_DIS
**/
UINT8 EnhancePort8xhDecoding;
/** Offset 0x011A - SPD Data Write
Enable/Disable SPD data write on the SMBUS. 0x00:Disable(Default), 0x01:Enable.
$EN_DIS
**/
UINT8 SpdWriteEnable;
/** Offset 0x011B - MRC Training Data Saving
Enable/Disable MRC training data saving in FSP. 0x00:Disable(Default), 0x01:Enable.
$EN_DIS
**/
UINT8 MrcDataSaving;
/** Offset 0x011C - OEM File Loading Address
Determine the memory base address to load a specified file from CSE file system
after memory is available.
**/
UINT32 OemLoadingBase;
/** Offset 0x0120 - OEM File Name to Load
Specify a file name to load from CSE file system after memory is available. Empty
indicates no file needs to be loaded.
**/
UINT8 OemFileName[16];
/** Offset 0x0130
**/
VOID* MrcBootDataPtr;
/** Offset 0x0134 - eMMC Trace Length
Select eMMC trace length to load OEM file from when loading OEM file name is specified.
0x0:Long(Default), 0x1:Short.
0x0:Long, 0x1:Short
**/
UINT8 eMMCTraceLen;
/** Offset 0x0135 - Skip CSE RBP to support zero sized IBB
Enable/Disable skip CSE RBP for bootloader which loads IBB without assistance of
CSE. 0x00:Disable(Default), 0x01:Enable.
$EN_DIS
**/
UINT8 SkipCseRbp;
/** Offset 0x0136 - Npk Enable
Enable/Disable Npk. 0:Disable, 1:Enable, 2:Debugger, 3:Auto(Default).
0:Disable, 1:Enable, 2:Debugger, 3:Auto
**/
UINT8 NpkEn;
/** Offset 0x0137 - FW Trace Enable
Enable/Disable FW Trace. 0:Disable, 1:Enable(Default).
$EN_DIS
**/
UINT8 FwTraceEn;
/** Offset 0x0138 - FW Trace Destination
FW Trace Destination. 1-NPK_TRACE_TO_MEMORY, 2-NPK_TRACE_TO_DCI, 3-NPK_TRACE_TO_BSSB,
4-NPK_TRACE_TO_PTI(Default).
**/
UINT8 FwTraceDestination;
/** Offset 0x0139 - NPK Recovery Dump
Enable/Disable NPK Recovery Dump. 0:Disable(Default), 1:Enable.
$EN_DIS
**/
UINT8 RecoverDump;
/** Offset 0x013A - Memory Region 0 Buffer WrapAround
Memory Region 0 Buffer WrapAround. 0-n0-warp, 1-warp(Default).
**/
UINT8 Msc0Wrap;
/** Offset 0x013B - Memory Region 1 Buffer WrapAround
Memory Region 1 Buffer WrapAround. 0-n0-warp, 1-warp(Default).
**/
UINT8 Msc1Wrap;
/** Offset 0x013C - Memory Region 0 Buffer Size
Memory Region 0 Buffer Size. 0-0MB(Default), 1-1MB, 2-8MB, 3-64MB, 4-128MB, 5-256MB,
6-512MB, 7-1GB.
**/
UINT32 Msc0Size;
/** Offset 0x0140 - Memory Region 1 Buffer Size
Memory Region 1 Buffer Size, 0-0MB(Default), 1-1MB, 2-8MB, 3-64MB, 4-128MB, 5-256MB,
6-512MB, 7-1GB.
**/
UINT32 Msc1Size;
/** Offset 0x0144 - PTI Mode
PTI Mode. 0-0ff, 1-x4(Default), 2-x8, 3-x12, 4-x16.
**/
UINT8 PtiMode;
/** Offset 0x0145 - PTI Training
PTI Training. 0-off(Default), 1-6=1-6.
**/
UINT8 PtiTraining;
/** Offset 0x0146 - PTI Speed
PTI Speed. 0-full, 1-half, 2-quarter(Default).
**/
UINT8 PtiSpeed;
/** Offset 0x0147 - Punit Message Level
Punit Message Output Verbosity Level. 0, 1(Default), 2-4=2-4.
**/
UINT8 PunitMlvl;
/** Offset 0x0148 - PMC Message Level
PMC Message Output Verbosity Level. 0, 1(Default), 2-4=2-4.
**/
UINT8 PmcMlvl;
/** Offset 0x0149 - SW Trace Enable
Enable/Disable SW Trace. 0:Disable(Default), 1:Enable.
$EN_DIS
**/
UINT8 SwTraceEn;
/** Offset 0x014A - Periodic Retraining Disable
Periodic Retraining Disable - This option allows customers to disable LPDDR4 Periodic
Retraining for debug purposes. Periodic Retraining should be enabled in production.
Periodic retraining allows the platform to operate reliably over a larger voltage
and temperature range. This field has no effect for DDR3L and LPDDR3 memory type
configurations. 0x00: Enable Periodic Retraining (default); 0x01: Disable Periodic
Retraining (debug configuration only)
0x0:Enabled, 0x1:Disabled
**/
UINT8 PeriodicRetrainingDisable;
/** Offset 0x014B - Enable Reset System
Enable FSP to trigger reset instead of returning reset request. 0x00: Return the
Return Status from FSP if a reset is required. (default); 0x01: Perform Reset inside
FSP instead of returning from the API.
0x0:Disabled, 0x1:Eabled
**/
UINT8 EnableResetSystem;
/** Offset 0x014C - Enable HECI2 in S3 resume path
Enable HECI2 in S3 resume path. 0x00: Skip HECI2 initialization in S3 resume. ;
0x01: Enable HECI2 in S3 resume path.(Default)
0x0:Disabled, 0x1:Eabled
**/
UINT8 EnableS3Heci2;
/** Offset 0x014D
**/
UINT8 UnusedUpdSpace1[3];
/** Offset 0x0150
**/
VOID* VariableNvsBufferPtr;
/** Offset 0x0154 - PCIE SLOT Power Enable Assert Time - PFET.
ACPI Timer Ticker to measure when PCIE Slot Power is enabled through PFET. FSP will
wait for 100ms for the power to be stable, before de-asserting PERST bin. Customer
who designed the board PCIE slot Power automatically enabled, can pass value of
zero here.
**/
UINT64 StartTimerTickerOfPfetAssert;
/** Offset 0x015C - Real Time Enabling
Real-Time Feature Configuration Bits settings. 0x0:Disabled (default), 0x1:Enabled
$EN_DIS
**/
UINT8 RtEn;
/** Offset 0x015D
**/
UINT8 ReservedFspmUpd[3];
} FSP_M_CONFIG;
/** Fsp M UPD Configuration
**/
typedef struct {
/** Offset 0x0000
**/
FSP_UPD_HEADER FspUpdHeader;
/** Offset 0x0020
**/
FSPM_ARCH_UPD FspmArchUpd;
/** Offset 0x0040
**/
FSP_M_CONFIG FspmConfig;
/** Offset 0x0160
**/
UINT8 UnusedUpdSpace2[158];
/** Offset 0x01FE
**/
UINT16 UpdTerminator;
} FSPM_UPD;
#pragma pack()
#endif

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/** @file
Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
This file is automatically generated. Please do NOT modify !!!
**/
#ifndef __FSPTUPD_H__
#define __FSPTUPD_H__
#include <FspUpd.h>
#pragma pack(1)
/** Fsp T Common UPD
**/
typedef struct {
/** Offset 0x0020
**/
UINT8 Revision;
/** Offset 0x0021
**/
UINT8 Reserved[3];
/** Offset 0x0024
**/
UINT32 MicrocodeRegionBase;
/** Offset 0x0028
**/
UINT32 MicrocodeRegionLength;
/** Offset 0x002C
**/
UINT32 CodeRegionBase;
/** Offset 0x0030
**/
UINT32 CodeRegionLength;
/** Offset 0x0034
**/
UINT8 Reserved1[12];
} FSPT_COMMON_UPD;
/** Fsp T UPD Configuration
**/
typedef struct {
/** Offset 0x0000
**/
FSP_UPD_HEADER FspUpdHeader;
/** Offset 0x0020
**/
FSPT_COMMON_UPD FsptCommonUpd;
/** Offset 0x0040
**/
UINT8 ReservedFsptUpd1[16];
/** Offset 0x0050
**/
UINT8 UnusedUpdSpace0[6];
/** Offset 0x0056
**/
UINT16 UpdTerminator;
} FSPT_UPD;
#pragma pack()
#endif

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/** @file
Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
This file is automatically generated. Please do NOT modify !!!
**/
#ifndef __GPIOCONFIG_H__
#define __GPIOCONFIG_H__
#include <stdint.h>
/* For any GpioPad usage in code use GPIO_PAD type*/
typedef u32 GPIO_PAD;
/* For any GpioGroup usage in code use GPIO_GROUP type */
typedef u32 GPIO_GROUP;
/*
GPIO configuration structure used for pin programming.
Structure contains fields that can be used to configure pad.
*/
typedef struct {
/*
Pad Mode
Pad can be set as GPIO or one of its native functions.
When in native mode setting Direction, OutputState, Interrupt is unnecessary.
Refer to definition of GPIO_PAD_MODE.
Refer to EDS for each native mode according to the pad.
*/
u32 PadMode : 3;
/*
Host Software Pad Ownership
Set pad to ACPI mode or GPIO Driver Mode.
Refer to definition of GPIO_HOSTSW_OWN.
*/
u32 HostSoftPadOwn : 2;
/*
GPIO Direction
Can choose between In, In with inversion Out, both In and Out, both In with inversion and out or d
isabling both.
Refer to definition of GPIO_DIRECTION for supported settings.
*/
u32 Direction : 5;
/*
Output State
Set Pad output value.
Refer to definition of GPIO_OUTPUT_STATE for supported settings.
This setting takes place when output is enabled.
*/
u32 OutputState : 2;
/*
GPIO Interrupt Configuration
Set Pad to cause one of interrupts (IOxAPIC/SCI/SMI/NMI). This setting is applicable only if GPIO
is in input mode.
If GPIO is set to cause an SCI then also Gpe is enabled for this pad.
Refer to definition of GPIO_INT_CONFIG for supported settings.
*/
u32 InterruptConfig : 8;
/*
GPIO Power Configuration.
This setting controls Pad Reset Configuration and Power Rail Type.
Refer to definition of GPIO_RESET_CONFIG for supported settings.
*/
u32 PowerConfig : 5;
/*
GPIO Electrical Configuration
This setting controls pads termination and voltage tolerance.
Refer to definition of GPIO_ELECTRICAL_CONFIG for supported settings.
*/
u32 ElectricalConfig : 7;
/*
GPIO Lock Configuration
This setting controls pads lock.
Refer to definition of GPIO_LOCK_CONFIG for supported settings.
*/
u32 LockConfig : 3;
/*
Additional GPIO configuration
Refer to definition of GPIO_OTHER_CONFIG for supported settings.
*/
u32 OtherSettings : 2;
u32 RsvdBits : 27;
} GPIO_CONFIG;
typedef struct {
GPIO_PAD GpioPad;
GPIO_CONFIG GpioConfig;
} GPIO_INIT_CONFIG;
typedef enum {
GpioHardwareDefault = 0x0
} GPIO_HARDWARE_DEFAULT;
/* GPIO Pad Mode */
typedef enum {
GpioPadModeGpio = 0x1,
GpioPadModeNative1 = 0x3,
GpioPadModeNative2 = 0x5,
GpioPadModeNative3 = 0x7
} GPIO_PAD_MODE;
/* Host Software Pad Ownership modes */
typedef enum {
GpioHostOwnDefault = 0x0, /* Leave ownership value unmodified */
GpioHostOwnAcpi = 0x1, /* Set HOST ownership to ACPI */
GpioHostOwnGpio = 0x3 /* Set HOST ownership to GPIO */
} GPIO_HOSTSW_OWN;
/* GPIO Direction */
typedef enum {
GpioDirDefault = 0x0, /* Leave pad direction setting unmodified */
GpioDirInOut = (0x1 | (0x1 << 3)), /* Set pad for both output and input */
GpioDirInInvOut = (0x1 | (0x3 << 3)), /* Set pad for both output and input with inversion */
GpioDirIn = (0x3 | (0x1 << 3)), /* Set pad for input only */
GpioDirInInv = (0x3 | (0x3 << 3)), /* Set pad for input with inversion */
GpioDirOut = 0x5, /* Set pad for output only */
GpioDirNone = 0x7 /* Disable both output and input */
} GPIO_DIRECTION;
/* GPIO Output State */
typedef enum {
GpioOutDefault = 0x0,
GpioOutLow = 0x1,
GpioOutHigh = 0x3
} GPIO_OUTPUT_STATE;
/*
GPIO interrupt configuration
This setting is applicable only if GPIO is in input mode.
GPIO_INT_CONFIG allows to choose which interrupt is generted
(IOxAPIC/SCI/SMI/NMI) and how it is triggered (edge or level).
Field from GpioIntNmi to GpioIntApic can be OR'ed with GpioIntLevel to
GpioIntBothEdgecan to describe an interrupt e.g. GpioIntApic | GpioIntLevel
If GPIO is set to cause an SCI then also Gpe is enabled for this pad.
Not all GPIO are capable of generating an SMI or NMI interrupt
*/
typedef enum {
GpioIntDefault = 0x0, /* Leave value of interrupt routing unmodified */
GpioIntDis = 0x1, /* Disable IOxAPIC/SCI/SMI/NMI interrupt generation */
GpioIntNmi = 0x3, /* Enable NMI interrupt only */
GpioIntSmi = 0x5, /* Enable SMI interrupt only */
GpioIntSci = 0x9, /* Enable SCI interrupt only */
GpioIntApic = 0x11, /* Enable IOxAPIC interrupt only */
GpioIntLevel = (0x1 << 5), /* Set interrupt as level triggered */
GpioIntEdge = (0x3 << 5), /* Set interrupt as edge triggered */
GpioIntLvlEdgDis = (0x5 << 5), /* Disable interrupt trigger */
GpioIntBothEdge = (0x7 << 5) /* Set interrupt as both edge triggered */
} GPIO_INT_CONFIG;
/*
GPIO Power Configuration
GPIO_RESET_CONFIG allows to set GPIO Reset (used to reset the specified
Pad Register fields).
*/
typedef enum {
GpioResetDefault = 0x0, /* Leave value of pad reset unmodified */
GpioResetPwrGood = 0x1, /* Powergood reset */
GpioResetDeep = 0x3, /* Deep GPIO Reset */
GpioResetNormal = 0x5, /* GPIO Reset */
GpioResetResume = 0x7 /* Resume Reset */
} GPIO_RESET_CONFIG;
/*
GPIO Electrical Configuration
Set GPIO termination and Pad Tolerance (applicable only for some pads)
Field from GpioTermDefault to GpioTermNative can be OR'ed with
GpioTolerance1v8.
*/
typedef enum {
GpioTermDefault = 0x0, /* Leave termination setting unmodified */
GpioTermNone = 0x1, /* none */
GpioTermWpd5K = 0x5, /* 5kOhm weak pull-down */
GpioTermWpd20K = 0x9, /* 20kOhm weak pull-down */
GpioTermWpu1K = 0x13, /* 1kOhm weak pull-up */
GpioTermWpu2K = 0x17, /* 2kOhm weak pull-up */
GpioTermWpu5K = 0x15, /* 5kOhm weak pull-up */
GpioTermWpu20K = 0x19, /* 20kOhm weak pull-up */
GpioTermWpu1K2K = 0x1B, /* 1kOhm & 2kOhm weak pull-up */
GpioTermNative = 0x1F, /* Native function for pads termination */
GpioNoTolerance1v8 = (0x1 << 5), /* Disable 1.8V pad tolerance */
GpioTolerance1v8 = (0x3 << 5) /* Enable 1.8V pad tolerance */
} GPIO_ELECTRICAL_CONFIG;
/*
GPIO LockConfiguration
Set GPIO configuration lock and output state lock
GpioLockPadConfig and GpioLockOutputState can be OR'ed
*/
typedef enum {
GpioLockDefault = 0x0, /* Leave lock setting unmodified */
GpioPadConfigLock = 0x3, /* Lock Pad Configuration */
GpioOutputStateLock = 0x5 /* Lock GPIO pad output value */
} GPIO_LOCK_CONFIG;
/*
Other GPIO Configuration
GPIO_OTHER_CONFIG is used for less often settings and for future extensions
Supported settings:
- RX raw override to '1' - allows to override input value to '1'
This is applicable only if in input mode (both in GPIO and native usage)
The override takes place at the internal pad state directly from buffer
and before the RXINV.
*/
typedef enum {
GpioRxRaw1Default = 0x0, /* Use default input override value */
GpioRxRaw1Dis = 0x1, /* Don't override input */
GpioRxRaw1En = 0x3 /* Override input to '1' */
} GPIO_OTHER_CONFIG;
/*
SKL LP GPIO pins
Use below for functions from PCH GPIO Lib which
require GpioPad as argument. Encoding used here
has all information required by library functions
*/
#define GPIO_SKL_LP_GPP_A0 0x02000000
#define GPIO_SKL_LP_GPP_A1 0x02000001
#define GPIO_SKL_LP_GPP_A2 0x02000002
#define GPIO_SKL_LP_GPP_A3 0x02000003
#define GPIO_SKL_LP_GPP_A4 0x02000004
#define GPIO_SKL_LP_GPP_A5 0x02000005
#define GPIO_SKL_LP_GPP_A6 0x02000006
#define GPIO_SKL_LP_GPP_A7 0x02000007
#define GPIO_SKL_LP_GPP_A8 0x02000008
#define GPIO_SKL_LP_GPP_A9 0x02000009
#define GPIO_SKL_LP_GPP_A10 0x0200000A
#define GPIO_SKL_LP_GPP_A11 0x0200000B
#define GPIO_SKL_LP_GPP_A12 0x0200000C
#define GPIO_SKL_LP_GPP_A13 0x0200000D
#define GPIO_SKL_LP_GPP_A14 0x0200000E
#define GPIO_SKL_LP_GPP_A15 0x0200000F
#define GPIO_SKL_LP_GPP_A16 0x02000010
#define GPIO_SKL_LP_GPP_A17 0x02000011
#define GPIO_SKL_LP_GPP_A18 0x02000012
#define GPIO_SKL_LP_GPP_A19 0x02000013
#define GPIO_SKL_LP_GPP_A20 0x02000014
#define GPIO_SKL_LP_GPP_A21 0x02000015
#define GPIO_SKL_LP_GPP_A22 0x02000016
#define GPIO_SKL_LP_GPP_A23 0x02000017
#define GPIO_SKL_LP_GPP_B0 0x02010000
#define GPIO_SKL_LP_GPP_B1 0x02010001
#define GPIO_SKL_LP_GPP_B2 0x02010002
#define GPIO_SKL_LP_GPP_B3 0x02010003
#define GPIO_SKL_LP_GPP_B4 0x02010004
#define GPIO_SKL_LP_GPP_B5 0x02010005
#define GPIO_SKL_LP_GPP_B6 0x02010006
#define GPIO_SKL_LP_GPP_B7 0x02010007
#define GPIO_SKL_LP_GPP_B8 0x02010008
#define GPIO_SKL_LP_GPP_B9 0x02010009
#define GPIO_SKL_LP_GPP_B10 0x0201000A
#define GPIO_SKL_LP_GPP_B11 0x0201000B
#define GPIO_SKL_LP_GPP_B12 0x0201000C
#define GPIO_SKL_LP_GPP_B13 0x0201000D
#define GPIO_SKL_LP_GPP_B14 0x0201000E
#define GPIO_SKL_LP_GPP_B15 0x0201000F
#define GPIO_SKL_LP_GPP_B16 0x02010010
#define GPIO_SKL_LP_GPP_B17 0x02010011
#define GPIO_SKL_LP_GPP_B18 0x02010012
#define GPIO_SKL_LP_GPP_B19 0x02010013
#define GPIO_SKL_LP_GPP_B20 0x02010014
#define GPIO_SKL_LP_GPP_B21 0x02010015
#define GPIO_SKL_LP_GPP_B22 0x02010016
#define GPIO_SKL_LP_GPP_B23 0x02010017
#define GPIO_SKL_LP_GPP_C0 0x02020000
#define GPIO_SKL_LP_GPP_C1 0x02020001
#define GPIO_SKL_LP_GPP_C2 0x02020002
#define GPIO_SKL_LP_GPP_C3 0x02020003
#define GPIO_SKL_LP_GPP_C4 0x02020004
#define GPIO_SKL_LP_GPP_C5 0x02020005
#define GPIO_SKL_LP_GPP_C6 0x02020006
#define GPIO_SKL_LP_GPP_C7 0x02020007
#define GPIO_SKL_LP_GPP_C8 0x02020008
#define GPIO_SKL_LP_GPP_C9 0x02020009
#define GPIO_SKL_LP_GPP_C10 0x0202000A
#define GPIO_SKL_LP_GPP_C11 0x0202000B
#define GPIO_SKL_LP_GPP_C12 0x0202000C
#define GPIO_SKL_LP_GPP_C13 0x0202000D
#define GPIO_SKL_LP_GPP_C14 0x0202000E
#define GPIO_SKL_LP_GPP_C15 0x0202000F
#define GPIO_SKL_LP_GPP_C16 0x02020010
#define GPIO_SKL_LP_GPP_C17 0x02020011
#define GPIO_SKL_LP_GPP_C18 0x02020012
#define GPIO_SKL_LP_GPP_C19 0x02020013
#define GPIO_SKL_LP_GPP_C20 0x02020014
#define GPIO_SKL_LP_GPP_C21 0x02020015
#define GPIO_SKL_LP_GPP_C22 0x02020016
#define GPIO_SKL_LP_GPP_C23 0x02020017
#define GPIO_SKL_LP_GPP_D0 0x02030000
#define GPIO_SKL_LP_GPP_D1 0x02030001
#define GPIO_SKL_LP_GPP_D2 0x02030002
#define GPIO_SKL_LP_GPP_D3 0x02030003
#define GPIO_SKL_LP_GPP_D4 0x02030004
#define GPIO_SKL_LP_GPP_D5 0x02030005
#define GPIO_SKL_LP_GPP_D6 0x02030006
#define GPIO_SKL_LP_GPP_D7 0x02030007
#define GPIO_SKL_LP_GPP_D8 0x02030008
#define GPIO_SKL_LP_GPP_D9 0x02030009
#define GPIO_SKL_LP_GPP_D10 0x0203000A
#define GPIO_SKL_LP_GPP_D11 0x0203000B
#define GPIO_SKL_LP_GPP_D12 0x0203000C
#define GPIO_SKL_LP_GPP_D13 0x0203000D
#define GPIO_SKL_LP_GPP_D14 0x0203000E
#define GPIO_SKL_LP_GPP_D15 0x0203000F
#define GPIO_SKL_LP_GPP_D16 0x02030010
#define GPIO_SKL_LP_GPP_D17 0x02030011
#define GPIO_SKL_LP_GPP_D18 0x02030012
#define GPIO_SKL_LP_GPP_D19 0x02030013
#define GPIO_SKL_LP_GPP_D20 0x02030014
#define GPIO_SKL_LP_GPP_D21 0x02030015
#define GPIO_SKL_LP_GPP_D22 0x02030016
#define GPIO_SKL_LP_GPP_D23 0x02030017
#define GPIO_SKL_LP_GPP_E0 0x02040000
#define GPIO_SKL_LP_GPP_E1 0x02040001
#define GPIO_SKL_LP_GPP_E2 0x02040002
#define GPIO_SKL_LP_GPP_E3 0x02040003
#define GPIO_SKL_LP_GPP_E4 0x02040004
#define GPIO_SKL_LP_GPP_E5 0x02040005
#define GPIO_SKL_LP_GPP_E6 0x02040006
#define GPIO_SKL_LP_GPP_E7 0x02040007
#define GPIO_SKL_LP_GPP_E8 0x02040008
#define GPIO_SKL_LP_GPP_E9 0x02040009
#define GPIO_SKL_LP_GPP_E10 0x0204000A
#define GPIO_SKL_LP_GPP_E11 0x0204000B
#define GPIO_SKL_LP_GPP_E12 0x0204000C
#define GPIO_SKL_LP_GPP_E13 0x0204000D
#define GPIO_SKL_LP_GPP_E14 0x0204000E
#define GPIO_SKL_LP_GPP_E15 0x0204000F
#define GPIO_SKL_LP_GPP_E16 0x02040010
#define GPIO_SKL_LP_GPP_E17 0x02040011
#define GPIO_SKL_LP_GPP_E18 0x02040012
#define GPIO_SKL_LP_GPP_E19 0x02040013
#define GPIO_SKL_LP_GPP_E20 0x02040014
#define GPIO_SKL_LP_GPP_E21 0x02040015
#define GPIO_SKL_LP_GPP_E22 0x02040016
#define GPIO_SKL_LP_GPP_E23 0x02040017
#define GPIO_SKL_LP_GPP_F0 0x02050000
#define GPIO_SKL_LP_GPP_F1 0x02050001
#define GPIO_SKL_LP_GPP_F2 0x02050002
#define GPIO_SKL_LP_GPP_F3 0x02050003
#define GPIO_SKL_LP_GPP_F4 0x02050004
#define GPIO_SKL_LP_GPP_F5 0x02050005
#define GPIO_SKL_LP_GPP_F6 0x02050006
#define GPIO_SKL_LP_GPP_F7 0x02050007
#define GPIO_SKL_LP_GPP_F8 0x02050008
#define GPIO_SKL_LP_GPP_F9 0x02050009
#define GPIO_SKL_LP_GPP_F10 0x0205000A
#define GPIO_SKL_LP_GPP_F11 0x0205000B
#define GPIO_SKL_LP_GPP_F12 0x0205000C
#define GPIO_SKL_LP_GPP_F13 0x0205000D
#define GPIO_SKL_LP_GPP_F14 0x0205000E
#define GPIO_SKL_LP_GPP_F15 0x0205000F
#define GPIO_SKL_LP_GPP_F16 0x02050010
#define GPIO_SKL_LP_GPP_F17 0x02050011
#define GPIO_SKL_LP_GPP_F18 0x02050012
#define GPIO_SKL_LP_GPP_F19 0x02050013
#define GPIO_SKL_LP_GPP_F20 0x02050014
#define GPIO_SKL_LP_GPP_F21 0x02050015
#define GPIO_SKL_LP_GPP_F22 0x02050016
#define GPIO_SKL_LP_GPP_F23 0x02050017
#define GPIO_SKL_LP_GPP_G0 0x02060000
#define GPIO_SKL_LP_GPP_G1 0x02060001
#define GPIO_SKL_LP_GPP_G2 0x02060002
#define GPIO_SKL_LP_GPP_G3 0x02060003
#define GPIO_SKL_LP_GPP_G4 0x02060004
#define GPIO_SKL_LP_GPP_G5 0x02060005
#define GPIO_SKL_LP_GPP_G6 0x02060006
#define GPIO_SKL_LP_GPP_G7 0x02060007
#define GPIO_SKL_LP_GPD0 0x02070000
#define GPIO_SKL_LP_GPD1 0x02070001
#define GPIO_SKL_LP_GPD2 0x02070002
#define GPIO_SKL_LP_GPD3 0x02070003
#define GPIO_SKL_LP_GPD4 0x02070004
#define GPIO_SKL_LP_GPD5 0x02070005
#define GPIO_SKL_LP_GPD6 0x02070006
#define GPIO_SKL_LP_GPD7 0x02070007
#define GPIO_SKL_LP_GPD8 0x02070008
#define GPIO_SKL_LP_GPD9 0x02070009
#define GPIO_SKL_LP_GPD10 0x0207000A
#define GPIO_SKL_LP_GPD11 0x0207000B
#define END_OF_GPIO_TABLE 0xFFFFFFFF
//Sample GPIO Table
static GPIO_INIT_CONFIG mGpioTableLpDdr3Rvp3[] =
{
//skip for eSPI function {GPIO_SKL_LP_GPP_A0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//H_RCIN_N
//skip for eSPI function {GPIO_SKL_LP_GPP_A1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermWpd20K}},//LPC_AD0_ESPI_IO0
//skip for eSPI function {GPIO_SKL_LP_GPP_A2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermWpd20K}},//LPC_AD1_ESPI_IO1
//skip for eSPI function {GPIO_SKL_LP_GPP_A3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermWpd20K}},//LPC_AD2_ESPI_IO2
//skip for eSPI function {GPIO_SKL_LP_GPP_A4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermWpd20K}},//LPC_AD3_ESPI_IO3
//skip for eSPI function {GPIO_SKL_LP_GPP_A5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//LPC_FRAME_ESPI_CS_N
//skip for eSPI function {GPIO_SKL_LP_GPP_A6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//INT_SERIRQ
//skip for eSPI function {GPIO_SKL_LP_GPP_A7, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone}},//PM_SLP_S0ix_R_N
{GPIO_SKL_LP_GPP_A8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//PM_CLKRUN_N
//skip for eSPI function {GPIO_SKL_LP_GPP_A9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermWpd20K}},//LPC_CLK_ESPI_CLK
{GPIO_SKL_LP_GPP_A10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermWpd20K}},//PCH_CLK_PCI_TPM
{GPIO_SKL_LP_GPP_A11, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioResetDeep, GpioTermNone}},//EC_HID_INTR
{GPIO_SKL_LP_GPP_A12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone}},//M.2_WWAN_GNSS_UART_RST_N
{GPIO_SKL_LP_GPP_A13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SUS_PWR_ACK_R
//skip for eSPI function {GPIO_SKL_LP_GPP_A14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//PM_SUS_STAT_ESPI_RST_N
{GPIO_SKL_LP_GPP_A15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermWpd20K}},//SUSACK_R_N
{GPIO_SKL_LP_GPP_A16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SD_1P8_SEL
{GPIO_SKL_LP_GPP_A17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SD_PWR_EN_N
{GPIO_SKL_LP_GPP_A18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//ISH_GP_0_SENSOR
{GPIO_SKL_LP_GPP_A19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//ISH_GP_1_SENSOR
{GPIO_SKL_LP_GPP_A20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//ISH_GP_2_SENSOR
{GPIO_SKL_LP_GPP_A21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//GNSS_CHUB_IRQ
{GPIO_SKL_LP_GPP_A22, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone}},//FPS_SLP_N
{GPIO_SKL_LP_GPP_A23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioResetDeep, GpioTermNone}},//FPS_DRDY
{GPIO_SKL_LP_GPP_B0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//V0.85A_VID0
{GPIO_SKL_LP_GPP_B1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//V0.85A_VID1
{GPIO_SKL_LP_GPP_B2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//GP_VRALERTB
{GPIO_SKL_LP_GPP_B3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioResetNormal, GpioTermNone}},//TCH_PAD_INTR_R_N
{GPIO_SKL_LP_GPP_B4, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone}},//BT_RF_KILL_N
{GPIO_SKL_LP_GPP_B5, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioResetDeep, GpioTermNone}},//M.2_BT_UART_WAKE_N
// {GPIO_SKL_LP_GPP_B6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//CLK_REQ_SLOT1_N
// {GPIO_SKL_LP_GPP_B7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//CLK_REQ_SLOT2_LAN_N
// {GPIO_SKL_LP_GPP_B8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//CLK_REQ_M.2_SSD_SLOT3_N
// {GPIO_SKL_LP_GPP_B9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//CLK_REQ_M.2_WIGIG_N
// {GPIO_SKL_LP_GPP_B10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//CLK_REQ_M.2_WLAN_N
{GPIO_SKL_LP_GPP_B11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//MPHY_EXT_PWR_GATEB
{GPIO_SKL_LP_GPP_B12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//PCH_SLP_S0_N
{GPIO_SKL_LP_GPP_B13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//PLT_RST_N
{GPIO_SKL_LP_GPP_B14, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermWpd20K}},//TCH_PNL_PWREN
{GPIO_SKL_LP_GPP_B15, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone}},//PCH_NFC_DFU
{GPIO_SKL_LP_GPP_B16, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioResetNormal, GpioTermNone}},//M.2_WLAN_WIFI_WAKE_N
{GPIO_SKL_LP_GPP_B17, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntSci, GpioResetDeep, GpioTermWpd20K}},//TBT_CIO_PLUG_EVENT_N
{GPIO_SKL_LP_GPP_B18, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioResetNormal, GpioTermWpu20K}},//PCH_SLOT1_WAKE_N
{GPIO_SKL_LP_GPP_B19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//FPS_GSPI1_CS_R1_N
{GPIO_SKL_LP_GPP_B20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermWpd20K}},//FPS_GSPI1_CLK_R1
{GPIO_SKL_LP_GPP_B21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermWpd20K}},//FPS_GSPI1_MISO_R1
{GPIO_SKL_LP_GPP_B22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermWpd20K}},//FPS_GSPI1_MOSI_R1
{GPIO_SKL_LP_GPP_B23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermWpd20K}},//DISCRETE_GNSS_RESET_N
{GPIO_SKL_LP_GPP_C0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SMB_CLK
{GPIO_SKL_LP_GPP_C1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermWpd20K}},//SMB_DATA
{GPIO_SKL_LP_GPP_C2, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermWpd20K}},//SKIN_THRM_SNSR_ALERT_N
{GPIO_SKL_LP_GPP_C3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SML0_CLK
{GPIO_SKL_LP_GPP_C4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SML0_DATA
{GPIO_SKL_LP_GPP_C5, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioResetDeep, GpioTermWpd20K}},//M.2_WIGIG_WAKE_N
{GPIO_SKL_LP_GPP_C6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SML1_CLK
{GPIO_SKL_LP_GPP_C7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermWpd20K}},//SML1_DATA
{GPIO_SKL_LP_GPP_C8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SERIALIO_UART0_RXD
{GPIO_SKL_LP_GPP_C9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SERIALIO_UART0_TXD
{GPIO_SKL_LP_GPP_C10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SERIALIO_UART0_RTS_N
{GPIO_SKL_LP_GPP_C11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SERIALIO_UART0_CTS_N
{GPIO_SKL_LP_GPP_C12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_RXD
{GPIO_SKL_LP_GPP_C13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_TXD
{GPIO_SKL_LP_GPP_C14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_RTS_N
{GPIO_SKL_LP_GPP_C15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_CTS_N
{GPIO_SKL_LP_GPP_C16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SERIALIO_I2C0_SDA
{GPIO_SKL_LP_GPP_C17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SERIALIO_I2C0_SCL
{GPIO_SKL_LP_GPP_C18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SERIALIO_I2C1_SDA
{GPIO_SKL_LP_GPP_C19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SERIALIO_I2C1_SCL
{GPIO_SKL_LP_GPP_C20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SERIALIO_UART2_RXD
{GPIO_SKL_LP_GPP_C21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SERIALIO_UART2_TXD
{GPIO_SKL_LP_GPP_C22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SERIALIO_UART2_RTS_N
{GPIO_SKL_LP_GPP_C23, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SERIALIO_UART2_CTS_N
{GPIO_SKL_LP_GPP_D0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SPI1_TCHPNL_CS_N
{GPIO_SKL_LP_GPP_D1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SPI1_TCHPNL_CLK
{GPIO_SKL_LP_GPP_D2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SPI1_TCHPNL_MISO
{GPIO_SKL_LP_GPP_D3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SPI1_TCHPNL_MOSI
{GPIO_SKL_LP_GPP_D4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//CSI2_FLASH_STROBE
{GPIO_SKL_LP_GPP_D5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//ISH_I2C0_SDA
{GPIO_SKL_LP_GPP_D6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//ISH_I2C0_SCL
{GPIO_SKL_LP_GPP_D7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//ISH_I2C1_SDA
{GPIO_SKL_LP_GPP_D8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//ISH_I2C1_SCL
{GPIO_SKL_LP_GPP_D9, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioResetDeep, GpioTermNone}},//HOME_BTN
{GPIO_SKL_LP_GPP_D10, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioResetDeep, GpioTermNone}},//SCREEN_LOCK_PCH
{GPIO_SKL_LP_GPP_D11, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioResetDeep, GpioTermNone}},//VOL_UP_PCH
{GPIO_SKL_LP_GPP_D12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioResetDeep, GpioTermNone}},//VOL_DOWN_PCH
{GPIO_SKL_LP_GPP_D13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//ISH_UART0_RXD_SML0B_DATA
{GPIO_SKL_LP_GPP_D14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//ISH_UART0_TXD_SML0B_CLK
{GPIO_SKL_LP_GPP_D15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//ISH_UART0_RTS_N
{GPIO_SKL_LP_GPP_D16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//ISH_UART0_CTS_SML0B_ALERT_N
{GPIO_SKL_LP_GPP_D17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//DMIC_CLK_1
{GPIO_SKL_LP_GPP_D18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//DMIC_DATA_1
{GPIO_SKL_LP_GPP_D19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//DMIC_CLK_0
{GPIO_SKL_LP_GPP_D20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//DMIC_DATA_0
{GPIO_SKL_LP_GPP_D21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SPI1_TCHPNL_IO2
{GPIO_SKL_LP_GPP_D22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SPI1_TCHPNL_IO3
{GPIO_SKL_LP_GPP_D23, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SSP_MCLK
{GPIO_SKL_LP_GPP_E0, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntApic, GpioResetDeep, GpioTermNone}},//SPI_TPM_HDR_IRQ_N
{GPIO_SKL_LP_GPP_E1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SATA_ODD_PRSNT_N
{GPIO_SKL_LP_GPP_E2, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntLvlEdgDis | GpioIntApic, GpioResetDeep, GpioTermNone}},//M.2_SSD_SATA2_PCIE3_DET_N
{GPIO_SKL_LP_GPP_E3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone}},//EINK_SSR_DFU_N
{GPIO_SKL_LP_GPP_E4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//PCH_NFC_RESET
{GPIO_SKL_LP_GPP_E5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SATA1_PHYSLP1_DIRECT_R
{GPIO_SKL_LP_GPP_E6, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone}},//SATA2_PHYSLP2_M.2SSD_R
{GPIO_SKL_LP_GPP_E8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//PCH_SATA_LED_N
{GPIO_SKL_LP_GPP_E9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//USB_OC_0_WP1_OTG_N
{GPIO_SKL_LP_GPP_E10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//USB_OC_1_WP4_N
{GPIO_SKL_LP_GPP_E11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//USB_OC_2_WP2_WP3_WP5_R_N
{GPIO_SKL_LP_GPP_E12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioResetDeep, GpioTermNone}},//PCH_NFC_IRQ
{GPIO_SKL_LP_GPP_E13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//DDI1_HPD_Q
{GPIO_SKL_LP_GPP_E14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//DDI2_HPD_Q
{GPIO_SKL_LP_GPP_E15, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntSmi, GpioResetDeep, GpioTermNone}},//SMC_EXTSMI_R_N
{GPIO_SKL_LP_GPP_E16, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioResetNormal, GpioTermNone}},//SMC_RUNTIME_SCI_R_N
{GPIO_SKL_LP_GPP_E17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//EDP_HPD
{GPIO_SKL_LP_GPP_E18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//DDI1_CTRL_CLK
{GPIO_SKL_LP_GPP_E19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermWpd20K}},//DDI1_CTRL_DATA
{GPIO_SKL_LP_GPP_E20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//DDI2_CTRL_CLK
{GPIO_SKL_LP_GPP_E21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermWpd20K}},//DDI2_CTRL_DATA
{GPIO_SKL_LP_GPP_E22, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioResetDeep, GpioTermNone}},//PCH_CODEC_IRQ
{GPIO_SKL_LP_GPP_E23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermWpd20K}},//TCH_PNL_RST_N
{GPIO_SKL_LP_GPP_F0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SSP2_SCLK
{GPIO_SKL_LP_GPP_F1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SSP2_SFRM
{GPIO_SKL_LP_GPP_F2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SSP2_TXD
{GPIO_SKL_LP_GPP_F3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SSP2_RXD
{GPIO_SKL_LP_GPP_F4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C2_SDA
{GPIO_SKL_LP_GPP_F5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C2_SCL
{GPIO_SKL_LP_GPP_F6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C3_SDA
{GPIO_SKL_LP_GPP_F7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C3_SCL
{GPIO_SKL_LP_GPP_F8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C4_SDA
{GPIO_SKL_LP_GPP_F9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C4_SCL
{GPIO_SKL_LP_GPP_F10, {GpioPadModeNative2, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C5_ISH_12C2_SDA
{GPIO_SKL_LP_GPP_F11, {GpioPadModeNative2, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C5_ISH_12C2_SCL
{GPIO_SKL_LP_GPP_F12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//EMMC_CMD
{GPIO_SKL_LP_GPP_F13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//EMMC_DATA0
{GPIO_SKL_LP_GPP_F14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//EMMC_DATA1
{GPIO_SKL_LP_GPP_F15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//EMMC_DATA2
{GPIO_SKL_LP_GPP_F16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//EMMC_DATA3
{GPIO_SKL_LP_GPP_F17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//EMMC_DATA4
{GPIO_SKL_LP_GPP_F18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//EMMC_DATA5
{GPIO_SKL_LP_GPP_F19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//EMMC_DATA6
{GPIO_SKL_LP_GPP_F20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//EMMC_DATA7
{GPIO_SKL_LP_GPP_F21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//EMMC_RCLK
{GPIO_SKL_LP_GPP_F22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//EMMC_CLK
{GPIO_SKL_LP_GPP_F23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioResetDeep, GpioTermNone}},//PCH_M.2_WWAN_UIM_SIM_DET
{GPIO_SKL_LP_GPP_G0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SD_CMD
{GPIO_SKL_LP_GPP_G1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SD_DATA0
{GPIO_SKL_LP_GPP_G2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SD_DATA1
{GPIO_SKL_LP_GPP_G3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SD_DATA2
{GPIO_SKL_LP_GPP_G4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SD_DATA3
{GPIO_SKL_LP_GPP_G5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SD_CDB
{GPIO_SKL_LP_GPP_G6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SD_CLK
{GPIO_SKL_LP_GPP_G7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},//SD_WP
{GPIO_SKL_LP_GPD0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone}},//PM_BATLOW_R_N
{GPIO_SKL_LP_GPD1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone}},//AC_PRESENT_R
{GPIO_SKL_LP_GPD2, {GpioPadModeNative1, GpioHostOwnAcpi, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioResetPwrGood, GpioTermNone}},//LANWAKE_SMC_WAKE_SCI_N
{GPIO_SKL_LP_GPD3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermWpu20K}},//PM_PWRBTN_R_N
{GPIO_SKL_LP_GPD4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone}},//SLP_S3_R_N
{GPIO_SKL_LP_GPD5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone}},//SLP_S4_R_N
{GPIO_SKL_LP_GPD6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone}},//SLP_M_R_N
{GPIO_SKL_LP_GPD7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone}},//USB_WAKEOUT_INTRUDET_N
{GPIO_SKL_LP_GPD8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone}},//SUS_CLK
{GPIO_SKL_LP_GPD9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone}},//PCH_SLP_WLAN_N
{GPIO_SKL_LP_GPD10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone}},//SLP_S5_R_N
{GPIO_SKL_LP_GPD11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone}},//PM_LANPHY_ENABLE
{END_OF_GPIO_TABLE, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone}},//Marking End of Table
};
#endif //_GPIO_CONFIG_H_

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/** @file
Boot Setting File for Platform Configuration.
Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
This file is automatically generated. Please do NOT modify !!!
**/
GlobalDataDef
SKUID = 0, "DEFAULT"
EndGlobalData
StructDef
Find "VLV2UPDR"
Skip 24 bytes
$gPlatformFspPkgTokenSpaceGuid_PcdMrcInitTsegSize 2 bytes $_DEFAULT_ = 0x0001
$gPlatformFspPkgTokenSpaceGuid_PcdMrcInitMmioSize 2 bytes $_DEFAULT_ = 0x0800
$gPlatformFspPkgTokenSpaceGuid_PcdMrcInitSPDAddr1 1 bytes $_DEFAULT_ = 0xA0
$gPlatformFspPkgTokenSpaceGuid_PcdMrcInitSPDAddr2 1 bytes $_DEFAULT_ = 0xA2
$gPlatformFspPkgTokenSpaceGuid_PcdeMMCBootMode 1 bytes $_DEFAULT_ = 2
$gPlatformFspPkgTokenSpaceGuid_PcdEnableSdio 1 bytes $_DEFAULT_ = 1
$gPlatformFspPkgTokenSpaceGuid_PcdEnableSdcard 1 bytes $_DEFAULT_ = 1
$gPlatformFspPkgTokenSpaceGuid_PcdEnableHsuart0 1 bytes $_DEFAULT_ = 0
$gPlatformFspPkgTokenSpaceGuid_PcdEnableHsuart1 1 bytes $_DEFAULT_ = 1
$gPlatformFspPkgTokenSpaceGuid_PcdEnableSpi 1 bytes $_DEFAULT_ = 1
Skip 1 bytes
$gPlatformFspPkgTokenSpaceGuid_PcdEnableSata 1 bytes $_DEFAULT_ = 1
$gPlatformFspPkgTokenSpaceGuid_PcdSataMode 1 bytes $_DEFAULT_ = 1
$gPlatformFspPkgTokenSpaceGuid_PcdEnableAzalia 1 bytes $_DEFAULT_ = 0
$gPlatformFspPkgTokenSpaceGuid_AzaliaConfigPtr 4 bytes $_DEFAULT_ = 0
$gPlatformFspPkgTokenSpaceGuid_PcdEnableXhci 1 bytes $_DEFAULT_ = 1
$gPlatformFspPkgTokenSpaceGuid_PcdEnableLpe 1 bytes $_DEFAULT_ = 1
$gPlatformFspPkgTokenSpaceGuid_PcdLpssSioEnablePciMode 1 bytes $_DEFAULT_ = 1
$gPlatformFspPkgTokenSpaceGuid_PcdEnableDma0 1 bytes $_DEFAULT_ = 1
$gPlatformFspPkgTokenSpaceGuid_PcdEnableDma1 1 bytes $_DEFAULT_ = 1
$gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C0 1 bytes $_DEFAULT_ = 1
$gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C1 1 bytes $_DEFAULT_ = 1
$gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C2 1 bytes $_DEFAULT_ = 1
$gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C3 1 bytes $_DEFAULT_ = 1
$gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C4 1 bytes $_DEFAULT_ = 1
$gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C5 1 bytes $_DEFAULT_ = 1
$gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C6 1 bytes $_DEFAULT_ = 1
$gPlatformFspPkgTokenSpaceGuid_PcdEnablePwm0 1 bytes $_DEFAULT_ = 1
$gPlatformFspPkgTokenSpaceGuid_PcdEnablePwm1 1 bytes $_DEFAULT_ = 1
$gPlatformFspPkgTokenSpaceGuid_PcdEnableHsi 1 bytes $_DEFAULT_ = 0
$gPlatformFspPkgTokenSpaceGuid_PcdIgdDvmt50PreAlloc 1 bytes $_DEFAULT_ = 2
$gPlatformFspPkgTokenSpaceGuid_PcdApertureSize 1 bytes $_DEFAULT_ = 2
$gPlatformFspPkgTokenSpaceGuid_PcdGttSize 1 bytes $_DEFAULT_ = 2
Skip 5 bytes
$gPlatformFspPkgTokenSpaceGuid_PcdMrcDebugMsg 1 bytes $_DEFAULT_ = 0
$gPlatformFspPkgTokenSpaceGuid_ISPEnable 1 bytes $_DEFAULT_ = 0
$gPlatformFspPkgTokenSpaceGuid_PcdSccEnablePciMode 1 bytes $_DEFAULT_ = 1
$gPlatformFspPkgTokenSpaceGuid_IgdRenderStandby 1 bytes $_DEFAULT_ = 0
$gPlatformFspPkgTokenSpaceGuid_TxeUmaEnable 1 bytes $_DEFAULT_ = 0
$gPlatformFspPkgTokenSpaceGuid_PcdOsSelection 1 bytes $_DEFAULT_ = 0x4
$gPlatformFspPkgTokenSpaceGuid_eMMC45DDR50Enabled 1 bytes $_DEFAULT_ = 1
$gPlatformFspPkgTokenSpaceGuid_eMMC45HS200Enabled 1 bytes $_DEFAULT_ = 0
$gPlatformFspPkgTokenSpaceGuid_eMMC45RetuneTimerValue 1 bytes $_DEFAULT_ = 8
$gPlatformFspPkgTokenSpaceGuid_PcdEnableIgd 1 bytes $_DEFAULT_ = 1
Skip 155 bytes
$gPlatformFspPkgTokenSpaceGuid_PcdEnableMemoryDown 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_PcdDRAMSpeed 1 bytes $_DEFAULT_ = 0x02
$gPlatformFspPkgTokenSpaceGuid_PcdDRAMType 1 bytes $_DEFAULT_ = 0x01
$gPlatformFspPkgTokenSpaceGuid_PcdDIMM0Enable 1 bytes $_DEFAULT_ = 0x01
$gPlatformFspPkgTokenSpaceGuid_PcdDIMM1Enable 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_PcdDIMMDWidth 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_PcdDIMMDensity 1 bytes $_DEFAULT_ = 0x01
$gPlatformFspPkgTokenSpaceGuid_PcdDIMMBusWidth 1 bytes $_DEFAULT_ = 0x03
$gPlatformFspPkgTokenSpaceGuid_PcdDIMMSides 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_PcdDIMMtCL 1 bytes $_DEFAULT_ = 0x09
$gPlatformFspPkgTokenSpaceGuid_PcdDIMMtRPtRCD 1 bytes $_DEFAULT_ = 0x09
$gPlatformFspPkgTokenSpaceGuid_PcdDIMMtWR 1 bytes $_DEFAULT_ = 0x0A
$gPlatformFspPkgTokenSpaceGuid_PcdDIMMtWTR 1 bytes $_DEFAULT_ = 0x05
$gPlatformFspPkgTokenSpaceGuid_PcdDIMMtRRD 1 bytes $_DEFAULT_ = 0x04
$gPlatformFspPkgTokenSpaceGuid_PcdDIMMtRTP 1 bytes $_DEFAULT_ = 0x05
$gPlatformFspPkgTokenSpaceGuid_PcdDIMMtFAW 1 bytes $_DEFAULT_ = 0x14
Find "VLYVIEW1"
$gPlatformFspPkgTokenSpaceGuid_PcdImageRevision 4 bytes $_DEFAULT_ = 0x00000304
Skip 24 bytes
$gPlatformFspPkgTokenSpaceGuid_PcdPlatformType 1 bytes $_DEFAULT_ = 2
$gPlatformFspPkgTokenSpaceGuid_PcdEnableSecureBoot 1 bytes $_DEFAULT_ = 2
EndStruct
List &EN_DIS
Selection 0x1 , "Enabled"
Selection 0x0 , "Disabled"
EndList
List &gPlatformFspPkgTokenSpaceGuid_PcdDIMMSides
Selection 0x0 , "1 Ranks"
Selection 0x1 , "2 Ranks"
EndList
List &gPlatformFspPkgTokenSpaceGuid_PcdIgdDvmt50PreAlloc
Selection 0x01 , "32 MB"
Selection 0x02 , "64 MB"
Selection 0x03 , "96 MB"
Selection 0x04 , "128 MB"
Selection 0x05 , "160 MB"
Selection 0x06 , "192 MB"
Selection 0x07 , "224 MB"
Selection 0x08 , "256 MB"
Selection 0x09 , "288 MB"
Selection 0x0A , "320 MB"
Selection 0x0B , "352 MB"
Selection 0x0C , "384 MB"
Selection 0x0D , "416 MB"
Selection 0x0E , "448 MB"
Selection 0x0F , "480 MB"
Selection 0x10 , "512 MB"
EndList
List &gPlatformFspPkgTokenSpaceGuid_PcdOsSelection
Selection 0x1 , "Android"
Selection 0x4 , "Linux OS"
EndList
List &gPlatformFspPkgTokenSpaceGuid_PcdDIMMDensity
Selection 0x0 , "1 Gbit"
Selection 0x1 , "2 Gbit"
Selection 0x2 , "4 Gbit"
Selection 0x3 , "8 Gbit"
EndList
List &gPlatformFspPkgTokenSpaceGuid_PcdEnableLpe
Selection 0x2 , "ACPI Mode"
Selection 0x1 , "PCI Mode"
Selection 0x0 , "Disabled"
EndList
List &gPlatformFspPkgTokenSpaceGuid_PcdDRAMType
Selection 0x0 , "DDR3"
Selection 0x1 , "DDR3L"
Selection 0x2 , "DDR3ECC"
Selection 0x4 , "LPDDR2"
Selection 0x5 , "LPDDR3"
Selection 0x6 , "DDR4"
EndList
List &gPlatformFspPkgTokenSpaceGuid_PcdMrcInitTsegSize
Selection 0x01 , "1 MB"
Selection 0x02 , "2 MB"
Selection 0x04 , "4 MB"
Selection 0x08 , "8 MB"
EndList
List &gPlatformFspPkgTokenSpaceGuid_PcdPlatformType
Selection 0x2 , "BayleyBay Platform Type"
Selection 0x3 , "BakerSport Platform (ECC) Type"
EndList
List &gPlatformFspPkgTokenSpaceGuid_PcdMrcInitMmioSize
Selection 0x400 , "1.0 GB"
Selection 0x600 , "1.5 GB"
Selection 0x800 , "2.0 GB"
EndList
List &gPlatformFspPkgTokenSpaceGuid_PcdGttSize
Selection 0x1 , "1 MB"
Selection 0x2 , "2 MB"
EndList
List &gPlatformFspPkgTokenSpaceGuid_PcdSataMode
Selection 1 , "AHCI"
Selection 0 , "IDE"
EndList
List &gPlatformFspPkgTokenSpaceGuid_PcdDIMMBusWidth
Selection 0x0 , "8 bits"
Selection 0x1 , "16 bits"
Selection 0x2 , "32 bits"
Selection 0x3 , "64 bits"
EndList
List &gPlatformFspPkgTokenSpaceGuid_PcdEnableSecureBoot
Selection 0 , "Disabled"
Selection 1 , "Enabled"
Selection 2 , "Auto"
EndList
List &gPlatformFspPkgTokenSpaceGuid_PcdApertureSize
Selection 0x1 , "128 MB"
Selection 0x2 , "256 MB"
Selection 0x3 , "512 MB"
EndList
List &gPlatformFspPkgTokenSpaceGuid_PcdDRAMSpeed
Selection 0x0 , "800 MT/s"
Selection 0x1 , "1066 MT/s"
Selection 0x2 , "1333 MT/s"
Selection 0x3 , "1600 MT/s"
EndList
List &gPlatformFspPkgTokenSpaceGuid_PcdDIMMDWidth
Selection 0x0 , "x8"
Selection 0x1 , "x16"
Selection 0x2 , "x32"
EndList
List &gPlatformFspPkgTokenSpaceGuid_PcdeMMCBootMode
Selection 0x0 , "Disabled"
Selection 0x1 , "Auto"
Selection 0x2 , "eMMC 4.1"
Selection 0x3 , "eMMC 4.5"
EndList
BeginInfoBlock
PPVer "1.0"
Description "BayTrail platform"
EndInfoBlock
Page "Platform"
Combo $gPlatformFspPkgTokenSpaceGuid_PcdPlatformType, "Platform Type", &gPlatformFspPkgTokenSpaceGuid_PcdPlatformType,
Help "Select Platform Type."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableSecureBoot, "Enable Secure Boot", &gPlatformFspPkgTokenSpaceGuid_PcdEnableSecureBoot,
Help "Enable/disable secure boot. Auto by default."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdOsSelection, "OS Selection", &gPlatformFspPkgTokenSpaceGuid_PcdOsSelection,
Help "Select Operating System"
EndPage
Page "Memory Down"
Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableMemoryDown, "Enable Memory Down", &EN_DIS,
Help "Enable = Memory Down, Disable = DIMM"
Combo $gPlatformFspPkgTokenSpaceGuid_PcdDRAMSpeed, "DRAM Speed", &gPlatformFspPkgTokenSpaceGuid_PcdDRAMSpeed,
Help "DRAM Speed"
Combo $gPlatformFspPkgTokenSpaceGuid_PcdDRAMType, "DRAM Type", &gPlatformFspPkgTokenSpaceGuid_PcdDRAMType,
Help "DRAM Type"
Combo $gPlatformFspPkgTokenSpaceGuid_PcdDIMM0Enable, "DIMM 0 Enable", &EN_DIS,
Help "Please populate DIMM slot 0 if only one DIMM is supported."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdDIMM1Enable, "DIMM 1 Enable", &EN_DIS,
Help "Please populate DIMM slot 1 if only one DIMM is supported."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdDIMMDWidth, "DIMM_DWidth", &gPlatformFspPkgTokenSpaceGuid_PcdDIMMDWidth,
Help "DRAM device data width."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdDIMMDensity, "DIMM_Density", &gPlatformFspPkgTokenSpaceGuid_PcdDIMMDensity,
Help "DRAM device data density."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdDIMMBusWidth, "DIMM_BusWidth", &gPlatformFspPkgTokenSpaceGuid_PcdDIMMBusWidth,
Help "DIMM Bus Width."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdDIMMSides, "DIMM_Sides", &gPlatformFspPkgTokenSpaceGuid_PcdDIMMSides,
Help "Ranks Per DIMM. "
EditNum $gPlatformFspPkgTokenSpaceGuid_PcdDIMMtCL, "tCL", DEC,
Help "tCL"
"Valid range: 1 ~ 255"
EditNum $gPlatformFspPkgTokenSpaceGuid_PcdDIMMtRPtRCD, "tRP_tRCD", DEC,
Help "tRP and tRCD in DRAM clk - 5:12.5ns, 6:15ns, etc."
"Valid range: 1 ~ 255"
EditNum $gPlatformFspPkgTokenSpaceGuid_PcdDIMMtWR, "tWR", DEC,
Help "tWR in DRAM clk"
"Valid range: 1 ~ 255"
EditNum $gPlatformFspPkgTokenSpaceGuid_PcdDIMMtWTR, "tWTR", DEC,
Help "tWTR in DRAM clk"
"Valid range: 1 ~ 255"
EditNum $gPlatformFspPkgTokenSpaceGuid_PcdDIMMtRRD, "tRRD", DEC,
Help "tRRD in DRAM clk"
"Valid range: 1 ~ 255"
EditNum $gPlatformFspPkgTokenSpaceGuid_PcdDIMMtRTP, "tRTP", DEC,
Help "tRTP in DRAM clk"
"Valid range: 1 ~ 255"
EditNum $gPlatformFspPkgTokenSpaceGuid_PcdDIMMtFAW, "tFAW", DEC,
Help "tFAW in DRAM clk"
"Valid range: 1 ~ 255"
EndPage
Page "South Complex"
Combo $gPlatformFspPkgTokenSpaceGuid_PcdeMMCBootMode, "eMMC Boot Mode", &gPlatformFspPkgTokenSpaceGuid_PcdeMMCBootMode,
Help "Select EMMC Mode."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableSdio, "Enable SDIO", &EN_DIS,
Help "Enable/disable SDIO."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableSdcard, "Enable SD Card", &EN_DIS,
Help "Enable/disable SD Card."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableHsuart0, "Enable HSUART0", &EN_DIS,
Help "Enable/disable HSUART0."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableHsuart1, "Enable HSUART1", &EN_DIS,
Help "Enable/disable HSUART1."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableSpi, "Enable SPI", &EN_DIS,
Help "Enable/disable SPI."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableSata, "Enable SATA", &EN_DIS,
Help "Enable/disable SATA controller."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdSataMode, "SATA Mode", &gPlatformFspPkgTokenSpaceGuid_PcdSataMode,
Help "Select SATA controller working mode."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableAzalia, "Enable Azalia", &EN_DIS,
Help "Enable/disable Azalia controller."
EditNum $gPlatformFspPkgTokenSpaceGuid_AzaliaConfigPtr, "Azalia Configuration Pointer", HEX,
Help "Address of the Azalia Configuration Data."
"Valid range: 0x00 ~ 0xFFFFFFFF"
Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableXhci, "Enable XHCI", &EN_DIS,
Help "Enable/disable XHCI controller."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableLpe, "Enable LPE", &gPlatformFspPkgTokenSpaceGuid_PcdEnableLpe,
Help "Choose LPE Mode."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdLpssSioEnablePciMode, "Enable PCI mode for LPSS SIO devices", &EN_DIS,
Help "Enable PCI Mode for LPSS SIO devices. If disabled, LPSS SIO devices will run in ACPI mode."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableDma0, "Enable DMA0", &EN_DIS,
Help "Enable/disable DMA0."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableDma1, "Enable DMA1", &EN_DIS,
Help "Enable/disable DMA1."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C0, "Enable I2C0", &EN_DIS,
Help "Enable/disable I2C0."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C1, "Enable I2C1", &EN_DIS,
Help "Enable/disable I2C1."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C2, "Enable I2C2", &EN_DIS,
Help "Enable/disable I2C2."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C3, "Enable I2C3", &EN_DIS,
Help "Enable/disable I2C3."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C4, "Enable I2C4", &EN_DIS,
Help "Enable/disable I2C4."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C5, "Enable I2C5", &EN_DIS,
Help "Enable/disable I2C5."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C6, "Enable I2C6", &EN_DIS,
Help "Enable/disable I2C6."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnablePwm0, "Enable PWM0", &EN_DIS,
Help "Enable/disable PWM0."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnablePwm1, "Enable PWM1", &EN_DIS,
Help "Enable/disable PWM1."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableHsi, "Enable HSI", &EN_DIS,
Help "Enable/disable HSI."
Combo $gPlatformFspPkgTokenSpaceGuid_ISPEnable, "Enable ISP", &EN_DIS,
Help "Enable/disable ISP."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdSccEnablePciMode, "Enable PCI mode for SCC devices", &EN_DIS,
Help "Enable PCI Mode for SCC devices. If disabled, SCC devices will run in ACPI mode."
Combo $gPlatformFspPkgTokenSpaceGuid_eMMC45DDR50Enabled, "eMMC45 DDR50", &EN_DIS,
Help "Enable eMMC45 DDR50"
Combo $gPlatformFspPkgTokenSpaceGuid_eMMC45HS200Enabled, "eMMC45 HS200", &EN_DIS,
Help "Enable eMMC45 HS200"
EditNum $gPlatformFspPkgTokenSpaceGuid_eMMC45RetuneTimerValue, "eMMC45 Retune Timer Value", DEC,
Help "Select Timer Value"
"Valid range: 0 ~ 15"
EndPage
Page "North Complex"
Combo $gPlatformFspPkgTokenSpaceGuid_PcdMrcInitTsegSize, "Tseg Size", &gPlatformFspPkgTokenSpaceGuid_PcdMrcInitTsegSize,
Help "Size of SMRAM memory reserved."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdMrcInitMmioSize, "MMIO Size", &gPlatformFspPkgTokenSpaceGuid_PcdMrcInitMmioSize,
Help "Size of memory address space reserved for MMIO (Memory Mapped I/O)."
EditNum $gPlatformFspPkgTokenSpaceGuid_PcdMrcInitSPDAddr1, "DIMM 0 SPD SMBus Address", HEX,
Help "SPD Address of DIMM."
"Valid range: 0x00 ~ 0xFF"
EditNum $gPlatformFspPkgTokenSpaceGuid_PcdMrcInitSPDAddr2, "DIMM 1 SPD SMBus Address", HEX,
Help "SPD Address of DIMM."
"Valid range: 0x00 ~ 0xFF"
Combo $gPlatformFspPkgTokenSpaceGuid_TxeUmaEnable, "Enable TXE UMA", &EN_DIS,
Help "Enable/disable Unified Memory Reservation for TXE engine."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdMrcDebugMsg, "MRC RMT Message Display", &EN_DIS,
Help "Enable/disable MRC RMT Message Display."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableIgd, "Enable IGD", &EN_DIS,
Help "Enable/disable internal graphics controller."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdIgdDvmt50PreAlloc, "Internal Graphics Pre-allocated Memory", &gPlatformFspPkgTokenSpaceGuid_PcdIgdDvmt50PreAlloc,
Help "Size of memory preallocated for internal graphics"
Combo $gPlatformFspPkgTokenSpaceGuid_PcdApertureSize, "Aperture Size", &gPlatformFspPkgTokenSpaceGuid_PcdApertureSize,
Help "Select the Aperture Size."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdGttSize, "GTT Size", &gPlatformFspPkgTokenSpaceGuid_PcdGttSize,
Help "Select the GTT Size."
Combo $gPlatformFspPkgTokenSpaceGuid_IgdRenderStandby, "Enable Render Standby", &EN_DIS,
Help "Enable/disable Integrated Graphics Render Standby."
EndPage

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/**@file
Copyright (C) 2013, Intel Corporation
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
**/
#ifndef _AZALIA_H_
#define _AZALIA_H_
#include <stdint.h>
#pragma pack(1)
typedef struct {
uint32_t VendorDeviceId;
uint16_t SubSystemId;
uint8_t RevisionId; /// 0xFF applies to all steppings
uint8_t FrontPanelSupport;
uint16_t NumberOfRearJacks;
uint16_t NumberOfFrontJacks;
} PCH_AZALIA_VERB_TABLE_HEADER;
typedef struct {
PCH_AZALIA_VERB_TABLE_HEADER VerbTableHeader;
uint32_t *VerbTableData;
} PCH_AZALIA_VERB_TABLE;
typedef struct {
uint8_t Pme : 1; /// 0: Disable; 1: Enable
uint8_t DS : 1; /// 0: Docking is not supported; 1:Docking is supported
uint8_t DA : 1; /// 0: Docking is not attached; 1:Docking is attached
uint8_t HdmiCodec : 1; /// 0: Disable; 1: Enable
uint8_t AzaliaVCi : 1; /// 0: Disable; 1: Enable
uint8_t Rsvdbits : 3;
uint8_t AzaliaVerbTableNum; /// Number of verb tables provided by platform
PCH_AZALIA_VERB_TABLE *AzaliaVerbTable; /// Pointer to the actual verb table(s)
uint16_t ResetWaitTimer; /// The delay timer after Azalia reset, the value is number of microseconds
} PCH_AZALIA_CONFIG;
#pragma pack()
#endif

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@ -0,0 +1,69 @@
/**
Copyright (C) 2013, Intel Corporation
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
**/
/** \file fsp.h
*
*
*/
#include <stdint.h>
#include "fsptypes.h"
#include "fspfv.h"
#include "fspffs.h"
#include "fsphob.h"
#include "fspapi.h"
#include "fspplatform.h"
#include "fspinfoheader.h"
#include "fspvpd.h"
#define FSP_HOB_RESOURCE_OWNER_FSP_GUID \
{ 0x69a79759, 0x1373, 0x4367, { 0xa6, 0xc4, 0xc7, 0xf5, 0x9e, 0xfd, 0x98, 0x6e } }
#define FSP_NON_VOLATILE_STORAGE_HOB_GUID \
{ 0x721acf02, 0x4d77, 0x4c2a, { 0xb3, 0xdc, 0x27, 0xb, 0x7b, 0xa9, 0xe4, 0xb0 } }
#define FSP_HOB_RESOURCE_OWNER_TSEG_GUID \
{ 0xd038747c, 0xd00c, 0x4980, { 0xb3, 0x19, 0x49, 0x01, 0x99, 0xa4, 0x7d, 0x55 } }
#define FSP_HOB_RESOURCE_OWNER_GRAPHICS_GUID \
{ 0x9c7c3aa7, 0x5332, 0x4917, { 0x82, 0xb9, 0x56, 0xa5, 0xf3, 0xe6, 0x2a, 0x07 } }
#define FSP_BOOTLOADER_TEMPORARY_MEMORY_HOB_GUID \
{ 0xbbcff46c, 0xc8d3, 0x4113, { 0x89, 0x85, 0xb9, 0xd4, 0xf3, 0xb3, 0xf6, 0x4e } }
//
// 0x21 - 0xf..f are reserved.
//
#define BOOT_WITH_FULL_CONFIGURATION 0x00
#define BOOT_WITH_MINIMAL_CONFIGURATION 0x01
#define BOOT_ASSUMING_NO_CONFIGURATION_CHANGES 0x02
#define BOOT_WITH_FULL_CONFIGURATION_PLUS_DIAGNOSTICS 0x03
#define BOOT_WITH_DEFAULT_SETTINGS 0x04
#define BOOT_ON_S4_RESUME 0x05
#define BOOT_ON_S5_RESUME 0x06
#define BOOT_ON_S2_RESUME 0x10
#define BOOT_ON_S3_RESUME 0x11
#define BOOT_ON_FLASH_UPDATE 0x12
#define BOOT_IN_RECOVERY_MODE 0x20

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/**
Copyright (C) 2013, Intel Corporation
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
**/
#ifndef _FSP_API_H_
#define _FSP_API_H_
#pragma pack(1)
typedef VOID (* CONTINUATION_PROC)(EFI_STATUS Status, VOID *HobListPtr);
typedef struct {
VOID *NvsBufferPtr;
VOID *RtBufferPtr;
CONTINUATION_PROC ContinuationFunc;
} FSP_INIT_PARAMS;
typedef struct {
UINT32 *StackTop;
UINT32 BootMode;
VOID *UpdDataRgnPtr;
UINT32 Reserved[7];
} FSP_INIT_RT_COMMON_BUFFER;
typedef enum {
EnumInitPhaseAfterPciEnumeration = 0x20,
EnumInitPhaseReadyToBoot = 0x40
} FSP_INIT_PHASE;
typedef struct {
FSP_INIT_PHASE Phase;
} NOTIFY_PHASE_PARAMS;
#pragma pack()
typedef FSP_STATUS (FSPAPI *FSP_FSP_INIT) (FSP_INIT_PARAMS *FspInitParamPtr);
typedef FSP_STATUS (FSPAPI *FSP_NOTFY_PHASE) (NOTIFY_PHASE_PARAMS *NotifyPhaseParamPtr);
#endif

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/**
Copyright (C) 2013, Intel Corporation
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
**/
#ifndef __PI_FIRMWARE_FILE_H__
#define __PI_FIRMWARE_FILE_H__
#pragma pack(1)
///
/// Used to verify the integrity of the file.
///
typedef union {
struct {
///
/// The IntegrityCheck.Checksum.Header field is an 8-bit checksum of the file
/// header. The State and IntegrityCheck.Checksum.File fields are assumed
/// to be zero and the checksum is calculated such that the entire header sums to zero.
///
UINT8 Header;
///
/// If the FFS_ATTRIB_CHECKSUM (see definition below) bit of the Attributes
/// field is set to one, the IntegrityCheck.Checksum.File field is an 8-bit
/// checksum of the file data.
/// If the FFS_ATTRIB_CHECKSUM bit of the Attributes field is cleared to zero,
/// the IntegrityCheck.Checksum.File field must be initialized with a value of
/// 0xAA. The IntegrityCheck.Checksum.File field is valid any time the
/// EFI_FILE_DATA_VALID bit is set in the State field.
///
UINT8 File;
} Checksum;
///
/// This is the full 16 bits of the IntegrityCheck field.
///
UINT16 Checksum16;
} EFI_FFS_INTEGRITY_CHECK;
///
/// FFS_FIXED_CHECKSUM is the checksum value used when the
/// FFS_ATTRIB_CHECKSUM attribute bit is clear.
///
#define FFS_FIXED_CHECKSUM 0xAA
typedef UINT8 EFI_FV_FILETYPE;
typedef UINT8 EFI_FFS_FILE_ATTRIBUTES;
typedef UINT8 EFI_FFS_FILE_STATE;
///
/// File Types Definitions
///
#define EFI_FV_FILETYPE_ALL 0x00
#define EFI_FV_FILETYPE_RAW 0x01
#define EFI_FV_FILETYPE_FREEFORM 0x02
#define EFI_FV_FILETYPE_SECURITY_CORE 0x03
#define EFI_FV_FILETYPE_PEI_CORE 0x04
#define EFI_FV_FILETYPE_DXE_CORE 0x05
#define EFI_FV_FILETYPE_PEIM 0x06
#define EFI_FV_FILETYPE_DRIVER 0x07
#define EFI_FV_FILETYPE_COMBINED_PEIM_DRIVER 0x08
#define EFI_FV_FILETYPE_APPLICATION 0x09
#define EFI_FV_FILETYPE_SMM 0x0A
#define EFI_FV_FILETYPE_FIRMWARE_VOLUME_IMAGE 0x0B
#define EFI_FV_FILETYPE_COMBINED_SMM_DXE 0x0C
#define EFI_FV_FILETYPE_SMM_CORE 0x0D
#define EFI_FV_FILETYPE_OEM_MIN 0xc0
#define EFI_FV_FILETYPE_OEM_MAX 0xdf
#define EFI_FV_FILETYPE_DEBUG_MIN 0xe0
#define EFI_FV_FILETYPE_DEBUG_MAX 0xef
#define EFI_FV_FILETYPE_FFS_MIN 0xf0
#define EFI_FV_FILETYPE_FFS_MAX 0xff
#define EFI_FV_FILETYPE_FFS_PAD 0xf0
///
/// FFS File Attributes.
///
#define FFS_ATTRIB_LARGE_FILE 0x01
#define FFS_ATTRIB_FIXED 0x04
#define FFS_ATTRIB_DATA_ALIGNMENT 0x38
#define FFS_ATTRIB_CHECKSUM 0x40
///
/// FFS File State Bits.
///
#define EFI_FILE_HEADER_CONSTRUCTION 0x01
#define EFI_FILE_HEADER_VALID 0x02
#define EFI_FILE_DATA_VALID 0x04
#define EFI_FILE_MARKED_FOR_UPDATE 0x08
#define EFI_FILE_DELETED 0x10
#define EFI_FILE_HEADER_INVALID 0x20
///
/// Each file begins with the header that describe the
/// contents and state of the files.
///
typedef struct {
///
/// This GUID is the file name. It is used to uniquely identify the file.
///
EFI_GUID Name;
///
/// Used to verify the integrity of the file.
///
EFI_FFS_INTEGRITY_CHECK IntegrityCheck;
///
/// Identifies the type of file.
///
EFI_FV_FILETYPE Type;
///
/// Declares various file attribute bits.
///
EFI_FFS_FILE_ATTRIBUTES Attributes;
///
/// The length of the file in bytes, including the FFS header.
///
UINT8 Size[3];
///
/// Used to track the state of the file throughout the life of the file from creation to deletion.
///
EFI_FFS_FILE_STATE State;
} EFI_FFS_FILE_HEADER;
typedef struct {
///
/// This GUID is the file name. It is used to uniquely identify the file. There may be only
/// one instance of a file with the file name GUID of Name in any given firmware
/// volume, except if the file type is EFI_FV_FILETYPE_FFS_PAD.
///
EFI_GUID Name;
///
/// Used to verify the integrity of the file.
///
EFI_FFS_INTEGRITY_CHECK IntegrityCheck;
///
/// Identifies the type of file.
///
EFI_FV_FILETYPE Type;
///
/// Declares various file attribute bits.
///
EFI_FFS_FILE_ATTRIBUTES Attributes;
///
/// The length of the file in bytes, including the FFS header.
/// The length of the file data is either (Size - sizeof(EFI_FFS_FILE_HEADER)). This calculation means a
/// zero-length file has a Size of 24 bytes, which is sizeof(EFI_FFS_FILE_HEADER).
/// Size is not required to be a multiple of 8 bytes. Given a file F, the next file header is
/// located at the next 8-byte aligned firmware volume offset following the last byte of the file F.
///
UINT8 Size[3];
///
/// Used to track the state of the file throughout the life of the file from creation to deletion.
///
EFI_FFS_FILE_STATE State;
///
/// If FFS_ATTRIB_LARGE_FILE is set in Attributes, then ExtendedSize exists and Size must be set to zero.
/// If FFS_ATTRIB_LARGE_FILE is not set then EFI_FFS_FILE_HEADER is used.
///
UINT32 ExtendedSize;
} EFI_FFS_FILE_HEADER2;
#define IS_FFS_FILE2(FfsFileHeaderPtr) \
(((((EFI_FFS_FILE_HEADER *) (UINTN) FfsFileHeaderPtr)->Attributes) & FFS_ATTRIB_LARGE_FILE) == FFS_ATTRIB_LARGE_FILE)
#define FFS_FILE_SIZE(FfsFileHeaderPtr) \
((UINT32) (*((UINT32 *) ((EFI_FFS_FILE_HEADER *) (UINTN) FfsFileHeaderPtr)->Size) & 0x00ffffff))
#define FFS_FILE2_SIZE(FfsFileHeaderPtr) \
(((EFI_FFS_FILE_HEADER2 *) (UINTN) FfsFileHeaderPtr)->ExtendedSize)
typedef UINT8 EFI_SECTION_TYPE;
///
/// Pseudo type. It is used as a wild card when retrieving sections.
/// The section type EFI_SECTION_ALL matches all section types.
///
#define EFI_SECTION_ALL 0x00
///
/// Encapsulation section Type values.
///
#define EFI_SECTION_COMPRESSION 0x01
#define EFI_SECTION_GUID_DEFINED 0x02
#define EFI_SECTION_DISPOSABLE 0x03
///
/// Leaf section Type values.
///
#define EFI_SECTION_PE32 0x10
#define EFI_SECTION_PIC 0x11
#define EFI_SECTION_TE 0x12
#define EFI_SECTION_DXE_DEPEX 0x13
#define EFI_SECTION_VERSION 0x14
#define EFI_SECTION_USER_INTERFACE 0x15
#define EFI_SECTION_COMPATIBILITY16 0x16
#define EFI_SECTION_FIRMWARE_VOLUME_IMAGE 0x17
#define EFI_SECTION_FREEFORM_SUBTYPE_GUID 0x18
#define EFI_SECTION_RAW 0x19
#define EFI_SECTION_PEI_DEPEX 0x1B
#define EFI_SECTION_SMM_DEPEX 0x1C
///
/// Common section header.
///
typedef struct {
///
/// A 24-bit unsigned integer that contains the total size of the section in bytes,
/// including the EFI_COMMON_SECTION_HEADER.
///
UINT8 Size[3];
EFI_SECTION_TYPE Type;
///
/// Declares the section type.
///
} EFI_COMMON_SECTION_HEADER;
typedef struct {
///
/// A 24-bit unsigned integer that contains the total size of the section in bytes,
/// including the EFI_COMMON_SECTION_HEADER.
///
UINT8 Size[3];
EFI_SECTION_TYPE Type;
///
/// If Size is 0xFFFFFF, then ExtendedSize contains the size of the section. If
/// Size is not equal to 0xFFFFFF, then this field does not exist.
///
UINT32 ExtendedSize;
} EFI_COMMON_SECTION_HEADER2;
///
/// Leaf section type that contains an
/// IA-32 16-bit executable image.
///
typedef EFI_COMMON_SECTION_HEADER EFI_COMPATIBILITY16_SECTION;
typedef EFI_COMMON_SECTION_HEADER2 EFI_COMPATIBILITY16_SECTION2;
///
/// CompressionType of EFI_COMPRESSION_SECTION.
///
#define EFI_NOT_COMPRESSED 0x00
#define EFI_STANDARD_COMPRESSION 0x01
///
/// An encapsulation section type in which the
/// section data is compressed.
///
typedef struct {
///
/// Usual common section header. CommonHeader.Type = EFI_SECTION_COMPRESSION.
///
EFI_COMMON_SECTION_HEADER CommonHeader;
///
/// The UINT32 that indicates the size of the section data after decompression.
///
UINT32 UncompressedLength;
///
/// Indicates which compression algorithm is used.
///
UINT8 CompressionType;
} EFI_COMPRESSION_SECTION;
typedef struct {
///
/// Usual common section header. CommonHeader.Type = EFI_SECTION_COMPRESSION.
///
EFI_COMMON_SECTION_HEADER2 CommonHeader;
///
/// UINT32 that indicates the size of the section data after decompression.
///
UINT32 UncompressedLength;
///
/// Indicates which compression algorithm is used.
///
UINT8 CompressionType;
} EFI_COMPRESSION_SECTION2;
///
/// An encapsulation section type in which the section data is disposable.
/// A disposable section is an encapsulation section in which the section data may be disposed of during
/// the process of creating or updating a firmware image without significant impact on the usefulness of
/// the file. The Type field in the section header is set to EFI_SECTION_DISPOSABLE. This
/// allows optional or descriptive data to be included with the firmware file which can be removed in
/// order to conserve space. The contents of this section are implementation specific, but might contain
/// debug data or detailed integration instructions.
///
typedef EFI_COMMON_SECTION_HEADER EFI_DISPOSABLE_SECTION;
typedef EFI_COMMON_SECTION_HEADER2 EFI_DISPOSABLE_SECTION2;
///
/// The leaf section which could be used to determine the dispatch order of DXEs.
///
typedef EFI_COMMON_SECTION_HEADER EFI_DXE_DEPEX_SECTION;
typedef EFI_COMMON_SECTION_HEADER2 EFI_DXE_DEPEX_SECTION2;
///
/// The leaf section which contains a PI FV.
///
typedef EFI_COMMON_SECTION_HEADER EFI_FIRMWARE_VOLUME_IMAGE_SECTION;
typedef EFI_COMMON_SECTION_HEADER2 EFI_FIRMWARE_VOLUME_IMAGE_SECTION2;
///
/// The leaf section which contains a single GUID.
///
typedef struct {
///
/// Common section header. CommonHeader.Type = EFI_SECTION_FREEFORM_SUBTYPE_GUID.
///
EFI_COMMON_SECTION_HEADER CommonHeader;
///
/// This GUID is defined by the creator of the file. It is a vendor-defined file type.
///
EFI_GUID SubTypeGuid;
} EFI_FREEFORM_SUBTYPE_GUID_SECTION;
typedef struct {
///
/// The common section header. CommonHeader.Type = EFI_SECTION_FREEFORM_SUBTYPE_GUID.
///
EFI_COMMON_SECTION_HEADER2 CommonHeader;
///
/// This GUID is defined by the creator of the file. It is a vendor-defined file type.
///
EFI_GUID SubTypeGuid;
} EFI_FREEFORM_SUBTYPE_GUID_SECTION2;
///
/// Attributes of EFI_GUID_DEFINED_SECTION.
///
#define EFI_GUIDED_SECTION_PROCESSING_REQUIRED 0x01
#define EFI_GUIDED_SECTION_AUTH_STATUS_VALID 0x02
///
/// The leaf section which is encapsulation defined by specific GUID.
///
typedef struct {
///
/// The common section header. CommonHeader.Type = EFI_SECTION_GUID_DEFINED.
///
EFI_COMMON_SECTION_HEADER CommonHeader;
///
/// The GUID that defines the format of the data that follows. It is a vendor-defined section type.
///
EFI_GUID SectionDefinitionGuid;
///
/// Contains the offset in bytes from the beginning of the common header to the first byte of the data.
///
UINT16 DataOffset;
///
/// The bit field that declares some specific characteristics of the section contents.
///
UINT16 Attributes;
} EFI_GUID_DEFINED_SECTION;
typedef struct {
///
/// The common section header. CommonHeader.Type = EFI_SECTION_GUID_DEFINED.
///
EFI_COMMON_SECTION_HEADER2 CommonHeader;
///
/// The GUID that defines the format of the data that follows. It is a vendor-defined section type.
///
EFI_GUID SectionDefinitionGuid;
///
/// Contains the offset in bytes from the beginning of the common header to the first byte of the data.
///
UINT16 DataOffset;
///
/// The bit field that declares some specific characteristics of the section contents.
///
UINT16 Attributes;
} EFI_GUID_DEFINED_SECTION2;
///
/// The leaf section which contains PE32+ image.
///
typedef EFI_COMMON_SECTION_HEADER EFI_PE32_SECTION;
typedef EFI_COMMON_SECTION_HEADER2 EFI_PE32_SECTION2;
///
/// The leaf section used to determine the dispatch order of PEIMs.
///
typedef EFI_COMMON_SECTION_HEADER EFI_PEI_DEPEX_SECTION;
typedef EFI_COMMON_SECTION_HEADER2 EFI_PEI_DEPEX_SECTION2;
///
/// A leaf section type that contains a position-independent-code (PIC) image.
/// A PIC image section is a leaf section that contains a position-independent-code (PIC) image.
/// In addition to normal PE32+ images that contain relocation information, PEIM executables may be
/// PIC and are referred to as PIC images. A PIC image is the same as a PE32+ image except that all
/// relocation information has been stripped from the image and the image can be moved and will
/// execute correctly without performing any relocation or other fix-ups. EFI_PIC_SECTION2 must
/// be used if the section is 16MB or larger.
///
typedef EFI_COMMON_SECTION_HEADER EFI_PIC_SECTION;
typedef EFI_COMMON_SECTION_HEADER2 EFI_PIC_SECTION2;
///
/// The leaf section which constains the position-independent-code image.
///
typedef EFI_COMMON_SECTION_HEADER EFI_TE_SECTION;
typedef EFI_COMMON_SECTION_HEADER2 EFI_TE_SECTION2;
///
/// The leaf section which contains an array of zero or more bytes.
///
typedef EFI_COMMON_SECTION_HEADER EFI_RAW_SECTION;
typedef EFI_COMMON_SECTION_HEADER2 EFI_RAW_SECTION2;
///
/// The SMM dependency expression section is a leaf section that contains a dependency expression that
/// is used to determine the dispatch order for SMM drivers. Before the SMRAM invocation of the
/// SMM driver's entry point, this dependency expression must evaluate to TRUE. See the Platform
/// Initialization Specification, Volume 2, for details regarding the format of the dependency expression.
/// The dependency expression may refer to protocols installed in either the UEFI or the SMM protocol
/// database. EFI_SMM_DEPEX_SECTION2 must be used if the section is 16MB or larger.
///
typedef EFI_COMMON_SECTION_HEADER EFI_SMM_DEPEX_SECTION;
typedef EFI_COMMON_SECTION_HEADER2 EFI_SMM_DEPEX_SECTION2;
///
/// The leaf section which contains a unicode string that
/// is human readable file name.
///
typedef struct {
EFI_COMMON_SECTION_HEADER CommonHeader;
///
/// Array of unicode string.
///
CHAR16 FileNameString[1];
} EFI_USER_INTERFACE_SECTION;
typedef struct {
EFI_COMMON_SECTION_HEADER2 CommonHeader;
CHAR16 FileNameString[1];
} EFI_USER_INTERFACE_SECTION2;
///
/// The leaf section which contains a numeric build number and
/// an optional unicode string that represents the file revision.
///
typedef struct {
EFI_COMMON_SECTION_HEADER CommonHeader;
UINT16 BuildNumber;
///
/// Array of unicode string.
///
CHAR16 VersionString[1];
} EFI_VERSION_SECTION;
typedef struct {
EFI_COMMON_SECTION_HEADER2 CommonHeader;
///
/// A UINT16 that represents a particular build. Subsequent builds have monotonically
/// increasing build numbers relative to earlier builds.
///
UINT16 BuildNumber;
CHAR16 VersionString[1];
} EFI_VERSION_SECTION2;
#define IS_SECTION2(SectionHeaderPtr) \
((UINT32) (*((UINT32 *) ((EFI_COMMON_SECTION_HEADER *) (UINTN) SectionHeaderPtr)->Size) & 0x00ffffff) == 0x00ffffff)
#define SECTION_SIZE(SectionHeaderPtr) \
((UINT32) (*((UINT32 *) ((EFI_COMMON_SECTION_HEADER *) (UINTN) SectionHeaderPtr)->Size) & 0x00ffffff))
#define SECTION2_SIZE(SectionHeaderPtr) \
(((EFI_COMMON_SECTION_HEADER2 *) (UINTN) SectionHeaderPtr)->ExtendedSize)
#pragma pack()
#endif

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/**
Copyright (C) 2013, Intel Corporation
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
**/
#ifndef __PI_FIRMWAREVOLUME_H__
#define __PI_FIRMWAREVOLUME_H__
///
/// EFI_FV_FILE_ATTRIBUTES
///
typedef UINT32 EFI_FV_FILE_ATTRIBUTES;
//
// Value of EFI_FV_FILE_ATTRIBUTES.
//
#define EFI_FV_FILE_ATTRIB_ALIGNMENT 0x0000001F
#define EFI_FV_FILE_ATTRIB_FIXED 0x00000100
#define EFI_FV_FILE_ATTRIB_MEMORY_MAPPED 0x00000200
///
/// type of EFI FVB attribute
///
typedef UINT32 EFI_FVB_ATTRIBUTES_2;
//
// Attributes bit definitions
//
#define EFI_FVB2_READ_DISABLED_CAP 0x00000001
#define EFI_FVB2_READ_ENABLED_CAP 0x00000002
#define EFI_FVB2_READ_STATUS 0x00000004
#define EFI_FVB2_WRITE_DISABLED_CAP 0x00000008
#define EFI_FVB2_WRITE_ENABLED_CAP 0x00000010
#define EFI_FVB2_WRITE_STATUS 0x00000020
#define EFI_FVB2_LOCK_CAP 0x00000040
#define EFI_FVB2_LOCK_STATUS 0x00000080
#define EFI_FVB2_STICKY_WRITE 0x00000200
#define EFI_FVB2_MEMORY_MAPPED 0x00000400
#define EFI_FVB2_ERASE_POLARITY 0x00000800
#define EFI_FVB2_READ_LOCK_CAP 0x00001000
#define EFI_FVB2_READ_LOCK_STATUS 0x00002000
#define EFI_FVB2_WRITE_LOCK_CAP 0x00004000
#define EFI_FVB2_WRITE_LOCK_STATUS 0x00008000
#define EFI_FVB2_ALIGNMENT 0x001F0000
#define EFI_FVB2_ALIGNMENT_1 0x00000000
#define EFI_FVB2_ALIGNMENT_2 0x00010000
#define EFI_FVB2_ALIGNMENT_4 0x00020000
#define EFI_FVB2_ALIGNMENT_8 0x00030000
#define EFI_FVB2_ALIGNMENT_16 0x00040000
#define EFI_FVB2_ALIGNMENT_32 0x00050000
#define EFI_FVB2_ALIGNMENT_64 0x00060000
#define EFI_FVB2_ALIGNMENT_128 0x00070000
#define EFI_FVB2_ALIGNMENT_256 0x00080000
#define EFI_FVB2_ALIGNMENT_512 0x00090000
#define EFI_FVB2_ALIGNMENT_1K 0x000A0000
#define EFI_FVB2_ALIGNMENT_2K 0x000B0000
#define EFI_FVB2_ALIGNMENT_4K 0x000C0000
#define EFI_FVB2_ALIGNMENT_8K 0x000D0000
#define EFI_FVB2_ALIGNMENT_16K 0x000E0000
#define EFI_FVB2_ALIGNMENT_32K 0x000F0000
#define EFI_FVB2_ALIGNMENT_64K 0x00100000
#define EFI_FVB2_ALIGNMENT_128K 0x00110000
#define EFI_FVB2_ALIGNMENT_256K 0x00120000
#define EFI_FVB2_ALIGNMENT_512K 0x00130000
#define EFI_FVB2_ALIGNMENT_1M 0x00140000
#define EFI_FVB2_ALIGNMENT_2M 0x00150000
#define EFI_FVB2_ALIGNMENT_4M 0x00160000
#define EFI_FVB2_ALIGNMENT_8M 0x00170000
#define EFI_FVB2_ALIGNMENT_16M 0x00180000
#define EFI_FVB2_ALIGNMENT_32M 0x00190000
#define EFI_FVB2_ALIGNMENT_64M 0x001A0000
#define EFI_FVB2_ALIGNMENT_128M 0x001B0000
#define EFI_FVB2_ALIGNMENT_256M 0x001C0000
#define EFI_FVB2_ALIGNMENT_512M 0x001D0000
#define EFI_FVB2_ALIGNMENT_1G 0x001E0000
#define EFI_FVB2_ALIGNMENT_2G 0x001F0000
typedef struct {
///
/// The number of sequential blocks which are of the same size.
///
UINT32 NumBlocks;
///
/// The size of the blocks.
///
UINT32 Length;
} EFI_FV_BLOCK_MAP_ENTRY;
///
/// Describes the features and layout of the firmware volume.
///
typedef struct {
///
/// The first 16 bytes are reserved to allow for the reset vector of
/// processors whose reset vector is at address 0.
///
UINT8 ZeroVector[16];
///
/// Declares the file system with which the firmware volume is formatted.
///
EFI_GUID FileSystemGuid;
///
/// Length in bytes of the complete firmware volume, including the header.
///
UINT64 FvLength;
///
/// Set to EFI_FVH_SIGNATURE
///
UINT32 Signature;
///
/// Declares capabilities and power-on defaults for the firmware volume.
///
EFI_FVB_ATTRIBUTES_2 Attributes;
///
/// Length in bytes of the complete firmware volume header.
///
UINT16 HeaderLength;
///
/// A 16-bit checksum of the firmware volume header. A valid header sums to zero.
///
UINT16 Checksum;
///
/// Offset, relative to the start of the header, of the extended header
/// (EFI_FIRMWARE_VOLUME_EXT_HEADER) or zero if there is no extended header.
///
UINT16 ExtHeaderOffset;
///
/// This field must always be set to zero.
///
UINT8 Reserved[1];
///
/// Set to 2. Future versions of this specification may define new header fields and will
/// increment the Revision field accordingly.
///
UINT8 Revision;
///
/// An array of run-length encoded FvBlockMapEntry structures. The array is
/// terminated with an entry of {0,0}.
///
EFI_FV_BLOCK_MAP_ENTRY BlockMap[1];
} EFI_FIRMWARE_VOLUME_HEADER;
#define EFI_FVH_SIGNATURE SIGNATURE_32 ('_', 'F', 'V', 'H')
///
/// Firmware Volume Header Revision definition
///
#define EFI_FVH_REVISION 0x02
///
/// Extension header pointed by ExtHeaderOffset of volume header.
///
typedef struct {
///
/// Firmware volume name.
///
EFI_GUID FvName;
///
/// Size of the rest of the extension header, including this structure.
///
UINT32 ExtHeaderSize;
} EFI_FIRMWARE_VOLUME_EXT_HEADER;
///
/// Entry struture for describing FV extension header
///
typedef struct {
///
/// Size of this header extension.
///
UINT16 ExtEntrySize;
///
/// Type of the header.
///
UINT16 ExtEntryType;
} EFI_FIRMWARE_VOLUME_EXT_ENTRY;
#define EFI_FV_EXT_TYPE_OEM_TYPE 0x01
///
/// This extension header provides a mapping between a GUID and an OEM file type.
///
typedef struct {
///
/// Standard extension entry, with the type EFI_FV_EXT_TYPE_OEM_TYPE.
///
EFI_FIRMWARE_VOLUME_EXT_ENTRY Hdr;
///
/// A bit mask, one bit for each file type between 0xC0 (bit 0) and 0xDF (bit 31). If a bit
/// is '1', then the GUID entry exists in Types. If a bit is '0' then no GUID entry exists in Types.
///
UINT32 TypeMask;
///
/// An array of GUIDs, each GUID representing an OEM file type.
///
/// EFI_GUID Types[1];
///
} EFI_FIRMWARE_VOLUME_EXT_ENTRY_OEM_TYPE;
#define EFI_FV_EXT_TYPE_GUID_TYPE 0x0002
///
/// This extension header EFI_FIRMWARE_VOLUME_EXT_ENTRY_GUID_TYPE provides a vendor specific
/// GUID FormatType type which includes a length and a successive series of data bytes.
///
typedef struct {
///
/// Standard extension entry, with the type EFI_FV_EXT_TYPE_OEM_TYPE.
///
EFI_FIRMWARE_VOLUME_EXT_ENTRY Hdr;
///
/// Vendor-specific GUID.
///
EFI_GUID FormatType;
///
/// An arry of bytes of length Length.
///
/// UINT8 Data[1];
///
} EFI_FIRMWARE_VOLUME_EXT_ENTRY_GUID_TYPE;
#endif

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/**
Copyright (C) 2013, Intel Corporation
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
**/
#ifndef __PI_HOB_H__
#define __PI_HOB_H__
//
// HobType of EFI_HOB_GENERIC_HEADER.
//
#define EFI_HOB_TYPE_MEMORY_ALLOCATION 0x0002
#define EFI_HOB_TYPE_RESOURCE_DESCRIPTOR 0x0003
#define EFI_HOB_TYPE_GUID_EXTENSION 0x0004
#define EFI_HOB_TYPE_UNUSED 0xFFFE
#define EFI_HOB_TYPE_END_OF_HOB_LIST 0xFFFF
///
/// Describes the format and size of the data inside the HOB.
/// All HOBs must contain this generic HOB header.
///
typedef struct {
///
/// Identifies the HOB data structure type.
///
UINT16 HobType;
///
/// The length in bytes of the HOB.
///
UINT16 HobLength;
///
/// This field must always be set to zero.
///
UINT32 Reserved;
} EFI_HOB_GENERIC_HEADER;
///
/// Enumeration of memory types introduced in UEFI.
///
typedef enum {
///
/// Not used.
///
EfiReservedMemoryType,
///
/// The code portions of a loaded application.
/// (Note that UEFI OS loaders are UEFI applications.)
///
EfiLoaderCode,
///
/// The data portions of a loaded application and the default data allocation
/// type used by an application to allocate pool memory.
///
EfiLoaderData,
///
/// The code portions of a loaded Boot Services Driver.
///
EfiBootServicesCode,
///
/// The data portions of a loaded Boot Serves Driver, and the default data
/// allocation type used by a Boot Services Driver to allocate pool memory.
///
EfiBootServicesData,
///
/// The code portions of a loaded Runtime Services Driver.
///
EfiRuntimeServicesCode,
///
/// The data portions of a loaded Runtime Services Driver and the default
/// data allocation type used by a Runtime Services Driver to allocate pool memory.
///
EfiRuntimeServicesData,
///
/// Free (unallocated) memory.
///
EfiConventionalMemory,
///
/// Memory in which errors have been detected.
///
EfiUnusableMemory,
///
/// Memory that holds the ACPI tables.
///
EfiACPIReclaimMemory,
///
/// Address space reserved for use by the firmware.
///
EfiACPIMemoryNVS,
///
/// Used by system firmware to request that a memory-mapped IO region
/// be mapped by the OS to a virtual address so it can be accessed by EFI runtime services.
///
EfiMemoryMappedIO,
///
/// System memory-mapped IO region that is used to translate memory
/// cycles to IO cycles by the processor.
///
EfiMemoryMappedIOPortSpace,
///
/// Address space reserved by the firmware for code that is part of the processor.
///
EfiPalCode,
EfiMaxMemoryType
} EFI_MEMORY_TYPE;
///
/// EFI_HOB_MEMORY_ALLOCATION_HEADER describes the
/// various attributes of the logical memory allocation. The type field will be used for
/// subsequent inclusion in the UEFI memory map.
///
typedef struct {
///
/// A GUID that defines the memory allocation region's type and purpose, as well as
/// other fields within the memory allocation HOB. This GUID is used to define the
/// additional data within the HOB that may be present for the memory allocation HOB.
/// Type EFI_GUID is defined in InstallProtocolInterface() in the UEFI 2.0
/// specification.
///
EFI_GUID Name;
///
/// The base address of memory allocated by this HOB. Type
/// EFI_PHYSICAL_ADDRESS is defined in AllocatePages() in the UEFI 2.0
/// specification.
///
EFI_PHYSICAL_ADDRESS MemoryBaseAddress;
///
/// The length in bytes of memory allocated by this HOB.
///
UINT64 MemoryLength;
///
/// Defines the type of memory allocated by this HOB. The memory type definition
/// follows the EFI_MEMORY_TYPE definition. Type EFI_MEMORY_TYPE is defined
/// in AllocatePages() in the UEFI 2.0 specification.
///
EFI_MEMORY_TYPE MemoryType;
///
/// Padding for Itanium processor family
///
UINT8 Reserved[4];
} EFI_HOB_MEMORY_ALLOCATION_HEADER;
///
/// Describes all memory ranges used during the HOB producer
/// phase that exist outside the HOB list. This HOB type
/// describes how memory is used, not the physical attributes of memory.
///
typedef struct {
///
/// The HOB generic header. Header.HobType = EFI_HOB_TYPE_MEMORY_ALLOCATION.
///
EFI_HOB_GENERIC_HEADER Header;
///
/// An instance of the EFI_HOB_MEMORY_ALLOCATION_HEADER that describes the
/// various attributes of the logical memory allocation.
///
EFI_HOB_MEMORY_ALLOCATION_HEADER AllocDescriptor;
//
// Additional data pertaining to the "Name" Guid memory
// may go here.
//
} EFI_HOB_MEMORY_ALLOCATION;
///
/// The resource type.
///
typedef UINT32 EFI_RESOURCE_TYPE;
//
// Value of ResourceType in EFI_HOB_RESOURCE_DESCRIPTOR.
//
#define EFI_RESOURCE_SYSTEM_MEMORY 0x00000000
#define EFI_RESOURCE_MEMORY_MAPPED_IO 0x00000001
#define EFI_RESOURCE_IO 0x00000002
#define EFI_RESOURCE_FIRMWARE_DEVICE 0x00000003
#define EFI_RESOURCE_MEMORY_MAPPED_IO_PORT 0x00000004
#define EFI_RESOURCE_MEMORY_RESERVED 0x00000005
#define EFI_RESOURCE_IO_RESERVED 0x00000006
#define EFI_RESOURCE_MAX_MEMORY_TYPE 0x00000007
///
/// A type of recount attribute type.
///
typedef UINT32 EFI_RESOURCE_ATTRIBUTE_TYPE;
//
// These types can be ORed together as needed.
//
// The first three enumerations describe settings
//
#define EFI_RESOURCE_ATTRIBUTE_PRESENT 0x00000001
#define EFI_RESOURCE_ATTRIBUTE_INITIALIZED 0x00000002
#define EFI_RESOURCE_ATTRIBUTE_TESTED 0x00000004
//
// The rest of the settings describe capabilities
//
#define EFI_RESOURCE_ATTRIBUTE_SINGLE_BIT_ECC 0x00000008
#define EFI_RESOURCE_ATTRIBUTE_MULTIPLE_BIT_ECC 0x00000010
#define EFI_RESOURCE_ATTRIBUTE_ECC_RESERVED_1 0x00000020
#define EFI_RESOURCE_ATTRIBUTE_ECC_RESERVED_2 0x00000040
#define EFI_RESOURCE_ATTRIBUTE_READ_PROTECTED 0x00000080
#define EFI_RESOURCE_ATTRIBUTE_WRITE_PROTECTED 0x00000100
#define EFI_RESOURCE_ATTRIBUTE_EXECUTION_PROTECTED 0x00000200
#define EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE 0x00000400
#define EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE 0x00000800
#define EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE 0x00001000
#define EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE 0x00002000
#define EFI_RESOURCE_ATTRIBUTE_16_BIT_IO 0x00004000
#define EFI_RESOURCE_ATTRIBUTE_32_BIT_IO 0x00008000
#define EFI_RESOURCE_ATTRIBUTE_64_BIT_IO 0x00010000
#define EFI_RESOURCE_ATTRIBUTE_UNCACHED_EXPORTED 0x00020000
///
/// Describes the resource properties of all fixed,
/// nonrelocatable resource ranges found on the processor
/// host bus during the HOB producer phase.
///
typedef struct {
///
/// The HOB generic header. Header.HobType = EFI_HOB_TYPE_RESOURCE_DESCRIPTOR.
///
EFI_HOB_GENERIC_HEADER Header;
///
/// A GUID representing the owner of the resource. This GUID is used by HOB
/// consumer phase components to correlate device ownership of a resource.
///
EFI_GUID Owner;
///
/// The resource type enumeration as defined by EFI_RESOURCE_TYPE.
///
EFI_RESOURCE_TYPE ResourceType;
///
/// Resource attributes as defined by EFI_RESOURCE_ATTRIBUTE_TYPE.
///
EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttribute;
///
/// The physical start address of the resource region.
///
EFI_PHYSICAL_ADDRESS PhysicalStart;
///
/// The number of bytes of the resource region.
///
UINT64 ResourceLength;
} EFI_HOB_RESOURCE_DESCRIPTOR;
///
/// Allows writers of executable content in the HOB producer phase to
/// maintain and manage HOBs with specific GUID.
///
typedef struct {
///
/// The HOB generic header. Header.HobType = EFI_HOB_TYPE_GUID_EXTENSION.
///
EFI_HOB_GENERIC_HEADER Header;
///
/// A GUID that defines the contents of this HOB.
///
EFI_GUID Name;
//
// Guid specific data goes here
//
} EFI_HOB_GUID_TYPE;
///
/// Union of all the possible HOB Types.
///
typedef union {
EFI_HOB_GENERIC_HEADER *Header;
EFI_HOB_MEMORY_ALLOCATION *MemoryAllocation;
EFI_HOB_RESOURCE_DESCRIPTOR *ResourceDescriptor;
EFI_HOB_GUID_TYPE *Guid;
UINT8 *Raw;
} EFI_PEI_HOB_POINTERS;
/**
Returns the type of a HOB.
This macro returns the HobType field from the HOB header for the
HOB specified by HobStart.
@param HobStart A pointer to a HOB.
@return HobType.
**/
#define GET_HOB_TYPE(HobStart) \
((*(EFI_HOB_GENERIC_HEADER **)&(HobStart))->HobType)
/**
Returns the length, in bytes, of a HOB.
This macro returns the HobLength field from the HOB header for the
HOB specified by HobStart.
@param HobStart A pointer to a HOB.
@return HobLength.
**/
#define GET_HOB_LENGTH(HobStart) \
((*(EFI_HOB_GENERIC_HEADER **)&(HobStart))->HobLength)
/**
Returns a pointer to the next HOB in the HOB list.
This macro returns a pointer to HOB that follows the
HOB specified by HobStart in the HOB List.
@param HobStart A pointer to a HOB.
@return A pointer to the next HOB in the HOB list.
**/
#define GET_NEXT_HOB(HobStart) \
(VOID *)(*(UINT8 **)&(HobStart) + GET_HOB_LENGTH (HobStart))
/**
Determines if a HOB is the last HOB in the HOB list.
This macro determine if the HOB specified by HobStart is the
last HOB in the HOB list. If HobStart is last HOB in the HOB list,
then TRUE is returned. Otherwise, FALSE is returned.
@param HobStart A pointer to a HOB.
@retval TRUE The HOB specified by HobStart is the last HOB in the HOB list.
@retval FALSE The HOB specified by HobStart is not the last HOB in the HOB list.
**/
#define END_OF_HOB_LIST(HobStart) (GET_HOB_TYPE (HobStart) == (UINT16)EFI_HOB_TYPE_END_OF_HOB_LIST)
/**
Returns a pointer to data buffer from a HOB of type EFI_HOB_TYPE_GUID_EXTENSION.
This macro returns a pointer to the data buffer in a HOB specified by HobStart.
HobStart is assumed to be a HOB of type EFI_HOB_TYPE_GUID_EXTENSION.
@param GuidHob A pointer to a HOB.
@return A pointer to the data buffer in a HOB.
**/
#define GET_GUID_HOB_DATA(HobStart) \
(VOID *)(*(UINT8 **)&(HobStart) + sizeof (EFI_HOB_GUID_TYPE))
/**
Returns the size of the data buffer from a HOB of type EFI_HOB_TYPE_GUID_EXTENSION.
This macro returns the size, in bytes, of the data buffer in a HOB specified by HobStart.
HobStart is assumed to be a HOB of type EFI_HOB_TYPE_GUID_EXTENSION.
@param GuidHob A pointer to a HOB.
@return The size of the data buffer.
**/
#define GET_GUID_HOB_DATA_SIZE(HobStart) \
(UINT16)(GET_HOB_LENGTH (HobStart) - sizeof (EFI_HOB_GUID_TYPE))
/**
Returns the pointer to the HOB list.
This function returns the pointer to first HOB in the list.
If the pointer to the HOB list is NULL, then ASSERT().
@return The pointer to the HOB list.
**/
VOID *
EFIAPI
GetHobList (
VOID
);
/**
Returns the next instance of a HOB type from the starting HOB.
This function searches the first instance of a HOB type from the starting HOB pointer.
If there does not exist such HOB type from the starting HOB pointer, it will return NULL.
In contrast with macro GET_NEXT_HOB(), this function does not skip the starting HOB pointer
unconditionally: it returns HobStart back if HobStart itself meets the requirement;
caller is required to use GET_NEXT_HOB() if it wishes to skip current HobStart.
If HobStart is NULL, then ASSERT().
@param Type The HOB type to return.
@param HobStart The starting HOB pointer to search from.
@return The next instance of a HOB type from the starting HOB.
**/
VOID *
EFIAPI
GetNextHob (
UINT16 Type,
CONST VOID *HobStart
);
/**
Returns the first instance of a HOB type among the whole HOB list.
This function searches the first instance of a HOB type among the whole HOB list.
If there does not exist such HOB type in the HOB list, it will return NULL.
If the pointer to the HOB list is NULL, then ASSERT().
@param Type The HOB type to return.
@return The next instance of a HOB type from the starting HOB.
**/
VOID *
EFIAPI
GetFirstHob (
UINT16 Type
);
/**
Returns the next instance of the matched GUID HOB from the starting HOB.
This function searches the first instance of a HOB from the starting HOB pointer.
Such HOB should satisfy two conditions:
its HOB type is EFI_HOB_TYPE_GUID_EXTENSION and its GUID Name equals to the input Guid.
If there does not exist such HOB from the starting HOB pointer, it will return NULL.
Caller is required to apply GET_GUID_HOB_DATA () and GET_GUID_HOB_DATA_SIZE ()
to extract the data section and its size info respectively.
In contrast with macro GET_NEXT_HOB(), this function does not skip the starting HOB pointer
unconditionally: it returns HobStart back if HobStart itself meets the requirement;
caller is required to use GET_NEXT_HOB() if it wishes to skip current HobStart.
If Guid is NULL, then ASSERT().
If HobStart is NULL, then ASSERT().
@param Guid The GUID to match with in the HOB list.
@param HobStart A pointer to a Guid.
@return The next instance of the matched GUID HOB from the starting HOB.
**/
VOID *
EFIAPI
GetNextGuidHob (
CONST EFI_GUID *Guid,
CONST VOID *HobStart
);
/**
Returns the first instance of the matched GUID HOB among the whole HOB list.
This function searches the first instance of a HOB among the whole HOB list.
Such HOB should satisfy two conditions:
its HOB type is EFI_HOB_TYPE_GUID_EXTENSION and its GUID Name equals to the input Guid.
If there does not exist such HOB from the starting HOB pointer, it will return NULL.
Caller is required to apply GET_GUID_HOB_DATA () and GET_GUID_HOB_DATA_SIZE ()
to extract the data section and its size info respectively.
If the pointer to the HOB list is NULL, then ASSERT().
If Guid is NULL, then ASSERT().
@param Guid The GUID to match with in the HOB list.
@return The first instance of the matched GUID HOB among the whole HOB list.
**/
VOID *
EFIAPI
GetFirstGuidHob (
CONST EFI_GUID *Guid
);
/**
Compares two GUIDs.
This function compares Guid1 to Guid2. If the GUIDs are identical then TRUE is returned.
If there are any bit differences in the two GUIDs, then FALSE is returned.
If Guid1 is NULL, then ASSERT().
If Guid2 is NULL, then ASSERT().
@param Guid1 A pointer to a 128 bit GUID.
@param Guid2 A pointer to a 128 bit GUID.
@retval TRUE Guid1 and Guid2 are identical.
@retval FALSE Guid1 and Guid2 are not identical.
**/
BOOLEAN
EFIAPI
CompareGuid (
CONST EFI_GUID *Guid1,
CONST EFI_GUID *Guid2
);
/**
Reads a 64-bit value from memory that may be unaligned.
This function returns the 64-bit value pointed to by Buffer. The function
guarantees that the read operation does not produce an alignment fault.
If the Buffer is NULL, then ASSERT().
@param Buffer Pointer to a 64-bit value that may be unaligned.
@return The 64-bit value read from Buffer.
**/
UINT64
EFIAPI
ReadUnaligned64 (
CONST UINT64 *Buffer
);
#endif

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/**
Copyright (C) 2013, Intel Corporation
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
**/
#ifndef _FSP_INFO_HEADER_H_
#define _FSP_INFO_HEADER_H_
#pragma pack(1)
typedef struct {
UINT32 Signature; // Off 0x94
UINT32 HeaderLength;
UINT8 Reserved1[3];
UINT8 HeaderRevision;
UINT32 ImageRevision;
CHAR8 ImageId[8]; // Off 0xA4
UINT32 ImageSize;
UINT32 ImageBase;
UINT32 ImageAttribute; // Off 0xB4
UINT32 CfgRegionOffset;
UINT32 CfgRegionSize;
UINT32 ApiEntryNum;
UINT32 NemInitEntry; // Off 0xC4
UINT32 FspInitEntry;
UINT32 NotifyPhaseEntry;
UINT32 Reserved2;
} FSP_INFO_HEADER;
#pragma pack()
#endif

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/**
Copyright (C) 2013, Intel Corporation
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
**/
#ifndef _FSP_PLATFORM_H_
#define _FSP_PLATFORM_H_
#include "fsptypes.h"
#include "fspapi.h"
#include "azalia.h"
#pragma pack(1)
typedef struct {
FSP_INIT_RT_COMMON_BUFFER Common;
} FSP_INIT_RT_BUFFER;
#pragma pack()
//
// Function prototypes for board_fsp.c
//
void
GetFspReservedMemoryFromGuid (
uint32_t *FspMemoryBase,
uint32_t *FspMemoryLength,
EFI_GUID FspReservedMemoryGuid
);
void
GetFspNVStorageMemory (
void **FspNVStorageHob,
uint16_t *DataSize
);
void
GetTempRamStack (
void **TempRamStackPtr,
uint16_t *DataSize
);
void
GetHighMemorySize (
uint64_t *HighMemoryLength
);
void
GetLowMemorySize (
uint32_t *LowMemoryLength
);
#endif

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/**
Copyright (C) 2013, Intel Corporation
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
**/
/** \file fsptypes.h
*
*
*/
#ifndef __FSP_TYPES_H__
#define __FSP_TYPES_H__
///
/// 8-byte unsigned value.
///
typedef unsigned long long UINT64;
///
/// 8-byte signed value.
///
typedef long long INT64;
///
/// 4-byte unsigned value.
///
typedef unsigned int UINT32;
///
/// 4-byte signed value.
///
typedef int INT32;
///
/// 2-byte unsigned value.
///
typedef unsigned short UINT16;
///
/// 2-byte Character. Unless otherwise specified all strings are stored in the
/// UTF-16 encoding format as defined by Unicode 2.1 and ISO/IEC 10646 standards.
///
typedef unsigned short CHAR16;
///
/// 2-byte signed value.
///
typedef short INT16;
///
/// Logical Boolean. 1-byte value containing 0 for FALSE or a 1 for TRUE. Other
/// values are undefined.
///
typedef unsigned char BOOLEAN;
///
/// 1-byte unsigned value.
///
typedef unsigned char UINT8;
///
/// 1-byte Character
///
typedef char CHAR8;
///
/// 1-byte signed value
///
typedef char INT8;
typedef void VOID;
typedef UINT64 EFI_PHYSICAL_ADDRESS;
typedef struct {
UINT32 Data1;
UINT16 Data2;
UINT16 Data3;
UINT8 Data4[8];
} EFI_GUID;
#define CONST const
#define STATIC static
#define TRUE ((BOOLEAN)(1==1))
#define FALSE ((BOOLEAN)(0==1))
static inline void DebugDeadLoop(void) {
for (;;);
}
#define FSPAPI __attribute__((cdecl))
#define EFIAPI __attribute__((cdecl))
#define _ASSERT(Expression) DebugDeadLoop()
#define ASSERT(Expression) \
do { \
if (!(Expression)) { \
_ASSERT (Expression); \
} \
} while (FALSE)
typedef UINT32 FSP_STATUS;
typedef UINT32 EFI_STATUS;
#endif

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/** @file
Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
This file is automatically generated. Please do NOT modify !!!
**/
#ifndef __FSP_VPD_H__
#define __FSP_VPD_H__
#pragma pack(1)
typedef struct {
UINT8 EnableMemoryDown;
UINT8 DRAMSpeed; /* DRAM Speed */
UINT8 DRAMType; /* DRAM Type */
UINT8 DIMM0Enable; /* DIMM 0 Enable */
UINT8 DIMM1Enable; /* DIMM 1 Enable */
UINT8 DIMMDWidth; /* DRAM device data width */
UINT8 DIMMDensity; /* DRAM device data density */
UINT8 DIMMBusWidth; /* DIMM Bus Width */
UINT8 DIMMSides; /* Ranks Per DIMM */
UINT8 DIMMtCL; /* tCL */
UINT8 DIMMtRPtRCD; /* tRP and tRCD in DRAM clk - 5:12.5ns, 6:15ns, etc. */
UINT8 DIMMtWR; /* tWR in DRAM clk */
UINT8 DIMMtWTR; /* tWTR in DRAM clk */
UINT8 DIMMtRRD; /* tRRD in DRAM clk */
UINT8 DIMMtRTP; /* tRTP in DRAM clk */
UINT8 DIMMtFAW; /* tFAW in DRAM clk */
} MEMORY_DOWN_DATA;
typedef struct _UPD_DATA_REGION {
UINT64 Signature; /* Offset 0x0000 */
UINT8 ReservedUpdSpace0[24]; /* Offset 0x0008 */
UINT16 PcdMrcInitTsegSize; /* Offset 0x0020 */
UINT16 PcdMrcInitMmioSize; /* Offset 0x0022 */
UINT8 PcdMrcInitSPDAddr1; /* Offset 0x0024 */
UINT8 PcdMrcInitSPDAddr2; /* Offset 0x0025 */
UINT8 PcdeMMCBootMode; /* Offset 0x0026 */
UINT8 PcdEnableSdio; /* Offset 0x0027 */
UINT8 PcdEnableSdcard; /* Offset 0x0028 */
UINT8 PcdEnableHsuart0; /* Offset 0x0029 */
UINT8 PcdEnableHsuart1; /* Offset 0x002A */
UINT8 PcdEnableSpi; /* Offset 0x002B */
UINT8 ReservedUpdSpace1; /* Offset 0x002C */
UINT8 PcdEnableSata; /* Offset 0x002D */
UINT8 PcdSataMode; /* Offset 0x002E */
UINT8 PcdEnableAzalia; /* Offset 0x002F */
UINT32 AzaliaConfigPtr; /* Offset 0x0030 */
UINT8 PcdEnableXhci; /* Offset 0x0034 */
UINT8 PcdEnableLpe; /* Offset 0x0035 */
UINT8 PcdLpssSioEnablePciMode; /* Offset 0x0036 */
UINT8 PcdEnableDma0; /* Offset 0x0037 */
UINT8 PcdEnableDma1; /* Offset 0x0038 */
UINT8 PcdEnableI2C0; /* Offset 0x0039 */
UINT8 PcdEnableI2C1; /* Offset 0x003A */
UINT8 PcdEnableI2C2; /* Offset 0x003B */
UINT8 PcdEnableI2C3; /* Offset 0x003C */
UINT8 PcdEnableI2C4; /* Offset 0x003D */
UINT8 PcdEnableI2C5; /* Offset 0x003E */
UINT8 PcdEnableI2C6; /* Offset 0x003F */
UINT8 PcdEnablePwm0; /* Offset 0x0040 */
UINT8 PcdEnablePwm1; /* Offset 0x0041 */
UINT8 PcdEnableHsi; /* Offset 0x0042 */
UINT8 PcdIgdDvmt50PreAlloc; /* Offset 0x0043 */
UINT8 PcdApertureSize; /* Offset 0x0044 */
UINT8 PcdGttSize; /* Offset 0x0045 */
UINT8 ReservedUpdSpace2[5]; /* Offset 0x0046 */
UINT8 PcdMrcDebugMsg; /* Offset 0x004B */
UINT8 ISPEnable; /* Offset 0x004C */
UINT8 PcdSccEnablePciMode; /* Offset 0x004D */
UINT8 IgdRenderStandby; /* Offset 0x004E */
UINT8 TxeUmaEnable; /* Offset 0x004F */
UINT8 PcdOsSelection; /* Offset 0x0050 */
UINT8 eMMC45DDR50Enabled; /* Offset 0x0051 */
UINT8 eMMC45HS200Enabled; /* Offset 0x0052 */
UINT8 eMMC45RetuneTimerValue; /* Offset 0x0053 */
UINT8 PcdEnableIgd; /* Offset 0x0054 */
UINT8 UnusedUpdSpace1[155]; /* Offset 0x0055 */
MEMORY_DOWN_DATA PcdMemoryParameters; /* Offset 0x00F0 */
UINT16 PcdRegionTerminator; /* Offset 0x0100 */
} UPD_DATA_REGION;
#define FSP_IMAGE_ID 0x3157454956594C56 /* 'VLYVIEW1' */
#define FSP_IMAGE_REV 0x00000304
typedef struct _VPD_DATA_REGION {
UINT64 PcdVpdRegionSign; /* Offset 0x0000 */
UINT32 PcdImageRevision; /* Offset 0x0008 */
UINT32 PcdUpdRegionOffset; /* Offset 0x000C */
UINT8 UnusedVpdSpace0[16]; /* Offset 0x0010 */
UINT32 PcdFspReservedMemoryLength; /* Offset 0x0020 */
UINT8 PcdPlatformType; /* Offset 0x0024 */
UINT8 PcdEnableSecureBoot; /* Offset 0x0025 */
} VPD_DATA_REGION;
#pragma pack()
#endif

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/**
Copyright (C) 2013, Intel Corporation
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
**/
/***********************************************************************
*
* board_fsp.c
*
* Parse HOB to get system data.
*
**********************************************************************/
#include "fsp.h"
void
GetLowMemorySize (
uint32_t *LowMemoryLength
)
{
EFI_PEI_HOB_POINTERS Hob;
*LowMemoryLength = 0x100000;
//
// Get the HOB list for processing
//
Hob.Raw = GetHobList();
//
// Collect memory ranges
//
while (!END_OF_HOB_LIST (Hob)) {
if (Hob.Header->HobType == EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) {
if (Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) {
//
// Need memory above 1MB to be collected here
//
if (Hob.ResourceDescriptor->PhysicalStart >= 0x100000 &&
Hob.ResourceDescriptor->PhysicalStart < (EFI_PHYSICAL_ADDRESS) 0x100000000) {
*LowMemoryLength += (uint32_t) (Hob.ResourceDescriptor->ResourceLength);
}
}
}
Hob.Raw = GET_NEXT_HOB (Hob);
}
return;
}
void
GetHighMemorySize (
uint64_t *HighMemoryLength
)
{
EFI_PEI_HOB_POINTERS Hob;
*HighMemoryLength = 0x0;
//
// Get the HOB list for processing
//
Hob.Raw = GetHobList();
//
// Collect memory ranges
//
while (!END_OF_HOB_LIST (Hob)) {
if (Hob.Header->HobType == EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) {
if (Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) {
//
// Need memory above 4GB to be collected here
//
if (Hob.ResourceDescriptor->PhysicalStart >= (EFI_PHYSICAL_ADDRESS) 0x100000000) {
*HighMemoryLength += (uint64_t) (Hob.ResourceDescriptor->ResourceLength);
}
}
}
Hob.Raw = GET_NEXT_HOB (Hob);
}
return;
}
void
GetFspReservedMemoryFromGuid (
uint32_t *FspMemoryBase,
uint32_t *FspMemoryLength,
EFI_GUID FspReservedMemoryGuid
)
{
EFI_PEI_HOB_POINTERS Hob;
//
// Get the HOB list for processing
//
Hob.Raw = GetHobList();
*FspMemoryBase = 0;
*FspMemoryLength = 0;
//
// Collect memory ranges
//
while (!END_OF_HOB_LIST (Hob)) {
if (Hob.Header->HobType == EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) {
if (Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_MEMORY_RESERVED) {
if (CompareGuid(&Hob.ResourceDescriptor->Owner, &FspReservedMemoryGuid)) {
*FspMemoryBase = (uint32_t) (Hob.ResourceDescriptor->PhysicalStart);
*FspMemoryLength = (uint32_t) (Hob.ResourceDescriptor->ResourceLength);
break;
}
}
}
Hob.Raw = GET_NEXT_HOB (Hob);
}
return;
}
void
GetFspNVStorageMemory (
VOID **FspNVStorageHob,
uint16_t *DataSize
)
{
EFI_GUID FspNVStorageHobGuid = FSP_NON_VOLATILE_STORAGE_HOB_GUID;
uint8_t *GuidHob;
EFI_HOB_GENERIC_HEADER *GuidHobHdr;
GuidHob = GetFirstGuidHob(&FspNVStorageHobGuid);
if (!GuidHob) {
*FspNVStorageHob = 0;
*DataSize = 0;
} else {
*FspNVStorageHob = GET_GUID_HOB_DATA (GuidHob);
GuidHobHdr = (EFI_HOB_GENERIC_HEADER *)GuidHob;
*DataSize = GET_GUID_HOB_DATA_SIZE (GuidHobHdr);
}
}
void
GetTempRamStack (
VOID **TempRamStackPtr,
uint16_t *DataSize
)
{
EFI_GUID FspBootloaderTemporaryMemoryHobGuid = FSP_BOOTLOADER_TEMPORARY_MEMORY_HOB_GUID;
uint8_t *GuidHob;
EFI_HOB_GENERIC_HEADER *GuidHobHdr;
GuidHob = GetFirstGuidHob(&FspBootloaderTemporaryMemoryHobGuid);
if (!GuidHob) {
*TempRamStackPtr = 0;
*DataSize = 0;
} else {
*TempRamStackPtr = GET_GUID_HOB_DATA (GuidHob);
GuidHobHdr = (EFI_HOB_GENERIC_HEADER *)GuidHob;
*DataSize = GET_GUID_HOB_DATA_SIZE (GuidHobHdr);
}
}

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/**
Copyright (C) 2013, Intel Corporation
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
**/
/***********************************************************************
*
* fsphob.c
*
* HOB infrastructure code.
*
**********************************************************************/
#include <string.h>
#include "fsptypes.h"
#include "fsphob.h"
//
// Pointer to the HOB should be initialized with the output of FSP INIT PARAMS
//
extern volatile void *FspHobListPtr;
/**
Reads a 64-bit value from memory that may be unaligned.
This function returns the 64-bit value pointed to by Buffer. The function
guarantees that the read operation does not produce an alignment fault.
If the Buffer is NULL, then ASSERT().
@param Buffer Pointer to a 64-bit value that may be unaligned.
@return The 64-bit value read from Buffer.
**/
UINT64
EFIAPI
ReadUnaligned64 (
CONST UINT64 *Buffer
)
{
ASSERT (Buffer != NULL);
return *Buffer;
}
/**
Compares two GUIDs.
This function compares Guid1 to Guid2. If the GUIDs are identical then TRUE is returned.
If there are any bit differences in the two GUIDs, then FALSE is returned.
If Guid1 is NULL, then ASSERT().
If Guid2 is NULL, then ASSERT().
@param Guid1 A pointer to a 128 bit GUID.
@param Guid2 A pointer to a 128 bit GUID.
@retval TRUE Guid1 and Guid2 are identical.
@retval FALSE Guid1 and Guid2 are not identical.
**/
BOOLEAN
EFIAPI
CompareGuid (
CONST EFI_GUID *Guid1,
CONST EFI_GUID *Guid2
)
{
UINT64 LowPartOfGuid1;
UINT64 LowPartOfGuid2;
UINT64 HighPartOfGuid1;
UINT64 HighPartOfGuid2;
LowPartOfGuid1 = ReadUnaligned64 ((CONST UINT64*) Guid1);
LowPartOfGuid2 = ReadUnaligned64 ((CONST UINT64*) Guid2);
HighPartOfGuid1 = ReadUnaligned64 ((CONST UINT64*) Guid1 + 1);
HighPartOfGuid2 = ReadUnaligned64 ((CONST UINT64*) Guid2 + 1);
return (BOOLEAN) (LowPartOfGuid1 == LowPartOfGuid2 && HighPartOfGuid1 == HighPartOfGuid2);
}
/**
Returns the pointer to the HOB list.
**/
VOID *
EFIAPI
GetHobList (
VOID
)
{
ASSERT (FspHobListPtr != NULL);
return ((VOID *)FspHobListPtr);
}
/**
Returns the next instance of a HOB type from the starting HOB.
**/
VOID *
EFIAPI
GetNextHob (
UINT16 Type,
CONST VOID *HobStart
)
{
EFI_PEI_HOB_POINTERS Hob;
ASSERT (HobStart != NULL);
Hob.Raw = (UINT8 *) HobStart;
//
// Parse the HOB list until end of list or matching type is found.
//
while (!END_OF_HOB_LIST (Hob)) {
if (Hob.Header->HobType == Type) {
return Hob.Raw;
}
Hob.Raw = GET_NEXT_HOB (Hob);
}
return NULL;
}
/**
Returns the first instance of a HOB type among the whole HOB list.
**/
VOID *
EFIAPI
GetFirstHob (
UINT16 Type
)
{
VOID *HobList;
HobList = GetHobList ();
return GetNextHob (Type, HobList);
}
/**
Returns the next instance of the matched GUID HOB from the starting HOB.
**/
VOID *
EFIAPI
GetNextGuidHob (
CONST EFI_GUID *Guid,
CONST VOID *HobStart
)
{
EFI_PEI_HOB_POINTERS GuidHob;
GuidHob.Raw = (UINT8 *) HobStart;
while ((GuidHob.Raw = GetNextHob (EFI_HOB_TYPE_GUID_EXTENSION, GuidHob.Raw)) != NULL) {
if (CompareGuid (Guid, &GuidHob.Guid->Name)) {
break;
}
GuidHob.Raw = GET_NEXT_HOB (GuidHob);
}
return GuidHob.Raw;
}
/**
Returns the first instance of the matched GUID HOB among the whole HOB list.
**/
VOID *
EFIAPI
GetFirstGuidHob (
CONST EFI_GUID *Guid
)
{
VOID *HobList;
HobList = GetHobList ();
return GetNextGuidHob (Guid, HobList);
}

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/** @file
Boot Setting File for Platform Configuration.
Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
This file is automatically generated. Please do NOT modify !!!
**/
GlobalDataDef
SKUID = 0, "DEFAULT"
EndGlobalData
StructDef
Find "$BSWUPD$"
Skip 40 bytes
$gPlatformFspPkgTokenSpaceGuid_PcdMrcInitTsegSize 2 bytes $_DEFAULT_ = 0x0004
$gPlatformFspPkgTokenSpaceGuid_PcdMrcInitMmioSize 2 bytes $_DEFAULT_ = 0x0800
$gPlatformFspPkgTokenSpaceGuid_PcdMrcInitSpdAddr1 1 bytes $_DEFAULT_ = 0xA0
$gPlatformFspPkgTokenSpaceGuid_PcdMrcInitSpdAddr2 1 bytes $_DEFAULT_ = 0xA2
Skip 6 bytes
$gPlatformFspPkgTokenSpaceGuid_PcdIgdDvmt50PreAlloc 1 bytes $_DEFAULT_ = 1
$gPlatformFspPkgTokenSpaceGuid_PcdApertureSize 1 bytes $_DEFAULT_ = 2
$gPlatformFspPkgTokenSpaceGuid_PcdGttSize 1 bytes $_DEFAULT_ = 1
$gPlatformFspPkgTokenSpaceGuid_PcdLegacySegDecode 1 bytes $_DEFAULT_ = 0
$gPlatformFspPkgTokenSpaceGuid_PcdDvfsEnable 1 bytes $_DEFAULT_ = 1
$gPlatformFspPkgTokenSpaceGuid_PcdMemoryTypeEnable 1 bytes $_DEFAULT_ = 0
$gPlatformFspPkgTokenSpaceGuid_PcdCaMirrorEn 1 bytes $_DEFAULT_ = 0
Skip 205 bytes
$gPlatformFspPkgTokenSpaceGuid_PcdSdcardMode 1 bytes $_DEFAULT_ = 1
$gPlatformFspPkgTokenSpaceGuid_PcdEnableHsuart0 1 bytes $_DEFAULT_ = 0
$gPlatformFspPkgTokenSpaceGuid_PcdEnableHsuart1 1 bytes $_DEFAULT_ = 1
$gPlatformFspPkgTokenSpaceGuid_PcdEnableAzalia 1 bytes $_DEFAULT_ = 0
Skip 4 bytes
$gPlatformFspPkgTokenSpaceGuid_PcdEnableSata 1 bytes $_DEFAULT_ = 1
$gPlatformFspPkgTokenSpaceGuid_PcdEnableXhci 1 bytes $_DEFAULT_ = 1
$gPlatformFspPkgTokenSpaceGuid_PcdEnableLpe 1 bytes $_DEFAULT_ = 1
$gPlatformFspPkgTokenSpaceGuid_PcdEnableDma0 1 bytes $_DEFAULT_ = 1
$gPlatformFspPkgTokenSpaceGuid_PcdEnableDma1 1 bytes $_DEFAULT_ = 1
$gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C0 1 bytes $_DEFAULT_ = 1
$gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C1 1 bytes $_DEFAULT_ = 1
$gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C2 1 bytes $_DEFAULT_ = 1
$gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C3 1 bytes $_DEFAULT_ = 1
$gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C4 1 bytes $_DEFAULT_ = 1
$gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C5 1 bytes $_DEFAULT_ = 1
$gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C6 1 bytes $_DEFAULT_ = 1
Skip 15 bytes
$gPlatformFspPkgTokenSpaceGuid_PcdEmmcMode 1 bytes $_DEFAULT_ = 1
Skip 27 bytes
$gPlatformFspPkgTokenSpaceGuid_PcdSataInterfaceSpeed 1 bytes $_DEFAULT_ = 3
Skip 13 bytes
$gPlatformFspPkgTokenSpaceGuid_PMIC_I2CBus 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_ISPEnable 1 bytes $_DEFAULT_ = 1
$gPlatformFspPkgTokenSpaceGuid_ISPPciDevConfig 1 bytes $_DEFAULT_ = 2
$gPlatformFspPkgTokenSpaceGuid_PcdTurboMode 1 bytes $_DEFAULT_ = 1
$gPlatformFspPkgTokenSpaceGuid_PcdPnpSettings 1 bytes $_DEFAULT_ = 3
$gPlatformFspPkgTokenSpaceGuid_PcdSdDetectChk 1 bytes $_DEFAULT_ = 1
Find "$BSWFSP$"
$gPlatformFspPkgTokenSpaceGuid_PcdImageRevision 4 bytes $_DEFAULT_ = 0x01010200
EndStruct
List &EN_DIS
Selection 0x1 , "Enabled"
Selection 0x0 , "Disabled"
EndList
List &gPlatformFspPkgTokenSpaceGuid_PcdSdcardMode
Selection 0x0 , "Disabled"
Selection 0x1 , "PCI Mode"
Selection 0x2 , "ACPI Mode"
EndList
List &gPlatformFspPkgTokenSpaceGuid_PcdIgdDvmt50PreAlloc
Selection 0x01 , "32 MB"
Selection 0x02 , "64 MB"
Selection 0x03 , "96 MB"
Selection 0x04 , "128 MB"
Selection 0x05 , "160 MB"
Selection 0x06 , "192 MB"
Selection 0x07 , "224 MB"
Selection 0x08 , "256 MB"
Selection 0x09 , "288 MB"
Selection 0x0A , "320 MB"
Selection 0x0B , "352 MB"
Selection 0x0C , "384 MB"
Selection 0x0D , "416 MB"
Selection 0x0E , "448 MB"
Selection 0x0F , "480 MB"
Selection 0x10 , "512 MB"
EndList
List &gPlatformFspPkgTokenSpaceGuid_PcdCaMirrorEn
Selection 0x00 , "Disable"
Selection 0x01 , "Enable"
EndList
List &gPlatformFspPkgTokenSpaceGuid_ISPPciDevConfig
Selection 0x1 , " ISP PCI Device as B0D2F0"
Selection 0x2 , " ISP PCI Device as B0D3F0"
Selection 0x3 , " ISP PCI Device as B0D3F0 with Virtual ISP B0D2F0"
EndList
List &gPlatformFspPkgTokenSpaceGuid_PcdEnableLpe
Selection 0x2 , "ACPI Mode"
Selection 0x1 , "PCI Mode"
Selection 0x0 , "Disabled"
EndList
List &gPlatformFspPkgTokenSpaceGuid_PcdMrcInitTsegSize
Selection 0x01 , "1 MB"
Selection 0x02 , "2 MB"
Selection 0x04 , "4 MB"
Selection 0x08 , "8 MB"
EndList
List &gPlatformFspPkgTokenSpaceGuid_PcdMrcInitMmioSize
Selection 0x400 , "1.0 GB"
Selection 0x600 , "1.5 GB"
Selection 0x800 , "2.0 GB"
EndList
List &gPlatformFspPkgTokenSpaceGuid_PcdGttSize
Selection 0x1 , "1 MB"
Selection 0x2 , "2 MB"
EndList
List &gPlatformFspPkgTokenSpaceGuid_PcdEmmcMode
Selection 0x0 , "Disabled"
Selection 0x1 , "PCI Mode"
Selection 0x2 , "ACPI Mode"
EndList
List &gPlatformFspPkgTokenSpaceGuid_PcdSataInterfaceSpeed
Selection 1 , "GEN1"
Selection 2 , "GEN2"
Selection 3 , "GEN3"
EndList
List &gPlatformFspPkgTokenSpaceGuid_PcdApertureSize
Selection 0x1 , "128 MB"
Selection 0x2 , "256 MB"
Selection 0x3 , "512 MB"
EndList
List &gPlatformFspPkgTokenSpaceGuid_PcdMemoryTypeEnable
Selection 0x00 , "DDR3"
Selection 0x01 , "LPDDR3"
EndList
BeginInfoBlock
PPVer "1.0"
Description "Braswell platform"
EndInfoBlock
Page "Platform"
Combo $gPlatformFspPkgTokenSpaceGuid_PcdTurboMode, "Processor Turbo Mode", &EN_DIS,
Help "Enable/disable Processor Turbo Mode."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdPnpSettings, "Pnp-Power & Performance", &EN_DIS,
Help "select Pnp type "
Combo $gPlatformFspPkgTokenSpaceGuid_PcdSdDetectChk, "SdDetectChk", &EN_DIS,
Help "Check for Sd card detect "
EndPage
Page "South Complex"
Combo $gPlatformFspPkgTokenSpaceGuid_PcdSdcardMode, "SD Card Mode", &gPlatformFspPkgTokenSpaceGuid_PcdSdcardMode,
Help "SD Card Mode"
Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableHsuart0, "Enable HSUART0", &EN_DIS,
Help "Enable/disable HSUART0."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableHsuart1, "Enable HSUART1", &EN_DIS,
Help "Enable/disable HSUART1."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableAzalia, "Enable Azalia", &EN_DIS,
Help "Enable/disable Azalia controller."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableSata, "Enable SATA", &EN_DIS,
Help "Enable/disable SATA controller."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableXhci, "Enable XHCI", &EN_DIS,
Help "Enable/disable XHCI controller."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableLpe, "Enable LPE", &gPlatformFspPkgTokenSpaceGuid_PcdEnableLpe,
Help "Choose LPE Mode."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableDma0, "Enable DMA0", &EN_DIS,
Help "Enable/disable DMA0."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableDma1, "Enable DMA1", &EN_DIS,
Help "Enable/disable DMA1."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C0, "Enable I2C0", &EN_DIS,
Help "Enable/disable I2C0."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C1, "Enable I2C1", &EN_DIS,
Help "Enable/disable I2C1."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C2, "Enable I2C2", &EN_DIS,
Help "Enable/disable I2C2."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C3, "Enable I2C3", &EN_DIS,
Help "Enable/disable I2C3."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C4, "Enable I2C4", &EN_DIS,
Help "Enable/disable I2C4."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C5, "Enable I2C5", &EN_DIS,
Help "Enable/disable I2C5."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C6, "Enable I2C6", &EN_DIS,
Help "Enable/disable I2C6."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdEmmcMode, "eMMC Mode", &gPlatformFspPkgTokenSpaceGuid_PcdEmmcMode,
Help "EMMC Mode"
Combo $gPlatformFspPkgTokenSpaceGuid_PcdSataInterfaceSpeed, "SATA Interface Speed", &gPlatformFspPkgTokenSpaceGuid_PcdSataInterfaceSpeed,
Help "Select SATA controller Interface Speed."
Combo $gPlatformFspPkgTokenSpaceGuid_ISPEnable, "Enable ISP", &EN_DIS,
Help "Enable/disable ISP."
Combo $gPlatformFspPkgTokenSpaceGuid_ISPPciDevConfig, "Select ISP Device Number", &gPlatformFspPkgTokenSpaceGuid_ISPPciDevConfig,
Help "Select ISP PCI Device Configuration"
EndPage
Page "North Complex"
Combo $gPlatformFspPkgTokenSpaceGuid_PcdMrcInitTsegSize, "Tseg Size", &gPlatformFspPkgTokenSpaceGuid_PcdMrcInitTsegSize,
Help "Size of SMRAM memory reserved."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdMrcInitMmioSize, "MMIO Size", &gPlatformFspPkgTokenSpaceGuid_PcdMrcInitMmioSize,
Help "Size of memory address space reserved for MMIO (Memory Mapped I/O)."
EditNum $gPlatformFspPkgTokenSpaceGuid_PcdMrcInitSpdAddr1, "DIMM 0 SPD SMBus Address", HEX,
Help "SPD Address of DIMM."
"Valid range: 0x00 ~ 0xFF"
EditNum $gPlatformFspPkgTokenSpaceGuid_PcdMrcInitSpdAddr2, "DIMM 1 SPD SMBus Address", HEX,
Help "SPD Address of DIMM."
"Valid range: 0x00 ~ 0xFF"
Combo $gPlatformFspPkgTokenSpaceGuid_PcdIgdDvmt50PreAlloc, "Internal Graphics Pre-allocated Memory", &gPlatformFspPkgTokenSpaceGuid_PcdIgdDvmt50PreAlloc,
Help "Size of memory preallocated for internal graphics"
Combo $gPlatformFspPkgTokenSpaceGuid_PcdApertureSize, "Aperture Size", &gPlatformFspPkgTokenSpaceGuid_PcdApertureSize,
Help "Select the Aperture Size."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdGttSize, "GTT Size", &gPlatformFspPkgTokenSpaceGuid_PcdGttSize,
Help "Select the GTT Size."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdLegacySegDecode, "Enable Legacy E/F segments decoding to ROM", &EN_DIS,
Help "If disabled, E0000h-FFFFFh decoding will be routed to DRAM."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdDvfsEnable, "Enable DVFS", &EN_DIS,
Help "Enable/disable DVFS."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdMemoryTypeEnable, "MemoryType", &gPlatformFspPkgTokenSpaceGuid_PcdMemoryTypeEnable,
Help "To Configure Memory Type"
Combo $gPlatformFspPkgTokenSpaceGuid_PcdCaMirrorEn, "CaMirrorEn", &gPlatformFspPkgTokenSpaceGuid_PcdCaMirrorEn,
Help "To Enable/Disable CaMirrorEn"
EndPage

View File

@ -0,0 +1,510 @@
/** @file
Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
This file is automatically generated. Please do NOT modify !!!
**/
#ifndef __FSPUPDVPD_H__
#define __FSPUPDVPD_H__
#pragma pack(1)
#define MAX_CHANNELS_NUM 2
#define MAX_DIMMS_NUM 2
typedef struct {
UINT32 VendorDeviceId;
UINT16 SubSystemId;
UINT8 RevisionId; /// 0xFF applies to all steppings
UINT8 FrontPanelSupport;
UINT16 NumberOfRearJacks;
UINT16 NumberOfFrontJacks;
} BL_PCH_AZALIA_VERB_TABLE_HEADER;
typedef struct {
BL_PCH_AZALIA_VERB_TABLE_HEADER VerbTableHeader;
UINT32 *VerbTableData;
} BL_PCH_AZALIA_VERB_TABLE;
typedef struct {
UINT8 Pme : 1; /// 0: Disable; 1: Enable
UINT8 DS : 1; /// 0: Docking is not supported; 1:Docking is supported
UINT8 DA : 1; /// 0: Docking is not attached; 1:Docking is attached
UINT8 HdmiCodec : 1; /// 0: Disable; 1: Enable
UINT8 AzaliaVCi : 1; /// 0: Disable; 1: Enable
UINT8 Rsvdbits : 3;
UINT8 AzaliaVerbTableNum; /// Number of verb tables provided by platform
BL_PCH_AZALIA_VERB_TABLE *AzaliaVerbTable; /// Pointer to the actual verb table(s)
UINT16 ResetWaitTimer; /// The delay timer after Azalia reset, the value is number of microseconds
} BL_PCH_AZALIA_CONFIG;
typedef struct {
UINT32 Confg;
UINT32 ConfgChanges;
UINT32 Misc;
UINT32 MmioAddr;
CHAR16 *Name;
} BL_GPIO_FAMILY_INIT;
typedef struct {
UINT32 Confg0;
UINT32 Confg0Changes;
UINT32 Confg1;
UINT32 Confg1Changes;
UINT32 Community;
UINT32 MmioAddr;
CHAR16 *Name;
UINT32 Misc;
} BL_GPIO_PAD_INIT;
typedef struct {
UINT8 DimmId;
UINT32 SizeInMb;
UINT16 MfgId;
/** Module part number for DRR3 is 18 bytes
but DRR4 is 20 bytes as per JEDEC Spec, so
reserving 20 bytes **/
UINT8 ModulePartNum[20];
} DIMM_INFO;
typedef struct {
UINT8 ChannelId;
UINT8 DimmCount;
DIMM_INFO DimmInfo[MAX_DIMMS_NUM];
} CHANNEL_INFO;
typedef struct {
UINT8 Revision;
UINT8 DataWidth;
/** As defined in SMBIOS 3.0 spec
Section 7.18.2 and Table 75
**/
UINT8 MemoryType;
UINT16 MemoryFrequencyInMHz;
/** As defined in SMBIOS 3.0 spec
Section 7.17.3 and Table 72
**/
UINT8 ErrorCorrectionType;
UINT8 ChannelCount;
CHANNEL_INFO ChannelInfo[MAX_CHANNELS_NUM];
} FSP_SMBIOS_MEMORY_INFO;
typedef struct {
/** Offset 0x0020
**/
UINT64 Signature;
/** Offset 0x0028
**/
UINT8 Revision;
/** Offset 0x0029
**/
UINT8 UnusedUpdSpace2[7];
/** Offset 0x0030
Tseg Size
Size of SMRAM memory reserved.
**/
UINT16 PcdMrcInitTsegSize;
/** Offset 0x0032
MMIO Size
Size of memory address space reserved for MMIO (Memory Mapped I/O).
**/
UINT16 PcdMrcInitMmioSize;
/** Offset 0x0034
DIMM 0 SPD SMBus Address
SPD Address of DIMM.
**/
UINT8 PcdMrcInitSpdAddr1;
/** Offset 0x0035
DIMM 1 SPD SMBus Address
SPD Address of DIMM.
**/
UINT8 PcdMrcInitSpdAddr2;
/** Offset 0x0036
**/
UINT8 PcdMemChannel0Config;
/** Offset 0x0037
**/
UINT8 PcdMemChannel1Config;
/** Offset 0x0038
**/
UINT32 PcdMemorySpdPtr;
/** Offset 0x003C
Internal Graphics Pre-allocated Memory
Size of memory preallocated for internal graphics
**/
UINT8 PcdIgdDvmt50PreAlloc;
/** Offset 0x003D
Aperture Size
Select the Aperture Size.
**/
UINT8 PcdApertureSize;
/** Offset 0x003E
GTT Size
Select the GTT Size.
**/
UINT8 PcdGttSize;
/** Offset 0x003F
Enable Legacy E/F segments decoding to ROM
If disabled, E0000h-FFFFFh decoding will be routed to DRAM.
**/
UINT8 PcdLegacySegDecode;
/** Offset 0x0040
Enable DVFS
Enable/disable DVFS.
**/
UINT8 PcdDvfsEnable;
/** Offset 0x0041
MemoryType
To Configure Memory Type
**/
UINT8 PcdMemoryTypeEnable;
/** Offset 0x0042
CaMirrorEn
To Enable/Disable CaMirrorEn
**/
UINT8 PcdCaMirrorEn;
/** Offset 0x0043
**/
UINT8 ReservedMemoryInitUpd[189];
} MEMORY_INIT_UPD;
typedef struct {
/** Offset 0x0100
**/
UINT64 Signature;
/** Offset 0x0108
**/
UINT8 Revision;
/** Offset 0x0109
**/
UINT8 UnusedUpdSpace3[7];
/** Offset 0x0110
SD Card Mode
SD Card Mode
**/
UINT8 PcdSdcardMode;
/** Offset 0x0111
Enable HSUART0
Enable/disable HSUART0.
**/
UINT8 PcdEnableHsuart0;
/** Offset 0x0112
Enable HSUART1
Enable/disable HSUART1.
**/
UINT8 PcdEnableHsuart1;
/** Offset 0x0113
Enable Azalia
Enable/disable Azalia controller.
**/
UINT8 PcdEnableAzalia;
/** Offset 0x0114
**/
BL_PCH_AZALIA_CONFIG* AzaliaConfigPtr;
/** Offset 0x0118
Enable SATA
Enable/disable SATA controller.
**/
UINT8 PcdEnableSata;
/** Offset 0x0119
Enable XHCI
Enable/disable XHCI controller.
**/
UINT8 PcdEnableXhci;
/** Offset 0x011A
Enable LPE
Choose LPE Mode.
**/
UINT8 PcdEnableLpe;
/** Offset 0x011B
Enable DMA0
Enable/disable DMA0.
**/
UINT8 PcdEnableDma0;
/** Offset 0x011C
Enable DMA1
Enable/disable DMA1.
**/
UINT8 PcdEnableDma1;
/** Offset 0x011D
Enable I2C0
Enable/disable I2C0.
**/
UINT8 PcdEnableI2C0;
/** Offset 0x011E
Enable I2C1
Enable/disable I2C1.
**/
UINT8 PcdEnableI2C1;
/** Offset 0x011F
Enable I2C2
Enable/disable I2C2.
**/
UINT8 PcdEnableI2C2;
/** Offset 0x0120
Enable I2C3
Enable/disable I2C3.
**/
UINT8 PcdEnableI2C3;
/** Offset 0x0121
Enable I2C4
Enable/disable I2C4.
**/
UINT8 PcdEnableI2C4;
/** Offset 0x0122
Enable I2C5
Enable/disable I2C5.
**/
UINT8 PcdEnableI2C5;
/** Offset 0x0123
Enable I2C6
Enable/disable I2C6.
**/
UINT8 PcdEnableI2C6;
/** Offset 0x0124
**/
UINT32 GraphicsConfigPtr;
/** Offset 0x0128
**/
BL_GPIO_FAMILY_INIT* GpioFamilyInitTablePtr;
/** Offset 0x012C
**/
BL_GPIO_PAD_INIT* GpioPadInitTablePtr;
/** Offset 0x0130
**/
UINT8 PunitPwrConfigDisable;
/** Offset 0x0131
**/
UINT8 ChvSvidConfig;
/** Offset 0x0132
**/
UINT8 DptfDisable;
/** Offset 0x0133
eMMC Mode
EMMC Mode
**/
UINT8 PcdEmmcMode;
/** Offset 0x0134
**/
UINT8 PcdUsb3ClkSsc;
/** Offset 0x0135
**/
UINT8 PcdDispClkSsc;
/** Offset 0x0136
**/
UINT8 PcdSataClkSsc;
/** Offset 0x0137
**/
UINT8 Usb2Port0PerPortPeTxiSet;
/** Offset 0x0138
**/
UINT8 Usb2Port0PerPortTxiSet;
/** Offset 0x0139
**/
UINT8 Usb2Port0IUsbTxEmphasisEn;
/** Offset 0x013A
**/
UINT8 Usb2Port0PerPortTxPeHalf;
/** Offset 0x013B
**/
UINT8 Usb2Port1PerPortPeTxiSet;
/** Offset 0x013C
**/
UINT8 Usb2Port1PerPortTxiSet;
/** Offset 0x013D
**/
UINT8 Usb2Port1IUsbTxEmphasisEn;
/** Offset 0x013E
**/
UINT8 Usb2Port1PerPortTxPeHalf;
/** Offset 0x013F
**/
UINT8 Usb2Port2PerPortPeTxiSet;
/** Offset 0x0140
**/
UINT8 Usb2Port2PerPortTxiSet;
/** Offset 0x0141
**/
UINT8 Usb2Port2IUsbTxEmphasisEn;
/** Offset 0x0142
**/
UINT8 Usb2Port2PerPortTxPeHalf;
/** Offset 0x0143
**/
UINT8 Usb2Port3PerPortPeTxiSet;
/** Offset 0x0144
**/
UINT8 Usb2Port3PerPortTxiSet;
/** Offset 0x0145
**/
UINT8 Usb2Port3IUsbTxEmphasisEn;
/** Offset 0x0146
**/
UINT8 Usb2Port3PerPortTxPeHalf;
/** Offset 0x0147
**/
UINT8 Usb2Port4PerPortPeTxiSet;
/** Offset 0x0148
**/
UINT8 Usb2Port4PerPortTxiSet;
/** Offset 0x0149
**/
UINT8 Usb2Port4IUsbTxEmphasisEn;
/** Offset 0x014A
**/
UINT8 Usb2Port4PerPortTxPeHalf;
/** Offset 0x014B
**/
UINT8 Usb3Lane0Ow2tapgen2deemph3p5;
/** Offset 0x014C
**/
UINT8 Usb3Lane1Ow2tapgen2deemph3p5;
/** Offset 0x014D
**/
UINT8 Usb3Lane2Ow2tapgen2deemph3p5;
/** Offset 0x014E
**/
UINT8 Usb3Lane3Ow2tapgen2deemph3p5;
/** Offset 0x014F
SATA Interface Speed
Select SATA controller Interface Speed.
**/
UINT8 PcdSataInterfaceSpeed;
/** Offset 0x0150
**/
UINT8 PcdPchUsbSsicPort;
/** Offset 0x0151
**/
UINT8 PcdPchUsbHsicPort;
/** Offset 0x0152
**/
UINT8 PcdPcieRootPortSpeed;
/** Offset 0x0153
**/
UINT8 PcdPchSsicEnable;
/** Offset 0x0154
**/
UINT32 PcdLogoPtr;
/** Offset 0x0158
**/
UINT32 PcdLogoSize;
/** Offset 0x015C
**/
UINT8 PcdRtcLock;
/** Offset 0x015D
PMIC I2c Bus Number
I2c Bus Number to communicate with PMIC
**/
UINT8 PMIC_I2CBus;
/** Offset 0x015E
Enable ISP
Enable/disable ISP.
**/
UINT8 ISPEnable;
/** Offset 0x015F
Select ISP Device Number
Select ISP PCI Device Configuration
**/
UINT8 ISPPciDevConfig;
/** Offset 0x0160
Processor Turbo Mode
Enable/disable Processor Turbo Mode.
**/
UINT8 PcdTurboMode;
/** Offset 0x0161
Pnp-Power & Performance
select Pnp type
**/
UINT8 PcdPnpSettings;
/** Offset 0x0162
SdDetectChk
Check for Sd card detect
**/
UINT8 PcdSdDetectChk;
/** Offset 0x0163
**/
UINT8 ReservedSiliconInitUpd[411];
} SILICON_INIT_UPD;
#define FSP_UPD_SIGNATURE 0x2444505557534224 /* '$BSWUPD$' */
#define FSP_MEMORY_INIT_UPD_SIGNATURE 0x244450554D454D24 /* '$MEMUPD$' */
#define FSP_SILICON_INIT_UPD_SIGNATURE 0x244450555F495324 /* '$SI_UPD$' */
typedef struct _UPD_DATA_REGION {
/** Offset 0x0000
**/
UINT64 Signature;
/** Offset 0x0008
**/
UINT8 Revision;
/** Offset 0x0009
**/
UINT8 UnusedUpdSpace0[7];
/** Offset 0x0010
**/
UINT32 MemoryInitUpdOffset;
/** Offset 0x0014
**/
UINT32 SiliconInitUpdOffset;
/** Offset 0x0018
**/
UINT64 UnusedUpdSpace1;
/** Offset 0x0020
**/
MEMORY_INIT_UPD MemoryInitUpd;
/** Offset 0x0100
**/
SILICON_INIT_UPD SiliconInitUpd;
/** Offset 0x02FE
**/
UINT16 PcdRegionTerminator;
} UPD_DATA_REGION;
#define FSP_IMAGE_ID 0x2450534657534224 /* '$BSWFSP$' */
#define FSP_IMAGE_REV 0x01010200
typedef struct _VPD_DATA_REGION {
/** Offset 0x0000
**/
UINT64 PcdVpdRegionSign;
/** Offset 0x0008
PcdImageRevision
**/
UINT32 PcdImageRevision;
/** Offset 0x000C
**/
UINT32 PcdUpdRegionOffset;
} VPD_DATA_REGION;
#pragma pack()
#endif

View File

@ -0,0 +1,510 @@
/** @file
Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
This file is automatically generated. Please do NOT modify !!!
**/
#ifndef __FSPUPDVPD_H__
#define __FSPUPDVPD_H__
#pragma pack(1)
#define MAX_CHANNELS_NUM 2
#define MAX_DIMMS_NUM 2
typedef struct {
UINT32 VendorDeviceId;
UINT16 SubSystemId;
UINT8 RevisionId; /// 0xFF applies to all steppings
UINT8 FrontPanelSupport;
UINT16 NumberOfRearJacks;
UINT16 NumberOfFrontJacks;
} BL_PCH_AZALIA_VERB_TABLE_HEADER;
typedef struct {
BL_PCH_AZALIA_VERB_TABLE_HEADER VerbTableHeader;
UINT32 *VerbTableData;
} BL_PCH_AZALIA_VERB_TABLE;
typedef struct {
UINT8 Pme : 1; /// 0: Disable; 1: Enable
UINT8 DS : 1; /// 0: Docking is not supported; 1:Docking is supported
UINT8 DA : 1; /// 0: Docking is not attached; 1:Docking is attached
UINT8 HdmiCodec : 1; /// 0: Disable; 1: Enable
UINT8 AzaliaVCi : 1; /// 0: Disable; 1: Enable
UINT8 Rsvdbits : 3;
UINT8 AzaliaVerbTableNum; /// Number of verb tables provided by platform
BL_PCH_AZALIA_VERB_TABLE *AzaliaVerbTable; /// Pointer to the actual verb table(s)
UINT16 ResetWaitTimer; /// The delay timer after Azalia reset, the value is number of microseconds
} BL_PCH_AZALIA_CONFIG;
typedef struct {
UINT32 Confg;
UINT32 ConfgChanges;
UINT32 Misc;
UINT32 MmioAddr;
CHAR16 *Name;
} BL_GPIO_FAMILY_INIT;
typedef struct {
UINT32 Confg0;
UINT32 Confg0Changes;
UINT32 Confg1;
UINT32 Confg1Changes;
UINT32 Community;
UINT32 MmioAddr;
CHAR16 *Name;
UINT32 Misc;
} BL_GPIO_PAD_INIT;
typedef struct {
UINT8 DimmId;
UINT32 SizeInMb;
UINT16 MfgId;
/** Module part number for DRR3 is 18 bytes
but DRR4 is 20 bytes as per JEDEC Spec, so
reserving 20 bytes **/
UINT8 ModulePartNum[20];
} DIMM_INFO;
typedef struct {
UINT8 ChannelId;
UINT8 DimmCount;
DIMM_INFO DimmInfo[MAX_DIMMS_NUM];
} CHANNEL_INFO;
typedef struct {
UINT8 Revision;
UINT8 DataWidth;
/** As defined in SMBIOS 3.0 spec
Section 7.18.2 and Table 75
**/
UINT8 MemoryType;
UINT16 MemoryFrequencyInMHz;
/** As defined in SMBIOS 3.0 spec
Section 7.17.3 and Table 72
**/
UINT8 ErrorCorrectionType;
UINT8 ChannelCount;
CHANNEL_INFO ChannelInfo[MAX_CHANNELS_NUM];
} FSP_SMBIOS_MEMORY_INFO;
typedef struct {
/** Offset 0x0020
**/
UINT64 Signature;
/** Offset 0x0028
**/
UINT8 Revision;
/** Offset 0x0029
**/
UINT8 UnusedUpdSpace2[7];
/** Offset 0x0030
Tseg Size
Size of SMRAM memory reserved.
**/
UINT16 PcdMrcInitTsegSize;
/** Offset 0x0032
MMIO Size
Size of memory address space reserved for MMIO (Memory Mapped I/O).
**/
UINT16 PcdMrcInitMmioSize;
/** Offset 0x0034
DIMM 0 SPD SMBus Address
SPD Address of DIMM.
**/
UINT8 PcdMrcInitSpdAddr1;
/** Offset 0x0035
DIMM 1 SPD SMBus Address
SPD Address of DIMM.
**/
UINT8 PcdMrcInitSpdAddr2;
/** Offset 0x0036
**/
UINT8 PcdMemChannel0Config;
/** Offset 0x0037
**/
UINT8 PcdMemChannel1Config;
/** Offset 0x0038
**/
UINT32 PcdMemorySpdPtr;
/** Offset 0x003C
Internal Graphics Pre-allocated Memory
Size of memory preallocated for internal graphics
**/
UINT8 PcdIgdDvmt50PreAlloc;
/** Offset 0x003D
Aperture Size
Select the Aperture Size.
**/
UINT8 PcdApertureSize;
/** Offset 0x003E
GTT Size
Select the GTT Size.
**/
UINT8 PcdGttSize;
/** Offset 0x003F
Enable Legacy E/F segments decoding to ROM
If disabled, E0000h-FFFFFh decoding will be routed to DRAM.
**/
UINT8 PcdLegacySegDecode;
/** Offset 0x0040
Enable DVFS
Enable/disable DVFS.
**/
UINT8 PcdDvfsEnable;
/** Offset 0x0041
MemoryType
To Configure Memory Type
**/
UINT8 PcdMemoryTypeEnable;
/** Offset 0x0042
CaMirrorEn
To Enable/Disable CaMirrorEn
**/
UINT8 PcdCaMirrorEn;
/** Offset 0x0043
**/
UINT8 ReservedMemoryInitUpd[189];
} MEMORY_INIT_UPD;
typedef struct {
/** Offset 0x0100
**/
UINT64 Signature;
/** Offset 0x0108
**/
UINT8 Revision;
/** Offset 0x0109
**/
UINT8 UnusedUpdSpace3[7];
/** Offset 0x0110
SD Card Mode
SD Card Mode
**/
UINT8 PcdSdcardMode;
/** Offset 0x0111
Enable HSUART0
Enable/disable HSUART0.
**/
UINT8 PcdEnableHsuart0;
/** Offset 0x0112
Enable HSUART1
Enable/disable HSUART1.
**/
UINT8 PcdEnableHsuart1;
/** Offset 0x0113
Enable Azalia
Enable/disable Azalia controller.
**/
UINT8 PcdEnableAzalia;
/** Offset 0x0114
**/
BL_PCH_AZALIA_CONFIG* AzaliaConfigPtr;
/** Offset 0x0118
Enable SATA
Enable/disable SATA controller.
**/
UINT8 PcdEnableSata;
/** Offset 0x0119
Enable XHCI
Enable/disable XHCI controller.
**/
UINT8 PcdEnableXhci;
/** Offset 0x011A
Enable LPE
Choose LPE Mode.
**/
UINT8 PcdEnableLpe;
/** Offset 0x011B
Enable DMA0
Enable/disable DMA0.
**/
UINT8 PcdEnableDma0;
/** Offset 0x011C
Enable DMA1
Enable/disable DMA1.
**/
UINT8 PcdEnableDma1;
/** Offset 0x011D
Enable I2C0
Enable/disable I2C0.
**/
UINT8 PcdEnableI2C0;
/** Offset 0x011E
Enable I2C1
Enable/disable I2C1.
**/
UINT8 PcdEnableI2C1;
/** Offset 0x011F
Enable I2C2
Enable/disable I2C2.
**/
UINT8 PcdEnableI2C2;
/** Offset 0x0120
Enable I2C3
Enable/disable I2C3.
**/
UINT8 PcdEnableI2C3;
/** Offset 0x0121
Enable I2C4
Enable/disable I2C4.
**/
UINT8 PcdEnableI2C4;
/** Offset 0x0122
Enable I2C5
Enable/disable I2C5.
**/
UINT8 PcdEnableI2C5;
/** Offset 0x0123
Enable I2C6
Enable/disable I2C6.
**/
UINT8 PcdEnableI2C6;
/** Offset 0x0124
**/
UINT32 GraphicsConfigPtr;
/** Offset 0x0128
**/
BL_GPIO_FAMILY_INIT* GpioFamilyInitTablePtr;
/** Offset 0x012C
**/
BL_GPIO_PAD_INIT* GpioPadInitTablePtr;
/** Offset 0x0130
**/
UINT8 PunitPwrConfigDisable;
/** Offset 0x0131
**/
UINT8 ChvSvidConfig;
/** Offset 0x0132
**/
UINT8 DptfDisable;
/** Offset 0x0133
eMMC Mode
EMMC Mode
**/
UINT8 PcdEmmcMode;
/** Offset 0x0134
**/
UINT8 PcdUsb3ClkSsc;
/** Offset 0x0135
**/
UINT8 PcdDispClkSsc;
/** Offset 0x0136
**/
UINT8 PcdSataClkSsc;
/** Offset 0x0137
**/
UINT8 Usb2Port0PerPortPeTxiSet;
/** Offset 0x0138
**/
UINT8 Usb2Port0PerPortTxiSet;
/** Offset 0x0139
**/
UINT8 Usb2Port0IUsbTxEmphasisEn;
/** Offset 0x013A
**/
UINT8 Usb2Port0PerPortTxPeHalf;
/** Offset 0x013B
**/
UINT8 Usb2Port1PerPortPeTxiSet;
/** Offset 0x013C
**/
UINT8 Usb2Port1PerPortTxiSet;
/** Offset 0x013D
**/
UINT8 Usb2Port1IUsbTxEmphasisEn;
/** Offset 0x013E
**/
UINT8 Usb2Port1PerPortTxPeHalf;
/** Offset 0x013F
**/
UINT8 Usb2Port2PerPortPeTxiSet;
/** Offset 0x0140
**/
UINT8 Usb2Port2PerPortTxiSet;
/** Offset 0x0141
**/
UINT8 Usb2Port2IUsbTxEmphasisEn;
/** Offset 0x0142
**/
UINT8 Usb2Port2PerPortTxPeHalf;
/** Offset 0x0143
**/
UINT8 Usb2Port3PerPortPeTxiSet;
/** Offset 0x0144
**/
UINT8 Usb2Port3PerPortTxiSet;
/** Offset 0x0145
**/
UINT8 Usb2Port3IUsbTxEmphasisEn;
/** Offset 0x0146
**/
UINT8 Usb2Port3PerPortTxPeHalf;
/** Offset 0x0147
**/
UINT8 Usb2Port4PerPortPeTxiSet;
/** Offset 0x0148
**/
UINT8 Usb2Port4PerPortTxiSet;
/** Offset 0x0149
**/
UINT8 Usb2Port4IUsbTxEmphasisEn;
/** Offset 0x014A
**/
UINT8 Usb2Port4PerPortTxPeHalf;
/** Offset 0x014B
**/
UINT8 Usb3Lane0Ow2tapgen2deemph3p5;
/** Offset 0x014C
**/
UINT8 Usb3Lane1Ow2tapgen2deemph3p5;
/** Offset 0x014D
**/
UINT8 Usb3Lane2Ow2tapgen2deemph3p5;
/** Offset 0x014E
**/
UINT8 Usb3Lane3Ow2tapgen2deemph3p5;
/** Offset 0x014F
SATA Interface Speed
Select SATA controller Interface Speed.
**/
UINT8 PcdSataInterfaceSpeed;
/** Offset 0x0150
**/
UINT8 PcdPchUsbSsicPort;
/** Offset 0x0151
**/
UINT8 PcdPchUsbHsicPort;
/** Offset 0x0152
**/
UINT8 PcdPcieRootPortSpeed;
/** Offset 0x0153
**/
UINT8 PcdPchSsicEnable;
/** Offset 0x0154
**/
UINT32 PcdLogoPtr;
/** Offset 0x0158
**/
UINT32 PcdLogoSize;
/** Offset 0x015C
**/
UINT8 PcdRtcLock;
/** Offset 0x015D
PMIC I2c Bus Number
I2c Bus Number to communicate with PMIC
**/
UINT8 PMIC_I2CBus;
/** Offset 0x015E
Enable ISP
Enable/disable ISP.
**/
UINT8 ISPEnable;
/** Offset 0x015F
Select ISP Device Number
Select ISP PCI Device Configuration
**/
UINT8 ISPPciDevConfig;
/** Offset 0x0160
Processor Turbo Mode
Enable/disable Processor Turbo Mode.
**/
UINT8 PcdTurboMode;
/** Offset 0x0161
Pnp-Power & Performance
select Pnp type
**/
UINT8 PcdPnpSettings;
/** Offset 0x0162
SdDetectChk
Check for Sd card detect
**/
UINT8 PcdSdDetectChk;
/** Offset 0x0163
**/
UINT8 ReservedSiliconInitUpd[411];
} SILICON_INIT_UPD;
#define FSP_UPD_SIGNATURE 0x2444505557534224 /* '$BSWUPD$' */
#define FSP_MEMORY_INIT_UPD_SIGNATURE 0x244450554D454D24 /* '$MEMUPD$' */
#define FSP_SILICON_INIT_UPD_SIGNATURE 0x244450555F495324 /* '$SI_UPD$' */
typedef struct _UPD_DATA_REGION {
/** Offset 0x0000
**/
UINT64 Signature;
/** Offset 0x0008
**/
UINT8 Revision;
/** Offset 0x0009
**/
UINT8 UnusedUpdSpace0[7];
/** Offset 0x0010
**/
UINT32 MemoryInitUpdOffset;
/** Offset 0x0014
**/
UINT32 SiliconInitUpdOffset;
/** Offset 0x0018
**/
UINT64 UnusedUpdSpace1;
/** Offset 0x0020
**/
MEMORY_INIT_UPD MemoryInitUpd;
/** Offset 0x0100
**/
SILICON_INIT_UPD SiliconInitUpd;
/** Offset 0x02FE
**/
UINT16 PcdRegionTerminator;
} UPD_DATA_REGION;
#define FSP_IMAGE_ID 0x2450534657534224 /* '$BSWFSP$' */
#define FSP_IMAGE_REV 0x01010200
typedef struct _VPD_DATA_REGION {
/** Offset 0x0000
**/
UINT64 PcdVpdRegionSign;
/** Offset 0x0008
PcdImageRevision
**/
UINT32 PcdImageRevision;
/** Offset 0x000C
**/
UINT32 PcdUpdRegionOffset;
} VPD_DATA_REGION;
#pragma pack()
#endif

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/**
Copyright (C) 2015, Intel Corporation
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
**/
/** \file fsp.h
*
*
*/
#ifndef __FSP_H__
#include "fsp_types.h"
#include "fsp_fv.h"
#include "fsp_ffs.h"
#include "fsp_api.h"
#include "fsp_hob.h"
#include "fsp_platform.h"
#include "fsp_infoheader.h"
#include "fsp_bootmode.h"
#include "FspUpdVpd.h"
#include "fsp_support.h"
#endif

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/** @file
Copyright (C) 2013, Intel Corporation
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
**/
#ifndef __FSP_API_H__
#define __FSP_API_H__
///
/// FSP Init continuation function prototype.
/// Control will be returned to this callback function after FspInit API call.
///
typedef VOID (FSPAPI *CONTINUATION_PROC) (EFI_STATUS Status, VOID *HobListPtr);
#pragma pack(1)
typedef struct {
///
/// Non-volatile storage buffer pointer.
///
VOID *NvsBufferPtr;
///
/// Runtime buffer pointer
///
VOID *RtBufferPtr;
///
/// Continuation function address
///
CONTINUATION_PROC ContinuationFunc;
} FSP_INIT_PARAMS;
typedef struct {
///
/// Stack top pointer used by the bootloader.
/// The new stack frame will be set up at this location after FspInit API call.
///
UINT32 *StackTop;
///
/// Current system boot mode.
///
UINT32 BootMode;
///
/// User platform configuraiton data region pointer.
///
VOID *UpdDataRgnPtr;
///
/// Reserved
///
UINT32 Reserved[7];
} FSP_INIT_RT_COMMON_BUFFER;
typedef enum {
///
/// Notification code for post PCI enuermation
///
EnumInitPhaseAfterPciEnumeration = 0x20,
///
/// Notification code before transfering control to the payload
///
EnumInitPhaseReadyToBoot = 0x40
} FSP_INIT_PHASE;
typedef struct {
///
/// Notification phase used for NotifyPhase API
///
FSP_INIT_PHASE Phase;
} NOTIFY_PHASE_PARAMS;
#pragma pack()
///
/// FspInit API function prototype
///
typedef FSP_STATUS (FSPAPI *FSP_FSP_INIT) (FSP_INIT_PARAMS *FspInitParamPtr);
///
/// NotifyPhase API function prototype
///
typedef FSP_STATUS (FSPAPI *FSP_NOTFY_PHASE) (NOTIFY_PHASE_PARAMS *NotifyPhaseParamPtr);
#endif

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/** @file
Copyright (C) 2013, Intel Corporation
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
**/
#ifndef __FSP_BOOT_MODE_H__
#define __FSP_BOOT_MODE_H__
///
/// EFI boot mode
///
typedef UINT32 EFI_BOOT_MODE;
//
// 0x21 - 0xf..f are reserved.
//
#define BOOT_WITH_FULL_CONFIGURATION 0x00
#define BOOT_ON_S3_RESUME 0x11
#endif

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/** @file
Copyright (C) 2013, Intel Corporation
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
**/
#ifndef __FSP_FFS_H__
#define __FSP_FFS_H__
#pragma pack(1)
///
/// Used to verify the integrity of the file.
///
typedef union {
struct {
///
/// The IntegrityCheck.Checksum.Header field is an 8-bit checksum of the file
/// header. The State and IntegrityCheck.Checksum.File fields are assumed
/// to be zero and the checksum is calculated such that the entire header sums to zero.
///
UINT8 Header;
///
/// If the FFS_ATTRIB_CHECKSUM (see definition below) bit of the Attributes
/// field is set to one, the IntegrityCheck.Checksum.File field is an 8-bit
/// checksum of the file data.
/// If the FFS_ATTRIB_CHECKSUM bit of the Attributes field is cleared to zero,
/// the IntegrityCheck.Checksum.File field must be initialized with a value of
/// 0xAA. The IntegrityCheck.Checksum.File field is valid any time the
/// EFI_FILE_DATA_VALID bit is set in the State field.
///
UINT8 File;
} Checksum;
///
/// This is the full 16 bits of the IntegrityCheck field.
///
UINT16 Checksum16;
} EFI_FFS_INTEGRITY_CHECK;
///
/// FFS_FIXED_CHECKSUM is the checksum value used when the
/// FFS_ATTRIB_CHECKSUM attribute bit is clear.
///
#define FFS_FIXED_CHECKSUM 0xAA
typedef UINT8 EFI_FV_FILETYPE;
typedef UINT8 EFI_FFS_FILE_ATTRIBUTES;
typedef UINT8 EFI_FFS_FILE_STATE;
///
/// File Types Definitions
///
#define EFI_FV_FILETYPE_ALL 0x00
#define EFI_FV_FILETYPE_RAW 0x01
#define EFI_FV_FILETYPE_FREEFORM 0x02
#define EFI_FV_FILETYPE_SECURITY_CORE 0x03
#define EFI_FV_FILETYPE_PEI_CORE 0x04
#define EFI_FV_FILETYPE_DXE_CORE 0x05
#define EFI_FV_FILETYPE_PEIM 0x06
#define EFI_FV_FILETYPE_DRIVER 0x07
#define EFI_FV_FILETYPE_COMBINED_PEIM_DRIVER 0x08
#define EFI_FV_FILETYPE_APPLICATION 0x09
#define EFI_FV_FILETYPE_SMM 0x0A
#define EFI_FV_FILETYPE_FIRMWARE_VOLUME_IMAGE 0x0B
#define EFI_FV_FILETYPE_COMBINED_SMM_DXE 0x0C
#define EFI_FV_FILETYPE_SMM_CORE 0x0D
#define EFI_FV_FILETYPE_OEM_MIN 0xc0
#define EFI_FV_FILETYPE_OEM_MAX 0xdf
#define EFI_FV_FILETYPE_DEBUG_MIN 0xe0
#define EFI_FV_FILETYPE_DEBUG_MAX 0xef
#define EFI_FV_FILETYPE_FFS_MIN 0xf0
#define EFI_FV_FILETYPE_FFS_MAX 0xff
#define EFI_FV_FILETYPE_FFS_PAD 0xf0
///
/// FFS File Attributes.
///
#define FFS_ATTRIB_LARGE_FILE 0x01
#define FFS_ATTRIB_FIXED 0x04
#define FFS_ATTRIB_DATA_ALIGNMENT 0x38
#define FFS_ATTRIB_CHECKSUM 0x40
///
/// FFS File State Bits.
///
#define EFI_FILE_HEADER_CONSTRUCTION 0x01
#define EFI_FILE_HEADER_VALID 0x02
#define EFI_FILE_DATA_VALID 0x04
#define EFI_FILE_MARKED_FOR_UPDATE 0x08
#define EFI_FILE_DELETED 0x10
#define EFI_FILE_HEADER_INVALID 0x20
///
/// Each file begins with the header that describe the
/// contents and state of the files.
///
typedef struct {
///
/// This GUID is the file name. It is used to uniquely identify the file.
///
EFI_GUID Name;
///
/// Used to verify the integrity of the file.
///
EFI_FFS_INTEGRITY_CHECK IntegrityCheck;
///
/// Identifies the type of file.
///
EFI_FV_FILETYPE Type;
///
/// Declares various file attribute bits.
///
EFI_FFS_FILE_ATTRIBUTES Attributes;
///
/// The length of the file in bytes, including the FFS header.
///
UINT8 Size[3];
///
/// Used to track the state of the file throughout the life of the file from creation to deletion.
///
EFI_FFS_FILE_STATE State;
} EFI_FFS_FILE_HEADER;
typedef struct {
///
/// This GUID is the file name. It is used to uniquely identify the file. There may be only
/// one instance of a file with the file name GUID of Name in any given firmware
/// volume, except if the file type is EFI_FV_FILETYPE_FFS_PAD.
///
EFI_GUID Name;
///
/// Used to verify the integrity of the file.
///
EFI_FFS_INTEGRITY_CHECK IntegrityCheck;
///
/// Identifies the type of file.
///
EFI_FV_FILETYPE Type;
///
/// Declares various file attribute bits.
///
EFI_FFS_FILE_ATTRIBUTES Attributes;
///
/// The length of the file in bytes, including the FFS header.
/// The length of the file data is either (Size - sizeof(EFI_FFS_FILE_HEADER)). This calculation means a
/// zero-length file has a Size of 24 bytes, which is sizeof(EFI_FFS_FILE_HEADER).
/// Size is not required to be a multiple of 8 bytes. Given a file F, the next file header is
/// located at the next 8-byte aligned firmware volume offset following the last byte of the file F.
///
UINT8 Size[3];
///
/// Used to track the state of the file throughout the life of the file from creation to deletion.
///
EFI_FFS_FILE_STATE State;
///
/// If FFS_ATTRIB_LARGE_FILE is set in Attributes, then ExtendedSize exists and Size must be set to zero.
/// If FFS_ATTRIB_LARGE_FILE is not set then EFI_FFS_FILE_HEADER is used.
///
UINT32 ExtendedSize;
} EFI_FFS_FILE_HEADER2;
#define IS_FFS_FILE2(FfsFileHeaderPtr) \
(((((EFI_FFS_FILE_HEADER *) (UINTN) FfsFileHeaderPtr)->Attributes) & FFS_ATTRIB_LARGE_FILE) == FFS_ATTRIB_LARGE_FILE)
#define FFS_FILE_SIZE(FfsFileHeaderPtr) \
((UINT32) (*((UINT32 *) ((EFI_FFS_FILE_HEADER *) (UINTN) FfsFileHeaderPtr)->Size) & 0x00ffffff))
#define FFS_FILE2_SIZE(FfsFileHeaderPtr) \
(((EFI_FFS_FILE_HEADER2 *) (UINTN) FfsFileHeaderPtr)->ExtendedSize)
typedef UINT8 EFI_SECTION_TYPE;
///
/// Pseudo type. It is used as a wild card when retrieving sections.
/// The section type EFI_SECTION_ALL matches all section types.
///
#define EFI_SECTION_ALL 0x00
///
/// Encapsulation section Type values.
///
#define EFI_SECTION_COMPRESSION 0x01
#define EFI_SECTION_GUID_DEFINED 0x02
#define EFI_SECTION_DISPOSABLE 0x03
///
/// Leaf section Type values.
///
#define EFI_SECTION_PE32 0x10
#define EFI_SECTION_PIC 0x11
#define EFI_SECTION_TE 0x12
#define EFI_SECTION_DXE_DEPEX 0x13
#define EFI_SECTION_VERSION 0x14
#define EFI_SECTION_USER_INTERFACE 0x15
#define EFI_SECTION_COMPATIBILITY16 0x16
#define EFI_SECTION_FIRMWARE_VOLUME_IMAGE 0x17
#define EFI_SECTION_FREEFORM_SUBTYPE_GUID 0x18
#define EFI_SECTION_RAW 0x19
#define EFI_SECTION_PEI_DEPEX 0x1B
#define EFI_SECTION_SMM_DEPEX 0x1C
///
/// Common section header.
///
typedef struct {
///
/// A 24-bit unsigned integer that contains the total size of the section in bytes,
/// including the EFI_COMMON_SECTION_HEADER.
///
UINT8 Size[3];
EFI_SECTION_TYPE Type;
///
/// Declares the section type.
///
} EFI_COMMON_SECTION_HEADER;
typedef struct {
///
/// A 24-bit unsigned integer that contains the total size of the section in bytes,
/// including the EFI_COMMON_SECTION_HEADER.
///
UINT8 Size[3];
EFI_SECTION_TYPE Type;
///
/// If Size is 0xFFFFFF, then ExtendedSize contains the size of the section. If
/// Size is not equal to 0xFFFFFF, then this field does not exist.
///
UINT32 ExtendedSize;
} EFI_COMMON_SECTION_HEADER2;
///
/// Leaf section type that contains an
/// IA-32 16-bit executable image.
///
typedef EFI_COMMON_SECTION_HEADER EFI_COMPATIBILITY16_SECTION;
typedef EFI_COMMON_SECTION_HEADER2 EFI_COMPATIBILITY16_SECTION2;
///
/// CompressionType of EFI_COMPRESSION_SECTION.
///
#define EFI_NOT_COMPRESSED 0x00
#define EFI_STANDARD_COMPRESSION 0x01
///
/// An encapsulation section type in which the
/// section data is compressed.
///
typedef struct {
///
/// Usual common section header. CommonHeader.Type = EFI_SECTION_COMPRESSION.
///
EFI_COMMON_SECTION_HEADER CommonHeader;
///
/// The UINT32 that indicates the size of the section data after decompression.
///
UINT32 UncompressedLength;
///
/// Indicates which compression algorithm is used.
///
UINT8 CompressionType;
} EFI_COMPRESSION_SECTION;
typedef struct {
///
/// Usual common section header. CommonHeader.Type = EFI_SECTION_COMPRESSION.
///
EFI_COMMON_SECTION_HEADER2 CommonHeader;
///
/// UINT32 that indicates the size of the section data after decompression.
///
UINT32 UncompressedLength;
///
/// Indicates which compression algorithm is used.
///
UINT8 CompressionType;
} EFI_COMPRESSION_SECTION2;
///
/// An encapsulation section type in which the section data is disposable.
/// A disposable section is an encapsulation section in which the section data may be disposed of during
/// the process of creating or updating a firmware image without significant impact on the usefulness of
/// the file. The Type field in the section header is set to EFI_SECTION_DISPOSABLE. This
/// allows optional or descriptive data to be included with the firmware file which can be removed in
/// order to conserve space. The contents of this section are implementation specific, but might contain
/// debug data or detailed integration instructions.
///
typedef EFI_COMMON_SECTION_HEADER EFI_DISPOSABLE_SECTION;
typedef EFI_COMMON_SECTION_HEADER2 EFI_DISPOSABLE_SECTION2;
///
/// The leaf section which could be used to determine the dispatch order of DXEs.
///
typedef EFI_COMMON_SECTION_HEADER EFI_DXE_DEPEX_SECTION;
typedef EFI_COMMON_SECTION_HEADER2 EFI_DXE_DEPEX_SECTION2;
///
/// The leaf section which contains a PI FV.
///
typedef EFI_COMMON_SECTION_HEADER EFI_FIRMWARE_VOLUME_IMAGE_SECTION;
typedef EFI_COMMON_SECTION_HEADER2 EFI_FIRMWARE_VOLUME_IMAGE_SECTION2;
///
/// The leaf section which contains a single GUID.
///
typedef struct {
///
/// Common section header. CommonHeader.Type = EFI_SECTION_FREEFORM_SUBTYPE_GUID.
///
EFI_COMMON_SECTION_HEADER CommonHeader;
///
/// This GUID is defined by the creator of the file. It is a vendor-defined file type.
///
EFI_GUID SubTypeGuid;
} EFI_FREEFORM_SUBTYPE_GUID_SECTION;
typedef struct {
///
/// The common section header. CommonHeader.Type = EFI_SECTION_FREEFORM_SUBTYPE_GUID.
///
EFI_COMMON_SECTION_HEADER2 CommonHeader;
///
/// This GUID is defined by the creator of the file. It is a vendor-defined file type.
///
EFI_GUID SubTypeGuid;
} EFI_FREEFORM_SUBTYPE_GUID_SECTION2;
///
/// Attributes of EFI_GUID_DEFINED_SECTION.
///
#define EFI_GUIDED_SECTION_PROCESSING_REQUIRED 0x01
#define EFI_GUIDED_SECTION_AUTH_STATUS_VALID 0x02
///
/// The leaf section which is encapsulation defined by specific GUID.
///
typedef struct {
///
/// The common section header. CommonHeader.Type = EFI_SECTION_GUID_DEFINED.
///
EFI_COMMON_SECTION_HEADER CommonHeader;
///
/// The GUID that defines the format of the data that follows. It is a vendor-defined section type.
///
EFI_GUID SectionDefinitionGuid;
///
/// Contains the offset in bytes from the beginning of the common header to the first byte of the data.
///
UINT16 DataOffset;
///
/// The bit field that declares some specific characteristics of the section contents.
///
UINT16 Attributes;
} EFI_GUID_DEFINED_SECTION;
typedef struct {
///
/// The common section header. CommonHeader.Type = EFI_SECTION_GUID_DEFINED.
///
EFI_COMMON_SECTION_HEADER2 CommonHeader;
///
/// The GUID that defines the format of the data that follows. It is a vendor-defined section type.
///
EFI_GUID SectionDefinitionGuid;
///
/// Contains the offset in bytes from the beginning of the common header to the first byte of the data.
///
UINT16 DataOffset;
///
/// The bit field that declares some specific characteristics of the section contents.
///
UINT16 Attributes;
} EFI_GUID_DEFINED_SECTION2;
///
/// The leaf section which contains PE32+ image.
///
typedef EFI_COMMON_SECTION_HEADER EFI_PE32_SECTION;
typedef EFI_COMMON_SECTION_HEADER2 EFI_PE32_SECTION2;
///
/// The leaf section used to determine the dispatch order of PEIMs.
///
typedef EFI_COMMON_SECTION_HEADER EFI_PEI_DEPEX_SECTION;
typedef EFI_COMMON_SECTION_HEADER2 EFI_PEI_DEPEX_SECTION2;
///
/// A leaf section type that contains a position-independent-code (PIC) image.
/// A PIC image section is a leaf section that contains a position-independent-code (PIC) image.
/// In addition to normal PE32+ images that contain relocation information, PEIM executables may be
/// PIC and are referred to as PIC images. A PIC image is the same as a PE32+ image except that all
/// relocation information has been stripped from the image and the image can be moved and will
/// execute correctly without performing any relocation or other fix-ups. EFI_PIC_SECTION2 must
/// be used if the section is 16MB or larger.
///
typedef EFI_COMMON_SECTION_HEADER EFI_PIC_SECTION;
typedef EFI_COMMON_SECTION_HEADER2 EFI_PIC_SECTION2;
///
/// The leaf section which constains the position-independent-code image.
///
typedef EFI_COMMON_SECTION_HEADER EFI_TE_SECTION;
typedef EFI_COMMON_SECTION_HEADER2 EFI_TE_SECTION2;
///
/// The leaf section which contains an array of zero or more bytes.
///
typedef EFI_COMMON_SECTION_HEADER EFI_RAW_SECTION;
typedef EFI_COMMON_SECTION_HEADER2 EFI_RAW_SECTION2;
///
/// The SMM dependency expression section is a leaf section that contains a dependency expression that
/// is used to determine the dispatch order for SMM drivers. Before the SMRAM invocation of the
/// SMM driver's entry point, this dependency expression must evaluate to TRUE. See the Platform
/// Initialization Specification, Volume 2, for details regarding the format of the dependency expression.
/// The dependency expression may refer to protocols installed in either the UEFI or the SMM protocol
/// database. EFI_SMM_DEPEX_SECTION2 must be used if the section is 16MB or larger.
///
typedef EFI_COMMON_SECTION_HEADER EFI_SMM_DEPEX_SECTION;
typedef EFI_COMMON_SECTION_HEADER2 EFI_SMM_DEPEX_SECTION2;
///
/// The leaf section which contains a unicode string that
/// is human readable file name.
///
typedef struct {
EFI_COMMON_SECTION_HEADER CommonHeader;
///
/// Array of unicode string.
///
CHAR16 FileNameString[1];
} EFI_USER_INTERFACE_SECTION;
typedef struct {
EFI_COMMON_SECTION_HEADER2 CommonHeader;
CHAR16 FileNameString[1];
} EFI_USER_INTERFACE_SECTION2;
///
/// The leaf section which contains a numeric build number and
/// an optional unicode string that represents the file revision.
///
typedef struct {
EFI_COMMON_SECTION_HEADER CommonHeader;
UINT16 BuildNumber;
///
/// Array of unicode string.
///
CHAR16 VersionString[1];
} EFI_VERSION_SECTION;
typedef struct {
EFI_COMMON_SECTION_HEADER2 CommonHeader;
///
/// A UINT16 that represents a particular build. Subsequent builds have monotonically
/// increasing build numbers relative to earlier builds.
///
UINT16 BuildNumber;
CHAR16 VersionString[1];
} EFI_VERSION_SECTION2;
#define IS_SECTION2(SectionHeaderPtr) \
((UINT32) (*((UINT32 *) ((EFI_COMMON_SECTION_HEADER *) (UINTN) SectionHeaderPtr)->Size) & 0x00ffffff) == 0x00ffffff)
#define SECTION_SIZE(SectionHeaderPtr) \
((UINT32) (*((UINT32 *) ((EFI_COMMON_SECTION_HEADER *) (UINTN) SectionHeaderPtr)->Size) & 0x00ffffff))
#define SECTION2_SIZE(SectionHeaderPtr) \
(((EFI_COMMON_SECTION_HEADER2 *) (UINTN) SectionHeaderPtr)->ExtendedSize)
#pragma pack()
#endif

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/** @file
Copyright (C) 2013, Intel Corporation
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
**/
#ifndef __FSP_FV___
#define __FSP_FV___
///
/// EFI_FV_FILE_ATTRIBUTES
///
typedef UINT32 EFI_FV_FILE_ATTRIBUTES;
//
// Value of EFI_FV_FILE_ATTRIBUTES.
//
#define EFI_FV_FILE_ATTRIB_ALIGNMENT 0x0000001F
#define EFI_FV_FILE_ATTRIB_FIXED 0x00000100
#define EFI_FV_FILE_ATTRIB_MEMORY_MAPPED 0x00000200
///
/// type of EFI FVB attribute
///
typedef UINT32 EFI_FVB_ATTRIBUTES_2;
//
// Attributes bit definitions
//
#define EFI_FVB2_READ_DISABLED_CAP 0x00000001
#define EFI_FVB2_READ_ENABLED_CAP 0x00000002
#define EFI_FVB2_READ_STATUS 0x00000004
#define EFI_FVB2_WRITE_DISABLED_CAP 0x00000008
#define EFI_FVB2_WRITE_ENABLED_CAP 0x00000010
#define EFI_FVB2_WRITE_STATUS 0x00000020
#define EFI_FVB2_LOCK_CAP 0x00000040
#define EFI_FVB2_LOCK_STATUS 0x00000080
#define EFI_FVB2_STICKY_WRITE 0x00000200
#define EFI_FVB2_MEMORY_MAPPED 0x00000400
#define EFI_FVB2_ERASE_POLARITY 0x00000800
#define EFI_FVB2_READ_LOCK_CAP 0x00001000
#define EFI_FVB2_READ_LOCK_STATUS 0x00002000
#define EFI_FVB2_WRITE_LOCK_CAP 0x00004000
#define EFI_FVB2_WRITE_LOCK_STATUS 0x00008000
#define EFI_FVB2_ALIGNMENT 0x001F0000
#define EFI_FVB2_ALIGNMENT_1 0x00000000
#define EFI_FVB2_ALIGNMENT_2 0x00010000
#define EFI_FVB2_ALIGNMENT_4 0x00020000
#define EFI_FVB2_ALIGNMENT_8 0x00030000
#define EFI_FVB2_ALIGNMENT_16 0x00040000
#define EFI_FVB2_ALIGNMENT_32 0x00050000
#define EFI_FVB2_ALIGNMENT_64 0x00060000
#define EFI_FVB2_ALIGNMENT_128 0x00070000
#define EFI_FVB2_ALIGNMENT_256 0x00080000
#define EFI_FVB2_ALIGNMENT_512 0x00090000
#define EFI_FVB2_ALIGNMENT_1K 0x000A0000
#define EFI_FVB2_ALIGNMENT_2K 0x000B0000
#define EFI_FVB2_ALIGNMENT_4K 0x000C0000
#define EFI_FVB2_ALIGNMENT_8K 0x000D0000
#define EFI_FVB2_ALIGNMENT_16K 0x000E0000
#define EFI_FVB2_ALIGNMENT_32K 0x000F0000
#define EFI_FVB2_ALIGNMENT_64K 0x00100000
#define EFI_FVB2_ALIGNMENT_128K 0x00110000
#define EFI_FVB2_ALIGNMENT_256K 0x00120000
#define EFI_FVB2_ALIGNMENT_512K 0x00130000
#define EFI_FVB2_ALIGNMENT_1M 0x00140000
#define EFI_FVB2_ALIGNMENT_2M 0x00150000
#define EFI_FVB2_ALIGNMENT_4M 0x00160000
#define EFI_FVB2_ALIGNMENT_8M 0x00170000
#define EFI_FVB2_ALIGNMENT_16M 0x00180000
#define EFI_FVB2_ALIGNMENT_32M 0x00190000
#define EFI_FVB2_ALIGNMENT_64M 0x001A0000
#define EFI_FVB2_ALIGNMENT_128M 0x001B0000
#define EFI_FVB2_ALIGNMENT_256M 0x001C0000
#define EFI_FVB2_ALIGNMENT_512M 0x001D0000
#define EFI_FVB2_ALIGNMENT_1G 0x001E0000
#define EFI_FVB2_ALIGNMENT_2G 0x001F0000
typedef struct {
///
/// The number of sequential blocks which are of the same size.
///
UINT32 NumBlocks;
///
/// The size of the blocks.
///
UINT32 Length;
} EFI_FV_BLOCK_MAP_ENTRY;
///
/// Describes the features and layout of the firmware volume.
///
typedef struct {
///
/// The first 16 bytes are reserved to allow for the reset vector of
/// processors whose reset vector is at address 0.
///
UINT8 ZeroVector[16];
///
/// Declares the file system with which the firmware volume is formatted.
///
EFI_GUID FileSystemGuid;
///
/// Length in bytes of the complete firmware volume, including the header.
///
UINT64 FvLength;
///
/// Set to EFI_FVH_SIGNATURE
///
UINT32 Signature;
///
/// Declares capabilities and power-on defaults for the firmware volume.
///
EFI_FVB_ATTRIBUTES_2 Attributes;
///
/// Length in bytes of the complete firmware volume header.
///
UINT16 HeaderLength;
///
/// A 16-bit checksum of the firmware volume header. A valid header sums to zero.
///
UINT16 Checksum;
///
/// Offset, relative to the start of the header, of the extended header
/// (EFI_FIRMWARE_VOLUME_EXT_HEADER) or zero if there is no extended header.
///
UINT16 ExtHeaderOffset;
///
/// This field must always be set to zero.
///
UINT8 Reserved[1];
///
/// Set to 2. Future versions of this specification may define new header fields and will
/// increment the Revision field accordingly.
///
UINT8 Revision;
///
/// An array of run-length encoded FvBlockMapEntry structures. The array is
/// terminated with an entry of {0,0}.
///
EFI_FV_BLOCK_MAP_ENTRY BlockMap[1];
} EFI_FIRMWARE_VOLUME_HEADER;
#define EFI_FVH_SIGNATURE SIGNATURE_32 ('_', 'F', 'V', 'H')
///
/// Firmware Volume Header Revision definition
///
#define EFI_FVH_REVISION 0x02
///
/// Extension header pointed by ExtHeaderOffset of volume header.
///
typedef struct {
///
/// Firmware volume name.
///
EFI_GUID FvName;
///
/// Size of the rest of the extension header, including this structure.
///
UINT32 ExtHeaderSize;
} EFI_FIRMWARE_VOLUME_EXT_HEADER;
///
/// Entry struture for describing FV extension header
///
typedef struct {
///
/// Size of this header extension.
///
UINT16 ExtEntrySize;
///
/// Type of the header.
///
UINT16 ExtEntryType;
} EFI_FIRMWARE_VOLUME_EXT_ENTRY;
#define EFI_FV_EXT_TYPE_OEM_TYPE 0x01
///
/// This extension header provides a mapping between a GUID and an OEM file type.
///
typedef struct {
///
/// Standard extension entry, with the type EFI_FV_EXT_TYPE_OEM_TYPE.
///
EFI_FIRMWARE_VOLUME_EXT_ENTRY Hdr;
///
/// A bit mask, one bit for each file type between 0xC0 (bit 0) and 0xDF (bit 31). If a bit
/// is '1', then the GUID entry exists in Types. If a bit is '0' then no GUID entry exists in Types.
///
UINT32 TypeMask;
///
/// An array of GUIDs, each GUID representing an OEM file type.
///
/// EFI_GUID Types[1];
///
} EFI_FIRMWARE_VOLUME_EXT_ENTRY_OEM_TYPE;
#define EFI_FV_EXT_TYPE_GUID_TYPE 0x0002
///
/// This extension header EFI_FIRMWARE_VOLUME_EXT_ENTRY_GUID_TYPE provides a vendor specific
/// GUID FormatType type which includes a length and a successive series of data bytes.
///
typedef struct {
///
/// Standard extension entry, with the type EFI_FV_EXT_TYPE_OEM_TYPE.
///
EFI_FIRMWARE_VOLUME_EXT_ENTRY Hdr;
///
/// Vendor-specific GUID.
///
EFI_GUID FormatType;
///
/// An arry of bytes of length Length.
///
/// UINT8 Data[1];
///
} EFI_FIRMWARE_VOLUME_EXT_ENTRY_GUID_TYPE;
#endif

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/**
Copyright (C) 2013, Intel Corporation
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
**/
#ifndef __FSP_HOB_H__
#define __FSP_HOB_H__
//
// HobType of EFI_HOB_GENERIC_HEADER.
//
#define EFI_HOB_TYPE_MEMORY_ALLOCATION 0x0002
#define EFI_HOB_TYPE_RESOURCE_DESCRIPTOR 0x0003
#define EFI_HOB_TYPE_GUID_EXTENSION 0x0004
#define EFI_HOB_TYPE_UNUSED 0xFFFE
#define EFI_HOB_TYPE_END_OF_HOB_LIST 0xFFFF
///
/// Describes the format and size of the data inside the HOB.
/// All HOBs must contain this generic HOB header.
///
typedef struct {
///
/// Identifies the HOB data structure type.
///
UINT16 HobType;
///
/// The length in bytes of the HOB.
///
UINT16 HobLength;
///
/// This field must always be set to zero.
///
UINT32 Reserved;
} EFI_HOB_GENERIC_HEADER;
///
/// Enumeration of memory types introduced in UEFI.
///
typedef enum {
///
/// Not used.
///
EfiReservedMemoryType,
///
/// The code portions of a loaded application.
/// (Note that UEFI OS loaders are UEFI applications.)
///
EfiLoaderCode,
///
/// The data portions of a loaded application and the default data allocation
/// type used by an application to allocate pool memory.
///
EfiLoaderData,
///
/// The code portions of a loaded Boot Services Driver.
///
EfiBootServicesCode,
///
/// The data portions of a loaded Boot Serves Driver, and the default data
/// allocation type used by a Boot Services Driver to allocate pool memory.
///
EfiBootServicesData,
///
/// The code portions of a loaded Runtime Services Driver.
///
EfiRuntimeServicesCode,
///
/// The data portions of a loaded Runtime Services Driver and the default
/// data allocation type used by a Runtime Services Driver to allocate pool memory.
///
EfiRuntimeServicesData,
///
/// Free (unallocated) memory.
///
EfiConventionalMemory,
///
/// Memory in which errors have been detected.
///
EfiUnusableMemory,
///
/// Memory that holds the ACPI tables.
///
EfiACPIReclaimMemory,
///
/// Address space reserved for use by the firmware.
///
EfiACPIMemoryNVS,
///
/// Used by system firmware to request that a memory-mapped IO region
/// be mapped by the OS to a virtual address so it can be accessed by EFI runtime services.
///
EfiMemoryMappedIO,
///
/// System memory-mapped IO region that is used to translate memory
/// cycles to IO cycles by the processor.
///
EfiMemoryMappedIOPortSpace,
///
/// Address space reserved by the firmware for code that is part of the processor.
///
EfiPalCode,
EfiMaxMemoryType
} EFI_MEMORY_TYPE;
///
/// EFI_HOB_MEMORY_ALLOCATION_HEADER describes the
/// various attributes of the logical memory allocation. The type field will be used for
/// subsequent inclusion in the UEFI memory map.
///
typedef struct {
///
/// A GUID that defines the memory allocation region's type and purpose, as well as
/// other fields within the memory allocation HOB. This GUID is used to define the
/// additional data within the HOB that may be present for the memory allocation HOB.
/// Type EFI_GUID is defined in InstallProtocolInterface() in the UEFI 2.0
/// specification.
///
EFI_GUID Name;
///
/// The base address of memory allocated by this HOB. Type
/// EFI_PHYSICAL_ADDRESS is defined in AllocatePages() in the UEFI 2.0
/// specification.
///
EFI_PHYSICAL_ADDRESS MemoryBaseAddress;
///
/// The length in bytes of memory allocated by this HOB.
///
UINT64 MemoryLength;
///
/// Defines the type of memory allocated by this HOB. The memory type definition
/// follows the EFI_MEMORY_TYPE definition. Type EFI_MEMORY_TYPE is defined
/// in AllocatePages() in the UEFI 2.0 specification.
///
EFI_MEMORY_TYPE MemoryType;
///
/// Padding for Itanium processor family
///
UINT8 Reserved[4];
} EFI_HOB_MEMORY_ALLOCATION_HEADER;
///
/// Describes all memory ranges used during the HOB producer
/// phase that exist outside the HOB list. This HOB type
/// describes how memory is used, not the physical attributes of memory.
///
typedef struct {
///
/// The HOB generic header. Header.HobType = EFI_HOB_TYPE_MEMORY_ALLOCATION.
///
EFI_HOB_GENERIC_HEADER Header;
///
/// An instance of the EFI_HOB_MEMORY_ALLOCATION_HEADER that describes the
/// various attributes of the logical memory allocation.
///
EFI_HOB_MEMORY_ALLOCATION_HEADER AllocDescriptor;
//
// Additional data pertaining to the "Name" Guid memory
// may go here.
//
} EFI_HOB_MEMORY_ALLOCATION;
///
/// The resource type.
///
typedef UINT32 EFI_RESOURCE_TYPE;
//
// Value of ResourceType in EFI_HOB_RESOURCE_DESCRIPTOR.
//
#define EFI_RESOURCE_SYSTEM_MEMORY 0x00000000
#define EFI_RESOURCE_MEMORY_MAPPED_IO 0x00000001
#define EFI_RESOURCE_IO 0x00000002
#define EFI_RESOURCE_FIRMWARE_DEVICE 0x00000003
#define EFI_RESOURCE_MEMORY_MAPPED_IO_PORT 0x00000004
#define EFI_RESOURCE_MEMORY_RESERVED 0x00000005
#define EFI_RESOURCE_IO_RESERVED 0x00000006
#define EFI_RESOURCE_MAX_MEMORY_TYPE 0x00000007
///
/// A type of recount attribute type.
///
typedef UINT32 EFI_RESOURCE_ATTRIBUTE_TYPE;
//
// These types can be ORed together as needed.
//
// The first three enumerations describe settings
//
#define EFI_RESOURCE_ATTRIBUTE_PRESENT 0x00000001
#define EFI_RESOURCE_ATTRIBUTE_INITIALIZED 0x00000002
#define EFI_RESOURCE_ATTRIBUTE_TESTED 0x00000004
//
// The rest of the settings describe capabilities
//
#define EFI_RESOURCE_ATTRIBUTE_SINGLE_BIT_ECC 0x00000008
#define EFI_RESOURCE_ATTRIBUTE_MULTIPLE_BIT_ECC 0x00000010
#define EFI_RESOURCE_ATTRIBUTE_ECC_RESERVED_1 0x00000020
#define EFI_RESOURCE_ATTRIBUTE_ECC_RESERVED_2 0x00000040
#define EFI_RESOURCE_ATTRIBUTE_READ_PROTECTED 0x00000080
#define EFI_RESOURCE_ATTRIBUTE_WRITE_PROTECTED 0x00000100
#define EFI_RESOURCE_ATTRIBUTE_EXECUTION_PROTECTED 0x00000200
#define EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE 0x00000400
#define EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE 0x00000800
#define EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE 0x00001000
#define EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE 0x00002000
#define EFI_RESOURCE_ATTRIBUTE_16_BIT_IO 0x00004000
#define EFI_RESOURCE_ATTRIBUTE_32_BIT_IO 0x00008000
#define EFI_RESOURCE_ATTRIBUTE_64_BIT_IO 0x00010000
#define EFI_RESOURCE_ATTRIBUTE_UNCACHED_EXPORTED 0x00020000
///
/// Describes the resource properties of all fixed,
/// nonrelocatable resource ranges found on the processor
/// host bus during the HOB producer phase.
///
typedef struct {
///
/// The HOB generic header. Header.HobType = EFI_HOB_TYPE_RESOURCE_DESCRIPTOR.
///
EFI_HOB_GENERIC_HEADER Header;
///
/// A GUID representing the owner of the resource. This GUID is used by HOB
/// consumer phase components to correlate device ownership of a resource.
///
EFI_GUID Owner;
///
/// The resource type enumeration as defined by EFI_RESOURCE_TYPE.
///
EFI_RESOURCE_TYPE ResourceType;
///
/// Resource attributes as defined by EFI_RESOURCE_ATTRIBUTE_TYPE.
///
EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttribute;
///
/// The physical start address of the resource region.
///
EFI_PHYSICAL_ADDRESS PhysicalStart;
///
/// The number of bytes of the resource region.
///
UINT64 ResourceLength;
} EFI_HOB_RESOURCE_DESCRIPTOR;
///
/// Allows writers of executable content in the HOB producer phase to
/// maintain and manage HOBs with specific GUID.
///
typedef struct {
///
/// The HOB generic header. Header.HobType = EFI_HOB_TYPE_GUID_EXTENSION.
///
EFI_HOB_GENERIC_HEADER Header;
///
/// A GUID that defines the contents of this HOB.
///
EFI_GUID Name;
//
// Guid specific data goes here
//
} EFI_HOB_GUID_TYPE;
///
/// Union of all the possible HOB Types.
///
typedef union {
EFI_HOB_GENERIC_HEADER *Header;
EFI_HOB_MEMORY_ALLOCATION *MemoryAllocation;
EFI_HOB_RESOURCE_DESCRIPTOR *ResourceDescriptor;
EFI_HOB_GUID_TYPE *Guid;
UINT8 *Raw;
} EFI_PEI_HOB_POINTERS;
/**
Returns the type of a HOB.
This macro returns the HobType field from the HOB header for the
HOB specified by HobStart.
@param HobStart A pointer to a HOB.
@return HobType.
**/
#define GET_HOB_TYPE(HobStart) \
((*(EFI_HOB_GENERIC_HEADER **)&(HobStart))->HobType)
/**
Returns the length, in bytes, of a HOB.
This macro returns the HobLength field from the HOB header for the
HOB specified by HobStart.
@param HobStart A pointer to a HOB.
@return HobLength.
**/
#define GET_HOB_LENGTH(HobStart) \
((*(EFI_HOB_GENERIC_HEADER **)&(HobStart))->HobLength)
/**
Returns a pointer to the next HOB in the HOB list.
This macro returns a pointer to HOB that follows the
HOB specified by HobStart in the HOB List.
@param HobStart A pointer to a HOB.
@return A pointer to the next HOB in the HOB list.
**/
#define GET_NEXT_HOB(HobStart) \
(VOID *)(*(UINT8 **)&(HobStart) + GET_HOB_LENGTH (HobStart))
/**
Determines if a HOB is the last HOB in the HOB list.
This macro determine if the HOB specified by HobStart is the
last HOB in the HOB list. If HobStart is last HOB in the HOB list,
then TRUE is returned. Otherwise, FALSE is returned.
@param HobStart A pointer to a HOB.
@retval TRUE The HOB specified by HobStart is the last HOB in the HOB list.
@retval FALSE The HOB specified by HobStart is not the last HOB in the HOB list.
**/
#define END_OF_HOB_LIST(HobStart) (GET_HOB_TYPE (HobStart) == (UINT16)EFI_HOB_TYPE_END_OF_HOB_LIST)
/**
Returns a pointer to data buffer from a HOB of type EFI_HOB_TYPE_GUID_EXTENSION.
This macro returns a pointer to the data buffer in a HOB specified by HobStart.
HobStart is assumed to be a HOB of type EFI_HOB_TYPE_GUID_EXTENSION.
@param GuidHob A pointer to a HOB.
@return A pointer to the data buffer in a HOB.
**/
#define GET_GUID_HOB_DATA(HobStart) \
(VOID *)(*(UINT8 **)&(HobStart) + sizeof (EFI_HOB_GUID_TYPE))
/**
Returns the size of the data buffer from a HOB of type EFI_HOB_TYPE_GUID_EXTENSION.
This macro returns the size, in bytes, of the data buffer in a HOB specified by HobStart.
HobStart is assumed to be a HOB of type EFI_HOB_TYPE_GUID_EXTENSION.
@param GuidHob A pointer to a HOB.
@return The size of the data buffer.
**/
#define GET_GUID_HOB_DATA_SIZE(HobStart) \
(UINT16)(GET_HOB_LENGTH (HobStart) - sizeof (EFI_HOB_GUID_TYPE))
/**
FSP specific GUID HOB definitions
**/
#define FSP_INFO_HEADER_GUID \
{ \
0x912740BE, 0x2284, 0x4734, {0xB9, 0x71, 0x84, 0xB0, 0x27, 0x35, 0x3F, 0x0C} \
}
#define FSP_NON_VOLATILE_STORAGE_HOB_GUID \
{ \
0x721acf02, 0x4d77, 0x4c2a, { 0xb3, 0xdc, 0x27, 0xb, 0x7b, 0xa9, 0xe4, 0xb0 } \
}
#define FSP_BOOTLOADER_TEMPORARY_MEMORY_HOB_GUID \
{ \
0xbbcff46c, 0xc8d3, 0x4113, { 0x89, 0x85, 0xb9, 0xd4, 0xf3, 0xb3, 0xf6, 0x4e } \
}
#define FSP_HOB_RESOURCE_OWNER_FSP_GUID \
{ \
0x69a79759, 0x1373, 0x4367, { 0xa6, 0xc4, 0xc7, 0xf5, 0x9e, 0xfd, 0x98, 0x6e } \
}
#define FSP_HOB_RESOURCE_OWNER_TSEG_GUID \
{ \
0xd038747c, 0xd00c, 0x4980, { 0xb3, 0x19, 0x49, 0x01, 0x99, 0xa4, 0x7d, 0x55 } \
}
#define FSP_HOB_RESOURCE_OWNER_GRAPHICS_GUID \
{ \
0x9c7c3aa7, 0x5332, 0x4917, { 0x82, 0xb9, 0x56, 0xa5, 0xf3, 0xe6, 0x2a, 0x07 } \
}
#define FSP_HOB_GRAPHICS_INFO_GUID \
{ 0x39f62cce, 0x6825, 0x4669, { 0xbb, 0x56, 0x54, 0x1a, 0xba, 0x75, 0x3a, 0x07 } }
#endif

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/** @file
Copyright (C) 2013, Intel Corporation
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
**/
#ifndef _FSP_INFO_HEADER_H_
#define _FSP_INFO_HEADER_H_
///
/// Fixed FSP header offset in the FSP image
///
#define FSP_INFO_HEADER_OFF 0x94
#pragma pack(1)
typedef struct {
///
/// Signature ('FSPH') for the FSP Information Header
///
UINT32 Signature;
///
/// Length of the FSP Information Header
///
UINT32 HeaderLength;
///
/// Reserved
///
UINT8 Reserved1[3];
///
/// Revision of the FSP Information Header
///
UINT8 HeaderRevision;
///
/// Revision of the FSP binary
///
UINT32 ImageRevision;
///
/// Signature string that will help match the FSP Binary to a supported
/// hardware configuration.
///
CHAR8 ImageId[8];
///
/// Size of the entire FSP binary
///
UINT32 ImageSize;
///
/// FSP binary preferred base address
///
UINT32 ImageBase;
///
/// Attribute for the FSP binary
///
UINT32 ImageAttribute;
///
/// Offset of the FSP configuration region
///
UINT32 CfgRegionOffset;
///
/// Size of the FSP configuration region
///
UINT32 CfgRegionSize;
///
/// Number of API entries this FSP supports
///
UINT32 ApiEntryNum;
///
/// TempRamInit API entry offset
///
UINT32 TempRamInitEntry;
///
/// FspInit API entry offset
///
UINT32 FspInitEntry;
///
/// NotifyPhase API entry offset
///
UINT32 NotifyPhaseEntry;
///
/// Reserved
///
UINT32 Reserved2;
} FSP_INFO_HEADER;
#pragma pack()
#endif

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@ -0,0 +1,75 @@
/** @file
Copyright (C) 2013, Intel Corporation
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
**/
#ifndef __FSP_PLATFORM_H__
#define __FSP_PLATFORM_H__
#pragma pack(1)
typedef struct {
uint32_t RedMask;
uint32_t GreenMask;
uint32_t BlueMask;
uint32_t ReservedMask;
} EFI_PIXEL_BITMASK;
typedef enum {
PixelRedGreenBlueReserved8BitPerColor,
PixelBlueGreenRedReserved8BitPerColor,
PixelBitMask,
PixelBltOnly,
PixelFormatMax
} EFI_GRAPHICS_PIXEL_FORMAT;
typedef struct {
uint32_t Version;
uint32_t HorizontalResolution;
uint32_t VerticalResolution;
EFI_GRAPHICS_PIXEL_FORMAT PixelFormat;
EFI_PIXEL_BITMASK PixelInformation;
uint32_t PixelsPerScanLine;
} EFI_GRAPHICS_OUTPUT_MODE_INFORMATION;
typedef struct {
EFI_PHYSICAL_ADDRESS FrameBufferBase;
uint32_t FrameBufferSize;
EFI_GRAPHICS_OUTPUT_MODE_INFORMATION GraphicsMode;
} PLATFORM_GRAPHICS_OUTPUT;
typedef struct {
///
/// FSP common runtime data structure
///
FSP_INIT_RT_COMMON_BUFFER Common;
} FSP_INIT_RT_BUFFER;
#pragma pack()
#endif

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@ -0,0 +1,130 @@
/**
Copyright (C) 2013, Intel Corporation
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
**/
/** \file fsp_support.h
*
*
*/
#ifndef __FSP_SUPPORT_H__
#define __FSP_SUPPORT_H__
UINT32
GetPhysicalLowMemTop (
CONST VOID *HobStart
);
UINT32
GetUsableLowMemTop (
CONST VOID *HobListPtr
);
UINT64
GetUsableHighMemTop (
CONST VOID *HobListPtr
);
VOID *
GetGuidHobDataBuffer (
CONST VOID *HobListPtr,
UINT32 *Length,
EFI_GUID *Guid
);
UINT64
GetFspReservedMemoryFromGuid (
CONST VOID *HobListPtr,
UINT64 *FspMemoryLength,
EFI_GUID *FspReservedMemoryGuid
);
UINT32
GetTsegReservedMemory (
CONST VOID *HobListPtr,
UINT32 *Length
);
UINT32
GetFspReservedMemory (
CONST VOID *HobListPtr,
UINT32 *Length
);
VOID*
GetFspNvsDataBuffer (
CONST VOID *HobListPtr,
UINT32 *Length
);
VOID *
GetBootloaderTempMemoryBuffer (
CONST VOID *HobListPtr,
UINT32 *Length
);
VOID *
EFIAPI
GetNextHob (
UINT16 Type,
CONST VOID *HobStart
);
VOID *
EFIAPI
GetFirstHob (
UINT16 Type
);
VOID *
EFIAPI
GetNextGuidHob (
CONST EFI_GUID *Guid,
CONST VOID *HobStart
);
VOID *
EFIAPI
GetFirstGuidHob (
CONST EFI_GUID *Guid
);
VOID
UpdateFspUpdConfigs (
UPD_DATA_REGION *UpdDataRgn
);
VOID *
GetFspGraphicsModeData(
CONST VOID *HobListPtr,
UINT32 *DataSize
);
#endif

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@ -0,0 +1,222 @@
/** @file
Copyright (C) 2013, Intel Corporation
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
**/
#ifndef __FSP_TYPES_H__
#define __FSP_TYPES_H__
///
/// 8-byte unsigned value.
///
typedef unsigned long long UINT64;
///
/// 8-byte signed value.
///
typedef long long INT64;
///
/// 4-byte unsigned value.
///
typedef unsigned int UINT32;
///
/// 4-byte signed value.
///
typedef int INT32;
///
/// 2-byte unsigned value.
///
typedef unsigned short UINT16;
///
/// 2-byte Character.
///
typedef unsigned short CHAR16;
///
/// 2-byte signed value.
///
typedef short INT16;
///
/// Logical Boolean. 1-byte value containing 0 for FALSE or a 1 for TRUE. Other
/// values are undefined.
///
typedef unsigned char BOOLEAN;
///
/// 1-byte unsigned value.
///
typedef unsigned char UINT8;
///
/// 1-byte Character
///
typedef char CHAR8;
///
/// 1-byte signed value
///
typedef char INT8;
///
/// Undeclared type.
///
typedef void VOID;
///
/// 64-bit physical memory address.
///
typedef UINT64 EFI_PHYSICAL_ADDRESS;
///
/// UEFI and FSP defined status.
///
typedef UINT32 EFI_STATUS;
#define FSP_STATUS EFI_STATUS
///
/// Datum is read-only.
///
#define CONST const
///
/// Datum is scoped to the current file or function.
///
#define STATIC static
///
/// Boolean true value. UEFI Specification defines this value to be 1,
/// but this form is more portable.
///
#define TRUE ((BOOLEAN)(1==1))
///
/// Boolean false value. UEFI Specification defines this value to be 0,
/// but this form is more portable.
///
#define FALSE ((BOOLEAN)(0==1))
///
/// Null pointer
///
#ifndef NULL
#define NULL ((VOID *) 0)
#endif
///
/// Modifier to ensure that all API functions use the correct C calling
/// convention.
///
#define EFIAPI __attribute__((cdecl))
#define FSPAPI EFIAPI
///
/// 128 bit buffer containing a unique identifier value.
///
typedef struct {
UINT32 Data1;
UINT16 Data2;
UINT16 Data3;
UINT8 Data4[8];
} EFI_GUID;
/**
Returns a 16-bit signature built from 2 ASCII characters.
This macro returns a 16-bit value built from the two ASCII characters specified
by A and B.
@param A The first ASCII character.
@param B The second ASCII character.
@return A 16-bit value built from the two ASCII characters specified by A and B.
**/
#define SIGNATURE_16(A, B) ((A) | (B << 8))
/**
Returns a 32-bit signature built from 4 ASCII characters.
This macro returns a 32-bit value built from the four ASCII characters specified
by A, B, C, and D.
@param A The first ASCII character.
@param B The second ASCII character.
@param C The third ASCII character.
@param D The fourth ASCII character.
@return A 32-bit value built from the two ASCII characters specified by A, B,
C and D.
**/
#define SIGNATURE_32(A, B, C, D) (SIGNATURE_16 (A, B) | (SIGNATURE_16 (C, D) << 16))
/**
Returns a 64-bit signature built from 8 ASCII characters.
This macro returns a 64-bit value built from the eight ASCII characters specified
by A, B, C, D, E, F, G,and H.
@param A The first ASCII character.
@param B The second ASCII character.
@param C The third ASCII character.
@param D The fourth ASCII character.
@param E The fifth ASCII character.
@param F The sixth ASCII character.
@param G The seventh ASCII character.
@param H The eighth ASCII character.
@return A 64-bit value built from the two ASCII characters specified by A, B,
C, D, E, F, G and H.
**/
#define SIGNATURE_64(A, B, C, D, E, F, G, H) \
(SIGNATURE_32 (A, B, C, D) | ((UINT64) (SIGNATURE_32 (E, F, G, H)) << 32))
///
/// Assertion for debug
///
#define ASSERT(Expression) do { if (!(Expression)) for (;;); } while (FALSE)
///
/// Define FSP API return status code.
/// Compatiable with EFI_STATUS defined in PI Spec.
///
#define FSP_SUCCESS 0
#define FSP_INVALID_PARAMETER 0x80000002
#define FSP_UNSUPPORTED 0x80000003
#define FSP_DEVICE_ERROR 0x80000007
#define FSP_NOT_FOUND 0x8000000E
#define FSP_ALREADY_STARTED 0x80000014
#endif

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@ -0,0 +1,803 @@
/** @file
Boot Setting File for Platform Configuration.
Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
This file is automatically generated. Please do NOT modify !!!
**/
GlobalDataDef
SKUID = 0, "DEFAULT"
EndGlobalData
StructDef
Find "BDX-DE_U"
Skip 24 bytes
$gPlatformFspPkgTokenSpaceGuid_SerialPortType 1 bytes $_DEFAULT_ = 1
$gPlatformFspPkgTokenSpaceGuid_SerialPortAddress 4 bytes $_DEFAULT_ = 0x3F8
$gPlatformFspPkgTokenSpaceGuid_SerialPortConfigure 1 bytes $_DEFAULT_ = 1
$gPlatformFspPkgTokenSpaceGuid_SerialPortBaudRate 1 bytes $_DEFAULT_ = 9
$gPlatformFspPkgTokenSpaceGuid_SerialPortControllerInit0 1 bytes $_DEFAULT_ = 1
$gPlatformFspPkgTokenSpaceGuid_SerialPortControllerInit1 1 bytes $_DEFAULT_ = 0
$gPlatformFspPkgTokenSpaceGuid_ConfigIOU1_PciPort3 1 bytes $_DEFAULT_ = 4
$gPlatformFspPkgTokenSpaceGuid_ConfigIOU2_PciPort1 1 bytes $_DEFAULT_ = 1
$gPlatformFspPkgTokenSpaceGuid_PowerStateAfterG3 1 bytes $_DEFAULT_ = 0
$gPlatformFspPkgTokenSpaceGuid_PchPciPort1 1 bytes $_DEFAULT_ = 1
$gPlatformFspPkgTokenSpaceGuid_PchPciPort2 1 bytes $_DEFAULT_ = 1
$gPlatformFspPkgTokenSpaceGuid_PchPciPort3 1 bytes $_DEFAULT_ = 1
$gPlatformFspPkgTokenSpaceGuid_PchPciPort4 1 bytes $_DEFAULT_ = 1
$gPlatformFspPkgTokenSpaceGuid_PchPciPort5 1 bytes $_DEFAULT_ = 1
$gPlatformFspPkgTokenSpaceGuid_PchPciPort6 1 bytes $_DEFAULT_ = 1
$gPlatformFspPkgTokenSpaceGuid_PchPciPort7 1 bytes $_DEFAULT_ = 1
$gPlatformFspPkgTokenSpaceGuid_PchPciPort8 1 bytes $_DEFAULT_ = 1
$gPlatformFspPkgTokenSpaceGuid_HotPlug_PchPciPort1 1 bytes $_DEFAULT_ = 0
$gPlatformFspPkgTokenSpaceGuid_HotPlug_PchPciPort2 1 bytes $_DEFAULT_ = 0
$gPlatformFspPkgTokenSpaceGuid_HotPlug_PchPciPort3 1 bytes $_DEFAULT_ = 0
$gPlatformFspPkgTokenSpaceGuid_HotPlug_PchPciPort4 1 bytes $_DEFAULT_ = 0
$gPlatformFspPkgTokenSpaceGuid_HotPlug_PchPciPort5 1 bytes $_DEFAULT_ = 0
$gPlatformFspPkgTokenSpaceGuid_HotPlug_PchPciPort6 1 bytes $_DEFAULT_ = 0
$gPlatformFspPkgTokenSpaceGuid_HotPlug_PchPciPort7 1 bytes $_DEFAULT_ = 0
$gPlatformFspPkgTokenSpaceGuid_HotPlug_PchPciPort8 1 bytes $_DEFAULT_ = 0
$gPlatformFspPkgTokenSpaceGuid_Ehci1Enable 1 bytes $_DEFAULT_ = 1
$gPlatformFspPkgTokenSpaceGuid_Ehci2Enable 1 bytes $_DEFAULT_ = 1
$gPlatformFspPkgTokenSpaceGuid_HyperThreading 1 bytes $_DEFAULT_ = 1
$gPlatformFspPkgTokenSpaceGuid_DebugOutputLevel 1 bytes $_DEFAULT_ = 1
$gPlatformFspPkgTokenSpaceGuid_TcoTimerHaltLock 1 bytes $_DEFAULT_ = 1
$gPlatformFspPkgTokenSpaceGuid_TurboMode 1 bytes $_DEFAULT_ = 1
$gPlatformFspPkgTokenSpaceGuid_BootPerfMode 1 bytes $_DEFAULT_ = 1
$gPlatformFspPkgTokenSpaceGuid_PciePort1aAspm 1 bytes $_DEFAULT_ = 7
$gPlatformFspPkgTokenSpaceGuid_PciePort1bAspm 1 bytes $_DEFAULT_ = 7
$gPlatformFspPkgTokenSpaceGuid_PciePort3aAspm 1 bytes $_DEFAULT_ = 7
$gPlatformFspPkgTokenSpaceGuid_PciePort3bAspm 1 bytes $_DEFAULT_ = 7
$gPlatformFspPkgTokenSpaceGuid_PciePort3cAspm 1 bytes $_DEFAULT_ = 7
$gPlatformFspPkgTokenSpaceGuid_PciePort3dAspm 1 bytes $_DEFAULT_ = 7
$gPlatformFspPkgTokenSpaceGuid_PchPciePort1Aspm 1 bytes $_DEFAULT_ = 4
$gPlatformFspPkgTokenSpaceGuid_PchPciePort2Aspm 1 bytes $_DEFAULT_ = 4
$gPlatformFspPkgTokenSpaceGuid_PchPciePort3Aspm 1 bytes $_DEFAULT_ = 4
$gPlatformFspPkgTokenSpaceGuid_PchPciePort4Aspm 1 bytes $_DEFAULT_ = 4
$gPlatformFspPkgTokenSpaceGuid_PchPciePort5Aspm 1 bytes $_DEFAULT_ = 4
$gPlatformFspPkgTokenSpaceGuid_PchPciePort6Aspm 1 bytes $_DEFAULT_ = 4
$gPlatformFspPkgTokenSpaceGuid_PchPciePort7Aspm 1 bytes $_DEFAULT_ = 4
$gPlatformFspPkgTokenSpaceGuid_PchPciePort8Aspm 1 bytes $_DEFAULT_ = 4
$gPlatformFspPkgTokenSpaceGuid_DFXEnable 1 bytes $_DEFAULT_ = 0
$gPlatformFspPkgTokenSpaceGuid_ThermalDeviceEnable 1 bytes $_DEFAULT_ = 0
Skip 88 bytes
$gPlatformFspPkgTokenSpaceGuid_MemEccSupport 1 bytes $_DEFAULT_ = 0x02
$gPlatformFspPkgTokenSpaceGuid_MemDdrMemoryType 1 bytes $_DEFAULT_ = 0x02
$gPlatformFspPkgTokenSpaceGuid_MemRankMultiplication 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_MemRankMarginTool 1 bytes $_DEFAULT_ = 0x02
$gPlatformFspPkgTokenSpaceGuid_MemScrambling 1 bytes $_DEFAULT_ = 0x02
$gPlatformFspPkgTokenSpaceGuid_MemRefreshMode 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_MemMcOdtOverride 1 bytes $_DEFAULT_ = 0x02
$gPlatformFspPkgTokenSpaceGuid_MemCAParity 1 bytes $_DEFAULT_ = 0x02
$gPlatformFspPkgTokenSpaceGuid_MemThermalThrottling 1 bytes $_DEFAULT_ = 0x02
$gPlatformFspPkgTokenSpaceGuid_MemPowerSavingsMode 1 bytes $_DEFAULT_ = 0x05
$gPlatformFspPkgTokenSpaceGuid_MemElectricalThrottling 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_MemPagePolicy 1 bytes $_DEFAULT_ = 0x03
$gPlatformFspPkgTokenSpaceGuid_MemSocketInterleaveBelow4G 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_MemChannelInterleave 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_MemRankInterleave 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_MemDownEnable 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_MemDownCh0Dimm0SpdPtr 4 bytes $_DEFAULT_ = 0x00000000
$gPlatformFspPkgTokenSpaceGuid_MemDownCh0Dimm1SpdPtr 4 bytes $_DEFAULT_ = 0x00000000
$gPlatformFspPkgTokenSpaceGuid_MemDownCh1Dimm0SpdPtr 4 bytes $_DEFAULT_ = 0x00000000
$gPlatformFspPkgTokenSpaceGuid_MemDownCh1Dimm1SpdPtr 4 bytes $_DEFAULT_ = 0x00000000
$gPlatformFspPkgTokenSpaceGuid_MemFastBoot 1 bytes $_DEFAULT_ = 0x01
$gPlatformFspPkgTokenSpaceGuid_pam0_hienable 1 bytes $_DEFAULT_ = 3
$gPlatformFspPkgTokenSpaceGuid_pam1_loenable 1 bytes $_DEFAULT_ = 3
$gPlatformFspPkgTokenSpaceGuid_pam1_hienable 1 bytes $_DEFAULT_ = 3
$gPlatformFspPkgTokenSpaceGuid_pam2_loenable 1 bytes $_DEFAULT_ = 3
$gPlatformFspPkgTokenSpaceGuid_pam2_hienable 1 bytes $_DEFAULT_ = 3
$gPlatformFspPkgTokenSpaceGuid_pam3_loenable 1 bytes $_DEFAULT_ = 3
$gPlatformFspPkgTokenSpaceGuid_pam3_hienable 1 bytes $_DEFAULT_ = 3
$gPlatformFspPkgTokenSpaceGuid_pam4_loenable 1 bytes $_DEFAULT_ = 3
$gPlatformFspPkgTokenSpaceGuid_pam4_hienable 1 bytes $_DEFAULT_ = 3
$gPlatformFspPkgTokenSpaceGuid_pam5_loenable 1 bytes $_DEFAULT_ = 3
$gPlatformFspPkgTokenSpaceGuid_pam5_hienable 1 bytes $_DEFAULT_ = 3
$gPlatformFspPkgTokenSpaceGuid_pam6_loenable 1 bytes $_DEFAULT_ = 3
$gPlatformFspPkgTokenSpaceGuid_pam6_hienable 1 bytes $_DEFAULT_ = 3
$gPlatformFspPkgTokenSpaceGuid_MemAdr 1 bytes $_DEFAULT_ = 0
Skip 1 bytes
$gPlatformFspPkgTokenSpaceGuid_MemBlockScTrafficOnAdr 1 bytes $_DEFAULT_ = 0
$gPlatformFspPkgTokenSpaceGuid_MemPlatformReleaseAdrClampsPort 2 bytes $_DEFAULT_ = 0
$gPlatformFspPkgTokenSpaceGuid_MemPlatformReleaseAdrClampsAnd 4 bytes $_DEFAULT_ = 0xffffffff
$gPlatformFspPkgTokenSpaceGuid_MemPlatformReleaseAdrClampsOr 4 bytes $_DEFAULT_ = 0x00000000
Find "_BDX-DE_"
$gPlatformFspPkgTokenSpaceGuid_PcdImageRevision 4 bytes $_DEFAULT_ = 0x00000301
EndStruct
List &EN_DIS
Selection 0x1 , "Enabled"
Selection 0x0 , "Disabled"
EndList
List &gPlatformFspPkgTokenSpaceGuid_pam6_loenable
Selection 0 , "Read/Write DMI only"
Selection 1 , "Read from DRAM and Write to DMI"
Selection 2 , "Read from DMI and Write to DRAM"
Selection 3 , "Read/Write DRAM only"
EndList
List &gPlatformFspPkgTokenSpaceGuid_pam2_loenable
Selection 0 , "Read/Write DMI only"
Selection 1 , "Read from DRAM and Write to DMI"
Selection 2 , "Read from DMI and Write to DRAM"
Selection 3 , "Read/Write DRAM only"
EndList
List &gPlatformFspPkgTokenSpaceGuid_pam6_hienable
Selection 0 , "Read/Write DMI only"
Selection 1 , "Read from DRAM and Write to DMI"
Selection 2 , "Read from DMI and Write to DRAM"
Selection 3 , "Read/Write DRAM only"
EndList
List &gPlatformFspPkgTokenSpaceGuid_PchPciePort1Aspm
Selection 0 , "Disabled"
Selection 1 , "L0s"
Selection 2 , "L1 Only"
Selection 3 , "L0sL1"
Selection 4 , "Auto"
EndList
List &gPlatformFspPkgTokenSpaceGuid_pam4_loenable
Selection 0 , "Read/Write DMI only"
Selection 1 , "Read from DRAM and Write to DMI"
Selection 2 , "Read from DMI and Write to DRAM"
Selection 3 , "Read/Write DRAM only"
EndList
List &gPlatformFspPkgTokenSpaceGuid_Ehci2Enable
Selection 0 , "Disable"
Selection 1 , "Enable"
EndList
List &gPlatformFspPkgTokenSpaceGuid_MemChannelInterleave
Selection 0 , "Auto"
Selection 1 , "1-Way"
Selection 2 , "2-Way"
Selection 3 , "3-Way"
Selection 4 , "4-Way"
EndList
List &gPlatformFspPkgTokenSpaceGuid_MemScrambling
Selection 0 , "Disabled"
Selection 1 , "Enabled"
Selection 2 , "Auto"
EndList
List &gPlatformFspPkgTokenSpaceGuid_MemEccSupport
Selection 0 , "Disabled"
Selection 1 , "Enabled"
Selection 2 , "Auto"
EndList
List &gPlatformFspPkgTokenSpaceGuid_pam5_hienable
Selection 0 , "Read/Write DMI only"
Selection 1 , "Read from DRAM and Write to DMI"
Selection 2 , "Read from DMI and Write to DRAM"
Selection 3 , "Read/Write DRAM only"
EndList
List &gPlatformFspPkgTokenSpaceGuid_Ehci1Enable
Selection 0 , "Disable"
Selection 1 , "Enable"
EndList
List &gPlatformFspPkgTokenSpaceGuid_pam0_hienable
Selection 0 , "Read/Write DMI only"
Selection 1 , "Read from DRAM and Write to DMI"
Selection 2 , "Read from DMI and Write to DRAM"
Selection 3 , "Read/Write DRAM only"
EndList
List &gPlatformFspPkgTokenSpaceGuid_PciePort1aAspm
Selection 0 , "Disabled"
Selection 2 , "L1 Only"
Selection 7 , "Auto"
EndList
List &gPlatformFspPkgTokenSpaceGuid_PciePort3dAspm
Selection 0 , "Disabled"
Selection 2 , "L1 Only"
Selection 7 , "Auto"
EndList
List &gPlatformFspPkgTokenSpaceGuid_pam1_loenable
Selection 0 , "Read/Write DMI only"
Selection 1 , "Read from DRAM and Write to DMI"
Selection 2 , "Read from DMI and Write to DRAM"
Selection 3 , "Read/Write DRAM only"
EndList
List &gPlatformFspPkgTokenSpaceGuid_PciePort3cAspm
Selection 0 , "Disabled"
Selection 2 , "L1 Only"
Selection 7 , "Auto"
EndList
List &gPlatformFspPkgTokenSpaceGuid_PchPciePort8Aspm
Selection 0 , "Disabled"
Selection 1 , "L0s"
Selection 2 , "L1 Only"
Selection 3 , "L0sL1"
Selection 4 , "Auto"
EndList
List &gPlatformFspPkgTokenSpaceGuid_HyperThreading
Selection 0 , "Disable"
Selection 1 , "Enable"
EndList
List &gPlatformFspPkgTokenSpaceGuid_ConfigIOU1_PciPort3
Selection 0 , "x4x4x4x4"
Selection 1 , "x4x4xxx8"
Selection 2 , "xxx8x4x4"
Selection 3 , "xxx8xxx8"
Selection 4 , "xxxxxx16"
EndList
List &gPlatformFspPkgTokenSpaceGuid_MemElectricalThrottling
Selection 0 , "Disabled"
Selection 1 , "Enabled"
Selection 2 , "Auto"
EndList
List &gPlatformFspPkgTokenSpaceGuid_PchPciePort4Aspm
Selection 0 , "Disabled"
Selection 1 , "L0s"
Selection 2 , "L1 Only"
Selection 3 , "L0sL1"
Selection 4 , "Auto"
EndList
List &gPlatformFspPkgTokenSpaceGuid_MemCAParity
Selection 0 , "Disabled"
Selection 1 , "Enabled"
Selection 2 , "Auto"
EndList
List &gPlatformFspPkgTokenSpaceGuid_PchPciePort2Aspm
Selection 0 , "Disabled"
Selection 1 , "L0s"
Selection 2 , "L1 Only"
Selection 3 , "L0sL1"
Selection 4 , "Auto"
EndList
List &gPlatformFspPkgTokenSpaceGuid_pam2_hienable
Selection 0 , "Read/Write DMI only"
Selection 1 , "Read from DRAM and Write to DMI"
Selection 2 , "Read from DMI and Write to DRAM"
Selection 3 , "Read/Write DRAM only"
EndList
List &gPlatformFspPkgTokenSpaceGuid_PchPciePort6Aspm
Selection 0 , "Disabled"
Selection 1 , "L0s"
Selection 2 , "L1 Only"
Selection 3 , "L0sL1"
Selection 4 , "Auto"
EndList
List &gPlatformFspPkgTokenSpaceGuid_HotPlug_PchPciPort7
Selection 0 , "Disable"
Selection 1 , "Enable"
EndList
List &gPlatformFspPkgTokenSpaceGuid_HotPlug_PchPciPort6
Selection 0 , "Disable"
Selection 1 , "Enable"
EndList
List &gPlatformFspPkgTokenSpaceGuid_HotPlug_PchPciPort5
Selection 0 , "Disable"
Selection 1 , "Enable"
EndList
List &gPlatformFspPkgTokenSpaceGuid_HotPlug_PchPciPort4
Selection 0 , "Disable"
Selection 1 , "Enable"
EndList
List &gPlatformFspPkgTokenSpaceGuid_HotPlug_PchPciPort3
Selection 0 , "Disable"
Selection 1 , "Enable"
EndList
List &gPlatformFspPkgTokenSpaceGuid_HotPlug_PchPciPort2
Selection 0 , "Disable"
Selection 1 , "Enable"
EndList
List &gPlatformFspPkgTokenSpaceGuid_HotPlug_PchPciPort1
Selection 0 , "Disable"
Selection 1 , "Enable"
EndList
List &gPlatformFspPkgTokenSpaceGuid_MemPowerSavingsMode
Selection 0 , "Disabled"
Selection 1 , "Slow"
Selection 2 , "Fast"
Selection 3 , "APD"
Selection 4 , "User"
Selection 5 , "Auto"
EndList
List &gPlatformFspPkgTokenSpaceGuid_pam4_hienable
Selection 0 , "Read/Write DMI only"
Selection 1 , "Read from DRAM and Write to DMI"
Selection 2 , "Read from DMI and Write to DRAM"
Selection 3 , "Read/Write DRAM only"
EndList
List &gPlatformFspPkgTokenSpaceGuid_PchPciePort5Aspm
Selection 0 , "Disabled"
Selection 1 , "L0s"
Selection 2 , "L1 Only"
Selection 3 , "L0sL1"
Selection 4 , "Auto"
EndList
List &gPlatformFspPkgTokenSpaceGuid_SerialPortControllerInit0
Selection 0 , "No"
Selection 1 , "Yes"
EndList
List &gPlatformFspPkgTokenSpaceGuid_SerialPortBaudRate
Selection 8 , "9600"
Selection 9 , "19200"
Selection 10 , "38400*"
Selection 11 , "57600*"
Selection 12 , "115200*"
EndList
List &gPlatformFspPkgTokenSpaceGuid_PchPciPort3
Selection 0 , "Disable"
Selection 1 , "Enable"
EndList
List &gPlatformFspPkgTokenSpaceGuid_PchPciPort2
Selection 0 , "Disable"
Selection 1 , "Enable"
EndList
List &gPlatformFspPkgTokenSpaceGuid_PchPciPort1
Selection 0 , "Disable"
Selection 1 , "Enable"
EndList
List &gPlatformFspPkgTokenSpaceGuid_PchPciPort7
Selection 0 , "Disable"
Selection 1 , "Enable"
EndList
List &gPlatformFspPkgTokenSpaceGuid_PchPciPort6
Selection 0 , "Disable"
Selection 1 , "Enable"
EndList
List &gPlatformFspPkgTokenSpaceGuid_PchPciPort5
Selection 0 , "Disable"
Selection 1 , "Enable"
EndList
List &gPlatformFspPkgTokenSpaceGuid_PchPciPort4
Selection 0 , "Disable"
Selection 1 , "Enable"
EndList
List &gPlatformFspPkgTokenSpaceGuid_ConfigIOU2_PciPort1
Selection 0 , "x4x4"
Selection 1 , "xxx8"
EndList
List &gPlatformFspPkgTokenSpaceGuid_BootPerfMode
Selection 0 , "Maximum Efficiency"
Selection 1 , "Maximum Performance"
EndList
List &gPlatformFspPkgTokenSpaceGuid_PchPciPort8
Selection 0 , "Disable"
Selection 1 , "Enable"
EndList
List &gPlatformFspPkgTokenSpaceGuid_PciePort3aAspm
Selection 0 , "Disabled"
Selection 2 , "L1 Only"
Selection 7 , "Auto"
EndList
List &gPlatformFspPkgTokenSpaceGuid_MemRankMarginTool
Selection 0 , "Disabled"
Selection 1 , "Enabled"
Selection 2 , "Auto"
EndList
List &gPlatformFspPkgTokenSpaceGuid_pam1_hienable
Selection 0 , "Read/Write DMI only"
Selection 1 , "Read from DRAM and Write to DMI"
Selection 2 , "Read from DMI and Write to DRAM"
Selection 3 , "Read/Write DRAM only"
EndList
List &gPlatformFspPkgTokenSpaceGuid_MemRankMultiplication
Selection 0 , "Auto"
Selection 1 , "Enabled"
EndList
List &gPlatformFspPkgTokenSpaceGuid_MemThermalThrottling
Selection 0 , "Disabled"
Selection 1 , "Open-Loop (OLTT)"
Selection 2 , "Closed-Loop (CLTT)"
EndList
List &gPlatformFspPkgTokenSpaceGuid_TurboMode
Selection 0 , "Disable"
Selection 1 , "Enable"
EndList
List &gPlatformFspPkgTokenSpaceGuid_MemFastBoot
Selection 0 , "No"
Selection 1 , "Yes"
EndList
List &gPlatformFspPkgTokenSpaceGuid_PciePort1bAspm
Selection 0 , "Disabled"
Selection 2 , "L1 Only"
Selection 7 , "Auto"
EndList
List &gPlatformFspPkgTokenSpaceGuid_MemDdrMemoryType
Selection 0 , "RDIMMs only"
Selection 1 , "UDIMMs only"
Selection 2 , "UDIMMs and RDIMMs"
EndList
List &gPlatformFspPkgTokenSpaceGuid_MemMcOdtOverride
Selection 0 , "50 Ohms"
Selection 1 , "100 Ohms"
Selection 2 , "Auto"
EndList
List &gPlatformFspPkgTokenSpaceGuid_PchPciePort7Aspm
Selection 0 , "Disabled"
Selection 1 , "L0s"
Selection 2 , "L1 Only"
Selection 3 , "L0sL1"
Selection 4 , "Auto"
EndList
List &gPlatformFspPkgTokenSpaceGuid_pam3_loenable
Selection 0 , "Read/Write DMI only"
Selection 1 , "Read from DRAM and Write to DMI"
Selection 2 , "Read from DMI and Write to DRAM"
Selection 3 , "Read/Write DRAM only"
EndList
List &gPlatformFspPkgTokenSpaceGuid_MemAdr
Selection 0 , "Disabled"
Selection 1 , "Enabled"
Selection 2 , "Enabled (NVDIMMs)"
EndList
List &gPlatformFspPkgTokenSpaceGuid_ThermalDeviceEnable
Selection 0 , "Disabled"
Selection 1 , "Enabled"
EndList
List &gPlatformFspPkgTokenSpaceGuid_MemRankInterleave
Selection 0 , "Auto"
Selection 1 , "1-Way"
Selection 2 , "2-Way"
Selection 4 , "4-Way"
Selection 8 , "8-Way"
EndList
List &gPlatformFspPkgTokenSpaceGuid_MemPagePolicy
Selection 0 , "Open"
Selection 1 , "Closed"
Selection 2 , "Adaptive"
Selection 3 , "Auto"
EndList
List &gPlatformFspPkgTokenSpaceGuid_PowerStateAfterG3
Selection 0 , "S0"
Selection 1 , "S5"
EndList
List &gPlatformFspPkgTokenSpaceGuid_PciePort3bAspm
Selection 0 , "Disabled"
Selection 2 , "L1 Only"
Selection 7 , "Auto"
EndList
List &gPlatformFspPkgTokenSpaceGuid_PchPciePort3Aspm
Selection 0 , "Disabled"
Selection 1 , "L0s"
Selection 2 , "L1 Only"
Selection 3 , "L0sL1"
Selection 4 , "Auto"
EndList
List &gPlatformFspPkgTokenSpaceGuid_DebugOutputLevel
Selection 0 , "Disabled"
Selection 1 , "Minimum"
Selection 2 , "Normal"
Selection 3 , "Maximum"
EndList
List &gPlatformFspPkgTokenSpaceGuid_pam5_loenable
Selection 0 , "Read/Write DMI only"
Selection 1 , "Read from DRAM and Write to DMI"
Selection 2 , "Read from DMI and Write to DRAM"
Selection 3 , "Read/Write DRAM only"
EndList
List &gPlatformFspPkgTokenSpaceGuid_MemRefreshMode
Selection 0 , "Acc Self Refresh"
Selection 1 , "2x Refresh"
EndList
List &gPlatformFspPkgTokenSpaceGuid_MemSocketInterleaveBelow4G
Selection 0 , "Disabled"
Selection 1 , "Enabled"
EndList
List &gPlatformFspPkgTokenSpaceGuid_SerialPortConfigure
Selection 0 , "No"
Selection 1 , "Yes"
EndList
List &gPlatformFspPkgTokenSpaceGuid_MemBlockScTrafficOnAdr
Selection 0 , "Disabled"
Selection 1 , "Enabled"
EndList
List &gPlatformFspPkgTokenSpaceGuid_HotPlug_PchPciPort8
Selection 0 , "Disable"
Selection 1 , "Enable"
EndList
List &gPlatformFspPkgTokenSpaceGuid_TcoTimerHaltLock
Selection 0 , "No"
Selection 1 , "Yes"
EndList
List &gPlatformFspPkgTokenSpaceGuid_SerialPortType
Selection 0 , "None"
Selection 1 , "I/O"
Selection 2 , "MMIO"
EndList
List &gPlatformFspPkgTokenSpaceGuid_pam3_hienable
Selection 0 , "Read/Write DMI only"
Selection 1 , "Read from DRAM and Write to DMI"
Selection 2 , "Read from DMI and Write to DRAM"
Selection 3 , "Read/Write DRAM only"
EndList
List &gPlatformFspPkgTokenSpaceGuid_DFXEnable
Selection 0 , "Disabled"
Selection 1 , "Enabled"
EndList
List &gPlatformFspPkgTokenSpaceGuid_MemDownEnable
Selection 0 , "No"
Selection 1 , "Yes"
EndList
List &gPlatformFspPkgTokenSpaceGuid_SerialPortControllerInit1
Selection 0 , "No"
Selection 1 , "Yes"
EndList
BeginInfoBlock
PPVer "0.1"
Description "Broadwell-DE Platform"
EndInfoBlock
Page "Memory"
Combo $gPlatformFspPkgTokenSpaceGuid_MemEccSupport, "ECC Support", &gPlatformFspPkgTokenSpaceGuid_MemEccSupport,
Help "Enable/disable DDR ECC Support."
Combo $gPlatformFspPkgTokenSpaceGuid_MemDdrMemoryType, "Memory Type", &gPlatformFspPkgTokenSpaceGuid_MemDdrMemoryType,
Help "Select the memory type supported by this platform."
Combo $gPlatformFspPkgTokenSpaceGuid_MemRankMultiplication, "Rank Multiplication", &gPlatformFspPkgTokenSpaceGuid_MemRankMultiplication,
Help "Force the Rank Multiplication factor for LRDIMM."
Combo $gPlatformFspPkgTokenSpaceGuid_MemRankMarginTool, "Rank Margin Tool", &gPlatformFspPkgTokenSpaceGuid_MemRankMarginTool,
Help "Run the Rank Margin Tool after memory training."
Combo $gPlatformFspPkgTokenSpaceGuid_MemScrambling, "Data Scrambling", &gPlatformFspPkgTokenSpaceGuid_MemScrambling,
Help "Enable data scrambling."
Combo $gPlatformFspPkgTokenSpaceGuid_MemRefreshMode, "Refresh Options", &gPlatformFspPkgTokenSpaceGuid_MemRefreshMode,
Help "Self refresh mode."
Combo $gPlatformFspPkgTokenSpaceGuid_MemMcOdtOverride, "MC ODT Mode", &gPlatformFspPkgTokenSpaceGuid_MemMcOdtOverride,
Help "Select MC ODT Mode."
Combo $gPlatformFspPkgTokenSpaceGuid_MemCAParity, "C/A Parity Enable", &gPlatformFspPkgTokenSpaceGuid_MemCAParity,
Help "Enable/Disable DDR4 Command Address Parity"
Combo $gPlatformFspPkgTokenSpaceGuid_MemThermalThrottling, "Set Throttling Mode", &gPlatformFspPkgTokenSpaceGuid_MemThermalThrottling,
Help "Configure Thermal Throttling Mode."
Combo $gPlatformFspPkgTokenSpaceGuid_MemPowerSavingsMode, "Memory Power Savings Mode", &gPlatformFspPkgTokenSpaceGuid_MemPowerSavingsMode,
Help "Configures CKE and related Memory Power Savings Features"
Combo $gPlatformFspPkgTokenSpaceGuid_MemElectricalThrottling, "Mem Electrical Throttling", &gPlatformFspPkgTokenSpaceGuid_MemElectricalThrottling,
Help "Configure Memory Electrical Throttling"
Combo $gPlatformFspPkgTokenSpaceGuid_MemPagePolicy, "Page Policy", &gPlatformFspPkgTokenSpaceGuid_MemPagePolicy,
Help "Select Page Policy"
Combo $gPlatformFspPkgTokenSpaceGuid_MemSocketInterleaveBelow4G, "Socket Interleave Below 4 GB", &gPlatformFspPkgTokenSpaceGuid_MemSocketInterleaveBelow4G,
Help "Splits the 0-4GB address space between two sockets, so that both sockets get a chunk of local memory below 4GB."
Combo $gPlatformFspPkgTokenSpaceGuid_MemChannelInterleave, "Channel Interleaving", &gPlatformFspPkgTokenSpaceGuid_MemChannelInterleave,
Help "Select Channel Interleaving setting."
Combo $gPlatformFspPkgTokenSpaceGuid_MemRankInterleave, "Rank Interleaving", &gPlatformFspPkgTokenSpaceGuid_MemRankInterleave,
Help "Select Rank Interleaving setting."
Combo $gPlatformFspPkgTokenSpaceGuid_MemDownEnable, "Memory Down", &gPlatformFspPkgTokenSpaceGuid_MemDownEnable,
Help "Select 'Yes' if memory is down. If set to 'Yes', at least one of the following SPD data pointers must also be provided."
EditNum $gPlatformFspPkgTokenSpaceGuid_MemDownCh0Dimm0SpdPtr, "Memory Down SPD Data Pointer for Ch0/DIMM0", HEX,
Help "If 'Memory Down' is 'Yes', this is the pointer to the SPD data for Channel 0, DIMM 0. Otherwise, this field is ignored. Specify 0x00000000 if this DIMM is not present."
"Valid range: 0x00000000 ~ 0xFFFFFFFF"
EditNum $gPlatformFspPkgTokenSpaceGuid_MemDownCh0Dimm1SpdPtr, "Memory Down SPD Data Pointer for Ch0/DIMM1", HEX,
Help "If 'Memory Down' is 'Yes', this is the pointer to the SPD data for Channel 0, DIMM 1. Otherwise, this field is ignored. Specify 0x00000000 if this DIMM is not present."
"Valid range: 0x00000000 ~ 0xFFFFFFFF"
EditNum $gPlatformFspPkgTokenSpaceGuid_MemDownCh1Dimm0SpdPtr, "Memory Down SPD Data Pointer for Ch1/DIMM0", HEX,
Help "If 'Memory Down' is 'Yes', this is the pointer to the SPD data for Channel 1, DIMM 0. Otherwise, this field is ignored. Specify 0x00000000 if this DIMM is not present."
"Valid range: 0x00000000 ~ 0xFFFFFFFF"
EditNum $gPlatformFspPkgTokenSpaceGuid_MemDownCh1Dimm1SpdPtr, "Memory Down SPD Data Pointer for Ch1/DIMM1", HEX,
Help "If 'Memory Down' is 'Yes', this is the pointer to the SPD data for Channel 1, DIMM 1. Otherwise, this field is ignored. Specify 0x00000000 if this DIMM is not present."
"Valid range: 0x00000000 ~ 0xFFFFFFFF"
Combo $gPlatformFspPkgTokenSpaceGuid_MemFastBoot, "Enable Fast Boot", &gPlatformFspPkgTokenSpaceGuid_MemFastBoot,
Help "Select 'Yes' to enable Fast Boot."
Combo $gPlatformFspPkgTokenSpaceGuid_pam0_hienable, "PAM0_HIENABLE (F0000-FFFFF)", &gPlatformFspPkgTokenSpaceGuid_pam0_hienable,
Help "Configure how reads and writes of F0000h-FFFFFh handled."
Combo $gPlatformFspPkgTokenSpaceGuid_pam1_loenable, "PAM1_LOENABLE (C0000-C3FFF)", &gPlatformFspPkgTokenSpaceGuid_pam1_loenable,
Help "Configure how reads and writes of C0000h-C3FFFh handled."
Combo $gPlatformFspPkgTokenSpaceGuid_pam1_hienable, "PAM1_HIENABLE (C4000-C7FFF)", &gPlatformFspPkgTokenSpaceGuid_pam1_hienable,
Help "Configure how reads and writes of C4000h-C7FFFh handled."
Combo $gPlatformFspPkgTokenSpaceGuid_pam2_loenable, "PAM2_LOENABLE (C8000-CBFFF)", &gPlatformFspPkgTokenSpaceGuid_pam2_loenable,
Help "Configure how reads and writes of C8000h-CBFFFh handled."
Combo $gPlatformFspPkgTokenSpaceGuid_pam2_hienable, "PAM2_HIENABLE (CC000-CFFFF)", &gPlatformFspPkgTokenSpaceGuid_pam2_hienable,
Help "Configure how reads and writes of CC000h-CFFFFh handled."
Combo $gPlatformFspPkgTokenSpaceGuid_pam3_loenable, "PAM3_LOENABLE (D0000-D3FFF)", &gPlatformFspPkgTokenSpaceGuid_pam3_loenable,
Help "Configure how reads and writes of D0000h-D3FFFh handled."
Combo $gPlatformFspPkgTokenSpaceGuid_pam3_hienable, "PAM3_HIENABLE (D4000-D7FFF)", &gPlatformFspPkgTokenSpaceGuid_pam3_hienable,
Help "Configure how reads and writes of D4000h-D7FFFh handled."
Combo $gPlatformFspPkgTokenSpaceGuid_pam4_loenable, "PAM4_LOENABLE (D8000-DBFFF)", &gPlatformFspPkgTokenSpaceGuid_pam4_loenable,
Help "Configure how reads and writes of D8000h-DBFFFh handled."
Combo $gPlatformFspPkgTokenSpaceGuid_pam4_hienable, "PAM4_HIENABLE (DC000-DFFFF)", &gPlatformFspPkgTokenSpaceGuid_pam4_hienable,
Help "Configure how reads and writes of DC000h-DFFFFh handled."
Combo $gPlatformFspPkgTokenSpaceGuid_pam5_loenable, "PAM5_LOENABLE (E0000-E3FFF)", &gPlatformFspPkgTokenSpaceGuid_pam5_loenable,
Help "Configure how reads and writes of E0000h-E3FFFh handled."
Combo $gPlatformFspPkgTokenSpaceGuid_pam5_hienable, "PAM5_HIENABLE (E4000-E7FFF)", &gPlatformFspPkgTokenSpaceGuid_pam5_hienable,
Help "Configure how reads and writes of E4000h-E7FFFh handled."
Combo $gPlatformFspPkgTokenSpaceGuid_pam6_loenable, "PAM6_LOENABLE (E8000-EBFFF)", &gPlatformFspPkgTokenSpaceGuid_pam6_loenable,
Help "Configure how reads and writes of E8000h-EBFFFh handled."
Combo $gPlatformFspPkgTokenSpaceGuid_pam6_hienable, "PAM6_HIENABLE (EC000-EFFFF)", &gPlatformFspPkgTokenSpaceGuid_pam6_hienable,
Help "Configure how reads and writes of EC000h-EFFFFh handled."
Combo $gPlatformFspPkgTokenSpaceGuid_MemAdr, "ADR", &gPlatformFspPkgTokenSpaceGuid_MemAdr,
Help "Asynchronous DRAM Refresh - Set to 'Enabled' if DIMMs are battery-backed or if the platform implements saving to some other non-volatile storage medium. Set to 'Enabled (NVDIMMs)' if NVDIMMs will be used on the platform."
Combo $gPlatformFspPkgTokenSpaceGuid_MemBlockScTrafficOnAdr, "Block SC traffic on ADR", &gPlatformFspPkgTokenSpaceGuid_MemBlockScTrafficOnAdr,
Help "Block all PCIe/South Complex Traffic on ADR. (For V0 and later steppings only)."
EditNum $gPlatformFspPkgTokenSpaceGuid_MemPlatformReleaseAdrClampsPort, "ADR CKE/DDR Reset Clamp Release I/O Port", HEX,
Help "Specify the i/o port which should be written to when CKE/DDR Reset clamps should be released. Specify '0' to skip."
"Valid range: 0x0000 ~ 0xFFFF"
EditNum $gPlatformFspPkgTokenSpaceGuid_MemPlatformReleaseAdrClampsAnd, "ADR CKE Clamp Release AND Bitmask", HEX,
Help "Specify the value that should be ANDed with the value read from the clamp release i/o port."
"Valid range: 0x00000000 ~ 0xFFFFFFFF"
EditNum $gPlatformFspPkgTokenSpaceGuid_MemPlatformReleaseAdrClampsOr, "ADR CKE Clamp Release OR Bitmask", HEX,
Help "Specify the value that should be ORed with the value read from the clamp release i/o port."
"Valid range: 0x00000000 ~ 0xFFFFFFFF"
EndPage
Page "Platform Settings"
Combo $gPlatformFspPkgTokenSpaceGuid_SerialPortType, "Serial Port Type", &gPlatformFspPkgTokenSpaceGuid_SerialPortType,
Help "Debug serial port resource type. Select 'None' to have FSP generate no output. Select 'I/O' to have FSP generate output via a legacy I/O output (i.e. 0x2f8/0x3f8)."
EditNum $gPlatformFspPkgTokenSpaceGuid_SerialPortAddress, "Serial Port Base", HEX,
Help "16550 compatible serial port resource base address. (I/O or MMIO base address)"
"Valid range: 0x00000000 ~ 0xFFFFFFFF"
Combo $gPlatformFspPkgTokenSpaceGuid_SerialPortConfigure, "Configure Serial Port", &gPlatformFspPkgTokenSpaceGuid_SerialPortConfigure,
Help "Select 'Yes' to have FSP configure the specified UART."
Combo $gPlatformFspPkgTokenSpaceGuid_SerialPortBaudRate, "Serial Port Baud Rate", &gPlatformFspPkgTokenSpaceGuid_SerialPortBaudRate,
Help "If 'Configure Serial Port' is set to 'Yes', this will be the baud rate that the UART located at 'Serial Port Base' is configured to use. *: Not all ES2 part support this baudrate, check Sighting Report before change it."
Combo $gPlatformFspPkgTokenSpaceGuid_SerialPortControllerInit0, "Initialize SoC UART Port 0 Controller", &gPlatformFspPkgTokenSpaceGuid_SerialPortControllerInit0,
Help "Select 'Yes' to have FSP initialize this controller. Note: If 'Yes' is selected, this controller will be mapped to the legacy IO port 0x3f8."
Combo $gPlatformFspPkgTokenSpaceGuid_SerialPortControllerInit1, "Initialize SoC UART Port 1 Controller", &gPlatformFspPkgTokenSpaceGuid_SerialPortControllerInit1,
Help "Select 'Yes' to have FSP initialize this controller. Note: If 'Yes' is selected, this controller will be mapped to the legacy IO port 0x2f8."
Combo $gPlatformFspPkgTokenSpaceGuid_ConfigIOU1_PciPort3, "IOU1 PCIe Port 3 Bifurcation", &gPlatformFspPkgTokenSpaceGuid_ConfigIOU1_PciPort3,
Help "Set your bifurcation option for IOU1 port"
Combo $gPlatformFspPkgTokenSpaceGuid_ConfigIOU2_PciPort1, "IOU2 PCIe Port 1 Bifurcation", &gPlatformFspPkgTokenSpaceGuid_ConfigIOU2_PciPort1,
Help "Set your bifurcation option for IOU2 port"
Combo $gPlatformFspPkgTokenSpaceGuid_PowerStateAfterG3, "PowerStateAfterG3 Power State recovering from G3 state)", &gPlatformFspPkgTokenSpaceGuid_PowerStateAfterG3,
Help "S0 = System will return to S0 state (boot) after power is re-applied. S5 = System will return to the S5 state (except if it was in S4, in which case it will return to S4). In the S5 state, the only enabled wake event is the Power Button or any enabled wake event that was preserved through the power failure."
Combo $gPlatformFspPkgTokenSpaceGuid_PchPciPort1, "PCH PCIe Port 1 Enable", &gPlatformFspPkgTokenSpaceGuid_PchPciPort1,
Help "Enable/Disable PCH PCie Ports. Port bifurcation options set in Fuse Straps decide the final enabling of PCIe ports"
Combo $gPlatformFspPkgTokenSpaceGuid_PchPciPort2, "PCH PCIe Port 2 Enable", &gPlatformFspPkgTokenSpaceGuid_PchPciPort2,
Help "Enable/Disable PCH PCie Ports. Port bifurcation options set in Fuse Straps decide the final enabling of PCIe ports"
Combo $gPlatformFspPkgTokenSpaceGuid_PchPciPort3, "PCH PCIe Port 3 Enable", &gPlatformFspPkgTokenSpaceGuid_PchPciPort3,
Help "Enable/Disable PCH PCie Ports. Port bifurcation options set in Fuse Straps decide the final enabling of PCIe ports"
Combo $gPlatformFspPkgTokenSpaceGuid_PchPciPort4, "PCH PCIe Port 4 Enable", &gPlatformFspPkgTokenSpaceGuid_PchPciPort4,
Help "Enable/Disable PCH PCie Ports. Port bifurcation options set in Fuse Straps decide the final enabling of PCIe ports"
Combo $gPlatformFspPkgTokenSpaceGuid_PchPciPort5, "PCH PCIe Port 5 Enable", &gPlatformFspPkgTokenSpaceGuid_PchPciPort5,
Help "Enable/Disable PCH PCie Ports. Port bifurcation options set in Fuse Straps decide the final enabling of PCIe ports"
Combo $gPlatformFspPkgTokenSpaceGuid_PchPciPort6, "PCH PCIe Port 6 Enable", &gPlatformFspPkgTokenSpaceGuid_PchPciPort6,
Help "Enable/Disable PCH PCie Ports. Port bifurcation options set in Fuse Straps decide the final enabling of PCIe ports"
Combo $gPlatformFspPkgTokenSpaceGuid_PchPciPort7, "PCH PCIe Port 7 Enable", &gPlatformFspPkgTokenSpaceGuid_PchPciPort7,
Help "Enable/Disable PCH PCie Ports. Port bifurcation options set in Fuse Straps decide the final enabling of PCIe ports"
Combo $gPlatformFspPkgTokenSpaceGuid_PchPciPort8, "PCH PCIe Port 8 Enable", &gPlatformFspPkgTokenSpaceGuid_PchPciPort8,
Help "Enable/Disable PCH PCie Ports. Port bifurcation options set in Fuse Straps decide the final enabling of PCIe ports"
Combo $gPlatformFspPkgTokenSpaceGuid_HotPlug_PchPciPort1, "PCH PCIe Port1 HotPlug", &gPlatformFspPkgTokenSpaceGuid_HotPlug_PchPciPort1,
Help "Enable/Disable the HotPlug for PCH PCie Ports"
Combo $gPlatformFspPkgTokenSpaceGuid_HotPlug_PchPciPort2, "PCH PCIe Port2 HotPlug", &gPlatformFspPkgTokenSpaceGuid_HotPlug_PchPciPort2,
Help "Enable/Disable the HotPlug for PCH PCie Ports"
Combo $gPlatformFspPkgTokenSpaceGuid_HotPlug_PchPciPort3, "PCH PCIe Port3 HotPlug", &gPlatformFspPkgTokenSpaceGuid_HotPlug_PchPciPort3,
Help "Enable/Disable the HotPlug for PCH PCie Ports"
Combo $gPlatformFspPkgTokenSpaceGuid_HotPlug_PchPciPort4, "PCH PCIe Port4 HotPlug", &gPlatformFspPkgTokenSpaceGuid_HotPlug_PchPciPort4,
Help "Enable/Disable the HotPlug for PCH PCie Ports"
Combo $gPlatformFspPkgTokenSpaceGuid_HotPlug_PchPciPort5, "PCH PCIe Port5 HotPlug", &gPlatformFspPkgTokenSpaceGuid_HotPlug_PchPciPort5,
Help "Enable/Disable the HotPlug for PCH PCie Ports"
Combo $gPlatformFspPkgTokenSpaceGuid_HotPlug_PchPciPort6, "PCH PCIe Port6 HotPlug", &gPlatformFspPkgTokenSpaceGuid_HotPlug_PchPciPort6,
Help "Enable/Disable the HotPlug for PCH PCie Ports"
Combo $gPlatformFspPkgTokenSpaceGuid_HotPlug_PchPciPort7, "PCH PCIe Port7 HotPlug", &gPlatformFspPkgTokenSpaceGuid_HotPlug_PchPciPort7,
Help "Enable/Disable the HotPlug for PCH PCie Ports"
Combo $gPlatformFspPkgTokenSpaceGuid_HotPlug_PchPciPort8, "PCH PCIe Port8 HotPlug", &gPlatformFspPkgTokenSpaceGuid_HotPlug_PchPciPort8,
Help "Enable/Disable the HotPlug for PCH PCie Ports"
Combo $gPlatformFspPkgTokenSpaceGuid_Ehci1Enable, "EHCI Controller 1", &gPlatformFspPkgTokenSpaceGuid_Ehci1Enable,
Help "Enable or disable the EHCI controller at 00.1d.00."
Combo $gPlatformFspPkgTokenSpaceGuid_Ehci2Enable, "EHCI Controller 2", &gPlatformFspPkgTokenSpaceGuid_Ehci2Enable,
Help "Enable or disable the EHCI controller at 00.1a.00."
Combo $gPlatformFspPkgTokenSpaceGuid_HyperThreading, "Hyper-Threading", &gPlatformFspPkgTokenSpaceGuid_HyperThreading,
Help "Enable or disable Intel(r) Hyper-Threading Technology."
Combo $gPlatformFspPkgTokenSpaceGuid_DebugOutputLevel, "Debug Output Level", &gPlatformFspPkgTokenSpaceGuid_DebugOutputLevel,
Help "Set debug print output level."
Combo $gPlatformFspPkgTokenSpaceGuid_TcoTimerHaltLock, "Halt and Lock TCO Timer", &gPlatformFspPkgTokenSpaceGuid_TcoTimerHaltLock,
Help "Halt and Lock the TCO Timer."
Combo $gPlatformFspPkgTokenSpaceGuid_TurboMode, "Turbo Mode", &gPlatformFspPkgTokenSpaceGuid_TurboMode,
Help "Enable/Disable processor Turbo Mode."
Combo $gPlatformFspPkgTokenSpaceGuid_BootPerfMode, "Boot Performance Mode", &gPlatformFspPkgTokenSpaceGuid_BootPerfMode,
Help "Select the performance state that should be set before OS hand-off."
Combo $gPlatformFspPkgTokenSpaceGuid_PciePort1aAspm, "PCIe Port 1A (IOU2) ASPM", &gPlatformFspPkgTokenSpaceGuid_PciePort1aAspm,
Help "PCI-Express Root Port ASPM Setting"
Combo $gPlatformFspPkgTokenSpaceGuid_PciePort1bAspm, "PCIe Port 1B (IOU2) ASPM", &gPlatformFspPkgTokenSpaceGuid_PciePort1bAspm,
Help "PCI-Express Root Port ASPM Setting"
Combo $gPlatformFspPkgTokenSpaceGuid_PciePort3aAspm, "PCIe Port 3A (IOU1) ASPM", &gPlatformFspPkgTokenSpaceGuid_PciePort3aAspm,
Help "PCI-Express Root Port ASPM Setting"
Combo $gPlatformFspPkgTokenSpaceGuid_PciePort3bAspm, "PCIe Port 3B (IOU1) ASPM", &gPlatformFspPkgTokenSpaceGuid_PciePort3bAspm,
Help "PCI-Express Root Port ASPM Setting"
Combo $gPlatformFspPkgTokenSpaceGuid_PciePort3cAspm, "PCIe Port 3C (IOU1) ASPM", &gPlatformFspPkgTokenSpaceGuid_PciePort3cAspm,
Help "PCI-Express Root Port ASPM Setting"
Combo $gPlatformFspPkgTokenSpaceGuid_PciePort3dAspm, "PCIe Port 3D (IOU1) ASPM", &gPlatformFspPkgTokenSpaceGuid_PciePort3dAspm,
Help "PCI-Express Root Port ASPM Setting"
Combo $gPlatformFspPkgTokenSpaceGuid_PchPciePort1Aspm, "PCH PCIe Port 1 ASPM", &gPlatformFspPkgTokenSpaceGuid_PchPciePort1Aspm,
Help "PCH PCIe Root Port ASPM Setting"
Combo $gPlatformFspPkgTokenSpaceGuid_PchPciePort2Aspm, "PCH PCIe Port 2 ASPM", &gPlatformFspPkgTokenSpaceGuid_PchPciePort2Aspm,
Help "PCH PCIe Root Port ASPM Setting"
Combo $gPlatformFspPkgTokenSpaceGuid_PchPciePort3Aspm, "PCH PCIe Port 3 ASPM", &gPlatformFspPkgTokenSpaceGuid_PchPciePort3Aspm,
Help "PCH PCIe Root Port ASPM Setting"
Combo $gPlatformFspPkgTokenSpaceGuid_PchPciePort4Aspm, "PCH PCIe Port 4 ASPM", &gPlatformFspPkgTokenSpaceGuid_PchPciePort4Aspm,
Help "PCH PCIe Root Port ASPM Setting"
Combo $gPlatformFspPkgTokenSpaceGuid_PchPciePort5Aspm, "PCH PCIe Port 5 ASPM", &gPlatformFspPkgTokenSpaceGuid_PchPciePort5Aspm,
Help "PCH PCIe Root Port ASPM Setting"
Combo $gPlatformFspPkgTokenSpaceGuid_PchPciePort6Aspm, "PCH PCIe Port 6 ASPM", &gPlatformFspPkgTokenSpaceGuid_PchPciePort6Aspm,
Help "PCH PCIe Root Port ASPM Setting"
Combo $gPlatformFspPkgTokenSpaceGuid_PchPciePort7Aspm, "PCH PCIe Port 7 ASPM", &gPlatformFspPkgTokenSpaceGuid_PchPciePort7Aspm,
Help "PCH PCIe Root Port ASPM Setting"
Combo $gPlatformFspPkgTokenSpaceGuid_PchPciePort8Aspm, "PCH PCIe Port 8 ASPM", &gPlatformFspPkgTokenSpaceGuid_PchPciePort8Aspm,
Help "PCH PCIe Root Port ASPM Setting"
Combo $gPlatformFspPkgTokenSpaceGuid_DFXEnable, "EV DFX Features", &gPlatformFspPkgTokenSpaceGuid_DFXEnable,
Help "Enable this option to allow DFX Lock Bits to remain clear."
Combo $gPlatformFspPkgTokenSpaceGuid_ThermalDeviceEnable, "PCH Thermal Device", &gPlatformFspPkgTokenSpaceGuid_ThermalDeviceEnable,
Help "Enable/Disable the PCH Thermal Device (D31:F6)."
EndPage

View File

@ -0,0 +1,436 @@
/** @file
Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
This file is automatically generated. Please do NOT modify !!!
**/
#ifndef __FSPUPDVPD_H__
#define __FSPUPDVPD_H__
#pragma pack(1)
typedef struct _UPD_DATA_REGION {
/**Offset 0x0000
**/
UINT64 Signature;
/**Offset 0x0008
**/
UINT64 Reserved;
/**Offset 0x0010
**/
UINT8 UnusedUpdSpace0[16];
/**Offset 0x0020
Debug serial port resource type. Select 'None' to have FSP generate no output. Select 'I/O' to have FSP generate output via a legacy I/O output (i.e. 0x2f8/0x3f8).
**/
UINT8 SerialPortType;
/**Offset 0x0021
16550 compatible serial port resource base address. (I/O or MMIO base address)
**/
UINT32 SerialPortAddress;
/**Offset 0x0025
Select 'Yes' to have FSP configure the specified UART.
**/
UINT8 SerialPortConfigure;
/**Offset 0x0026
If 'Configure Serial Port' is set to 'Yes', this will be the baud rate that the UART located at 'Serial Port Base' is configured to use. *: Not all ES2 part support this baudrate, check Sighting Report before change it.
**/
UINT8 SerialPortBaudRate;
/**Offset 0x0027
Select 'Yes' to have FSP initialize this controller. Note: If 'Yes' is selected, this controller will be mapped to the legacy IO port 0x3f8.
**/
UINT8 SerialPortControllerInit0;
/**Offset 0x0028
Select 'Yes' to have FSP initialize this controller. Note: If 'Yes' is selected, this controller will be mapped to the legacy IO port 0x2f8.
**/
UINT8 SerialPortControllerInit1;
/**Offset 0x0029
Set your bifurcation option for IOU1 port
**/
UINT8 ConfigIOU1_PciPort3;
/**Offset 0x002A
Set your bifurcation option for IOU2 port
**/
UINT8 ConfigIOU2_PciPort1;
/**Offset 0x002B
S0 = System will return to S0 state (boot) after power is re-applied. S5 = System will return to the S5 state (except if it was in S4, in which case it will return to S4). In the S5 state, the only enabled wake event is the Power Button or any enabled wake event that was preserved through the power failure.
**/
UINT8 PowerStateAfterG3;
/**Offset 0x002C
Enable/Disable PCH PCie Ports. Port bifurcation options set in Fuse Straps decide the final enabling of PCIe ports
**/
UINT8 PchPciPort1;
/**Offset 0x002D
Enable/Disable PCH PCie Ports. Port bifurcation options set in Fuse Straps decide the final enabling of PCIe ports
**/
UINT8 PchPciPort2;
/**Offset 0x002E
Enable/Disable PCH PCie Ports. Port bifurcation options set in Fuse Straps decide the final enabling of PCIe ports
**/
UINT8 PchPciPort3;
/**Offset 0x002F
Enable/Disable PCH PCie Ports. Port bifurcation options set in Fuse Straps decide the final enabling of PCIe ports
**/
UINT8 PchPciPort4;
/**Offset 0x0030
Enable/Disable PCH PCie Ports. Port bifurcation options set in Fuse Straps decide the final enabling of PCIe ports
**/
UINT8 PchPciPort5;
/**Offset 0x0031
Enable/Disable PCH PCie Ports. Port bifurcation options set in Fuse Straps decide the final enabling of PCIe ports
**/
UINT8 PchPciPort6;
/**Offset 0x0032
Enable/Disable PCH PCie Ports. Port bifurcation options set in Fuse Straps decide the final enabling of PCIe ports
**/
UINT8 PchPciPort7;
/**Offset 0x0033
Enable/Disable PCH PCie Ports. Port bifurcation options set in Fuse Straps decide the final enabling of PCIe ports
**/
UINT8 PchPciPort8;
/**Offset 0x0034
Enable/Disable the HotPlug for PCH PCie Ports
**/
UINT8 HotPlug_PchPciPort1;
/**Offset 0x0035
Enable/Disable the HotPlug for PCH PCie Ports
**/
UINT8 HotPlug_PchPciPort2;
/**Offset 0x0036
Enable/Disable the HotPlug for PCH PCie Ports
**/
UINT8 HotPlug_PchPciPort3;
/**Offset 0x0037
Enable/Disable the HotPlug for PCH PCie Ports
**/
UINT8 HotPlug_PchPciPort4;
/**Offset 0x0038
Enable/Disable the HotPlug for PCH PCie Ports
**/
UINT8 HotPlug_PchPciPort5;
/**Offset 0x0039
Enable/Disable the HotPlug for PCH PCie Ports
**/
UINT8 HotPlug_PchPciPort6;
/**Offset 0x003A
Enable/Disable the HotPlug for PCH PCie Ports
**/
UINT8 HotPlug_PchPciPort7;
/**Offset 0x003B
Enable/Disable the HotPlug for PCH PCie Ports
**/
UINT8 HotPlug_PchPciPort8;
/**Offset 0x003C
Enable or disable the EHCI controller at 00.1d.00.
**/
UINT8 Ehci1Enable;
/**Offset 0x003D
Enable or disable the EHCI controller at 00.1a.00.
**/
UINT8 Ehci2Enable;
/**Offset 0x003E
Enable or disable Intel(r) Hyper-Threading Technology.
**/
UINT8 HyperThreading;
/**Offset 0x003F
Set debug print output level.
**/
UINT8 DebugOutputLevel;
/**Offset 0x0040
Halt and Lock the TCO Timer.
**/
UINT8 TcoTimerHaltLock;
/**Offset 0x0041
Enable/Disable processor Turbo Mode.
**/
UINT8 TurboMode;
/**Offset 0x0042
Select the performance state that should be set before OS hand-off.
**/
UINT8 BootPerfMode;
/**Offset 0x0043
PCI-Express Root Port ASPM Setting
**/
UINT8 PciePort1aAspm;
/**Offset 0x0044
PCI-Express Root Port ASPM Setting
**/
UINT8 PciePort1bAspm;
/**Offset 0x0045
PCI-Express Root Port ASPM Setting
**/
UINT8 PciePort3aAspm;
/**Offset 0x0046
PCI-Express Root Port ASPM Setting
**/
UINT8 PciePort3bAspm;
/**Offset 0x0047
PCI-Express Root Port ASPM Setting
**/
UINT8 PciePort3cAspm;
/**Offset 0x0048
PCI-Express Root Port ASPM Setting
**/
UINT8 PciePort3dAspm;
/**Offset 0x0049
PCH PCIe Root Port ASPM Setting
**/
UINT8 PchPciePort1Aspm;
/**Offset 0x004A
PCH PCIe Root Port ASPM Setting
**/
UINT8 PchPciePort2Aspm;
/**Offset 0x004B
PCH PCIe Root Port ASPM Setting
**/
UINT8 PchPciePort3Aspm;
/**Offset 0x004C
PCH PCIe Root Port ASPM Setting
**/
UINT8 PchPciePort4Aspm;
/**Offset 0x004D
PCH PCIe Root Port ASPM Setting
**/
UINT8 PchPciePort5Aspm;
/**Offset 0x004E
PCH PCIe Root Port ASPM Setting
**/
UINT8 PchPciePort6Aspm;
/**Offset 0x004F
PCH PCIe Root Port ASPM Setting
**/
UINT8 PchPciePort7Aspm;
/**Offset 0x0050
PCH PCIe Root Port ASPM Setting
**/
UINT8 PchPciePort8Aspm;
/**Offset 0x0051
Enable this option to allow DFX Lock Bits to remain clear.
**/
UINT8 DFXEnable;
/**Offset 0x0052
Enable/Disable the PCH Thermal Device (D31:F6).
**/
UINT8 ThermalDeviceEnable;
/**Offset 0x0053
**/
UINT8 UnusedUpdSpace1[88];
/**Offset 0x00AB
Enable/disable DDR ECC Support.
**/
UINT8 MemEccSupport;
/**Offset 0x00AC
Select the memory type supported by this platform.
**/
UINT8 MemDdrMemoryType;
/**Offset 0x00AD
Force the Rank Multiplication factor for LRDIMM.
**/
UINT8 MemRankMultiplication;
/**Offset 0x00AE
Run the Rank Margin Tool after memory training.
**/
UINT8 MemRankMarginTool;
/**Offset 0x00AF
Enable data scrambling.
**/
UINT8 MemScrambling;
/**Offset 0x00B0
Self refresh mode.
**/
UINT8 MemRefreshMode;
/**Offset 0x00B1
Select MC ODT Mode.
**/
UINT8 MemMcOdtOverride;
/**Offset 0x00B2
Enable/Disable DDR4 Command Address Parity
**/
UINT8 MemCAParity;
/**Offset 0x00B3
Configure Thermal Throttling Mode.
**/
UINT8 MemThermalThrottling;
/**Offset 0x00B4
Configures CKE and related Memory Power Savings Features
**/
UINT8 MemPowerSavingsMode;
/**Offset 0x00B5
Configure Memory Electrical Throttling
**/
UINT8 MemElectricalThrottling;
/**Offset 0x00B6
Select Page Policy
**/
UINT8 MemPagePolicy;
/**Offset 0x00B7
Splits the 0-4GB address space between two sockets, so that both sockets get a chunk of local memory below 4GB.
**/
UINT8 MemSocketInterleaveBelow4G;
/**Offset 0x00B8
Select Channel Interleaving setting.
**/
UINT8 MemChannelInterleave;
/**Offset 0x00B9
Select Rank Interleaving setting.
**/
UINT8 MemRankInterleave;
/**Offset 0x00BA
Select 'Yes' if memory is down. If set to 'Yes', at least one of the following SPD data pointers must also be provided.
**/
UINT8 MemDownEnable;
/**Offset 0x00BB
If 'Memory Down' is 'Yes', this is the pointer to the SPD data for Channel 0, DIMM 0. Otherwise, this field is ignored. Specify 0x00000000 if this DIMM is not present.
**/
UINT32 MemDownCh0Dimm0SpdPtr;
/**Offset 0x00BF
If 'Memory Down' is 'Yes', this is the pointer to the SPD data for Channel 0, DIMM 1. Otherwise, this field is ignored. Specify 0x00000000 if this DIMM is not present.
**/
UINT32 MemDownCh0Dimm1SpdPtr;
/**Offset 0x00C3
If 'Memory Down' is 'Yes', this is the pointer to the SPD data for Channel 1, DIMM 0. Otherwise, this field is ignored. Specify 0x00000000 if this DIMM is not present.
**/
UINT32 MemDownCh1Dimm0SpdPtr;
/**Offset 0x00C7
If 'Memory Down' is 'Yes', this is the pointer to the SPD data for Channel 1, DIMM 1. Otherwise, this field is ignored. Specify 0x00000000 if this DIMM is not present.
**/
UINT32 MemDownCh1Dimm1SpdPtr;
/**Offset 0x00CB
Select 'Yes' to enable Fast Boot.
**/
UINT8 MemFastBoot;
/**Offset 0x00CC
Configure how reads and writes of F0000h-FFFFFh handled.
**/
UINT8 pam0_hienable;
/**Offset 0x00CD
Configure how reads and writes of C0000h-C3FFFh handled.
**/
UINT8 pam1_loenable;
/**Offset 0x00CE
Configure how reads and writes of C4000h-C7FFFh handled.
**/
UINT8 pam1_hienable;
/**Offset 0x00CF
Configure how reads and writes of C8000h-CBFFFh handled.
**/
UINT8 pam2_loenable;
/**Offset 0x00D0
Configure how reads and writes of CC000h-CFFFFh handled.
**/
UINT8 pam2_hienable;
/**Offset 0x00D1
Configure how reads and writes of D0000h-D3FFFh handled.
**/
UINT8 pam3_loenable;
/**Offset 0x00D2
Configure how reads and writes of D4000h-D7FFFh handled.
**/
UINT8 pam3_hienable;
/**Offset 0x00D3
Configure how reads and writes of D8000h-DBFFFh handled.
**/
UINT8 pam4_loenable;
/**Offset 0x00D4
Configure how reads and writes of DC000h-DFFFFh handled.
**/
UINT8 pam4_hienable;
/**Offset 0x00D5
Configure how reads and writes of E0000h-E3FFFh handled.
**/
UINT8 pam5_loenable;
/**Offset 0x00D6
Configure how reads and writes of E4000h-E7FFFh handled.
**/
UINT8 pam5_hienable;
/**Offset 0x00D7
Configure how reads and writes of E8000h-EBFFFh handled.
**/
UINT8 pam6_loenable;
/**Offset 0x00D8
Configure how reads and writes of EC000h-EFFFFh handled.
**/
UINT8 pam6_hienable;
/**Offset 0x00D9
Asynchronous DRAM Refresh - Set to 'Enabled' if DIMMs are battery-backed or if the platform implements saving to some other non-volatile storage medium. Set to 'Enabled (NVDIMMs)' if NVDIMMs will be used on the platform.
**/
UINT8 MemAdr;
/**Offset 0x00DA
**/
UINT8 MemAdrResumePath;
/**Offset 0x00DB
Block all PCIe/South Complex Traffic on ADR. (For V0 and later steppings only).
**/
UINT8 MemBlockScTrafficOnAdr;
/**Offset 0x00DC
Specify the i/o port which should be written to when CKE/DDR Reset clamps should be released. Specify '0' to skip.
**/
UINT16 MemPlatformReleaseAdrClampsPort;
/**Offset 0x00DE
Specify the value that should be ANDed with the value read from the clamp release i/o port.
**/
UINT32 MemPlatformReleaseAdrClampsAnd;
/**Offset 0x00E2
Specify the value that should be ORed with the value read from the clamp release i/o port.
**/
UINT32 MemPlatformReleaseAdrClampsOr;
/**Offset 0x00E6
**/
UINT8 UnusedUpdSpace2[24];
/**Offset 0x00FE
**/
UINT16 PcdRegionTerminator;
} UPD_DATA_REGION;
#define FSP_IMAGE_ID 0x5F45442D5844425F /* '_BDX-DE_' */
#define FSP_IMAGE_REV 0x00000301
typedef struct _VPD_DATA_REGION {
/**Offset 0x0000
**/
UINT64 PcdVpdRegionSign;
/**Offset 0x0008
**/
UINT32 PcdImageRevision;
/**Offset 0x000C
**/
UINT32 PcdUpdRegionOffset;
/**Offset 0x0010
**/
UINT8 UnusedVpdSpace0[16];
/**Offset 0x0020
**/
UINT32 PcdFspReservedMemoryLength;
} VPD_DATA_REGION;
#pragma pack()
#endif

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@ -0,0 +1,243 @@
/** @file
Boot Setting File for Platform Configuration.
Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
This file is automatically generated. Please do NOT modify !!!
**/
GlobalDataDef
SKUID = 0, "DEFAULT"
EndGlobalData
StructDef
Find "$BDWUPD$"
Skip 24 bytes
$gBroadwellFspPkgTokenSpaceGuid_PcdSpdBaseAddress_0_0 1 bytes $_DEFAULT_ = 0xA2
$gBroadwellFspPkgTokenSpaceGuid_PcdSpdBaseAddress_0_1 1 bytes $_DEFAULT_ = 0xA0
$gBroadwellFspPkgTokenSpaceGuid_PcdSpdBaseAddress_1_0 1 bytes $_DEFAULT_ = 0xA2
$gBroadwellFspPkgTokenSpaceGuid_PcdSpdBaseAddress_1_1 1 bytes $_DEFAULT_ = 0xA0
$gBroadwellFspPkgTokenSpaceGuid_PcdTsegSize 1 bytes $_DEFAULT_ = 0x03
Skip 4 bytes
$gBroadwellFspPkgTokenSpaceGuid_PcdIgdDvmt50PreAlloc 1 bytes $_DEFAULT_ = 0x01
$gBroadwellFspPkgTokenSpaceGuid_PcdPrimaryDisplay 1 bytes $_DEFAULT_ = 0x03
$gBroadwellFspPkgTokenSpaceGuid_PcdInternalGfx 1 bytes $_DEFAULT_ = 0x01
$gBroadwellFspPkgTokenSpaceGuid_PcdMmioSize 1 bytes $_DEFAULT_ = 0x00
Skip 1 bytes
$gBroadwellFspPkgTokenSpaceGuid_PcdApertureSize 1 bytes $_DEFAULT_ = 0x01
Skip 81 bytes
$gBroadwellFspPkgTokenSpaceGuid_PcdEnableLan 1 bytes $_DEFAULT_ = 0x01
$gBroadwellFspPkgTokenSpaceGuid_PcdEnableSata 1 bytes $_DEFAULT_ = 0x01
$gBroadwellFspPkgTokenSpaceGuid_PcdSataMode 1 bytes $_DEFAULT_ = 0x01
$gBroadwellFspPkgTokenSpaceGuid_PcdEnableAzalia 1 bytes $_DEFAULT_ = 0x00
$gBroadwellFspPkgTokenSpaceGuid_PcdEnableXhci 1 bytes $_DEFAULT_ = 0x03
$gBroadwellFspPkgTokenSpaceGuid_PcdEnableEhci1 1 bytes $_DEFAULT_ = 0x01
$gBroadwellFspPkgTokenSpaceGuid_PcdEnableEhci2 1 bytes $_DEFAULT_ = 0x00
$gBroadwellFspPkgTokenSpaceGuid_PcdEnableSmbus 1 bytes $_DEFAULT_ = 0x01
$gBroadwellFspPkgTokenSpaceGuid_PcdEnableAudioDsp 1 bytes $_DEFAULT_ = 0x01
Skip 8 bytes
$gBroadwellFspPkgTokenSpaceGuid_PcdPmBase 2 bytes $_DEFAULT_ = 0x1000
$gBroadwellFspPkgTokenSpaceGuid_PcdPchPcieRootPortEnable 2 bytes $_DEFAULT_ = 0x003F
$gBroadwellFspPkgTokenSpaceGuid_PcdPchPcieSlotImplemented 2 bytes $_DEFAULT_ = 0x003F
$gBroadwellFspPkgTokenSpaceGuid_PcdPchPcieRootPortFunctionSwappingEnable 1 bytes $_DEFAULT_ = 0x00
$gBroadwellFspPkgTokenSpaceGuid_PcdGpioBase 2 bytes $_DEFAULT_ = 0x1400
$gBroadwellFspPkgTokenSpaceGuid_PcdPchSataPortEnable 2 bytes $_DEFAULT_ = 0x000F
$gBroadwellFspPkgTokenSpaceGuid_PcdPchSataSolidStateDrive 2 bytes $_DEFAULT_ = 0xFFFF
$gBroadwellFspPkgTokenSpaceGuid_PcdPchSataInterlockSw 2 bytes $_DEFAULT_ = 0xFFFF
$gBroadwellFspPkgTokenSpaceGuid_PcdPchSataSpinUp 2 bytes $_DEFAULT_ = 0xFFFF
$gBroadwellFspPkgTokenSpaceGuid_PcdPchSataHotPlug 2 bytes $_DEFAULT_ = 0x0000
Skip 92 bytes
$gBroadwellFspPkgTokenSpaceGuid_PcdFastBoot 1 bytes $_DEFAULT_ = 0x01
$gBroadwellFspPkgTokenSpaceGuid_PcdUserCrbBoardType 1 bytes $_DEFAULT_ = 0x02
Skip 142 bytes
$gBroadwellFspPkgTokenSpaceGuid_DqDqsDataEffective 1 bytes $_DEFAULT_ = 0x1
Skip 11 bytes
$gBroadwellFspPkgTokenSpaceGuid_DqByteMap 24 bytes $_DEFAULT_ = 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00, 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00
Skip 76 bytes
$gBroadwellFspPkgTokenSpaceGuid_DqsMapCpu2Dram 16 bytes $_DEFAULT_ = 2, 0, 1, 3, 6, 4, 7, 5, 1, 3, 2, 0, 5, 7, 6, 4
Find "$BDWFSP$"
$gPlatformFspPkgTokenSpaceGuid_PcdImageRevision 4 bytes $_DEFAULT_ = 0x02090000
Skip 24 bytes
$gBroadwellFspPkgTokenSpaceGuid_PcdPort80Route 1 bytes $_DEFAULT_ = 0x00
EndStruct
List &EN_DIS
Selection 0x1 , "Enabled"
Selection 0x0 , "Disabled"
EndList
List &gBroadwellFspPkgTokenSpaceGuid_PcdApertureSize
Selection 0 , "128 MB"
Selection 1 , "256 MB"
Selection 2 , "512 MB"
EndList
List &gBroadwellFspPkgTokenSpaceGuid_PcdUserCrbBoardType
Selection 0 , "Mobile"
Selection 1 , "Desktop"
Selection 2 , "Embedded (default)"
EndList
List &gBroadwellFspPkgTokenSpaceGuid_PcdEnableXhci
Selection 0 , "Disabled"
Selection 1 , "Enabled"
Selection 2 , "Auto"
Selection 3 , "Smart Auto"
EndList
List &gBroadwellFspPkgTokenSpaceGuid_PcdSataMode
Selection 0 , "IDE"
Selection 1 , "AHCI"
Selection 2 , "RAID"
EndList
List &gBroadwellFspPkgTokenSpaceGuid_PcdPrimaryDisplay
Selection 0 , "IGFX"
Selection 1 , "PEG"
Selection 2 , "PCI"
Selection 3 , "AUTO"
EndList
List &gBroadwellFspPkgTokenSpaceGuid_PcdMmioSize
Selection 0 , "Dynamic"
Selection 1 , "1.0 GB"
Selection 2 , "1.5 GB"
Selection 3 , "2.0 GB"
EndList
List &gBroadwellFspPkgTokenSpaceGuid_PcdTsegSize
Selection 0 , "1 MB"
Selection 1 , "2 MB"
Selection 2 , "4 MB"
Selection 3 , "8 MB"
EndList
List &gBroadwellFspPkgTokenSpaceGuid_PcdIgdDvmt50PreAlloc
Selection 0x00 , "0 MB"
Selection 0x01 , "32 MB"
Selection 0x02 , "64 MB"
Selection 0x03 , "128 MB"
Selection 0x04 , "256 MB"
Selection 0x05 , "512 MB"
EndList
List &gBroadwellFspPkgTokenSpaceGuid_PcdPort80Route
Selection 0 , "LPC"
Selection 1 , "PCI"
EndList
BeginInfoBlock
PPVer "0.1"
Description "Broadwell platform"
EndInfoBlock
Page "Wildcat Point PCH"
Combo $gBroadwellFspPkgTokenSpaceGuid_PcdPort80Route, "Port 80 Route", &gBroadwellFspPkgTokenSpaceGuid_PcdPort80Route,
Help "Control where the Port 80h cycles are sent, 0: LPC; 1: PCI."
Combo $gBroadwellFspPkgTokenSpaceGuid_PcdEnableLan, "Enable LAN", &EN_DIS,
Help "Enable/disable LAN controller."
Combo $gBroadwellFspPkgTokenSpaceGuid_PcdEnableSata, "Enable SATA", &EN_DIS,
Help "Enable/disable SATA controller."
Combo $gBroadwellFspPkgTokenSpaceGuid_PcdSataMode, "SATA Mode", &gBroadwellFspPkgTokenSpaceGuid_PcdSataMode,
Help "Select SATA controller working mode."
Combo $gBroadwellFspPkgTokenSpaceGuid_PcdEnableAzalia, "Enable Azalia", &EN_DIS,
Help "Enable/disable Azalia controller."
Combo $gBroadwellFspPkgTokenSpaceGuid_PcdEnableXhci, "Enable XHCI", &gBroadwellFspPkgTokenSpaceGuid_PcdEnableXhci,
Help "Enable/disable XHCI controller."
Combo $gBroadwellFspPkgTokenSpaceGuid_PcdEnableEhci1, "Enable EHCI #1", &EN_DIS,
Help "Enable/disable EHCI controller #1."
Combo $gBroadwellFspPkgTokenSpaceGuid_PcdEnableEhci2, "Enable EHCI #2", &EN_DIS,
Help "Enable/disable EHCI controller #2. Note this option is only applicable to SKUs with two EHCI controllers."
Combo $gBroadwellFspPkgTokenSpaceGuid_PcdEnableSmbus, "Enable SMBus", &EN_DIS,
Help "Enable/disable SMBus"
Combo $gBroadwellFspPkgTokenSpaceGuid_PcdEnableAudioDsp, "Enable Audio DSP", &EN_DIS,
Help "Enable/disable PCH Audio DSP controller. Note: if enabled Azalia must be disabled."
EditNum $gBroadwellFspPkgTokenSpaceGuid_PcdPmBase, "PM Base Address", HEX,
Help "Power Management Base Address"
"Valid range: 0x0000 ~ 0xFFFF"
EditNum $gBroadwellFspPkgTokenSpaceGuid_PcdPchPcieRootPortEnable, "Pch PCIe Root Port Enable", HEX,
Help "Pch PCIe Root Port Enable. The bit 0 is mapped to port 1, bit 1 is mapped to port 2, and so on."
"Valid range: 0x0000 ~ 0xFFFF"
EditNum $gBroadwellFspPkgTokenSpaceGuid_PcdPchPcieSlotImplemented, "Pch PCIe Slot Implemented", HEX,
Help "Pch PCIe Slot Implemented. The bit 0 is mapped to port 1, bit 1 is mapped to port 2, and so on."
"Valid range: 0x0000 ~ 0xFFFF"
Combo $gBroadwellFspPkgTokenSpaceGuid_PcdPchPcieRootPortFunctionSwappingEnable, "Pch PCIe Root Port Function Swapping Enable", &EN_DIS,
Help "Pch PCIe Root Port Function Swapping Enable"
EditNum $gBroadwellFspPkgTokenSpaceGuid_PcdGpioBase, "GPIO Base Address", HEX,
Help "GPIO Base Address"
"Valid range: 0x0000 ~ 0xFFFF"
EditNum $gBroadwellFspPkgTokenSpaceGuid_PcdPchSataPortEnable, "Pch SATA Port Enable", HEX,
Help "Pch SATA Port Enable. The bit 0 is mapped to port 1, bit 1 is mapped to port 2, and so on."
"Valid range: 0x0000 ~ 0xFFFF"
EditNum $gBroadwellFspPkgTokenSpaceGuid_PcdPchSataSolidStateDrive, "Pch SATA Solid State Drive", HEX,
Help "SATA Drive Type. 0: HDD, 1: SDD. The bit 0 is mapped to port 1, bit 1 is mapped to port 2, and so on."
"Valid range: 0x0000 ~ 0xFFFF"
EditNum $gBroadwellFspPkgTokenSpaceGuid_PcdPchSataInterlockSw, "Pch SATA Mechanical Presence Switch", HEX,
Help "SATA Mechanical Presence Switch. 0: No, 1: Yes. The bit 0 is mapped to port 1, bit 1 is mapped to port 2, and so on."
"Valid range: 0x0000 ~ 0xFFFF"
EditNum $gBroadwellFspPkgTokenSpaceGuid_PcdPchSataSpinUp, "SATA Spin Up Device", HEX,
Help "If enabled for any of ports Staggered Spin Up will be performed and only the drives which have this option enabled will spin up at boot. Otherwise all drives spin up at boot. 0: No, 1: Yes. The bit 0 is mapped to port 1, bit 1 is mapped to port 2, and so on."
"Valid range: 0x0000 ~ 0xFFFF"
EditNum $gBroadwellFspPkgTokenSpaceGuid_PcdPchSataHotPlug, "SATA Hot Plug", HEX,
Help "Designates port as Hot Pluggable. 0: No, 1: Yes. The bit 0 is mapped to port 1, bit 1 is mapped to port 2, and so on."
"Valid range: 0x0000 ~ 0xFFFF"
EndPage
Page "Broadwell System Agent"
EditNum $gBroadwellFspPkgTokenSpaceGuid_PcdSpdBaseAddress_0_0, "Channel 0 DIMM 0 SPD SMBus Address", HEX,
Help "SPD Address of DIMM."
"Valid range: 0x00 ~ 0xFF"
EditNum $gBroadwellFspPkgTokenSpaceGuid_PcdSpdBaseAddress_0_1, "Channel 0 DIMM 1 SPD SMBus Address", HEX,
Help "SPD Address of DIMM."
"Valid range: 0x00 ~ 0xFF"
EditNum $gBroadwellFspPkgTokenSpaceGuid_PcdSpdBaseAddress_1_0, "Channel 1 DIMM 0 SPD SMBus Address", HEX,
Help "SPD Address of DIMM."
"Valid range: 0x00 ~ 0xFF"
EditNum $gBroadwellFspPkgTokenSpaceGuid_PcdSpdBaseAddress_1_1, "Channel 1 DIMM 1 SPD SMBus Address", HEX,
Help "SPD Address of DIMM."
"Valid range: 0x00 ~ 0xFF"
Combo $gBroadwellFspPkgTokenSpaceGuid_PcdTsegSize, "Tseg Size", &gBroadwellFspPkgTokenSpaceGuid_PcdTsegSize,
Help "Size of SMRAM memory reserved."
Combo $gBroadwellFspPkgTokenSpaceGuid_PcdIgdDvmt50PreAlloc, "Internal Graphics Pre-allocated Memory", &gBroadwellFspPkgTokenSpaceGuid_PcdIgdDvmt50PreAlloc,
Help "Size of memory preallocated for internal graphics."
Combo $gBroadwellFspPkgTokenSpaceGuid_PcdPrimaryDisplay, "Primary Display", &gBroadwellFspPkgTokenSpaceGuid_PcdPrimaryDisplay,
Help "Select which of IGFX/PEG/PCI Graphics device should be Primary Display."
Combo $gBroadwellFspPkgTokenSpaceGuid_PcdInternalGfx, "Enable Internal Graphics", &EN_DIS,
Help "Enable/disable internal graphics."
Combo $gBroadwellFspPkgTokenSpaceGuid_PcdMmioSize, "MMIO Size", &gBroadwellFspPkgTokenSpaceGuid_PcdMmioSize,
Help "Size of memory address space reserved for MMIO (Memory Mapped I/O)."
Combo $gBroadwellFspPkgTokenSpaceGuid_PcdApertureSize, "Aperture Size", &gBroadwellFspPkgTokenSpaceGuid_PcdApertureSize,
Help "Select the Aperture Size."
EndPage
Page "Platform Settings"
Combo $gBroadwellFspPkgTokenSpaceGuid_PcdFastBoot, "Fast Boot", &EN_DIS,
Help "Enable/disable Fast Boot function. Once enabled, all following boots will use the presaved MRC data to improve the boot performance."
Combo $gBroadwellFspPkgTokenSpaceGuid_PcdUserCrbBoardType, "CRB Board Type", &gBroadwellFspPkgTokenSpaceGuid_PcdUserCrbBoardType,
Help "Specify the closest CRB board type to the platform."
Combo $gBroadwellFspPkgTokenSpaceGuid_DqDqsDataEffective, "Dq Dqs Data effective", &EN_DIS,
Help "Indicate whether it comes with effective Dq/Dqs mapping data "
EditNum $gBroadwellFspPkgTokenSpaceGuid_DqByteMap, "Dq Byte Map", HEX,
Help "Dq byte mapping between CPU and DRAM"
"Valid range: 0x00 ~ 0xFF"
EditNum $gBroadwellFspPkgTokenSpaceGuid_DqsMapCpu2Dram, "Dqs Map CPU to DRAM", HEX,
Help "Set Dqs mapping relationship between CPU and DRAM"
"Valid range: 0x00 ~ 0xFF"
EndPage

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@ -0,0 +1,310 @@
/** @file
Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
This file is automatically generated. Please do NOT modify !!!
**/
#ifndef __FSP_VPD_H__
#define __FSP_VPD_H__
#pragma pack(1)
#define MAX_CH 2 /* Maximum Number of Memory Channels */
#define MAX_DIMM 2 /* Maximum Number of DIMMs PER Memory Channel */
typedef enum {
MEMORY_ABSENT = 0, /* No memory down and no physical memory slot. */
MEMORY_DOWN_ONLY = 1, /* Memory down and not a physical memory slot. */
MEMORY_SLOT_ONLY = 2, /* No memory down and a physical memory slot. */
} MemorySlotStatus;
typedef struct {
MemorySlotStatus SlotStatus[MAX_CH][MAX_DIMM]; /* Memory Down, Absent or Slot status of each DIMM in each Channel */
UINT16 SpdDataLen; /* Length in Bytes of a single DIMM's SPD Data */
UINT8 *SpdDataPtr[MAX_CH][MAX_DIMM]; /* Array of Pointers to SPD Data for each DIMM in each Channel */
} MEMORY_DOWN_DATA;
typedef struct {
UINT32 VendorDeviceId; /* Vendor ID/Device ID */
UINT16 SubSystemId; /* SubSystem ID */
UINT8 RevisionId; /* Revision ID. 0xFF applies to all steppings */
UINT8 FrontPanelSupport; /* Front panel support (1=yes, 2=no) */
UINT16 NumberOfRearJacks; /* Number of Rear Jacks */
UINT16 NumberOfFrontJacks; /* Number of Front Jacks */
} SA_HDA_HEADER;
typedef struct {
UINT16 VendorId; /* Codec Vendor ID */
UINT16 DeviceId; /* Codec Device ID */
UINT8 RevisionId; /* Revision ID of the codec. 0xFF matches any revision. */
UINT8 SdiNo; /* SDI number, 0xFF matches any SDI. */
UINT16 DataDwords; /* Number of data DWORDs pointed by the codec data buffer. */
UINT32 Reserved; /* Reserved for future use. Must be set to 0. */
} AZALIA_HEADER;
typedef struct {
SA_HDA_HEADER Header; /* SA HDA header */
UINT32 *Data; /* Pointer to the data buffer. Its length is determined by the header */
} AUDIO_SA_VERB_TABLE;
typedef struct {
AZALIA_HEADER Header; /* AZALIA PCH header */
UINT32 *Data; /* Pointer to the data buffer. Its length is specified in the header */
} AUDIO_AZALIA_VERB_TABLE;
typedef struct _UPD_DATA_REGION {
/**Offset 0x0000
**/
UINT64 Signature;
/**Offset 0x0008
**/
UINT64 Reserved;
/**Offset 0x0010
**/
UINT8 UnusedUpdSpace0[16];
/**Offset 0x0020
SPD Address of DIMM.
**/
UINT8 PcdSpdBaseAddress_0_0;
/**Offset 0x0021
SPD Address of DIMM.
**/
UINT8 PcdSpdBaseAddress_0_1;
/**Offset 0x0022
SPD Address of DIMM.
**/
UINT8 PcdSpdBaseAddress_1_0;
/**Offset 0x0023
SPD Address of DIMM.
**/
UINT8 PcdSpdBaseAddress_1_1;
/**Offset 0x0024
Size of SMRAM memory reserved.
**/
UINT8 PcdTsegSize;
/**Offset 0x0025
**/
UINT32 UnusedUpdSpace1;
/**Offset 0x0029
Size of memory preallocated for internal graphics.
**/
UINT8 PcdIgdDvmt50PreAlloc;
/**Offset 0x002A
Select which of IGFX/PEG/PCI Graphics device should be Primary Display.
**/
UINT8 PcdPrimaryDisplay;
/**Offset 0x002B
Enable/disable internal graphics.
**/
UINT8 PcdInternalGfx;
/**Offset 0x002C
Size of memory address space reserved for MMIO (Memory Mapped I/O).
**/
UINT8 PcdMmioSize;
/**Offset 0x002D
**/
UINT8 UnusedUpdSpace2;
/**Offset 0x002E
Select the Aperture Size.
**/
UINT8 PcdApertureSize;
/**Offset 0x0030
**/
UINT8 ReservedUpdSpace0[80];
/**Offset 0x002F
**/
UINT8 UnusedUpdSpace3;
/**Offset 0x0080
Enable/disable LAN controller.
**/
UINT8 PcdEnableLan;
/**Offset 0x0081
Enable/disable SATA controller.
**/
UINT8 PcdEnableSata;
/**Offset 0x0082
Select SATA controller working mode.
**/
UINT8 PcdSataMode;
/**Offset 0x0083
Enable/disable Azalia controller.
**/
UINT8 PcdEnableAzalia;
/**Offset 0x0084
Enable/disable XHCI controller.
**/
UINT8 PcdEnableXhci;
/**Offset 0x0085
Enable/disable EHCI controller #1.
**/
UINT8 PcdEnableEhci1;
/**Offset 0x0086
Enable/disable EHCI controller #2. Note this option is only applicable to SKUs with two EHCI controllers.
**/
UINT8 PcdEnableEhci2;
/**Offset 0x0087
Enable/disable SMBus
**/
UINT8 PcdEnableSmbus;
/**Offset 0x0088
Enable/disable PCH Audio DSP controller. Note: if enabled Azalia must be disabled.
**/
UINT8 PcdEnableAudioDsp;
/**Offset 0x0089
**/
UINT64 ReservedUpdSpace1;
/**Offset 0x0091
Power Management Base Address
**/
UINT16 PcdPmBase;
/**Offset 0x0093
Pch PCIe Root Port Enable. The bit 0 is mapped to port 1, bit 1 is mapped to port 2, and so on.
**/
UINT16 PcdPchPcieRootPortEnable;
/**Offset 0x0095
Pch PCIe Slot Implemented. The bit 0 is mapped to port 1, bit 1 is mapped to port 2, and so on.
**/
UINT16 PcdPchPcieSlotImplemented;
/**Offset 0x0097
Pch PCIe Root Port Function Swapping Enable
**/
UINT8 PcdPchPcieRootPortFunctionSwappingEnable;
/**Offset 0x0098
GPIO Base Address
**/
UINT16 PcdGpioBase;
/**Offset 0x009A
Pch SATA Port Enable. The bit 0 is mapped to port 1, bit 1 is mapped to port 2, and so on.
**/
UINT16 PcdPchSataPortEnable;
/**Offset 0x009C
SATA Drive Type. 0: HDD, 1: SDD. The bit 0 is mapped to port 1, bit 1 is mapped to port 2, and so on.
**/
UINT16 PcdPchSataSolidStateDrive;
/**Offset 0x009E
SATA Mechanical Presence Switch. 0: No, 1: Yes. The bit 0 is mapped to port 1, bit 1 is mapped to port 2, and so on.
**/
UINT16 PcdPchSataInterlockSw;
/**Offset 0x00A0
If enabled for any of ports Staggered Spin Up will be performed and only the drives which have this option enabled will spin up at boot. Otherwise all drives spin up at boot. 0: No, 1: Yes. The bit 0 is mapped to port 1, bit 1 is mapped to port 2, and so on.
**/
UINT16 PcdPchSataSpinUp;
/**Offset 0x00A2
Designates port as Hot Pluggable. 0: No, 1: Yes. The bit 0 is mapped to port 1, bit 1 is mapped to port 2, and so on.
**/
UINT16 PcdPchSataHotPlug;
/**Offset 0x00A4
**/
UINT8 UnusedUpdSpace5[92];
/**Offset 0x0100
Enable/disable Fast Boot function. Once enabled, all following boots will use the presaved MRC data to improve the boot performance.
**/
UINT8 PcdFastBoot;
/**Offset 0x0101
Specify the closest CRB board type to the platform.
**/
UINT8 PcdUserCrbBoardType;
/**Offset 0x0102
**/
UINT8 UnusedUpdSpace6[130];
/**Offset 0x0184
**/
AUDIO_AZALIA_VERB_TABLE* AzaliaVerbTablePtr;
/**Offset 0x0188
**/
UINT64 UnusedUpdSpace7;
/**Offset 0x0190
Indicate whether it comes with effective Dq/Dqs mapping data
**/
UINT8 DqDqsDataEffective;
/**Offset 0x0191
**/
UINT8 UnusedUpdSpace8[11];
/**Offset 0x019C
Dq byte mapping between CPU and DRAM
**/
UINT8 DqByteMap[24];
/**Offset 0x01B4
**/
UINT8 UnusedUpdSpace9[76];
/**Offset 0x0200
Set Dqs mapping relationship between CPU and DRAM
**/
UINT8 DqsMapCpu2Dram[16];
/**Offset 0x0210
**/
UINT32 SpdDataBuffer_0_0;
/**Offset 0x0214
**/
UINT32 SpdDataBuffer_0_1;
/**Offset 0x0218
**/
UINT32 SpdDataBuffer_1_0;
/**Offset 0x021C
**/
UINT32 SpdDataBuffer_1_1;
/**Offset 0x0220
**/
UINT8 UnusedUpdSpace10[240];
/**Offset 0x0310
**/
UINT16 PcdRegionTerminator;
} UPD_DATA_REGION;
#define FSP_IMAGE_ID 0x2450534657444224 /* '$BDWFSP$' */
#define FSP_IMAGE_REV 0x02090000
typedef struct _VPD_DATA_REGION {
/**Offset 0x0000
**/
UINT64 PcdVpdRegionSign;
/**Offset 0x0008
**/
UINT32 PcdImageRevision;
/**Offset 0x000C
**/
UINT32 PcdUpdRegionOffset;
/**Offset 0x0010
**/
UINT8 UnusedVpdSpace0[16];
/**Offset 0x0020
**/
UINT32 PcdFspReservedMemoryLength;
/**Offset 0x0024
Control where the Port 80h cycles are sent, 0: LPC; 1: PCI.
**/
UINT8 PcdPort80Route;
} VPD_DATA_REGION;
#pragma pack()
#endif

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@ -0,0 +1,90 @@
================================================================================
Intel® Firmware Support Package (Intel® FSP) for 3rd Generation Intel® Core™
Processors with Mobile Intel® HM76/QM77 Express Chipsets Gold Release Notes.
Release label: CHIEFRIVER_FSP_GOLD_001_09-OCTOBER-2013
October 09th 2013
================================================================================
================================================================================
Copyright (c) 2013, Intel Corporation.
This Intel® Firmware Support Package ("Software") is furnished under license and
may only be used or copied in accordance with the terms of that license.
No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. The Software is subject to change
without notice, and should not be construed as a commitment by Intel Corporation
to market, license, sell or support any product or technology. Unless otherwise
provided for in the license under which this Software is provided, the Software
is provided AS IS, with no warranties of any kind, express or implied.
Except as expressly permitted by the Software license, neither Intel Corporation
nor its suppliers assumes any responsibility or liability for any errors or
inaccuracies that may appear herein. Except as expressly permitted by the
Software license, no part of the Software may be reproduced, stored in a
retrieval system, transmitted in any form, or distributed by any means without
the express written consent of Intel Corporation.
================================================================================
================================================================================
RELEASE NOTES CONTENTS
================================================================================
1. OVERVIEW
2. RELEASE INFORMATION
3. INTEGRATION NOTES
4. CONFIGURATION
5. LIMITATIONS & KNOWN ISSUES
6. CHANGE LOG
================================================================================
1. OVERVIEW
================================================================================
This Gold package contains required binary image(s) and collateral for
Intel® Firmware Support Package (Intel® FSP) for 3rd Generation Intel® Core™
Processors with Mobile Intel® HM76/QM77 Express Chipsets.
This Gold package supports Intel® Firmware Support Package Design
Specification v1.0. Please consult the Intel® FSP Integration Guide for further
information.
================================================================================
2. RELEASE INFORMATION
================================================================================
This Gold release has been integrated into a coreboot Proof of Concept (POC)
bootloader and verified on the Cougar Canyon 2 Customer Reference Board (CRB).
================================================================================
3. INTEGRATION NOTES
================================================================================
Several header and source files are provided in the package to assist with
integrating the FSP with the bootloader.
Please consult the Intel® FSP Integration Guide for further information.
================================================================================
4. CONFIGURATION
================================================================================
A Binary Configuration Tool for Intel® FSP is available as a companion tool and
is intended to be used to:
- Change configuration options based on provided BSF and FSP.
- Rebase the FSP to a different Base Address.
Please refer the Binary Configuration Tool User's Guide for the usage
instructions.
================================================================================
5. LIMITATIONS & KNOWN ISSUES
================================================================================
- None
================================================================================
6. CHANGE LOG
================================================================================
Release CHIEFRIVER_FSP_GOLD_001_09-OCTOBER-2013:
- Gold Release.
================================================================================

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@ -0,0 +1,605 @@
//
// This file contains an 'Intel Peripheral Driver' and is
// licensed for Intel CPUs and chipsets under the terms of your
// license agreement with Intel or your vendor. This file must not
// be modified by end users or could render the generated boot loader
// inoperable.
//
// @file
// Boot Setting File for Platform: Cougar Canyon 2 Platform
//
// Copyright (c) 2010-2013 Intel Corporation. All rights reserved
// This software and associated documentation (if any) is furnished
// under a license and may only be used or copied in accordance
// with the terms of the license. Except as permitted by such
// license, no part of this software or documentation may be
// reproduced, stored in a retrieval system, or transmitted in any
// form or by any means without the express written consent of
// Intel Corporation.
//
//
GlobalDataDef
SKUID = 0, "DEFAULT"
CategoryID = %IVBSA, 0x00000001, "Ivy Bridge System Agent"
CategoryID = %PPTPCH, 0x00000002, "Panther Point PCH"
CategoryID = %CPUINIT, 0x00000004, "CPU Features"
EndGlobalData
StructDef
Find "CC2-FSPV"
$gPlatformFspPkgTokenSpaceGuid_PcdImageRevision 4 bytes $_DEFAULT_ = 0x00000001
Skip 8 bytes
$gPlatformFspPkgTokenSpaceGuid_PcdMeStolenSize 4 bytes $_DEFAULT_ = 0x00FF %IVBSA
$gPlatformFspPkgTokenSpaceGuid_PcdVgaMemoryEnable 1 byte $_DEFAULT_ = 1 %IVBSA
$gPlatformFspPkgTokenSpaceGuid_PcdFastTrainingMode 1 byte $_DEFAULT_ = 0 %IVBSA
$gPlatformFspPkgTokenSpaceGuid_PcdTsegSize 4 byte $_DEFAULT_ = 0x00800000 %IVBSA
$gPlatformFspPkgTokenSpaceGuid_PcdSpdAddress 8 bytes $_DEFAULT_ = 0xA0, 0xA2, 0xA4, 0xA6, 0x00, 0x00, 0x00, 0x00 %IVBSA
$gPlatformFspPkgTokenSpaceGuid_PcdEccSupport 1 byte $_DEFAULT_ = 1 %IVBSA
$gPlatformFspPkgTokenSpaceGuid_PcdDdrFreqLimit 2 byte $_DEFAULT_ = 0 %IVBSA
$gPlatformFspPkgTokenSpaceGuid_PcdNModeSupport 1 byte $_DEFAULT_ = 0x10 %IVBSA
$gPlatformFspPkgTokenSpaceGuid_PcdScramblerSupport 1 byte $_DEFAULT_ = 1 %IVBSA
$gPlatformFspPkgTokenSpaceGuid_PcdRmtCrosserEnable 1 byte $_DEFAULT_ = 0 %IVBSA
$gPlatformFspPkgTokenSpaceGuid_PcdThermalManagement 1 byte $_DEFAULT_ = 1 %IVBSA
$gPlatformFspPkgTokenSpaceGuid_PcdPowerDownMode 1 byte $_DEFAULT_ = 0xFF %IVBSA
$gPlatformFspPkgTokenSpaceGuid_PcdDisableDimmChannel0 1 byte $_DEFAULT_ = 0 %IVBSA
$gPlatformFspPkgTokenSpaceGuid_PcdDisableDimmChannel1 1 byte $_DEFAULT_ = 0 %IVBSA
$gPlatformFspPkgTokenSpaceGuid_PcdDDR3Voltage 1 byte $_DEFAULT_ = 3 %IVBSA
$gPlatformFspPkgTokenSpaceGuid_PcdDmiVc1 1 byte $_DEFAULT_ = 1 %IVBSA
$gPlatformFspPkgTokenSpaceGuid_PcdDmiVcp 1 byte $_DEFAULT_ = 1 %IVBSA
$gPlatformFspPkgTokenSpaceGuid_PcdDmiVcm 1 byte $_DEFAULT_ = 1 %IVBSA
$gPlatformFspPkgTokenSpaceGuid_PcdDmiGen2 1 byte $_DEFAULT_ = 2 %IVBSA
$gPlatformFspPkgTokenSpaceGuid_PcdPegGenx 4 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00 %IVBSA
$gPlatformFspPkgTokenSpaceGuid_PcdMmioSize 2 byte $_DEFAULT_ = 0x400 %IVBSA
$gPlatformFspPkgTokenSpaceGuid_PcdGttSize 2 byte $_DEFAULT_ = 2 %IVBSA
$gPlatformFspPkgTokenSpaceGuid_PcdIgdDvmt50PreAlloc 1 byte $_DEFAULT_ = 2 %IVBSA
$gPlatformFspPkgTokenSpaceGuid_PcdAlwaysEnablePeg 1 byte $_DEFAULT_ = 0 %IVBSA
$gPlatformFspPkgTokenSpaceGuid_PcdInternalGraphics 1 byte $_DEFAULT_ = 2 %IVBSA
$gPlatformFspPkgTokenSpaceGuid_PcdPrimaryDisplay 1 byte $_DEFAULT_ = 3 %IVBSA
$gPlatformFspPkgTokenSpaceGuid_PcdApertureSize 1 byte $_DEFAULT_ = 2 %IVBSA
$gPlatformFspPkgTokenSpaceGuid_PcdEnableGbe 1 byte $_DEFAULT_ = 1 %PPTPCH
$gPlatformFspPkgTokenSpaceGuid_PcdHpetEnable 1 byte $_DEFAULT_ = 1 %PPTPCH
$gPlatformFspPkgTokenSpaceGuid_PcdPchSataMode 1 byte $_DEFAULT_ = 1 %PPTPCH
$gPlatformFspPkgTokenSpaceGuid_PcdPchSata 1 byte $_DEFAULT_ = 1 %PPTPCH
$gPlatformFspPkgTokenSpaceGuid_PcdPchSmbus 1 byte $_DEFAULT_ = 1 %PPTPCH
$gPlatformFspPkgTokenSpaceGuid_PcdPchPciClockRun 1 byte $_DEFAULT_ = 1 %PPTPCH
$gPlatformFspPkgTokenSpaceGuid_PcdPchLan 1 byte $_DEFAULT_ = 1 %PPTPCH
$gPlatformFspPkgTokenSpaceGuid_PcdPchDisplay 1 byte $_DEFAULT_ = 1 %PPTPCH
$gPlatformFspPkgTokenSpaceGuid_PcdPchCrid 1 byte $_DEFAULT_ = 0 %PPTPCH
$gPlatformFspPkgTokenSpaceGuid_PcdPchAzalia 1 byte $_DEFAULT_ = 1 %PPTPCH
$gPlatformFspPkgTokenSpaceGuid_PcdUsbPerPortCtl 1 byte $_DEFAULT_ = 0 %PPTPCH
$gPlatformFspPkgTokenSpaceGuid_PcdEhci1Usbr 1 byte $_DEFAULT_ = 0 %PPTPCH
$gPlatformFspPkgTokenSpaceGuid_PcdEhci2Usbr 1 byte $_DEFAULT_ = 0 %PPTPCH
$gPlatformFspPkgTokenSpaceGuid_PcdPortLength 28 byte $_DEFAULT_ = 0x09, 0x01, 0x01, 0x01, 0x12, 0x01, 0x15, 0x01, 0x37,0x00, 0x27, 0x00, 0x41, 0x00, 0x45, 0x00, 0x07, 0x01, 0x05, 0x01, 0x42, 0x00, 0x43, 0x00, 0x31, 0x00, 0x29, 0x00 %PPTPCH
$gPlatformFspPkgTokenSpaceGuid_PcdOverCurrentMappings 14 bytes $_DEFAULT_ = 0x00, 0x00, 0x01, 0x01, 0x02, 0x02, 0x03, 0x03, 0x04, 0x04, 0x05, 0x05, 0x06, 0x06 %PPTPCH
$gPlatformFspPkgTokenSpaceGuid_PcdXhciMode 2 byte $_DEFAULT_ = 2 %PPTPCH
$gPlatformFspPkgTokenSpaceGuid_PcdXhciHsPortSwitchMask 2 byte $_DEFAULT_ = 0x000F %PPTPCH
$gPlatformFspPkgTokenSpaceGuid_PcdXhciPreBootSupport 2 byte $_DEFAULT_ = 0 %PPTPCH
$gPlatformFspPkgTokenSpaceGuid_PcdXhciStreams 2 byte $_DEFAULT_ = 1 %PPTPCH
$gPlatformFspPkgTokenSpaceGuid_PcdPchPciePortEn 8 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 %PPTPCH
$gPlatformFspPkgTokenSpaceGuid_PcdPchPciePortHide 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 %PPTPCH
$gPlatformFspPkgTokenSpaceGuid_PcdPchPciePortSlotImplemented 8 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 %PPTPCH
$gPlatformFspPkgTokenSpaceGuid_PcdPchPciePortHotplug 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 %PPTPCH
$gPlatformFspPkgTokenSpaceGuid_PcdPchSataPortEn 8 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00 %PPTPCH
$gPlatformFspPkgTokenSpaceGuid_PcdPchDmiAspm 1 byte $_DEFAULT_ = 1 %PPTPCH
$gPlatformFspPkgTokenSpaceGuid_PcdPchDmiAspmCtrl 1 byte $_DEFAULT_ = 0 %PPTPCH
$gPlatformFspPkgTokenSpaceGuid_PcdPchDmiExtSync 1 byte $_DEFAULT_ = 0 %PPTPCH
$gPlatformFspPkgTokenSpaceGuid_PcdDmiAspm 1 byte $_DEFAULT_ = 3 %IVBSA
$gPlatformFspPkgTokenSpaceGuid_PcdPegAspm 1 byte $_DEFAULT_ = 0 %IVBSA
$gPlatformFspPkgTokenSpaceGuid_PcdDmiExtSync 1 byte $_DEFAULT_ = 0 %IVBSA
$gPlatformFspPkgTokenSpaceGuid_PcdDeEmphasis 1 byte $_DEFAULT_ = 1 %IVBSA
$gPlatformFspPkgTokenSpaceGuid_PcdPortSettingsEnable 14 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 %PPTPCH
$gPlatformFspPkgTokenSpaceGuid_PcdPortSettingsPanel 14 bytes $_DEFAULT_ = 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0x01 %PPTPCH
$gPlatformFspPkgTokenSpaceGuid_PcdPortSettingsDock 14 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 %PPTPCH
$gPlatformFspPkgTokenSpaceGuid_PcdPort80Route 1 byte $_DEFAULT_ = 0 %PPTPCH
$gPlatformFspPkgTokenSpaceGuid_PcdPchGlobalSmi 1 byte $_DEFAULT_ = 1 %PPTPCH
$gPlatformFspPkgTokenSpaceGuid_PcdPchBiosInterface 1 byte $_DEFAULT_ = 1 %PPTPCH
$gPlatformFspPkgTokenSpaceGuid_PcdPchGpioLockDown 1 byte $_DEFAULT_ = 0 %PPTPCH
$gPlatformFspPkgTokenSpaceGuid_PcdPchRtcLock 1 byte $_DEFAULT_ = 1 %PPTPCH
$gPlatformFspPkgTokenSpaceGuid_PcdPchBiosLock 1 byte $_DEFAULT_ = 0 %PPTPCH
$gPlatformFspPkgTokenSpaceGuid_PcdPchNoaLock 1 byte $_DEFAULT_ = 1 %PPTPCH
$gPlatformFspPkgTokenSpaceGuid_PcdFeatureConfigure 1 byte $_DEFAULT_ = 1 %CPUINIT
$gPlatformFspPkgTokenSpaceGuid_PcdLimitCpuidMaximumValue 1 byte $_DEFAULT_ = 0 %CPUINIT
$gPlatformFspPkgTokenSpaceGuid_PcdVmxEnable 1 byte $_DEFAULT_ = 1 %CPUINIT
$gPlatformFspPkgTokenSpaceGuid_PcdTxtEnable 1 byte $_DEFAULT_ = 0 %CPUINIT
$gPlatformFspPkgTokenSpaceGuid_PcdMonitorMwaitEnable 1 byte $_DEFAULT_ = 1 %CPUINIT
$gPlatformFspPkgTokenSpaceGuid_PcdExecuteDisableBit 1 byte $_DEFAULT_ = 1 %CPUINIT
$gPlatformFspPkgTokenSpaceGuid_PcdFastString 1 byte $_DEFAULT_ = 1 %CPUINIT
$gPlatformFspPkgTokenSpaceGuid_PcdMachineCheckEnable 1 byte $_DEFAULT_ = 1 %CPUINIT
$gPlatformFspPkgTokenSpaceGuid_PcdXapicEnable 1 byte $_DEFAULT_ = 0 %CPUINIT
$gPlatformFspPkgTokenSpaceGuid_PcdDcaEnable 1 byte $_DEFAULT_ = 0 %CPUINIT
EndStruct
List &EN_DIS
Selection 0x1 , "Enabled"
Selection 0x0 , "Disabled"
EndList
List &PORT80_ROUT
Selection 0x1 , "PCI"
Selection 0x0 , "LPC"
EndList
List &MEM_SIZES
Selection 0x00, "0 MB"
Selection 0x01, "1 MB"
Selection 0x02, "2 MB"
Selection 0x04, "4 MB"
Selection 0x08, "8 MB"
Selection 0x10, "16 MB"
Selection 0x20, "32 MB"
Selection 0xFF, "Autoconfig"
EndList
List &APER_MEM
Selection 0x01, "128 MB"
Selection 0x02, "256 MB"
Selection 0x03, "512 MB"
EndList
List &GTT_MEM
Selection 0x00, "Disable"
Selection 0x01, "1 MB"
Selection 0x02, "2 MB"
EndList
List &GMS_MEM
Selection 00h, "0 MB"
Selection 01h, "32 MB"
Selection 02h, "64 MB"
Selection 03h, "96 MB"
Selection 04h, "128 MB"
Selection 05h, "160 MB"
Selection 06h, "192 MB"
Selection 07h, "224 MB"
Selection 08h, "256 MB"
Selection 09h, "288 MB"
Selection 0Ah, "320 MB"
Selection 0Bh, "352 MB"
Selection 0Ch, "384 MB"
Selection 0Dh, "416 MB"
Selection 0Eh, "448 MB"
Selection 0Fh, "480 MB"
Selection 10h, "512 MB"
Selection 11h, "1 GB"
EndList
List &DDR_FREQ
Selection 0x00, "Auto"
Selection 0x01, "800"
Selection 0x02, "1067"
Selection 0x03, "1333"
Selection 0x04, "1400"
Selection 0x05, "1600"
Selection 0x06, "1800"
Selection 0x07, "1867"
Selection 0x08, "2000"
Selection 0x09, "2133"
EndList
List &DIMM_CTRL
Selection 0, "Enable Both"
Selection 1, "Disable DIMM0"
Selection 2, "Disable DIMM1"
Selection 3, "Disable Both"
EndList
List &DDR3LV
Selection 0, "Disable"
Selection 1, "DDR3"
Selection 2, "DDR3L"
Selection 3, "DDR3 & DDR3L"
EndList
List &N_MODE
Selection 16, "Auto"
Selection 0, "1 N Mode"
Selection 2, "2 N Mode"
EndList
List &ASPM
Selection 0, "Disable"
Selection 1, "Enable L0s"
Selection 2, "Enable L1"
Selection 3, "Enable L0s and L1"
Selection 4, "AutoConfig"
EndList
List &PEG_GEN
Selection 0, "Auto"
Selection 1, "Gen1"
Selection 2, "Gen2"
Selection 3, "Gen3"
EndList
List &PEG_CONFIG
Selection 0, "Enable Peg when a PCIe device was detected"
Selection 1, "Always enable Peg"
EndList
List &PRI_DISP
Selection 0, "IGD"
Selection 1, "PEG"
Selection 2, "PCI"
Selection 3, "Auto"
EndList
List &EN_DIS_AUTO
Selection 0, "Disable"
Selection 1, "Enable"
Selection 2, "Auto"
EndList
List &PWRDOWN_MODE
Selection 0, "Power Down Disabled"
Selection 1, "APD"
Selection 2, "PPD"
Selection 3, "APD & PPD"
Selection 6, "DLL OFF"
Selection 7, "APD & DLL OFF"
Selection 0xFF, "Default"
EndList
List &SATA_MODE
Selection 0, "IDE"
Selection 1, "AHCI"
Selection 2, "RAID"
EndList
List &PANEL_CONFIG
Selection 0, "Back Pannel"
Selection 1, "Front Pannel"
EndList
List &DOCK_CONFIG
Selection 0, "Not Docking Port"
Selection 1, "Docking Port"
EndList
List &XHCI_MODE
Selection 0, "Off"
Selection 1, "On"
Selection 2, "Auto"
Selection 3, "Smart Auto"
EndList
List &XHCI_PREBOOT
Selection 0, "No xHCI Driver Available"
Selection 1, "xHCI Driver Available"
EndList
List &LOCK
Selection 0, "Lock Disable"
Selection 1, "Lock Enable"
EndList
BeginInfoBlock
PPVer "0.1"
Description "Cougar Canyon 2 FSP Configuration"
EndInfoBlock
Page "Ivy Bridge System Agent"
Combo $gPlatformFspPkgTokenSpaceGuid_PcdMeStolenSize, "ME Stolen Memory Size", &MEM_SIZES,
Help "Size of memory reserved for ME, in MB."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdVgaMemoryEnable, "IGD Memroy Reserve", &EN_DIS,
Help "Configure IGD Memory Reserve"
Combo $gPlatformFspPkgTokenSpaceGuid_PcdFastTrainingMode, "Memory Fast Trainning Mode", &EN_DIS,
Help "Configure Memory Fast Training Mode"
EditNum $gPlatformFspPkgTokenSpaceGuid_PcdTsegSize, "TSEG Memory Size", HEX,
Help "Size of memory reserved for TSEG, in Byte."
Table $gPlatformFspPkgTokenSpaceGuid_PcdSpdAddress "Configure Memory DIMM SPD Address",
Column "DIMM 0", 1 byte, HEX
Column "DIMM 1", 1 byte, HEX
Column "DIMM 2", 1 byte, HEX
Column "DIMM 3", 1 byte, HEX
Column "n/a", 1 byte, HEX
Column "n/a", 1 byte, HEX
Column "n/a", 1 byte, HEX
Column "n/a", 1 byte, HEX,
Help "Configure Memory DIMM SPD Address."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdEccSupport, "ECC", &EN_DIS,
Help "Configure Memory ECC"
Combo $gPlatformFspPkgTokenSpaceGuid_PcdDdrFreqLimit, "DDR Frequency Limitation", &DDR_FREQ,
Help "DDR Frequency Limitation, default Auto"
Combo $gPlatformFspPkgTokenSpaceGuid_PcdNModeSupport, "NMode Selection", &N_MODE,
Help "NModeSupport configuration, default Auto"
Combo $gPlatformFspPkgTokenSpaceGuid_PcdScramblerSupport, "Scrambler", &EN_DIS,
Help "Scrambler configuration"
Combo $gPlatformFspPkgTokenSpaceGuid_PcdRmtCrosserEnable, "Rmt Crosser", &EN_DIS,
Help "Rmt Crosser configuration"
Combo $gPlatformFspPkgTokenSpaceGuid_PcdThermalManagement, "Thermal Management", &EN_DIS,
Help "Thermal Management configuration"
Combo $gPlatformFspPkgTokenSpaceGuid_PcdPowerDownMode, "Power Down Mode", &PWRDOWN_MODE,
Help "Powern Down Mode configuration, default 0xFF"
Combo $gPlatformFspPkgTokenSpaceGuid_PcdDisableDimmChannel0, "DIMM Channel 0", &DIMM_CTRL,
Help "DIMM Channel 0 configuration"
Combo $gPlatformFspPkgTokenSpaceGuid_PcdDisableDimmChannel1, "DIMM Channel 1", &DIMM_CTRL,
Help "DIMM Channel 1 configuration"
Combo $gPlatformFspPkgTokenSpaceGuid_PcdDDR3Voltage, "DDR3 Voltage", &DDR3LV,
Help "DDR3 Voltage Support configuration"
Combo $gPlatformFspPkgTokenSpaceGuid_PcdDmiVc1, "SA DMI Vc1", &EN_DIS,
Help "SA DMI Vc1 configuration"
Combo $gPlatformFspPkgTokenSpaceGuid_PcdDmiVcp, "SA DMI Vcp", &EN_DIS,
Help "SA DMI Vcp configuration"
Combo $gPlatformFspPkgTokenSpaceGuid_PcdDmiVcm, "SA DMI Vcm", &EN_DIS,
Help "SA DMI Vcm configuration"
Combo $gPlatformFspPkgTokenSpaceGuid_PcdDmiGen2, "SA DMI Gen2", &EN_DIS_AUTO,
Help "SA DMI Gen2 Mode configuration"
Table $gPlatformFspPkgTokenSpaceGuid_PcdPegGenx "Configure Peg Genx",
Column "Peg 0", 1 byte, HEX
Column "Peg 1", 1 byte, HEX
Column "Peg 2", 1 byte, HEX
Column "Peg 3", 1 byte, HEX,
Help "Configure PEG Genx Mode."
"0 - Auto"
"1 - Gen1"
"2 - Gen2"
"3 - Gen3"
EditNum $gPlatformFspPkgTokenSpaceGuid_PcdMmioSize, "MMIO Size", HEX,
Help "Size of memory reserved for MMIO, in MB."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdGttSize, "GTT Size", &GTT_MEM,
Help "Configure Graphics GTT Memory Size."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdIgdDvmt50PreAlloc, "Graphics Mode Select Memory Size", &GMS_MEM,
Help "Configure Graphics Mode Select Memory Pre-allocated size."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdAlwaysEnablePeg, "PEG", &PEG_CONFIG,
Help "Configure PEG."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdInternalGraphics, "IGD", &EN_DIS_AUTO,
Help "Configure IGD."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdPrimaryDisplay, "Primary Display Device", &PRI_DISP,
Help "Configure Primary Display Device."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdApertureSize, "Aperture Size", &APER_MEM,
Help "Configure Aperture Size."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdDmiAspm, "DMI ASPM", &ASPM,
Help "Configure DMI ASPM."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdPegAspm, "PEG ASPM", &ASPM,
Help "Configure PEG ASPM."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdDmiExtSync, "DMI Exit Sync", &EN_DIS,
Help "Determines if force extended transmission of FTS ordered sets when exiting L0s prior to entering L0."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdDeEmphasis, "SA DeEmphasis", &EN_DIS,
Help "Configure SA DeEmphasis."
EndPage
Page "Panther Point PCH"
Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableGbe, "PCH Gbe", &EN_DIS,
Help "Configure PCH Gbe."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdPort80Route, "Port 80 Route", &PORT80_ROUT,
Help "Configure Port 80 Route."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdHpetEnable, "PCH HPET", &EN_DIS,
Help "Configure PCH HPET."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdPchSataMode, "SATA Mode", &SATA_MODE,
Help "Configure PCH SATA Mode."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdPchSata, "PCH SATA", &EN_DIS,
Help "Configure PCH SATA."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdPchSmbus, "PCH SMBUS", &EN_DIS,
Help "Configure PCH SMBUS."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdPchPciClockRun, "PCI Clock Run", &EN_DIS,
Help "Configure PCH PCI Clock Run."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdPchDisplay, "PCH Display", &EN_DIS,
Help "Configure PCH Display."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdPchCrid, "PCH Crid", &EN_DIS,
Help "Configure PCH Crid."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdPchAzalia, "PCH Azalia", &EN_DIS_AUTO,
Help "Configure PCH Azalia."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdUsbPerPortCtl, "USB Pre-Port Control", &EN_DIS,
Help "PCH USB Pre-Port Control."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdEhci1Usbr, "EHCI #1 Usbr", &EN_DIS,
Help "Configure EHCI #1 Usbr."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdEhci2Usbr, "EHCI #2 Usbr", &EN_DIS,
Help "Configure EHCI #2 Usbr."
Table $gPlatformFspPkgTokenSpaceGuid_PcdPortLength "USB Port Length",
Column "Port 0", 2 byte, HEX
Column "Port 1", 2 byte, HEX
Column "Port 2", 2 byte, HEX
Column "Port 3", 2 byte, HEX
Column "Port 4", 2 byte, HEX
Column "Port 5", 2 byte, HEX
Column "Port 6", 2 byte, HEX
Column "Port 7", 2 byte, HEX
Column "Port 8", 2 byte, HEX
Column "Port 9", 2 byte, HEX
Column "Port 10", 2 byte, HEX
Column "Port 11", 2 byte, HEX
Column "Port 12", 2 byte, HEX
Column "Port 13", 2 byte, HEX,
Help "Configure USB Port Length."
Table $gPlatformFspPkgTokenSpaceGuid_PcdPortSettingsEnable "USB Ports Enable",
Column "Port 0", 1 byte, HEX
Column "Port 1", 1 byte, HEX
Column "Port 2", 1 byte, HEX
Column "Port 3", 1 byte, HEX
Column "Port 4", 1 byte, HEX
Column "Port 5", 1 byte, HEX
Column "Port 6", 1 byte, HEX
Column "Port 7", 1 byte, HEX
Column "Port 8", 1 byte, HEX
Column "Port 9", 1 byte, HEX
Column "Port 10", 1 byte, HEX
Column "Port 11", 1 byte, HEX
Column "Port 12", 1 byte, HEX
Column "Port 13", 1 byte, HEX,
Help "Configure USB Ports."
"0 - Disable"
"1 - Enable"
Table $gPlatformFspPkgTokenSpaceGuid_PcdPortSettingsPanel "USB Ports Panel",
Column "Port 0", 1 byte, HEX
Column "Port 1", 1 byte, HEX
Column "Port 2", 1 byte, HEX
Column "Port 3", 1 byte, HEX
Column "Port 4", 1 byte, HEX
Column "Port 5", 1 byte, HEX
Column "Port 6", 1 byte, HEX
Column "Port 7", 1 byte, HEX
Column "Port 8", 1 byte, HEX
Column "Port 9", 1 byte, HEX
Column "Port 10", 1 byte, HEX
Column "Port 11", 1 byte, HEX
Column "Port 12", 1 byte, HEX
Column "Port 13", 1 byte, HEX,
Help "Configure USB Ports Panel, Desktop PPT ONLY."
"0 - Back Pannel"
"1 - Front Pannel"
Table $gPlatformFspPkgTokenSpaceGuid_PcdPortSettingsDock "USB Ports Dock",
Column "Port 0", 1 byte, HEX
Column "Port 1", 1 byte, HEX
Column "Port 2", 1 byte, HEX
Column "Port 3", 1 byte, HEX
Column "Port 4", 1 byte, HEX
Column "Port 5", 1 byte, HEX
Column "Port 6", 1 byte, HEX
Column "Port 7", 1 byte, HEX
Column "Port 8", 1 byte, HEX
Column "Port 9", 1 byte, HEX
Column "Port 10", 1 byte, HEX
Column "Port 11", 1 byte, HEX
Column "Port 12", 1 byte, HEX
Column "Port 13", 1 byte, HEX,
Help "Configure USB Ports Docking, Mobile PPT ONLY."
"0 - Not Docking Port"
"1 - Docking Port"
Table $gPlatformFspPkgTokenSpaceGuid_PcdOverCurrentMappings "Configure USB Overcurrent Pin Mappings",
Column "Port 0", 1 byte, HEX
Column "Port 1", 1 byte, HEX
Column "Port 2", 1 byte, HEX
Column "Port 3", 1 byte, HEX
Column "Port 4", 1 byte, HEX
Column "Port 5", 1 byte, HEX
Column "Port 6", 1 byte, HEX
Column "Port 7", 1 byte, HEX
Column "Port 8", 1 byte, HEX
Column "Port 9", 1 byte, HEX
Column "Port 10", 1 byte, HEX
Column "Port 11", 1 byte, HEX
Column "Port 12", 1 byte, HEX
Column "Port 13", 1 byte, HEX,
Help "Configure USB Overcurrent Pin Mappings."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdXhciMode, "XHCI Mode", &XHCI_MODE,
Help "Configure XHCI Mode."
EditNum $gPlatformFspPkgTokenSpaceGuid_PcdXhciHsPortSwitchMask, "XHCI Port Switch", HEX,
Help "Configure USB 3.0 Port Switch Mask."
"BIT[0:3] Bit Mask"
"0 - Port not Switchable"
"1 - Port Switchable"
Combo $gPlatformFspPkgTokenSpaceGuid_PcdXhciPreBootSupport, "XHCI Pre-Boot Support", &XHCI_PREBOOT,
Help "Configure USB 3.0 Pre Boot Support."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdXhciStreams, "XHCI Stream Support", &EN_DIS,
Help "Configure USB 3.0 Stream Support."
Table $gPlatformFspPkgTokenSpaceGuid_PcdPchPciePortEn "Configure PCH PCIE Root Ports",
Column "Port 0", 1 byte, HEX
Column "Port 1", 1 byte, HEX
Column "Port 2", 1 byte, HEX
Column "Port 3", 1 byte, HEX
Column "Port 4", 1 byte, HEX
Column "Port 5", 1 byte, HEX
Column "Port 6", 1 byte, HEX
Column "Port 7", 1 byte, HEX,
Help "Configure PCH PCIE Root Ports."
"0 - Disable"
"1 - Enable"
Table $gPlatformFspPkgTokenSpaceGuid_PcdPchPciePortHide "Hide PCH PCIE Root Ports",
Column "Port 0", 1 byte, HEX
Column "Port 1", 1 byte, HEX
Column "Port 2", 1 byte, HEX
Column "Port 3", 1 byte, HEX
Column "Port 4", 1 byte, HEX
Column "Port 5", 1 byte, HEX
Column "Port 6", 1 byte, HEX
Column "Port 7", 1 byte, HEX,
Help "Configure PCH PCI-E Root Port whether or not to hide the configuration space."
"0 - Disable"
"1 - Enable"
Table $gPlatformFspPkgTokenSpaceGuid_PcdPchPciePortSlotImplemented "Slots behind PCH PCIE Root Ports",
Column "Port 0", 1 byte, HEX
Column "Port 1", 1 byte, HEX
Column "Port 2", 1 byte, HEX
Column "Port 3", 1 byte, HEX
Column "Port 4", 1 byte, HEX
Column "Port 5", 1 byte, HEX
Column "Port 6", 1 byte, HEX
Column "Port 7", 1 byte, HEX,
Help "Configure PCH PCI-E Root Port SlotImplemented."
"0 - Disable"
"1 - Enable"
Table $gPlatformFspPkgTokenSpaceGuid_PcdPchPciePortHotplug "Hot Plug on PCH PCIE Root Ports",
Column "Port 0", 1 byte, HEX
Column "Port 1", 1 byte, HEX
Column "Port 2", 1 byte, HEX
Column "Port 3", 1 byte, HEX
Column "Port 4", 1 byte, HEX
Column "Port 5", 1 byte, HEX
Column "Port 6", 1 byte, HEX
Column "Port 7", 1 byte, HEX,
Help "Configure PCH PCI-E Root Port Hotplug."
"0 - Disable"
"1 - Enable"
Table $gPlatformFspPkgTokenSpaceGuid_PcdPchSataPortEn "PCH SATA Ports",
Column "Port 0", 1 byte, HEX
Column "Port 1", 1 byte, HEX
Column "Port 2", 1 byte, HEX
Column "Port 3", 1 byte, HEX
Column "Port 4", 1 byte, HEX
Column "Port 5", 1 byte, HEX
Column "n/a", 1 byte, HEX
Column "n/a", 1 byte, HEX,
Help "Configure PCH SATA Ports."
"0 - Disable"
"1 - Enable"
Combo $gPlatformFspPkgTokenSpaceGuid_PcdPchGlobalSmi, "Global SMI", &LOCK,
Help "Configure Lock Global SMI Enable/Disable."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdPchBiosInterface, "BIOS Interface", &LOCK,
Help "Configure Lock BIOS Interface Enable/Disable."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdPchGpioLockDown, "GPIO Lock Down", &LOCK,
Help "Configure GPIO Lock Down."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdPchRtcLock, "RTC", &LOCK,
Help "Configure Lock RTC Enable/Disable."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdPchBiosLock, "BIOS", &LOCK,
Help "Configure Lock BIOS Enable/Disable."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdPchNoaLock, "NOA", &LOCK,
Help "Configure Lock NOA Enable/Disable."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdPchDmiAspm, "PCH DMI ASPM", &EN_DIS,
Help "PCH DMI ASPM Enable/Disable."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdPchDmiAspmCtrl, "PCH DMI ASPM Configure", &ASPM,
Help "Configure PCH DMI ASPM."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdPchDmiExtSync, "PCH DMI Exit Sync", &EN_DIS,
Help "Determines if force extended transmission of FTS ordered sets when exiting L0s prior to entering L0."
EndPage
Page "CPU Features"
Combo $gPlatformFspPkgTokenSpaceGuid_PcdFeatureConfigure, "FSP Configure CPU features", &EN_DIS,
Help "Determines if FSP is used to configure CPU features."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdLimitCpuidMaximumValue, "Limit MAX CPUID", &EN_DIS,
Help "Determines if Limit Max CPUID feature enable or disable."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdVmxEnable, "Intel Virtualization Technology", &EN_DIS,
Help "Determines if Intel Virtualization Technology enable or disable."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdTxtEnable, "Intel Trusted Execution Technology", &EN_DIS,
Help "Determines if Intel Trusted Execution Technology enable or disable."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdMonitorMwaitEnable, "Monitor & Mwait", &EN_DIS,
Help "Determines if Monitor and Mwait enable or disable."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdExecuteDisableBit, "Execute Disable Bit", &EN_DIS,
Help "Determines if Execute Disable Bit enable or disable."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdFastString, "Fast String", &EN_DIS,
Help "Determines if Fast String enable or disable."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdMachineCheckEnable, "MCE", &EN_DIS,
Help "Determines if MCE enable or disable."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdXapicEnable, "XAPIC", &EN_DIS,
Help "Determines if XAPIC enable or disable."
Combo $gPlatformFspPkgTokenSpaceGuid_PcdDcaEnable, "DCA", &EN_DIS,
Help "Determines if DCA enable or disable."
EndPage

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/** @file
Copyright (C) 2013, Intel Corporation
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
**/
#ifndef _FSP_API_H_
#define _FSP_API_H_
#pragma pack(1)
typedef VOID (* CONTINUATION_PROC)(EFI_STATUS Status, VOID *HobListPtr);
typedef struct {
VOID *NvsBufferPtr;
VOID *RtBufferPtr;
CONTINUATION_PROC ContinuationFunc;
} FSP_INIT_PARAMS;
typedef struct {
UINT32 *StackTop;
UINT32 BootMode;
} FSP_INIT_RT_COMMON_BUFFER;
typedef enum {
EnumInitPhaseAfterPciEnumeration = 0x20,
EnumInitPhaseReadyToBoot = 0x40
} FSP_INIT_PHASE;
typedef struct {
FSP_INIT_PHASE Phase;
} NOTIFY_PHASE_PARAMS;
#pragma pack()
typedef FSP_STATUS (FSPAPI *FSP_FSP_INIT) (FSP_INIT_PARAMS *FspInitParamPtr);
typedef FSP_STATUS (FSPAPI *FSP_NOTFY_PHASE) (NOTIFY_PHASE_PARAMS *NotifyPhaseParamPtr);
#endif

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/** @file
Copyright (C) 2013, Intel Corporation
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
**/
#ifndef __PI_FIRMWARE_FILE_H__
#define __PI_FIRMWARE_FILE_H__
#pragma pack(1)
///
/// Used to verify the integrity of the file.
///
typedef union {
struct {
///
/// The IntegrityCheck.Checksum.Header field is an 8-bit checksum of the file
/// header. The State and IntegrityCheck.Checksum.File fields are assumed
/// to be zero and the checksum is calculated such that the entire header sums to zero.
///
UINT8 Header;
///
/// If the FFS_ATTRIB_CHECKSUM (see definition below) bit of the Attributes
/// field is set to one, the IntegrityCheck.Checksum.File field is an 8-bit
/// checksum of the file data.
/// If the FFS_ATTRIB_CHECKSUM bit of the Attributes field is cleared to zero,
/// the IntegrityCheck.Checksum.File field must be initialized with a value of
/// 0xAA. The IntegrityCheck.Checksum.File field is valid any time the
/// EFI_FILE_DATA_VALID bit is set in the State field.
///
UINT8 File;
} Checksum;
///
/// This is the full 16 bits of the IntegrityCheck field.
///
UINT16 Checksum16;
} EFI_FFS_INTEGRITY_CHECK;
///
/// FFS_FIXED_CHECKSUM is the checksum value used when the
/// FFS_ATTRIB_CHECKSUM attribute bit is clear.
///
#define FFS_FIXED_CHECKSUM 0xAA
typedef UINT8 EFI_FV_FILETYPE;
typedef UINT8 EFI_FFS_FILE_ATTRIBUTES;
typedef UINT8 EFI_FFS_FILE_STATE;
///
/// File Types Definitions
///
#define EFI_FV_FILETYPE_ALL 0x00
#define EFI_FV_FILETYPE_RAW 0x01
#define EFI_FV_FILETYPE_FREEFORM 0x02
#define EFI_FV_FILETYPE_SECURITY_CORE 0x03
#define EFI_FV_FILETYPE_PEI_CORE 0x04
#define EFI_FV_FILETYPE_DXE_CORE 0x05
#define EFI_FV_FILETYPE_PEIM 0x06
#define EFI_FV_FILETYPE_DRIVER 0x07
#define EFI_FV_FILETYPE_COMBINED_PEIM_DRIVER 0x08
#define EFI_FV_FILETYPE_APPLICATION 0x09
#define EFI_FV_FILETYPE_SMM 0x0A
#define EFI_FV_FILETYPE_FIRMWARE_VOLUME_IMAGE 0x0B
#define EFI_FV_FILETYPE_COMBINED_SMM_DXE 0x0C
#define EFI_FV_FILETYPE_SMM_CORE 0x0D
#define EFI_FV_FILETYPE_OEM_MIN 0xc0
#define EFI_FV_FILETYPE_OEM_MAX 0xdf
#define EFI_FV_FILETYPE_DEBUG_MIN 0xe0
#define EFI_FV_FILETYPE_DEBUG_MAX 0xef
#define EFI_FV_FILETYPE_FFS_MIN 0xf0
#define EFI_FV_FILETYPE_FFS_MAX 0xff
#define EFI_FV_FILETYPE_FFS_PAD 0xf0
///
/// FFS File Attributes.
///
#define FFS_ATTRIB_LARGE_FILE 0x01
#define FFS_ATTRIB_FIXED 0x04
#define FFS_ATTRIB_DATA_ALIGNMENT 0x38
#define FFS_ATTRIB_CHECKSUM 0x40
///
/// FFS File State Bits.
///
#define EFI_FILE_HEADER_CONSTRUCTION 0x01
#define EFI_FILE_HEADER_VALID 0x02
#define EFI_FILE_DATA_VALID 0x04
#define EFI_FILE_MARKED_FOR_UPDATE 0x08
#define EFI_FILE_DELETED 0x10
#define EFI_FILE_HEADER_INVALID 0x20
///
/// Each file begins with the header that describe the
/// contents and state of the files.
///
typedef struct {
///
/// This GUID is the file name. It is used to uniquely identify the file.
///
EFI_GUID Name;
///
/// Used to verify the integrity of the file.
///
EFI_FFS_INTEGRITY_CHECK IntegrityCheck;
///
/// Identifies the type of file.
///
EFI_FV_FILETYPE Type;
///
/// Declares various file attribute bits.
///
EFI_FFS_FILE_ATTRIBUTES Attributes;
///
/// The length of the file in bytes, including the FFS header.
///
UINT8 Size[3];
///
/// Used to track the state of the file throughout the life of the file from creation to deletion.
///
EFI_FFS_FILE_STATE State;
} EFI_FFS_FILE_HEADER;
typedef struct {
///
/// This GUID is the file name. It is used to uniquely identify the file. There may be only
/// one instance of a file with the file name GUID of Name in any given firmware
/// volume, except if the file type is EFI_FV_FILETYPE_FFS_PAD.
///
EFI_GUID Name;
///
/// Used to verify the integrity of the file.
///
EFI_FFS_INTEGRITY_CHECK IntegrityCheck;
///
/// Identifies the type of file.
///
EFI_FV_FILETYPE Type;
///
/// Declares various file attribute bits.
///
EFI_FFS_FILE_ATTRIBUTES Attributes;
///
/// The length of the file in bytes, including the FFS header.
/// The length of the file data is either (Size - sizeof(EFI_FFS_FILE_HEADER)). This calculation means a
/// zero-length file has a Size of 24 bytes, which is sizeof(EFI_FFS_FILE_HEADER).
/// Size is not required to be a multiple of 8 bytes. Given a file F, the next file header is
/// located at the next 8-byte aligned firmware volume offset following the last byte of the file F.
///
UINT8 Size[3];
///
/// Used to track the state of the file throughout the life of the file from creation to deletion.
///
EFI_FFS_FILE_STATE State;
///
/// If FFS_ATTRIB_LARGE_FILE is set in Attributes, then ExtendedSize exists and Size must be set to zero.
/// If FFS_ATTRIB_LARGE_FILE is not set then EFI_FFS_FILE_HEADER is used.
///
UINT32 ExtendedSize;
} EFI_FFS_FILE_HEADER2;
#define IS_FFS_FILE2(FfsFileHeaderPtr) \
(((((EFI_FFS_FILE_HEADER *) (UINTN) FfsFileHeaderPtr)->Attributes) & FFS_ATTRIB_LARGE_FILE) == FFS_ATTRIB_LARGE_FILE)
#define FFS_FILE_SIZE(FfsFileHeaderPtr) \
((UINT32) (*((UINT32 *) ((EFI_FFS_FILE_HEADER *) (UINTN) FfsFileHeaderPtr)->Size) & 0x00ffffff))
#define FFS_FILE2_SIZE(FfsFileHeaderPtr) \
(((EFI_FFS_FILE_HEADER2 *) (UINTN) FfsFileHeaderPtr)->ExtendedSize)
typedef UINT8 EFI_SECTION_TYPE;
///
/// Pseudo type. It is used as a wild card when retrieving sections.
/// The section type EFI_SECTION_ALL matches all section types.
///
#define EFI_SECTION_ALL 0x00
///
/// Encapsulation section Type values.
///
#define EFI_SECTION_COMPRESSION 0x01
#define EFI_SECTION_GUID_DEFINED 0x02
#define EFI_SECTION_DISPOSABLE 0x03
///
/// Leaf section Type values.
///
#define EFI_SECTION_PE32 0x10
#define EFI_SECTION_PIC 0x11
#define EFI_SECTION_TE 0x12
#define EFI_SECTION_DXE_DEPEX 0x13
#define EFI_SECTION_VERSION 0x14
#define EFI_SECTION_USER_INTERFACE 0x15
#define EFI_SECTION_COMPATIBILITY16 0x16
#define EFI_SECTION_FIRMWARE_VOLUME_IMAGE 0x17
#define EFI_SECTION_FREEFORM_SUBTYPE_GUID 0x18
#define EFI_SECTION_RAW 0x19
#define EFI_SECTION_PEI_DEPEX 0x1B
#define EFI_SECTION_SMM_DEPEX 0x1C
///
/// Common section header.
///
typedef struct {
///
/// A 24-bit unsigned integer that contains the total size of the section in bytes,
/// including the EFI_COMMON_SECTION_HEADER.
///
UINT8 Size[3];
EFI_SECTION_TYPE Type;
///
/// Declares the section type.
///
} EFI_COMMON_SECTION_HEADER;
typedef struct {
///
/// A 24-bit unsigned integer that contains the total size of the section in bytes,
/// including the EFI_COMMON_SECTION_HEADER.
///
UINT8 Size[3];
EFI_SECTION_TYPE Type;
///
/// If Size is 0xFFFFFF, then ExtendedSize contains the size of the section. If
/// Size is not equal to 0xFFFFFF, then this field does not exist.
///
UINT32 ExtendedSize;
} EFI_COMMON_SECTION_HEADER2;
///
/// Leaf section type that contains an
/// IA-32 16-bit executable image.
///
typedef EFI_COMMON_SECTION_HEADER EFI_COMPATIBILITY16_SECTION;
typedef EFI_COMMON_SECTION_HEADER2 EFI_COMPATIBILITY16_SECTION2;
///
/// CompressionType of EFI_COMPRESSION_SECTION.
///
#define EFI_NOT_COMPRESSED 0x00
#define EFI_STANDARD_COMPRESSION 0x01
///
/// An encapsulation section type in which the
/// section data is compressed.
///
typedef struct {
///
/// Usual common section header. CommonHeader.Type = EFI_SECTION_COMPRESSION.
///
EFI_COMMON_SECTION_HEADER CommonHeader;
///
/// The UINT32 that indicates the size of the section data after decompression.
///
UINT32 UncompressedLength;
///
/// Indicates which compression algorithm is used.
///
UINT8 CompressionType;
} EFI_COMPRESSION_SECTION;
typedef struct {
///
/// Usual common section header. CommonHeader.Type = EFI_SECTION_COMPRESSION.
///
EFI_COMMON_SECTION_HEADER2 CommonHeader;
///
/// UINT32 that indicates the size of the section data after decompression.
///
UINT32 UncompressedLength;
///
/// Indicates which compression algorithm is used.
///
UINT8 CompressionType;
} EFI_COMPRESSION_SECTION2;
///
/// An encapsulation section type in which the section data is disposable.
/// A disposable section is an encapsulation section in which the section data may be disposed of during
/// the process of creating or updating a firmware image without significant impact on the usefulness of
/// the file. The Type field in the section header is set to EFI_SECTION_DISPOSABLE. This
/// allows optional or descriptive data to be included with the firmware file which can be removed in
/// order to conserve space. The contents of this section are implementation specific, but might contain
/// debug data or detailed integration instructions.
///
typedef EFI_COMMON_SECTION_HEADER EFI_DISPOSABLE_SECTION;
typedef EFI_COMMON_SECTION_HEADER2 EFI_DISPOSABLE_SECTION2;
///
/// The leaf section which could be used to determine the dispatch order of DXEs.
///
typedef EFI_COMMON_SECTION_HEADER EFI_DXE_DEPEX_SECTION;
typedef EFI_COMMON_SECTION_HEADER2 EFI_DXE_DEPEX_SECTION2;
///
/// The leaf section which contains a PI FV.
///
typedef EFI_COMMON_SECTION_HEADER EFI_FIRMWARE_VOLUME_IMAGE_SECTION;
typedef EFI_COMMON_SECTION_HEADER2 EFI_FIRMWARE_VOLUME_IMAGE_SECTION2;
///
/// The leaf section which contains a single GUID.
///
typedef struct {
///
/// Common section header. CommonHeader.Type = EFI_SECTION_FREEFORM_SUBTYPE_GUID.
///
EFI_COMMON_SECTION_HEADER CommonHeader;
///
/// This GUID is defined by the creator of the file. It is a vendor-defined file type.
///
EFI_GUID SubTypeGuid;
} EFI_FREEFORM_SUBTYPE_GUID_SECTION;
typedef struct {
///
/// The common section header. CommonHeader.Type = EFI_SECTION_FREEFORM_SUBTYPE_GUID.
///
EFI_COMMON_SECTION_HEADER2 CommonHeader;
///
/// This GUID is defined by the creator of the file. It is a vendor-defined file type.
///
EFI_GUID SubTypeGuid;
} EFI_FREEFORM_SUBTYPE_GUID_SECTION2;
///
/// Attributes of EFI_GUID_DEFINED_SECTION.
///
#define EFI_GUIDED_SECTION_PROCESSING_REQUIRED 0x01
#define EFI_GUIDED_SECTION_AUTH_STATUS_VALID 0x02
///
/// The leaf section which is encapsulation defined by specific GUID.
///
typedef struct {
///
/// The common section header. CommonHeader.Type = EFI_SECTION_GUID_DEFINED.
///
EFI_COMMON_SECTION_HEADER CommonHeader;
///
/// The GUID that defines the format of the data that follows. It is a vendor-defined section type.
///
EFI_GUID SectionDefinitionGuid;
///
/// Contains the offset in bytes from the beginning of the common header to the first byte of the data.
///
UINT16 DataOffset;
///
/// The bit field that declares some specific characteristics of the section contents.
///
UINT16 Attributes;
} EFI_GUID_DEFINED_SECTION;
typedef struct {
///
/// The common section header. CommonHeader.Type = EFI_SECTION_GUID_DEFINED.
///
EFI_COMMON_SECTION_HEADER2 CommonHeader;
///
/// The GUID that defines the format of the data that follows. It is a vendor-defined section type.
///
EFI_GUID SectionDefinitionGuid;
///
/// Contains the offset in bytes from the beginning of the common header to the first byte of the data.
///
UINT16 DataOffset;
///
/// The bit field that declares some specific characteristics of the section contents.
///
UINT16 Attributes;
} EFI_GUID_DEFINED_SECTION2;
///
/// The leaf section which contains PE32+ image.
///
typedef EFI_COMMON_SECTION_HEADER EFI_PE32_SECTION;
typedef EFI_COMMON_SECTION_HEADER2 EFI_PE32_SECTION2;
///
/// The leaf section used to determine the dispatch order of PEIMs.
///
typedef EFI_COMMON_SECTION_HEADER EFI_PEI_DEPEX_SECTION;
typedef EFI_COMMON_SECTION_HEADER2 EFI_PEI_DEPEX_SECTION2;
///
/// A leaf section type that contains a position-independent-code (PIC) image.
/// A PIC image section is a leaf section that contains a position-independent-code (PIC) image.
/// In addition to normal PE32+ images that contain relocation information, PEIM executables may be
/// PIC and are referred to as PIC images. A PIC image is the same as a PE32+ image except that all
/// relocation information has been stripped from the image and the image can be moved and will
/// execute correctly without performing any relocation or other fix-ups. EFI_PIC_SECTION2 must
/// be used if the section is 16MB or larger.
///
typedef EFI_COMMON_SECTION_HEADER EFI_PIC_SECTION;
typedef EFI_COMMON_SECTION_HEADER2 EFI_PIC_SECTION2;
///
/// The leaf section which constains the position-independent-code image.
///
typedef EFI_COMMON_SECTION_HEADER EFI_TE_SECTION;
typedef EFI_COMMON_SECTION_HEADER2 EFI_TE_SECTION2;
///
/// The leaf section which contains an array of zero or more bytes.
///
typedef EFI_COMMON_SECTION_HEADER EFI_RAW_SECTION;
typedef EFI_COMMON_SECTION_HEADER2 EFI_RAW_SECTION2;
///
/// The SMM dependency expression section is a leaf section that contains a dependency expression that
/// is used to determine the dispatch order for SMM drivers. Before the SMRAM invocation of the
/// SMM driver's entry point, this dependency expression must evaluate to TRUE. See the Platform
/// Initialization Specification, Volume 2, for details regarding the format of the dependency expression.
/// The dependency expression may refer to protocols installed in either the UEFI or the SMM protocol
/// database. EFI_SMM_DEPEX_SECTION2 must be used if the section is 16MB or larger.
///
typedef EFI_COMMON_SECTION_HEADER EFI_SMM_DEPEX_SECTION;
typedef EFI_COMMON_SECTION_HEADER2 EFI_SMM_DEPEX_SECTION2;
///
/// The leaf section which contains a unicode string that
/// is human readable file name.
///
typedef struct {
EFI_COMMON_SECTION_HEADER CommonHeader;
///
/// Array of unicode string.
///
CHAR16 FileNameString[1];
} EFI_USER_INTERFACE_SECTION;
typedef struct {
EFI_COMMON_SECTION_HEADER2 CommonHeader;
CHAR16 FileNameString[1];
} EFI_USER_INTERFACE_SECTION2;
///
/// The leaf section which contains a numeric build number and
/// an optional unicode string that represents the file revision.
///
typedef struct {
EFI_COMMON_SECTION_HEADER CommonHeader;
UINT16 BuildNumber;
///
/// Array of unicode string.
///
CHAR16 VersionString[1];
} EFI_VERSION_SECTION;
typedef struct {
EFI_COMMON_SECTION_HEADER2 CommonHeader;
///
/// A UINT16 that represents a particular build. Subsequent builds have monotonically
/// increasing build numbers relative to earlier builds.
///
UINT16 BuildNumber;
CHAR16 VersionString[1];
} EFI_VERSION_SECTION2;
#define IS_SECTION2(SectionHeaderPtr) \
((UINT32) (*((UINT32 *) ((EFI_COMMON_SECTION_HEADER *) (UINTN) SectionHeaderPtr)->Size) & 0x00ffffff) == 0x00ffffff)
#define SECTION_SIZE(SectionHeaderPtr) \
((UINT32) (*((UINT32 *) ((EFI_COMMON_SECTION_HEADER *) (UINTN) SectionHeaderPtr)->Size) & 0x00ffffff))
#define SECTION2_SIZE(SectionHeaderPtr) \
(((EFI_COMMON_SECTION_HEADER2 *) (UINTN) SectionHeaderPtr)->ExtendedSize)
#pragma pack()
#endif

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/** @file
Copyright (C) 2013, Intel Corporation
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
**/
#ifndef __PI_FIRMWAREVOLUME_H__
#define __PI_FIRMWAREVOLUME_H__
///
/// EFI_FV_FILE_ATTRIBUTES
///
typedef UINT32 EFI_FV_FILE_ATTRIBUTES;
//
// Value of EFI_FV_FILE_ATTRIBUTES.
//
#define EFI_FV_FILE_ATTRIB_ALIGNMENT 0x0000001F
#define EFI_FV_FILE_ATTRIB_FIXED 0x00000100
#define EFI_FV_FILE_ATTRIB_MEMORY_MAPPED 0x00000200
///
/// type of EFI FVB attribute
///
typedef UINT32 EFI_FVB_ATTRIBUTES_2;
//
// Attributes bit definitions
//
#define EFI_FVB2_READ_DISABLED_CAP 0x00000001
#define EFI_FVB2_READ_ENABLED_CAP 0x00000002
#define EFI_FVB2_READ_STATUS 0x00000004
#define EFI_FVB2_WRITE_DISABLED_CAP 0x00000008
#define EFI_FVB2_WRITE_ENABLED_CAP 0x00000010
#define EFI_FVB2_WRITE_STATUS 0x00000020
#define EFI_FVB2_LOCK_CAP 0x00000040
#define EFI_FVB2_LOCK_STATUS 0x00000080
#define EFI_FVB2_STICKY_WRITE 0x00000200
#define EFI_FVB2_MEMORY_MAPPED 0x00000400
#define EFI_FVB2_ERASE_POLARITY 0x00000800
#define EFI_FVB2_READ_LOCK_CAP 0x00001000
#define EFI_FVB2_READ_LOCK_STATUS 0x00002000
#define EFI_FVB2_WRITE_LOCK_CAP 0x00004000
#define EFI_FVB2_WRITE_LOCK_STATUS 0x00008000
#define EFI_FVB2_ALIGNMENT 0x001F0000
#define EFI_FVB2_ALIGNMENT_1 0x00000000
#define EFI_FVB2_ALIGNMENT_2 0x00010000
#define EFI_FVB2_ALIGNMENT_4 0x00020000
#define EFI_FVB2_ALIGNMENT_8 0x00030000
#define EFI_FVB2_ALIGNMENT_16 0x00040000
#define EFI_FVB2_ALIGNMENT_32 0x00050000
#define EFI_FVB2_ALIGNMENT_64 0x00060000
#define EFI_FVB2_ALIGNMENT_128 0x00070000
#define EFI_FVB2_ALIGNMENT_256 0x00080000
#define EFI_FVB2_ALIGNMENT_512 0x00090000
#define EFI_FVB2_ALIGNMENT_1K 0x000A0000
#define EFI_FVB2_ALIGNMENT_2K 0x000B0000
#define EFI_FVB2_ALIGNMENT_4K 0x000C0000
#define EFI_FVB2_ALIGNMENT_8K 0x000D0000
#define EFI_FVB2_ALIGNMENT_16K 0x000E0000
#define EFI_FVB2_ALIGNMENT_32K 0x000F0000
#define EFI_FVB2_ALIGNMENT_64K 0x00100000
#define EFI_FVB2_ALIGNMENT_128K 0x00110000
#define EFI_FVB2_ALIGNMENT_256K 0x00120000
#define EFI_FVB2_ALIGNMENT_512K 0x00130000
#define EFI_FVB2_ALIGNMENT_1M 0x00140000
#define EFI_FVB2_ALIGNMENT_2M 0x00150000
#define EFI_FVB2_ALIGNMENT_4M 0x00160000
#define EFI_FVB2_ALIGNMENT_8M 0x00170000
#define EFI_FVB2_ALIGNMENT_16M 0x00180000
#define EFI_FVB2_ALIGNMENT_32M 0x00190000
#define EFI_FVB2_ALIGNMENT_64M 0x001A0000
#define EFI_FVB2_ALIGNMENT_128M 0x001B0000
#define EFI_FVB2_ALIGNMENT_256M 0x001C0000
#define EFI_FVB2_ALIGNMENT_512M 0x001D0000
#define EFI_FVB2_ALIGNMENT_1G 0x001E0000
#define EFI_FVB2_ALIGNMENT_2G 0x001F0000
typedef struct {
///
/// The number of sequential blocks which are of the same size.
///
UINT32 NumBlocks;
///
/// The size of the blocks.
///
UINT32 Length;
} EFI_FV_BLOCK_MAP_ENTRY;
///
/// Describes the features and layout of the firmware volume.
///
typedef struct {
///
/// The first 16 bytes are reserved to allow for the reset vector of
/// processors whose reset vector is at address 0.
///
UINT8 ZeroVector[16];
///
/// Declares the file system with which the firmware volume is formatted.
///
EFI_GUID FileSystemGuid;
///
/// Length in bytes of the complete firmware volume, including the header.
///
UINT64 FvLength;
///
/// Set to EFI_FVH_SIGNATURE
///
UINT32 Signature;
///
/// Declares capabilities and power-on defaults for the firmware volume.
///
EFI_FVB_ATTRIBUTES_2 Attributes;
///
/// Length in bytes of the complete firmware volume header.
///
UINT16 HeaderLength;
///
/// A 16-bit checksum of the firmware volume header. A valid header sums to zero.
///
UINT16 Checksum;
///
/// Offset, relative to the start of the header, of the extended header
/// (EFI_FIRMWARE_VOLUME_EXT_HEADER) or zero if there is no extended header.
///
UINT16 ExtHeaderOffset;
///
/// This field must always be set to zero.
///
UINT8 Reserved[1];
///
/// Set to 2. Future versions of this specification may define new header fields and will
/// increment the Revision field accordingly.
///
UINT8 Revision;
///
/// An array of run-length encoded FvBlockMapEntry structures. The array is
/// terminated with an entry of {0,0}.
///
EFI_FV_BLOCK_MAP_ENTRY BlockMap[1];
} EFI_FIRMWARE_VOLUME_HEADER;
#define EFI_FVH_SIGNATURE SIGNATURE_32 ('_', 'F', 'V', 'H')
///
/// Firmware Volume Header Revision definition
///
#define EFI_FVH_REVISION 0x02
///
/// Extension header pointed by ExtHeaderOffset of volume header.
///
typedef struct {
///
/// Firmware volume name.
///
EFI_GUID FvName;
///
/// Size of the rest of the extension header, including this structure.
///
UINT32 ExtHeaderSize;
} EFI_FIRMWARE_VOLUME_EXT_HEADER;
///
/// Entry struture for describing FV extension header
///
typedef struct {
///
/// Size of this header extension.
///
UINT16 ExtEntrySize;
///
/// Type of the header.
///
UINT16 ExtEntryType;
} EFI_FIRMWARE_VOLUME_EXT_ENTRY;
#define EFI_FV_EXT_TYPE_OEM_TYPE 0x01
///
/// This extension header provides a mapping between a GUID and an OEM file type.
///
typedef struct {
///
/// Standard extension entry, with the type EFI_FV_EXT_TYPE_OEM_TYPE.
///
EFI_FIRMWARE_VOLUME_EXT_ENTRY Hdr;
///
/// A bit mask, one bit for each file type between 0xC0 (bit 0) and 0xDF (bit 31). If a bit
/// is '1', then the GUID entry exists in Types. If a bit is '0' then no GUID entry exists in Types.
///
UINT32 TypeMask;
///
/// An array of GUIDs, each GUID representing an OEM file type.
///
/// EFI_GUID Types[1];
///
} EFI_FIRMWARE_VOLUME_EXT_ENTRY_OEM_TYPE;
#define EFI_FV_EXT_TYPE_GUID_TYPE 0x0002
///
/// This extension header EFI_FIRMWARE_VOLUME_EXT_ENTRY_GUID_TYPE provides a vendor specific
/// GUID FormatType type which includes a length and a successive series of data bytes.
///
typedef struct {
///
/// Standard extension entry, with the type EFI_FV_EXT_TYPE_OEM_TYPE.
///
EFI_FIRMWARE_VOLUME_EXT_ENTRY Hdr;
///
/// Vendor-specific GUID.
///
EFI_GUID FormatType;
///
/// An arry of bytes of length Length.
///
/// UINT8 Data[1];
///
} EFI_FIRMWARE_VOLUME_EXT_ENTRY_GUID_TYPE;
#endif

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/** @file
Copyright (C) 2013, Intel Corporation
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
**/
#ifndef __PI_HOB_H__
#define __PI_HOB_H__
//
// HobType of EFI_HOB_GENERIC_HEADER.
//
#define EFI_HOB_TYPE_MEMORY_ALLOCATION 0x0002
#define EFI_HOB_TYPE_RESOURCE_DESCRIPTOR 0x0003
#define EFI_HOB_TYPE_GUID_EXTENSION 0x0004
#define EFI_HOB_TYPE_UNUSED 0xFFFE
#define EFI_HOB_TYPE_END_OF_HOB_LIST 0xFFFF
///
/// Describes the format and size of the data inside the HOB.
/// All HOBs must contain this generic HOB header.
///
typedef struct {
///
/// Identifies the HOB data structure type.
///
UINT16 HobType;
///
/// The length in bytes of the HOB.
///
UINT16 HobLength;
///
/// This field must always be set to zero.
///
UINT32 Reserved;
} EFI_HOB_GENERIC_HEADER;
///
/// Enumeration of memory types introduced in UEFI.
///
typedef enum {
///
/// Not used.
///
EfiReservedMemoryType,
///
/// The code portions of a loaded application.
/// (Note that UEFI OS loaders are UEFI applications.)
///
EfiLoaderCode,
///
/// The data portions of a loaded application and the default data allocation
/// type used by an application to allocate pool memory.
///
EfiLoaderData,
///
/// The code portions of a loaded Boot Services Driver.
///
EfiBootServicesCode,
///
/// The data portions of a loaded Boot Serves Driver, and the default data
/// allocation type used by a Boot Services Driver to allocate pool memory.
///
EfiBootServicesData,
///
/// The code portions of a loaded Runtime Services Driver.
///
EfiRuntimeServicesCode,
///
/// The data portions of a loaded Runtime Services Driver and the default
/// data allocation type used by a Runtime Services Driver to allocate pool memory.
///
EfiRuntimeServicesData,
///
/// Free (unallocated) memory.
///
EfiConventionalMemory,
///
/// Memory in which errors have been detected.
///
EfiUnusableMemory,
///
/// Memory that holds the ACPI tables.
///
EfiACPIReclaimMemory,
///
/// Address space reserved for use by the firmware.
///
EfiACPIMemoryNVS,
///
/// Used by system firmware to request that a memory-mapped IO region
/// be mapped by the OS to a virtual address so it can be accessed by EFI runtime services.
///
EfiMemoryMappedIO,
///
/// System memory-mapped IO region that is used to translate memory
/// cycles to IO cycles by the processor.
///
EfiMemoryMappedIOPortSpace,
///
/// Address space reserved by the firmware for code that is part of the processor.
///
EfiPalCode,
EfiMaxMemoryType
} EFI_MEMORY_TYPE;
///
/// EFI_HOB_MEMORY_ALLOCATION_HEADER describes the
/// various attributes of the logical memory allocation. The type field will be used for
/// subsequent inclusion in the UEFI memory map.
///
typedef struct {
///
/// A GUID that defines the memory allocation region's type and purpose, as well as
/// other fields within the memory allocation HOB. This GUID is used to define the
/// additional data within the HOB that may be present for the memory allocation HOB.
/// Type EFI_GUID is defined in InstallProtocolInterface() in the UEFI 2.0
/// specification.
///
EFI_GUID Name;
///
/// The base address of memory allocated by this HOB. Type
/// EFI_PHYSICAL_ADDRESS is defined in AllocatePages() in the UEFI 2.0
/// specification.
///
EFI_PHYSICAL_ADDRESS MemoryBaseAddress;
///
/// The length in bytes of memory allocated by this HOB.
///
UINT64 MemoryLength;
///
/// Defines the type of memory allocated by this HOB. The memory type definition
/// follows the EFI_MEMORY_TYPE definition. Type EFI_MEMORY_TYPE is defined
/// in AllocatePages() in the UEFI 2.0 specification.
///
EFI_MEMORY_TYPE MemoryType;
///
/// Padding for Itanium processor family
///
UINT8 Reserved[4];
} EFI_HOB_MEMORY_ALLOCATION_HEADER;
///
/// Describes all memory ranges used during the HOB producer
/// phase that exist outside the HOB list. This HOB type
/// describes how memory is used, not the physical attributes of memory.
///
typedef struct {
///
/// The HOB generic header. Header.HobType = EFI_HOB_TYPE_MEMORY_ALLOCATION.
///
EFI_HOB_GENERIC_HEADER Header;
///
/// An instance of the EFI_HOB_MEMORY_ALLOCATION_HEADER that describes the
/// various attributes of the logical memory allocation.
///
EFI_HOB_MEMORY_ALLOCATION_HEADER AllocDescriptor;
//
// Additional data pertaining to the "Name" Guid memory
// may go here.
//
} EFI_HOB_MEMORY_ALLOCATION;
///
/// The resource type.
///
typedef UINT32 EFI_RESOURCE_TYPE;
//
// Value of ResourceType in EFI_HOB_RESOURCE_DESCRIPTOR.
//
#define EFI_RESOURCE_SYSTEM_MEMORY 0x00000000
#define EFI_RESOURCE_MEMORY_MAPPED_IO 0x00000001
#define EFI_RESOURCE_IO 0x00000002
#define EFI_RESOURCE_FIRMWARE_DEVICE 0x00000003
#define EFI_RESOURCE_MEMORY_MAPPED_IO_PORT 0x00000004
#define EFI_RESOURCE_MEMORY_RESERVED 0x00000005
#define EFI_RESOURCE_IO_RESERVED 0x00000006
#define EFI_RESOURCE_MAX_MEMORY_TYPE 0x00000007
///
/// A type of recount attribute type.
///
typedef UINT32 EFI_RESOURCE_ATTRIBUTE_TYPE;
//
// These types can be ORed together as needed.
//
// The first three enumerations describe settings
//
#define EFI_RESOURCE_ATTRIBUTE_PRESENT 0x00000001
#define EFI_RESOURCE_ATTRIBUTE_INITIALIZED 0x00000002
#define EFI_RESOURCE_ATTRIBUTE_TESTED 0x00000004
//
// The rest of the settings describe capabilities
//
#define EFI_RESOURCE_ATTRIBUTE_SINGLE_BIT_ECC 0x00000008
#define EFI_RESOURCE_ATTRIBUTE_MULTIPLE_BIT_ECC 0x00000010
#define EFI_RESOURCE_ATTRIBUTE_ECC_RESERVED_1 0x00000020
#define EFI_RESOURCE_ATTRIBUTE_ECC_RESERVED_2 0x00000040
#define EFI_RESOURCE_ATTRIBUTE_READ_PROTECTED 0x00000080
#define EFI_RESOURCE_ATTRIBUTE_WRITE_PROTECTED 0x00000100
#define EFI_RESOURCE_ATTRIBUTE_EXECUTION_PROTECTED 0x00000200
#define EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE 0x00000400
#define EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE 0x00000800
#define EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE 0x00001000
#define EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE 0x00002000
#define EFI_RESOURCE_ATTRIBUTE_16_BIT_IO 0x00004000
#define EFI_RESOURCE_ATTRIBUTE_32_BIT_IO 0x00008000
#define EFI_RESOURCE_ATTRIBUTE_64_BIT_IO 0x00010000
#define EFI_RESOURCE_ATTRIBUTE_UNCACHED_EXPORTED 0x00020000
///
/// Describes the resource properties of all fixed,
/// nonrelocatable resource ranges found on the processor
/// host bus during the HOB producer phase.
///
typedef struct {
///
/// The HOB generic header. Header.HobType = EFI_HOB_TYPE_RESOURCE_DESCRIPTOR.
///
EFI_HOB_GENERIC_HEADER Header;
///
/// A GUID representing the owner of the resource. This GUID is used by HOB
/// consumer phase components to correlate device ownership of a resource.
///
EFI_GUID Owner;
///
/// The resource type enumeration as defined by EFI_RESOURCE_TYPE.
///
EFI_RESOURCE_TYPE ResourceType;
///
/// Resource attributes as defined by EFI_RESOURCE_ATTRIBUTE_TYPE.
///
EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttribute;
///
/// The physical start address of the resource region.
///
EFI_PHYSICAL_ADDRESS PhysicalStart;
///
/// The number of bytes of the resource region.
///
UINT64 ResourceLength;
} EFI_HOB_RESOURCE_DESCRIPTOR;
///
/// Allows writers of executable content in the HOB producer phase to
/// maintain and manage HOBs with specific GUID.
///
typedef struct {
///
/// The HOB generic header. Header.HobType = EFI_HOB_TYPE_GUID_EXTENSION.
///
EFI_HOB_GENERIC_HEADER Header;
///
/// A GUID that defines the contents of this HOB.
///
EFI_GUID Name;
//
// Guid specific data goes here
//
} EFI_HOB_GUID_TYPE;
///
/// Union of all the possible HOB Types.
///
typedef union {
EFI_HOB_GENERIC_HEADER *Header;
EFI_HOB_MEMORY_ALLOCATION *MemoryAllocation;
EFI_HOB_RESOURCE_DESCRIPTOR *ResourceDescriptor;
EFI_HOB_GUID_TYPE *Guid;
UINT8 *Raw;
} EFI_PEI_HOB_POINTERS;
/**
Returns the type of a HOB.
This macro returns the HobType field from the HOB header for the
HOB specified by HobStart.
@param HobStart A pointer to a HOB.
@return HobType.
**/
#define GET_HOB_TYPE(HobStart) \
((*(EFI_HOB_GENERIC_HEADER **)&(HobStart))->HobType)
/**
Returns the length, in bytes, of a HOB.
This macro returns the HobLength field from the HOB header for the
HOB specified by HobStart.
@param HobStart A pointer to a HOB.
@return HobLength.
**/
#define GET_HOB_LENGTH(HobStart) \
((*(EFI_HOB_GENERIC_HEADER **)&(HobStart))->HobLength)
/**
Returns a pointer to the next HOB in the HOB list.
This macro returns a pointer to HOB that follows the
HOB specified by HobStart in the HOB List.
@param HobStart A pointer to a HOB.
@return A pointer to the next HOB in the HOB list.
**/
#define GET_NEXT_HOB(HobStart) \
(VOID *)(*(UINT8 **)&(HobStart) + GET_HOB_LENGTH (HobStart))
/**
Determines if a HOB is the last HOB in the HOB list.
This macro determine if the HOB specified by HobStart is the
last HOB in the HOB list. If HobStart is last HOB in the HOB list,
then TRUE is returned. Otherwise, FALSE is returned.
@param HobStart A pointer to a HOB.
@retval TRUE The HOB specified by HobStart is the last HOB in the HOB list.
@retval FALSE The HOB specified by HobStart is not the last HOB in the HOB list.
**/
#define END_OF_HOB_LIST(HobStart) (GET_HOB_TYPE (HobStart) == (UINT16)EFI_HOB_TYPE_END_OF_HOB_LIST)
/**
Returns a pointer to data buffer from a HOB of type EFI_HOB_TYPE_GUID_EXTENSION.
This macro returns a pointer to the data buffer in a HOB specified by HobStart.
HobStart is assumed to be a HOB of type EFI_HOB_TYPE_GUID_EXTENSION.
@param GuidHob A pointer to a HOB.
@return A pointer to the data buffer in a HOB.
**/
#define GET_GUID_HOB_DATA(HobStart) \
(VOID *)(*(UINT8 **)&(HobStart) + sizeof (EFI_HOB_GUID_TYPE))
/**
Returns the size of the data buffer from a HOB of type EFI_HOB_TYPE_GUID_EXTENSION.
This macro returns the size, in bytes, of the data buffer in a HOB specified by HobStart.
HobStart is assumed to be a HOB of type EFI_HOB_TYPE_GUID_EXTENSION.
@param GuidHob A pointer to a HOB.
@return The size of the data buffer.
**/
#define GET_GUID_HOB_DATA_SIZE(HobStart) \
(UINT16)(GET_HOB_LENGTH (HobStart) - sizeof (EFI_HOB_GUID_TYPE))
/**
Returns the pointer to the HOB list.
This function returns the pointer to first HOB in the list.
If the pointer to the HOB list is NULL, then ASSERT().
@return The pointer to the HOB list.
**/
VOID *
EFIAPI
GetHobList (
VOID
);
/**
Returns the next instance of a HOB type from the starting HOB.
This function searches the first instance of a HOB type from the starting HOB pointer.
If there does not exist such HOB type from the starting HOB pointer, it will return NULL.
In contrast with macro GET_NEXT_HOB(), this function does not skip the starting HOB pointer
unconditionally: it returns HobStart back if HobStart itself meets the requirement;
caller is required to use GET_NEXT_HOB() if it wishes to skip current HobStart.
If HobStart is NULL, then ASSERT().
@param Type The HOB type to return.
@param HobStart The starting HOB pointer to search from.
@return The next instance of a HOB type from the starting HOB.
**/
VOID *
EFIAPI
GetNextHob (
UINT16 Type,
CONST VOID *HobStart
);
/**
Returns the first instance of a HOB type among the whole HOB list.
This function searches the first instance of a HOB type among the whole HOB list.
If there does not exist such HOB type in the HOB list, it will return NULL.
If the pointer to the HOB list is NULL, then ASSERT().
@param Type The HOB type to return.
@return The next instance of a HOB type from the starting HOB.
**/
VOID *
EFIAPI
GetFirstHob (
UINT16 Type
);
/**
Returns the next instance of the matched GUID HOB from the starting HOB.
This function searches the first instance of a HOB from the starting HOB pointer.
Such HOB should satisfy two conditions:
its HOB type is EFI_HOB_TYPE_GUID_EXTENSION and its GUID Name equals to the input Guid.
If there does not exist such HOB from the starting HOB pointer, it will return NULL.
Caller is required to apply GET_GUID_HOB_DATA () and GET_GUID_HOB_DATA_SIZE ()
to extract the data section and its size info respectively.
In contrast with macro GET_NEXT_HOB(), this function does not skip the starting HOB pointer
unconditionally: it returns HobStart back if HobStart itself meets the requirement;
caller is required to use GET_NEXT_HOB() if it wishes to skip current HobStart.
If Guid is NULL, then ASSERT().
If HobStart is NULL, then ASSERT().
@param Guid The GUID to match with in the HOB list.
@param HobStart A pointer to a Guid.
@return The next instance of the matched GUID HOB from the starting HOB.
**/
VOID *
EFIAPI
GetNextGuidHob (
CONST EFI_GUID *Guid,
CONST VOID *HobStart
);
/**
Returns the first instance of the matched GUID HOB among the whole HOB list.
This function searches the first instance of a HOB among the whole HOB list.
Such HOB should satisfy two conditions:
its HOB type is EFI_HOB_TYPE_GUID_EXTENSION and its GUID Name equals to the input Guid.
If there does not exist such HOB from the starting HOB pointer, it will return NULL.
Caller is required to apply GET_GUID_HOB_DATA () and GET_GUID_HOB_DATA_SIZE ()
to extract the data section and its size info respectively.
If the pointer to the HOB list is NULL, then ASSERT().
If Guid is NULL, then ASSERT().
@param Guid The GUID to match with in the HOB list.
@return The first instance of the matched GUID HOB among the whole HOB list.
**/
VOID *
EFIAPI
GetFirstGuidHob (
CONST EFI_GUID *Guid
);
BOOLEAN
EFIAPI
CompareGuid (
CONST EFI_GUID *Guid1,
CONST EFI_GUID *Guid2
);
#endif

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/** @file
Copyright (C) 2013, Intel Corporation
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
**/
#ifndef _FSP_INFO_HEADER_H_
#define _FSP_INFO_HEADER_H_
#pragma pack(1)
typedef struct {
UINT32 Signature; // Off 0x94
UINT32 HeaderLength;
UINT8 Reserved1[3];
UINT8 HeaderRevision;
UINT32 ImageRevision;
CHAR8 ImageId[8]; // Off 0xA4
UINT32 ImageSize;
UINT32 ImageBase;
UINT32 ImageAttribute; // Off 0xB4
UINT32 CfgRegionOffset;
UINT32 CfgRegionSize;
UINT32 ApiEntryNum;
UINT32 NemInitEntry; // Off 0xC4
UINT32 FspInitEntry;
UINT32 NotifyPhaseEntry;
UINT32 Reserved2;
} FSP_INFO_HEADER;
#pragma pack()
#endif

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/** @file
Copyright (C) 2013, Intel Corporation
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
**/
#ifndef _FSP_PLATFORM_H_
#define _FSP_PLATFORM_H_
#include "fsptypes.h"
#include "fspapi.h"
#include "mem_config.h"
#pragma pack(1)
typedef struct {
MEM_CONFIG *MemoryConfig;
} FSP_INIT_RT_PLATFORM_BUFFER;
typedef struct {
uint8_t HTEnable;
uint8_t TurboEnable;
uint8_t MemoryDownEnable;
uint8_t FastBootEnable;
} PLATFORM_CONFIG;
typedef struct {
const PLATFORM_CONFIG *PlatformConfig;
} FSP_INIT_RT_CONFIG_BUFFER;
typedef struct {
FSP_INIT_RT_COMMON_BUFFER Common;
FSP_INIT_RT_CONFIG_BUFFER PlatformConfiguration;
FSP_INIT_RT_PLATFORM_BUFFER Platform;
} FSP_INIT_RT_BUFFER;
#pragma pack()
#endif

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/** @file
Copyright (C) 2013, Intel Corporation
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
**/
/** \file fsptypes.h
*
*
*/
#ifndef __FSP_TYPES_H__
#define __FSP_TYPES_H__
///
/// 8-byte unsigned value.
///
typedef unsigned long long UINT64;
///
/// 8-byte signed value.
///
typedef long long INT64;
///
/// 4-byte unsigned value.
///
typedef unsigned int UINT32;
///
/// 4-byte signed value.
///
typedef int INT32;
///
/// 2-byte unsigned value.
///
typedef unsigned short UINT16;
///
/// 2-byte Character. Unless otherwise specified all strings are stored in the
/// UTF-16 encoding format as defined by Unicode 2.1 and ISO/IEC 10646 standards.
///
typedef unsigned short CHAR16;
///
/// 2-byte signed value.
///
typedef short INT16;
///
/// Logical Boolean. 1-byte value containing 0 for FALSE or a 1 for TRUE. Other
/// values are undefined.
///
typedef unsigned char BOOLEAN;
///
/// 1-byte unsigned value.
///
typedef unsigned char UINT8;
///
/// 1-byte Character
///
typedef char CHAR8;
///
/// 1-byte signed value
///
typedef char INT8;
typedef void VOID;
typedef UINT64 EFI_PHYSICAL_ADDRESS;
typedef struct {
UINT32 Data1;
UINT16 Data2;
UINT16 Data3;
UINT8 Data4[8];
} EFI_GUID;
#define CONST const
#define STATIC static
#define TRUE ((BOOLEAN)(1==1))
#define FALSE ((BOOLEAN)(0==1))
static inline void DebugDeadLoop(void) {
for (;;);
}
#define FSPAPI __attribute__((cdecl))
#define EFIAPI __attribute__((cdecl))
#define _ASSERT(Expression) DebugDeadLoop()
#define ASSERT(Expression) \
do { \
if (!(Expression)) { \
_ASSERT (Expression); \
} \
} while (FALSE)
typedef UINT32 FSP_STATUS;
typedef UINT32 EFI_STATUS;
#endif

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/** @file
Copyright (C) 2013, Intel Corporation
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
**/
//
// mem_config.h
//
#ifndef _MEM_CONFIG_H_
#define _MEM_CONFIG_H_
typedef enum {
fi1067_IVB=0,
fi1333_IVB,
fi1400_IVB,
fi1600_IVB,
fi1800_IVB,
fi1867_IVB,
fi2000_IVB,
fi2133_IVB,
fi2200_IVB,
fi2400_IVB,
fi2600_IVB,
fi2667_IVB,
fi2800_IVB,
fiUnsupport_IVB,
}TFrequencyIndex_IVB;
#define NUM_IVB_MEM_CLK_FREQUENCIES 13
// DDR3 memory SPD data
//
// NOTE: This only includes the SPD bytes that are relevant to the MRC
typedef struct { // BYTE
uint8_t SPDGeneral; // 0 Number of Serial PD Bytes Written / SPD Device Size / CRC Coverage 1, 2
uint8_t SPDRevision; // 1 SPD Revision
uint8_t DRAMDeviceType; // 2 DRAM Device Type
uint8_t ModuleType; // 3 Module Type
uint8_t SDRAMDensityAndBanks; // 4 SDRAM Density and Banks
uint8_t SDRAMAddressing; // 5 SDRAM Addressing
uint8_t VDD; // 6 Module Nominal Voltage
uint8_t ModuleOrganization; // 7 Module Organization
uint8_t ModuleMemoryBusWidth; // 8 Module Memory Bus Width
uint8_t FineTimebase; // 9 Fine Timebase (FTB) Dividend / Divisor
uint8_t TimebaseDividend; // 10 Medium Timebase (MTB) Dividend
uint8_t TimebaseDivisor; // 11 Medium Timebase (MTB) Divisor
uint8_t SDRAMMinimumCycleTime; // 12 SDRAM Minimum Cycle Time (tCKmin)
uint8_t Reserved0; // 13 Reserved0
uint8_t CASLatenciesLSB; // 14 CAS Latencies Supported, Least Significant Byte
uint8_t CASLatenciesMSB; // 15 CAS Latencies Supported, Most Significant Byte
uint8_t MinimumCASLatencyTime; // 16 Minimum CAS Latency Time (tAAmin)
uint8_t MinimumWriteRecoveryTime; // 17 Minimum Write Recovery Time (tWRmin)
uint8_t MinimumRASToCASDelayTime; // 18 Minimum RAS# to CAS# Delay Time (tRCDmin)
uint8_t MinimumRowToRowDelayTime; // 19 Minimum Row Active to Row Active Delay Time (tRRDmin)
uint8_t MinimumRowPrechargeDelayTime; // 20 Minimum Row Precharge Delay Time (tRPmin)
uint8_t UpperNibblesFortRASAndtRC; // 21 Upper Nibbles for tRAS and tRC
uint8_t tRASmin; // 22 Minimum Active to Precharge Delay Time (tRASmin), Least Significant Byte
uint8_t tRCmin; // 23 Minimum Active to Active/Refresh Delay Time (tRCmin), Least Significant Byte
uint8_t tRFCminLeastSignificantByte; // 24 Minimum Refresh Recovery Delay Time (tRFCmin), Least Significant Byte
uint8_t tRFCminMostSignificantByte; // 25 Minimum Refresh Recovery Delay Time (tRFCmin), Most Significant Byte
uint8_t tWTRmin; // 26 Minimum Internal Write to Read Command Delay Time (tWTRmin)
uint8_t tRTPmin; // 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin)
uint8_t UpperNibbleFortFAW; // 28 Upper Nibble for tFAW
uint8_t tFAWmin; // 29 Minimum Four Activate Window Delay Time (tFAWmin)
uint8_t SDRAMOptionalFeatures; // 30 SDRAM Optional Features
uint8_t SDRAMThermalAndRefreshOptions; // 31 SDRAMThermalAndRefreshOptions
uint8_t ModuleThermalSensor; // 32 ModuleThermalSensor
uint8_t SDRAMDeviceType; // 33 SDRAM Device Type
int8_t tCKminFine; // 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin)
int8_t tAAminFine; // 35 Fine Offset for Minimum CAS Latency Time (tAAmin)
int8_t tRCDminFine; // 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
int8_t tRPminFine; // 37 Fine Offset for Minimum Row Precharge Delay Time (tRPmin)
int8_t tRCminFine; // 38 Fine Offset for Minimum Active to Active/Refresh Delay Time (tRCmin)
uint8_t ReferenceRawCardUsed; // 62 Reference Raw Card Used
uint8_t AddressMappingEdgeConnector; // 63 Address Mapping from Edge Connector to DRAM
uint8_t ThermalHeatSpreaderSolution; // 64 ThermalHeatSpreaderSolution
uint8_t ModuleManufacturerIdCodeLsb; // 117 Module Manufacturer ID Code, Least Significant Byte
uint8_t ModuleManufacturerIdCodeMsb; // 118 Module Manufacturer ID Code, Most Significant Byte
uint8_t ModuleManufacturingLocation; // 119 Module Manufacturing Location
uint8_t ModuleManufacturingDateYear; // 120 Module Manufacturing Date Year
uint8_t ModuleManufacturingDateWW; // 121 Module Manufacturing Date creation work week
uint8_t ModuleSerialNumberA; // 122 Module Serial Number A
uint8_t ModuleSerialNumberB; // 123 Module Serial Number B
uint8_t ModuleSerialNumberC; // 124 Module Serial Number C
uint8_t ModuleSerialNumberD; // 125 Module Serial Number D
uint8_t CRCA; // 126 CRC A
uint8_t CRCB; // 127 CRC B
} DDR3_SPD;
// Configuration for each memory channel/bank
typedef struct {
uint32_t Exists;
DDR3_SPD SpdData;
uint8_t InitClkPiValue[NUM_IVB_MEM_CLK_FREQUENCIES];
} MEM_BANK_CONFIG;
// Memory configuration
typedef struct {
MEM_BANK_CONFIG ChannelABank0;
MEM_BANK_CONFIG ChannelABank1;
MEM_BANK_CONFIG ChannelBBank0;
MEM_BANK_CONFIG ChannelBBank1;
} MEM_CONFIG;
#endif

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/** @file
Copyright (C) 2013, Intel Corporation
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
**/
/** \file peifsp.h
*
*
*/
#include <stdint.h>
#include "fsptypes.h"
#include "fspfv.h"
#include "fspffs.h"
#include "fsphob.h"
#include "fspapi.h"
#include "fspplatform.h"
#include "fspinfoheader.h"

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/**
Copyright (C) 2013, Intel Corporation
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
**/
/***********************************************************************
*
* fsphob.c
*
* HOB infrastructure code.
*
**********************************************************************/
#include <string.h>
#include "fsptypes.h"
#include "fsphob.h"
//
// Pointer to the HOB should be initialized with the output of FSP INIT PARAMS
//
extern volatile void *FspHobListPtr;
//
// Function prototype
//
UINT64
EFIAPI
ReadUnaligned64 (
CONST UINT64 *Buffer
);
/**
Reads a 64-bit value from memory that may be unaligned.
This function returns the 64-bit value pointed to by Buffer. The function
guarantees that the read operation does not produce an alignment fault.
If the Buffer is NULL, then ASSERT().
@param Buffer Pointer to a 64-bit value that may be unaligned.
@return The 64-bit value read from Buffer.
**/
UINT64
EFIAPI
ReadUnaligned64 (
CONST UINT64 *Buffer
)
{
ASSERT (Buffer != NULL);
return *Buffer;
}
/**
Compares two GUIDs.
This function compares Guid1 to Guid2. If the GUIDs are identical then TRUE is returned.
If there are any bit differences in the two GUIDs, then FALSE is returned.
If Guid1 is NULL, then ASSERT().
If Guid2 is NULL, then ASSERT().
@param Guid1 A pointer to a 128 bit GUID.
@param Guid2 A pointer to a 128 bit GUID.
@retval TRUE Guid1 and Guid2 are identical.
@retval FALSE Guid1 and Guid2 are not identical.
**/
BOOLEAN
EFIAPI
CompareGuid (
CONST EFI_GUID *Guid1,
CONST EFI_GUID *Guid2
)
{
UINT64 LowPartOfGuid1;
UINT64 LowPartOfGuid2;
UINT64 HighPartOfGuid1;
UINT64 HighPartOfGuid2;
LowPartOfGuid1 = ReadUnaligned64 ((CONST UINT64*) Guid1);
LowPartOfGuid2 = ReadUnaligned64 ((CONST UINT64*) Guid2);
HighPartOfGuid1 = ReadUnaligned64 ((CONST UINT64*) Guid1 + 1);
HighPartOfGuid2 = ReadUnaligned64 ((CONST UINT64*) Guid2 + 1);
return (BOOLEAN) (LowPartOfGuid1 == LowPartOfGuid2 && HighPartOfGuid1 == HighPartOfGuid2);
}
/**
Returns the pointer to the HOB list.
**/
VOID *
EFIAPI
GetHobList (
VOID
)
{
ASSERT (FspHobListPtr != NULL);
return ((VOID *)FspHobListPtr);
}
/**
Returns the next instance of a HOB type from the starting HOB.
**/
VOID *
EFIAPI
GetNextHob (
UINT16 Type,
CONST VOID *HobStart
)
{
EFI_PEI_HOB_POINTERS Hob;
ASSERT (HobStart != NULL);
Hob.Raw = (UINT8 *) HobStart;
//
// Parse the HOB list until end of list or matching type is found.
//
while (!END_OF_HOB_LIST (Hob)) {
if (Hob.Header->HobType == Type) {
return Hob.Raw;
}
Hob.Raw = GET_NEXT_HOB (Hob);
}
return NULL;
}
/**
Returns the first instance of a HOB type among the whole HOB list.
**/
VOID *
EFIAPI
GetFirstHob (
UINT16 Type
)
{
VOID *HobList;
HobList = GetHobList ();
return GetNextHob (Type, HobList);
}
/**
Returns the next instance of the matched GUID HOB from the starting HOB.
**/
VOID *
EFIAPI
GetNextGuidHob (
CONST EFI_GUID *Guid,
CONST VOID *HobStart
)
{
EFI_PEI_HOB_POINTERS GuidHob;
GuidHob.Raw = (UINT8 *) HobStart;
while ((GuidHob.Raw = GetNextHob (EFI_HOB_TYPE_GUID_EXTENSION, GuidHob.Raw)) != NULL) {
if (CompareGuid (Guid, &GuidHob.Guid->Name)) {
break;
}
GuidHob.Raw = GET_NEXT_HOB (GuidHob);
}
return GuidHob.Raw;
}
/**
Returns the first instance of the matched GUID HOB among the whole HOB list.
**/
VOID *
EFIAPI
GetFirstGuidHob (
CONST EFI_GUID *Guid
)
{
VOID *HobList;
HobList = GetHobList ();
return GetNextGuidHob (Guid, HobList);
}

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================================================================================
Intel® Firmware Support Package (Intel® FSP) for Intel® Xeon® E3-1125C v2,
E3-1105C v2, Intel® Pentium® Processor B925C, and Intel® Core™ i3-3115C
Processors for Communications Infrastructure with Intel® Communications
Chipset 89xx Series Platform Controller Hub Release Notes
Release label: CRYSTALFOREST_IVB_FSP_GOLD_001_20-DECEMBER-2013
December 20th 2013
================================================================================
================================================================================
Copyright (c) 2013, Intel Corporation.
This Intel® Firmware Support Package ("Software") is furnished under license and
may only be used or copied in accordance with the terms of that license.
No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. The Software is subject to change
without notice, and should not be construed as a commitment by Intel Corporation
to market, license, sell or support any product or technology. Unless otherwise
provided for in the license under which this Software is provided, the Software
is provided AS IS, with no warranties of any kind, express or implied.
Except as expressly permitted by the Software license, neither Intel Corporation
nor its suppliers assumes any responsibility or liability for any errors or
inaccuracies that may appear herein. Except as expressly permitted by the
Software license, no part of the Software may be reproduced, stored in a
retrieval system, transmitted in any form, or distributed by any means without
the express written consent of Intel Corporation.
================================================================================
================================================================================
RELEASE NOTES CONTENTS
================================================================================
1. OVERVIEW
2. RELEASE INFORMATION
3. INTEGRATION NOTES
4. CONFIGURATION
5. LIMITATIONS & KNOWN ISSUES
6. CHANGE LOG
================================================================================
1. OVERVIEW
================================================================================
This Gold package contains required binary image(s) and collateral for
Intel® Firmware Support Package (Intel® FSP) for Intel® Xeon® E3-1125C v2,
E3-1105C v2, Intel® Pentium® Processor B925C, and Intel® Core™ i3-3115C
Processors for Communications Infrastructure with Intel® Communications
Chipset 89xx Series Platform Controller Hub.
This Gold package supports Intel® Firmware Support Package Design
Specification v1.0. Please consult the Intel FSP Integration Guide for further
information.
================================================================================
2. RELEASE INFORMATION
================================================================================
This Gold release has been integrated into a coreboot Proof of Concept (POC)
bootloader and verified on the Stargo 2 Customer Reference Board (CRB).
================================================================================
3. INTEGRATION NOTES
================================================================================
Several header and source files are provided in the package to assist with
integrating the FSP with the bootloader.
Please consult the Intel® FSP Integration Guide for further information.
================================================================================
4. CONFIGURATION
================================================================================
A Binary Configuration Tool for Intel® FSP is available as a companion tool and
is intended to be used to:
- Change configuration options based on provided BSF and FSP.
- Rebase the FSP to a different Base Address.
Please refer the Intel(R) Binary Configuration Tool User's Guide for the
usage instructions.
================================================================================
5. LIMITATIONS & KNOWN ISSUES
================================================================================
- None
================================================================================
6. CHANGE LOG
================================================================================
Release CRYSTALFOREST_IVB_FSP_GOLD_001_20-DECEMBER-2013:
- Gold release.
================================================================================

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/** @file
Copyright (C) 2013, Intel Corporation
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
**/
#ifndef __VPDHEADER_H__
#define __VPDHEADER_H__
#pragma pack(1)
typedef struct _UPD_DATA_REGION {
UINT64 Signature; /* Offset 0x0000 */
UINT64 Reserved; /* Offset 0x0008 */
UINT8 HTEnable; /* Offset 0x0010 */
UINT8 TurboEnable; /* Offset 0x0011 */
UINT8 MemoryDownEnable; /* Offset 0x0012 */
UINT8 FastBootEnable; /* Offset 0x0013 */
UINT16 PcdRegionTerminator; /* Offset 0x0310 */
} UPD_DATA_REGION;
#define VPD_IMAGE_SIGN 0x565053462d325453 /* 'ST2-FSPV' */
#define VPD_IMAGE_REV 0x00000001
typedef struct _VPD_DATA_REGION {
UINT64 PcdVpdRegionSign; /* Offset 0x0000 */
UINT32 PcdImageRevision; /* Offset 0x0008 */
UINT32 PcdUpdRegionOffset; /* Offset 0x000C */
UINT8 Padding0[16]; /* Offset 0x0010 */
UINT32 PcdFspReservedMemoryLength; /* Offset 0x0020 */
} VPD_DATA_REGION;
#pragma pack()
#endif

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/**
Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.
This software and associated documentation (if any) is furnished
under a license and may only be used or copied in accordance
with the terms of the license. Except as permitted by such
license, no part of this software or documentation may be
reproduced, stored in a retrieval system, or transmitted in any
form or by any means without the express written consent of
Intel Corporation.
**/
#ifndef _FSP_API_H_
#define _FSP_API_H_
#pragma pack(1)
typedef VOID (* CONTINUATION_PROC)(EFI_STATUS Status, VOID *HobListPtr);
typedef struct {
VOID *NvsBufferPtr;
VOID *RtBufferPtr;
CONTINUATION_PROC ContinuationFunc;
} FSP_INIT_PARAMS;
typedef struct {
UINT32 *StackTop;
UINT32 BootMode; /* Refer to boot mode defined in MdePkg\Include\Pi\PiBootMode.h */
VOID *UpdDataRgnPtr;
UINT32 Reserved[7];
} FSP_INIT_RT_COMMON_BUFFER;
typedef enum {
EnumInitPhaseAfterPciEnumeration = 0x20,
EnumInitPhaseReadyToBoot = 0x40
} FSP_INIT_PHASE;
typedef struct {
FSP_INIT_PHASE Phase;
} NOTIFY_PHASE_PARAMS;
#pragma pack()
typedef FSP_STATUS (FSPAPI *FSP_FSP_INIT) (FSP_INIT_PARAMS *FspInitParamPtr);
typedef FSP_STATUS (FSPAPI *FSP_NOTFY_PHASE) (NOTIFY_PHASE_PARAMS *NotifyPhaseParamPtr);
#endif

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/** @file
Copyright (C) 2013, Intel Corporation
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
**/
#ifndef __PI_FIRMWARE_FILE_H__
#define __PI_FIRMWARE_FILE_H__
#pragma pack(1)
///
/// Used to verify the integrity of the file.
///
typedef union {
struct {
///
/// The IntegrityCheck.Checksum.Header field is an 8-bit checksum of the file
/// header. The State and IntegrityCheck.Checksum.File fields are assumed
/// to be zero and the checksum is calculated such that the entire header sums to zero.
///
UINT8 Header;
///
/// If the FFS_ATTRIB_CHECKSUM (see definition below) bit of the Attributes
/// field is set to one, the IntegrityCheck.Checksum.File field is an 8-bit
/// checksum of the file data.
/// If the FFS_ATTRIB_CHECKSUM bit of the Attributes field is cleared to zero,
/// the IntegrityCheck.Checksum.File field must be initialized with a value of
/// 0xAA. The IntegrityCheck.Checksum.File field is valid any time the
/// EFI_FILE_DATA_VALID bit is set in the State field.
///
UINT8 File;
} Checksum;
///
/// This is the full 16 bits of the IntegrityCheck field.
///
UINT16 Checksum16;
} EFI_FFS_INTEGRITY_CHECK;
///
/// FFS_FIXED_CHECKSUM is the checksum value used when the
/// FFS_ATTRIB_CHECKSUM attribute bit is clear.
///
#define FFS_FIXED_CHECKSUM 0xAA
typedef UINT8 EFI_FV_FILETYPE;
typedef UINT8 EFI_FFS_FILE_ATTRIBUTES;
typedef UINT8 EFI_FFS_FILE_STATE;
///
/// File Types Definitions
///
#define EFI_FV_FILETYPE_ALL 0x00
#define EFI_FV_FILETYPE_RAW 0x01
#define EFI_FV_FILETYPE_FREEFORM 0x02
#define EFI_FV_FILETYPE_SECURITY_CORE 0x03
#define EFI_FV_FILETYPE_PEI_CORE 0x04
#define EFI_FV_FILETYPE_DXE_CORE 0x05
#define EFI_FV_FILETYPE_PEIM 0x06
#define EFI_FV_FILETYPE_DRIVER 0x07
#define EFI_FV_FILETYPE_COMBINED_PEIM_DRIVER 0x08
#define EFI_FV_FILETYPE_APPLICATION 0x09
#define EFI_FV_FILETYPE_SMM 0x0A
#define EFI_FV_FILETYPE_FIRMWARE_VOLUME_IMAGE 0x0B
#define EFI_FV_FILETYPE_COMBINED_SMM_DXE 0x0C
#define EFI_FV_FILETYPE_SMM_CORE 0x0D
#define EFI_FV_FILETYPE_OEM_MIN 0xc0
#define EFI_FV_FILETYPE_OEM_MAX 0xdf
#define EFI_FV_FILETYPE_DEBUG_MIN 0xe0
#define EFI_FV_FILETYPE_DEBUG_MAX 0xef
#define EFI_FV_FILETYPE_FFS_MIN 0xf0
#define EFI_FV_FILETYPE_FFS_MAX 0xff
#define EFI_FV_FILETYPE_FFS_PAD 0xf0
///
/// FFS File Attributes.
///
#define FFS_ATTRIB_LARGE_FILE 0x01
#define FFS_ATTRIB_FIXED 0x04
#define FFS_ATTRIB_DATA_ALIGNMENT 0x38
#define FFS_ATTRIB_CHECKSUM 0x40
///
/// FFS File State Bits.
///
#define EFI_FILE_HEADER_CONSTRUCTION 0x01
#define EFI_FILE_HEADER_VALID 0x02
#define EFI_FILE_DATA_VALID 0x04
#define EFI_FILE_MARKED_FOR_UPDATE 0x08
#define EFI_FILE_DELETED 0x10
#define EFI_FILE_HEADER_INVALID 0x20
///
/// Each file begins with the header that describe the
/// contents and state of the files.
///
typedef struct {
///
/// This GUID is the file name. It is used to uniquely identify the file.
///
EFI_GUID Name;
///
/// Used to verify the integrity of the file.
///
EFI_FFS_INTEGRITY_CHECK IntegrityCheck;
///
/// Identifies the type of file.
///
EFI_FV_FILETYPE Type;
///
/// Declares various file attribute bits.
///
EFI_FFS_FILE_ATTRIBUTES Attributes;
///
/// The length of the file in bytes, including the FFS header.
///
UINT8 Size[3];
///
/// Used to track the state of the file throughout the life of the file from creation to deletion.
///
EFI_FFS_FILE_STATE State;
} EFI_FFS_FILE_HEADER;
typedef struct {
///
/// This GUID is the file name. It is used to uniquely identify the file. There may be only
/// one instance of a file with the file name GUID of Name in any given firmware
/// volume, except if the file type is EFI_FV_FILETYPE_FFS_PAD.
///
EFI_GUID Name;
///
/// Used to verify the integrity of the file.
///
EFI_FFS_INTEGRITY_CHECK IntegrityCheck;
///
/// Identifies the type of file.
///
EFI_FV_FILETYPE Type;
///
/// Declares various file attribute bits.
///
EFI_FFS_FILE_ATTRIBUTES Attributes;
///
/// The length of the file in bytes, including the FFS header.
/// The length of the file data is either (Size - sizeof(EFI_FFS_FILE_HEADER)). This calculation means a
/// zero-length file has a Size of 24 bytes, which is sizeof(EFI_FFS_FILE_HEADER).
/// Size is not required to be a multiple of 8 bytes. Given a file F, the next file header is
/// located at the next 8-byte aligned firmware volume offset following the last byte of the file F.
///
UINT8 Size[3];
///
/// Used to track the state of the file throughout the life of the file from creation to deletion.
///
EFI_FFS_FILE_STATE State;
///
/// If FFS_ATTRIB_LARGE_FILE is set in Attributes, then ExtendedSize exists and Size must be set to zero.
/// If FFS_ATTRIB_LARGE_FILE is not set then EFI_FFS_FILE_HEADER is used.
///
UINT32 ExtendedSize;
} EFI_FFS_FILE_HEADER2;
#define IS_FFS_FILE2(FfsFileHeaderPtr) \
(((((EFI_FFS_FILE_HEADER *) (UINTN) FfsFileHeaderPtr)->Attributes) & FFS_ATTRIB_LARGE_FILE) == FFS_ATTRIB_LARGE_FILE)
#define FFS_FILE_SIZE(FfsFileHeaderPtr) \
((UINT32) (*((UINT32 *) ((EFI_FFS_FILE_HEADER *) (UINTN) FfsFileHeaderPtr)->Size) & 0x00ffffff))
#define FFS_FILE2_SIZE(FfsFileHeaderPtr) \
(((EFI_FFS_FILE_HEADER2 *) (UINTN) FfsFileHeaderPtr)->ExtendedSize)
typedef UINT8 EFI_SECTION_TYPE;
///
/// Pseudo type. It is used as a wild card when retrieving sections.
/// The section type EFI_SECTION_ALL matches all section types.
///
#define EFI_SECTION_ALL 0x00
///
/// Encapsulation section Type values.
///
#define EFI_SECTION_COMPRESSION 0x01
#define EFI_SECTION_GUID_DEFINED 0x02
#define EFI_SECTION_DISPOSABLE 0x03
///
/// Leaf section Type values.
///
#define EFI_SECTION_PE32 0x10
#define EFI_SECTION_PIC 0x11
#define EFI_SECTION_TE 0x12
#define EFI_SECTION_DXE_DEPEX 0x13
#define EFI_SECTION_VERSION 0x14
#define EFI_SECTION_USER_INTERFACE 0x15
#define EFI_SECTION_COMPATIBILITY16 0x16
#define EFI_SECTION_FIRMWARE_VOLUME_IMAGE 0x17
#define EFI_SECTION_FREEFORM_SUBTYPE_GUID 0x18
#define EFI_SECTION_RAW 0x19
#define EFI_SECTION_PEI_DEPEX 0x1B
#define EFI_SECTION_SMM_DEPEX 0x1C
///
/// Common section header.
///
typedef struct {
///
/// A 24-bit unsigned integer that contains the total size of the section in bytes,
/// including the EFI_COMMON_SECTION_HEADER.
///
UINT8 Size[3];
EFI_SECTION_TYPE Type;
///
/// Declares the section type.
///
} EFI_COMMON_SECTION_HEADER;
typedef struct {
///
/// A 24-bit unsigned integer that contains the total size of the section in bytes,
/// including the EFI_COMMON_SECTION_HEADER.
///
UINT8 Size[3];
EFI_SECTION_TYPE Type;
///
/// If Size is 0xFFFFFF, then ExtendedSize contains the size of the section. If
/// Size is not equal to 0xFFFFFF, then this field does not exist.
///
UINT32 ExtendedSize;
} EFI_COMMON_SECTION_HEADER2;
///
/// Leaf section type that contains an
/// IA-32 16-bit executable image.
///
typedef EFI_COMMON_SECTION_HEADER EFI_COMPATIBILITY16_SECTION;
typedef EFI_COMMON_SECTION_HEADER2 EFI_COMPATIBILITY16_SECTION2;
///
/// CompressionType of EFI_COMPRESSION_SECTION.
///
#define EFI_NOT_COMPRESSED 0x00
#define EFI_STANDARD_COMPRESSION 0x01
///
/// An encapsulation section type in which the
/// section data is compressed.
///
typedef struct {
///
/// Usual common section header. CommonHeader.Type = EFI_SECTION_COMPRESSION.
///
EFI_COMMON_SECTION_HEADER CommonHeader;
///
/// The UINT32 that indicates the size of the section data after decompression.
///
UINT32 UncompressedLength;
///
/// Indicates which compression algorithm is used.
///
UINT8 CompressionType;
} EFI_COMPRESSION_SECTION;
typedef struct {
///
/// Usual common section header. CommonHeader.Type = EFI_SECTION_COMPRESSION.
///
EFI_COMMON_SECTION_HEADER2 CommonHeader;
///
/// UINT32 that indicates the size of the section data after decompression.
///
UINT32 UncompressedLength;
///
/// Indicates which compression algorithm is used.
///
UINT8 CompressionType;
} EFI_COMPRESSION_SECTION2;
///
/// An encapsulation section type in which the section data is disposable.
/// A disposable section is an encapsulation section in which the section data may be disposed of during
/// the process of creating or updating a firmware image without significant impact on the usefulness of
/// the file. The Type field in the section header is set to EFI_SECTION_DISPOSABLE. This
/// allows optional or descriptive data to be included with the firmware file which can be removed in
/// order to conserve space. The contents of this section are implementation specific, but might contain
/// debug data or detailed integration instructions.
///
typedef EFI_COMMON_SECTION_HEADER EFI_DISPOSABLE_SECTION;
typedef EFI_COMMON_SECTION_HEADER2 EFI_DISPOSABLE_SECTION2;
///
/// The leaf section which could be used to determine the dispatch order of DXEs.
///
typedef EFI_COMMON_SECTION_HEADER EFI_DXE_DEPEX_SECTION;
typedef EFI_COMMON_SECTION_HEADER2 EFI_DXE_DEPEX_SECTION2;
///
/// The leaf section which contains a PI FV.
///
typedef EFI_COMMON_SECTION_HEADER EFI_FIRMWARE_VOLUME_IMAGE_SECTION;
typedef EFI_COMMON_SECTION_HEADER2 EFI_FIRMWARE_VOLUME_IMAGE_SECTION2;
///
/// The leaf section which contains a single GUID.
///
typedef struct {
///
/// Common section header. CommonHeader.Type = EFI_SECTION_FREEFORM_SUBTYPE_GUID.
///
EFI_COMMON_SECTION_HEADER CommonHeader;
///
/// This GUID is defined by the creator of the file. It is a vendor-defined file type.
///
EFI_GUID SubTypeGuid;
} EFI_FREEFORM_SUBTYPE_GUID_SECTION;
typedef struct {
///
/// The common section header. CommonHeader.Type = EFI_SECTION_FREEFORM_SUBTYPE_GUID.
///
EFI_COMMON_SECTION_HEADER2 CommonHeader;
///
/// This GUID is defined by the creator of the file. It is a vendor-defined file type.
///
EFI_GUID SubTypeGuid;
} EFI_FREEFORM_SUBTYPE_GUID_SECTION2;
///
/// Attributes of EFI_GUID_DEFINED_SECTION.
///
#define EFI_GUIDED_SECTION_PROCESSING_REQUIRED 0x01
#define EFI_GUIDED_SECTION_AUTH_STATUS_VALID 0x02
///
/// The leaf section which is encapsulation defined by specific GUID.
///
typedef struct {
///
/// The common section header. CommonHeader.Type = EFI_SECTION_GUID_DEFINED.
///
EFI_COMMON_SECTION_HEADER CommonHeader;
///
/// The GUID that defines the format of the data that follows. It is a vendor-defined section type.
///
EFI_GUID SectionDefinitionGuid;
///
/// Contains the offset in bytes from the beginning of the common header to the first byte of the data.
///
UINT16 DataOffset;
///
/// The bit field that declares some specific characteristics of the section contents.
///
UINT16 Attributes;
} EFI_GUID_DEFINED_SECTION;
typedef struct {
///
/// The common section header. CommonHeader.Type = EFI_SECTION_GUID_DEFINED.
///
EFI_COMMON_SECTION_HEADER2 CommonHeader;
///
/// The GUID that defines the format of the data that follows. It is a vendor-defined section type.
///
EFI_GUID SectionDefinitionGuid;
///
/// Contains the offset in bytes from the beginning of the common header to the first byte of the data.
///
UINT16 DataOffset;
///
/// The bit field that declares some specific characteristics of the section contents.
///
UINT16 Attributes;
} EFI_GUID_DEFINED_SECTION2;
///
/// The leaf section which contains PE32+ image.
///
typedef EFI_COMMON_SECTION_HEADER EFI_PE32_SECTION;
typedef EFI_COMMON_SECTION_HEADER2 EFI_PE32_SECTION2;
///
/// The leaf section used to determine the dispatch order of PEIMs.
///
typedef EFI_COMMON_SECTION_HEADER EFI_PEI_DEPEX_SECTION;
typedef EFI_COMMON_SECTION_HEADER2 EFI_PEI_DEPEX_SECTION2;
///
/// A leaf section type that contains a position-independent-code (PIC) image.
/// A PIC image section is a leaf section that contains a position-independent-code (PIC) image.
/// In addition to normal PE32+ images that contain relocation information, PEIM executables may be
/// PIC and are referred to as PIC images. A PIC image is the same as a PE32+ image except that all
/// relocation information has been stripped from the image and the image can be moved and will
/// execute correctly without performing any relocation or other fix-ups. EFI_PIC_SECTION2 must
/// be used if the section is 16MB or larger.
///
typedef EFI_COMMON_SECTION_HEADER EFI_PIC_SECTION;
typedef EFI_COMMON_SECTION_HEADER2 EFI_PIC_SECTION2;
///
/// The leaf section which constains the position-independent-code image.
///
typedef EFI_COMMON_SECTION_HEADER EFI_TE_SECTION;
typedef EFI_COMMON_SECTION_HEADER2 EFI_TE_SECTION2;
///
/// The leaf section which contains an array of zero or more bytes.
///
typedef EFI_COMMON_SECTION_HEADER EFI_RAW_SECTION;
typedef EFI_COMMON_SECTION_HEADER2 EFI_RAW_SECTION2;
///
/// The SMM dependency expression section is a leaf section that contains a dependency expression that
/// is used to determine the dispatch order for SMM drivers. Before the SMRAM invocation of the
/// SMM driver's entry point, this dependency expression must evaluate to TRUE. See the Platform
/// Initialization Specification, Volume 2, for details regarding the format of the dependency expression.
/// The dependency expression may refer to protocols installed in either the UEFI or the SMM protocol
/// database. EFI_SMM_DEPEX_SECTION2 must be used if the section is 16MB or larger.
///
typedef EFI_COMMON_SECTION_HEADER EFI_SMM_DEPEX_SECTION;
typedef EFI_COMMON_SECTION_HEADER2 EFI_SMM_DEPEX_SECTION2;
///
/// The leaf section which contains a unicode string that
/// is human readable file name.
///
typedef struct {
EFI_COMMON_SECTION_HEADER CommonHeader;
///
/// Array of unicode string.
///
CHAR16 FileNameString[1];
} EFI_USER_INTERFACE_SECTION;
typedef struct {
EFI_COMMON_SECTION_HEADER2 CommonHeader;
CHAR16 FileNameString[1];
} EFI_USER_INTERFACE_SECTION2;
///
/// The leaf section which contains a numeric build number and
/// an optional unicode string that represents the file revision.
///
typedef struct {
EFI_COMMON_SECTION_HEADER CommonHeader;
UINT16 BuildNumber;
///
/// Array of unicode string.
///
CHAR16 VersionString[1];
} EFI_VERSION_SECTION;
typedef struct {
EFI_COMMON_SECTION_HEADER2 CommonHeader;
///
/// A UINT16 that represents a particular build. Subsequent builds have monotonically
/// increasing build numbers relative to earlier builds.
///
UINT16 BuildNumber;
CHAR16 VersionString[1];
} EFI_VERSION_SECTION2;
#define IS_SECTION2(SectionHeaderPtr) \
((UINT32) (*((UINT32 *) ((EFI_COMMON_SECTION_HEADER *) (UINTN) SectionHeaderPtr)->Size) & 0x00ffffff) == 0x00ffffff)
#define SECTION_SIZE(SectionHeaderPtr) \
((UINT32) (*((UINT32 *) ((EFI_COMMON_SECTION_HEADER *) (UINTN) SectionHeaderPtr)->Size) & 0x00ffffff))
#define SECTION2_SIZE(SectionHeaderPtr) \
(((EFI_COMMON_SECTION_HEADER2 *) (UINTN) SectionHeaderPtr)->ExtendedSize)
#pragma pack()
#endif

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/** @file
Copyright (C) 2013, Intel Corporation
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
**/
#ifndef __PI_FIRMWAREVOLUME_H__
#define __PI_FIRMWAREVOLUME_H__
///
/// EFI_FV_FILE_ATTRIBUTES
///
typedef UINT32 EFI_FV_FILE_ATTRIBUTES;
//
// Value of EFI_FV_FILE_ATTRIBUTES.
//
#define EFI_FV_FILE_ATTRIB_ALIGNMENT 0x0000001F
#define EFI_FV_FILE_ATTRIB_FIXED 0x00000100
#define EFI_FV_FILE_ATTRIB_MEMORY_MAPPED 0x00000200
///
/// type of EFI FVB attribute
///
typedef UINT32 EFI_FVB_ATTRIBUTES_2;
//
// Attributes bit definitions
//
#define EFI_FVB2_READ_DISABLED_CAP 0x00000001
#define EFI_FVB2_READ_ENABLED_CAP 0x00000002
#define EFI_FVB2_READ_STATUS 0x00000004
#define EFI_FVB2_WRITE_DISABLED_CAP 0x00000008
#define EFI_FVB2_WRITE_ENABLED_CAP 0x00000010
#define EFI_FVB2_WRITE_STATUS 0x00000020
#define EFI_FVB2_LOCK_CAP 0x00000040
#define EFI_FVB2_LOCK_STATUS 0x00000080
#define EFI_FVB2_STICKY_WRITE 0x00000200
#define EFI_FVB2_MEMORY_MAPPED 0x00000400
#define EFI_FVB2_ERASE_POLARITY 0x00000800
#define EFI_FVB2_READ_LOCK_CAP 0x00001000
#define EFI_FVB2_READ_LOCK_STATUS 0x00002000
#define EFI_FVB2_WRITE_LOCK_CAP 0x00004000
#define EFI_FVB2_WRITE_LOCK_STATUS 0x00008000
#define EFI_FVB2_ALIGNMENT 0x001F0000
#define EFI_FVB2_ALIGNMENT_1 0x00000000
#define EFI_FVB2_ALIGNMENT_2 0x00010000
#define EFI_FVB2_ALIGNMENT_4 0x00020000
#define EFI_FVB2_ALIGNMENT_8 0x00030000
#define EFI_FVB2_ALIGNMENT_16 0x00040000
#define EFI_FVB2_ALIGNMENT_32 0x00050000
#define EFI_FVB2_ALIGNMENT_64 0x00060000
#define EFI_FVB2_ALIGNMENT_128 0x00070000
#define EFI_FVB2_ALIGNMENT_256 0x00080000
#define EFI_FVB2_ALIGNMENT_512 0x00090000
#define EFI_FVB2_ALIGNMENT_1K 0x000A0000
#define EFI_FVB2_ALIGNMENT_2K 0x000B0000
#define EFI_FVB2_ALIGNMENT_4K 0x000C0000
#define EFI_FVB2_ALIGNMENT_8K 0x000D0000
#define EFI_FVB2_ALIGNMENT_16K 0x000E0000
#define EFI_FVB2_ALIGNMENT_32K 0x000F0000
#define EFI_FVB2_ALIGNMENT_64K 0x00100000
#define EFI_FVB2_ALIGNMENT_128K 0x00110000
#define EFI_FVB2_ALIGNMENT_256K 0x00120000
#define EFI_FVB2_ALIGNMENT_512K 0x00130000
#define EFI_FVB2_ALIGNMENT_1M 0x00140000
#define EFI_FVB2_ALIGNMENT_2M 0x00150000
#define EFI_FVB2_ALIGNMENT_4M 0x00160000
#define EFI_FVB2_ALIGNMENT_8M 0x00170000
#define EFI_FVB2_ALIGNMENT_16M 0x00180000
#define EFI_FVB2_ALIGNMENT_32M 0x00190000
#define EFI_FVB2_ALIGNMENT_64M 0x001A0000
#define EFI_FVB2_ALIGNMENT_128M 0x001B0000
#define EFI_FVB2_ALIGNMENT_256M 0x001C0000
#define EFI_FVB2_ALIGNMENT_512M 0x001D0000
#define EFI_FVB2_ALIGNMENT_1G 0x001E0000
#define EFI_FVB2_ALIGNMENT_2G 0x001F0000
typedef struct {
///
/// The number of sequential blocks which are of the same size.
///
UINT32 NumBlocks;
///
/// The size of the blocks.
///
UINT32 Length;
} EFI_FV_BLOCK_MAP_ENTRY;
///
/// Describes the features and layout of the firmware volume.
///
typedef struct {
///
/// The first 16 bytes are reserved to allow for the reset vector of
/// processors whose reset vector is at address 0.
///
UINT8 ZeroVector[16];
///
/// Declares the file system with which the firmware volume is formatted.
///
EFI_GUID FileSystemGuid;
///
/// Length in bytes of the complete firmware volume, including the header.
///
UINT64 FvLength;
///
/// Set to EFI_FVH_SIGNATURE
///
UINT32 Signature;
///
/// Declares capabilities and power-on defaults for the firmware volume.
///
EFI_FVB_ATTRIBUTES_2 Attributes;
///
/// Length in bytes of the complete firmware volume header.
///
UINT16 HeaderLength;
///
/// A 16-bit checksum of the firmware volume header. A valid header sums to zero.
///
UINT16 Checksum;
///
/// Offset, relative to the start of the header, of the extended header
/// (EFI_FIRMWARE_VOLUME_EXT_HEADER) or zero if there is no extended header.
///
UINT16 ExtHeaderOffset;
///
/// This field must always be set to zero.
///
UINT8 Reserved[1];
///
/// Set to 2. Future versions of this specification may define new header fields and will
/// increment the Revision field accordingly.
///
UINT8 Revision;
///
/// An array of run-length encoded FvBlockMapEntry structures. The array is
/// terminated with an entry of {0,0}.
///
EFI_FV_BLOCK_MAP_ENTRY BlockMap[1];
} EFI_FIRMWARE_VOLUME_HEADER;
#define EFI_FVH_SIGNATURE SIGNATURE_32 ('_', 'F', 'V', 'H')
///
/// Firmware Volume Header Revision definition
///
#define EFI_FVH_REVISION 0x02
///
/// Extension header pointed by ExtHeaderOffset of volume header.
///
typedef struct {
///
/// Firmware volume name.
///
EFI_GUID FvName;
///
/// Size of the rest of the extension header, including this structure.
///
UINT32 ExtHeaderSize;
} EFI_FIRMWARE_VOLUME_EXT_HEADER;
///
/// Entry struture for describing FV extension header
///
typedef struct {
///
/// Size of this header extension.
///
UINT16 ExtEntrySize;
///
/// Type of the header.
///
UINT16 ExtEntryType;
} EFI_FIRMWARE_VOLUME_EXT_ENTRY;
#define EFI_FV_EXT_TYPE_OEM_TYPE 0x01
///
/// This extension header provides a mapping between a GUID and an OEM file type.
///
typedef struct {
///
/// Standard extension entry, with the type EFI_FV_EXT_TYPE_OEM_TYPE.
///
EFI_FIRMWARE_VOLUME_EXT_ENTRY Hdr;
///
/// A bit mask, one bit for each file type between 0xC0 (bit 0) and 0xDF (bit 31). If a bit
/// is '1', then the GUID entry exists in Types. If a bit is '0' then no GUID entry exists in Types.
///
UINT32 TypeMask;
///
/// An array of GUIDs, each GUID representing an OEM file type.
///
/// EFI_GUID Types[1];
///
} EFI_FIRMWARE_VOLUME_EXT_ENTRY_OEM_TYPE;
#define EFI_FV_EXT_TYPE_GUID_TYPE 0x0002
///
/// This extension header EFI_FIRMWARE_VOLUME_EXT_ENTRY_GUID_TYPE provides a vendor specific
/// GUID FormatType type which includes a length and a successive series of data bytes.
///
typedef struct {
///
/// Standard extension entry, with the type EFI_FV_EXT_TYPE_OEM_TYPE.
///
EFI_FIRMWARE_VOLUME_EXT_ENTRY Hdr;
///
/// Vendor-specific GUID.
///
EFI_GUID FormatType;
///
/// An arry of bytes of length Length.
///
/// UINT8 Data[1];
///
} EFI_FIRMWARE_VOLUME_EXT_ENTRY_GUID_TYPE;
#endif

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/** @file
Copyright (C) 2013, Intel Corporation
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
**/
#ifndef __PI_HOB_H__
#define __PI_HOB_H__
//
// HobType of EFI_HOB_GENERIC_HEADER.
//
#define EFI_HOB_TYPE_MEMORY_ALLOCATION 0x0002
#define EFI_HOB_TYPE_RESOURCE_DESCRIPTOR 0x0003
#define EFI_HOB_TYPE_GUID_EXTENSION 0x0004
#define EFI_HOB_TYPE_UNUSED 0xFFFE
#define EFI_HOB_TYPE_END_OF_HOB_LIST 0xFFFF
///
/// Describes the format and size of the data inside the HOB.
/// All HOBs must contain this generic HOB header.
///
typedef struct {
///
/// Identifies the HOB data structure type.
///
UINT16 HobType;
///
/// The length in bytes of the HOB.
///
UINT16 HobLength;
///
/// This field must always be set to zero.
///
UINT32 Reserved;
} EFI_HOB_GENERIC_HEADER;
///
/// Enumeration of memory types introduced in UEFI.
///
typedef enum {
///
/// Not used.
///
EfiReservedMemoryType,
///
/// The code portions of a loaded application.
/// (Note that UEFI OS loaders are UEFI applications.)
///
EfiLoaderCode,
///
/// The data portions of a loaded application and the default data allocation
/// type used by an application to allocate pool memory.
///
EfiLoaderData,
///
/// The code portions of a loaded Boot Services Driver.
///
EfiBootServicesCode,
///
/// The data portions of a loaded Boot Serves Driver, and the default data
/// allocation type used by a Boot Services Driver to allocate pool memory.
///
EfiBootServicesData,
///
/// The code portions of a loaded Runtime Services Driver.
///
EfiRuntimeServicesCode,
///
/// The data portions of a loaded Runtime Services Driver and the default
/// data allocation type used by a Runtime Services Driver to allocate pool memory.
///
EfiRuntimeServicesData,
///
/// Free (unallocated) memory.
///
EfiConventionalMemory,
///
/// Memory in which errors have been detected.
///
EfiUnusableMemory,
///
/// Memory that holds the ACPI tables.
///
EfiACPIReclaimMemory,
///
/// Address space reserved for use by the firmware.
///
EfiACPIMemoryNVS,
///
/// Used by system firmware to request that a memory-mapped IO region
/// be mapped by the OS to a virtual address so it can be accessed by EFI runtime services.
///
EfiMemoryMappedIO,
///
/// System memory-mapped IO region that is used to translate memory
/// cycles to IO cycles by the processor.
///
EfiMemoryMappedIOPortSpace,
///
/// Address space reserved by the firmware for code that is part of the processor.
///
EfiPalCode,
EfiMaxMemoryType
} EFI_MEMORY_TYPE;
///
/// EFI_HOB_MEMORY_ALLOCATION_HEADER describes the
/// various attributes of the logical memory allocation. The type field will be used for
/// subsequent inclusion in the UEFI memory map.
///
typedef struct {
///
/// A GUID that defines the memory allocation region's type and purpose, as well as
/// other fields within the memory allocation HOB. This GUID is used to define the
/// additional data within the HOB that may be present for the memory allocation HOB.
/// Type EFI_GUID is defined in InstallProtocolInterface() in the UEFI 2.0
/// specification.
///
EFI_GUID Name;
///
/// The base address of memory allocated by this HOB. Type
/// EFI_PHYSICAL_ADDRESS is defined in AllocatePages() in the UEFI 2.0
/// specification.
///
EFI_PHYSICAL_ADDRESS MemoryBaseAddress;
///
/// The length in bytes of memory allocated by this HOB.
///
UINT64 MemoryLength;
///
/// Defines the type of memory allocated by this HOB. The memory type definition
/// follows the EFI_MEMORY_TYPE definition. Type EFI_MEMORY_TYPE is defined
/// in AllocatePages() in the UEFI 2.0 specification.
///
EFI_MEMORY_TYPE MemoryType;
///
/// Padding for Itanium processor family
///
UINT8 Reserved[4];
} EFI_HOB_MEMORY_ALLOCATION_HEADER;
///
/// Describes all memory ranges used during the HOB producer
/// phase that exist outside the HOB list. This HOB type
/// describes how memory is used, not the physical attributes of memory.
///
typedef struct {
///
/// The HOB generic header. Header.HobType = EFI_HOB_TYPE_MEMORY_ALLOCATION.
///
EFI_HOB_GENERIC_HEADER Header;
///
/// An instance of the EFI_HOB_MEMORY_ALLOCATION_HEADER that describes the
/// various attributes of the logical memory allocation.
///
EFI_HOB_MEMORY_ALLOCATION_HEADER AllocDescriptor;
//
// Additional data pertaining to the "Name" Guid memory
// may go here.
//
} EFI_HOB_MEMORY_ALLOCATION;
///
/// The resource type.
///
typedef UINT32 EFI_RESOURCE_TYPE;
//
// Value of ResourceType in EFI_HOB_RESOURCE_DESCRIPTOR.
//
#define EFI_RESOURCE_SYSTEM_MEMORY 0x00000000
#define EFI_RESOURCE_MEMORY_MAPPED_IO 0x00000001
#define EFI_RESOURCE_IO 0x00000002
#define EFI_RESOURCE_FIRMWARE_DEVICE 0x00000003
#define EFI_RESOURCE_MEMORY_MAPPED_IO_PORT 0x00000004
#define EFI_RESOURCE_MEMORY_RESERVED 0x00000005
#define EFI_RESOURCE_IO_RESERVED 0x00000006
#define EFI_RESOURCE_MAX_MEMORY_TYPE 0x00000007
///
/// A type of recount attribute type.
///
typedef UINT32 EFI_RESOURCE_ATTRIBUTE_TYPE;
//
// These types can be ORed together as needed.
//
// The first three enumerations describe settings
//
#define EFI_RESOURCE_ATTRIBUTE_PRESENT 0x00000001
#define EFI_RESOURCE_ATTRIBUTE_INITIALIZED 0x00000002
#define EFI_RESOURCE_ATTRIBUTE_TESTED 0x00000004
//
// The rest of the settings describe capabilities
//
#define EFI_RESOURCE_ATTRIBUTE_SINGLE_BIT_ECC 0x00000008
#define EFI_RESOURCE_ATTRIBUTE_MULTIPLE_BIT_ECC 0x00000010
#define EFI_RESOURCE_ATTRIBUTE_ECC_RESERVED_1 0x00000020
#define EFI_RESOURCE_ATTRIBUTE_ECC_RESERVED_2 0x00000040
#define EFI_RESOURCE_ATTRIBUTE_READ_PROTECTED 0x00000080
#define EFI_RESOURCE_ATTRIBUTE_WRITE_PROTECTED 0x00000100
#define EFI_RESOURCE_ATTRIBUTE_EXECUTION_PROTECTED 0x00000200
#define EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE 0x00000400
#define EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE 0x00000800
#define EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE 0x00001000
#define EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE 0x00002000
#define EFI_RESOURCE_ATTRIBUTE_16_BIT_IO 0x00004000
#define EFI_RESOURCE_ATTRIBUTE_32_BIT_IO 0x00008000
#define EFI_RESOURCE_ATTRIBUTE_64_BIT_IO 0x00010000
#define EFI_RESOURCE_ATTRIBUTE_UNCACHED_EXPORTED 0x00020000
///
/// Describes the resource properties of all fixed,
/// nonrelocatable resource ranges found on the processor
/// host bus during the HOB producer phase.
///
typedef struct {
///
/// The HOB generic header. Header.HobType = EFI_HOB_TYPE_RESOURCE_DESCRIPTOR.
///
EFI_HOB_GENERIC_HEADER Header;
///
/// A GUID representing the owner of the resource. This GUID is used by HOB
/// consumer phase components to correlate device ownership of a resource.
///
EFI_GUID Owner;
///
/// The resource type enumeration as defined by EFI_RESOURCE_TYPE.
///
EFI_RESOURCE_TYPE ResourceType;
///
/// Resource attributes as defined by EFI_RESOURCE_ATTRIBUTE_TYPE.
///
EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttribute;
///
/// The physical start address of the resource region.
///
EFI_PHYSICAL_ADDRESS PhysicalStart;
///
/// The number of bytes of the resource region.
///
UINT64 ResourceLength;
} EFI_HOB_RESOURCE_DESCRIPTOR;
///
/// Allows writers of executable content in the HOB producer phase to
/// maintain and manage HOBs with specific GUID.
///
typedef struct {
///
/// The HOB generic header. Header.HobType = EFI_HOB_TYPE_GUID_EXTENSION.
///
EFI_HOB_GENERIC_HEADER Header;
///
/// A GUID that defines the contents of this HOB.
///
EFI_GUID Name;
//
// Guid specific data goes here
//
} EFI_HOB_GUID_TYPE;
///
/// Union of all the possible HOB Types.
///
typedef union {
EFI_HOB_GENERIC_HEADER *Header;
EFI_HOB_MEMORY_ALLOCATION *MemoryAllocation;
EFI_HOB_RESOURCE_DESCRIPTOR *ResourceDescriptor;
EFI_HOB_GUID_TYPE *Guid;
UINT8 *Raw;
} EFI_PEI_HOB_POINTERS;
/**
Returns the type of a HOB.
This macro returns the HobType field from the HOB header for the
HOB specified by HobStart.
@param HobStart A pointer to a HOB.
@return HobType.
**/
#define GET_HOB_TYPE(HobStart) \
((*(EFI_HOB_GENERIC_HEADER **)&(HobStart))->HobType)
/**
Returns the length, in bytes, of a HOB.
This macro returns the HobLength field from the HOB header for the
HOB specified by HobStart.
@param HobStart A pointer to a HOB.
@return HobLength.
**/
#define GET_HOB_LENGTH(HobStart) \
((*(EFI_HOB_GENERIC_HEADER **)&(HobStart))->HobLength)
/**
Returns a pointer to the next HOB in the HOB list.
This macro returns a pointer to HOB that follows the
HOB specified by HobStart in the HOB List.
@param HobStart A pointer to a HOB.
@return A pointer to the next HOB in the HOB list.
**/
#define GET_NEXT_HOB(HobStart) \
(VOID *)(*(UINT8 **)&(HobStart) + GET_HOB_LENGTH (HobStart))
/**
Determines if a HOB is the last HOB in the HOB list.
This macro determine if the HOB specified by HobStart is the
last HOB in the HOB list. If HobStart is last HOB in the HOB list,
then TRUE is returned. Otherwise, FALSE is returned.
@param HobStart A pointer to a HOB.
@retval TRUE The HOB specified by HobStart is the last HOB in the HOB list.
@retval FALSE The HOB specified by HobStart is not the last HOB in the HOB list.
**/
#define END_OF_HOB_LIST(HobStart) (GET_HOB_TYPE (HobStart) == (UINT16)EFI_HOB_TYPE_END_OF_HOB_LIST)
/**
Returns a pointer to data buffer from a HOB of type EFI_HOB_TYPE_GUID_EXTENSION.
This macro returns a pointer to the data buffer in a HOB specified by HobStart.
HobStart is assumed to be a HOB of type EFI_HOB_TYPE_GUID_EXTENSION.
@param GuidHob A pointer to a HOB.
@return A pointer to the data buffer in a HOB.
**/
#define GET_GUID_HOB_DATA(HobStart) \
(VOID *)(*(UINT8 **)&(HobStart) + sizeof (EFI_HOB_GUID_TYPE))
/**
Returns the size of the data buffer from a HOB of type EFI_HOB_TYPE_GUID_EXTENSION.
This macro returns the size, in bytes, of the data buffer in a HOB specified by HobStart.
HobStart is assumed to be a HOB of type EFI_HOB_TYPE_GUID_EXTENSION.
@param GuidHob A pointer to a HOB.
@return The size of the data buffer.
**/
#define GET_GUID_HOB_DATA_SIZE(HobStart) \
(UINT16)(GET_HOB_LENGTH (HobStart) - sizeof (EFI_HOB_GUID_TYPE))
/**
Returns the pointer to the HOB list.
This function returns the pointer to first HOB in the list.
If the pointer to the HOB list is NULL, then ASSERT().
@return The pointer to the HOB list.
**/
VOID *
EFIAPI
GetHobList (
VOID
);
/**
Returns the next instance of a HOB type from the starting HOB.
This function searches the first instance of a HOB type from the starting HOB pointer.
If there does not exist such HOB type from the starting HOB pointer, it will return NULL.
In contrast with macro GET_NEXT_HOB(), this function does not skip the starting HOB pointer
unconditionally: it returns HobStart back if HobStart itself meets the requirement;
caller is required to use GET_NEXT_HOB() if it wishes to skip current HobStart.
If HobStart is NULL, then ASSERT().
@param Type The HOB type to return.
@param HobStart The starting HOB pointer to search from.
@return The next instance of a HOB type from the starting HOB.
**/
VOID *
EFIAPI
GetNextHob (
UINT16 Type,
CONST VOID *HobStart
);
/**
Returns the first instance of a HOB type among the whole HOB list.
This function searches the first instance of a HOB type among the whole HOB list.
If there does not exist such HOB type in the HOB list, it will return NULL.
If the pointer to the HOB list is NULL, then ASSERT().
@param Type The HOB type to return.
@return The next instance of a HOB type from the starting HOB.
**/
VOID *
EFIAPI
GetFirstHob (
UINT16 Type
);
/**
Returns the next instance of the matched GUID HOB from the starting HOB.
This function searches the first instance of a HOB from the starting HOB pointer.
Such HOB should satisfy two conditions:
its HOB type is EFI_HOB_TYPE_GUID_EXTENSION and its GUID Name equals to the input Guid.
If there does not exist such HOB from the starting HOB pointer, it will return NULL.
Caller is required to apply GET_GUID_HOB_DATA () and GET_GUID_HOB_DATA_SIZE ()
to extract the data section and its size info respectively.
In contrast with macro GET_NEXT_HOB(), this function does not skip the starting HOB pointer
unconditionally: it returns HobStart back if HobStart itself meets the requirement;
caller is required to use GET_NEXT_HOB() if it wishes to skip current HobStart.
If Guid is NULL, then ASSERT().
If HobStart is NULL, then ASSERT().
@param Guid The GUID to match with in the HOB list.
@param HobStart A pointer to a Guid.
@return The next instance of the matched GUID HOB from the starting HOB.
**/
VOID *
EFIAPI
GetNextGuidHob (
CONST EFI_GUID *Guid,
CONST VOID *HobStart
);
/**
Returns the first instance of the matched GUID HOB among the whole HOB list.
This function searches the first instance of a HOB among the whole HOB list.
Such HOB should satisfy two conditions:
its HOB type is EFI_HOB_TYPE_GUID_EXTENSION and its GUID Name equals to the input Guid.
If there does not exist such HOB from the starting HOB pointer, it will return NULL.
Caller is required to apply GET_GUID_HOB_DATA () and GET_GUID_HOB_DATA_SIZE ()
to extract the data section and its size info respectively.
If the pointer to the HOB list is NULL, then ASSERT().
If Guid is NULL, then ASSERT().
@param Guid The GUID to match with in the HOB list.
@return The first instance of the matched GUID HOB among the whole HOB list.
**/
VOID *
EFIAPI
GetFirstGuidHob (
CONST EFI_GUID *Guid
);
BOOLEAN
EFIAPI
CompareGuid (
CONST EFI_GUID *Guid1,
CONST EFI_GUID *Guid2
);
#endif

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/** @file
Copyright (C) 2013, Intel Corporation
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
**/
#ifndef _FSP_INFO_HEADER_H_
#define _FSP_INFO_HEADER_H_
#pragma pack(1)
typedef struct {
UINT32 Signature; // Off 0x94
UINT32 HeaderLength;
UINT8 Reserved1[3];
UINT8 HeaderRevision;
UINT32 ImageRevision;
CHAR8 ImageId[8]; // Off 0xA4
UINT32 ImageSize;
UINT32 ImageBase;
UINT32 ImageAttribute; // Off 0xB4
UINT32 CfgRegionOffset;
UINT32 CfgRegionSize;
UINT32 ApiEntryNum;
UINT32 NemInitEntry; // Off 0xC4
UINT32 FspInitEntry;
UINT32 NotifyPhaseEntry;
UINT32 Reserved2;
} FSP_INFO_HEADER;
#pragma pack()
#endif

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/** @file
Copyright (C) 2013, Intel Corporation
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
**/
#ifndef _FSP_PLATFORM_H_
#define _FSP_PLATFORM_H_
#include "fsptypes.h"
#include "fspapi.h"
#include "mem_config.h"
#pragma pack(1)
typedef struct {
MEM_CONFIG *MemoryConfig;
} FSP_INIT_RT_PLATFORM_BUFFER;
typedef struct {
FSP_INIT_RT_COMMON_BUFFER Common;
FSP_INIT_RT_PLATFORM_BUFFER Platform;
} FSP_INIT_RT_BUFFER;
#pragma pack()
#endif

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/** @file
Copyright (C) 2013, Intel Corporation
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
**/
/** \file fsptypes.h
*
*
*/
#ifndef __FSP_TYPES_H__
#define __FSP_TYPES_H__
///
/// 8-byte unsigned value.
///
typedef unsigned long long UINT64;
///
/// 8-byte signed value.
///
typedef long long INT64;
///
/// 4-byte unsigned value.
///
typedef unsigned int UINT32;
///
/// 4-byte signed value.
///
typedef int INT32;
///
/// 2-byte unsigned value.
///
typedef unsigned short UINT16;
///
/// 2-byte Character. Unless otherwise specified all strings are stored in the
/// UTF-16 encoding format as defined by Unicode 2.1 and ISO/IEC 10646 standards.
///
typedef unsigned short CHAR16;
///
/// 2-byte signed value.
///
typedef short INT16;
///
/// Logical Boolean. 1-byte value containing 0 for FALSE or a 1 for TRUE. Other
/// values are undefined.
///
typedef unsigned char BOOLEAN;
///
/// 1-byte unsigned value.
///
typedef unsigned char UINT8;
///
/// 1-byte Character
///
typedef char CHAR8;
///
/// 1-byte signed value
///
typedef char INT8;
typedef void VOID;
typedef UINT64 EFI_PHYSICAL_ADDRESS;
typedef struct {
UINT32 Data1;
UINT16 Data2;
UINT16 Data3;
UINT8 Data4[8];
} EFI_GUID;
#define CONST const
#define STATIC static
#define TRUE ((BOOLEAN)(1==1))
#define FALSE ((BOOLEAN)(0==1))
static inline void DebugDeadLoop(void) {
for (;;);
}
#define FSPAPI __attribute__((cdecl))
#define EFIAPI __attribute__((cdecl))
#define _ASSERT(Expression) DebugDeadLoop()
#define ASSERT(Expression) \
do { \
if (!(Expression)) { \
_ASSERT (Expression); \
} \
} while (FALSE)
typedef UINT32 FSP_STATUS;
typedef UINT32 EFI_STATUS;
#endif

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/** @file
Copyright (C) 2013, Intel Corporation
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
**/
//
// mem_config.h
//
#ifndef _MEM_CONFIG_H_
#define _MEM_CONFIG_H_
typedef enum {
fi1067_IVB=0,
fi1333_IVB,
fi1400_IVB,
fi1600_IVB,
fi1800_IVB,
fi1867_IVB,
fi2000_IVB,
fi2133_IVB,
fi2200_IVB,
fi2400_IVB,
fi2600_IVB,
fi2667_IVB,
fi2800_IVB,
fiUnsupport_IVB,
}TFrequencyIndex_IVB;
#define NUM_IVB_MEM_CLK_FREQUENCIES 13
// DDR3 memory SPD data
//
// NOTE: This only includes the SPD bytes that are relevant to the MRC
typedef struct { // BYTE
uint8_t SPDGeneral; // 0 Number of Serial PD Bytes Written / SPD Device Size / CRC Coverage 1, 2
uint8_t SPDRevision; // 1 SPD Revision
uint8_t DRAMDeviceType; // 2 DRAM Device Type
uint8_t ModuleType; // 3 Module Type
uint8_t SDRAMDensityAndBanks; // 4 SDRAM Density and Banks
uint8_t SDRAMAddressing; // 5 SDRAM Addressing
uint8_t VDD; // 6 Module Nominal Voltage
uint8_t ModuleOrganization; // 7 Module Organization
uint8_t ModuleMemoryBusWidth; // 8 Module Memory Bus Width
uint8_t FineTimebase; // 9 Fine Timebase (FTB) Dividend / Divisor
uint8_t TimebaseDividend; // 10 Medium Timebase (MTB) Dividend
uint8_t TimebaseDivisor; // 11 Medium Timebase (MTB) Divisor
uint8_t SDRAMMinimumCycleTime; // 12 SDRAM Minimum Cycle Time (tCKmin)
uint8_t Reserved0; // 13 Reserved0
uint8_t CASLatenciesLSB; // 14 CAS Latencies Supported, Least Significant Byte
uint8_t CASLatenciesMSB; // 15 CAS Latencies Supported, Most Significant Byte
uint8_t MinimumCASLatencyTime; // 16 Minimum CAS Latency Time (tAAmin)
uint8_t MinimumWriteRecoveryTime; // 17 Minimum Write Recovery Time (tWRmin)
uint8_t MinimumRASToCASDelayTime; // 18 Minimum RAS# to CAS# Delay Time (tRCDmin)
uint8_t MinimumRowToRowDelayTime; // 19 Minimum Row Active to Row Active Delay Time (tRRDmin)
uint8_t MinimumRowPrechargeDelayTime; // 20 Minimum Row Precharge Delay Time (tRPmin)
uint8_t UpperNibblesFortRASAndtRC; // 21 Upper Nibbles for tRAS and tRC
uint8_t tRASmin; // 22 Minimum Active to Precharge Delay Time (tRASmin), Least Significant Byte
uint8_t tRCmin; // 23 Minimum Active to Active/Refresh Delay Time (tRCmin), Least Significant Byte
uint8_t tRFCminLeastSignificantByte; // 24 Minimum Refresh Recovery Delay Time (tRFCmin), Least Significant Byte
uint8_t tRFCminMostSignificantByte; // 25 Minimum Refresh Recovery Delay Time (tRFCmin), Most Significant Byte
uint8_t tWTRmin; // 26 Minimum Internal Write to Read Command Delay Time (tWTRmin)
uint8_t tRTPmin; // 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin)
uint8_t UpperNibbleFortFAW; // 28 Upper Nibble for tFAW
uint8_t tFAWmin; // 29 Minimum Four Activate Window Delay Time (tFAWmin)
uint8_t SDRAMOptionalFeatures; // 30 SDRAM Optional Features
uint8_t SDRAMThermalAndRefreshOptions; // 31 SDRAMThermalAndRefreshOptions
uint8_t ModuleThermalSensor; // 32 ModuleThermalSensor
uint8_t SDRAMDeviceType; // 33 SDRAM Device Type
int8_t tCKminFine; // 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin)
int8_t tAAminFine; // 35 Fine Offset for Minimum CAS Latency Time (tAAmin)
int8_t tRCDminFine; // 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
int8_t tRPminFine; // 37 Fine Offset for Minimum Row Precharge Delay Time (tRPmin)
int8_t tRCminFine; // 38 Fine Offset for Minimum Active to Active/Refresh Delay Time (tRCmin)
uint8_t ReferenceRawCardUsed; // 62 Reference Raw Card Used
uint8_t AddressMappingEdgeConnector; // 63 Address Mapping from Edge Connector to DRAM
uint8_t ThermalHeatSpreaderSolution; // 64 ThermalHeatSpreaderSolution
uint8_t ModuleManufacturerIdCodeLsb; // 117 Module Manufacturer ID Code, Least Significant Byte
uint8_t ModuleManufacturerIdCodeMsb; // 118 Module Manufacturer ID Code, Most Significant Byte
uint8_t ModuleManufacturingLocation; // 119 Module Manufacturing Location
uint8_t ModuleManufacturingDateYear; // 120 Module Manufacturing Date Year
uint8_t ModuleManufacturingDateWW; // 121 Module Manufacturing Date creation work week
uint8_t ModuleSerialNumberA; // 122 Module Serial Number A
uint8_t ModuleSerialNumberB; // 123 Module Serial Number B
uint8_t ModuleSerialNumberC; // 124 Module Serial Number C
uint8_t ModuleSerialNumberD; // 125 Module Serial Number D
uint8_t CRCA; // 126 CRC A
uint8_t CRCB; // 127 CRC B
} DDR3_SPD;
// Configuration for each memory channel/bank
typedef struct {
uint32_t Exists;
DDR3_SPD SpdData;
uint8_t InitClkPiValue[NUM_IVB_MEM_CLK_FREQUENCIES];
} MEM_BANK_CONFIG;
// Memory configuration
typedef struct {
MEM_BANK_CONFIG ChannelABank0;
MEM_BANK_CONFIG ChannelABank1;
MEM_BANK_CONFIG ChannelBBank0;
MEM_BANK_CONFIG ChannelBBank1;
} MEM_CONFIG;
#endif

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/** @file
Copyright (C) 2013, Intel Corporation
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
**/
/** \file peifsp.h
*
*
*/
#include <stdint.h>
#include "fsptypes.h"
#include "fspfv.h"
#include "fspffs.h"
#include "fsphob.h"
#include "fspapi.h"
#include "fspplatform.h"
#include "fspinfoheader.h"

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/**
Copyright (C) 2013, Intel Corporation
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
**/
/***********************************************************************
*
* fsphob.c
*
* HOB infrastructure code.
*
**********************************************************************/
#include <string.h>
#include "fsptypes.h"
#include "fsphob.h"
//
// Pointer to the HOB should be initialized with the output of FSP INIT PARAMS
//
extern volatile void *FspHobListPtr;
//
// Function prototype
//
UINT64
EFIAPI
ReadUnaligned64 (
CONST UINT64 *Buffer
);
/**
Reads a 64-bit value from memory that may be unaligned.
This function returns the 64-bit value pointed to by Buffer. The function
guarantees that the read operation does not produce an alignment fault.
If the Buffer is NULL, then ASSERT().
@param Buffer Pointer to a 64-bit value that may be unaligned.
@return The 64-bit value read from Buffer.
**/
UINT64
EFIAPI
ReadUnaligned64 (
CONST UINT64 *Buffer
)
{
ASSERT (Buffer != NULL);
return *Buffer;
}
/**
Compares two GUIDs.
This function compares Guid1 to Guid2. If the GUIDs are identical then TRUE is returned.
If there are any bit differences in the two GUIDs, then FALSE is returned.
If Guid1 is NULL, then ASSERT().
If Guid2 is NULL, then ASSERT().
@param Guid1 A pointer to a 128 bit GUID.
@param Guid2 A pointer to a 128 bit GUID.
@retval TRUE Guid1 and Guid2 are identical.
@retval FALSE Guid1 and Guid2 are not identical.
**/
BOOLEAN
EFIAPI
CompareGuid (
CONST EFI_GUID *Guid1,
CONST EFI_GUID *Guid2
)
{
UINT64 LowPartOfGuid1;
UINT64 LowPartOfGuid2;
UINT64 HighPartOfGuid1;
UINT64 HighPartOfGuid2;
LowPartOfGuid1 = ReadUnaligned64 ((CONST UINT64*) Guid1);
LowPartOfGuid2 = ReadUnaligned64 ((CONST UINT64*) Guid2);
HighPartOfGuid1 = ReadUnaligned64 ((CONST UINT64*) Guid1 + 1);
HighPartOfGuid2 = ReadUnaligned64 ((CONST UINT64*) Guid2 + 1);
return (BOOLEAN) (LowPartOfGuid1 == LowPartOfGuid2 && HighPartOfGuid1 == HighPartOfGuid2);
}
/**
Returns the pointer to the HOB list.
**/
VOID *
EFIAPI
GetHobList (
VOID
)
{
ASSERT (FspHobListPtr != NULL);
return ((VOID *)FspHobListPtr);
}
/**
Returns the next instance of a HOB type from the starting HOB.
**/
VOID *
EFIAPI
GetNextHob (
UINT16 Type,
CONST VOID *HobStart
)
{
EFI_PEI_HOB_POINTERS Hob;
ASSERT (HobStart != NULL);
Hob.Raw = (UINT8 *) HobStart;
//
// Parse the HOB list until end of list or matching type is found.
//
while (!END_OF_HOB_LIST (Hob)) {
if (Hob.Header->HobType == Type) {
return Hob.Raw;
}
Hob.Raw = GET_NEXT_HOB (Hob);
}
return NULL;
}
/**
Returns the first instance of a HOB type among the whole HOB list.
**/
VOID *
EFIAPI
GetFirstHob (
UINT16 Type
)
{
VOID *HobList;
HobList = GetHobList ();
return GetNextHob (Type, HobList);
}
/**
Returns the next instance of the matched GUID HOB from the starting HOB.
**/
VOID *
EFIAPI
GetNextGuidHob (
CONST EFI_GUID *Guid,
CONST VOID *HobStart
)
{
EFI_PEI_HOB_POINTERS GuidHob;
GuidHob.Raw = (UINT8 *) HobStart;
while ((GuidHob.Raw = GetNextHob (EFI_HOB_TYPE_GUID_EXTENSION, GuidHob.Raw)) != NULL) {
if (CompareGuid (Guid, &GuidHob.Guid->Name)) {
break;
}
GuidHob.Raw = GET_NEXT_HOB (GuidHob);
}
return GuidHob.Raw;
}
/**
Returns the first instance of the matched GUID HOB among the whole HOB list.
**/
VOID *
EFIAPI
GetFirstGuidHob (
CONST EFI_GUID *Guid
)
{
VOID *HobList;
HobList = GetHobList ();
return GetNextGuidHob (Guid, HobList);
}

View File

@ -0,0 +1,596 @@
/** @file
Boot Setting File for Platform Configuration.
Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
This file is automatically generated. Please do NOT modify !!!
**/
GlobalDataDef
SKUID = 0, "DEFAULT"
EndGlobalData
StructDef
Find "DNVUPD_T"
$gPlatformFspPkgTokenSpaceGuid_Revision 1 bytes $_DEFAULT_ = 0x01
Skip 55 bytes
$gHarrisonvilleFspPkgTokenSpaceGuid_PcdFsptPort80RouteDisable 1 bytes $_DEFAULT_ = 0x01
Find "DNVUPD_M"
$gPlatformFspPkgTokenSpaceGuid_Revision 1 bytes $_DEFAULT_ = 0x01
Skip 31 bytes
$gHarrisonvilleFspPkgTokenSpaceGuid_StackBase 4 bytes $_DEFAULT_ = 0xFEFB0000
$gHarrisonvilleFspPkgTokenSpaceGuid_StackSize 4 bytes $_DEFAULT_ = 0x4FF00
$gHarrisonvilleFspPkgTokenSpaceGuid_BootLoaderTolumSize 4 bytes $_DEFAULT_ = 0x00000000
$gHarrisonvilleFspPkgTokenSpaceGuid_Bootmode 4 bytes $_DEFAULT_ = 0x00000000
Skip 8 bytes
$gHarrisonvilleFspPkgTokenSpaceGuid_PcdSmmTsegSize 1 bytes $_DEFAULT_ = 0x02
$gHarrisonvilleFspPkgTokenSpaceGuid_PcdFspDebugPrintErrorLevel 1 bytes $_DEFAULT_ = 0x02
$gHarrisonvilleFspPkgTokenSpaceGuid_PcdSpdSmbusAddress_0_0 1 bytes $_DEFAULT_ = 0xA0
$gHarrisonvilleFspPkgTokenSpaceGuid_PcdSpdSmbusAddress_0_1 1 bytes $_DEFAULT_ = 0xA2
$gHarrisonvilleFspPkgTokenSpaceGuid_PcdSpdSmbusAddress_1_0 1 bytes $_DEFAULT_ = 0xA4
$gHarrisonvilleFspPkgTokenSpaceGuid_PcdSpdSmbusAddress_1_1 1 bytes $_DEFAULT_ = 0xA6
$gHarrisonvilleFspPkgTokenSpaceGuid_PcdMrcRmtSupport 1 bytes $_DEFAULT_ = 0
$gHarrisonvilleFspPkgTokenSpaceGuid_PcdMrcRmtCpgcExpLoopCntValue 1 bytes $_DEFAULT_ = 12
$gHarrisonvilleFspPkgTokenSpaceGuid_PcdMrcRmtCpgcNumBursts 1 bytes $_DEFAULT_ = 6
$gHarrisonvilleFspPkgTokenSpaceGuid_PcdMemoryPreservation 1 bytes $_DEFAULT_ = 0
$gHarrisonvilleFspPkgTokenSpaceGuid_PcdFastBoot 1 bytes $_DEFAULT_ = 1
$gHarrisonvilleFspPkgTokenSpaceGuid_PcdEccSupport 1 bytes $_DEFAULT_ = 1
$gHarrisonvilleFspPkgTokenSpaceGuid_PcdHsuartDevice 1 bytes $_DEFAULT_ = 0
$gHarrisonvilleFspPkgTokenSpaceGuid_PcdMemoryDown 1 bytes $_DEFAULT_ = 0
Skip 4 bytes
$gHarrisonvilleFspPkgTokenSpaceGuid_PcdEnableSATA0 1 bytes $_DEFAULT_ = 1
$gHarrisonvilleFspPkgTokenSpaceGuid_PcdEnableSATA1 1 bytes $_DEFAULT_ = 1
$gHarrisonvilleFspPkgTokenSpaceGuid_PcdEnableIQAT 1 bytes $_DEFAULT_ = 1
$gHarrisonvilleFspPkgTokenSpaceGuid_PcdSmbusSpdWriteDisable 1 bytes $_DEFAULT_ = 0
$gHarrisonvilleFspPkgTokenSpaceGuid_PcdEnableMeShutdown 1 bytes $_DEFAULT_ = 0
$gHarrisonvilleFspPkgTokenSpaceGuid_PcdEnableXhci 1 bytes $_DEFAULT_ = 1
$gHarrisonvilleFspPkgTokenSpaceGuid_PcdDdrFreq 1 bytes $_DEFAULT_ = 6
$gHarrisonvilleFspPkgTokenSpaceGuid_PcdMmioSize 1 bytes $_DEFAULT_ = 0
$gHarrisonvilleFspPkgTokenSpaceGuid_PcdMeHeciCommunication 1 bytes $_DEFAULT_ = 1
$gHarrisonvilleFspPkgTokenSpaceGuid_PcdHsioLanesNumber 1 bytes $_DEFAULT_ = 20
Skip 4 bytes
$gHarrisonvilleFspPkgTokenSpaceGuid_PcdCustomerRevision 32 bytes $_DEFAULT_ = 0x76,0x65,0x72,0x73,0x69,0x6F,0x6E,0x20,0x78,0x78,0x78,0x00
$gHarrisonvilleFspPkgTokenSpaceGuid_PcdHalfWidthEnable 1 bytes $_DEFAULT_ = 0
$gHarrisonvilleFspPkgTokenSpaceGuid_PcdTclIdle 1 bytes $_DEFAULT_ = 1
$gHarrisonvilleFspPkgTokenSpaceGuid_PcdInterleaveMode 1 bytes $_DEFAULT_ = 3
$gHarrisonvilleFspPkgTokenSpaceGuid_PcdMemoryThermalThrottling 1 bytes $_DEFAULT_ = 0
$gHarrisonvilleFspPkgTokenSpaceGuid_PcdSkipMemoryTest 1 bytes $_DEFAULT_ = 0
Skip 4 bytes
$gHarrisonvilleFspPkgTokenSpaceGuid_PcdUsb2Port1Pin 1 bytes $_DEFAULT_ = 8
$gHarrisonvilleFspPkgTokenSpaceGuid_PcdUsb2Port2Pin 1 bytes $_DEFAULT_ = 8
$gHarrisonvilleFspPkgTokenSpaceGuid_PcdUsb2Port3Pin 1 bytes $_DEFAULT_ = 8
$gHarrisonvilleFspPkgTokenSpaceGuid_PcdUsb2Port4Pin 1 bytes $_DEFAULT_ = 8
$gHarrisonvilleFspPkgTokenSpaceGuid_PcdUsb3Port1Pin 1 bytes $_DEFAULT_ = 8
$gHarrisonvilleFspPkgTokenSpaceGuid_PcdUsb3Port2Pin 1 bytes $_DEFAULT_ = 8
$gHarrisonvilleFspPkgTokenSpaceGuid_PcdUsb3Port3Pin 1 bytes $_DEFAULT_ = 8
$gHarrisonvilleFspPkgTokenSpaceGuid_PcdUsb3Port4Pin 1 bytes $_DEFAULT_ = 8
$gHarrisonvilleFspPkgTokenSpaceGuid_PcdIOxAPIC0_199 1 bytes $_DEFAULT_ = 0
$gHarrisonvilleFspPkgTokenSpaceGuid_PcdDmapX16 1 bytes $_DEFAULT_ = 0x0
Find "DNVUPD_S"
$gPlatformFspPkgTokenSpaceGuid_Revision 1 bytes $_DEFAULT_ = 0x01
Skip 23 bytes
$gHarrisonvilleFspPkgTokenSpaceGuid_PcdBifurcationPcie0 1 bytes $_DEFAULT_ = 4
$gHarrisonvilleFspPkgTokenSpaceGuid_PcdBifurcationPcie1 1 bytes $_DEFAULT_ = 3
$gHarrisonvilleFspPkgTokenSpaceGuid_PcdActiveCoreCount 1 bytes $_DEFAULT_ = 0
Skip 8 bytes
$gHarrisonvilleFspPkgTokenSpaceGuid_PcdEnablePcie0 1 bytes $_DEFAULT_ = 1
$gHarrisonvilleFspPkgTokenSpaceGuid_PcdEnablePcie1 1 bytes $_DEFAULT_ = 1
$gHarrisonvilleFspPkgTokenSpaceGuid_PcdEnableEmmc 1 bytes $_DEFAULT_ = 1
$gHarrisonvilleFspPkgTokenSpaceGuid_PcdEnableGbE 1 bytes $_DEFAULT_ = 1
Skip 8 bytes
$gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort0DeEmphasis 1 bytes $_DEFAULT_ = 0
$gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort1DeEmphasis 1 bytes $_DEFAULT_ = 0
$gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort2DeEmphasis 1 bytes $_DEFAULT_ = 0
$gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort3DeEmphasis 1 bytes $_DEFAULT_ = 0
$gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort4DeEmphasis 1 bytes $_DEFAULT_ = 0
$gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort5DeEmphasis 1 bytes $_DEFAULT_ = 0
$gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort6DeEmphasis 1 bytes $_DEFAULT_ = 0
$gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort7DeEmphasis 1 bytes $_DEFAULT_ = 0
Skip 5 bytes
$gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort0LinkSpeed 1 bytes $_DEFAULT_ = 0x03
$gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort1LinkSpeed 1 bytes $_DEFAULT_ = 0x03
$gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort2LinkSpeed 1 bytes $_DEFAULT_ = 0x03
$gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort3LinkSpeed 1 bytes $_DEFAULT_ = 0x03
$gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort4LinkSpeed 1 bytes $_DEFAULT_ = 0x03
$gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort5LinkSpeed 1 bytes $_DEFAULT_ = 0x03
$gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort6LinkSpeed 1 bytes $_DEFAULT_ = 0x03
$gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort7LinkSpeed 1 bytes $_DEFAULT_ = 0x03
$gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort0Aspm 1 bytes $_DEFAULT_ = 0x02
$gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort1Aspm 1 bytes $_DEFAULT_ = 0x02
$gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort2Aspm 1 bytes $_DEFAULT_ = 0x02
$gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort3Aspm 1 bytes $_DEFAULT_ = 0x02
$gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort4Aspm 1 bytes $_DEFAULT_ = 0x02
$gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort5Aspm 1 bytes $_DEFAULT_ = 0x02
$gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort6Aspm 1 bytes $_DEFAULT_ = 0x02
$gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort7Aspm 1 bytes $_DEFAULT_ = 0x02
EndStruct
List &EN_DIS
Selection 0x1 , "Enabled"
Selection 0x0 , "Disabled"
EndList
List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort3Aspm
Selection 0 , "Disabled"
Selection 2 , "L1"
EndList
List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort5Aspm
Selection 0 , "Disabled"
Selection 2 , "L1"
EndList
List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdBifurcationPcie1
Selection 0 , "X2X2X2X2"
Selection 1 , "X2X2X4"
Selection 2 , "X4X2X2"
Selection 3 , "X4X4"
Selection 4 , "X8"
EndList
List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdBifurcationPcie0
Selection 0 , "X2X2X2X2"
Selection 1 , "X2X2X4"
Selection 2 , "X4X2X2"
Selection 3 , "X4X4"
Selection 4 , "X8"
EndList
List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdHsioLanesNumber
Selection 6 , "6"
Selection 8 , "8"
Selection 10 , "10"
Selection 12 , "12"
Selection 20 , "20"
EndList
List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdActiveCoreCount
Selection 0 , "ALL"
Selection 1 , "1"
Selection 2 , "2"
Selection 3 , "3"
Selection 4 , "4"
Selection 5 , "5"
Selection 6 , "6"
Selection 7 , "7"
Selection 8 , "8"
Selection 9 , "9"
Selection 10 , "10"
Selection 11 , "11"
Selection 12 , "12"
Selection 13 , "13"
Selection 14 , "14"
Selection 15 , "15"
EndList
List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort1Aspm
Selection 0 , "Disabled"
Selection 2 , "L1"
EndList
List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort0Aspm
Selection 0 , "Disabled"
Selection 2 , "L1"
EndList
List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdMrcRmtCpgcExpLoopCntValue
Selection 1 , "1"
Selection 2 , "2"
Selection 3 , "3"
Selection 4 , "4"
Selection 5 , "5"
Selection 6 , "6"
Selection 7 , "7"
Selection 8 , "8"
Selection 9 , "9"
Selection 10 , "10"
Selection 11 , "11"
Selection 12 , "12"
Selection 13 , "13"
Selection 14 , "14"
Selection 15 , "15"
EndList
List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdMmioSize
Selection 0 , "2048M"
Selection 1 , "1024M"
Selection 2 , "3072M"
EndList
List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort2LinkSpeed
Selection 1 , "GEN1"
Selection 2 , "GEN2"
Selection 3 , "GEN3"
EndList
List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdUsb2Port4Pin
Selection 0 , "OC Pin 0"
Selection 8 , "No pin mapped"
EndList
List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort4DeEmphasis
Selection 0 , "6dB"
Selection 1 , "3.5dB"
EndList
List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdSmmTsegSize
Selection 2 , "2 MB"
Selection 4 , "4 MB"
Selection 8 , "8 MB"
Selection 16 , "16 MB"
EndList
List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort3LinkSpeed
Selection 1 , "GEN1"
Selection 2 , "GEN2"
Selection 3 , "GEN3"
EndList
List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort3DeEmphasis
Selection 0 , "6dB"
Selection 1 , "3.5dB"
EndList
List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort2Aspm
Selection 0 , "Disabled"
Selection 2 , "L1"
EndList
List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort4Aspm
Selection 0 , "Disabled"
Selection 2 , "L1"
EndList
List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdUsb2Port1Pin
Selection 0 , "OC Pin 0"
Selection 8 , "No pin mapped"
EndList
List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort0DeEmphasis
Selection 0 , "6dB"
Selection 1 , "3.5dB"
EndList
List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort6LinkSpeed
Selection 1 , "GEN1"
Selection 2 , "GEN2"
Selection 3 , "GEN3"
EndList
List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort2DeEmphasis
Selection 0 , "6dB"
Selection 1 , "3.5dB"
EndList
List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort1DeEmphasis
Selection 0 , "6dB"
Selection 1 , "3.5dB"
EndList
List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdDdrFreq
Selection 15 , "Auto"
Selection 3 , "1600"
Selection 4 , "1866"
Selection 5 , "2133"
Selection 6 , "2400"
EndList
List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdMrcRmtCpgcNumBursts
Selection 1 , "1"
Selection 2 , "2"
Selection 3 , "3"
Selection 4 , "4"
Selection 5 , "5"
Selection 6 , "6"
Selection 7 , "7"
Selection 8 , "8"
Selection 9 , "9"
Selection 10 , "10"
Selection 11 , "11"
Selection 12 , "12"
Selection 13 , "13"
Selection 14 , "14"
Selection 15 , "15"
EndList
List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort4LinkSpeed
Selection 1 , "GEN1"
Selection 2 , "GEN2"
Selection 3 , "GEN3"
EndList
List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort6Aspm
Selection 0 , "Disabled"
Selection 2 , "L1"
EndList
List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdUsb3Port2Pin
Selection 0 , "OC Pin 0"
Selection 8 , "No pin mapped"
EndList
List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdFsptPort80RouteDisable
Selection 0 , "VPD-Style"
Selection 1 , "Enable Port80 Output[Default]"
Selection 2 , "Disable Port80 Output"
EndList
List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdInterleaveMode
Selection 0 , "DISABLED"
Selection 1 , "MODE0"
Selection 2 , "MODE1"
Selection 3 , "MODE2"
EndList
List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdFspDebugPrintErrorLevel
Selection 0 , "NO DEBUG"
Selection 1 , "MIN DEBUG"
Selection 2 , "MED DEBUG"
Selection 3 , "VERBOSE DEBUG"
EndList
List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort7LinkSpeed
Selection 1 , "GEN1"
Selection 2 , "GEN2"
Selection 3 , "GEN3"
EndList
List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdUsb3Port4Pin
Selection 0 , "OC Pin 0"
Selection 8 , "No pin mapped"
EndList
List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdUsb3Port1Pin
Selection 0 , "OC Pin 0"
Selection 8 , "No pin mapped"
EndList
List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort7Aspm
Selection 0 , "Disabled"
Selection 2 , "L1"
EndList
List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdUsb2Port2Pin
Selection 0 , "OC Pin 0"
Selection 8 , "No pin mapped"
EndList
List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdUsb3Port3Pin
Selection 0 , "OC Pin 0"
Selection 8 , "No pin mapped"
EndList
List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort5DeEmphasis
Selection 0 , "6dB"
Selection 1 , "3.5dB"
EndList
List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort7DeEmphasis
Selection 0 , "6dB"
Selection 1 , "3.5dB"
EndList
List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort5LinkSpeed
Selection 1 , "GEN1"
Selection 2 , "GEN2"
Selection 3 , "GEN3"
EndList
List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdSmbusSpdWriteDisable
Selection 0 , "Force Enable"
Selection 1 , "Force Disable"
EndList
List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort6DeEmphasis
Selection 0 , "6dB"
Selection 1 , "3.5dB"
EndList
List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort1LinkSpeed
Selection 1 , "GEN1"
Selection 2 , "GEN2"
Selection 3 , "GEN3"
EndList
List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdUsb2Port3Pin
Selection 0 , "OC Pin 0"
Selection 8 , "No pin mapped"
EndList
List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdEnableGbE
Selection 0 , "Disable LAN 0 & LAN 1"
Selection 1 , "Enable LAN 0 & LAN 1"
Selection 2 , "Disable LAN 1 only"
EndList
List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdHsuartDevice
Selection 0 , "HSUART0"
Selection 1 , "HSUART1"
Selection 2 , "HSUART2"
EndList
List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort0LinkSpeed
Selection 1 , "GEN1"
Selection 2 , "GEN2"
Selection 3 , "GEN3"
EndList
BeginInfoBlock
PPVer "0.1"
Description "Harrisonville platform"
EndInfoBlock
Page "SoC"
Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdBifurcationPcie0, "PCIe Controller 0 Bifurcation", &gHarrisonvilleFspPkgTokenSpaceGuid_PcdBifurcationPcie0,
Help "Configure PCI Express controller 0 bifurcation."
Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdBifurcationPcie1, "PCIe Controller 1 Bifurcation", &gHarrisonvilleFspPkgTokenSpaceGuid_PcdBifurcationPcie1,
Help "Configure PCI Express controller 1 bifurcation."
Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdActiveCoreCount, "Active Core Count", &gHarrisonvilleFspPkgTokenSpaceGuid_PcdActiveCoreCount,
Help "Select # of Active Cores (Default: 0, 0:ALL, 1..15 = 1..15 Cores)"
Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdEnablePcie0, "PCIe Controller 0", &EN_DIS,
Help "Enable / Disable PCI Express controller 0"
Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdEnablePcie1, "PCIe Controller 1", &EN_DIS,
Help "Enable / Disable PCI Express controller 1"
Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdEnableEmmc, "Embedded Multi-Media Controller (eMMC)", &EN_DIS,
Help "Enable / Disable Embedded Multi-Media controller"
Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdEnableGbE, "LAN Controllers", &gHarrisonvilleFspPkgTokenSpaceGuid_PcdEnableGbE,
Help "Enable / Disable LAN controllers, refer to FSP Integration Guide for details."
Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort0DeEmphasis, "PCIe Root Port 0 DeEmphasis", &gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort0DeEmphasis,
Help "Desired DeEmphasis level for PCIE root port"
Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort1DeEmphasis, "PCIe Root Port 1 DeEmphasis", &gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort1DeEmphasis,
Help "Desired DeEmphasis level for PCIE root port"
Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort2DeEmphasis, "PCIe Root Port 2 DeEmphasis", &gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort2DeEmphasis,
Help "Desired DeEmphasis level for PCIE root port"
Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort3DeEmphasis, "PCIe Root Port 3 DeEmphasis", &gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort3DeEmphasis,
Help "Desired DeEmphasis level for PCIE root port"
Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort4DeEmphasis, "PCIe Root Port 4 DeEmphasis", &gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort4DeEmphasis,
Help "Desired DeEmphasis level for PCIE root port"
Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort5DeEmphasis, "PCIe Root Port 5 DeEmphasis", &gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort5DeEmphasis,
Help "Desired DeEmphasis level for PCIE root port"
Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort6DeEmphasis, "PCIe Root Port 6 DeEmphasis", &gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort6DeEmphasis,
Help "Desired DeEmphasis level for PCIE root port"
Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort7DeEmphasis, "PCIe Root Port 7 DeEmphasis", &gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort7DeEmphasis,
Help "Desired DeEmphasis level for PCIE root port"
Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdFsptPort80RouteDisable, "Disable Port80 output in FSP-T", &gHarrisonvilleFspPkgTokenSpaceGuid_PcdFsptPort80RouteDisable,
Help "Select Port80 Control in FSP-T (0:VPD-Style, 1:Enable Port80 Output, 2:Disable Port80 Output, refer to FSP Integration Guide for details"
Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort0LinkSpeed, "PCIe Root Port 0 Link Speed", &gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort0LinkSpeed,
Help "Upper limit on link operational speed for PCI Express RootPort"
Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort1LinkSpeed, "PCIe Root Port 1 Link Speed", &gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort1LinkSpeed,
Help "Upper limit on link operational speed for PCI Express RootPort"
Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort2LinkSpeed, "PCIe Root Port 2 Link Speed", &gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort2LinkSpeed,
Help "Upper limit on link operational speed for PCI Express RootPort"
Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort3LinkSpeed, "PCIe Root Port 3 Link Speed", &gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort3LinkSpeed,
Help "Upper limit on link operational speed for PCI Express RootPort"
Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort4LinkSpeed, "PCIe Root Port 4 Link Speed", &gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort4LinkSpeed,
Help "Upper limit on link operational speed for PCI Express RootPort"
Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort5LinkSpeed, "PCIe Root Port 5 Link Speed", &gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort5LinkSpeed,
Help "Upper limit on link operational speed for PCI Express RootPort"
Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort6LinkSpeed, "PCIe Root Port 6 Link Speed", &gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort6LinkSpeed,
Help "Upper limit on link operational speed for PCI Express RootPort"
Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort7LinkSpeed, "PCIe Root Port 7 Link Speed", &gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort7LinkSpeed,
Help "Upper limit on link operational speed for PCI Express RootPort"
Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort0Aspm, "PCIe Root Port 0 ASPM", &gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort0Aspm,
Help "Enable PCI Express Active State Power Management settings"
Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort1Aspm, "PCIe Root Port 1 ASPM", &gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort1Aspm,
Help "Enable PCI Express Active State Power Management settings"
Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort2Aspm, "PCIe Root Port 2 ASPM", &gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort2Aspm,
Help "Enable PCI Express Active State Power Management settings"
Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort3Aspm, "PCIe Root Port 3 ASPM", &gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort3Aspm,
Help "Enable PCI Express Active State Power Management settings"
Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort4Aspm, "PCIe Root Port 4 ASPM", &gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort4Aspm,
Help "Enable PCI Express Active State Power Management settings"
Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort5Aspm, "PCIe Root Port 5 ASPM", &gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort5Aspm,
Help "Enable PCI Express Active State Power Management settings"
Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort6Aspm, "PCIe Root Port 6 ASPM", &gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort6Aspm,
Help "Enable PCI Express Active State Power Management settings"
Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort7Aspm, "PCIe Root Port 7 ASPM", &gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort7Aspm,
Help "Enable PCI Express Active State Power Management settings"
EndPage
Page "Platform Specific"
EditText $gHarrisonvilleFspPkgTokenSpaceGuid_PcdCustomerRevision, "Customer Revision",
Help "The Customer can set this revision string for their own purpose."
Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdHalfWidthEnable, "32-Bit bus mode", &EN_DIS,
Help "Enable/Disable 32-Bit bus memory mode."
Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdTclIdle, "TCL Performance", &EN_DIS,
Help "Enable/Disable Tcl timing for performance."
Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdInterleaveMode, "Interleave Mode", &gHarrisonvilleFspPkgTokenSpaceGuid_PcdInterleaveMode,
Help "Select Interleave Mode"
Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdMemoryThermalThrottling, "Memory Thermal Throttling", &EN_DIS,
Help "Enable/disable Memory Thermal Throttling management mode"
Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdSkipMemoryTest, "Memory Test", &EN_DIS,
Help "Enable / Disable Memory Test, refer to FSP Integration Guide for details."
Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdUsb2Port1Pin, "USB2 Port 1 OC Pin", &gHarrisonvilleFspPkgTokenSpaceGuid_PcdUsb2Port1Pin,
Help "Map selected OC pin to the port"
Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdUsb2Port2Pin, "USB2 Port 2 OC Pin", &gHarrisonvilleFspPkgTokenSpaceGuid_PcdUsb2Port2Pin,
Help "Map selected OC pin to the port"
Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdUsb2Port3Pin, "USB2 Port 3 OC Pin", &gHarrisonvilleFspPkgTokenSpaceGuid_PcdUsb2Port3Pin,
Help "Map selected OC pin to the port"
Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdUsb2Port4Pin, "USB2 Port 4 OC Pin", &gHarrisonvilleFspPkgTokenSpaceGuid_PcdUsb2Port4Pin,
Help "Map selected OC pin to the port"
Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdUsb3Port1Pin, "USB3 Port 1 OC Pin", &gHarrisonvilleFspPkgTokenSpaceGuid_PcdUsb3Port1Pin,
Help "Map selected OC pin to the port"
Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdUsb3Port2Pin, "USB3 Port 2 OC Pin", &gHarrisonvilleFspPkgTokenSpaceGuid_PcdUsb3Port2Pin,
Help "Map selected OC pin to the port"
Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdUsb3Port3Pin, "USB3 Port 3 OC Pin", &gHarrisonvilleFspPkgTokenSpaceGuid_PcdUsb3Port3Pin,
Help "Map selected OC pin to the port"
Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdUsb3Port4Pin, "USB3 Port 4 OC Pin", &gHarrisonvilleFspPkgTokenSpaceGuid_PcdUsb3Port4Pin,
Help "Map selected OC pin to the port"
Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdIOxAPIC0_199, "IOxAPIC 0-199", &EN_DIS,
Help "Enable/disable IOxAPIC 24-119 entries"
Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdDmapX16, "DMAP_X16", &EN_DIS,
Help "Enable/Disable DMAP_X16 dynamic MRC field indicating memory device width is x16 or not"
EndPage
Page "MRC & Early SoC"
Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdSmmTsegSize, "Tseg Size", &gHarrisonvilleFspPkgTokenSpaceGuid_PcdSmmTsegSize,
Help "Size of SMRAM memory reserved."
Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdFspDebugPrintErrorLevel, "FSP Debug Print Level", &gHarrisonvilleFspPkgTokenSpaceGuid_PcdFspDebugPrintErrorLevel,
Help "Select the FSP debug message print level."
EditNum $gHarrisonvilleFspPkgTokenSpaceGuid_PcdSpdSmbusAddress_0_0, "Channel 0 DIMM 0 SPD SMBus Address", HEX,
Help "SPD SMBus Address of each DIMM slot."
"Valid range: 0x00 ~ 0xFF"
EditNum $gHarrisonvilleFspPkgTokenSpaceGuid_PcdSpdSmbusAddress_0_1, "Channel 0 DIMM 1 SPD SMBus Address", HEX,
Help "SPD SMBus Address of each DIMM slot."
"Valid range: 0x00 ~ 0xFF"
EditNum $gHarrisonvilleFspPkgTokenSpaceGuid_PcdSpdSmbusAddress_1_0, "Channel 1 DIMM 0 SPD SMBus Address", HEX,
Help "SPD SMBus Address of each DIMM slot."
"Valid range: 0x00 ~ 0xFF"
EditNum $gHarrisonvilleFspPkgTokenSpaceGuid_PcdSpdSmbusAddress_1_1, "Channel 1 DIMM 1 SPD SMBus Address", HEX,
Help "SPD SMBus Address of each DIMM slot."
"Valid range: 0x00 ~ 0xFF"
Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdMrcRmtSupport, "Enable Rank Margin Tool", &EN_DIS,
Help "Enable/disable Rank Margin Tool."
Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdMrcRmtCpgcExpLoopCntValue, "RMT CPGC exp_loop_cnt", &gHarrisonvilleFspPkgTokenSpaceGuid_PcdMrcRmtCpgcExpLoopCntValue,
Help "Set the CPGC exp_loop_cnt field for RMT execution 2^(exp_loop_cnt -1)."
Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdMrcRmtCpgcNumBursts, "RMT CPGC num_bursts", &gHarrisonvilleFspPkgTokenSpaceGuid_PcdMrcRmtCpgcNumBursts,
Help "Set the CPGC num_bursts field for RMT execution 2^(num_bursts -1)."
Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdMemoryPreservation, "Preserve Memory Across Reset", &EN_DIS,
Help "Enable/disable memory preservation across reset."
Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdFastBoot, "Fast Boot", &EN_DIS,
Help "Enable/disable Fast Boot function. Once enabled, all following boots will use the presaved MRC data to improve the boot performance."
Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdEccSupport, "ECC Support", &EN_DIS,
Help "Enable/disable ECC Support."
Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdHsuartDevice, "HSUART Device", &gHarrisonvilleFspPkgTokenSpaceGuid_PcdHsuartDevice,
Help "Select the PCI High Speed UART Device for Serial Port."
Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdMemoryDown, "Memory Down", &EN_DIS,
Help "Enable/disable Memory Down function."
Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdEnableSATA0, "SATA Controller 0", &EN_DIS,
Help "Enable/disable SATA Controller 0."
Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdEnableSATA1, "SATA Controller 1", &EN_DIS,
Help "Enable/disable SATA Controller 1."
Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdEnableIQAT, "Intel Quick Assist Technology", &EN_DIS,
Help "Enable/disable Intel Quick Assist Technology."
Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdSmbusSpdWriteDisable, "SPD Write Disable", &gHarrisonvilleFspPkgTokenSpaceGuid_PcdSmbusSpdWriteDisable,
Help "Select SMBus SPD Write Enable State (Default: 0 = [FORCE_ENABLE], 1 = [FORCE_DISABLE])"
Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdEnableMeShutdown, "ME_SHUTDOWN Message", &EN_DIS,
Help "Enable/Disable sending ME_SHUTDOWN message to ME, refer to FSP Integration Guide for details."
Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdEnableXhci, "XHCI Controller", &EN_DIS,
Help "Enable / Disable XHCI controller"
Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdDdrFreq, "Memory Frequency", &gHarrisonvilleFspPkgTokenSpaceGuid_PcdDdrFreq,
Help "Set DDR Memory Frequency, refer to FSP Integration Guide for details."
Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdMmioSize, "MMIO Size", &gHarrisonvilleFspPkgTokenSpaceGuid_PcdMmioSize,
Help "Set memory mapped IO space size"
Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdMeHeciCommunication, "ME HECI Communication", &EN_DIS,
Help "Enable/Disable ME HECI communication"
Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdHsioLanesNumber, "HSIO Lanes Number", &gHarrisonvilleFspPkgTokenSpaceGuid_PcdHsioLanesNumber,
Help "HSIO lanes number of SKU"
EndPage

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/** @file
Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
This file is automatically generated. Please do NOT modify !!!
**/
#ifndef __FSPUPD_H__
#define __FSPUPD_H__
#include <FspEas.h>
#pragma pack(1)
#define FSPT_UPD_SIGNATURE 0x545F445055564E44 /* 'DNVUPD_T' */
#define FSPM_UPD_SIGNATURE 0x4D5F445055564E44 /* 'DNVUPD_M' */
#define FSPS_UPD_SIGNATURE 0x535F445055564E44 /* 'DNVUPD_S' */
#pragma pack()
#endif

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@ -0,0 +1,674 @@
/** @file
Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
This file is automatically generated. Please do NOT modify !!!
**/
#ifndef __FSPMUPD_H__
#define __FSPMUPD_H__
#include <FspUpd.h>
#pragma pack(1)
#define MAX_CH 2 /* Maximum Number of Memory Channels */
#define MAX_DIMM 2 /* Maximum Number of DIMMs PER Memory Channel */
#define MAX_SPD_BYTES 512 /* Maximum Number of SPD bytes */
/*
* Memory Down structures.
*/
typedef enum {
STATE_MEMORY_SLOT = 0, /* No memory down and a physical memory slot. */
STATE_MEMORY_DOWN = 1, /* Memory down and not a physical memory slot. */
} MemorySlotState;
typedef struct {
MemorySlotState SlotState[MAX_CH][MAX_DIMM]; /* Memory Down state of each DIMM in each Channel */
UINT16 SpdDataLen; /* Length in Bytes of a single DIMM's SPD Data */
UINT8 *SpdDataPtr[MAX_CH][MAX_DIMM]; /* Pointer to SPD Data for each DIMM in each Channel */
} MEMORY_DOWN_CONFIG;
/*
* SMBIOS Memory Info structures.
*/
typedef struct {
UINT8 DimmId;
UINT32 SizeInMb;
UINT16 MfgId;
UINT8 ModulePartNum[20];/* Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes */
} DIMM_INFO;
typedef struct {
UINT8 ChannelId;
UINT8 DimmCount;
DIMM_INFO DimmInfo[MAX_DIMM];
} CHANNEL_INFO;
typedef struct {
UINT8 Revision;
UINT16 DataWidth;
/** As defined in SMBIOS 3.0 spec
Section 7.18.2 and Table 75
**/
UINT8 MemoryType;
UINT16 MemoryFrequencyInMHz;
/** As defined in SMBIOS 3.0 spec
Section 7.17.3 and Table 72
**/
UINT8 ErrorCorrectionType;
UINT8 ChannelCount;
CHANNEL_INFO ChannelInfo[MAX_CH];
} FSP_SMBIOS_MEMORY_INFO;
/*
* GBE PCD supported states.
*/
typedef enum {
BL_GBE0_GBE1_DISABLED,
BL_GBE0_GBE1_ENABLED,
BL_GBE1_DISABLED,
} BL_GBE_PCD_STATE;
/*
* FIA MUX configuration structures.
*/
#define BL_ME_FIA_MUX_LANE_NUM_MAX 20
#define BL_ME_FIA_MUX_LANE_NUM_MIN 1
#define BL_ME_FIA_MUX_LANE_MUX_SEL_WIDTH 2
#define BL_ME_FIA_MUX_LANE_MUX_SEL_MASK 0x3
#define BL_ME_FIA_MUX_LANE_XHCI_ONLY 0xFF00000000
typedef enum {
BL_FIA_LANE00 = 0,
BL_FIA_LANE01,
BL_FIA_LANE02,
BL_FIA_LANE03,
BL_FIA_LANE04,
BL_FIA_LANE05,
BL_FIA_LANE06,
BL_FIA_LANE07,
BL_FIA_LANE08,
BL_FIA_LANE09,
BL_FIA_LANE10,
BL_FIA_LANE11,
BL_FIA_LANE12,
BL_FIA_LANE13,
BL_FIA_LANE14,
BL_FIA_LANE15,
BL_FIA_LANE16,
BL_FIA_LANE17,
BL_FIA_LANE18,
BL_FIA_LANE19,
} BL_ME_FIA_MUX_LANE_ORDER;
#define BL_ME_FIA_MUX_LANE_SATA0_BEGING BL_FIA_LANE04
#define BL_ME_FIA_MUX_LANE_SATA1_BEGING BL_FIA_LANE12
#define BL_FIA_LANE_CONFIG(Config, Lane) ( (UINT64) ( (UINT64)(Config) << ( (UINT64)(Lane) * (BL_ME_FIA_MUX_LANE_MUX_SEL_WIDTH))))
typedef union _BL_ME_FIA_MUX_CONFIG {
UINT64 MeFiaMuxLaneConfig;
struct {
UINT64 Lane00MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE
UINT64 Lane01MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE
UINT64 Lane02MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE
UINT64 Lane03MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE
UINT64 Lane04MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE or SATA
UINT64 Lane05MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE or SATA
UINT64 Lane06MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE or SATA
UINT64 Lane07MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE or SATA
UINT64 Lane08MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE or SATA
UINT64 Lane09MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE or SATA
UINT64 Lane10MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE or SATA
UINT64 Lane11MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE or SATA
UINT64 Lane12MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE or SATA
UINT64 Lane13MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE or SATA
UINT64 Lane14MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE or SATA
UINT64 Lane15MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE or SATA
UINT64 Lane16MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or XHCI or SATA
UINT64 Lane17MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or XHCI or SATA
UINT64 Lane18MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or XHCI or SATA
UINT64 Lane19MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or XHCI or SATA
UINT64 Reserved : 24;
} BL_MeFiaMuxLaneMuxSel;
} BL_ME_FIA_MUX_CONFIG;
typedef enum {
BL_ME_FIA_MUX_LANE_DISCONNECTED,
BL_ME_FIA_MUX_LANE_PCIE,
BL_ME_FIA_MUX_LANE_SATA,
BL_ME_FIA_MUX_LANE_XHCI,
} BL_ME_FIA_MUX_LANE_CONFIG;
#define BL_ME_FIA_SATA_LANE_SEL_WIDTH 2
#define BL_ME_FIA_SATA_LANE_XHCI_ONLY 0x55000000
typedef enum {
BL_FIA_SATA_LANE04 = 0,
BL_FIA_SATA_LANE05,
BL_FIA_SATA_LANE06,
BL_FIA_SATA_LANE07,
BL_FIA_SATA_LANE08,
BL_FIA_SATA_LANE09,
BL_FIA_SATA_LANE10,
BL_FIA_SATA_LANE11,
BL_FIA_SATA_LANE12,
BL_FIA_SATA_LANE13,
BL_FIA_SATA_LANE14,
BL_FIA_SATA_LANE15,
BL_FIA_SATA_LANE16,
BL_FIA_SATA_LANE17,
BL_FIA_SATA_LANE18,
BL_FIA_SATA_LANE19
} BL_ME_FIA_SATA_LANE_ORDER;
#define BL_FIA_SATA_LANE_CONFIG(Config, Lane) ( (UINT32) ( (UINT32)(Config) << ( (UINT32)(Lane) * (BL_ME_FIA_SATA_LANE_SEL_WIDTH))))
typedef union _BL_ME_FIA_SATA_CONFIG {
UINT64 MeFiaSataLaneConfig;
struct {
UINT64 Lane04SataSel : 2;
UINT64 Lane05SataSel : 2;
UINT64 Lane06SataSel : 2;
UINT64 Lane07SataSel : 2;
UINT64 Lane08SataSel : 2;
UINT64 Lane09SataSel : 2;
UINT64 Lane10SataSel : 2;
UINT64 Lane11SataSel : 2;
UINT64 Lane12SataSel : 2;
UINT64 Lane13SataSel : 2;
UINT64 Lane14SataSel : 2;
UINT64 Lane15SataSel : 2;
UINT64 Lane16SataSel : 2;
UINT64 Lane17SataSel : 2;
UINT64 Lane18SataSel : 2;
UINT64 Lane19SataSel : 2;
UINT64 Reserved : 32;
} BL_MeFiaSataLaneSataSel;
} BL_ME_FIA_SATA_CONFIG;
typedef enum
{
BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED = 0,
BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED = 1,
BL_ME_FIA_SATA_CONTROLLER_LANE_SS_AND_GPIO_ASSIGNED = 3
} BL_ME_FIA_SATA_LANE_CONFIG;
#define BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_SEL_WIDTH 4
#define BL_ME_FIA_PCIE_ROOT_PORTS_STATE_WIDTH 8
#define BL_ME_FIA_PCIE_ROOT_CONFIG_XHCI_ONLY 0x0
typedef enum {
BL_FIA_PCIE_ROOT_PORT_0 = 0,
BL_FIA_PCIE_ROOT_PORT_1,
BL_FIA_PCIE_ROOT_PORT_2,
BL_FIA_PCIE_ROOT_PORT_3,
BL_FIA_PCIE_ROOT_PORT_4,
BL_FIA_PCIE_ROOT_PORT_5,
BL_FIA_PCIE_ROOT_PORT_6,
BL_FIA_PCIE_ROOT_PORT_7
} BL_ME_FIA_PCIE_ROOT_PORT_ORDER;
#define BL_FIA_PCIE_ROOT_PORT_CONFIG(Type, Config, PcieRootPort) \
(((Type) == BL_ME_FIA_PCIE_ROOT_PORT_STATE) ? \
((UINT64)((UINT64)(Config) << (UINT64)(PcieRootPort))) : \
((UINT64)((UINT64)(Config) << (UINT64)(((UINT64)(PcieRootPort) * (BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_SEL_WIDTH)) + BL_ME_FIA_PCIE_ROOT_PORTS_STATE_WIDTH))))
typedef union _BL_ME_FIA_PCIE_ROOT_PORTS_CONFIG {
UINT64 MeFiaPcieRootPortsConfig;
struct {
UINT64 PcieRp0En : 1;
UINT64 PcieRp1En : 1;
UINT64 PcieRp2En : 1;
UINT64 PcieRp3En : 1;
UINT64 PcieRp4En : 1;
UINT64 PcieRp5En : 1;
UINT64 PcieRp6En : 1;
UINT64 PcieRp7En : 1;
UINT64 PcieRp0LinkWidth : 4;
UINT64 PcieRp1LinkWidth : 4;
UINT64 PcieRp2LinkWidth : 4;
UINT64 PcieRp3LinkWidth : 4;
UINT64 PcieRp4LinkWidth : 4;
UINT64 PcieRp5LinkWidth : 4;
UINT64 PcieRp6LinkWidth : 4;
UINT64 PcieRp7LinkWidth : 4;
UINT64 Reserved : 24;
} BL_MeFiaPcieRpConfig;
} BL_ME_FIA_PCIE_ROOT_PORTS_CONFIG;
typedef enum
{
BL_ME_FIA_PCIE_ROOT_PORT_STATE,
BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH
} BL_ME_FIA_PCIE_ROOT_PORT_CONFIG_TYPE;
typedef enum
{
BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
BL_ME_FIA_PCIE_ROOT_PORT_ENABLED
} BL_ME_FIA_PCIE_ROOT_PORT_STATE_CONFIG;
typedef enum
{
BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL = 0,
BL_ME_FIA_PCIE_ROOT_PORT_LINK_X1 = 0xF
} BL_ME_FIA_PCIE_ROOT_PORT_LINK_CONFIG;
typedef struct _BL_ME_FIA_CONFIG
{
BL_ME_FIA_MUX_CONFIG MuxConfiguration;
BL_ME_FIA_SATA_CONFIG SataLaneConfiguration;
BL_ME_FIA_PCIE_ROOT_PORTS_CONFIG PcieRootPortsConfiguration;
} BL_ME_FIA_CONFIG;
/*
* The FIA_MUX_CONFIG block describes the expected configuration of
* FIA MUX configuration.
*/
typedef struct {
UINT32 SkuNumLanesAllowed; // Platform view of Num Lanes allowed
BL_ME_FIA_CONFIG FiaMuxConfig; // Current Platform FIA MUX Configuration
BL_ME_FIA_CONFIG FiaMuxConfigRequest; // FIA MUX Configuration Requested
} BL_FIA_MUX_CONFIG;
/*
* The FIA_MUX_CONFIG_STATUS describes the status of configuring
* FIA MUX configuration.
*/
typedef struct {
UINT64 FiaMuxConfigGetStatus; // Status returned from FiaMuxConfigGet,if not EFI_SUCCESS, then error occurred and user can decide on next steps
UINT64 FiaMuxConfigSetStatus; // Status returned from FiaMuxConfigSet,if not EFI_SUCCESS, then error occurred and user can decide on next steps
BOOLEAN FiaMuxConfigSetRequired; // Boolean: True - A FiaMuxConfigSet was required, False - Otherwise
} BL_FIA_MUX_CONFIG_STATUS;
/*
* FIA MUX Config HOB structure
*/
typedef struct {
BL_FIA_MUX_CONFIG FiaMuxConfig;
BL_FIA_MUX_CONFIG_STATUS FiaMuxConfigStatus;
} BL_FIA_MUX_CONFIG_HOB;
/* PCIe port bifurcation codes - matches setup option values */
#define PCIE_BIF_CTRL_x2x2x2x2 0
#define PCIE_BIF_CTRL_x2x2x4 1
#define PCIE_BIF_CTRL_x4x2x2 2
#define PCIE_BIF_CTRL_x4x4 3
#define PCIE_BIF_CTRL_x8 4
#define BL_MAX_PCIE_CTRL 2
/*
* HSIO INFORMATION structure
*/
typedef enum {
BL_SKU_HSIO_06 = 6,
BL_SKU_HSIO_08 = 8,
BL_SKU_HSIO_10 = 10,
BL_SKU_HSIO_12 = 12,
BL_SKU_HSIO_20 = 20,
} BL_SKU_HSIO_LANE_NUMBER;
typedef struct {
UINT16 NumLanesSupported;
UINT8 PcieBifCtr[BL_MAX_PCIE_CTRL];
BL_ME_FIA_CONFIG FiaConfig;
} BL_HSIO_INFORMATION;
/*
* eMMC DLL structure for EMMC DLL registers settings
*/
typedef struct {
UINT32 TxCmdCntl;
UINT32 TxDataCntl1;
UINT32 TxDataCntl2;
UINT32 RxCmdDataCntl1;
UINT32 RxStrobeCntl;
UINT32 RxCmdDataCntl2;
UINT32 MasterSwCntl;
} BL_EMMC_DLL_CONFIG;
typedef struct {
UINT16 Signature;
BL_EMMC_DLL_CONFIG eMMCDLLConfig;
} BL_EMMC_INFORMATION;
typedef enum {
BL_FAST_BOOT_CHECKER_NORMAL = 0,
BL_FAST_BOOT_CHECKER_WARNING,
BL_FAST_BOOT_CHECKER_CRITICAL
} BL_FAST_BOOT_CHECKER;
#define BL_MAX_SCRUB_SEGMENTS 5
typedef struct {
UINT16 Start; // Determines the low range for a memory segment (in MB)
UINT16 End; // Determines the high range for a memory segment (in MB)
} BL_SCRUB_SEGMENT;
typedef struct {
UINT8 NumberOfSegments;
UINT8 Reserved;
BL_SCRUB_SEGMENT ScrubSegment[BL_MAX_SCRUB_SEGMENTS];
} BL_MEMORY_SCRUB_SEGMENTS;
/** Fsp M Configuration
**/
typedef struct {
/** Offset 0x0040 - Tseg Size
Size of SMRAM memory reserved.
2:2 MB, 4:4 MB, 8:8 MB, 16:16 MB
**/
UINT8 PcdSmmTsegSize;
/** Offset 0x0041 - FSP Debug Print Level
Select the FSP debug message print level.
0:NO DEBUG, 1:MIN DEBUG, 2:MED DEBUG, 3:VERBOSE DEBUG
**/
UINT8 PcdFspDebugPrintErrorLevel;
/** Offset 0x0042 - Channel 0 DIMM 0 SPD SMBus Address
SPD SMBus Address of each DIMM slot.
**/
UINT8 PcdSpdSmbusAddress_0_0;
/** Offset 0x0043 - Channel 0 DIMM 1 SPD SMBus Address
SPD SMBus Address of each DIMM slot.
**/
UINT8 PcdSpdSmbusAddress_0_1;
/** Offset 0x0044 - Channel 1 DIMM 0 SPD SMBus Address
SPD SMBus Address of each DIMM slot.
**/
UINT8 PcdSpdSmbusAddress_1_0;
/** Offset 0x0045 - Channel 1 DIMM 1 SPD SMBus Address
SPD SMBus Address of each DIMM slot.
**/
UINT8 PcdSpdSmbusAddress_1_1;
/** Offset 0x0046 - Enable Rank Margin Tool
Enable/disable Rank Margin Tool.
$EN_DIS
**/
UINT8 PcdMrcRmtSupport;
/** Offset 0x0047 - RMT CPGC exp_loop_cnt
Set the CPGC exp_loop_cnt field for RMT execution 2^(exp_loop_cnt -1).
1:1, 2:2, 3:3, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, 12:12, 13:13, 14:14, 15:15
**/
UINT8 PcdMrcRmtCpgcExpLoopCntValue;
/** Offset 0x0048 - RMT CPGC num_bursts
Set the CPGC num_bursts field for RMT execution 2^(num_bursts -1).
1:1, 2:2, 3:3, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, 12:12, 13:13, 14:14, 15:15
**/
UINT8 PcdMrcRmtCpgcNumBursts;
/** Offset 0x0049 - Preserve Memory Across Reset
Enable/disable memory preservation across reset.
$EN_DIS
**/
UINT8 PcdMemoryPreservation;
/** Offset 0x004A - Fast Boot
Enable/disable Fast Boot function. Once enabled, all following boots will use the
presaved MRC data to improve the boot performance.
$EN_DIS
**/
UINT8 PcdFastBoot;
/** Offset 0x004B - ECC Support
Enable/disable ECC Support.
$EN_DIS
**/
UINT8 PcdEccSupport;
/** Offset 0x004C - HSUART Device
Select the PCI High Speed UART Device for Serial Port.
0:HSUART0, 1:HSUART1, 2:HSUART2
**/
UINT8 PcdHsuartDevice;
/** Offset 0x004D - Memory Down
Enable/disable Memory Down function.
$EN_DIS
**/
UINT8 PcdMemoryDown;
/** Offset 0x004E
**/
UINT32 PcdMemoryDownConfigPtr;
/** Offset 0x0052 - SATA Controller 0
Enable/disable SATA Controller 0.
$EN_DIS
**/
UINT8 PcdEnableSATA0;
/** Offset 0x0053 - SATA Controller 1
Enable/disable SATA Controller 1.
$EN_DIS
**/
UINT8 PcdEnableSATA1;
/** Offset 0x0054 - Intel Quick Assist Technology
Enable/disable Intel Quick Assist Technology.
$EN_DIS
**/
UINT8 PcdEnableIQAT;
/** Offset 0x0055 - SPD Write Disable
Select SMBus SPD Write Enable State (Default: 0 = [FORCE_ENABLE], 1 = [FORCE_DISABLE])
0:Force Enable, 1:Force Disable
**/
UINT8 PcdSmbusSpdWriteDisable;
/** Offset 0x0056 - ME_SHUTDOWN Message
Enable/Disable sending ME_SHUTDOWN message to ME, refer to FSP Integration Guide
for details.
$EN_DIS
**/
UINT8 PcdEnableMeShutdown;
/** Offset 0x0057 - XHCI Controller
Enable / Disable XHCI controller
$EN_DIS
**/
UINT8 PcdEnableXhci;
/** Offset 0x0058 - Memory Frequency
Set DDR Memory Frequency, refer to FSP Integration Guide for details.
15:Auto, 3:1600, 4:1866, 5:2133, 6:2400
**/
UINT8 PcdDdrFreq;
/** Offset 0x0059 - MMIO Size
Set memory mapped IO space size
0:2048M, 1:1024M, 2:3072M
**/
UINT8 PcdMmioSize;
/** Offset 0x005A - ME HECI Communication
Enable/Disable ME HECI communication
$EN_DIS
**/
UINT8 PcdMeHeciCommunication;
/** Offset 0x005B - HSIO Lanes Number
HSIO lanes number of SKU
6:6, 8:8, 10:10, 12:12, 20:20
**/
UINT8 PcdHsioLanesNumber;
/** Offset 0x005C
**/
UINT32 PcdFiaMuxConfigPtr;
/** Offset 0x0060 - Customer Revision
The Customer can set this revision string for their own purpose.
**/
UINT8 PcdCustomerRevision[32];
/** Offset 0x0080 - 32-Bit bus mode
Enable/Disable 32-Bit bus memory mode.
$EN_DIS
**/
UINT8 PcdHalfWidthEnable;
/** Offset 0x0081 - TCL Performance
Enable/Disable Tcl timing for performance.
$EN_DIS
**/
UINT8 PcdTclIdle;
/** Offset 0x0082 - Interleave Mode
Select Interleave Mode
0:DISABLED, 1:MODE0, 2:MODE1, 3:MODE2
**/
UINT8 PcdInterleaveMode;
/** Offset 0x0083 - Memory Thermal Throttling
Enable/disable Memory Thermal Throttling management mode
$EN_DIS
**/
UINT8 PcdMemoryThermalThrottling;
/** Offset 0x0084 - Memory Test
Enable / Disable Memory Test, refer to FSP Integration Guide for details.
$EN_DIS
**/
UINT8 PcdSkipMemoryTest;
/** Offset 0x0085
**/
BL_MEMORY_SCRUB_SEGMENTS* PcdScrubSegmentPtr;
/** Offset 0x0089 - USB2 Port 1 OC Pin
Map selected OC pin to the port
0:OC Pin 0, 8:No pin mapped
**/
UINT8 PcdUsb2Port1Pin;
/** Offset 0x008A - USB2 Port 2 OC Pin
Map selected OC pin to the port
0:OC Pin 0, 8:No pin mapped
**/
UINT8 PcdUsb2Port2Pin;
/** Offset 0x008B - USB2 Port 3 OC Pin
Map selected OC pin to the port
0:OC Pin 0, 8:No pin mapped
**/
UINT8 PcdUsb2Port3Pin;
/** Offset 0x008C - USB2 Port 4 OC Pin
Map selected OC pin to the port
0:OC Pin 0, 8:No pin mapped
**/
UINT8 PcdUsb2Port4Pin;
/** Offset 0x008D - USB3 Port 1 OC Pin
Map selected OC pin to the port
0:OC Pin 0, 8:No pin mapped
**/
UINT8 PcdUsb3Port1Pin;
/** Offset 0x008E - USB3 Port 2 OC Pin
Map selected OC pin to the port
0:OC Pin 0, 8:No pin mapped
**/
UINT8 PcdUsb3Port2Pin;
/** Offset 0x008F - USB3 Port 3 OC Pin
Map selected OC pin to the port
0:OC Pin 0, 8:No pin mapped
**/
UINT8 PcdUsb3Port3Pin;
/** Offset 0x0090 - USB3 Port 4 OC Pin
Map selected OC pin to the port
0:OC Pin 0, 8:No pin mapped
**/
UINT8 PcdUsb3Port4Pin;
/** Offset 0x0091 - IOxAPIC 0-199
Enable/disable IOxAPIC 24-119 entries
$EN_DIS
**/
UINT8 PcdIOxAPIC0_199;
/** Offset 0x0092 - DMAP_X16
Enable/Disable DMAP_X16 dynamic MRC field indicating memory device width is x16 or not
$EN_DIS
**/
UINT8 PcdDmapX16;
/** Offset 0x0093
**/
UINT8 UnusedUpdSpace0[333];
/** Offset 0x01E0
**/
UINT8 ReservedMemoryInitUpd[16];
} FSPM_CONFIG;
/** Fsp M UPD Configuration
**/
typedef struct {
/** Offset 0x0000
**/
FSP_UPD_HEADER FspUpdHeader;
/** Offset 0x0020
**/
FSPM_ARCH_UPD FspmArchUpd;
/** Offset 0x0040
**/
FSPM_CONFIG FspmConfig;
/** Offset 0x01F0
**/
UINT8 UnusedUpdSpace1[14];
/** Offset 0x01FE
**/
UINT16 UpdTerminator;
} FSPM_UPD;
#pragma pack()
#endif

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@ -0,0 +1,288 @@
/** @file
Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
This file is automatically generated. Please do NOT modify !!!
**/
#ifndef __FSPSUPD_H__
#define __FSPSUPD_H__
#include <FspUpd.h>
#pragma pack(1)
/** Fsp S Configuration
**/
typedef struct {
/** Offset 0x0020 - PCIe Controller 0 Bifurcation
Configure PCI Express controller 0 bifurcation.
0:X2X2X2X2, 1:X2X2X4, 2:X4X2X2, 3:X4X4, 4:X8
**/
UINT8 PcdBifurcationPcie0;
/** Offset 0x0021 - PCIe Controller 1 Bifurcation
Configure PCI Express controller 1 bifurcation.
0:X2X2X2X2, 1:X2X2X4, 2:X4X2X2, 3:X4X4, 4:X8
**/
UINT8 PcdBifurcationPcie1;
/** Offset 0x0022 - Active Core Count
Select # of Active Cores (Default: 0, 0:ALL, 1..15 = 1..15 Cores)
0:ALL, 1:1, 2:2, 3:3, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, 12:12, 13:13,
14:14, 15:15
**/
UINT8 PcdActiveCoreCount;
/** Offset 0x0023
**/
UINT32 PcdCpuMicrocodePatchBase;
/** Offset 0x0027
**/
UINT32 PcdCpuMicrocodePatchSize;
/** Offset 0x002B - PCIe Controller 0
Enable / Disable PCI Express controller 0
$EN_DIS
**/
UINT8 PcdEnablePcie0;
/** Offset 0x002C - PCIe Controller 1
Enable / Disable PCI Express controller 1
$EN_DIS
**/
UINT8 PcdEnablePcie1;
/** Offset 0x002D - Embedded Multi-Media Controller (eMMC)
Enable / Disable Embedded Multi-Media controller
$EN_DIS
**/
UINT8 PcdEnableEmmc;
/** Offset 0x002E - LAN Controllers
Enable / Disable LAN controllers, refer to FSP Integration Guide for details.
0:Disable LAN 0 & LAN 1, 1:Enable LAN 0 & LAN 1, 2:Disable LAN 1 only
**/
UINT8 PcdEnableGbE;
/** Offset 0x002F
**/
UINT32 PcdFiaMuxConfigRequestPtr;
/** Offset 0x0033
**/
UINT8 UnusedUpdSpace0[4];
/** Offset 0x0037 - PCIe Root Port 0 DeEmphasis
Desired DeEmphasis level for PCIE root port
0:6dB, 1:3.5dB
**/
UINT8 PcdPcieRootPort0DeEmphasis;
/** Offset 0x0038 - PCIe Root Port 1 DeEmphasis
Desired DeEmphasis level for PCIE root port
0:6dB, 1:3.5dB
**/
UINT8 PcdPcieRootPort1DeEmphasis;
/** Offset 0x0039 - PCIe Root Port 2 DeEmphasis
Desired DeEmphasis level for PCIE root port
0:6dB, 1:3.5dB
**/
UINT8 PcdPcieRootPort2DeEmphasis;
/** Offset 0x003A - PCIe Root Port 3 DeEmphasis
Desired DeEmphasis level for PCIE root port
0:6dB, 1:3.5dB
**/
UINT8 PcdPcieRootPort3DeEmphasis;
/** Offset 0x003B - PCIe Root Port 4 DeEmphasis
Desired DeEmphasis level for PCIE root port
0:6dB, 1:3.5dB
**/
UINT8 PcdPcieRootPort4DeEmphasis;
/** Offset 0x003C - PCIe Root Port 5 DeEmphasis
Desired DeEmphasis level for PCIE root port
0:6dB, 1:3.5dB
**/
UINT8 PcdPcieRootPort5DeEmphasis;
/** Offset 0x003D - PCIe Root Port 6 DeEmphasis
Desired DeEmphasis level for PCIE root port
0:6dB, 1:3.5dB
**/
UINT8 PcdPcieRootPort6DeEmphasis;
/** Offset 0x003E - PCIe Root Port 7 DeEmphasis
Desired DeEmphasis level for PCIE root port
0:6dB, 1:3.5dB
**/
UINT8 PcdPcieRootPort7DeEmphasis;
/** Offset 0x003F
**/
UINT8 UnusedUpdSpace1;
/** Offset 0x0040
**/
UINT32 PcdEMMCDLLConfigPtr;
/** Offset 0x0044 - PCIe Root Port 0 Link Speed
Upper limit on link operational speed for PCI Express RootPort
1:GEN1, 2:GEN2, 3:GEN3
**/
UINT8 PcdPcieRootPort0LinkSpeed;
/** Offset 0x0045 - PCIe Root Port 1 Link Speed
Upper limit on link operational speed for PCI Express RootPort
1:GEN1, 2:GEN2, 3:GEN3
**/
UINT8 PcdPcieRootPort1LinkSpeed;
/** Offset 0x0046 - PCIe Root Port 2 Link Speed
Upper limit on link operational speed for PCI Express RootPort
1:GEN1, 2:GEN2, 3:GEN3
**/
UINT8 PcdPcieRootPort2LinkSpeed;
/** Offset 0x0047 - PCIe Root Port 3 Link Speed
Upper limit on link operational speed for PCI Express RootPort
1:GEN1, 2:GEN2, 3:GEN3
**/
UINT8 PcdPcieRootPort3LinkSpeed;
/** Offset 0x0048 - PCIe Root Port 4 Link Speed
Upper limit on link operational speed for PCI Express RootPort
1:GEN1, 2:GEN2, 3:GEN3
**/
UINT8 PcdPcieRootPort4LinkSpeed;
/** Offset 0x0049 - PCIe Root Port 5 Link Speed
Upper limit on link operational speed for PCI Express RootPort
1:GEN1, 2:GEN2, 3:GEN3
**/
UINT8 PcdPcieRootPort5LinkSpeed;
/** Offset 0x004A - PCIe Root Port 6 Link Speed
Upper limit on link operational speed for PCI Express RootPort
1:GEN1, 2:GEN2, 3:GEN3
**/
UINT8 PcdPcieRootPort6LinkSpeed;
/** Offset 0x004B - PCIe Root Port 7 Link Speed
Upper limit on link operational speed for PCI Express RootPort
1:GEN1, 2:GEN2, 3:GEN3
**/
UINT8 PcdPcieRootPort7LinkSpeed;
/** Offset 0x004C - PCIe Root Port 0 ASPM
Enable PCI Express Active State Power Management settings
0:Disabled, 2:L1
**/
UINT8 PcdPcieRootPort0Aspm;
/** Offset 0x004D - PCIe Root Port 1 ASPM
Enable PCI Express Active State Power Management settings
0:Disabled, 2:L1
**/
UINT8 PcdPcieRootPort1Aspm;
/** Offset 0x004E - PCIe Root Port 2 ASPM
Enable PCI Express Active State Power Management settings
0:Disabled, 2:L1
**/
UINT8 PcdPcieRootPort2Aspm;
/** Offset 0x004F - PCIe Root Port 3 ASPM
Enable PCI Express Active State Power Management settings
0:Disabled, 2:L1
**/
UINT8 PcdPcieRootPort3Aspm;
/** Offset 0x0050 - PCIe Root Port 4 ASPM
Enable PCI Express Active State Power Management settings
0:Disabled, 2:L1
**/
UINT8 PcdPcieRootPort4Aspm;
/** Offset 0x0051 - PCIe Root Port 5 ASPM
Enable PCI Express Active State Power Management settings
0:Disabled, 2:L1
**/
UINT8 PcdPcieRootPort5Aspm;
/** Offset 0x0052 - PCIe Root Port 6 ASPM
Enable PCI Express Active State Power Management settings
0:Disabled, 2:L1
**/
UINT8 PcdPcieRootPort6Aspm;
/** Offset 0x0053 - PCIe Root Port 7 ASPM
Enable PCI Express Active State Power Management settings
0:Disabled, 2:L1
**/
UINT8 PcdPcieRootPort7Aspm;
/** Offset 0x0054
**/
UINT8 UnusedUpdSpace2[140];
/** Offset 0x00E0
**/
UINT8 ReservedSiliconInitUpd[16];
} FSPS_CONFIG;
/** Fsp S UPD Configuration
**/
typedef struct {
/** Offset 0x0000
**/
FSP_UPD_HEADER FspUpdHeader;
/** Offset 0x0020
**/
FSPS_CONFIG FspsConfig;
/** Offset 0x00F0
**/
UINT8 UnusedUpdSpace3[14];
/** Offset 0x00FE
**/
UINT16 UpdTerminator;
} FSPS_UPD;
#pragma pack()
#endif

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@ -0,0 +1,109 @@
/** @file
Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
This file is automatically generated. Please do NOT modify !!!
**/
#ifndef __FSPTUPD_H__
#define __FSPTUPD_H__
#include <FspUpd.h>
#pragma pack(1)
/** Fsp T Core UPD
**/
typedef struct {
/** Offset 0x0020
**/
UINT32 MicrocodeRegionBase;
/** Offset 0x0024
**/
UINT32 MicrocodeRegionLength;
/** Offset 0x0028
**/
UINT32 CodeRegionBase;
/** Offset 0x002C
**/
UINT32 CodeRegionLength;
/** Offset 0x0030
**/
UINT8 Reserved1[16];
} FSPT_CORE_UPD;
/** Fsp T Configuration
**/
typedef struct {
/** Offset 0x0040 - Disable Port80 output in FSP-T
Select Port80 Control in FSP-T (0:VPD-Style, 1:Enable Port80 Output, 2:Disable Port80
Output, refer to FSP Integration Guide for details
0:VPD-Style, 1:Enable Port80 Output[Default], 2:Disable Port80 Output
**/
UINT8 PcdFsptPort80RouteDisable;
/** Offset 0x0041
**/
UINT8 ReservedTempRamInitUpd[31];
} FSPT_CONFIG;
/** Fsp T UPD Configuration
**/
typedef struct {
/** Offset 0x0000
**/
FSP_UPD_HEADER FspUpdHeader;
/** Offset 0x0020
**/
FSPT_CORE_UPD FsptCoreUpd;
/** Offset 0x0040
**/
FSPT_CONFIG FsptConfig;
/** Offset 0x0060
**/
UINT8 UnusedUpdSpace0[30];
/** Offset 0x007E
**/
UINT16 UpdTerminator;
} FSPT_UPD;
#pragma pack()
#endif

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