From 3853be02e71adb8f87d2c792b9f3f855b798e428 Mon Sep 17 00:00:00 2001 From: Nate DeSimone Date: Tue, 28 Jun 2022 16:37:59 -0700 Subject: [PATCH] Alder Lake FSP C.1.69.74 --- .../Client/AlderLakeP/AlderLakeFspBinPkg.dec | 19 + AlderLakeFspBinPkg/Client/AlderLakeP/Fsp.bsf | 6028 ++ AlderLakeFspBinPkg/Client/AlderLakeP/Fsp.fd | Bin 0 -> 1241088 bytes .../Client/AlderLakeP/FspPkgPcdShare.dsc | 90 + .../AlderLakeP/Include/FirmwareVersionInfo.h | 54 + .../Include/FirmwareVersionInfoHob.h | 65 + .../Client/AlderLakeP/Include/FspInfoHob.h | 32 + .../Client/AlderLakeP/Include/FspUpd.h | 48 + .../Client/AlderLakeP/Include/FspmUpd.h | 4029 + .../Client/AlderLakeP/Include/FspsUpd.h | 4280 + .../Client/AlderLakeP/Include/FsptUpd.h | 357 + .../Client/AlderLakeP/Include/GpioConfig.h | 332 + .../Client/AlderLakeP/Include/GpioSampleDef.h | 381 + .../AlderLakeP/Include/HobUsageDataHob.h | 35 + .../Client/AlderLakeP/Include/MemInfoHob.h | 315 + .../AlderLakeP/Include/SmbiosCacheInfoHob.h | 47 + .../Include/SmbiosProcessorInfoHob.h | 62 + .../Library/FspPcdListLib/FspPcdListLibNull.c | 25 + .../FspPcdListLib/FspPcdListLibNull.inf | 61 + .../Client/AlderLakeP/SampleCode/Vbt/Vbt.bin | Bin 0 -> 8704 bytes .../Client/AlderLakeP/SampleCode/Vbt/Vbt.json | 72466 ++++++++++++++++ 21 files changed, 88726 insertions(+) create mode 100644 AlderLakeFspBinPkg/Client/AlderLakeP/AlderLakeFspBinPkg.dec create mode 100644 AlderLakeFspBinPkg/Client/AlderLakeP/Fsp.bsf create mode 100644 AlderLakeFspBinPkg/Client/AlderLakeP/Fsp.fd create mode 100644 AlderLakeFspBinPkg/Client/AlderLakeP/FspPkgPcdShare.dsc create mode 100644 AlderLakeFspBinPkg/Client/AlderLakeP/Include/FirmwareVersionInfo.h create mode 100644 AlderLakeFspBinPkg/Client/AlderLakeP/Include/FirmwareVersionInfoHob.h create mode 100644 AlderLakeFspBinPkg/Client/AlderLakeP/Include/FspInfoHob.h create mode 100644 AlderLakeFspBinPkg/Client/AlderLakeP/Include/FspUpd.h create mode 100644 AlderLakeFspBinPkg/Client/AlderLakeP/Include/FspmUpd.h create mode 100644 AlderLakeFspBinPkg/Client/AlderLakeP/Include/FspsUpd.h create mode 100644 AlderLakeFspBinPkg/Client/AlderLakeP/Include/FsptUpd.h create mode 100644 AlderLakeFspBinPkg/Client/AlderLakeP/Include/GpioConfig.h create mode 100644 AlderLakeFspBinPkg/Client/AlderLakeP/Include/GpioSampleDef.h create mode 100644 AlderLakeFspBinPkg/Client/AlderLakeP/Include/HobUsageDataHob.h create mode 100644 AlderLakeFspBinPkg/Client/AlderLakeP/Include/MemInfoHob.h create mode 100644 AlderLakeFspBinPkg/Client/AlderLakeP/Include/SmbiosCacheInfoHob.h create mode 100644 AlderLakeFspBinPkg/Client/AlderLakeP/Include/SmbiosProcessorInfoHob.h create mode 100644 AlderLakeFspBinPkg/Client/AlderLakeP/Library/FspPcdListLib/FspPcdListLibNull.c create mode 100644 AlderLakeFspBinPkg/Client/AlderLakeP/Library/FspPcdListLib/FspPcdListLibNull.inf create mode 100644 AlderLakeFspBinPkg/Client/AlderLakeP/SampleCode/Vbt/Vbt.bin create mode 100644 AlderLakeFspBinPkg/Client/AlderLakeP/SampleCode/Vbt/Vbt.json diff --git a/AlderLakeFspBinPkg/Client/AlderLakeP/AlderLakeFspBinPkg.dec b/AlderLakeFspBinPkg/Client/AlderLakeP/AlderLakeFspBinPkg.dec new file mode 100644 index 0000000..6f2c09e --- /dev/null +++ b/AlderLakeFspBinPkg/Client/AlderLakeP/AlderLakeFspBinPkg.dec @@ -0,0 +1,19 @@ +## @file +# Component description file for AlderLake Fsp Bin package. +# +# @copyright +# Copyright (c) 2022, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# @par Specification +## + +[Defines] + DEC_SPECIFICATION = 0x00010005 + PACKAGE_NAME = AlderLakeFspBinPkg + PACKAGE_GUID = 0F3DA8C5-37D9-4AF8-8302-3B6CB2D97FC1 + PACKAGE_VERSION = 1.02 + +[Includes] + Include diff --git a/AlderLakeFspBinPkg/Client/AlderLakeP/Fsp.bsf b/AlderLakeFspBinPkg/Client/AlderLakeP/Fsp.bsf new file mode 100644 index 0000000..ea20a06 --- /dev/null +++ b/AlderLakeFspBinPkg/Client/AlderLakeP/Fsp.bsf @@ -0,0 +1,6028 @@ +/** @file + + Boot Setting File for Platform Configuration. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + This file is automatically generated. Please do NOT modify !!! + +**/ + + + +GlobalDataDef + SKUID = 0, "DEFAULT" +EndGlobalData + + +StructDef + + Find "ADLUPD_T" + $gPlatformFspPkgTokenSpaceGuid_Revision 1 bytes $_DEFAULT_ = 0x02 + Skip 87 bytes + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartDebugEnable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartNumber 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartMode 1 bytes $_DEFAULT_ = 0x02 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartBaudRate 4 bytes $_DEFAULT_ = 115200 + $gPlatformFspPkgTokenSpaceGuid_PcdPciExpressBaseAddress 8 bytes $_DEFAULT_ = 0xC0000000 + $gPlatformFspPkgTokenSpaceGuid_PcdPciExpressRegionLength 4 bytes $_DEFAULT_ = 0x10000000 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartParity 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartDataBits 1 bytes $_DEFAULT_ = 0x08 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartStopBits 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartAutoFlow 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartRxPinMux 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartTxPinMux 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartRtsPinMux 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartCtsPinMux 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartDebugMmioBase 4 bytes $_DEFAULT_ = 0xFE036000 + $gPlatformFspPkgTokenSpaceGuid_PcdLpcUartDebugEnable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcdDebugInterfaceFlags 1 bytes $_DEFAULT_ = 0x012 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugLevel 1 bytes $_DEFAULT_ = 0x03 + $gPlatformFspPkgTokenSpaceGuid_PcdIsaSerialUartBase 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIo2ndUartEnable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIo2ndUartNumber 1 bytes $_DEFAULT_ = 0x02 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIo2ndUartMode 1 bytes $_DEFAULT_ = 0x02 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIo2ndUartBaudRate 4 bytes $_DEFAULT_ = 115200 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIo2ndUartParity 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIo2ndUartDataBits 1 bytes $_DEFAULT_ = 0x08 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIo2ndUartStopBits 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIo2ndUartAutoFlow 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIo2ndUartRxPinMux 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIo2ndUartTxPinMux 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIo2ndUartRtsPinMux 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIo2ndUartCtsPinMux 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIo2ndUartMmioBase 4 bytes $_DEFAULT_ = 0xFE034000 + Skip 4 bytes + $gPlatformFspPkgTokenSpaceGuid_FspDebugHandler 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoSpiCsPolarity 2 bytes $_DEFAULT_ = 0x0, 0x0 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoSpiCsEnable 2 bytes $_DEFAULT_ = 0x0, 0x0 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoSpiMode 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoSpiDefaultCsOutput 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoSpiCsMode 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoSpiCsState 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoSpiNumber 1 bytes $_DEFAULT_ = 0x0 + Skip 3 bytes + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoSpiMmioBase 4 bytes $_DEFAULT_ = 0x0 + + Find "ADLUPD_M" + $gPlatformFspPkgTokenSpaceGuid_Revision 1 bytes $_DEFAULT_ = 0x02 + Skip 55 bytes + $gPlatformFspPkgTokenSpaceGuid_PlatformMemorySize 8 bytes $_DEFAULT_ = 0x550000 + $gPlatformFspPkgTokenSpaceGuid_MemorySpdDataLen 2 bytes $_DEFAULT_ = 0x200 + $gPlatformFspPkgTokenSpaceGuid_EnableAbove4GBMmio 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_CpuCrashLogDevice 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr000 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr001 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr010 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr011 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr020 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr021 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr030 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr031 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr100 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr101 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr110 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr111 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr120 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr121 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr130 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr131 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_RcompResistor 2 bytes $_DEFAULT_ = 0 + $gPlatformFspPkgTokenSpaceGuid_RcompTarget 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_DqsMapCpu2DramMc0Ch0 2 bytes $_DEFAULT_ = 0, 1 + $gPlatformFspPkgTokenSpaceGuid_DqsMapCpu2DramMc0Ch1 2 bytes $_DEFAULT_ = 0, 1 + $gPlatformFspPkgTokenSpaceGuid_DqsMapCpu2DramMc0Ch2 2 bytes $_DEFAULT_ = 0, 1 + $gPlatformFspPkgTokenSpaceGuid_DqsMapCpu2DramMc0Ch3 2 bytes $_DEFAULT_ = 0, 1 + $gPlatformFspPkgTokenSpaceGuid_DqsMapCpu2DramMc1Ch0 2 bytes $_DEFAULT_ = 0, 1 + $gPlatformFspPkgTokenSpaceGuid_DqsMapCpu2DramMc1Ch1 2 bytes $_DEFAULT_ = 0, 1 + $gPlatformFspPkgTokenSpaceGuid_DqsMapCpu2DramMc1Ch2 2 bytes $_DEFAULT_ = 0, 1 + $gPlatformFspPkgTokenSpaceGuid_DqsMapCpu2DramMc1Ch3 2 bytes $_DEFAULT_ = 0, 1 + $gPlatformFspPkgTokenSpaceGuid_DqMapCpu2DramMc0Ch0 16 bytes $_DEFAULT_ = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 + $gPlatformFspPkgTokenSpaceGuid_DqMapCpu2DramMc0Ch1 16 bytes $_DEFAULT_ = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 + $gPlatformFspPkgTokenSpaceGuid_DqMapCpu2DramMc0Ch2 16 bytes $_DEFAULT_ = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 + $gPlatformFspPkgTokenSpaceGuid_DqMapCpu2DramMc0Ch3 16 bytes $_DEFAULT_ = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 + $gPlatformFspPkgTokenSpaceGuid_DqMapCpu2DramMc1Ch0 16 bytes $_DEFAULT_ = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 + $gPlatformFspPkgTokenSpaceGuid_DqMapCpu2DramMc1Ch1 16 bytes $_DEFAULT_ = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 + $gPlatformFspPkgTokenSpaceGuid_DqMapCpu2DramMc1Ch2 16 bytes $_DEFAULT_ = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 + $gPlatformFspPkgTokenSpaceGuid_DqMapCpu2DramMc1Ch3 16 bytes $_DEFAULT_ = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 + $gPlatformFspPkgTokenSpaceGuid_DqPinsInterleaved 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_SmramMask 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_Ibecc 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_IbeccOperationMode 1 bytes $_DEFAULT_ = 0x02 + $gPlatformFspPkgTokenSpaceGuid_IbeccProtectedRangeEnable 8 bytes $_DEFAULT_ = 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 + $gPlatformFspPkgTokenSpaceGuid_IbeccProtectedRangeBase 32 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_IbeccProtectedRangeMask 32 bytes $_DEFAULT_ = 0xE0,0xFF,0xFF,0x03,0xE0,0xFF,0xFF,0x03,0xE0,0xFF,0xFF,0x03,0xE0,0xFF,0xFF,0x03,0xE0,0xFF,0xFF,0x03,0xE0,0xFF,0xFF,0x03,0xE0,0xFF,0xFF,0x03,0xE0,0xFF,0xFF,0x03 + $gPlatformFspPkgTokenSpaceGuid_MrcFastBoot 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_RmtPerTask 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_TrainTrace 1 bytes $_DEFAULT_ = 0x0 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_TsegSize 4 bytes $_DEFAULT_ = 0x0400000 + $gPlatformFspPkgTokenSpaceGuid_MmioSize 2 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_ProbelessTrace 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_SmbusEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_SpdAddressTable 16 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_PlatformDebugConsent 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_DciEn 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_DciDbcMode 1 bytes $_DEFAULT_ = 0x04 + $gPlatformFspPkgTokenSpaceGuid_DciModphyPg 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_DciUsb3TypecUfpDbg 1 bytes $_DEFAULT_ = 0x02 + $gPlatformFspPkgTokenSpaceGuid_PchTraceHubMode 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchTraceHubMemReg0Size 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchTraceHubMemReg1Size 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkDmicClockSelect 2 bytes $_DEFAULT_ = 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPreMemRsvd 5 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_X2ApicOptOut 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_DmaControlGuarantee 1 bytes $_DEFAULT_ = 0x1 + Skip 3 bytes + $gPlatformFspPkgTokenSpaceGuid_VtdBaseAddress 36 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_VtdDisable 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_VtdIgdEnable 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_VtdIpuEnable 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_VtdIopEnable 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_VtdItbtEnable 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_IgdDvmt50PreAlloc 1 bytes $_DEFAULT_ = 0xFE + $gPlatformFspPkgTokenSpaceGuid_InternalGfx 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_ApertureSize 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_UserBd 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_DisableMrcRetrainingOnRtcPowerLoss 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_DdrFreqLimit 2 bytes $_DEFAULT_ = 0 + $gPlatformFspPkgTokenSpaceGuid_SaGv 1 bytes $_DEFAULT_ = 0x05 + $gPlatformFspPkgTokenSpaceGuid_MemTestOnWarmBoot 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_DdrSpeedControl 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_RMT 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_DisableMc0Ch0 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_DisableMc0Ch1 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_DisableMc0Ch2 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_DisableMc0Ch3 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_DisableMc1Ch0 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_DisableMc1Ch1 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_DisableMc1Ch2 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_DisableMc1Ch3 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_ScramblerSupport 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_SpdProfileSelected 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_RefClk 1 bytes $_DEFAULT_ = 0x00 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_VddVoltage 2 bytes $_DEFAULT_ = 0x0000 + $gPlatformFspPkgTokenSpaceGuid_Ratio 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_tCL 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_tCWL 1 bytes $_DEFAULT_ = 0x00 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_tFAW 2 bytes $_DEFAULT_ = 0x0000 + $gPlatformFspPkgTokenSpaceGuid_tRAS 2 bytes $_DEFAULT_ = 0x0000 + $gPlatformFspPkgTokenSpaceGuid_tRCDtRP 1 bytes $_DEFAULT_ = 0x00 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_tREFI 2 bytes $_DEFAULT_ = 0x0000 + $gPlatformFspPkgTokenSpaceGuid_tRFC 2 bytes $_DEFAULT_ = 0x0000 + $gPlatformFspPkgTokenSpaceGuid_tRRD 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_tRTP 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_tWR 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_tWTR 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_NModeSupport 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchHdaEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchIshEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMode 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMemReg0Size 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMemReg1Size 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_SaGvGear 4 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_SaGvFreq 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_GearRatio 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_HeciTimeouts 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_Heci1BarAddress 4 bytes $_DEFAULT_ = 0xFEDA2000 + $gPlatformFspPkgTokenSpaceGuid_Heci2BarAddress 4 bytes $_DEFAULT_ = 0xFEDA3000 + $gPlatformFspPkgTokenSpaceGuid_Heci3BarAddress 4 bytes $_DEFAULT_ = 0xFEDA4000 + $gPlatformFspPkgTokenSpaceGuid_HgDelayAfterPwrEn 2 bytes $_DEFAULT_ = 300 + $gPlatformFspPkgTokenSpaceGuid_HgDelayAfterHoldReset 2 bytes $_DEFAULT_ = 100 + $gPlatformFspPkgTokenSpaceGuid_MmioSizeAdjustment 2 bytes $_DEFAULT_ = 0 + $gPlatformFspPkgTokenSpaceGuid_InitPcieAspmAfterOprom 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PrimaryDisplay 1 bytes $_DEFAULT_ = 0x3 + $gPlatformFspPkgTokenSpaceGuid_PsmiRegionSize 1 bytes $_DEFAULT_ = 0x0 + Skip 3 bytes + $gPlatformFspPkgTokenSpaceGuid_GmAdr 4 bytes $_DEFAULT_ = 0xB0000000 + $gPlatformFspPkgTokenSpaceGuid_GttMmAdr 4 bytes $_DEFAULT_ = 0xAF000000 + $gPlatformFspPkgTokenSpaceGuid_GttSize 2 bytes $_DEFAULT_ = 0x3 + $gPlatformFspPkgTokenSpaceGuid_CpuPcie0Rtd3Gpio 24 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_TxtImplemented 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_SaOcSupport 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_GtVoltageMode 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_GtMaxOcRatio 1 bytes $_DEFAULT_ = 0 + $gPlatformFspPkgTokenSpaceGuid_GtVoltageOffset 2 bytes $_DEFAULT_ = 0 + $gPlatformFspPkgTokenSpaceGuid_GtVoltageOverride 2 bytes $_DEFAULT_ = 0 + $gPlatformFspPkgTokenSpaceGuid_GtExtraTurboVoltage 2 bytes $_DEFAULT_ = 0 + $gPlatformFspPkgTokenSpaceGuid_SaVoltageOffset 2 bytes $_DEFAULT_ = 0 + $gPlatformFspPkgTokenSpaceGuid_RootPortIndex 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_RealtimeMemoryTiming 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PcieMultipleSegmentEnabled 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_SaIpuEnable 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_IpuLaneUsed 8 bytes $_DEFAULT_ = 0x04, 0x01, 0x02, 0x04, 0x04, 0x04, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_CsiSpeed 8 bytes $_DEFAULT_ = 0x2, 0x1, 0x2, 0x2, 0x2, 0x2, 0x0, 0x0 + $gPlatformFspPkgTokenSpaceGuid_ImguClkOutEn 6 bytes $_DEFAULT_ = 0x1, 0x1, 0x1, 0x1, 0x0, 0x0 + $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpEnableMask 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpLinkDownGpios 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpClockReqMsgEnable 3 bytes $_DEFAULT_ = 0x1, 0x1, 0x1 + $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpPcieSpeed 4 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_GtPsmiSupport 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_DdiPortAConfig 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_DdiPortBConfig 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_DdiPortAHpd 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_DdiPortBHpd 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_DdiPortCHpd 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_DdiPort1Hpd 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_DdiPort2Hpd 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_DdiPort3Hpd 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_DdiPort4Hpd 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_DdiPortADdc 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_DdiPortBDdc 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_DdiPortCDdc 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_DdiPort1Ddc 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_DdiPort2Ddc 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_DdiPort3Ddc 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_DdiPort4Ddc 1 bytes $_DEFAULT_ = 0x0 + Skip 7 bytes + $gPlatformFspPkgTokenSpaceGuid_GmAdr64 8 bytes $_DEFAULT_ = 0xB0000000 + $gPlatformFspPkgTokenSpaceGuid_PerCoreHtDisable 2 bytes $_DEFAULT_ = 0x0000 + $gPlatformFspPkgTokenSpaceGuid_SaVoltageMode 1 bytes $_DEFAULT_ = 0x00 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_SaVoltageOverride 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_SaExtraTurboVoltage 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_TvbRatioClipping 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_TvbVoltageOptimization 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_DisplayAudioLink 1 bytes $_DEFAULT_ = 0x0 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_VddqVoltage 2 bytes $_DEFAULT_ = 0x0000 + $gPlatformFspPkgTokenSpaceGuid_VppVoltage 2 bytes $_DEFAULT_ = 0x0000 + $gPlatformFspPkgTokenSpaceGuid_CpuPcieNewFom 4 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_DmiNewFom 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_DynamicMemoryBoost 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_HgSupport 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_RealtimeMemoryFrequency 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_SaPreMemProductionRsvd 97 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_GtClosEnable 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_DmiMaxLinkSpeed 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_DmiGen3EqPh2Enable 1 bytes $_DEFAULT_ = 0x02 + $gPlatformFspPkgTokenSpaceGuid_DmiGen3EqPh3Method 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_DmiGen3ProgramStaticEq 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_DmiDeEmphasis 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_DmiGen3RootPortPreset 8 bytes $_DEFAULT_ = 0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08 + $gPlatformFspPkgTokenSpaceGuid_DmiGen3EndPointPreset 8 bytes $_DEFAULT_ = 0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07 + $gPlatformFspPkgTokenSpaceGuid_DmiGen3EndPointHint 8 bytes $_DEFAULT_ = 0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02 + $gPlatformFspPkgTokenSpaceGuid_DmiGen3RxCtlePeaking 4 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_DmiAspm 1 bytes $_DEFAULT_ = 0x2 + $gPlatformFspPkgTokenSpaceGuid_DmiHweq 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_Gen3EqPhase23Bypass 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_Gen3EqPhase3Bypass 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_Gen3LtcoEnable 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_Gen3RtcoRtpoEnable 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_DmiGen3Ltcpre 8 bytes $_DEFAULT_ = 0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02 + $gPlatformFspPkgTokenSpaceGuid_DmiGen3Ltcpo 8 bytes $_DEFAULT_ = 0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02 + $gPlatformFspPkgTokenSpaceGuid_CpuDmiHwEqGen3CoeffListCm 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_CpuDmiHwEqGen3CoeffListCp 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_DmiGen3DsPresetEnable 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_DmiGen3DsPortRxPreset 8 bytes $_DEFAULT_ = 0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01 + $gPlatformFspPkgTokenSpaceGuid_DmiGen3DsPortTxPreset 8 bytes $_DEFAULT_ = 0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07 + $gPlatformFspPkgTokenSpaceGuid_DmiGen3UsPresetEnable 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_DmiGen3UsPortRxPreset 8 bytes $_DEFAULT_ = 0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07 + $gPlatformFspPkgTokenSpaceGuid_DmiGen3UsPortTxPreset 8 bytes $_DEFAULT_ = 0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07 + $gPlatformFspPkgTokenSpaceGuid_CpuDmiHwEqGen4CoeffListCm 8 bytes $_DEFAULT_ = 0x0, 0x7, 0x6, 0x7, 0x7, 0x7, 0x7, 0x7 + $gPlatformFspPkgTokenSpaceGuid_CpuDmiHwEqGen4CoeffListCp 8 bytes $_DEFAULT_ = 0x0, 0xE, 0xA, 0x7, 0x7, 0x7, 0x7, 0x7 + $gPlatformFspPkgTokenSpaceGuid_Gen4EqPhase23Bypass 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_Gen4EqPhase3Bypass 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_DmiGen4DsPresetEnable 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_DmiGen4DsPortTxPreset 8 bytes $_DEFAULT_ = 0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07 + $gPlatformFspPkgTokenSpaceGuid_Gen4RtcoRtpoEnable 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_Gen4LtcoEnable 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_DmiGen4Ltcpre 8 bytes $_DEFAULT_ = 0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07 + $gPlatformFspPkgTokenSpaceGuid_DmiGen4Ltcpo 8 bytes $_DEFAULT_ = 0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07 + $gPlatformFspPkgTokenSpaceGuid_DmiGen4UsPresetEnable 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_DmiGen4UsPortTxPreset 8 bytes $_DEFAULT_ = 0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07 + $gPlatformFspPkgTokenSpaceGuid_DmiAspmCtrl 1 bytes $_DEFAULT_ = 0x2 + $gPlatformFspPkgTokenSpaceGuid_DmiAspmL1ExitLatency 1 bytes $_DEFAULT_ = 0x4 + $gPlatformFspPkgTokenSpaceGuid_BistOnReset 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_SkipStopPbet 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_EnableC6Dram 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_OcSupport 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_OcLock 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_CoreMaxOcRatio 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_CoreVoltageMode 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_RingMaxOcRatio 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_HyperThreading 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_CpuRatioOverride 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_CpuRatio 1 bytes $_DEFAULT_ = 0x1C + $gPlatformFspPkgTokenSpaceGuid_BootFrequency 1 bytes $_DEFAULT_ = 0x02 + $gPlatformFspPkgTokenSpaceGuid_ActiveCoreCount 1 bytes $_DEFAULT_ = 0xFF + $gPlatformFspPkgTokenSpaceGuid_FClkFrequency 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_JtagC10PowerGateDisable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_VmxEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_Avx2RatioOffset 1 bytes $_DEFAULT_ = 0 + $gPlatformFspPkgTokenSpaceGuid_Avx3RatioOffset 1 bytes $_DEFAULT_ = 0 + $gPlatformFspPkgTokenSpaceGuid_BclkAdaptiveVoltage 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_CoreVoltageOverride 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_CoreVoltageAdaptive 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_CoreVoltageOffset 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_CorePllVoltageOffset 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_AtomPllVoltageOffset 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_RingDownBin 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_RingVoltageMode 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_TjMaxOffset 1 bytes $_DEFAULT_ = 0x00 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_RingVoltageOverride 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_RingVoltageAdaptive 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_RingVoltageOffset 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_TmeEnable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_CpuCrashLogEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_DebugInterfaceEnable 1 bytes $_DEFAULT_ = 0x02 + $gPlatformFspPkgTokenSpaceGuid_DebugInterfaceLockEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_AtomL2VoltageMode 1 bytes $_DEFAULT_ = 0x00 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_AtomL2VoltageOverride 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_AtomL2VoltageAdaptive 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_AtomL2VoltageOffset 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PerAtomClusterVoltageOffset 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_PerAtomClusterVoltageOffsetPrefix 4 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_IaCepEnable 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_GtCepEnable 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_DlvrBypassModeEnable 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_ActiveSmallCoreCount 1 bytes $_DEFAULT_ = 0xFF + $gPlatformFspPkgTokenSpaceGuid_CoreVfPointOffsetMode 1 bytes $_DEFAULT_ = 0x00 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_CoreVfPointOffset 30 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_CoreVfPointOffsetPrefix 15 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_CoreVfPointRatio 15 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_CoreVfPointCount 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_CoreVfConfigScope 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PerCoreVoltageOffset 16 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_PerCoreVoltageOffsetPrefix 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PerCoreRatioOverride 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PerCoreRatio 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_AtomClusterRatio 4 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_CoreRatioExtensionMode 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PvdRatioThreshold 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_UnlimitedIccMax 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_CrashLogGprs 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_RingVfPointOffsetMode 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_RingVfPointOffset 30 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_RingVfPointOffsetPrefix 15 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_RingVfPointRatio 15 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_RingVfPointCount 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_BclkSource 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_GpioOverride 1 bytes $_DEFAULT_ = 0x00 + Skip 3 bytes + $gPlatformFspPkgTokenSpaceGuid_CpuBclkOcFrequency 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_DisablePerCoreMask 4 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_DisablePerAtomMask 4 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_SaPllFreqOverride 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_SiSkipOverrideBootModeWhenFwUpdate 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_TscDisableHwFixup 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_IaIccUnlimitedMode 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_IaIccMax 2 bytes $_DEFAULT_ = 0x04 + $gPlatformFspPkgTokenSpaceGuid_GtIccUnlimitedMode 1 bytes $_DEFAULT_ = 0x00 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_GtIccMax 2 bytes $_DEFAULT_ = 0x04 + $gPlatformFspPkgTokenSpaceGuid_TvbDownBinsTempThreshold0 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_TvbTempThreshold0 1 bytes $_DEFAULT_ = 0x46 + $gPlatformFspPkgTokenSpaceGuid_TvbTempThreshold1 1 bytes $_DEFAULT_ = 0x64 + $gPlatformFspPkgTokenSpaceGuid_TvbDownBinsTempThreshold1 1 bytes $_DEFAULT_ = 0x02 + $gPlatformFspPkgTokenSpaceGuid_FllOcModeEn 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_FllOverclockMode 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_ConfigTdpLevel 1 bytes $_DEFAULT_ = 0x00 + Skip 3 bytes + $gPlatformFspPkgTokenSpaceGuid_CustomPowerLimit1 4 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_Etvb 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_UnderVoltProtection 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_ReservedCpuPreMem 6 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_BiosGuard 1 bytes $_DEFAULT_ = 0x01 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_Txt 1 bytes $_DEFAULT_ = 0x00 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_PrmrrSize 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_SinitMemorySize 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_TxtDprMemoryBase 8 bytes $_DEFAULT_ = 0x0000000000000000 + $gPlatformFspPkgTokenSpaceGuid_TxtHeapMemorySize 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_TxtDprMemorySize 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_BiosAcmBase 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_BiosAcmSize 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_ApStartupBase 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_TgaSize 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_TxtLcpPdBase 8 bytes $_DEFAULT_ = 0x0000000000000000 + $gPlatformFspPkgTokenSpaceGuid_TxtLcpPdSize 8 bytes $_DEFAULT_ = 0x0000000000000000 + $gPlatformFspPkgTokenSpaceGuid_IsTPMPresence 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_ReservedSecurityPreMem 32 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioRxSetCtleEnable 28 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioRxSetCtle 28 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen1DownscaleAmpEnable 28 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen1DownscaleAmp 28 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DownscaleAmpEnable 28 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DownscaleAmp 28 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen3DownscaleAmpEnable 28 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen3DownscaleAmp 28 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen1DeEmphEnable 28 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen1DeEmph 28 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DeEmph3p5Enable 28 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DeEmph3p5 28 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DeEmph6p0Enable 28 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DeEmph6p0 28 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen1EqBoostMagEnable 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen1EqBoostMag 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen2EqBoostMagEnable 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen2EqBoostMag 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen3EqBoostMagEnable 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen3EqBoostMag 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen1DownscaleAmpEnable 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen1DownscaleAmp 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen2DownscaleAmpEnable 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen2DownscaleAmp 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen3DownscaleAmpEnable 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen3DownscaleAmp 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen1DeEmphEnable 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen1DeEmph 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen2DeEmphEnable 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen2DeEmph 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen3DeEmphEnable 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen3DeEmph 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchLpcEnhancePort8xhDecoding 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchPort80Route 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_SmbusArpEnable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchNumRsvdSmbusAddresses 1 bytes $_DEFAULT_ = 0x00 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_PchSmbusIoBase 2 bytes $_DEFAULT_ = 0xEFA0 + $gPlatformFspPkgTokenSpaceGuid_PchSmbAlertEnable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieClkSrcUsage 18 bytes $_DEFAULT_ = 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF + Skip 14 bytes + $gPlatformFspPkgTokenSpaceGuid_PcieClkSrcClkReq 18 bytes $_DEFAULT_ = 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 0x00, 0x01 + Skip 17 bytes + $gPlatformFspPkgTokenSpaceGuid_PcieClkReqGpioMux 72 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_RsvdSmbusAddressTablePtr 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_PcieRpEnableMask 4 bytes $_DEFAULT_ = 0x00FFFFFF + $gPlatformFspPkgTokenSpaceGuid_PchHdaVcType 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchHdaDspUaaCompliance 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkHdaEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchHdaSdiEnable 2 bytes $_DEFAULT_ = 0x01, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchHdaTestPowerClockGating 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkDmicEnable 2 bytes $_DEFAULT_ = 0x01, 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkDmicClkAPinMux 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkDmicClkBPinMux 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_PchHdaDspEnable 1 bytes $_DEFAULT_ = 0x01 + Skip 3 bytes + $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkDmicDataPinMux 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSspEnable 6 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSndwEnable 4 bytes $_DEFAULT_ = 0x01, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchHdaIDispLinkFrequency 1 bytes $_DEFAULT_ = 0x04 + $gPlatformFspPkgTokenSpaceGuid_PchHdaIDispLinkTmode 1 bytes $_DEFAULT_ = 0x03 + $gPlatformFspPkgTokenSpaceGuid_PchHdaIDispCodecDisconnect 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_CnviDdrRfim 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PcdDebugInterfaceFlags 1 bytes $_DEFAULT_ = 0x32 + $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugControllerNumber 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugAutoFlow 1 bytes $_DEFAULT_ = 0x0 + Skip 3 bytes + $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugBaudRate 4 bytes $_DEFAULT_ = 115200 + $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugParity 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugStopBits 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugDataBits 1 bytes $_DEFAULT_ = 0x8 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugMmioBase 4 bytes $_DEFAULT_ = 0xFE036000 + $gPlatformFspPkgTokenSpaceGuid_PcdIsaSerialUartBase 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_GtPllVoltageOffset 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_RingPllVoltageOffset 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_SaPllVoltageOffset 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_McPllVoltageOffset 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_MrcSafeConfig 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_TcssItbtPcie0En 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_TcssItbtPcie1En 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_TcssItbtPcie2En 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_TcssItbtPcie3En 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_TcssXhciEn 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_TcssXdciEn 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_TcssDma0En 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_TcssDma1En 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugBaudRate 1 bytes $_DEFAULT_ = 0x07 + $gPlatformFspPkgTokenSpaceGuid_HobBufferSize 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_ECT 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_SOT 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_ERDMPRTC2D 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_RDMPRT 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_RCVET 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_JWRL 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_EWRTC2D 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_ERDTC2D 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_WRTC1D 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_WRVC1D 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_RDTC1D 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_DIMMODTT 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_DIMMRONT 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_WRDSEQT 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_WRSRT 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_RDODTT 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_RDEQT 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_RDAPT 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_WRTC2D 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_RDTC2D 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_WRVC2D 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_RDVC2D 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_CMDVC 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_LCT 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_RTL 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_TAT 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_MEMTST 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_ALIASCHK 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_RCVENC1D 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_RMC 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_WRDSUDT 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_EccSupport 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_RemapEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_RankInterleave 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_EnhancedInterleave 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_ChHashEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_ChHashOverride 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_EnableExtts 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_EnablePwrDn 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_EnablePwrDnLpddr 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_SrefCfgEna 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_ThrtCkeMinDefeatLpddr 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_ThrtCkeMinDefeat 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_RhSelect 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_ExitOnFailure 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_NewFeatureEnable1 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_NewFeatureEnable2 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_DCC 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_RDVC1D 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_TXTCO 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_CLKTCO 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_CMDSR 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_CMDDSEQ 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_DIMMODTCA 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_TXTCODQS 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_CMDDRUD 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_VCCDLLBP 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PVTTDNLP 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_RDVREFDC 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_VDDQT 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_RMTBIT 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_EccDftEn 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_Write0 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_Ddr4DdpSharedClock 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_Ddr4DdpSharedZq 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_ChHashInterleaveBit 1 bytes $_DEFAULT_ = 0x02 + $gPlatformFspPkgTokenSpaceGuid_ChHashMask 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_BClkFrequency 4 bytes $_DEFAULT_ = 100000000 + $gPlatformFspPkgTokenSpaceGuid_Idd3n 2 bytes $_DEFAULT_ = 0x1A + $gPlatformFspPkgTokenSpaceGuid_Idd3p 2 bytes $_DEFAULT_ = 0x0B + $gPlatformFspPkgTokenSpaceGuid_CMDNORM 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_EWRDSEQ 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_McRefresh2X 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_IdleEnergyMc0Ch0Dimm0 1 bytes $_DEFAULT_ = 0x0A + $gPlatformFspPkgTokenSpaceGuid_IdleEnergyMc0Ch0Dimm1 1 bytes $_DEFAULT_ = 0x0A + $gPlatformFspPkgTokenSpaceGuid_IdleEnergyMc0Ch1Dimm0 1 bytes $_DEFAULT_ = 0x0A + $gPlatformFspPkgTokenSpaceGuid_IdleEnergyMc0Ch1Dimm1 1 bytes $_DEFAULT_ = 0x0A + $gPlatformFspPkgTokenSpaceGuid_IdleEnergyMc1Ch0Dimm0 1 bytes $_DEFAULT_ = 0x0A + $gPlatformFspPkgTokenSpaceGuid_IdleEnergyMc1Ch0Dimm1 1 bytes $_DEFAULT_ = 0x0A + $gPlatformFspPkgTokenSpaceGuid_IdleEnergyMc1Ch1Dimm0 1 bytes $_DEFAULT_ = 0x0A + $gPlatformFspPkgTokenSpaceGuid_IdleEnergyMc1Ch1Dimm1 1 bytes $_DEFAULT_ = 0x0A + $gPlatformFspPkgTokenSpaceGuid_PdEnergyMc0Ch0Dimm0 1 bytes $_DEFAULT_ = 0x06 + $gPlatformFspPkgTokenSpaceGuid_PdEnergyMc0Ch0Dimm1 1 bytes $_DEFAULT_ = 0x06 + $gPlatformFspPkgTokenSpaceGuid_PdEnergyMc0Ch1Dimm0 1 bytes $_DEFAULT_ = 0x06 + $gPlatformFspPkgTokenSpaceGuid_PdEnergyMc0Ch1Dimm1 1 bytes $_DEFAULT_ = 0x06 + $gPlatformFspPkgTokenSpaceGuid_PdEnergyMc1Ch0Dimm0 1 bytes $_DEFAULT_ = 0x06 + $gPlatformFspPkgTokenSpaceGuid_PdEnergyMc1Ch0Dimm1 1 bytes $_DEFAULT_ = 0x06 + $gPlatformFspPkgTokenSpaceGuid_PdEnergyMc1Ch1Dimm0 1 bytes $_DEFAULT_ = 0x06 + $gPlatformFspPkgTokenSpaceGuid_PdEnergyMc1Ch1Dimm1 1 bytes $_DEFAULT_ = 0x06 + $gPlatformFspPkgTokenSpaceGuid_ActEnergyMc0Ch0Dimm0 1 bytes $_DEFAULT_ = 0xAC + $gPlatformFspPkgTokenSpaceGuid_ActEnergyMc0Ch0Dimm1 1 bytes $_DEFAULT_ = 0xAC + $gPlatformFspPkgTokenSpaceGuid_ActEnergyMc0Ch1Dimm0 1 bytes $_DEFAULT_ = 0xAC + $gPlatformFspPkgTokenSpaceGuid_ActEnergyMc0Ch1Dimm1 1 bytes $_DEFAULT_ = 0xAC + $gPlatformFspPkgTokenSpaceGuid_ActEnergyMc1Ch0Dimm0 1 bytes $_DEFAULT_ = 0xAC + $gPlatformFspPkgTokenSpaceGuid_ActEnergyMc1Ch0Dimm1 1 bytes $_DEFAULT_ = 0xAC + $gPlatformFspPkgTokenSpaceGuid_ActEnergyMc1Ch1Dimm0 1 bytes $_DEFAULT_ = 0xAC + $gPlatformFspPkgTokenSpaceGuid_ActEnergyMc1Ch1Dimm1 1 bytes $_DEFAULT_ = 0xAC + $gPlatformFspPkgTokenSpaceGuid_RdEnergyMc0Ch0Dimm0 1 bytes $_DEFAULT_ = 0xD4 + $gPlatformFspPkgTokenSpaceGuid_RdEnergyMc0Ch0Dimm1 1 bytes $_DEFAULT_ = 0xD4 + $gPlatformFspPkgTokenSpaceGuid_RdEnergyMc0Ch1Dimm0 1 bytes $_DEFAULT_ = 0xD4 + $gPlatformFspPkgTokenSpaceGuid_RdEnergyMc0Ch1Dimm1 1 bytes $_DEFAULT_ = 0xD4 + $gPlatformFspPkgTokenSpaceGuid_RdEnergyMc1Ch0Dimm0 1 bytes $_DEFAULT_ = 0xD4 + $gPlatformFspPkgTokenSpaceGuid_RdEnergyMc1Ch0Dimm1 1 bytes $_DEFAULT_ = 0xD4 + $gPlatformFspPkgTokenSpaceGuid_RdEnergyMc1Ch1Dimm0 1 bytes $_DEFAULT_ = 0xD4 + $gPlatformFspPkgTokenSpaceGuid_RdEnergyMc1Ch1Dimm1 1 bytes $_DEFAULT_ = 0xD4 + $gPlatformFspPkgTokenSpaceGuid_WrEnergyMc0Ch0Dimm0 1 bytes $_DEFAULT_ = 0xDD + $gPlatformFspPkgTokenSpaceGuid_WrEnergyMc0Ch0Dimm1 1 bytes $_DEFAULT_ = 0xDD + $gPlatformFspPkgTokenSpaceGuid_WrEnergyMc0Ch1Dimm0 1 bytes $_DEFAULT_ = 0xDD + $gPlatformFspPkgTokenSpaceGuid_WrEnergyMc0Ch1Dimm1 1 bytes $_DEFAULT_ = 0xDD + $gPlatformFspPkgTokenSpaceGuid_WrEnergyMc1Ch0Dimm0 1 bytes $_DEFAULT_ = 0xDD + $gPlatformFspPkgTokenSpaceGuid_WrEnergyMc1Ch0Dimm1 1 bytes $_DEFAULT_ = 0xDD + $gPlatformFspPkgTokenSpaceGuid_WrEnergyMc1Ch1Dimm0 1 bytes $_DEFAULT_ = 0xDD + $gPlatformFspPkgTokenSpaceGuid_WrEnergyMc1Ch1Dimm1 1 bytes $_DEFAULT_ = 0xDD + $gPlatformFspPkgTokenSpaceGuid_ThrtCkeMinTmr 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_AllowOppRefBelowWriteThrehold 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_WriteThreshold 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_RaplPwrFlCh0 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_RaplPwrFlCh1 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_EnCmdRate 1 bytes $_DEFAULT_ = 0x07 + $gPlatformFspPkgTokenSpaceGuid_Refresh2X 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_EpgEnable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_Lfsr0Mask 1 bytes $_DEFAULT_ = 0xB + $gPlatformFspPkgTokenSpaceGuid_UserThresholdEnable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_UserBudgetEnable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PowerDownMode 1 bytes $_DEFAULT_ = 0xFF + $gPlatformFspPkgTokenSpaceGuid_PwdwnIdleCounter 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_DisPgCloseIdleTimeout 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_CmdRanksTerminated 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugLevel 1 bytes $_DEFAULT_ = 0x03 + $gPlatformFspPkgTokenSpaceGuid_SafeMode 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_CleanMemory 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_LpDdrDqDqsReTraining 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_UsbTcPortEnPreMem 1 bytes $_DEFAULT_ = 0x00 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_PostCodeOutputPort 2 bytes $_DEFAULT_ = 0x80 + $gPlatformFspPkgTokenSpaceGuid_RMTLoopCount 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_CridEnable 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_WrcFeatureEnable 1 bytes $_DEFAULT_ = 0x01 + Skip 3 bytes + $gPlatformFspPkgTokenSpaceGuid_BclkRfiFreq 16 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieImrSize 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieImrEnabled 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieImrRpLocation 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PcieImrRpSelection 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_SerialDebugMrcLevel 1 bytes $_DEFAULT_ = 0x03 + $gPlatformFspPkgTokenSpaceGuid_Ddr4OneDpc 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_Lfsr1Mask 1 bytes $_DEFAULT_ = 0xB + $gPlatformFspPkgTokenSpaceGuid_LpddrRttWr 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_LpddrRttCa 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_RefreshPanicWm 1 bytes $_DEFAULT_ = 0x08 + $gPlatformFspPkgTokenSpaceGuid_RefreshHpWm 1 bytes $_DEFAULT_ = 0x07 + $gPlatformFspPkgTokenSpaceGuid_Lp5CccConfig 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_CmdMirror 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_DIMMDFE 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_ExtendedBankHashing 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_RefreshWm 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_McRefreshRate 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PeriodicDcc 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_LpMode 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_TXDQSDCC 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_DRAMDCA 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_EARLYDIMMDFE 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_SkipExtGfxScan 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_BdatEnable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_LockPTMregs 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PegGen3Rsvd 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PanelPowerEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_BdatTestType 1 bytes $_DEFAULT_ = 0x00 + Skip 3 bytes + $gPlatformFspPkgTokenSpaceGuid_DmaBufferSize 4 bytes $_DEFAULT_ = 0x0400000 + $gPlatformFspPkgTokenSpaceGuid_PreBootDmaMask 1 bytes $_DEFAULT_ = 0x0 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_DeltaT12PowerCycleDelay 2 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_ReuseAdlSDdr5Board 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_OemT12DelayOverride 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_SaPreMemTestRsvd 89 bytes $_DEFAULT_ = 0x00 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_TotalFlashSize 2 bytes $_DEFAULT_ = 0x0000 + $gPlatformFspPkgTokenSpaceGuid_BiosSize 2 bytes $_DEFAULT_ = 0x2800 + $gPlatformFspPkgTokenSpaceGuid_SecurityTestRsvd 12 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_SmbusDynamicPowerGating 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_WdtDisableAndLock 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_SmbusSpdWriteDisable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_DidInitStat 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_DisableCpuReplacedPolling 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_DisableMessageCheck 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_SkipMbpHob 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_HeciCommunication2 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_KtDeviceEnable 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_SkipCpuReplacementCheck 1 bytes $_DEFAULT_ = 0x00 + Skip 2 bytes + $gPlatformFspPkgTokenSpaceGuid_CpuPcie1Rtd3Gpio 96 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_CpuPcie2Rtd3Gpio 96 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_CpuPcie3Rtd3Gpio 96 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_Avx2VoltageScaleFactor 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_Avx512VoltageScaleFactor 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugMode 1 bytes $_DEFAULT_ = 0x02 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugRxPinMux 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugTxPinMux 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugRtsPinMux 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugCtsPinMux 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PprEnable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_MarginLimitCheck 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_MarginLimitL2 2 bytes $_DEFAULT_ = 100 + $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpCdrRelock 4 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01 + $gPlatformFspPkgTokenSpaceGuid_DmiCdrRelock 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_IbeccErrInjControl 1 bytes $_DEFAULT_ = 0x0 + Skip 6 bytes + $gPlatformFspPkgTokenSpaceGuid_IbeccErrInjAddress 8 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_IbeccErrInjMask 8 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_IbeccErrInjCount 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_EnableDmaBuffer 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PllMaxBandingRatio 1 bytes $_DEFAULT_ = 0x00 + Skip 3 bytes + $gPlatformFspPkgTokenSpaceGuid_DebugValue 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_BoardGpioTablePreMemAddress 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_tRFCpb 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_tRFC2 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_tRFC4 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_tRRD_L 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_tRRD_S 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_tWTR_L 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_tCCD_L 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_tWTR_S 1 bytes $_DEFAULT_ = 0x00 + Skip 5 bytes + $gPlatformFspPkgTokenSpaceGuid_EccErrInjAddress 8 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_EccErrInjMask 8 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_EccErrInjCount 4 bytes $_DEFAULT_ = 0xF + $gPlatformFspPkgTokenSpaceGuid_FreqLimitMixedConfig 2 bytes $_DEFAULT_ = 0x0000 + $gPlatformFspPkgTokenSpaceGuid_FirstDimmBitMask 1 bytes $_DEFAULT_ = 0x0A + $gPlatformFspPkgTokenSpaceGuid_SagvSwitchFactorIA 1 bytes $_DEFAULT_ = 0x1E + $gPlatformFspPkgTokenSpaceGuid_SagvSwitchFactorGT 1 bytes $_DEFAULT_ = 0x1E + $gPlatformFspPkgTokenSpaceGuid_SagvSwitchFactorIO 1 bytes $_DEFAULT_ = 0x1E + $gPlatformFspPkgTokenSpaceGuid_SagvSwitchFactorStall 1 bytes $_DEFAULT_ = 0x1E + $gPlatformFspPkgTokenSpaceGuid_SagvHeuristicsDownControl 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_SagvHeuristicsUpControl 1 bytes $_DEFAULT_ = 0x01 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_FreqLimitMixedConfig_1R1R_8GB 2 bytes $_DEFAULT_ = 0x07D0 + $gPlatformFspPkgTokenSpaceGuid_FreqLimitMixedConfig_1R1R_16GB 2 bytes $_DEFAULT_ = 0x07D0 + $gPlatformFspPkgTokenSpaceGuid_FreqLimitMixedConfig_1R1R_8GB_16GB 2 bytes $_DEFAULT_ = 0x07D0 + $gPlatformFspPkgTokenSpaceGuid_FreqLimitMixedConfig_2R2R 2 bytes $_DEFAULT_ = 0x07D0 + $gPlatformFspPkgTokenSpaceGuid_PchDmiHwEqGen3CoeffListCm 8 bytes $_DEFAULT_ = 0x06, 0x05, 0x02, 0x09, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchDmiHwEqGen3CoeffListCp 8 bytes $_DEFAULT_ = 0x05, 0x03, 0x07, 0x08, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_LctCmdEyeWidth 2 bytes $_DEFAULT_ = 0x60 + $gPlatformFspPkgTokenSpaceGuid_ThrtCkeMinTmrLpddr 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_FirstDimmBitMaskEcc 1 bytes $_DEFAULT_ = 0x0A + $gPlatformFspPkgTokenSpaceGuid_Lp5BankMode 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_WRDS 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_OverloadSAM 1 bytes $_DEFAULT_ = 0x00 + + Find "ADLUPD_S" + $gPlatformFspPkgTokenSpaceGuid_Revision 1 bytes $_DEFAULT_ = 0x02 + Skip 55 bytes + $gPlatformFspPkgTokenSpaceGuid_LogoPtr 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_LogoSize 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_BltBufferAddress 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_BltBufferSize 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_GraphicsConfigPtr 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_Device4Enable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_ShowSpiController 1 bytes $_DEFAULT_ = 0x00 + Skip 2 bytes + $gPlatformFspPkgTokenSpaceGuid_MicrocodeRegionBase 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_MicrocodeRegionSize 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_TurboMode 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_SataSalpSupport 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_SataPortsEnable 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_SataPortsDevSlp 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + Skip 2 bytes + $gPlatformFspPkgTokenSpaceGuid_SataPortDevSlpPinMux 32 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_PortUsb20Enable 16 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 + $gPlatformFspPkgTokenSpaceGuid_PortUsb30Enable 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_XdciEnable 1 bytes $_DEFAULT_ = 0x00 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_DevIntConfigPtr 4 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_NumOfDevIntConfig 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PxRcConfig 8 bytes $_DEFAULT_ = 0x0B, 0x0A, 0x0B, 0x0B, 0x0B, 0x0B, 0x0B, 0x0B + $gPlatformFspPkgTokenSpaceGuid_GpioIrqRoute 1 bytes $_DEFAULT_ = 0x0E + $gPlatformFspPkgTokenSpaceGuid_SciIrqSelect 1 bytes $_DEFAULT_ = 0x09 + $gPlatformFspPkgTokenSpaceGuid_TcoIrqSelect 1 bytes $_DEFAULT_ = 0x09 + $gPlatformFspPkgTokenSpaceGuid_TcoIrqEnable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchHdaVerbTableEntryNum 1 bytes $_DEFAULT_ = 0 + Skip 2 bytes + $gPlatformFspPkgTokenSpaceGuid_PchHdaVerbTablePtr 4 bytes $_DEFAULT_ = 0 + $gPlatformFspPkgTokenSpaceGuid_PchHdaCodecSxWakeCapability 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_SataEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_SataMode 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_SerialIoSpiMode 7 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_SerialIoSpiCsPolarity 14 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 + $gPlatformFspPkgTokenSpaceGuid_SerialIoSpiCsEnable 14 bytes $_DEFAULT_ = 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00 + $gPlatformFspPkgTokenSpaceGuid_SerialIoSpiDefaultCsOutput 7 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_SerialIoSpiCsMode 7 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_SerialIoSpiCsState 7 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_SerialIoUartMode 7 bytes $_DEFAULT_ = 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00 + Skip 2 bytes + $gPlatformFspPkgTokenSpaceGuid_SerialIoUartBaudRate 28 bytes $_DEFAULT_ = 0x00,0xC2,0x01,0x00,0x00,0xC2,0x01,0x00,0x00,0xC2,0x01,0x00,0x00,0xC2,0x01,0x00,0x00,0xC2,0x01,0x00,0x00,0xC2,0x01,0x00,0x00,0xC2,0x01,0x00 + $gPlatformFspPkgTokenSpaceGuid_SerialIoUartParity 7 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 + $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDataBits 7 bytes $_DEFAULT_ = 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08 + $gPlatformFspPkgTokenSpaceGuid_SerialIoUartStopBits 7 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 + $gPlatformFspPkgTokenSpaceGuid_SerialIoUartPowerGating 7 bytes $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02 + $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDmaEnable 7 bytes $_DEFAULT_ = 0x01, 0x01, 0x00, 0x01, 0x01, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_SerialIoUartAutoFlow 7 bytes $_DEFAULT_ = 0x01, 0x01, 0x00, 0x01, 0x01, 0x00, 0x00 + Skip 2 bytes + $gPlatformFspPkgTokenSpaceGuid_SerialIoUartRtsPinMuxPolicy 28 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_SerialIoUartCtsPinMuxPolicy 28 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_SerialIoUartRxPinMuxPolicy 28 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_SerialIoUartTxPinMuxPolicy 28 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_SerialIoDebugUartNumber 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDbg2 7 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_SerialIoI2cMode 8 bytes $_DEFAULT_ = 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchSerialIoI2cSdaPinMux 32 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_PchSerialIoI2cSclPinMux 32 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_PchSerialIoI2cPadsTermination 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_IshGpGpioPinMuxing 32 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_IshUartRxPinMuxing 12 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_IshUartTxPinMuxing 12 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_IshUartRtsPinMuxing 12 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_IshUartCtsPinMuxing 12 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_IshI2cSdaPinMuxing 12 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_IshI2cSclPinMuxing 12 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_IshSpiMosiPinMuxing 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_IshSpiMisoPinMuxing 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_IshSpiClkPinMuxing 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_IshSpiCsPinMuxing 16 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_IshGpGpioPadTermination 8 bytes $_DEFAULT_ = 0, 0, 0, 0, 0, 0, 0, 0 + $gPlatformFspPkgTokenSpaceGuid_IshUartRxPadTermination 3 bytes $_DEFAULT_ = 0, 0, 0 + $gPlatformFspPkgTokenSpaceGuid_IshUartTxPadTermination 3 bytes $_DEFAULT_ = 0, 0, 0 + $gPlatformFspPkgTokenSpaceGuid_IshUartRtsPadTermination 3 bytes $_DEFAULT_ = 0, 0, 0 + $gPlatformFspPkgTokenSpaceGuid_IshUartCtsPadTermination 3 bytes $_DEFAULT_ = 0, 0, 0 + $gPlatformFspPkgTokenSpaceGuid_IshI2cSdaPadTermination 3 bytes $_DEFAULT_ = 0, 0, 0 + $gPlatformFspPkgTokenSpaceGuid_IshI2cSclPadTermination 3 bytes $_DEFAULT_ = 0, 0, 0 + $gPlatformFspPkgTokenSpaceGuid_IshSpiMosiPadTermination 2 bytes $_DEFAULT_ = 0, 0 + $gPlatformFspPkgTokenSpaceGuid_IshSpiMisoPadTermination 2 bytes $_DEFAULT_ = 0, 0 + $gPlatformFspPkgTokenSpaceGuid_IshSpiClkPadTermination 2 bytes $_DEFAULT_ = 0, 0 + $gPlatformFspPkgTokenSpaceGuid_IshSpiCsPadTermination 4 bytes $_DEFAULT_ = 0, 0, 0, 0 + $gPlatformFspPkgTokenSpaceGuid_PchIshSpiCsEnable 4 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_Usb2PhyPetxiset 16 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_Usb2PhyTxiset 16 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_Usb2PhyPredeemp 16 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_Usb2PhyPehalfbit 16 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxDeEmphEnable 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxDeEmph 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxDownscaleAmpEnable 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxDownscaleAmp 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + Skip 80 bytes + $gPlatformFspPkgTokenSpaceGuid_PchLanEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchTsnEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchTsnLinkSpeed 1 bytes $_DEFAULT_ = 0x02 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_PchTsnMacAddressHigh 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_PchTsnMacAddressLow 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_PciePtm 28 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 + $gPlatformFspPkgTokenSpaceGuid_PcieDpc 28 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieEdpc 28 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 + $gPlatformFspPkgTokenSpaceGuid_UsbPdoProgramming 1 bytes $_DEFAULT_ = 0x01 + Skip 3 bytes + $gPlatformFspPkgTokenSpaceGuid_PmcPowerButtonDebounce 4 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchEspiBmeMasterSlaveEnabled 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchEspiLockLinkConfiguration 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchFivrExtV1p05RailEnabledStates 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PchFivrExtV1p05RailSupportedVoltageStates 1 bytes $_DEFAULT_ = 0x2 + $gPlatformFspPkgTokenSpaceGuid_PchFivrExtV1p05RailVoltage 2 bytes $_DEFAULT_ = 0x01A4 + $gPlatformFspPkgTokenSpaceGuid_PchFivrExtV1p05RailIccMax 1 bytes $_DEFAULT_ = 0x64 + $gPlatformFspPkgTokenSpaceGuid_PchFivrExtVnnRailEnabledStates 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PchFivrExtVnnRailSupportedVoltageStates 1 bytes $_DEFAULT_ = 0x2 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_PchFivrExtVnnRailVoltage 2 bytes $_DEFAULT_ = 0x01A4 + $gPlatformFspPkgTokenSpaceGuid_PchFivrExtVnnRailIccMax 1 bytes $_DEFAULT_ = 0xC8 + $gPlatformFspPkgTokenSpaceGuid_PchFivrExtVnnRailSxEnabledStates 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PchFivrExtVnnRailSxVoltage 2 bytes $_DEFAULT_ = 0x01A4 + $gPlatformFspPkgTokenSpaceGuid_PchFivrExtVnnRailSxIccMax 1 bytes $_DEFAULT_ = 0xC8 + $gPlatformFspPkgTokenSpaceGuid_PchFivrVccinAuxLowToHighCurModeVolTranTime 1 bytes $_DEFAULT_ = 0x0C + $gPlatformFspPkgTokenSpaceGuid_PchFivrVccinAuxRetToHighCurModeVolTranTime 1 bytes $_DEFAULT_ = 0x036 + $gPlatformFspPkgTokenSpaceGuid_PchFivrVccinAuxRetToLowCurModeVolTranTime 1 bytes $_DEFAULT_ = 0x2B + $gPlatformFspPkgTokenSpaceGuid_PchFivrVccinAuxOffToHighCurModeVolTranTime 2 bytes $_DEFAULT_ = 0x0096 + $gPlatformFspPkgTokenSpaceGuid_PmcDbgMsgEn 1 bytes $_DEFAULT_ = 0x00 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_ChipsetInitBinPtr 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_ChipsetInitBinLen 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_PchFivrDynPm 1 bytes $_DEFAULT_ = 0x01 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_PchFivrExtV1p05RailIccMaximum 2 bytes $_DEFAULT_ = 0x1F4 + $gPlatformFspPkgTokenSpaceGuid_PchFivrExtVnnRailIccMaximum 2 bytes $_DEFAULT_ = 0x1F4 + $gPlatformFspPkgTokenSpaceGuid_PchFivrExtVnnRailSxIccMaximum 2 bytes $_DEFAULT_ = 0x1F4 + $gPlatformFspPkgTokenSpaceGuid_PchSpiExtendedBiosDecodeRangeEnable 1 bytes $_DEFAULT_ = 0x00 + Skip 3 bytes + $gPlatformFspPkgTokenSpaceGuid_PchSpiExtendedBiosDecodeRangeBase 4 bytes $_DEFAULT_ = 0xF8000000 + $gPlatformFspPkgTokenSpaceGuid_PchSpiExtendedBiosDecodeRangeLimit 4 bytes $_DEFAULT_ = 0xF9FFFFFF + $gPlatformFspPkgTokenSpaceGuid_PchXhciUaolEnable 1 bytes $_DEFAULT_ = 0x01 + Skip 3 bytes + $gPlatformFspPkgTokenSpaceGuid_SynpsPhyBinPtr 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_SynpsPhyBinLen 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_CnviMode 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_CnviWifiCore 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_CnviBtCore 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_CnviBtAudioOffload 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_CnviRfResetPinMux 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_CnviClkreqPinMux 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PchEspiHostC10ReportEnable 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PmcUsb2PhySusPgEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchUsbOverCurrentEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchEspiLgmrEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchFivrExtV1p05RailCtrlRampTmr 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_PchFivrExtVnnRailCtrlRampTmr 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_SataPortsDevSlpResetConfig 8 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchHotEnable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_SataLedEnable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPmVrAlert 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_AmtEnabled 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_WatchDogEnabled 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_FwProgress 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_AmtSolEnabled 1 bytes $_DEFAULT_ = 0x0 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_WatchDogTimerOs 2 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_WatchDogTimerBios 2 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_ForcMebxSyncUp 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PcieRpSlotImplemented 28 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 + $gPlatformFspPkgTokenSpaceGuid_PcieRpAcsEnabled 28 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 + $gPlatformFspPkgTokenSpaceGuid_PcieRpEnableCpm 28 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_PcieRpDetectTimeoutMs 56 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_PmcModPhySusPgEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PmcV1p05PhyExtFetControlEn 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PmcV1p05IsExtFetControlEn 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PavpEnable 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_CdClock 1 bytes $_DEFAULT_ = 0xFF + $gPlatformFspPkgTokenSpaceGuid_PeiGraphicsPeimInit 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_D3HotEnable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_GnaEnable 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_IomTypeCPortPadCfg 32 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x06,0x11,0x00,0x04,0x06,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_CpuUsb3OverCurrentPin 8 bytes $_DEFAULT_ = 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF + $gPlatformFspPkgTokenSpaceGuid_D3ColdEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_ITbtPcieTunnelingForUsb4 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_SkipFspGop 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_TcCstateLimit 1 bytes $_DEFAULT_ = 0x0A + $gPlatformFspPkgTokenSpaceGuid_VbtSize 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_LidStatus 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_IomStayInTCColdSeconds 1 bytes $_DEFAULT_ = 0x32 + $gPlatformFspPkgTokenSpaceGuid_IomBeforeEnteringTCColdSeconds 1 bytes $_DEFAULT_ = 0x0A + $gPlatformFspPkgTokenSpaceGuid_SaPostMemRsvd 5 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchXhciHsiiEnable 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_VmdEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_VmdPort 31 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_VmdPortDev 31 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_VmdPortFunc 31 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_VmdCfgBarSize 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_VmdCfgBarAttr 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_VmdMemBarSize1 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_VmdMemBar1Attr 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_VmdMemBarSize2 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_VmdMemBar2Attr 1 bytes $_DEFAULT_ = 0x00 + Skip 3 bytes + $gPlatformFspPkgTokenSpaceGuid_VmdVariablePtr 4 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_VmdCfgBarBase 4 bytes $_DEFAULT_ = 0xA0000000 + $gPlatformFspPkgTokenSpaceGuid_VmdMemBar1Base 4 bytes $_DEFAULT_ = 0xA2000000 + $gPlatformFspPkgTokenSpaceGuid_VmdMemBar2Base 4 bytes $_DEFAULT_ = 0xA4000000 + $gPlatformFspPkgTokenSpaceGuid_TcssCpuUsbPdoProgramming 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PmcPdEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_TcssAuxOri 2 bytes $_DEFAULT_ = 0x0000 + $gPlatformFspPkgTokenSpaceGuid_TcssHslOri 2 bytes $_DEFAULT_ = 0x0000 + $gPlatformFspPkgTokenSpaceGuid_UsbOverride 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_ITbtPcieRootPortEn 4 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_UsbTcPortEn 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_ITbtForcePowerOnTimeoutInMs 2 bytes $_DEFAULT_ = 0x1F4 + $gPlatformFspPkgTokenSpaceGuid_ITbtConnectTopologyTimeoutInMs 2 bytes $_DEFAULT_ = 0x1388 + $gPlatformFspPkgTokenSpaceGuid_VccSt 1 bytes $_DEFAULT_ = 0x00 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_ITbtDmaLtr 4 bytes $_DEFAULT_ = 0xFF,0x97,0xFF,0x97 + $gPlatformFspPkgTokenSpaceGuid_CpuCrashLogEnable 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_PtmEnabled 4 bytes $_DEFAULT_ = 0, 0, 0, 0 + $gPlatformFspPkgTokenSpaceGuid_SaPcieItbtRpLtrEnable 4 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01 + $gPlatformFspPkgTokenSpaceGuid_SaPcieItbtRpSnoopLatencyOverrideMode 4 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01 + $gPlatformFspPkgTokenSpaceGuid_SaPcieItbtRpSnoopLatencyOverrideMultiplier 4 bytes $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_SaPcieItbtRpSnoopLatencyOverrideValue 8 bytes $_DEFAULT_ = 0xC8,0x00,0xC8,0x00,0x3C,0x00,0xC8,0x00 + $gPlatformFspPkgTokenSpaceGuid_SaPcieItbtRpNonSnoopLatencyOverrideMode 4 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01 + $gPlatformFspPkgTokenSpaceGuid_SaPcieItbtRpNonSnoopLatencyOverrideMultiplier 4 bytes $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02 + $gPlatformFspPkgTokenSpaceGuid_SaPcieItbtRpNonSnoopLatencyOverrideValue 8 bytes $_DEFAULT_ = 0xC8,0x00,0xC8,0x00,0xC8,0x00,0xC8,0x00 + $gPlatformFspPkgTokenSpaceGuid_SaPcieItbtRpForceLtrOverride 4 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_SaPcieItbtRpLtrConfigLock 4 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_AesEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_Psi3Enable 5 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01 + $gPlatformFspPkgTokenSpaceGuid_Psi4Enable 5 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_ImonSlope 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_ImonOffset 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_VrConfigEnable 5 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01 + $gPlatformFspPkgTokenSpaceGuid_TdcEnable 5 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00 + Skip 2 bytes + $gPlatformFspPkgTokenSpaceGuid_TdcTimeWindow 20 bytes $_DEFAULT_ = 0x01,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x01,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_TdcLock 5 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PsysSlope 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PsysOffset 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_AcousticNoiseMitigation 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_FastPkgCRampDisable 5 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_SlowSlewRate 5 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_TdcCurrentLimit 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_AcLoadline 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_DcLoadline 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_Psi1Threshold 10 bytes $_DEFAULT_ = 0x50,0x00,0x50,0x00,0x50,0x00,0x50,0x00,0x50,0x00 + $gPlatformFspPkgTokenSpaceGuid_Psi2Threshold 10 bytes $_DEFAULT_ = 0x14,0x00,0x14,0x00,0x14,0x00,0x14,0x00,0x14,0x00 + $gPlatformFspPkgTokenSpaceGuid_Psi3Threshold 10 bytes $_DEFAULT_ = 0x04,0x00,0x04,0x00,0x04,0x00,0x04,0x00,0x04,0x00 + $gPlatformFspPkgTokenSpaceGuid_IccMax 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_TxtEnable 1 bytes $_DEFAULT_ = 0 + $gPlatformFspPkgTokenSpaceGuid_SkipMpInit 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_FivrRfiFrequency 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_FivrSpreadSpectrum 1 bytes $_DEFAULT_ = 0x08 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_CpuBistData 4 bytes $_DEFAULT_ = 0 + $gPlatformFspPkgTokenSpaceGuid_CpuMpPpi 4 bytes $_DEFAULT_ = 0 + $gPlatformFspPkgTokenSpaceGuid_PreWake 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_RampUp 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_RampDown 1 bytes $_DEFAULT_ = 0x00 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_VrVoltageLimit 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_VccInAuxImonIccImax 2 bytes $_DEFAULT_ = 160 + $gPlatformFspPkgTokenSpaceGuid_EnableVsysCritical 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_VsysFullScale 1 bytes $_DEFAULT_ = 0x18 + $gPlatformFspPkgTokenSpaceGuid_VsysCriticalThreshold 1 bytes $_DEFAULT_ = 0x06 + $gPlatformFspPkgTokenSpaceGuid_VsysAssertionDeglitchMantissa 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_VsysAssertionDeglitchExponent 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_VsysDeassertionDeglitchMantissa 1 bytes $_DEFAULT_ = 0x0D + $gPlatformFspPkgTokenSpaceGuid_VsysDeassertionDeglitchExponent 1 bytes $_DEFAULT_ = 0x02 + $gPlatformFspPkgTokenSpaceGuid_VccInAuxImonSlope 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_VccInAuxImonOffset 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_FivrSpectrumEnable 1 bytes $_DEFAULT_ = 0x01 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_IccLimit 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + Skip 2 bytes + $gPlatformFspPkgTokenSpaceGuid_PpinSupport 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_EnableMinVoltageOverride 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_MinVoltageRuntime 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_ProcessorTraceMemSize 1 bytes $_DEFAULT_ = 0xff + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_MinVoltageC8 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_SmbiosType4MaxSpeedOverride 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_Irms 5 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_AvxDisable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_Avx3Disable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_X2ApicSupport 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_VrPowerDeliveryDesign 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_EnableFastVmode 5 bytes $_DEFAULT_ = 0x0, 0x0, 0x0, 0x0, 0x0 + $gPlatformFspPkgTokenSpaceGuid_ReservedCpuPostMemProduction 32 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPwrOptEnable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchWriteProtectionEnable 5 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchReadProtectionEnable 5 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_PchProtectedRangeLimit 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_PchProtectedRangeBase 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_PchHdaPme 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchHdaLinkFrequency 1 bytes $_DEFAULT_ = 0x02 + $gPlatformFspPkgTokenSpaceGuid_PchIshSpiCs0Enable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchIoApicEntry24_119 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchIoApicId 1 bytes $_DEFAULT_ = 0x02 + $gPlatformFspPkgTokenSpaceGuid_PchIshSpiEnable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchIshUartEnable 2 bytes $_DEFAULT_ = 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchIshI2cEnable 3 bytes $_DEFAULT_ = 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchIshGpEnable 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchIshPdtUnlock 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchLanLtrEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchLockDownBiosLock 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchCrid 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_RtcBiosInterfaceLock 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_RtcMemoryLock 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PcieRpHotPlug 28 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieRpPmSci 28 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 + $gPlatformFspPkgTokenSpaceGuid_PcieRpTransmitterHalfSwing 28 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieRpClkReqDetect 28 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieRpAdvancedErrorReporting 28 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieRpUnsupportedRequestReport 28 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieRpFatalErrorReport 28 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieRpNoFatalErrorReport 28 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieRpCorrectableErrorReport 28 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieRpSystemErrorOnFatalError 28 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieRpSystemErrorOnNonFatalError 28 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieRpSystemErrorOnCorrectableError 28 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieRpMaxPayload 28 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_ThcPort0Assignment 1 bytes $_DEFAULT_ = 0x0 + Skip 2 bytes + $gPlatformFspPkgTokenSpaceGuid_ThcPort0InterruptPinMuxing 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_ThcPort0WakeOnTouch 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_ThcPort1Assignment 1 bytes $_DEFAULT_ = 0x0 + Skip 2 bytes + $gPlatformFspPkgTokenSpaceGuid_ThcPort1InterruptPinMuxing 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_ThcPort1WakeOnTouch 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PcieRpPcieSpeed 28 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieRpPhysicalSlotNumber 28 bytes $_DEFAULT_ = 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B + $gPlatformFspPkgTokenSpaceGuid_PcieRpCompletionTimeout 28 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieRpAspm 28 bytes $_DEFAULT_ = 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04 + $gPlatformFspPkgTokenSpaceGuid_PcieRpL1Substates 28 bytes $_DEFAULT_ = 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03 + $gPlatformFspPkgTokenSpaceGuid_PcieRpL1Low 28 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieRpLtrEnable 28 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieRpLtrConfigLock 28 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieEqOverrideDefault 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieEqMethod 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieEqMode 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieEqLocalTransmitterOverrideEnable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieEqPh3NumberOfPresetsOrCoefficients 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieEqPh3PreCursorList 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieEqPh3PostCursorList 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieEqPh3PresetList 11 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + Skip 3 bytes + $gPlatformFspPkgTokenSpaceGuid_PcieEqPh1DownstreamPortTransmitterPreset 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PcieEqPh1UpstreamPortTransmitterPreset 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PcieEqPh2LocalTransmitterOverridePreset 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PcieEnablePeerMemoryWrite 28 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieComplianceTestMode 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieRpFunctionSwap 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_CpuPcieGen3ProgramStaticEq 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_CpuPcieGen4ProgramStaticEq 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_PchPmPmeB0S5Dis 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieRpImrEnabled 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PcieRpImrSelection 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPmWolEnableOverride 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchPmPcieWakeFromDeepSx 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPmWoWlanEnable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPmWoWlanDeepSxEnable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPmLanWakeFromDeepSx 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchPmDeepSxPol 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS3MinAssert 1 bytes $_DEFAULT_ = 0x03 + $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS4MinAssert 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchPmSlpSusMinAssert 1 bytes $_DEFAULT_ = 0x04 + $gPlatformFspPkgTokenSpaceGuid_PchPmSlpAMinAssert 1 bytes $_DEFAULT_ = 0x04 + $gPlatformFspPkgTokenSpaceGuid_PchEnableDbcObs 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPmSlpStrchSusUp 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPmSlpLanLowDc 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchPmPwrBtnOverridePeriod 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPmDisableDsxAcPresentPulldown 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPmDisableNativePowerButton 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPmMeWakeSts 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchPmWolOvrWkSts 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchPmPwrCycDur 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPmPciePllSsc 1 bytes $_DEFAULT_ = 0xFF + $gPlatformFspPkgTokenSpaceGuid_PchLegacyIoLowLatency 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_SataPwrOptEnable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_EsataSpeedLimit 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_SataSpeedLimit 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_SataPortsHotPlug 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_SataPortsInterlockSw 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_SataPortsExternal 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_SataPortsSpinUp 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_SataPortsSolidStateDrive 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_SataPortsEnableDitoConfig 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_SataPortsDmVal 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_SataPortsDitoVal 16 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_SataPortsZpOdd 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_SataRstRaidDeviceId 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_SataRstPcieEnable 3 bytes $_DEFAULT_ = 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_SataRstPcieStoragePort 3 bytes $_DEFAULT_ = 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_SataRstPcieDeviceResetDelay 3 bytes $_DEFAULT_ = 100, 100, 100 + $gPlatformFspPkgTokenSpaceGuid_UfsEnable 2 bytes $_DEFAULT_ = 0, 0 + $gPlatformFspPkgTokenSpaceGuid_IehMode 1 bytes $_DEFAULT_ = 0x00 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_PchT0Level 2 bytes $_DEFAULT_ = 0x0000 + $gPlatformFspPkgTokenSpaceGuid_PchT1Level 2 bytes $_DEFAULT_ = 0x0000 + $gPlatformFspPkgTokenSpaceGuid_PchT2Level 2 bytes $_DEFAULT_ = 0x0000 + $gPlatformFspPkgTokenSpaceGuid_PchTTEnable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchTTState13Enable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchTTLock 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_TTSuggestedSetting 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_TTCrossThrottling 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchDmiTsawEn 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_DmiSuggestedSetting 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_DmiTS0TW 1 bytes $_DEFAULT_ = 0x03 + $gPlatformFspPkgTokenSpaceGuid_DmiTS1TW 1 bytes $_DEFAULT_ = 0x02 + $gPlatformFspPkgTokenSpaceGuid_DmiTS2TW 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_DmiTS3TW 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_SataP0T1M 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_SataP0T2M 1 bytes $_DEFAULT_ = 0x02 + $gPlatformFspPkgTokenSpaceGuid_SataP0T3M 1 bytes $_DEFAULT_ = 0x03 + $gPlatformFspPkgTokenSpaceGuid_SataP0TDisp 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_SataP1T1M 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_SataP1T2M 1 bytes $_DEFAULT_ = 0x02 + $gPlatformFspPkgTokenSpaceGuid_SataP1T3M 1 bytes $_DEFAULT_ = 0x03 + $gPlatformFspPkgTokenSpaceGuid_SataP1TDisp 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_SataP0Tinact 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_SataP0TDispFinit 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_SataP1Tinact 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_SataP1TDispFinit 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_SataThermalSuggestedSetting 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchMemoryThrottlingEnable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchMemoryPmsyncEnable 2 bytes $_DEFAULT_ = 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchMemoryC0TransmitEnable 2 bytes $_DEFAULT_ = 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchMemoryPinSelection 2 bytes $_DEFAULT_ = 0x00, 0x00 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_PchTemperatureHotLevel 2 bytes $_DEFAULT_ = 0x0073 + $gPlatformFspPkgTokenSpaceGuid_Usb2OverCurrentPin 16 bytes $_DEFAULT_ = 0x00, 0x00, 0x01, 0x01, 0x02, 0x02, 0x03, 0x03, 0x04, 0x04, 0x05, 0x05, 0x06, 0x06, 0x07, 0x07 + $gPlatformFspPkgTokenSpaceGuid_Usb3OverCurrentPin 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x01, 0x01, 0x02, 0x02, 0x03, 0x03, 0x04, 0x04 + $gPlatformFspPkgTokenSpaceGuid_PchUsbLtrOverrideEnable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_ThcMode 2 bytes $_DEFAULT_ = 0x0, 0x0 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_PchUsbLtrHighIdleTimeOverride 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_PchUsbLtrMediumIdleTimeOverride 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_PchUsbLtrLowIdleTimeOverride 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_Enable8254ClockGating 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_Enable8254ClockGatingOnS3 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_EnableTcoTimer 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_HybridStorageMode 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_CpuRootportUsedForHybridStorage 1 bytes $_DEFAULT_ = 0xFF + $gPlatformFspPkgTokenSpaceGuid_PchRootportUsedForCpuAttach 1 bytes $_DEFAULT_ = 0xFF + $gPlatformFspPkgTokenSpaceGuid_PchAcpiL6dPmeHandling 1 bytes $_DEFAULT_ = 0x0 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_BgpdtHash 32 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_BiosGuardAttr 4 bytes $_DEFAULT_ = 0xFFFFFFFF + Skip 4 bytes + $gPlatformFspPkgTokenSpaceGuid_BiosGuardModulePtr 8 bytes $_DEFAULT_ = 0xFFFFFFFFFFFFFFFF + $gPlatformFspPkgTokenSpaceGuid_SendEcCmd 8 bytes $_DEFAULT_ = 0xFFFFFFFFFFFFFFFF + $gPlatformFspPkgTokenSpaceGuid_EcCmdProvisionEav 1 bytes $_DEFAULT_ = 0xFF + $gPlatformFspPkgTokenSpaceGuid_EcCmdLock 1 bytes $_DEFAULT_ = 0xFF + $gPlatformFspPkgTokenSpaceGuid_SiSkipSsidProgramming 1 bytes $_DEFAULT_ = 0x00 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_SiCustomizedSvid 2 bytes $_DEFAULT_ = 0x0000 + $gPlatformFspPkgTokenSpaceGuid_SiCustomizedSsid 2 bytes $_DEFAULT_ = 0x0000 + $gPlatformFspPkgTokenSpaceGuid_SiSsidTablePtr 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_SiNumberOfSsidTableEntry 2 bytes $_DEFAULT_ = 0x0000 + $gPlatformFspPkgTokenSpaceGuid_PortResetMessageEnable 16 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_SataRstInterrupt 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_MeUnconfigOnRtcClear 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_EnforceEDebugMode 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PsOnEnable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PmcCpuC10GatePinEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchDmiAspmCtrl 1 bytes $_DEFAULT_ = 0x02 + $gPlatformFspPkgTokenSpaceGuid_PchDmiCwbEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PmcOsIdleEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchS0ixAutoDemotion 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchPmLatchEventsC10Exit 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PmcAdrEn 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PmcAdrTimerEn 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PmcAdrTimer1Val 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PmcAdrMultiplier1Val 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PmcAdrHostPartitionReset 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PmcAdrSrcOverride 1 bytes $_DEFAULT_ = 0x00 + Skip 2 bytes + $gPlatformFspPkgTokenSpaceGuid_PmcAdrSrcSel 4 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_CpuPcieEqPh3LaneParamCm 32 bytes $_DEFAULT_ = 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06 + $gPlatformFspPkgTokenSpaceGuid_CpuPcieEqPh3LaneParamCp 32 bytes $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02 + $gPlatformFspPkgTokenSpaceGuid_CpuPcieGen3RootPortPreset 20 bytes $_DEFAULT_ = 0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07 + $gPlatformFspPkgTokenSpaceGuid_CpuPcieGen4RootPortPreset 20 bytes $_DEFAULT_ = 0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07 + $gPlatformFspPkgTokenSpaceGuid_CpuPcieGen3EndPointPreset 20 bytes $_DEFAULT_ = 0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07 + $gPlatformFspPkgTokenSpaceGuid_CpuPcieGen4EndPointPreset 20 bytes $_DEFAULT_ = 0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07 + $gPlatformFspPkgTokenSpaceGuid_CpuPcieGen3EndPointHint 20 bytes $_DEFAULT_ = 0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02 + $gPlatformFspPkgTokenSpaceGuid_CpuPcieGen4EndPointHint 20 bytes $_DEFAULT_ = 0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02 + $gPlatformFspPkgTokenSpaceGuid_CpuPcieFiaProgramming 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_CpuPcieClockGating 4 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01 + $gPlatformFspPkgTokenSpaceGuid_CpuPciePowerGating 4 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01 + $gPlatformFspPkgTokenSpaceGuid_CpuPcieComplianceTestMode 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_CpuPcieEnablePeerMemoryWrite 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpFunctionSwap 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_CpuPcieSlotSelection 1 bytes $_DEFAULT_ = 0x01 + Skip 3 bytes + $gPlatformFspPkgTokenSpaceGuid_CpuPcieDeviceOverrideTablePtr 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpHotPlug 4 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpPmSci 4 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpTransmitterHalfSwing 4 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpAcsEnabled 4 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01 + $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpEnableCpm 4 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01 + $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpAdvancedErrorReporting 4 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01 + $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpUnsupportedRequestReport 4 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpFatalErrorReport 4 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpNoFatalErrorReport 4 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpCorrectableErrorReport 4 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpSystemErrorOnFatalError 4 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpSystemErrorOnNonFatalError 4 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpSystemErrorOnCorrectableError 4 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpMaxPayload 4 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpDpcEnabled 4 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpDpcExtensionsEnabled 4 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01 + $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpSlotImplemented 4 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01 + $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpGen3EqPh3Method 4 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01 + $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpGen4EqPh3Method 4 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01 + $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpPhysicalSlotNumber 4 bytes $_DEFAULT_ = 0x00, 0x01, 0x02, 0x03 + $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpAspm 4 bytes $_DEFAULT_ = 0x03, 0x03, 0x03, 0x03 + $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpL1Substates 4 bytes $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02 + $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpLtrEnable 4 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpLtrConfigLock 4 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpPtmEnabled 4 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01 + $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpDetectTimeoutMs 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpMultiVcEnabled 4 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate3UniqTranEnable 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate3UniqTran 10 bytes $_DEFAULT_ = 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C + $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate2UniqTranEnable 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate2UniqTran 10 bytes $_DEFAULT_ = 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C + $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate1UniqTranEnable 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate1UniqTran 10 bytes $_DEFAULT_ = 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C + $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate0UniqTranEnable 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate0UniqTran 10 bytes $_DEFAULT_ = 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C + $gPlatformFspPkgTokenSpaceGuid_SkipPamLock 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_EdramTestMode 1 bytes $_DEFAULT_ = 0x2 + $gPlatformFspPkgTokenSpaceGuid_RenderStandby 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_PmSupport 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_CdynmaxClampEnable 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_GtFreqMax 1 bytes $_DEFAULT_ = 0xFF + $gPlatformFspPkgTokenSpaceGuid_DisableTurboGt 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_SkipCdClockInit 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_RC1pFreqEnable 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PchTsnMultiVcEnable 1 bytes $_DEFAULT_ = 0x0 + Skip 2 bytes + $gPlatformFspPkgTokenSpaceGuid_LogoPixelHeight 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_LogoPixelWidth 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_Usb4CmMode 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_CpuPcieResizableBarSupport 1 bytes $_DEFAULT_ = 0x02 + $gPlatformFspPkgTokenSpaceGuid_SaPostMemTestRsvd 3 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_EnableRsr 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_ReservedCpuPostMem1 4 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_Hwp 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_HdcControl 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PowerLimit1Time 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PowerLimit2 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_TurboPowerLimitLock 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PowerLimit3Time 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PowerLimit3DutyCycle 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PowerLimit3Lock 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PowerLimit4Lock 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_TccActivationOffset 1 bytes $_DEFAULT_ = 0x0A + $gPlatformFspPkgTokenSpaceGuid_TccOffsetClamp 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_TccOffsetLock 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_NumberOfEntries 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_Custom1PowerLimit1Time 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_Custom1TurboActivationRatio 1 bytes $_DEFAULT_ = 0x14 + $gPlatformFspPkgTokenSpaceGuid_Custom1ConfigTdpControl 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_Custom2PowerLimit1Time 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_Custom2TurboActivationRatio 1 bytes $_DEFAULT_ = 0x14 + $gPlatformFspPkgTokenSpaceGuid_Custom2ConfigTdpControl 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_Custom3PowerLimit1Time 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_Custom3TurboActivationRatio 1 bytes $_DEFAULT_ = 0x14 + $gPlatformFspPkgTokenSpaceGuid_Custom3ConfigTdpControl 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_ConfigTdpLock 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_ConfigTdpBios 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit1 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit1Time 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit2 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_MlcStreamerPrefetcher 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_MlcSpatialPrefetcher 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_MonitorMwaitEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_MachineCheckEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_ApIdleManner 1 bytes $_DEFAULT_ = 0x02 + $gPlatformFspPkgTokenSpaceGuid_ProcessorTraceOutputScheme 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_ProcessorTraceEnable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_Eist 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_EnergyEfficientPState 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_EnergyEfficientTurbo 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_TStates 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_BiProcHot 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_DisableProcHotOut 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_ProcHotResponse 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_DisableVrThermalAlert 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_EnableAllThermalFunctions 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_ThermalMonitor 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_Cx 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PmgCstCfgCtrlLock 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_C1e 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PkgCStateDemotion 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PkgCStateUnDemotion 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_CStatePreWake 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_TimedMwait 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_CstCfgCtrIoMwaitRedirection 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PkgCStateLimit 1 bytes $_DEFAULT_ = 0x08 + $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl0TimeUnit 1 bytes $_DEFAULT_ = 0x02 + $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl1TimeUnit 1 bytes $_DEFAULT_ = 0x02 + $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl2TimeUnit 1 bytes $_DEFAULT_ = 0x02 + $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl3TimeUnit 1 bytes $_DEFAULT_ = 0x02 + $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl4TimeUnit 1 bytes $_DEFAULT_ = 0x02 + $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl5TimeUnit 1 bytes $_DEFAULT_ = 0x02 + $gPlatformFspPkgTokenSpaceGuid_PpmIrmSetting 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_ProcHotLock 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_ConfigTdpLevel 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_MaxRatio 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_StateRatio 40 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_StateRatioMax16 16 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_PsysPmax 2 bytes $_DEFAULT_ = 0xAC + $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl1Irtl 2 bytes $_DEFAULT_ = 0 + $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl2Irtl 2 bytes $_DEFAULT_ = 0 + $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl3Irtl 2 bytes $_DEFAULT_ = 0 + $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl4Irtl 2 bytes $_DEFAULT_ = 0 + $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl5Irtl 2 bytes $_DEFAULT_ = 0 + Skip 2 bytes + $gPlatformFspPkgTokenSpaceGuid_PowerLimit1 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PowerLimit2Power 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PowerLimit3 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PowerLimit4 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_TccOffsetTimeWindowForRatl 4 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_Custom1PowerLimit1 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_Custom1PowerLimit2 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_Custom2PowerLimit1 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_Custom2PowerLimit2 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_Custom3PowerLimit1 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_Custom3PowerLimit2 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit1Power 4 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit2Power 4 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_RaceToHalt 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_ThreeStrikeCounterDisable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_HwpInterruptControl 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_ReservedCpuPostMem2 4 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_EnableItbm 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_C1StateAutoDemotion 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_C1StateUnDemotion 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_MinRingRatioLimit 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_MaxRingRatioLimit 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_EnablePerCorePState 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_EnableHwpAutoPerCorePstate 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_EnableHwpAutoEppGrouping 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_EnableEpbPeciOverride 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_EnableFastMsrHwpReq 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_ApplyConfigTdp 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_HwpLock 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_DualTauBoost 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_ReservedCpuPostMemTest 16 bytes $_DEFAULT_ = 0x00 + Skip 16 bytes + $gPlatformFspPkgTokenSpaceGuid_EndOfPostMessage 1 bytes $_DEFAULT_ = 0x2 + $gPlatformFspPkgTokenSpaceGuid_DisableD0I3SettingForHeci 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_MctpBroadcastCycle 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PchLockDownGlobalSmi 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchLockDownBiosInterface 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchUnlockGpioPads 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchSbAccessUnlock 1 bytes $_DEFAULT_ = 0x00 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_PcieRpLtrMaxSnoopLatency 56 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieRpLtrMaxNoSnoopLatency 56 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieRpSnoopLatencyOverrideMode 28 bytes $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02 + $gPlatformFspPkgTokenSpaceGuid_PcieRpSnoopLatencyOverrideMultiplier 28 bytes $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02 + $gPlatformFspPkgTokenSpaceGuid_PcieRpSnoopLatencyOverrideValue 56 bytes $_DEFAULT_ = 0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieRpNonSnoopLatencyOverrideMode 28 bytes $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02 + $gPlatformFspPkgTokenSpaceGuid_PcieRpNonSnoopLatencyOverrideMultiplier 28 bytes $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02 + $gPlatformFspPkgTokenSpaceGuid_PcieRpNonSnoopLatencyOverrideValue 56 bytes $_DEFAULT_ = 0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieRpSlotPowerLimitScale 28 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieRpSlotPowerLimitValue 56 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieEnablePort8xhDecode 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPciePort8xhDecodePortIndex 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPmDisableEnergyReport 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_SataTestMode 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchXhciOcLock 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PmcLpmS0ixSubStateEnableMask 1 bytes $_DEFAULT_ = 0x9 + $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpLtrMaxSnoopLatency 8 bytes $_DEFAULT_ = 0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10 + $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpLtrMaxNoSnoopLatency 8 bytes $_DEFAULT_ = 0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10 + $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpSnoopLatencyOverrideMode 4 bytes $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02 + $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpSnoopLatencyOverrideMultiplier 4 bytes $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02 + $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpSnoopLatencyOverrideValue 8 bytes $_DEFAULT_ = 0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00 + $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpNonSnoopLatencyOverrideMode 4 bytes $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02 + $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpNonSnoopLatencyOverrideMultiplier 4 bytes $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02 + $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpNonSnoopLatencyOverrideValue 8 bytes $_DEFAULT_ = 0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00 + $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpGen3Uptp 4 bytes $_DEFAULT_ = 0x07, 0x07, 0x07, 0x07 + $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpGen3Dptp 4 bytes $_DEFAULT_ = 0x07, 0x07, 0x07, 0x07 + $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpGen4Uptp 4 bytes $_DEFAULT_ = 0x08, 0x08, 0x08, 0x08 + $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpGen4Dptp 4 bytes $_DEFAULT_ = 0x09, 0x09, 0x09, 0x09 + $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpGen5Uptp 4 bytes $_DEFAULT_ = 0x07, 0x07, 0x07, 0x07 + $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpGen5Dptp 4 bytes $_DEFAULT_ = 0x07, 0x07, 0x07, 0x07 + $gPlatformFspPkgTokenSpaceGuid_EnableTcssCovTypeA 4 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_MappingPchXhciUsbA 4 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_CpuPcieFomsCp 4 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PmcC10DynamicThresholdAdjustment 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpPeerToPeerMode 4 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_TurboRatioLimitRatio 8 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_TurboRatioLimitNumCore 8 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_AtomTurboRatioLimitRatio 8 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_AtomTurboRatioLimitNumCore 8 bytes $_DEFAULT_ = 0x00 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_FspEventHandler 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_VmdGlobalMapping 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_CpuPcieFunc0LinkDisable 4 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PmcSkipVccInConfig 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_CseDataResilience 1 bytes $_DEFAULT_ = 0x01 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_HorizontalResolution 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_VerticalResolution 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_ThcActiveLtr 8 bytes $_DEFAULT_ = 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF + $gPlatformFspPkgTokenSpaceGuid_ThcIdleLtr 8 bytes $_DEFAULT_ = 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF + $gPlatformFspPkgTokenSpaceGuid_ThcHidResetPad 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_ThcHidResetPadTrigger 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_ThcHidConnectionSpeed 8 bytes $_DEFAULT_ = 0x40,0x66,0x03,0x01,0x40,0x66,0x03,0x01 + $gPlatformFspPkgTokenSpaceGuid_ThcLimitPacketSize 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_ThcPerformanceLimitation 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_ThcHidInputReportHeaderAddress 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_ThcHidInputReportBodyAddress 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_ThcHidOutputReportAddress 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_ThcHidReadOpcode 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_ThcHidWriteOpcode 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_ThcHidFlags 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + +EndStruct + + +List &EN_DIS + Selection 0x1 , "Enabled" + Selection 0x0 , "Disabled" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartDebugEnable + Selection 0 , "Disable" + Selection 1 , "Enable and Initialize" + Selection 2 , "Enable without Initializing" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartNumber + Selection 0 , "SerialIoUart0" + Selection 1 , "SerialIoUart1" + Selection 2 , "SerialIoUart2" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartMode + Selection 0 , "SerialIoUartDisabled" + Selection 1 , "SerialIoUartPci" + Selection 2 , "SerialIoUartHidden" + Selection 3 , "SerialIoUartCom" + Selection 4 , "SerialIoUartSkipInit" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartParity + Selection 0 , " DefaultParity" + Selection 1 , " NoParity" + Selection 2 , " EvenParity" + Selection 3 , " OddParity" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartStopBits + Selection 0 , " DefaultStopBits" + Selection 1 , " OneStopBit" + Selection 2 , " OneFiveStopBits" + Selection 3 , " TwoStopBits" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartAutoFlow + Selection 0 , " Disable" + Selection 1 , "Enable" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcdLpcUartDebugEnable + Selection 0 , "Disable" + Selection 1 , "Enable" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugLevel + Selection 0 , "Disable" + Selection 1 , "Error Only" + Selection 2 , "Error and Warnings" + Selection 3 , "Load Error Warnings and Info" + Selection 4 , "Load Error Warnings and Info & Event" + Selection 5 , "Load Error Warnings Info and Verbose" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcdIsaSerialUartBase + Selection 0 , "0x3F8" + Selection 1 , "0x2F8" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcdSerialIo2ndUartEnable + Selection 0 , "Disable" + Selection 1 , "Enable and Initialize" + Selection 2 , "Enable without Initializing" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcdSerialIo2ndUartNumber + Selection 0 , "SerialIoUart0" + Selection 1 , "SerialIoUart1" + Selection 2 , "SerialIoUart2" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcdSerialIo2ndUartMode + Selection 0 , "SerialIoUartDisabled" + Selection 1 , "SerialIoUartPci" + Selection 2 , "SerialIoUartHidden" + Selection 3 , "SerialIoUartCom" + Selection 4 , "SerialIoUartSkipInit" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcdSerialIo2ndUartParity + Selection 0 , " DefaultParity" + Selection 1 , " NoParity" + Selection 2 , " EvenParity" + Selection 3 , " OddParity" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcdSerialIo2ndUartStopBits + Selection 0 , " DefaultStopBits" + Selection 1 , " OneStopBit" + Selection 2 , " OneFiveStopBits" + Selection 3 , " TwoStopBits" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcdSerialIo2ndUartAutoFlow + Selection 0 , " Disable" + Selection 1 , "Enable" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_MemorySpdDataLen + Selection 0x100 , "256 Bytes" + Selection 0x200 , "512 Bytes" + Selection 0x400 , "1024 Bytes" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_SmramMask + Selection 0 , " Neither" + Selection 1 , "AB-SEG" + Selection 2 , "H-SEG" + Selection 3 , " Both" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_IbeccOperationMode + Selection 0 , "Protect base on address range" + Selection 1 , "Non-protected" + Selection 2 , "All protected" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_TsegSize + Selection 0x0400000 , "4MB" + Selection 0x01000000 , "16MB" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PlatformDebugConsent + Selection 0 , "Disabled" + Selection 2 , "Enabled (All Probes+TraceHub)" + Selection 6 , "Enable (Low Power)" + Selection 7 , "Manual" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_DciDbcMode + Selection 0 , "Disabled" + Selection 1 , "USB2 DbC" + Selection 2 , "USB3 DbC" + Selection 3 , "Both" + Selection 4 , "No Change" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_DciUsb3TypecUfpDbg + Selection 0 , "Disabled" + Selection 1 , "Enabled" + Selection 2 , "No Change" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PchTraceHubMode + Selection 0 , " Disable" + Selection 1 , " Target Debugger Mode" + Selection 2 , " Host Debugger Mode" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PchTraceHubMemReg0Size + Selection 0 , "0" + Selection 1 , "1MB" + Selection 2 , "8MB" + Selection 3 , "64MB" + Selection 4 , "128MB" + Selection 5 , "256MB" + Selection 6 , "512MB" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PchTraceHubMemReg1Size + Selection 0 , "0" + Selection 1 , "1MB" + Selection 2 , "8MB" + Selection 3 , "64MB" + Selection 4 , "128MB" + Selection 5 , "256MB" + Selection 6 , "512MB" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkDmicClockSelect + Selection 0 , " Both" + Selection 1 , " ClkA" + Selection 2 , " ClkB" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_IgdDvmt50PreAlloc + Selection 0x00 , "0MB" + Selection 0x01 , "32MB" + Selection 0x02 , "64MB" + Selection 0x03 , "96MB" + Selection 0x04 , "128MB" + Selection 0x05 , "160MB" + Selection 0xF0 , "4MB" + Selection 0xF1 , "8MB" + Selection 0xF2 , "12MB" + Selection 0xF3 , "16MB" + Selection 0xF4 , "20MB" + Selection 0xF5 , "24MB" + Selection 0xF6 , "28MB" + Selection 0xF7 , "32MB" + Selection 0xF8 , "36MB" + Selection 0xF9 , "40MB" + Selection 0xFA , "44MB" + Selection 0xFB , "48MB" + Selection 0xFC , "52MB" + Selection 0xFD , "56MB" + Selection 0xFE , "60MB" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_ApertureSize + Selection 0 , "128 MB" + Selection 1 , "256 MB" + Selection 3 , "512 MB" + Selection 7 , "1024 MB" + Selection 15 , " 2048 MB" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_UserBd + Selection 0 , "Mobile" + Selection 1 , "Desktop1Dpc" + Selection 2 , "Desktop2DpcDaisyChain" + Selection 3 , "Desktop2DpcTeeTopologyAsymmetrical" + Selection 4 , "Desktop2DpcTeeTopology" + Selection 5 , "UltMobile" + Selection 7 , "UP Server" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_DisableMrcRetrainingOnRtcPowerLoss + Selection 0 , "Disabled" + Selection 1 , "Enabled" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_DdrFreqLimit + Selection 1067 , "1067" + Selection 1333 , "1333" + Selection 1600 , "1600" + Selection 1867 , "1867" + Selection 2133 , "2133" + Selection 2400 , "2400" + Selection 2667 , "2667" + Selection 2933 , "2933" + Selection 0 , "Auto" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_SaGv + Selection 0 , "Disabled" + Selection 1 , "FixedPoint0" + Selection 2 , "FixedPoint1" + Selection 3 , "FixedPoint2" + Selection 4 , "FixedPoint3" + Selection 5 , "Enabled" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_MemTestOnWarmBoot + Selection 0 , "Disable" + Selection 1 , "Enable" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_DdrSpeedControl + Selection 0 , "Auto" + Selection 1 , "Manual" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_SpdProfileSelected + Selection 0 , "Default SPD Profile" + Selection 1 , "Custom Profile" + Selection 2 , "XMP Profile 1" + Selection 3 , "XMP Profile 2" + Selection 4 , "XMP Profile 3" + Selection 5 , "XMP User Profile 4" + Selection 6 , "XMP User Profile 5" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_RefClk + Selection 0 , "133MHz" + Selection 1 , "100MHz" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_Ratio + Selection 0 , "Auto" + Selection 4 , "4" + Selection 5 , "5" + Selection 6 , "6" + Selection 7 , "7" + Selection 8 , "8" + Selection 9 , "9" + Selection 10 , "10" + Selection 11 , "11" + Selection 12 , "12" + Selection 13 , "13" + Selection 14 , "14" + Selection 15 , "15" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_tWR + Selection 0 , "Auto" + Selection 5 , "5" + Selection 6 , "6" + Selection 7 , "7" + Selection 8 , "8" + Selection 10 , "10" + Selection 12 , "12" + Selection 14 , "14" + Selection 16 , "16" + Selection 18 , "18" + Selection 20 , "20" + Selection 24 , "24" + Selection 30 , "30" + Selection 34 , "34" + Selection 40 , "40" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMode + Selection 0 , " Disable" + Selection 1 , "Target Debugger Mode" + Selection 2 , "Host Debugger Mode" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMemReg0Size + Selection 0 , "0" + Selection 1 , "1MB" + Selection 2 , "8MB" + Selection 3 , "64MB" + Selection 4 , "128MB" + Selection 5 , "256MB" + Selection 6 , "512MB" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMemReg1Size + Selection 0 , "0" + Selection 1 , "1MB" + Selection 2 , "8MB" + Selection 3 , "64MB" + Selection 4 , "128MB" + Selection 5 , "256MB" + Selection 6 , "512MB" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_InitPcieAspmAfterOprom + Selection 0 , "Before" + Selection 1 , "After" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PrimaryDisplay + Selection 0 , "iGFX" + Selection 1 , "PEG" + Selection 2 , "PCIe Graphics on PCH" + Selection 3 , "AUTO" + Selection 4 , "Hybrid Graphics" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PsmiRegionSize + Selection 0 , "32MB" + Selection 1 , "288MB" + Selection 2 , "544MB" + Selection 3 , "800MB" + Selection 4 , "1024MB" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_GttSize + Selection 1 , "2MB" + Selection 2 , "4MB" + Selection 3 , "8MB" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_GtVoltageMode + Selection 0 , " Adaptive" + Selection 1 , " Override" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_RealtimeMemoryTiming + Selection 0 , " Disabled" + Selection 1 , " Enabled" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_IpuLaneUsed + Selection 1 , "x1" + Selection 2 , "x2" + Selection 3 , "x3" + Selection 4 , "x4" + Selection 8 , "x8" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_CsiSpeed + Selection 0 , "Sensor default" + Selection 1 , "<416Mbps" + Selection 2 , "<1.5Gbps" + Selection 3 , "<2Gbps" + Selection 4 , "<2.5Gbps" + Selection 5 , "<4Gbps" + Selection 6 , ">4Gbps" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_CpuPcieRpLinkDownGpios + Selection 0 , "Disable" + Selection 1 , "Enable" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_CpuPcieRpClockReqMsgEnable + Selection 0 , "Disable" + Selection 1 , "Enable" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_DdiPortAConfig + Selection 0 , "Disabled" + Selection 1 , "eDP" + Selection 2 , "MIPI DSI" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_DdiPortBConfig + Selection 0 , "Disabled" + Selection 1 , "eDP" + Selection 2 , "MIPI DSI" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_TvbRatioClipping + Selection 0 , " Disabled" + Selection 1 , " Enabled" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_TvbVoltageOptimization + Selection 0 , " Disabled" + Selection 1 , " Enabled" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_DisplayAudioLink + Selection 0 , " Disabled" + Selection 1 , " Enabled" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_DmiMaxLinkSpeed + Selection 0 , "Auto" + Selection 1 , "Gen1" + Selection 2 , "Gen2" + Selection 3 , "Gen3" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_DmiGen3EqPh2Enable + Selection 0 , "Disable phase2" + Selection 1 , "Enable phase2" + Selection 2 , "Auto" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_DmiGen3EqPh3Method + Selection 0 , "Auto" + Selection 1 , "HwEq" + Selection 2 , "SwEq" + Selection 3 , "StaticEq" + Selection 4 , "BypassPhase3" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_DmiDeEmphasis + Selection 0 , " -6dB" + Selection 1 , " -3.5dB" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_BootFrequency + Selection 0 , "0" + Selection 1 , "1" + Selection 2 , "2" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_ActiveCoreCount + Selection 0 , "Disable all big cores" + Selection 1 , "1" + Selection 2 , "2" + Selection 3 , "3" + Selection 0xFF , "Active all big cores" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_FClkFrequency + Selection 0 , "800 MHz" + Selection 1 , " 1 GHz" + Selection 2 , " 400 MHz" + Selection 3 , " Reserved" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_JtagC10PowerGateDisable + Selection 0 , " False" + Selection 1 , " True" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_DebugInterfaceEnable + Selection 0 , "Disabled" + Selection 1 , "Enabled" + Selection 2 , "No Change" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_ActiveSmallCoreCount + Selection 0 , "Disable all small cores" + Selection 1 , "1" + Selection 2 , "2" + Selection 3 , "3" + Selection 0xFF , "Active all small cores" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_CoreVfPointOffsetMode + Selection 0 , "Legacy" + Selection 1 , "Selection" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_CoreVfPointOffsetPrefix + Selection 0 , "Positive" + Selection 1 , "Negative" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_CoreVfConfigScope + Selection 0 , "All-core" + Selection 1 , "Per-core" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_CrashLogGprs + Selection 0 , "Disabled" + Selection 1 , "Enabled" + Selection 2 , "Only Smm GPRs Disabled" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_RingVfPointOffsetMode + Selection 0 , "Legacy" + Selection 1 , "Selection" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_BclkSource + Selection 1 , "CPU BCLK" + Selection 2 , "PCH BCLK" + Selection 3 , "External CLK" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_SaPllFreqOverride + Selection 0 , " 3200MHz" + Selection 1 , " 1600MHz" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_TscDisableHwFixup + Selection 0 , "Enable" + Selection 1 , "Disable" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PchPort80Route + Selection 0 , "LPC" + Selection 1 , "PCI" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PchHdaVcType + Selection 0 , " VC0" + Selection 1 , " VC1" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PchHdaTestPowerClockGating + Selection 0 , " POR" + Selection 1 , " Force Enable" + Selection 2 , " Force Disable" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PchHdaIDispLinkFrequency + Selection 4 , " 96MHz" + Selection 3 , " 48MHz" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PchHdaIDispLinkTmode + Selection 0 , " 2T" + Selection 2 , " 4T" + Selection 3 , " 8T" + Selection 4 , " 16T" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugControllerNumber + Selection 0 , "SerialIoUart0" + Selection 1 , "SerialIoUart1" + Selection 2 , "SerialIoUart2" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugParity + Selection 0 , " DefaultParity" + Selection 1 , " NoParity" + Selection 2 , " EvenParity" + Selection 3 , " OddParity" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugStopBits + Selection 0 , " DefaultStopBits" + Selection 1 , " OneStopBit" + Selection 2 , " OneFiveStopBits" + Selection 3 , " TwoStopBits" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugBaudRate + Selection 3 , "9600" + Selection 4 , "19200" + Selection 6 , "56700" + Selection 7 , "115200" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_HobBufferSize + Selection 0 , "Default" + Selection 1 , " 1 Byte" + Selection 2 , " 1 KB" + Selection 3 , " Max value" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_RhSelect + Selection 0 , "Disable" + Selection 1 , "RFM" + Selection 2 , "pTRR" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_NewFeatureEnable1 + Selection 0 , "Disable" + Selection 1 , "Enable" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_NewFeatureEnable2 + Selection 0 , "Disable" + Selection 1 , "Enable" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_ChHashInterleaveBit + Selection 0 , "BIT6" + Selection 1 , "BIT7" + Selection 2 , "BIT8" + Selection 3 , "BIT9" + Selection 4 , "BIT10" + Selection 5 , "BIT11" + Selection 6 , "BIT12" + Selection 7 , "BIT13" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_BClkFrequency + Selection 100000000 , "100Hz" + Selection 125000000 , "125Hz" + Selection 167000000 , "167Hz" + Selection 250000000 , "250Hz" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_EnCmdRate + Selection 0 , "Disable" + Selection 5 , "2 CMDS" + Selection 7 , "3 CMDS" + Selection 9 , "4 CMDS" + Selection 11 , "5 CMDS" + Selection 13 , "6 CMDS" + Selection 15 , "7 CMDS" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_Refresh2X + Selection 0 , "Disable" + Selection 1 , "Enabled for WARM or HOT" + Selection 2 , "Enabled HOT only" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PowerDownMode + Selection 0x0 , "No Power Down" + Selection 0x1 , "APD" + Selection 0x6 , "PPD DLL OFF" + Selection 0xFF , "Auto" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_DisPgCloseIdleTimeout + Selection 0 , "Enabled" + Selection 1 , "Disabled" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_SerialDebugMrcLevel + Selection 0 , "Disable" + Selection 1 , "Error Only" + Selection 2 , "Error and Warnings" + Selection 3 , "Load Error Warnings and Info" + Selection 4 , "Load Error Warnings and Info & Event" + Selection 5 , "Load Error Warnings Info and Verbose" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_Ddr4OneDpc + Selection 0 , " Disabled" + Selection 1 , " Enabled on DIMM0 only" + Selection 2 , " Enabled on DIMM1 only" + Selection 3 , " Enabled" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_RefreshWm + Selection 0 , "Set Refresh Watermarks to Low" + Selection 1 , "Set Refresh Watermarks to High (Default)" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_McRefreshRate + Selection 0 , "NORMAL Refresh" + Selection 1 , "1x Refresh" + Selection 2 , "2x Refresh" + Selection 3 , "4x Refresh" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_LpMode + Selection 0 , " Auto (default)" + Selection 1 , " Enabled" + Selection 2 , " Disabled" + Selection 3 , " Reserved" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_BdatTestType + Selection 0 , "RMT per Rank" + Selection 1 , "RMT per Bit" + Selection 2 , "Margin2D" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_DeltaT12PowerCycleDelay + Selection 0 , " No Delay" + Selection 0xFFFF , " Auto Calulate T12 Delay" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_ReuseAdlSDdr5Board + Selection 0 , " no" + Selection 1 , " yes" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugMode + Selection 0 , "SerialIoUartDisabled" + Selection 1 , "SerialIoUartPci" + Selection 2 , "SerialIoUartHidden" + Selection 3 , "SerialIoUartCom" + Selection 4 , "SerialIoUartSkipInit" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PprEnable + Selection 0 , "Disable" + Selection 2 , "Hard PPR" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_MarginLimitCheck + Selection 0 , "Disable" + Selection 1 , "L1" + Selection 2 , "L2" + Selection 3 , "Both" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_IbeccErrInjControl + Selection 0 , " No Error Injection" + Selection 1 , "Inject Correctable Error Address match" + Selection 3 , "Inject Correctable Error on insertion counter" + Selection 5 , " Inject Uncorrectable Error Address match" + Selection 7 , "Inject Uncorrectable Error on insertion counter" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_Lp5BankMode + Selection 0 , "Auto" + Selection 1 , "8 Bank Mode" + Selection 2 , "16 Bank Mode" + Selection 3 , "BG Mode" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_SataMode + Selection 0 , "AHCI" + Selection 1 , "RAID" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_SerialIoDebugUartNumber + Selection 0 , "UART0" + Selection 1 , "UART1" + Selection 2 , "UART2" + Selection 3 , "UART3" + Selection 4 , "UART4" + Selection 5 , "UART5" + Selection 6 , "UART6" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PchTsnLinkSpeed + Selection 0 , " 24Mhz 2.5Gbps" + Selection 1 , " 24Mhz 1Gbps" + Selection 2 , " 38.4Mhz 2.5Gbps" + Selection 3 , " 38.4Mhz 1Gbps" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_CnviMode + Selection 0 , "Disable" + Selection 1 , "Auto" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_CdClock + Selection 0xFF , " Auto (Max based on reference clock frequency)" + Selection 0 , " 192" + Selection 1 , " 307.2" + Selection 2 , " 312 Mhz" + Selection 3 , " 324Mhz" + Selection 4 , " 326.4 Mhz" + Selection 5 , " 552 Mhz" + Selection 6 , " 556.8 Mhz" + Selection 7 , " 648 Mhz" + Selection 8 , " 652.8 Mhz" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_LidStatus + Selection 0 , " LidClosed" + Selection 1 , " LidOpen" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_VmdCfgBarAttr + Selection 0 , " VMD_32BIT_NONPREFETCH" + Selection 1 , " VMD_64BIT_NONPREFETCH" + Selection 2 , " VMD_64BIT_PREFETCH" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_VmdMemBar1Attr + Selection 0 , " VMD_32BIT_NONPREFETCH" + Selection 1 , " VMD_64BIT_NONPREFETCH" + Selection 2 , " VMD_64BIT_PREFETCH" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_VmdMemBar2Attr + Selection 0 , " VMD_32BIT_NONPREFETCH" + Selection 1 , " VMD_64BIT_NONPREFETCH" + Selection 2 , " VMD_64BIT_PREFETCH" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_SlowSlewRate + Selection 0 , " Fast/2" + Selection 1 , " Fast/4" + Selection 2 , " Fast/8" + Selection 3 , " Fast/16" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PpinSupport + Selection 0 , " Disable" + Selection 1 , " Enable" + Selection 2 , " Auto" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_AvxDisable + Selection 0 , " Enable" + Selection 1 , " Disable" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_Avx3Disable + Selection 0 , " Enable" + Selection 1 , " Disable" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_EnableFastVmode + Selection 0 , " Disable" + Selection 1 , " Enable" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PchHdaLinkFrequency + Selection 0 , " 6MHz" + Selection 1 , " 12MHz" + Selection 2 , " 24MHz" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_ThcPort0Assignment + Selection 0x0 , "ThcAssignmentNone" + Selection 0x1 , "ThcAssignmentThc0" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_ThcPort1Assignment + Selection 0x0 , "ThcAssignmentNone" + Selection 0x1 , "ThcPort1AssignmentThc0" + Selection 0x2 , "ThcAssignmentThc1" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcieEqMethod + Selection 0 , " HardwareEq" + Selection 1 , " FixedEq" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcieEqMode + Selection 0 , " PresetEq" + Selection 1 , " CoefficientEq" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_IehMode + Selection 0 , " Bypass" + Selection 1 , "Enable" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_DmiTS0TW + Selection 0 , "x1" + Selection 1 , "x2" + Selection 2 , "x4" + Selection 3 , "x8" + Selection 4 , "x16" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_DmiTS1TW + Selection 0 , "x1" + Selection 1 , "x2" + Selection 2 , "x4" + Selection 3 , "x8" + Selection 4 , "x16" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_DmiTS2TW + Selection 0 , "x1" + Selection 1 , "x2" + Selection 2 , "x4" + Selection 3 , "x8" + Selection 4 , "x16" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_DmiTS3TW + Selection 0 , "x1" + Selection 1 , "x2" + Selection 2 , "x4" + Selection 3 , "x8" + Selection 4 , "x16" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_HybridStorageMode + Selection 0 , " Disabled" + Selection 1 , " Dynamic Configuration" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_SataRstInterrupt + Selection 0 , "Msix" + Selection 1 , "Msi" + Selection 2 , "Legacy" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_MeUnconfigOnRtcClear + Selection 0 , " Disable ME Unconfig On Rtc Clear" + Selection 1 , " Enable ME Unconfig On Rtc Clear" + Selection 2 , " Cmos is clear" + Selection 3 , " Reserved" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PchDmiAspmCtrl + Selection 0 , "Disabled" + Selection 1 , "L0s" + Selection 2 , "L1" + Selection 3 , "L0sL1" + Selection 4 , "Auto" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_EdramTestMode + Selection 0 , " EDRAM SW disable" + Selection 1 , " EDRAM SW Enable" + Selection 2 , " EDRAM HW mode" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_GtFreqMax + Selection 0xFF , " Auto(Default)" + Selection 2 , " 100 Mhz" + Selection 3 , " 150 Mhz" + Selection 4 , " 200 Mhz" + Selection 5 , " 250 Mhz" + Selection 6 , " 300 Mhz" + Selection 7 , " 350 Mhz" + Selection 8 , " 400 Mhz" + Selection 9 , " 450 Mhz" + Selection 0xA , " 500 Mhz" + Selection 0xB , " 550 Mhz" + Selection 0xC , " 600 Mhz" + Selection 0xD , " 650 Mhz" + Selection 0xE , " 700 Mhz" + Selection 0xF , " 750 Mhz" + Selection 0x10 , " 800 Mhz" + Selection 0x11 , " 850 Mhz" + Selection 0x12 , "900 Mhz" + Selection 0x13 , " 950 Mhz" + Selection 0x14 , " 1000 Mhz" + Selection 0x15 , " 1050 Mhz" + Selection 0x16 , " 1100 Mhz" + Selection 0x17 , " 1150 Mhz" + Selection 0x18 , " 1200 Mhz" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_ApIdleManner + Selection 1 , " HALT loop" + Selection 2 , " MWAIT loop" + Selection 3 , " RUN loop" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_ProcessorTraceOutputScheme + Selection 0 , " Single Range Output" + Selection 1 , " ToPA Output" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_ThreeStrikeCounterDisable + Selection 0 , " False" + Selection 1 , " True" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_EndOfPostMessage + Selection 0 , "Disable" + Selection 1 , "Send in PEI" + Selection 2 , "Send in DXE" + Selection 3 , "Reserved" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_CpuPcieFomsCp + Selection 0 , " Auto" + Selection 1 , " Gen3 Foms" + Selection 2 , " Gen4 Foms" + Selection 3 , " Gen3 and Gen4 Foms" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_CpuPcieRpPeerToPeerMode + Selection 0 , " Disable" + Selection 1 , " Enable" +EndList + +BeginInfoBlock + PPVer "0.1" + Description "Alder Lake Platform" +EndInfoBlock + +Page "FSP-T Settings" + Combo $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartDebugEnable, "PcdSerialIoUartDebugEnable", &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartDebugEnable, + Help "Enable SerialIo Uart debug library with/without initializing SerialIo Uart device in FSP. " + Combo $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartNumber, "PcdSerialIoUartNumber", &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartNumber, + Help "Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT Core interface, it cannot be used for debug purpose." + Combo $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartMode, "PcdSerialIoUartMode - FSPT", &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartMode, + Help "Select SerialIo Uart Controller mode" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartBaudRate, "PcdSerialIoUartBaudRate - FSPT", DEC, + Help "Set default BaudRate Supported from 0 - default to 6000000" + "Valid range: 0 ~ 6000000" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcdPciExpressBaseAddress, "Pci Express Base Address", HEX, + Help "Base address to be programmed for Pci Express " + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcdPciExpressRegionLength, "Pci Express Region Length", HEX, + Help "Region Length to be programmed for Pci Express " + "Valid range: 0x00 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartParity, "PcdSerialIoUartParity - FSPT", &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartParity, + Help "Set default Parity." + EditNum $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartDataBits, "PcdSerialIoUartDataBits - FSPT", HEX, + Help "Set default word length. 0: Default, 5,6,7,8" + "Valid range: 0x0 ~ 0x08" + Combo $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartStopBits, "PcdSerialIoUartStopBits - FSPT", &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartStopBits, + Help "Set default stop bits." + Combo $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartAutoFlow, "PcdSerialIoUartAutoFlow - FSPT", &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartAutoFlow, + Help "Enables UART hardware flow control, CTS and RTS lines." + EditNum $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartRxPinMux, "PcdSerialIoUartRxPinMux - FSPT", HEX, + Help "Select RX pin muxing for SerialIo UART used for debug" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartTxPinMux, "PcdSerialIoUartTxPinMux - FSPT", HEX, + Help "Select TX pin muxing for SerialIo UART used for debug" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartRtsPinMux, "PcdSerialIoUartRtsPinMux - FSPT", HEX, + Help "Select SerialIo Uart used for debug Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS* for possible values." + "Valid range: 0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartCtsPinMux, "PcdSerialIoUartCtsPinMux - FSPT", HEX, + Help "Select SerialIo Uart used for debug Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS* for possible values." + "Valid range: 0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartDebugMmioBase, "PcdSerialIoUartDebugMmioBase - FSPT", HEX, + Help "Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIoUartMode = SerialIoUartPci." + "Valid range: 0 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PcdLpcUartDebugEnable, "PcdLpcUartDebugEnable", &gPlatformFspPkgTokenSpaceGuid_PcdLpcUartDebugEnable, + Help "Enable to initialize LPC Uart device in FSP." + EditNum $gPlatformFspPkgTokenSpaceGuid_PcdDebugInterfaceFlags, "Debug Interfaces", HEX, + Help "Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, BIT2 - Not used." + "Valid range: 0x00 ~ 0x3F" + Combo $gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugLevel, "PcdSerialDebugLevel", &gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugLevel, + Help "Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, Info & Verbose." + Combo $gPlatformFspPkgTokenSpaceGuid_PcdIsaSerialUartBase, "ISA Serial Base selection", &gPlatformFspPkgTokenSpaceGuid_PcdIsaSerialUartBase, + Help "Select ISA Serial Base address. Default is 0x3F8." + Combo $gPlatformFspPkgTokenSpaceGuid_PcdSerialIo2ndUartEnable, "PcdSerialIo2ndUartEnable", &gPlatformFspPkgTokenSpaceGuid_PcdSerialIo2ndUartEnable, + Help "Enable Additional SerialIo Uart device in FSP." + Combo $gPlatformFspPkgTokenSpaceGuid_PcdSerialIo2ndUartNumber, "PcdSerialIo2ndUartNumber", &gPlatformFspPkgTokenSpaceGuid_PcdSerialIo2ndUartNumber, + Help "Select SerialIo Uart Controller Number" + Combo $gPlatformFspPkgTokenSpaceGuid_PcdSerialIo2ndUartMode, "PcdSerialIo2ndUartMode - FSPT", &gPlatformFspPkgTokenSpaceGuid_PcdSerialIo2ndUartMode, + Help "Select SerialIo Uart Controller mode" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcdSerialIo2ndUartBaudRate, "PcdSerialIo2ndUartBaudRate - FSPT", DEC, + Help "Set default BaudRate Supported from 0 - default to 6000000" + "Valid range: 0 ~ 6000000" + Combo $gPlatformFspPkgTokenSpaceGuid_PcdSerialIo2ndUartParity, "PcdSerialIo2ndUartParity - FSPT", &gPlatformFspPkgTokenSpaceGuid_PcdSerialIo2ndUartParity, + Help "Set default Parity." + EditNum $gPlatformFspPkgTokenSpaceGuid_PcdSerialIo2ndUartDataBits, "PcdSerialIo2ndUartDataBits - FSPT", HEX, + Help "Set default word length. 0: Default, 5,6,7,8" + "Valid range: 0x0 ~ 0x08" + Combo $gPlatformFspPkgTokenSpaceGuid_PcdSerialIo2ndUartStopBits, "PcdSerialIo2ndUartStopBits - FSPT", &gPlatformFspPkgTokenSpaceGuid_PcdSerialIo2ndUartStopBits, + Help "Set default stop bits." + Combo $gPlatformFspPkgTokenSpaceGuid_PcdSerialIo2ndUartAutoFlow, "PcdSerialIo2ndUartAutoFlow - FSPT", &gPlatformFspPkgTokenSpaceGuid_PcdSerialIo2ndUartAutoFlow, + Help "Enables UART hardware flow control, CTS and RTS lines." + EditNum $gPlatformFspPkgTokenSpaceGuid_PcdSerialIo2ndUartRxPinMux, "PcdSerialIo2ndUartRxPinMux - FSPT", HEX, + Help "Select RX pin muxing for SerialIo UART" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcdSerialIo2ndUartTxPinMux, "PcdSerialIo2ndUartTxPinMux - FSPT", HEX, + Help "Select TX pin muxing for SerialIo UART" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcdSerialIo2ndUartRtsPinMux, "PcdSerialIo2ndUartRtsPinMux - FSPT", HEX, + Help "Select SerialIo Uart Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS* for possible values." + "Valid range: 0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcdSerialIo2ndUartCtsPinMux, "PcdSerialIo2ndUartCtsPinMux - FSPT", HEX, + Help "Select SerialIo Uart Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS* for possible values." + "Valid range: 0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcdSerialIo2ndUartMmioBase, "PcdSerialIo2ndUartMmioBase - FSPT", HEX, + Help "Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIo2ndUartMode = SerialIoUartPci." + "Valid range: 0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_FspDebugHandler, "FspDebugHandler", HEX, + Help "Optional pointer to the boot loader's implementation of FSP_DEBUG_HANDLER." + "Valid range: 0x0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoSpiCsPolarity, "Serial Io SPI Chip Select Polarity", HEX, + Help "Sets polarity for each chip Select. Available options: 0:SerialIoSpiCsActiveLow, 1:SerialIoSpiCsActiveHigh" + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoSpiCsEnable, "Serial Io SPI Chip Select Enable", HEX, + Help "0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled" + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoSpiDefaultCsOutput, "Serial Io SPI Default Chip Select Output", HEX, + Help "Sets Default CS as Output. Available options: 0:CS0, 1:CS1" + "Valid range: 0x00 ~ 0x1" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoSpiCsMode, "Serial Io SPI Default Chip Select Mode HW/SW", HEX, + Help "Sets Default CS Mode Hardware or Software. Available options: 0:HW, 1:SW" + "Valid range: 0x00 ~ 0x1" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoSpiCsState, "Serial Io SPI Default Chip Select State Low/High", HEX, + Help "Sets Default CS State Low or High. Available options: 0:Low, 1:High" + "Valid range: 0x00 ~ 0x1" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoSpiMmioBase, "Serial Io SPI Device MMIO Base", HEX, + Help "Assigns MMIO for Serial Io SPI controller usage in early stage." + "Valid range: 0x0 ~ 0xFFFFFFFF" +EndPage + +Page "Memory Reference Code" + EditNum $gPlatformFspPkgTokenSpaceGuid_PlatformMemorySize, "Platform Reserved Memory Size", HEX, + Help "The minimum platform memory size required to pass control into DXE" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_MemorySpdDataLen, "SPD Data Length", &gPlatformFspPkgTokenSpaceGuid_MemorySpdDataLen, + Help "Length of SPD Data" + Combo $gPlatformFspPkgTokenSpaceGuid_EnableAbove4GBMmio, "Enable above 4GB MMIO resource support", &EN_DIS, + Help "Enable/disable above 4GB MMIO resource support" + EditNum $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr000, "Memory SPD Pointer Controller 0 Channel 0 Dimm 0", HEX, + Help "Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr001, "Memory SPD Pointer Controller 0 Channel 0 Dimm 1", HEX, + Help "Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr010, "Memory SPD Pointer Controller 0 Channel 1 Dimm 0", HEX, + Help "Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr011, "Memory SPD Pointer Controller 0 Channel 1 Dimm 1", HEX, + Help "Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr020, "Memory SPD Pointer Controller 0 Channel 2 Dimm 0", HEX, + Help "Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr021, "Memory SPD Pointer Controller 0 Channel 2 Dimm 1", HEX, + Help "Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr030, "Memory SPD Pointer Controller 0 Channel 3 Dimm 0", HEX, + Help "Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr031, "Memory SPD Pointer Controller 0 Channel 3 Dimm 1", HEX, + Help "Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr100, "Memory SPD Pointer Controller 1 Channel 0 Dimm 0", HEX, + Help "Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr101, "Memory SPD Pointer Controller 1 Channel 0 Dimm 1", HEX, + Help "Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr110, "Memory SPD Pointer Controller 1 Channel 1 Dimm 0", HEX, + Help "Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr111, "Memory SPD Pointer Controller 1 Channel 1 Dimm 1", HEX, + Help "Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr120, "Memory SPD Pointer Controller 1 Channel 2 Dimm 0", HEX, + Help "Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr121, "Memory SPD Pointer Controller 1 Channel 2 Dimm 1", HEX, + Help "Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr130, "Memory SPD Pointer Controller 1 Channel 3 Dimm 0", HEX, + Help "Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr131, "Memory SPD Pointer Controller 1 Channel 3 Dimm 1", HEX, + Help "Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_RcompResistor, "RcompResistor settings", HEX, + Help "Indicates RcompResistor settings: Board-dependent" + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_RcompTarget, "RcompTarget settings", HEX, + Help "RcompTarget settings: board-dependent" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DqsMapCpu2DramMc0Ch0, "Dqs Map CPU to DRAM MC 0 CH 0", HEX, + Help "Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent" + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DqsMapCpu2DramMc0Ch1, "Dqs Map CPU to DRAM MC 0 CH 1", HEX, + Help "Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent" + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DqsMapCpu2DramMc0Ch2, "Dqs Map CPU to DRAM MC 0 CH 2", HEX, + Help "Set Dqs mapping relationship between CPU and DRAM, Channel 2: board-dependent" + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DqsMapCpu2DramMc0Ch3, "Dqs Map CPU to DRAM MC 0 CH 3", HEX, + Help "Set Dqs mapping relationship between CPU and DRAM, Channel 3: board-dependent" + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DqsMapCpu2DramMc1Ch0, "Dqs Map CPU to DRAM MC 1 CH 0", HEX, + Help "Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent" + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DqsMapCpu2DramMc1Ch1, "Dqs Map CPU to DRAM MC 1 CH 1", HEX, + Help "Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent" + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DqsMapCpu2DramMc1Ch2, "Dqs Map CPU to DRAM MC 1 CH 2", HEX, + Help "Set Dqs mapping relationship between CPU and DRAM, Channel 2: board-dependent" + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DqsMapCpu2DramMc1Ch3, "Dqs Map CPU to DRAM MC 1 CH 3", HEX, + Help "Set Dqs mapping relationship between CPU and DRAM, Channel 3: board-dependent" + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DqMapCpu2DramMc0Ch0, "Dq Map CPU to DRAM MC 0 CH 0", HEX, + Help "Set Dq mapping relationship between CPU and DRAM, Channel 0: board-dependent" + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DqMapCpu2DramMc0Ch1, "Dq Map CPU to DRAM MC 0 CH 1", HEX, + Help "Set Dq mapping relationship between CPU and DRAM, Channel 1: board-dependent" + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DqMapCpu2DramMc0Ch2, "Dq Map CPU to DRAM MC 0 CH 2", HEX, + Help "Set Dq mapping relationship between CPU and DRAM, Channel 2: board-dependet" + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DqMapCpu2DramMc0Ch3, "Dq Map CPU to DRAM MC 0 CH 3", HEX, + Help "Set Dq mapping relationship between CPU and DRAM, Channel 3: board-dependent" + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DqMapCpu2DramMc1Ch0, "Dq Map CPU to DRAM MC 1 CH 0", HEX, + Help "Set Dq mapping relationship between CPU and DRAM, Channel 0: board-dependent" + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DqMapCpu2DramMc1Ch1, "Dq Map CPU to DRAM MC 1 CH 1", HEX, + Help "Set Dq mapping relationship between CPU and DRAM, Channel 1: board-dependent" + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DqMapCpu2DramMc1Ch2, "Dq Map CPU to DRAM MC 1 CH 2", HEX, + Help "Set Dq mapping relationship between CPU and DRAM, Channel 2: board-dependent" + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DqMapCpu2DramMc1Ch3, "Dq Map CPU to DRAM MC 1 CH 3", HEX, + Help "Set Dq mapping relationship between CPU and DRAM, Channel 3: board-dependent" + "Valid range: 0x00 ~ 0xFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_DqPinsInterleaved, "Dqs Pins Interleaved Setting", &EN_DIS, + Help "Indicates DqPinsInterleaved setting: board-dependent" + Combo $gPlatformFspPkgTokenSpaceGuid_SmramMask, "Smram Mask", &gPlatformFspPkgTokenSpaceGuid_SmramMask, + Help "The SMM Regions AB-SEG and/or H-SEG reserved" + Combo $gPlatformFspPkgTokenSpaceGuid_Ibecc, "Ibecc", &EN_DIS, + Help "Enable/Disable Ibecc" + Combo $gPlatformFspPkgTokenSpaceGuid_IbeccOperationMode, "IbeccOperationMode", &gPlatformFspPkgTokenSpaceGuid_IbeccOperationMode, + Help "In-Band ECC Operation Mode" + Combo $gPlatformFspPkgTokenSpaceGuid_IbeccProtectedRangeEnable, "IbeccProtectedRangeEnable", &EN_DIS, + Help "In-Band ECC Protected Region Enable" + EditNum $gPlatformFspPkgTokenSpaceGuid_IbeccProtectedRangeBase, "IbeccProtectedRangeBase", HEX, + Help "IBECC Protected Region Base" + "Valid range: 0x00000000 ~ 0x03FFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IbeccProtectedRangeMask, "IbeccProtectedRangeMask", HEX, + Help "IBECC Protected Region Mask" + "Valid range: 0x00000001 ~ 0x03FFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_MrcFastBoot, "MRC Fast Boot", &EN_DIS, + Help "Enables/Disable the MRC fast path thru the MRC" + Combo $gPlatformFspPkgTokenSpaceGuid_RmtPerTask, "Rank Margin Tool per Task", &EN_DIS, + Help "This option enables the user to execute Rank Margin Tool per major training step in the MRC." + Combo $gPlatformFspPkgTokenSpaceGuid_TrainTrace, "Training Trace", &EN_DIS, + Help "This option enables the trained state tracing feature in MRC. This feature will print out the key training parameters state across major training steps." + Combo $gPlatformFspPkgTokenSpaceGuid_TsegSize, "Tseg Size", &gPlatformFspPkgTokenSpaceGuid_TsegSize, + Help "Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build" + EditNum $gPlatformFspPkgTokenSpaceGuid_MmioSize, "MMIO Size", HEX, + Help "Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB" + "Valid range: 0 ~ 0xC00" + Combo $gPlatformFspPkgTokenSpaceGuid_ProbelessTrace, "Probeless Trace", &EN_DIS, + Help "Probeless Trace: 0=Disabled, 1=Enable. Enabling Probeless Trace will reserve 128MB. This also requires IED to be enabled." + EditNum $gPlatformFspPkgTokenSpaceGuid_SpdAddressTable, "Spd Address Tabl", HEX, + Help "Specify SPD Address table for CH0D0/CH0D1/CH1D0&CH1D1. MemorySpdPtr will be used if SPD Address is 00" + "Valid range: 0x00 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_UserBd, "Board Type", &gPlatformFspPkgTokenSpaceGuid_UserBd, + Help "MrcBoardType, Options are 0:Mobile, 1:Desktop1Dpc, 2:Desktop2DpcDaisyChain, 3:Desktop2DpcTeeTopologyAsymmetrical, 4:Desktop2DpcTeeTopology, 5:UltMobile, 7:UP Server" + Combo $gPlatformFspPkgTokenSpaceGuid_DisableMrcRetrainingOnRtcPowerLoss, "MRC Retraining on RTC Power Loss", &gPlatformFspPkgTokenSpaceGuid_DisableMrcRetrainingOnRtcPowerLoss, + Help "Specifies whether MRC memory training will occur when RTC power loss is detected. Options are 0=Memory will be re-trained if RTC power loss is detected. 1=Memory will not be re-trained when RTC power loss is detected. (Typically used on board designs without a dedicated RTC battery)" + Combo $gPlatformFspPkgTokenSpaceGuid_DdrFreqLimit, "DDR Frequency Limit", &gPlatformFspPkgTokenSpaceGuid_DdrFreqLimit, + Help "Maximum Memory Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, 2133, 2400, 2667, 2933 and 0 for Auto." + Combo $gPlatformFspPkgTokenSpaceGuid_SaGv, "SA GV", &gPlatformFspPkgTokenSpaceGuid_SaGv, + Help "System Agent dynamic frequency support and when enabled memory will be training at four different frequencies." + Combo $gPlatformFspPkgTokenSpaceGuid_MemTestOnWarmBoot, "Memory Test on Warm Boot", &gPlatformFspPkgTokenSpaceGuid_MemTestOnWarmBoot, + Help "Run Base Memory Test on Warm Boot" + Combo $gPlatformFspPkgTokenSpaceGuid_DdrSpeedControl, "DDR Speed Control", &gPlatformFspPkgTokenSpaceGuid_DdrSpeedControl, + Help "DDR Frequency and Gear control for all SAGV points." + Combo $gPlatformFspPkgTokenSpaceGuid_RMT, "Rank Margin Tool", &EN_DIS, + Help "Enable/disable Rank Margin Tool." + Combo $gPlatformFspPkgTokenSpaceGuid_DisableMc0Ch0, "Controller 0 Channel 0 DIMM Control", &EN_DIS, + Help "Enable / Disable DIMMs on Controller 0 Channel 0" + Combo $gPlatformFspPkgTokenSpaceGuid_DisableMc0Ch1, "Controller 0 Channel 1 DIMM Control", &EN_DIS, + Help "Enable / Disable DIMMs on Controller 0 Channel 1" + Combo $gPlatformFspPkgTokenSpaceGuid_DisableMc0Ch2, "Controller 0 Channel 2 DIMM Control", &EN_DIS, + Help "Enable / Disable DIMMs on Controller 0 Channel 2" + Combo $gPlatformFspPkgTokenSpaceGuid_DisableMc0Ch3, "Controller 0 Channel 3 DIMM Control", &EN_DIS, + Help "Enable / Disable DIMMs on Controller 0 Channel 3" + Combo $gPlatformFspPkgTokenSpaceGuid_DisableMc1Ch0, "Controller 1 Channel 0 DIMM Control", &EN_DIS, + Help "Enable / Disable DIMMs on Controller 1 Channel 0" + Combo $gPlatformFspPkgTokenSpaceGuid_DisableMc1Ch1, "Controller 1 Channel 1 DIMM Control", &EN_DIS, + Help "Enable / Disable DIMMs on Controller 1 Channel 1" + Combo $gPlatformFspPkgTokenSpaceGuid_DisableMc1Ch2, "Controller 1 Channel 2 DIMM Control", &EN_DIS, + Help "Enable / Disable DIMMs on Controller 1 Channel 2" + Combo $gPlatformFspPkgTokenSpaceGuid_DisableMc1Ch3, "Controller 1 Channel 3 DIMM Control", &EN_DIS, + Help "Enable / Disable DIMMs on Controller 1 Channel 3" + Combo $gPlatformFspPkgTokenSpaceGuid_ScramblerSupport, "Scrambler Support", &EN_DIS, + Help "This option enables data scrambling in memory." + Combo $gPlatformFspPkgTokenSpaceGuid_SpdProfileSelected, "SPD Profile Selected", &gPlatformFspPkgTokenSpaceGuid_SpdProfileSelected, + Help "Select DIMM timing profile. Options are 0:Default SPD Profile, 1:Custom Profile, 2:XMP Profile 1, 3:XMP Profile 2, 4:XMP Profile 3, 5:XMP User Profile 4, 6:XMP User Profile 5" + Combo $gPlatformFspPkgTokenSpaceGuid_RefClk, "Memory Reference Clock", &gPlatformFspPkgTokenSpaceGuid_RefClk, + Help "100MHz, 133MHz." + EditNum $gPlatformFspPkgTokenSpaceGuid_VddVoltage, "Memory Voltage", DEC, + Help "DRAM voltage (Vdd) (supply voltage for input buffers and core logic of the DRAM chips) in millivolts from 0 - default to 1435mv." + "Valid range: 0 ~ 1435" + Combo $gPlatformFspPkgTokenSpaceGuid_Ratio, "Memory Ratio", &gPlatformFspPkgTokenSpaceGuid_Ratio, + Help "Automatic or the frequency will equal ratio times reference clock. Set to Auto to recalculate memory timings listed below." + EditNum $gPlatformFspPkgTokenSpaceGuid_tCL, "tCL", HEX, + Help "CAS Latency, 0: AUTO, max: 31. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile)." + "Valid range: 0x00 ~ 0x1F" + EditNum $gPlatformFspPkgTokenSpaceGuid_tCWL, "tCWL", HEX, + Help "Min CAS Write Latency Delay Time, 0: AUTO, max: 34. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile)." + "Valid range: 0x00 ~ 0x22" + EditNum $gPlatformFspPkgTokenSpaceGuid_tFAW, "tFAW", HEX, + Help "Min Four Activate Window Delay Time, 0: AUTO, max: 63. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile)." + "Valid range: 0x00 ~ 0x3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_tRAS, "tRAS", HEX, + Help "RAS Active Time, 0: AUTO, max: 64. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile)." + "Valid range: 0x00 ~ 0x40" + EditNum $gPlatformFspPkgTokenSpaceGuid_tRCDtRP, "tRCD/tRP", HEX, + Help "RAS to CAS delay time and Row Precharge delay time, 0: AUTO, max: 63. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile)." + "Valid range: 0x00 ~ 0x3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_tREFI, "tREFI", HEX, + Help "Refresh Interval, 0: AUTO, max: 65535. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile)." + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_tRFC, "tRFC", HEX, + Help "Min Refresh Recovery Delay Time, 0: AUTO, max: 1023. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile)." + "Valid range: 0x00 ~ 0x3FF" + EditNum $gPlatformFspPkgTokenSpaceGuid_tRRD, "tRRD", HEX, + Help "Min Row Active to Row Active Delay Time, 0: AUTO, max: 15. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile)." + "Valid range: 0x00 ~ 0x0F" + EditNum $gPlatformFspPkgTokenSpaceGuid_tRTP, "tRTP", HEX, + Help "Min Internal Read to Precharge Command Delay Time, 0: AUTO, max: 15. DDR4 legal values: 5, 6, 7, 8, 9, 10, 12. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile)." + "Valid range: 0x00 ~ 0x0F" + Combo $gPlatformFspPkgTokenSpaceGuid_tWR, "tWR", &gPlatformFspPkgTokenSpaceGuid_tWR, + Help "Min Write Recovery Time, 0: AUTO, legal values: 5, 6, 7, 8, 10, 12, 14, 16, 18, 20, 24, 30, 34, 40. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile)." + EditNum $gPlatformFspPkgTokenSpaceGuid_tWTR, "tWTR", HEX, + Help "Min Internal Write to Read Command Delay Time, 0: AUTO, max: 28. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile)." + "Valid range: 0x00 ~ 0x1C" + EditNum $gPlatformFspPkgTokenSpaceGuid_NModeSupport, "NMode", HEX, + Help "System command rate, range 0-2, 0 means auto, 1 = 1N, 2 = 2N" + "Valid range: 0x00 ~ 0x02" + EditNum $gPlatformFspPkgTokenSpaceGuid_SaGvGear, "SAGV Gear Ratio", HEX, + Help "Gear Selection for SAGV points. 0 - Auto, 1-1 Gear 1, 2-Gear 2" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SaGvFreq, "SAGV Frequency", HEX, + Help "SAGV Frequency per point in Mhz. 0 for Auto and a ratio of 133/100MHz: 1333/1300." + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_GearRatio, "SAGV Disabled Gear Ratio", HEX, + Help "Gear Selection for SAGV Disabled. 0 - Auto, 1-1 Gear 1, 2-Gear 2" + "Valid range: 0x00 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_TxtImplemented, "Enable/Disable MRC TXT dependency", &EN_DIS, + Help "When enabled MRC execution will wait for TXT initialization to be done first. Disabled(0x0)(Default): MRC will not wait for TXT initialization, Enabled(0x1): MRC will wait for TXT initialization" + Combo $gPlatformFspPkgTokenSpaceGuid_RealtimeMemoryTiming, "Realtime Memory Timing", &gPlatformFspPkgTokenSpaceGuid_RealtimeMemoryTiming, + Help "0(Default): Disabled, 1: Enabled. When enabled, it will allow the system to perform realtime memory timing changes after MRC_DONE." + EditNum $gPlatformFspPkgTokenSpaceGuid_VddqVoltage, "Memory VDDQ Voltage", DEC, + Help "DRAM voltage (Vddq) (supply voltage for DQ/DQS of the DRAM chips) in millivolts from 0 - default to 1435mv." + "Valid range: 0 ~ 1435" + EditNum $gPlatformFspPkgTokenSpaceGuid_VppVoltage, "Memory VPP Voltage", DEC, + Help "DRAM voltage (Vpp) (supply voltage for VPP of the DRAM chips) in millivolts from 0 - default to 2135mv." + "Valid range: 0 ~ 2135" + Combo $gPlatformFspPkgTokenSpaceGuid_CpuPcieNewFom, "CPU PCIe New FOM", &EN_DIS, + Help "Enable/Disable NewFom for DEKEL Programming. 0: Disable(Default); 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_DmiNewFom, "DMI DEKEL New FOM", &EN_DIS, + Help "Enable/Disable NewFom for DEKEL Programming. 0: Disable(Default); 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_DynamicMemoryBoost, "Dynamic Memory Boost", &EN_DIS, + Help "0(Default): Disable, 1: Enable. When enabled, MRC will train the Default SPD Profile, and also the profile selected by SpdProfileSelected, to allow automatic switching during runtime. Only valid if SpdProfileSelected is an XMP Profile, otherwise ignored." + EditNum $gPlatformFspPkgTokenSpaceGuid_HgSupport, "Hybrid Graphics Support ", HEX, + Help "0(Default): PEG10, 1: PEG60, 2:PEG62. Help to select Hybrid Graphics Support on Peg Port" + "Valid range: 0x00 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_RealtimeMemoryFrequency, "Realtime Memory Frequency", &EN_DIS, + Help "0(Default): Disabled, 1: Enabled. Ignored unless SpdProfileSelected is an XMP Profile. If enabled, MRC will train the Default SPD Profile, and also the selected XMP Profile, to allow manually triggered switching between frequencies at runtime." + Combo $gPlatformFspPkgTokenSpaceGuid_SaPreMemProductionRsvd, "SaPreMemProductionRsvd", &EN_DIS, + Help "Reserved for SA Pre-Mem Production" + Combo $gPlatformFspPkgTokenSpaceGuid_GtClosEnable, "Enable Gt CLOS", &EN_DIS, + Help "0(Default)=Disable, 1=Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_DmiMaxLinkSpeed, "DMI Max Link Speed", &gPlatformFspPkgTokenSpaceGuid_DmiMaxLinkSpeed, + Help "Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed" + Combo $gPlatformFspPkgTokenSpaceGuid_DmiGen3EqPh2Enable, "DMI Equalization Phase 2", &gPlatformFspPkgTokenSpaceGuid_DmiGen3EqPh2Enable, + Help "DMI Equalization Phase 2. (0x0): Disable phase 2, (0x1): Enable phase 2, (0x2)(Default): AUTO - Use the current default method" + Combo $gPlatformFspPkgTokenSpaceGuid_DmiGen3EqPh3Method, "DMI Gen3 Equalization Phase3", &gPlatformFspPkgTokenSpaceGuid_DmiGen3EqPh3Method, + Help "DMI Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just Phase1), Disabled(0x4): Bypass Equalization Phase 3" + Combo $gPlatformFspPkgTokenSpaceGuid_DmiGen3ProgramStaticEq, "Enable/Disable DMI GEN3 Static EQ Phase1 programming", &EN_DIS, + Help "Program DMI Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming" + Combo $gPlatformFspPkgTokenSpaceGuid_DmiDeEmphasis, "DeEmphasis control for DMI", &gPlatformFspPkgTokenSpaceGuid_DmiDeEmphasis, + Help "DeEmphasis control for DMI. 0=-6dB, 1(Default)=-3.5 dB" + EditNum $gPlatformFspPkgTokenSpaceGuid_DmiGen3RootPortPreset, "DMI Gen3 Root port preset values per lane", HEX, + Help "Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DmiGen3EndPointPreset, "DMI Gen3 End port preset values per lane", HEX, + Help "Used for programming DMI Gen3 preset values per lane. Range: 0-9, 7 is default for each lane" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DmiGen3EndPointHint, "DMI Gen3 End port Hint values per lane", HEX, + Help "Used for programming DMI Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DmiGen3RxCtlePeaking, "DMI Gen3 RxCTLEp per-Bundle control", HEX, + Help "Range: 0-15, 0 is default for each bundle, must be specified based upon platform design" + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DmiAspm, "DMI ASPM Configuration:{Combo", HEX, + Help "Set ASPM Configuration" + "Valid range: 0x00 ~ 0xFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_DmiHweq, "Enable/Disable DMI GEN3 Hardware Eq", &EN_DIS, + Help "Enable/Disable DMI GEN3 Hardware Eq. Disabled(0x0)(Default): Disable Hardware Eq, Enabled(0x1): Enable EQ Phase1 Static Presets Programming" + Combo $gPlatformFspPkgTokenSpaceGuid_Gen3EqPhase23Bypass, "Enable/Disable CPU DMI GEN3 Phase 23 Bypass", &EN_DIS, + Help "CPU DMI GEN3 Phase 23 Bypass. Disabled(0x0)(Default): Disable Phase 23 Bypass, Enabled(0x1): Enable Phase 23 Bypass" + Combo $gPlatformFspPkgTokenSpaceGuid_Gen3EqPhase3Bypass, "Enable/Disable CPU DMI GEN3 Phase 3 Bypass", &EN_DIS, + Help "CPU DMI GEN3 Phase 3 Bypass. Disabled(0x0)(Default): Disable Phase 3 Bypass, Enabled(0x1): Enable Phase 3 Bypass" + Combo $gPlatformFspPkgTokenSpaceGuid_Gen3LtcoEnable, "Enable/Disable CPU DMI Gen3 EQ Local Transmitter Coefficient Override Enable", &EN_DIS, + Help "Program Gen3 EQ Local Transmitter Coefficient Override. Disabled(0x0)(Default): Disable Local Transmitter Coefficient Override, Enabled(0x1): Enable Local Transmitter Coefficient Override" + Combo $gPlatformFspPkgTokenSpaceGuid_Gen3RtcoRtpoEnable, "Enable/Disable CPU DMI Gen3 EQ Remote Transmitter Coefficient/Preset Override Enable", &EN_DIS, + Help "Program Remote Transmitter Coefficient/Preset Override. Disabled(0x0)(Default): Disable Remote Transmitter Coefficient/Preset Override, Enabled(0x1): Enable Remote Transmitter Coefficient/Preset Override" + EditNum $gPlatformFspPkgTokenSpaceGuid_DmiGen3Ltcpre, "DMI Gen3 Transmitter Pre-Cursor Coefficient ", HEX, + Help "Used for programming DMI Gen3 Transmitter Pre-Cursor Coefficient . Range: 0-10, 2 is default for each lane" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DmiGen3Ltcpo, "DMI Gen3 Transmitter Post-Cursor Coefficient", HEX, + Help "Used for programming Transmitter Post-Cursor Coefficient. Range: 0-9, 2 is default for each lane" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CpuDmiHwEqGen3CoeffListCm, "PCIE Hw Eq Gen3 CoeffList Cm", HEX, + Help "CPU_PCIE_EQ_PARAM. Coefficient C-1." + "Valid range: 0x00 ~ 0xFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CpuDmiHwEqGen3CoeffListCp, "PCIE Hw Eq Gen3 CoeffList Cp", HEX, + Help "CPU_PCIE_EQ_PARAM. Coefficient C+1." + "Valid range: 0x00 ~ 0xFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_DmiGen3DsPresetEnable, "Enable/Disable DMI GEN3 DmiGen3DsPresetEnable", &EN_DIS, + Help "Enable/Disable DMI GEN3 DmiGen3DsPreset. Auto(0x0)(Default): DmiGen3DsPresetEnable, Manual(0x1): Enable DmiGen3DsPresetEnable" + EditNum $gPlatformFspPkgTokenSpaceGuid_DmiGen3DsPortRxPreset, "DMI Gen3 Root port preset Rx values per lane", HEX, + Help "Used for programming DMI Gen3 preset values per lane. Range: 0-10, 1 is default for each lane" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DmiGen3DsPortTxPreset, "DMI Gen3 Root port preset Tx values per lane", HEX, + Help "Used for programming DMI Gen3 preset values per lane. Range: 0-10, 7 is default for each lane" + "Valid range: 0x00 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_DmiGen3UsPresetEnable, "Enable/Disable DMI GEN3 DmiGen3UsPresetEnable", &EN_DIS, + Help "Enable/Disable DMI GEN3 DmiGen3UsPreset. Auto(0x0)(Default): DmiGen3UsPresetEnable, Manual(0x1): Enable DmiGen3UsPresetEnable" + EditNum $gPlatformFspPkgTokenSpaceGuid_DmiGen3UsPortRxPreset, "DMI Gen3 Root port preset Rx values per lane", HEX, + Help "Used for programming DMI Gen3 preset values per lane. Range: 0-10, 7 is default for each lane" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DmiGen3UsPortTxPreset, "DMI Gen3 Root port preset Tx values per lane", HEX, + Help "Used for programming DMI Gen3 preset values per lane. Range: 0-10, 7 is default for each lane" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CpuDmiHwEqGen4CoeffListCm, "DMI Hw Eq Gen4 CoeffList Cm", HEX, + Help "CPU_PCIE_EQ_PARAM. Coefficient C-1." + "Valid range: 0x00 ~ 0xFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CpuDmiHwEqGen4CoeffListCp, "DMI Hw Eq Gen4 CoeffList Cp", HEX, + Help "CPU_PCIE_EQ_PARAM. Coefficient C+1." + "Valid range: 0x00 ~ 0xFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_Gen4EqPhase23Bypass, "Enable/Disable CPU DMI GEN4 Phase 23 Bypass", &EN_DIS, + Help "CPU DMI GEN4 Phase 23 Bypass. Disabled(0x0)(Default): Disable Phase 23 Bypass, Enabled(0x1): Enable Phase 23 Bypass" + Combo $gPlatformFspPkgTokenSpaceGuid_Gen4EqPhase3Bypass, "Enable/Disable CPU DMI GEN4 Phase 3 Bypass", &EN_DIS, + Help "CPU DMI GEN3 Phase 4 Bypass. Disabled(0x0)(Default): Disable Phase 3 Bypass, Enabled(0x1): Enable Phase 3 Bypass" + Combo $gPlatformFspPkgTokenSpaceGuid_DmiGen4DsPresetEnable, "Enable/Disable DMI GEN4 DmiGen4DsPresetEnable", &EN_DIS, + Help "Enable/Disable DMI GEN4 DmiGen4DsPreset. Auto(0x0)(Default): DmiGen4DsPresetEnable, Manual(0x1): Enable DmiGen4DsPresetEnable" + EditNum $gPlatformFspPkgTokenSpaceGuid_DmiGen4DsPortTxPreset, "DMI Gen4 Root port preset Tx values per lane", HEX, + Help "Used for programming DMI Gen4 preset values per lane. Range: 0-10, 7 is default for each lane" + "Valid range: 0x00 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_Gen4RtcoRtpoEnable, "Enable/Disable CPU DMI Gen4 EQ Remote Transmitter Coefficient/Preset Override Enable", &EN_DIS, + Help "Program Remote Transmitter Coefficient/Preset Override. Disabled(0x0)(Default): Disable Remote Transmitter Coefficient/Preset Override, Enabled(0x1): Enable Remote Transmitter Coefficient/Preset Override" + Combo $gPlatformFspPkgTokenSpaceGuid_Gen4LtcoEnable, "Enable/Disable CPU DMI Gen4 EQ Local Transmitter Coefficient Override Enable", &EN_DIS, + Help "Program Gen3 EQ Local Transmitter Coefficient Override. Disabled(0x0)(Default): Disable Local Transmitter Coefficient Override, Enabled(0x1): Enable Local Transmitter Coefficient Override" + EditNum $gPlatformFspPkgTokenSpaceGuid_DmiGen4Ltcpre, "DMI Gen4 Transmitter Pre-Cursor Coefficient ", HEX, + Help "Used for programming DMI Gen4 Transmitter Pre-Cursor Coefficient . Range: 0-10, 7 is default for each lane" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DmiGen4Ltcpo, "DMI Gen4 Transmitter Post-Cursor Coefficient", HEX, + Help "Used for programming DMI Gen4 Transmitter Post-Cursor Coefficient. Range: 0-9, 7 is default for each lane" + "Valid range: 0x00 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_DmiGen4UsPresetEnable, "Enable/Disable DMI GEN4 DmiGen4UsPresetEnable", &EN_DIS, + Help "Enable/Disable DMI GEN4 DmiGen4UsPreset. Auto(0x0)(Default): DmiGen4UsPresetEnable, Manual(0x1): Enable DmiGen4UsPresetEnable" + EditNum $gPlatformFspPkgTokenSpaceGuid_DmiGen4UsPortTxPreset, "DMI Gen4 Root port preset Tx values per lane", HEX, + Help "Used for programming DMI Gen4 preset values per lane. Range: 0-10, 1 is default for each lane" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DmiAspmCtrl, "DMI ASPM Control Configuration:{Combo", HEX, + Help "Set ASPM Control configuration" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DmiAspmL1ExitLatency, "DMI ASPM L1 exit Latency", HEX, + Help "Range: 0-7, 4 is default L1 exit Latency" + "Valid range: 0x00 ~ 0x07" + Combo $gPlatformFspPkgTokenSpaceGuid_SiSkipOverrideBootModeWhenFwUpdate, "Skip override boot mode When Fw Update.", &EN_DIS, + Help "When set to TRUE and boot mode is BOOT_ON_FLASH_UPDATE, skip setting boot mode to BOOT_WITH_FULL_CONFIGURATION in PEI memory init." + Combo $gPlatformFspPkgTokenSpaceGuid_TscDisableHwFixup, "TSC HW Fixup disable", &gPlatformFspPkgTokenSpaceGuid_TscDisableHwFixup, + Help "TSC HW Fixup disable during TSC copy from PMA to APIC. 0: Enable; 1: Disable" + Combo $gPlatformFspPkgTokenSpaceGuid_IaIccUnlimitedMode, "Support IA Unlimited ICCMAX", &EN_DIS, + Help "Support IA Unlimited ICCMAX up to maximum value 512A; 0: Disabled; 1: Enabled." + EditNum $gPlatformFspPkgTokenSpaceGuid_IaIccMax, "IA ICCMAX", HEX, + Help "IA ICCMAX value is represented in 1/4 A increments. A value of 400 = 100A. 4 . Range is 4-2047." + "Valid range: 0x00 ~ 0x7FF" + Combo $gPlatformFspPkgTokenSpaceGuid_GtIccUnlimitedMode, "Support GT Unlimited ICCMAX", &EN_DIS, + Help "Support GT Unlimited ICCMAX up to maximum value 512A; 0: Disabled; 1: Enabled." + EditNum $gPlatformFspPkgTokenSpaceGuid_GtIccMax, "GT ICCMAX", HEX, + Help "GT ICCMAX value is represented in 1/4 A increments. A value of 400 = 100A. 4 . Range is 4-2047." + "Valid range: 0x00 ~ 0x7FF" + EditNum $gPlatformFspPkgTokenSpaceGuid_TvbDownBinsTempThreshold0, "TVB Down Bins for Temp Threshold 0", DEC, + Help "Down Bins (delta) for Temperature Threshold 0. When running above Temperature Threshold 0, the ratio will be clipped by MAX_RATIO[n]-This value, when TVB ratio clipping is enabled. Default is 1." + "Valid range: 0 ~ 10" + EditNum $gPlatformFspPkgTokenSpaceGuid_TvbTempThreshold0, "TVB Temperature Threshold 0", DEC, + Help "TVB Temp (degrees C) - Temperature Threshold 0. Running ABOVE this temperature will clip delta Down Bins for Threshold 0 from the resolved OC Ratio, when TVB ratio clipping is enabled. Default is 70." + "Valid range: 0 ~ 100" + EditNum $gPlatformFspPkgTokenSpaceGuid_TvbTempThreshold1, "TVB Temperature Threshold 1", DEC, + Help "TVB Temp (degrees C) - Temperature Threshold 1. Running ABOVE this temperature will clip delta Down Bins for Threshold 1 from the resolved OC Ratio, when TVB ratio clipping is enabled. Default is 100." + "Valid range: 0 ~ 100" + EditNum $gPlatformFspPkgTokenSpaceGuid_TvbDownBinsTempThreshold1, "TVB Down Bins for Temp Threshold 1", DEC, + Help "Down Bins (delta) for Temperature Threshold 1. When running above Temperature Threshold 1, the ratio will be clipped by MAX_RATIO[n]-Down Bin Threshold 1-This value, when TVB ratio clipping is enabled. Default is 2." + "Valid range: 0 ~ 10" + Combo $gPlatformFspPkgTokenSpaceGuid_FllOcModeEn, "FLL Overclock Mode Enable", &EN_DIS, + Help "Select FLL Mode Value from 0 to 3. 0x0 = no overclocking, 0x1 = ratio overclocking with nominal (0.5-1x) reference clock frequency, 0x2 = BCLK overclocking with elevated (1-3x) reference clock frequency, 0x3 = BCLK overclocking with extreme elevated (3-5x) reference clock frequency and ratio limited to 63." + EditNum $gPlatformFspPkgTokenSpaceGuid_FllOverclockMode, "FLL Overclock Mode", HEX, + Help "Select FLL Mode Value from 0 to 3. 0x0 = no overclocking, 0x1 = ratio overclocking with nominal (0.5-1x) reference clock frequency, 0x2 = BCLK overclocking with elevated (1-3x) reference clock frequency, 0x3 = BCLK overclocking with extreme elevated (3-5x) reference clock frequency and ratio limited to 63." + "Valid range: 0x0 ~ 0x3" + EditNum $gPlatformFspPkgTokenSpaceGuid_ConfigTdpLevel, "Configuration for boot TDP selection", HEX, + Help "Configuration for boot TDP selection; 0: TDP Nominal; 1: TDP Down; 2: TDP Up;0xFF : Deactivate" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CustomPowerLimit1, "Short term Power Limit value for custom cTDP level 1", HEX, + Help "Short term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125" + "Valid range: 0x00 ~ 0x3E7F83" + Combo $gPlatformFspPkgTokenSpaceGuid_Etvb, "Enhanced Thermal Turbo Mode", &EN_DIS, + Help "When eTVB mode is enabled user will be clipped when temperatures reach 70C 0: Disabled; 1: Enabled." + Combo $gPlatformFspPkgTokenSpaceGuid_UnderVoltProtection, "UnderVolt Protection", &EN_DIS, + Help "When UnderVolt Protection is enabled, user will be not be able to program under voltage in OS runtime. 0: Disabled; 1: Enabled" + Combo $gPlatformFspPkgTokenSpaceGuid_ReservedCpuPreMem, "ReservedCpuPreMem", &EN_DIS, + Help "Reserved for Cpu Pre-Mem" + EditNum $gPlatformFspPkgTokenSpaceGuid_MrcSafeConfig, "MRC Safe Config", HEX, + Help "Enables/Disable MRC Safe Config" + "Valid range: 0x00 ~ 0x0F" + Combo $gPlatformFspPkgTokenSpaceGuid_HobBufferSize, "HobBufferSize", &gPlatformFspPkgTokenSpaceGuid_HobBufferSize, + Help "Size to set HOB Buffer. 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value(assuming 63KB total HOB size)." + Combo $gPlatformFspPkgTokenSpaceGuid_ECT, "Early Command Training", &EN_DIS, + Help "Enables/Disable Early Command Training" + Combo $gPlatformFspPkgTokenSpaceGuid_SOT, "SenseAmp Offset Training", &EN_DIS, + Help "Enables/Disable SenseAmp Offset Training" + Combo $gPlatformFspPkgTokenSpaceGuid_ERDMPRTC2D, "Early ReadMPR Timing Centering 2D", &EN_DIS, + Help "Enables/Disable Early ReadMPR Timing Centering 2D" + Combo $gPlatformFspPkgTokenSpaceGuid_RDMPRT, "Read MPR Training", &EN_DIS, + Help "Enables/Disable Read MPR Training" + Combo $gPlatformFspPkgTokenSpaceGuid_RCVET, "Receive Enable Training", &EN_DIS, + Help "Enables/Disable Receive Enable Training" + Combo $gPlatformFspPkgTokenSpaceGuid_JWRL, "Jedec Write Leveling", &EN_DIS, + Help "Enables/Disable Jedec Write Leveling" + Combo $gPlatformFspPkgTokenSpaceGuid_EWRTC2D, "Early Write Time Centering 2D", &EN_DIS, + Help "Enables/Disable Early Write Time Centering 2D" + Combo $gPlatformFspPkgTokenSpaceGuid_ERDTC2D, "Early Read Time Centering 2D", &EN_DIS, + Help "Enables/Disable Early Read Time Centering 2D" + Combo $gPlatformFspPkgTokenSpaceGuid_WRTC1D, "Write Timing Centering 1D", &EN_DIS, + Help "Enables/Disable Write Timing Centering 1D" + Combo $gPlatformFspPkgTokenSpaceGuid_WRVC1D, "Write Voltage Centering 1D", &EN_DIS, + Help "Enables/Disable Write Voltage Centering 1D" + Combo $gPlatformFspPkgTokenSpaceGuid_RDTC1D, "Read Timing Centering 1D", &EN_DIS, + Help "Enables/Disable Read Timing Centering 1D" + Combo $gPlatformFspPkgTokenSpaceGuid_DIMMODTT, "Dimm ODT Training", &EN_DIS, + Help "Enables/Disable Dimm ODT Training" + Combo $gPlatformFspPkgTokenSpaceGuid_DIMMRONT, "DIMM RON Training", &EN_DIS, + Help "Enables/Disable DIMM RON Training" + Combo $gPlatformFspPkgTokenSpaceGuid_WRDSEQT, "Write Drive Strength/Equalization 2D", &EN_DIS, + Help "Enables/Disable Write Drive Strength/Equalization 2D" + Combo $gPlatformFspPkgTokenSpaceGuid_WRSRT, "Write Slew Rate Training", &EN_DIS, + Help "Enables/Disable Write Slew Rate Training" + Combo $gPlatformFspPkgTokenSpaceGuid_RDODTT, "Read ODT Training", &EN_DIS, + Help "Enables/Disable Read ODT Training" + Combo $gPlatformFspPkgTokenSpaceGuid_RDEQT, "Read Equalization Training", &EN_DIS, + Help "Enables/Disable Read Equalization Training" + Combo $gPlatformFspPkgTokenSpaceGuid_RDAPT, "Read Amplifier Training", &EN_DIS, + Help "Enables/Disable Read Amplifier Training" + Combo $gPlatformFspPkgTokenSpaceGuid_WRTC2D, "Write Timing Centering 2D", &EN_DIS, + Help "Enables/Disable Write Timing Centering 2D" + Combo $gPlatformFspPkgTokenSpaceGuid_RDTC2D, "Read Timing Centering 2D", &EN_DIS, + Help "Enables/Disable Read Timing Centering 2D" + Combo $gPlatformFspPkgTokenSpaceGuid_WRVC2D, "Write Voltage Centering 2D", &EN_DIS, + Help "Enables/Disable Write Voltage Centering 2D" + Combo $gPlatformFspPkgTokenSpaceGuid_RDVC2D, "Read Voltage Centering 2D", &EN_DIS, + Help "Enables/Disable Read Voltage Centering 2D" + Combo $gPlatformFspPkgTokenSpaceGuid_CMDVC, "Command Voltage Centering", &EN_DIS, + Help "Enables/Disable Command Voltage Centering" + Combo $gPlatformFspPkgTokenSpaceGuid_LCT, "Late Command Training", &EN_DIS, + Help "Enables/Disable Late Command Training" + Combo $gPlatformFspPkgTokenSpaceGuid_RTL, "Round Trip Latency Training", &EN_DIS, + Help "Enables/Disable Round Trip Latency Training" + Combo $gPlatformFspPkgTokenSpaceGuid_TAT, "Turn Around Timing Training", &EN_DIS, + Help "Enables/Disable Turn Around Timing Training" + Combo $gPlatformFspPkgTokenSpaceGuid_MEMTST, "Memory Test", &EN_DIS, + Help "Enables/Disable Memory Test" + Combo $gPlatformFspPkgTokenSpaceGuid_ALIASCHK, "DIMM SPD Alias Test", &EN_DIS, + Help "Enables/Disable DIMM SPD Alias Test" + Combo $gPlatformFspPkgTokenSpaceGuid_RCVENC1D, "Receive Enable Centering 1D", &EN_DIS, + Help "Enables/Disable Receive Enable Centering 1D" + Combo $gPlatformFspPkgTokenSpaceGuid_RMC, "Retrain Margin Check", &EN_DIS, + Help "Enables/Disable Retrain Margin Check" + Combo $gPlatformFspPkgTokenSpaceGuid_WRDSUDT, "Write Drive Strength Up/Dn independently", &EN_DIS, + Help "Enables/Disable Write Drive Strength Up/Dn independently" + Combo $gPlatformFspPkgTokenSpaceGuid_EccSupport, "ECC Support", &EN_DIS, + Help "Enables/Disable ECC Support" + Combo $gPlatformFspPkgTokenSpaceGuid_RemapEnable, "Memory Remap", &EN_DIS, + Help "Enables/Disable Memory Remap" + Combo $gPlatformFspPkgTokenSpaceGuid_RankInterleave, "Rank Interleave support", &EN_DIS, + Help "Enables/Disable Rank Interleave support. NOTE: RI and HORI can not be enabled at the same time." + Combo $gPlatformFspPkgTokenSpaceGuid_EnhancedInterleave, "Enhanced Interleave support", &EN_DIS, + Help "Enables/Disable Enhanced Interleave support" + Combo $gPlatformFspPkgTokenSpaceGuid_ChHashEnable, "Ch Hash Support", &EN_DIS, + Help "Enable/Disable Channel Hash Support. NOTE: ONLY if Memory interleaved Mode" + Combo $gPlatformFspPkgTokenSpaceGuid_ChHashOverride, "Ch Hash Settings Override", &EN_DIS, + Help "Channel Hash Settings Override" + Combo $gPlatformFspPkgTokenSpaceGuid_EnableExtts, "Extern Therm Status", &EN_DIS, + Help "Enables/Disable Extern Therm Status" + Combo $gPlatformFspPkgTokenSpaceGuid_EnablePwrDn, "DDR PowerDown and idle counter", &EN_DIS, + Help "Enables/Disable DDR PowerDown and idle counter(For LPDDR Only)" + Combo $gPlatformFspPkgTokenSpaceGuid_EnablePwrDnLpddr, "DDR PowerDown and idle counter", &EN_DIS, + Help "Enables/Disable DDR PowerDown and idle counter(For LPDDR Only)" + Combo $gPlatformFspPkgTokenSpaceGuid_SrefCfgEna, "SelfRefresh Enable", &EN_DIS, + Help "Enables/Disable SelfRefresh Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_ThrtCkeMinDefeatLpddr, "Throttler CKEMin Defeature", &EN_DIS, + Help "Enables/Disable Throttler CKEMin Defeature(For LPDDR Only)" + Combo $gPlatformFspPkgTokenSpaceGuid_ThrtCkeMinDefeat, "Throttler CKEMin Defeature", &EN_DIS, + Help "Enables/Disable Throttler CKEMin Defeature" + Combo $gPlatformFspPkgTokenSpaceGuid_RhSelect, "Row Hammer Select", &gPlatformFspPkgTokenSpaceGuid_RhSelect, + Help "Row Hammer Select" + Combo $gPlatformFspPkgTokenSpaceGuid_ExitOnFailure, "Exit On Failure (MRC)", &EN_DIS, + Help "Enables/Disable Exit On Failure (MRC)" + Combo $gPlatformFspPkgTokenSpaceGuid_NewFeatureEnable1, "New Features 1 - MRC", &gPlatformFspPkgTokenSpaceGuid_NewFeatureEnable1, + Help "New Feature Enabling 1, 0:Disable, 1:Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_NewFeatureEnable2, "New Features 2 - MRC", &gPlatformFspPkgTokenSpaceGuid_NewFeatureEnable2, + Help "New Feature Enabling 2, 0:Disable, 1:Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_DCC, "Duty Cycle Correction Training", &EN_DIS, + Help "Enable/Disable Duty Cycle Correction Training" + Combo $gPlatformFspPkgTokenSpaceGuid_RDVC1D, "Read Voltage Centering 1D", &EN_DIS, + Help "Enable/Disable Read Voltage Centering 1D" + Combo $gPlatformFspPkgTokenSpaceGuid_TXTCO, "TxDqTCO Comp Training", &EN_DIS, + Help "Enable/Disable TxDqTCO Comp Training" + Combo $gPlatformFspPkgTokenSpaceGuid_CLKTCO, "ClkTCO Comp Training", &EN_DIS, + Help "Enable/Disable ClkTCO Comp Training" + Combo $gPlatformFspPkgTokenSpaceGuid_CMDSR, "CMD Slew Rate Training", &EN_DIS, + Help "Enable/Disable CMD Slew Rate Training" + Combo $gPlatformFspPkgTokenSpaceGuid_CMDDSEQ, "CMD Drive Strength and Tx Equalization", &EN_DIS, + Help "Enable/Disable CMD Drive Strength and Tx Equalization" + Combo $gPlatformFspPkgTokenSpaceGuid_DIMMODTCA, "DIMM CA ODT Training", &EN_DIS, + Help "Enable/Disable DIMM CA ODT Training" + Combo $gPlatformFspPkgTokenSpaceGuid_TXTCODQS, "TxDqsTCO Comp Training", &EN_DIS, + Help "Enable/Disable TxDqsTCO Comp Training" + Combo $gPlatformFspPkgTokenSpaceGuid_CMDDRUD, "CMD/CTL Drive Strength Up/Dn 2D", &EN_DIS, + Help "Enable/Disable CMD/CTL Drive Strength Up/Dn 2D" + Combo $gPlatformFspPkgTokenSpaceGuid_VCCDLLBP, "VccDLL Bypass Training", &EN_DIS, + Help "Enable/Disable VccDLL Bypass Training" + Combo $gPlatformFspPkgTokenSpaceGuid_PVTTDNLP, "PanicVttDnLp Training", &EN_DIS, + Help "Enable/Disable PanicVttDnLp Training" + Combo $gPlatformFspPkgTokenSpaceGuid_RDVREFDC, "Read Vref Decap Training*", &EN_DIS, + Help "Enable/Disable Read Vref Decap Training*" + Combo $gPlatformFspPkgTokenSpaceGuid_VDDQT, "Vddq Training", &EN_DIS, + Help "Enable/Disable Vddq Training" + Combo $gPlatformFspPkgTokenSpaceGuid_RMTBIT, "Rank Margin Tool Per Bit", &EN_DIS, + Help "Enable/Disable Rank Margin Tool Per Bit" + Combo $gPlatformFspPkgTokenSpaceGuid_EccDftEn, "ECC DFT feature", &EN_DIS, + Help "Enables/Disable ECC DFT feature" + Combo $gPlatformFspPkgTokenSpaceGuid_Write0, "Write0 feature", &EN_DIS, + Help "Enables/Disable Write0 feature" + Combo $gPlatformFspPkgTokenSpaceGuid_Ddr4DdpSharedClock, "Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP", &EN_DIS, + Help "Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP" + Combo $gPlatformFspPkgTokenSpaceGuid_Ddr4DdpSharedZq, "Select if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP", &EN_DIS, + Help "ESelect if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP" + Combo $gPlatformFspPkgTokenSpaceGuid_ChHashInterleaveBit, "Ch Hash Interleaved Bit", &gPlatformFspPkgTokenSpaceGuid_ChHashInterleaveBit, + Help "Select the BIT to be used for Channel Interleaved mode. NOTE: BIT7 will interlave the channels at a 2 cacheline granularity, BIT8 at 4 and BIT9 at 8. Default is BIT8" + EditNum $gPlatformFspPkgTokenSpaceGuid_ChHashMask, "Ch Hash Mask", HEX, + Help "Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to BITS [19:6] Default is 0x30CC" + "Valid range: 0x0000 ~ 0x3FFF" + Combo $gPlatformFspPkgTokenSpaceGuid_BClkFrequency, "Base reference clock value", &gPlatformFspPkgTokenSpaceGuid_BClkFrequency, + Help "Base reference clock value, in Hertz(Default is 100Hz)" + EditNum $gPlatformFspPkgTokenSpaceGuid_Idd3n, "EPG DIMM Idd3N", HEX, + Help "Active standby current (Idd3N) in milliamps from datasheet. Must be calculated on a per DIMM basis. Default is 26" + "Valid range: 0x00 ~ 0x7D0" + EditNum $gPlatformFspPkgTokenSpaceGuid_Idd3p, "EPG DIMM Idd3P", HEX, + Help "Active power-down current (Idd3P) in milliamps from datasheet. Must be calculated on a per DIMM basis. Default is 11" + "Valid range: 0x00 ~ 0x7D0" + Combo $gPlatformFspPkgTokenSpaceGuid_CMDNORM, "CMD Normalization", &EN_DIS, + Help "Enable/Disable CMD Normalization" + Combo $gPlatformFspPkgTokenSpaceGuid_EWRDSEQ, "Early DQ Write Drive Strength and Equalization Training", &EN_DIS, + Help "Enable/Disable Early DQ Write Drive Strength and Equalization Training" + Combo $gPlatformFspPkgTokenSpaceGuid_McRefresh2X, "MC_REFRESH_2X_MODE", &EN_DIS, + Help "DEPRECATED" + EditNum $gPlatformFspPkgTokenSpaceGuid_IdleEnergyMc0Ch0Dimm0, "Idle Energy Mc0Ch0Dimm0", HEX, + Help "Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)" + "Valid range: 0x0 ~ 0x3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_IdleEnergyMc0Ch0Dimm1, "Idle Energy Mc0Ch0Dimm1", HEX, + Help "Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)" + "Valid range: 0x0 ~ 0x3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_IdleEnergyMc0Ch1Dimm0, "Idle Energy Mc0Ch1Dimm0", HEX, + Help "Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)" + "Valid range: 0x0 ~ 0x3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_IdleEnergyMc0Ch1Dimm1, "Idle Energy Mc0Ch1Dimm1", HEX, + Help "Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)" + "Valid range: 0x0 ~ 0x3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_IdleEnergyMc1Ch0Dimm0, "Idle Energy Mc1Ch0Dimm0", HEX, + Help "Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)" + "Valid range: 0x0 ~ 0x3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_IdleEnergyMc1Ch0Dimm1, "Idle Energy Mc1Ch0Dimm1", HEX, + Help "Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)" + "Valid range: 0x0 ~ 0x3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_IdleEnergyMc1Ch1Dimm0, "Idle Energy Mc1Ch1Dimm0", HEX, + Help "Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)" + "Valid range: 0x0 ~ 0x3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_IdleEnergyMc1Ch1Dimm1, "Idle Energy Mc1Ch1Dimm1", HEX, + Help "Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)" + "Valid range: 0x0 ~ 0x3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PdEnergyMc0Ch0Dimm0, "PowerDown Energy Mc0Ch0Dimm0", HEX, + Help "PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def)" + "Valid range: 0x0 ~ 0x3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PdEnergyMc0Ch0Dimm1, "PowerDown Energy Mc0Ch0Dimm1", HEX, + Help "PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def)" + "Valid range: 0x0 ~ 0x3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PdEnergyMc0Ch1Dimm0, "PowerDown Energy Mc0Ch1Dimm0", HEX, + Help "PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def)" + "Valid range: 0x0 ~ 0x3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PdEnergyMc0Ch1Dimm1, "PowerDown Energy Mc0Ch1Dimm1", HEX, + Help "PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def)" + "Valid range: 0x0 ~ 0x3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PdEnergyMc1Ch0Dimm0, "PowerDown Energy Mc1Ch0Dimm0", HEX, + Help "PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def)" + "Valid range: 0x0 ~ 0x3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PdEnergyMc1Ch0Dimm1, "PowerDown Energy Mc1Ch0Dimm1", HEX, + Help "PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def)" + "Valid range: 0x0 ~ 0x3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PdEnergyMc1Ch1Dimm0, "PowerDown Energy Mc1Ch1Dimm0", HEX, + Help "PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def)" + "Valid range: 0x0 ~ 0x3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PdEnergyMc1Ch1Dimm1, "PowerDown Energy Mc1Ch1Dimm1", HEX, + Help "PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def)" + "Valid range: 0x0 ~ 0x3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_ActEnergyMc0Ch0Dimm0, "Activate Energy Mc0Ch0Dimm0", HEX, + Help "Activate Energy Contribution, range[255;0],(172= Def)" + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ActEnergyMc0Ch0Dimm1, "Activate Energy Mc0Ch0Dimm1", HEX, + Help "Activate Energy Contribution, range[255;0],(172= Def)" + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ActEnergyMc0Ch1Dimm0, "Activate Energy Mc0Ch1Dimm0", HEX, + Help "Activate Energy Contribution, range[255;0],(172= Def)" + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ActEnergyMc0Ch1Dimm1, "Activate Energy Mc0Ch1Dimm1", HEX, + Help "Activate Energy Contribution, range[255;0],(172= Def)" + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ActEnergyMc1Ch0Dimm0, "Activate Energy Mc1Ch0Dimm0", HEX, + Help "Activate Energy Contribution, range[255;0],(172= Def)" + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ActEnergyMc1Ch0Dimm1, "Activate Energy Mc1Ch0Dimm1", HEX, + Help "Activate Energy Contribution, range[255;0],(172= Def)" + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ActEnergyMc1Ch1Dimm0, "Activate Energy Mc1Ch1Dimm0", HEX, + Help "Activate Energy Contribution, range[255;0],(172= Def)" + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ActEnergyMc1Ch1Dimm1, "Activate Energy Mc1Ch1Dimm1", HEX, + Help "Activate Energy Contribution, range[255;0],(172= Def)" + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_RdEnergyMc0Ch0Dimm0, "Read Energy Mc0Ch0Dimm0", HEX, + Help "Read Energy Contribution, range[255;0],(212= Def)" + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_RdEnergyMc0Ch0Dimm1, "Read Energy Mc0Ch0Dimm1", HEX, + Help "Read Energy Contribution, range[255;0],(212= Def)" + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_RdEnergyMc0Ch1Dimm0, "Read Energy Mc0Ch1Dimm0", HEX, + Help "Read Energy Contribution, range[255;0],(212= Def)" + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_RdEnergyMc0Ch1Dimm1, "Read Energy Mc0Ch1Dimm1", HEX, + Help "Read Energy Contribution, range[255;0],(212= Def)" + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_RdEnergyMc1Ch0Dimm0, "Read Energy Mc1Ch0Dimm0", HEX, + Help "Read Energy Contribution, range[255;0],(212= Def)" + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_RdEnergyMc1Ch0Dimm1, "Read Energy Mc1Ch0Dimm1", HEX, + Help "Read Energy Contribution, range[255;0],(212= Def)" + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_RdEnergyMc1Ch1Dimm0, "Read Energy Mc1Ch1Dimm0", HEX, + Help "Read Energy Contribution, range[255;0],(212= Def)" + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_RdEnergyMc1Ch1Dimm1, "Read Energy Mc1Ch1Dimm1", HEX, + Help "Read Energy Contribution, range[255;0],(212= Def)" + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_WrEnergyMc0Ch0Dimm0, "Write Energy Mc0Ch0Dimm0", HEX, + Help "Write Energy Contribution, range[255;0],(221= Def)" + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_WrEnergyMc0Ch0Dimm1, "Write Energy Mc0Ch0Dimm1", HEX, + Help "Write Energy Contribution, range[255;0],(221= Def)" + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_WrEnergyMc0Ch1Dimm0, "Write Energy Mc0Ch1Dimm0", HEX, + Help "Write Energy Contribution, range[255;0],(221= Def)" + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_WrEnergyMc0Ch1Dimm1, "Write Energy Mc0Ch1Dimm1", HEX, + Help "Write Energy Contribution, range[255;0],(221= Def)" + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_WrEnergyMc1Ch0Dimm0, "Write Energy Mc1Ch0Dimm0", HEX, + Help "Write Energy Contribution, range[255;0],(221= Def)" + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_WrEnergyMc1Ch0Dimm1, "Write Energy Mc1Ch0Dimm1", HEX, + Help "Write Energy Contribution, range[255;0],(221= Def)" + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_WrEnergyMc1Ch1Dimm0, "Write Energy Mc1Ch1Dimm0", HEX, + Help "Write Energy Contribution, range[255;0],(221= Def)" + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_WrEnergyMc1Ch1Dimm1, "Write Energy Mc1Ch1Dimm1", HEX, + Help "Write Energy Contribution, range[255;0],(221= Def)" + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThrtCkeMinTmr, "Throttler CKEMin Timer", HEX, + Help "Timer value for CKEMin, range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH (4). Dfault is 0x00" + "Valid range: 0x0 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_AllowOppRefBelowWriteThrehold, "Allow Opp Ref Below Write Threhold", &EN_DIS, + Help "Allow opportunistic refreshes while we don't exit power down." + EditNum $gPlatformFspPkgTokenSpaceGuid_WriteThreshold, "Write Threshold", HEX, + Help "Number of writes that can be accumulated while CKE is low before CKE is asserted." + "Valid range: 0x00 ~ 0x3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_RaplPwrFlCh0, "Rapl Power Floor Ch0", HEX, + Help "Power budget ,range[255;0],(0= 5.3W Def)" + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_RaplPwrFlCh1, "Rapl Power Floor Ch1", HEX, + Help "Power budget ,range[255;0],(0= 5.3W Def)" + "Valid range: 0x0 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_EnCmdRate, "Command Rate Support", &gPlatformFspPkgTokenSpaceGuid_EnCmdRate, + Help "CMD Rate and Limit Support Option. NOTE: ONLY supported in 1N Mode, Default is 3 CMDs" + Combo $gPlatformFspPkgTokenSpaceGuid_Refresh2X, "REFRESH_2X_MODE", &gPlatformFspPkgTokenSpaceGuid_Refresh2X, + Help "0- (Default)Disabled 1-iMC enables 2xRef when Warm and Hot 2- iMC enables 2xRef when Hot" + Combo $gPlatformFspPkgTokenSpaceGuid_EpgEnable, "Energy Performance Gain", &EN_DIS, + Help "Enable/disable(default) Energy Performance Gain." + EditNum $gPlatformFspPkgTokenSpaceGuid_Lfsr0Mask, "RH pTRR LFSR0 Mask", HEX, + Help "Row Hammer pTRR LFSR0 Mask, 1/2^(value)" + "Valid range: 0x01 ~ 0xF" + Combo $gPlatformFspPkgTokenSpaceGuid_UserThresholdEnable, "User Manual Threshold", &EN_DIS, + Help "Disabled: Predefined threshold will be used.\nEnabled: User Input will be used." + Combo $gPlatformFspPkgTokenSpaceGuid_UserBudgetEnable, "User Manual Budget", &EN_DIS, + Help "Disabled: Configuration of memories will defined the Budget value.\nEnabled: User Input will be used." + Combo $gPlatformFspPkgTokenSpaceGuid_PowerDownMode, "Power Down Mode", &gPlatformFspPkgTokenSpaceGuid_PowerDownMode, + Help "This option controls command bus tristating during idle periods" + EditNum $gPlatformFspPkgTokenSpaceGuid_PwdwnIdleCounter, "Pwr Down Idle Timer", HEX, + Help "The minimum value should = to the worst case Roundtrip delay + Burst_Length. 0 means AUTO: 64 for ULX/ULT, 128 for DT/Halo" + "Valid range: 0x0 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_DisPgCloseIdleTimeout, "Page Close Idle Timeout", &gPlatformFspPkgTokenSpaceGuid_DisPgCloseIdleTimeout, + Help "This option controls Page Close Idle Timeout" + EditNum $gPlatformFspPkgTokenSpaceGuid_CmdRanksTerminated, "Bitmask of ranks that have CA bus terminated", HEX, + Help "Offset 225 LPDDR4: Bitmask of ranks that have CA bus terminated. 0x01=Default, Rank0 is terminating and Rank1 is non-terminating" + "Valid range: 0x0 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_SafeMode, "Safe Mode Support", &EN_DIS, + Help "This option configures the varous items in the IO and MC to be more conservative.(def=Disable)" + Combo $gPlatformFspPkgTokenSpaceGuid_CleanMemory, "Ask MRC to clear memory content", &EN_DIS, + Help "Ask MRC to clear memory content 0: Do not Clear Memory; 1: Clear Memory." + Combo $gPlatformFspPkgTokenSpaceGuid_LpDdrDqDqsReTraining, "LpDdrDqDqsReTraining", &EN_DIS, + Help "Enable/Disable TxDqDqs ReTraining for LP4/5 and DDR5" + EditNum $gPlatformFspPkgTokenSpaceGuid_RMTLoopCount, "RMTLoopCount", HEX, + Help "Specifies the Loop Count to be used during Rank Margin Tool Testing. 0 - AUTO" + "Valid range: 0 ~ 0x20" + EditNum $gPlatformFspPkgTokenSpaceGuid_BclkRfiFreq, "BCLK RFI Frequency", HEX, + Help "Bclk RFI Frequency for each SAGV point in Hz units. 98000000Hz = 98MHz 0 - No RFI Tuning. Range is 98Mhz-100Mhz." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_RefreshPanicWm, "REFRESH_PANIC_WM", HEX, + Help "DEPRECATED" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_RefreshHpWm, "REFRESH_HP_WM", HEX, + Help "DEPRECATED" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_Lp5CccConfig, "Command Pins Mapping", HEX, + Help "BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller 1 Channel [3:0]. 0 = CCC pin mapping is Ascending, 1 = CCC pin mapping is Descending." + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CmdMirror, "Command Pins Mirrored", HEX, + Help "BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller 1 Channel [3:0]. 0 = No Command Mirror and 1 = Command Mirror." + "Valid range: 0x00 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_DIMMDFE, "DIMM DFE Training", &EN_DIS, + Help "Enable/Disable DIMM DFE Training" + Combo $gPlatformFspPkgTokenSpaceGuid_ExtendedBankHashing, "Extended Bank Hashing", &EN_DIS, + Help "Enable/Disable Extended Bank Hashing" + Combo $gPlatformFspPkgTokenSpaceGuid_RefreshWm, "Refresh Watermarks", &gPlatformFspPkgTokenSpaceGuid_RefreshWm, + Help "Refresh Watermarks: 0-Low, 1-High (default)" + Combo $gPlatformFspPkgTokenSpaceGuid_McRefreshRate, "MC_REFRESH_RATE", &gPlatformFspPkgTokenSpaceGuid_McRefreshRate, + Help "Type of Refresh Rate used to prevent Row Hammer. Default is NORMAL Refresh" + Combo $gPlatformFspPkgTokenSpaceGuid_PeriodicDcc, "Periodic DCC", &EN_DIS, + Help "Enable/Disable Periodic DCC; default: Disabled" + Combo $gPlatformFspPkgTokenSpaceGuid_LpMode, "LpMode", &gPlatformFspPkgTokenSpaceGuid_LpMode, + Help "LpMode feature" + Combo $gPlatformFspPkgTokenSpaceGuid_TXDQSDCC, "TX DQS DCC Training", &EN_DIS, + Help "Enable/Disable TX DQS DCC Training" + Combo $gPlatformFspPkgTokenSpaceGuid_DRAMDCA, "DRAM DCA Training", &EN_DIS, + Help "Enable/Disable DRAM DCA Training" + Combo $gPlatformFspPkgTokenSpaceGuid_EARLYDIMMDFE, "EARLY DIMM DFE Training", &EN_DIS, + Help "Enable/Disable EARLY DIMM DFE Training" + Combo $gPlatformFspPkgTokenSpaceGuid_BdatEnable, "Generate BIOS Data ACPI Table", &EN_DIS, + Help "Enable: Generate BDAT for MRC RMT or SA PCIe data. Disable (Default): Do not generate it" + Combo $gPlatformFspPkgTokenSpaceGuid_LockPTMregs, "Lock PCU Thermal Management registers", &EN_DIS, + Help "Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0" + Combo $gPlatformFspPkgTokenSpaceGuid_PegGen3Rsvd, "Rsvd", &EN_DIS, + Help "Disable(0x0)(Default): Normal Operation - RxCTLE adaptive behavior enabled, Enable(0x1): Override RxCTLE - Disable RxCTLE adaptive behavior to keep the configured RxCTLE peak values unmodified" + Combo $gPlatformFspPkgTokenSpaceGuid_PanelPowerEnable, "Panel Power Enable", &EN_DIS, + Help "Control for enabling/disabling VDD force bit (Required only for early enabling of eDP panel). 0=Disable, 1(Default)=Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_BdatTestType, "BdatTestType", &gPlatformFspPkgTokenSpaceGuid_BdatTestType, + Help "Indicates the type of Memory Training data to populate into the BDAT ACPI table." + Combo $gPlatformFspPkgTokenSpaceGuid_ReuseAdlSDdr5Board, "Reuse Adl DDR5 Board or not", &gPlatformFspPkgTokenSpaceGuid_ReuseAdlSDdr5Board, + Help "Indicate whether adl ddr5 board is reused." + Combo $gPlatformFspPkgTokenSpaceGuid_OemT12DelayOverride, "Oem T12 Delay Override", &EN_DIS, + Help "Oem T12 Delay Override. 0(Default)=Disable 1=Enable " + Combo $gPlatformFspPkgTokenSpaceGuid_SaPreMemTestRsvd, "SaPreMemTestRsvd", &EN_DIS, + Help "Reserved for SA Pre-Mem Test" + Combo $gPlatformFspPkgTokenSpaceGuid_MarginLimitCheck, "Margin Limit Check", &gPlatformFspPkgTokenSpaceGuid_MarginLimitCheck, + Help "Margin Limit Check. Choose level of margin check" + EditNum $gPlatformFspPkgTokenSpaceGuid_MarginLimitL2, "Margin Limit L2", HEX, + Help "% of L1 check for margin limit check" + "Valid range: 0x01 ~ 0x12C" + EditNum $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpCdrRelock, "DEKEL CDR Relock", HEX, + Help "Enable/Disable CDR Relock. 0: Disable(Default); 1: Enable" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_DmiCdrRelock, "DMI DEKEL CDR Relock", &EN_DIS, + Help "Enable/Disable CPU DMI CDR Relock. 0: Disable(Default); 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_IbeccErrInjControl, "IbeccErrInjControl", &gPlatformFspPkgTokenSpaceGuid_IbeccErrInjControl, + Help "IBECC Error Injection Control" + EditNum $gPlatformFspPkgTokenSpaceGuid_IbeccErrInjAddress, "IbeccErrInjAddress", HEX, + Help "Address to match against for ECC error injection" + "Valid range: 0x0 ~ 0x3FFFFFFFFFC0" + EditNum $gPlatformFspPkgTokenSpaceGuid_IbeccErrInjMask, "IbeccErrInjMask", HEX, + Help "Mask to match against for ECC error injection" + "Valid range: 0x0 ~ 0x3FFFFFFFFFC0" + EditNum $gPlatformFspPkgTokenSpaceGuid_IbeccErrInjCount, "IbeccErrInjCount", HEX, + Help "Number of transactions between ECC error injection" + "Valid range: 0x0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_EnableDmaBuffer, "Pointer EnableDmaBuffer", HEX, + Help "Pointer of EnableDmaBuffer Callback Function." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PllMaxBandingRatio, "PLL Max Banding Ratio", HEX, + Help "DEPRECATED" + "Valid range: 0x0 ~ 0x78" + EditNum $gPlatformFspPkgTokenSpaceGuid_DebugValue, "Debug Value", HEX, + Help "Debug Value" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_BoardGpioTablePreMemAddress, "Pre-Mem GPIO table address", HEX, + Help "AlderLake S needs to assert PCIe SLOT RTD3 and PEG reset pins in early PreMem phase. 0: Skip FSP PCIe pins programming. Refer to mAdlSPcieRstPinGpioTable[] in GpioSampleDef.h." + "Valid range: 0x0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_tRFCpb, "tRFCpb", HEX, + Help "Min Internal per bank refresh recovery delay time, 0: AUTO, max: 0xFFFF. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile)." + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_tRFC2, "tRFC2", HEX, + Help "Min Internal refresh recovery delay time, 0: AUTO, max: 0xFFFF. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile)." + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_tRFC4, "tRFC4", HEX, + Help "Min Internal refresh recovery delay time, 0: AUTO, max: 0xFFFF. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile)." + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_tRRD_L, "tRRD_L", HEX, + Help "Min Internal row active to row active delay time for same bank groups, 0: AUTO, max: 80. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile)." + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_tRRD_S, "tRRD_S", HEX, + Help "Min Internal row active to row active delay time for different bank groups, 0: AUTO, max: 80. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile)." + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_tWTR_L, "tWTR_L", HEX, + Help "Min Internal write to read command delay time for same bank groups, 0: AUTO, max: 127. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile)." + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_tCCD_L, "tCCD_L", HEX, + Help "Min Internal CAS-to-CAS delay for same bank group, 0: AUTO, max: 80. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile)." + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_tWTR_S, "tWTR_S", HEX, + Help "Min Internal write to read command delay time for different bank groups, 0: AUTO, max: 50. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile)." + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_EccErrInjAddress, "EccErrInjAddress", HEX, + Help "Address to match against for ECC error injection" + "Valid range: 0x0 ~ 0x1FFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_EccErrInjMask, "EccErrInjMask", HEX, + Help "Mask to match against for ECC error injection" + "Valid range: 0x0 ~ 0x1FFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_EccErrInjCount, "EccErrInjCount", HEX, + Help "Number of transactions between ECC error injection" + "Valid range: 0x0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_FreqLimitMixedConfig, "Frequency Limit for 2DPC Mixed or non-POR Config", DEC, + Help "Frequency Limit for 2DPC Mixed or non-POR Config. 0: Auto (default), otherwise a frequency in MT/s" + "Valid range: 0 ~ 10000" + EditNum $gPlatformFspPkgTokenSpaceGuid_FirstDimmBitMask, "First Dimm BitMask", HEX, + Help "Defines which DIMM should be populated first on a 2DPC board. Bit0: MC0 DIMM0, Bit1: MC0 DIMM1, Bit2: MC1 DIMM0, Bit3: MC1 DIMM1. For each MC, the first DIMM to be populated should be set to '1'" + "Valid range: 0x00 ~ 0x0F" + EditNum $gPlatformFspPkgTokenSpaceGuid_SagvSwitchFactorIA, "SAGV Switch Factor IA DDR BW", DEC, + Help "SAGV Switch Factor IA DDR BW: IA DDR load percentage when system switch to high SAGV point from 1 to 50%." + "Valid range: 1 ~ 50" + EditNum $gPlatformFspPkgTokenSpaceGuid_SagvSwitchFactorGT, "SAGV Switch Factor GT DDR BW", DEC, + Help "SAGV Switch Factor GT DDR BW: GT DDR load percentage when system switch to high SAGV point from 1 to 50%." + "Valid range: 1 ~ 50" + EditNum $gPlatformFspPkgTokenSpaceGuid_SagvSwitchFactorIO, "SAGV Switch Factor IO DDR BW", DEC, + Help "SAGV Switch Factor IO DDR BW: IO DDR load percentage when system switch to high SAGV point from 1 to 50%." + "Valid range: 1 ~ 50" + EditNum $gPlatformFspPkgTokenSpaceGuid_SagvSwitchFactorStall, "SAGV Switch Factor IA and GT Stall", DEC, + Help "SAGV Switch Factor IA and GT Stall: IA and GT percentage when system switch to high SAGV point from 1 to 50%." + "Valid range: 1 ~ 50" + EditNum $gPlatformFspPkgTokenSpaceGuid_SagvHeuristicsDownControl, "Threshold For Switch Down", DEC, + Help "SAGV heuristics down control: Duration in ms of low activity after which SAGV will switch down, from 1 to 50ms." + "Valid range: 1 ~ 50" + EditNum $gPlatformFspPkgTokenSpaceGuid_SagvHeuristicsUpControl, "Threshold For Switch Up", DEC, + Help "SAGV heuristics up control: Duration in ms of low activity after which SAGV will switch up, from 1 to 50ms." + "Valid range: 1 ~ 50" + EditNum $gPlatformFspPkgTokenSpaceGuid_FreqLimitMixedConfig_1R1R_8GB, "Frequency Limit for Mixed 2DPC DDR5 1 Rank 8GB and 8GB", DEC, + Help "Frequency Limit for 2DPC Mixed or non-POR Config. 0: Auto, otherwise a frequency in MT/s, default is 2000" + "Valid range: 0 ~ 10000" + EditNum $gPlatformFspPkgTokenSpaceGuid_FreqLimitMixedConfig_1R1R_16GB, "Frequency Limit for Mixed 2DPC DDR5 1 Rank 16GB and 16GB", DEC, + Help "Frequency Limit for 2DPC Mixed or non-POR Config. 0: Auto, otherwise a frequency in MT/s, default is 2000" + "Valid range: 0 ~ 10000" + EditNum $gPlatformFspPkgTokenSpaceGuid_FreqLimitMixedConfig_1R1R_8GB_16GB, "Frequency Limit for Mixed 2DPC DDR5 1 Rank 8GB and 16GB", DEC, + Help "Frequency Limit for 2DPC Mixed or non-POR Config. 0: Auto, otherwise a frequency in MT/s, default is 2000" + "Valid range: 0 ~ 10000" + EditNum $gPlatformFspPkgTokenSpaceGuid_FreqLimitMixedConfig_2R2R, "Frequency Limit for Mixed 2DPC DDR5 2 Rank", DEC, + Help "Frequency Limit for 2DPC Mixed or non-POR Config. 0: Auto, otherwise a frequency in MT/s, default is 2000" + "Valid range: 0 ~ 10000" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchDmiHwEqGen3CoeffListCm, "DMI Hw Eq Gen3 CoeffList Cm", HEX, + Help "PCH_DMI_EQ_PARAM. Coefficient C-1." + "Valid range: 0x00 ~ 0xFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchDmiHwEqGen3CoeffListCp, "DMI Hw Eq Gen3 CoeffList Cp", HEX, + Help "PCH_DMI_EQ_PARAM. Coefficient C+1." + "Valid range: 0x00 ~ 0xFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_LctCmdEyeWidth, " LCT Command eyewidth", DEC, + Help " LCT Command eyewidth. 0: Auto, otherwise eyewidth , default is 96" + "Valid range: 0 ~ 256" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThrtCkeMinTmrLpddr, "For LPDDR Only: Throttler CKEMin Timer", HEX, + Help "For LPDDR Only: Timer value for CKEMin, range[255;0]. Reqd min of SC_ROUND_T + BYTE_LENGTH (4). Dfault is 0x00" + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_FirstDimmBitMaskEcc, "First ECC Dimm BitMask", HEX, + Help "Defines which ECC DIMM should be populated first on a 2DPC board. Bit0: MC0 DIMM0, Bit1: MC0 DIMM1, Bit2: MC1 DIMM0, Bit3: MC1 DIMM1. For each MC, the first DIMM to be populated should be set to '1'" + "Valid range: 0x00 ~ 0x0F" + Combo $gPlatformFspPkgTokenSpaceGuid_Lp5BankMode, " LP5 Bank Mode", &gPlatformFspPkgTokenSpaceGuid_Lp5BankMode, + Help " LP5 Bank Mode. 0: Auto, 1: 8 Bank Mode, 2: 16 Bank Mode, 3: BG Mode, default is 0" + Combo $gPlatformFspPkgTokenSpaceGuid_WRDS, "Write DS Training", &EN_DIS, + Help "Enable/Disable Write DS Training" + Combo $gPlatformFspPkgTokenSpaceGuid_OverloadSAM, "SAM Overlaoding", &EN_DIS, + Help "Enable: copy the sagv frequency point. Disable: not copy." +EndPage + +Page "CPU (Pre-Mem)" + Combo $gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMode, "CPU Trace Hub Mode", &gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMode, + Help "Select 'Host Debugger' if Trace Hub is used with host debugger tool or 'Target Debugger' if Trace Hub is used by target debugger software or 'Disable' trace hub functionality." + Combo $gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMemReg0Size, "CPU Trace Hub Memory Region 0", &gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMemReg0Size, + Help "CPU Trace Hub Memory Region 0, The avaliable memory size is : 0MB, 1MB, 8MB, 64MB, 128MB, 256MB, 512MB" + Combo $gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMemReg1Size, "CPU Trace Hub Memory Region 1", &gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMemReg1Size, + Help "CPU Trace Hub Memory Region 1. The avaliable memory size is : 0MB, 1MB, 8MB, 64MB, 128MB, 256MB, 512MB" + Combo $gPlatformFspPkgTokenSpaceGuid_BistOnReset, "BIST on Reset", &EN_DIS, + Help "Enable or Disable BIST on Reset; 0: Disable; 1: Enable." + Combo $gPlatformFspPkgTokenSpaceGuid_SkipStopPbet, "Skip Stop PBET Timer Enable/Disable", &EN_DIS, + Help "Skip Stop PBET Timer; 0: Disable; 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_EnableC6Dram, "C6DRAM power gating feature", &EN_DIS, + Help "This policy indicates whether or not BIOS should allocate PRMRR memory for C6DRAM power gating feature.- 0: Don't allocate any PRMRR memory for C6DRAM power gating feature.- 1: Allocate PRMRR memory for C6DRAM power gating feature." + Combo $gPlatformFspPkgTokenSpaceGuid_OcSupport, "Over clocking support", &EN_DIS, + Help "Over clocking support; 0: Disable; 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_OcLock, "Over clocking Lock", &EN_DIS, + Help "Over clocking Lock Enable/Disable; 0: Disable; 1: Enable" + EditNum $gPlatformFspPkgTokenSpaceGuid_CoreMaxOcRatio, "Maximum Core Turbo Ratio Override", HEX, + Help "Maximum core turbo ratio override allows to increase CPU core frequency beyond the fused max turbo ratio limit. 0: Hardware defaults. Range: 0-85" + "Valid range: 0x00 ~ 0x53" + Combo $gPlatformFspPkgTokenSpaceGuid_CoreVoltageMode, "Core voltage mode", &EN_DIS, + Help "Core voltage mode; 0: Adaptive; 1: Override." + EditNum $gPlatformFspPkgTokenSpaceGuid_RingMaxOcRatio, "Maximum clr turbo ratio override", HEX, + Help "Maximum clr turbo ratio override allows to increase CPU clr frequency beyond the fused max turbo ratio limit. 0: Hardware defaults. Range: 0-85" + "Valid range: 0x00 ~ 0x53" + Combo $gPlatformFspPkgTokenSpaceGuid_HyperThreading, "Hyper Threading Enable/Disable", &EN_DIS, + Help "Enable or Disable Hyper Threading; 0: Disable; 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_CpuRatioOverride, "Enable or Disable CPU Ratio Override", &EN_DIS, + Help "Enable or Disable CPU Ratio Override; 0: Disable; 1: Enable." + EditNum $gPlatformFspPkgTokenSpaceGuid_CpuRatio, "CPU ratio value", HEX, + Help "CPU ratio value. Valid Range 0 to 63" + "Valid range: 0x00 ~ 0x3F" + Combo $gPlatformFspPkgTokenSpaceGuid_BootFrequency, "Boot frequency", &gPlatformFspPkgTokenSpaceGuid_BootFrequency, + Help "Sets the boot frequency starting from reset vector.- 0: Maximum battery performance. 1: Maximum non-turbo performance. 2: Turbo performance " + Combo $gPlatformFspPkgTokenSpaceGuid_ActiveCoreCount, "Number of active big cores", &gPlatformFspPkgTokenSpaceGuid_ActiveCoreCount, + Help "Number of active big cores(Depends on Number of big cores). Default 0xFF means to active all system supported big cores. 0xFF: Active all big cores; 0: Disable all big cores; 1: 1; 2: 2; 3: 3;" + Combo $gPlatformFspPkgTokenSpaceGuid_FClkFrequency, "Processor Early Power On Configuration FCLK setting", &gPlatformFspPkgTokenSpaceGuid_FClkFrequency, + Help " 0: 800 MHz (ULT/ULX). 1: 1 GHz (DT/Halo). Not supported on ULT/ULX.- 2: 400 MHz. - 3: Reserved" + Combo $gPlatformFspPkgTokenSpaceGuid_JtagC10PowerGateDisable, "Set JTAG power in C10 and deeper power states", &gPlatformFspPkgTokenSpaceGuid_JtagC10PowerGateDisable, + Help "False: JTAG is power gated in C10 state. True: keeps the JTAG power up during C10 and deeper power states for debug purpose. 0: False; 1: True." + Combo $gPlatformFspPkgTokenSpaceGuid_VmxEnable, "Enable or Disable VMX", &EN_DIS, + Help "Enable or Disable VMX; 0: Disable; 1: Enable." + EditNum $gPlatformFspPkgTokenSpaceGuid_Avx2RatioOffset, "AVX2 Ratio Offset", HEX, + Help "0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B." + "Valid range: 0x00 ~ 0x1F" + EditNum $gPlatformFspPkgTokenSpaceGuid_Avx3RatioOffset, "AVX3 Ratio Offset", HEX, + Help "DEPRECATED" + "Valid range: 0x00 ~ 0x1F" + Combo $gPlatformFspPkgTokenSpaceGuid_BclkAdaptiveVoltage, "BCLK Adaptive Voltage Enable", &EN_DIS, + Help "When enabled, the CPU V/F curves are aware of BCLK frequency when calculated. 0: Disable; 1: Enable" + EditNum $gPlatformFspPkgTokenSpaceGuid_CoreVoltageOverride, "core voltage override", HEX, + Help "The core voltage override which is applied to the entire range of cpu core frequencies. Valid Range 0 to 2000" + "Valid range: 0x00 ~ 0x7D0" + EditNum $gPlatformFspPkgTokenSpaceGuid_CoreVoltageAdaptive, "Core Turbo voltage Adaptive", HEX, + Help "Extra Turbo voltage applied to the cpu core when the cpu is operating in turbo mode. Valid Range 0 to 2000" + "Valid range: 0x00 ~ 0x7D0" + EditNum $gPlatformFspPkgTokenSpaceGuid_CoreVoltageOffset, "Core Turbo voltage Offset", HEX, + Help "The voltage offset applied to the core while operating in turbo mode.Valid Range 0 to 1000" + "Valid range: 0x00 ~ 0x3E8" + EditNum $gPlatformFspPkgTokenSpaceGuid_CorePllVoltageOffset, "Core PLL voltage offset", HEX, + Help "Core PLL voltage offset. 0: No offset. Range 0-15" + "Valid range: 0x00 ~ 0x0F" + EditNum $gPlatformFspPkgTokenSpaceGuid_AtomPllVoltageOffset, "Atom Core PLL voltage offset", HEX, + Help "Atom Core PLL voltage offset. 0: No offset. Range 0-15" + "Valid range: 0x00 ~ 0x0F" + Combo $gPlatformFspPkgTokenSpaceGuid_RingDownBin, "Ring Downbin", &EN_DIS, + Help "Ring Downbin enable/disable. When enabled, CPU will ensure the ring ratio is always lower than the core ratio.0: Disable; 1: Enable." + Combo $gPlatformFspPkgTokenSpaceGuid_RingVoltageMode, "Ring voltage mode", &EN_DIS, + Help "Ring voltage mode; 0: Adaptive; 1: Override." + EditNum $gPlatformFspPkgTokenSpaceGuid_TjMaxOffset, "TjMax Offset", HEX, + Help "TjMax offset.Specified value here is clipped by pCode (125 - TjMax Offset) to support TjMax in the range of 62 to 115 deg Celsius. Valid Range 10 - 63" + "Valid range: 0x0A ~ 0x3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_RingVoltageOverride, "Ring voltage override", HEX, + Help "The ring voltage override which is applied to the entire range of cpu ring frequencies. Valid Range 0 to 2000" + "Valid range: 0x00 ~ 0x7D0" + EditNum $gPlatformFspPkgTokenSpaceGuid_RingVoltageAdaptive, "Ring Turbo voltage Adaptive", HEX, + Help "Extra Turbo voltage applied to the cpu ring when the cpu is operating in turbo mode. Valid Range 0 to 2000" + "Valid range: 0x00 ~ 0x7D0" + EditNum $gPlatformFspPkgTokenSpaceGuid_RingVoltageOffset, "Ring Turbo voltage Offset", HEX, + Help "The voltage offset applied to the ring while operating in turbo mode. Valid Range 0 to 1000" + "Valid range: 0x00 ~ 0x3E8" + Combo $gPlatformFspPkgTokenSpaceGuid_TmeEnable, "Enable or Disable TME", &EN_DIS, + Help "Enable or Disable TME; 0: Disable; 1: Enable." + Combo $gPlatformFspPkgTokenSpaceGuid_CpuCrashLogEnable, "Enable CPU CrashLog", &EN_DIS, + Help "Enable or Disable CPU CrashLog; 0: Disable; 1: Enable." + Combo $gPlatformFspPkgTokenSpaceGuid_DebugInterfaceEnable, "CPU Run Control", &gPlatformFspPkgTokenSpaceGuid_DebugInterfaceEnable, + Help "Enable, Disable or Do not configure CPU Run Control; 0: Disable; 1: Enable ; 2: No Change" + Combo $gPlatformFspPkgTokenSpaceGuid_DebugInterfaceLockEnable, "CPU Run Control Lock", &EN_DIS, + Help "Lock or Unlock CPU Run Control; 0: Disable; 1: Enable." + Combo $gPlatformFspPkgTokenSpaceGuid_AtomL2VoltageMode, "Atom L2 voltage mode", &EN_DIS, + Help "Atom L2 voltage mode; 0: Adaptive; 1: Override." + EditNum $gPlatformFspPkgTokenSpaceGuid_AtomL2VoltageOverride, "Atom L2 Voltage Override", HEX, + Help "The atom L2 voltage override which is applied to the entire range of atom L2 frequencies. Valid Range 0 to 2000" + "Valid range: 0x00 ~ 0x7D0" + EditNum $gPlatformFspPkgTokenSpaceGuid_AtomL2VoltageAdaptive, "Atom L2 Turbo voltage Adaptive", HEX, + Help "Extra Turbo voltage applied to the atom L2 when the atom L2 is operating in turbo mode. Valid Range 0 to 2000" + "Valid range: 0x00 ~ 0x7D0" + EditNum $gPlatformFspPkgTokenSpaceGuid_AtomL2VoltageOffset, "Atom L2 Turbo voltage Offset", HEX, + Help "The voltage offset applied to the atom while operating in turbo mode.Valid Range 0 to 1000" + "Valid range: 0x00 ~ 0x3E8" + EditNum $gPlatformFspPkgTokenSpaceGuid_PerAtomClusterVoltageOffset, "Per-Atom-Cluster VF Offset", HEX, + Help "Array used to specifies the selected Atom Core Cluster Offset Voltage. This voltage is specified in millivolts." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PerAtomClusterVoltageOffsetPrefix, "Per-Atom-Cluster VF Offset Prefix", HEX, + Help "Sets the PerAtomClusterVoltageOffset value as positive or negative for the selected Core; 0: Positive ; 1: Negative." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_IaCepEnable, "Enable IA CEP", &EN_DIS, + Help "Control for enabling/disabling IA CEP (Current Excursion Protection)). 1: Enable; 0: Disable" + Combo $gPlatformFspPkgTokenSpaceGuid_GtCepEnable, "Enable GT CEP", &EN_DIS, + Help "Control for enabling/disabling GT CEP (Current Excursion Protection)). 1: Enable; 0: Disable" + Combo $gPlatformFspPkgTokenSpaceGuid_DlvrBypassModeEnable, "Enable CPU DLVR bypass mode support", &EN_DIS, + Help "Control for enabling/disabling CPU DLVR bypass mode). 0: Disable; 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_ActiveSmallCoreCount, "Number of active small cores", &gPlatformFspPkgTokenSpaceGuid_ActiveSmallCoreCount, + Help "Number of active small cores(Depends on Number of small cores). Default 0xFF means to active all system supported small cores. 0xFF: Active all small cores; 0: Disable all small cores; 1: 1; 2: 2; 3: 3;" + Combo $gPlatformFspPkgTokenSpaceGuid_CoreVfPointOffsetMode, "Core VF Point Offset Mode", &gPlatformFspPkgTokenSpaceGuid_CoreVfPointOffsetMode, + Help "Selects Core Voltage & Frequency Offset mode between Legacy and Selection modes. In Legacy Mode, setting a global offset for the entire VF curve. In Selection Mode, setting a selected VF point; 0: Legacy; 1: Selection." + EditNum $gPlatformFspPkgTokenSpaceGuid_CoreVfPointOffset, "Core VF Point Offset", HEX, + Help "Array used to specifies the Core Voltage Offset applied to the each selected VF Point. This voltage is specified in millivolts." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_CoreVfPointOffsetPrefix, "Core VF Point Offset Prefix", &gPlatformFspPkgTokenSpaceGuid_CoreVfPointOffsetPrefix, + Help "Sets the CoreVfPointOffset value as positive or negative for corresponding core VF Point; 0: Positive ; 1: Negative." + EditNum $gPlatformFspPkgTokenSpaceGuid_CoreVfPointRatio, "Core VF Point Ratio", HEX, + Help "Array for the each selected Core VF Point to display the ration." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CoreVfPointCount, "Core VF Point Count", HEX, + Help "Number of supported Core Voltage & Frequency Point Offset" + "Valid range: 0x0 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_CoreVfConfigScope, "Core VF Configuration Scope", &gPlatformFspPkgTokenSpaceGuid_CoreVfConfigScope, + Help "Alows both all-core VF curve or per-core VF curve configuration; 0: All-core; 1: Per-core." + EditNum $gPlatformFspPkgTokenSpaceGuid_PerCoreVoltageOffset, "Per-core VF Offset", HEX, + Help "Array used to specifies the selected Core Offset Voltage. This voltage is specified in millivolts." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PerCoreVoltageOffsetPrefix, "Per-core VF Offset Prefix", HEX, + Help "Sets the PerCoreVoltageOffset value as positive or negative for the selected Core; 0: Positive ; 1: Negative." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PerCoreRatioOverride, "Per Core Max Ratio override", &EN_DIS, + Help "Enable or disable Per Core PState OC supported by writing OCMB 0x1D to program new favored core ratio to each Core. 0: Disable, 1: enable" + EditNum $gPlatformFspPkgTokenSpaceGuid_PerCoreRatio, "Per Core Current Max Ratio", HEX, + Help "Array for the Per Core Max Ratio" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_AtomClusterRatio, "Atom Cluster Max Ratio", HEX, + Help "Array for Atom Cluster Max Ratio, 4 ATOM cores are in the same Cluster and their max core ratio will be aligned." + "Valid range: 0x00 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_CoreRatioExtensionMode, "Core Ratio Extension Mode", &EN_DIS, + Help "Enable or disable Core Ratio above 85 Extension Mode by writing BIOS MB 0x37 to enable FULL_RANGE_MULTIPLIER_UNLOCK_EN. 0: Disable, 1: enable" + EditNum $gPlatformFspPkgTokenSpaceGuid_PvdRatioThreshold, "Pvd Ratio Threshold", HEX, + Help "Select PVD Ratio Threshold Value from Range 1 to 40. 0 - Auto/Default." + "Valid range: 0x0 ~ 0x28" + Combo $gPlatformFspPkgTokenSpaceGuid_UnlimitedIccMax, "Support Unlimited ICCMAX", &EN_DIS, + Help "DEPRECATED" + Combo $gPlatformFspPkgTokenSpaceGuid_CrashLogGprs, "Enable CPU CrashLog GPRs dump", &gPlatformFspPkgTokenSpaceGuid_CrashLogGprs, + Help "Enable or Disable CPU CrashLog GPRs dump; 0: Disable; 1: Enable; 2: Only disable Smm GPRs dump" + Combo $gPlatformFspPkgTokenSpaceGuid_RingVfPointOffsetMode, "Ring VF Point Offset Mode", &gPlatformFspPkgTokenSpaceGuid_RingVfPointOffsetMode, + Help "Selects Ring Voltage & Frequency Offset mode between Legacy and Selection modes. In Legacy Mode, setting a global offset for the entire VF curve. In Selection Mode, setting a selected VF point; 0: Legacy; 1: Selection." + EditNum $gPlatformFspPkgTokenSpaceGuid_RingVfPointOffset, "Ring VF Point Offset", HEX, + Help "Array used to specifies the Ring Voltage Offset applied to the each selected VF Point. This voltage is specified in millivolts." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_RingVfPointOffsetPrefix, "Ring VF Point Offset Prefix", HEX, + Help "Sets the RingVfPointOffset value as positive or negative for corresponding core VF Point; 0: Positive ; 1: Negative." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_RingVfPointRatio, "Ring VF Point Ratio", HEX, + Help "Array for the each selected Ring VF Point to display the ration." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_RingVfPointCount, "Ring VF Point Count", HEX, + Help "Number of supported Ring Voltage & Frequency Point Offset" + "Valid range: 0x0 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_BclkSource, "BCLK Frequency Source", &gPlatformFspPkgTokenSpaceGuid_BclkSource, + Help "Clock source of BCLK OC frequency, 1:CPU BCLK, 2:PCH BCLK, 3:External CLK" + EditNum $gPlatformFspPkgTokenSpaceGuid_GpioOverride, "GPIO Override", HEX, + Help "Gpio Override Level - FSP will not configure any GPIOs and rely on GPIO setings before moved to FSP. Available configurations 0: Disable; 1: Level 1 - Skips GPIO configuration in PEI/FSPM/FSPT phase;2: Level 2 - Reserved for future use" + "Valid range: 0x00 ~ 0x7" + EditNum $gPlatformFspPkgTokenSpaceGuid_CpuBclkOcFrequency, "CPU BCLK OC Frequency", HEX, + Help "CPU BCLK OC Frequency in 10KHz units increasing. Value 9800 (10KHz) = 98MHz 0 - Auto. Range is 8000-50000 (10KHz)." + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DisablePerCoreMask, "Bitmask of disable cores", HEX, + Help "Core mask is a bitwise indication of which core should be disabled. 0x00=Default; Bit 0 - core 0, bit 7 - core 7." + "Valid range: 0x0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DisablePerAtomMask, "Bitmask of disable atoms", HEX, + Help "DEPRECATED" + "Valid range: 0x0 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_SaPllFreqOverride, "Sa PLL Frequency", &gPlatformFspPkgTokenSpaceGuid_SaPllFreqOverride, + Help "Configure Sa PLL Frequency. 0: 3200MHz , 1: 1600MHz" +EndPage + +Page "CPU (Post-Mem)" + EditNum $gPlatformFspPkgTokenSpaceGuid_MicrocodeRegionBase, "MicrocodeRegionBase", HEX, + Help "Memory Base of Microcode Updates" + "Valid range: 0x0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_MicrocodeRegionSize, "MicrocodeRegionSize", HEX, + Help "Size of Microcode Updates" + "Valid range: 0x0 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_TurboMode, "Turbo Mode", &EN_DIS, + Help "Enable/Disable Turbo mode. 0: disable, 1: enable" + Combo $gPlatformFspPkgTokenSpaceGuid_AesEnable, "Advanced Encryption Standard (AES) feature", &EN_DIS, + Help "Enable or Disable Advanced Encryption Standard (AES) feature; 0: Disable; 1: Enable" + EditNum $gPlatformFspPkgTokenSpaceGuid_Psi3Enable, "Power State 3 enable/disable", HEX, + Help "PCODE MMIO Mailbox: Power State 3 enable/disable; 0: Disable; 1: Enable. For all VR Indexes" + "Valid range: 0x00 ~ 0xFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_Psi4Enable, "Power State 4 enable/disable", HEX, + Help "PCODE MMIO Mailbox: Power State 4 enable/disable; 0: Disable; 1: Enable.For all VR Indexes" + "Valid range: 0x00 ~ 0xFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ImonSlope, "Imon slope correction", HEX, + Help "PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values. Range is 0-200. 125 = 1.25. 0: Auto.For all VR Indexes" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ImonOffset, "Imon offset correction", HEX, + Help "PCODE MMIO Mailbox: Imon offset correction. Value is a 2's complement signed integer. Units 1/1000, Range 0-63999. For an offset = 12.580, use 12580. 0: Auto" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_VrConfigEnable, "Enable/Disable BIOS configuration of VR", HEX, + Help "Enable/Disable BIOS configuration of VR; 0: Disable; 1: Enable.For all VR Indexes" + "Valid range: 0x00 ~ 0xFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_TdcEnable, "Thermal Design Current enable/disable", HEX, + Help "PCODE MMIO Mailbox: Thermal Design Current enable/disable; 0: Disable; 1: Enable.For all VR Indexes" + "Valid range: 0x00 ~ 0xFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_TdcTimeWindow, "Thermal Design Current time window", HEX, + Help "PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds. Range 1ms to 448s" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_TdcLock, "Thermal Design Current Lock", HEX, + Help "PCODE MMIO Mailbox: Thermal Design Current Lock; 0: Disable; 1: Enable.For all VR Indexes" + "Valid range: 0x00 ~ 0xFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PsysSlope, "Platform Psys slope correction", HEX, + Help "PCODE MMIO Mailbox: Platform Psys slope correction. 0 - Auto Specified in 1/100 increment values. Range is 0-200. 125 = 1.25" + "Valid range: 0x00 ~ 0xC8" + EditNum $gPlatformFspPkgTokenSpaceGuid_PsysOffset, "Platform Psys offset correction", HEX, + Help "PCODE MMIO Mailbox: Platform Psys offset correction. 0 - Auto Units 1/1000, Range 0-63999. For an offset of 25.348, enter 25348." + "Valid range: 0x0000 ~ 0xFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_AcousticNoiseMitigation, "Acoustic Noise Mitigation feature", &EN_DIS, + Help "Enable or Disable Acoustic Noise Mitigation feature. 0: Disabled; 1: Enabled" + Combo $gPlatformFspPkgTokenSpaceGuid_FastPkgCRampDisable, "Disable Fast Slew Rate for Deep Package C States for VR domains", &EN_DIS, + Help "Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation feature enabled. 0: False; 1: True" + Combo $gPlatformFspPkgTokenSpaceGuid_SlowSlewRate, "Slew Rate configuration for Deep Package C States for VR domains", &gPlatformFspPkgTokenSpaceGuid_SlowSlewRate, + Help "Slew Rate configuration for Deep Package C States for VR domains based on Acoustic Noise Mitigation feature enabled. ADL supports VCCIA FAST/2/4/8/16, VCCGT FAST/2/4/8 and VCCSA FAST/2 0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16" + EditNum $gPlatformFspPkgTokenSpaceGuid_TdcCurrentLimit, "Thermal Design Current current limit", HEX, + Help "PCODE MMIO Mailbox: Thermal Design Current current limit. Specified in 1/8A units. Range is 0-4095. 1000 = 125A. 0: Auto. For all VR Indexes" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_AcLoadline, "AcLoadline", HEX, + Help "PCODE MMIO Mailbox: AcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is 0-6249. Intel Recommended Defaults vary by domain and SKU." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DcLoadline, "DcLoadline", HEX, + Help "PCODE MMIO Mailbox: DcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is 0-6249.Intel Recommended Defaults vary by domain and SKU." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_Psi1Threshold, "Power State 1 Threshold current", HEX, + Help "PCODE MMIO Mailbox: Power State 1 current cuttof in 1/4 Amp increments. Range is 0-128A." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_Psi2Threshold, "Power State 2 Threshold current", HEX, + Help "PCODE MMIO Mailbox: Power State 2 current cuttof in 1/4 Amp increments. Range is 0-128A." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_Psi3Threshold, "Power State 3 Threshold current", HEX, + Help "PCODE MMIO Mailbox: Power State 3 current cuttof in 1/4 Amp increments. Range is 0-128A." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IccMax, "Icc Max limit", HEX, + Help "PCODE MMIO Mailbox: VR Icc Max limit. 0-512A in 1/4 A units. 400 = 100A" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_TxtEnable, "Enable or Disable TXT", &EN_DIS, + Help "Enable or Disable TXT; 0: Disable; 1: Enable." + Combo $gPlatformFspPkgTokenSpaceGuid_SkipMpInit, "Skip Multi-Processor Initialization", &EN_DIS, + Help "When this is skipped, boot loader must initialize processors before SilicionInit API. 0: Initialize; 1: Skip" + EditNum $gPlatformFspPkgTokenSpaceGuid_FivrRfiFrequency, "FIVR RFI Frequency", HEX, + Help "PCODE MMIO Mailbox: Set the desired RFI frequency, in increments of 100KHz. 0: Auto. Range varies based on XTAL clock: 0-1918 (Up to 191.8HMz) for 24MHz clock; 0-1535 (Up to 153.5MHz) for 19MHz clock." + "Valid range: 0x0 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_FivrSpreadSpectrum, "FIVR RFI Spread Spectrum", HEX, + Help "Set the Spread Spectrum Range. 1.5%; Range: 0.5%, 1%, 1.5%, 2%, 3%, 4%, 5%, 6%. Each Range is translated to an encoded value for FIVR register. 0.5% = 0, 1% = 3, 1.5% = 8, 2% = 18, 3% = 28, 4% = 34, 5% = 39, 6% = 44." + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CpuBistData, "CpuBistData", HEX, + Help "Pointer CPU BIST Data" + "Valid range: 0x0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CpuMpPpi, "CpuMpPpi", HEX, + Help "Optional pointer to the boot loader's implementation of EFI_PEI_MP_SERVICES_PPI. If not NULL, FSP will use the boot loader's implementation of multiprocessing. See section 5.1.4 of the FSP Integration Guide for more details." + "Valid range: 0x0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PreWake, "Pre Wake Randomization time", HEX, + Help "PCODE MMIO Mailbox: Acoustic Noise Mitigation Range.Defines the maximum pre-wake randomization time in micro ticks.This can be programmed only if AcousticNoiseMitigation is enabled. Range 0-255 0." + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_RampUp, "Ramp Up Randomization time", HEX, + Help "PCODE MMIO Mailbox: Acoustic Noise Mitigation Range.Defines the maximum Ramp Up randomization time in micro ticks.This can be programmed only if AcousticNoiseMitigation is enabled.Range 0-255 0." + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_RampDown, "Ramp Down Randomization time", HEX, + Help "PCODE MMIO Mailbox: Acoustic Noise Mitigation Range.Defines the maximum Ramp Down randomization time in micro ticks.This can be programmed only if AcousticNoiseMitigation is enabled.Range 0-255 0." + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_VrVoltageLimit, "VR Voltage Limit", HEX, + Help "PCODE MMIO Mailbox: Voltage Limit. Range is 0 - 7999mV" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_VccInAuxImonIccImax, "VccIn Aux Imon IccMax", HEX, + Help "PCODE MMIO Mailbox: VccIn Aux Imon IccMax. 0 - Auto Values are in 1/4 Amp increments. Range is 0-512." + "Valid range: 0x0000 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_EnableVsysCritical, "Vsys Critical", HEX, + Help "PCODE MMIO Mailbox: Vsys Critical. 0: Disable; 1: Enable Range is 0-255." + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_VsysFullScale, "Vsys Full Scale", HEX, + Help "Vsys Full Scale, Range is 0-255" + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_VsysCriticalThreshold, "Vsys Critical Threshold", HEX, + Help "Vsys Critical Threshold, Range is 0-255 " + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_VsysAssertionDeglitchMantissa, "Assertion Deglitch Mantissa", HEX, + Help "Assertion Deglitch Mantissa, Range is 0-255" + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_VsysAssertionDeglitchExponent, "Assertion Deglitch Exponent", HEX, + Help "Assertion Deglitch Exponent, Range is 0-255" + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_VsysDeassertionDeglitchMantissa, "De assertion Deglitch Mantissa", HEX, + Help "De assertion Deglitch Mantissa, Range is 0-255" + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_VsysDeassertionDeglitchExponent, "De assertion Deglitch Exponent", HEX, + Help "De assertion Deglitch Exponent, Range is 0-255" + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_VccInAuxImonSlope, "VccIn Aux Imon slope correction", HEX, + Help "PCODE MMIO Mailbox: VccIn Aux Imon slope correction. 0 - Auto Specified in 1/100 increment values. Range is 0-200. 125 = 1.25" + "Valid range: 0x00 ~ 0xC8" + EditNum $gPlatformFspPkgTokenSpaceGuid_VccInAuxImonOffset, "VccIn Aux Imon offset correction", HEX, + Help "PCODE MMIO Mailbox: VccIn Aux Imon offset correction. 0 - Auto Units 1/1000, Range 0-63999. For an offset of 25.348, enter 25348." + "Valid range: 0x0000 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_FivrSpectrumEnable, "FIVR RFI Spread Spectrum Enable or disable", HEX, + Help "Enable or Disable FIVR RFI Spread Spectrum. 0: Disable ; 1: Enable " + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IccLimit, "VR Fast Vmode ICC Limit support", HEX, + Help "PCODE MMIO Mailbox: VR Fast Vmode ICC Limit support. 0-255A in 1/4 A units. 400 = 100A" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PpinSupport, "PpinSupport to view Protected Processor Inventory Number", &gPlatformFspPkgTokenSpaceGuid_PpinSupport, + Help "Enable or Disable or Auto (Based on End of Manufacturing flag. Disabled if this flag is set) for PPIN Support" + Combo $gPlatformFspPkgTokenSpaceGuid_EnableMinVoltageOverride, "Enable or Disable Minimum Voltage Override", &EN_DIS, + Help "Enable or disable Minimum Voltage overrides ; 0: Disable; 1: Enable." + EditNum $gPlatformFspPkgTokenSpaceGuid_MinVoltageRuntime, "Min Voltage for Runtime ", HEX, + Help "PCODE MMIO Mailbox: Minimum voltage for runtime. Valid if EnableMinVoltageOverride = 1. Range 0 to 1999mV. 0: 0mV " + "Valid range: 0x00 ~ 0x7CF" + EditNum $gPlatformFspPkgTokenSpaceGuid_MinVoltageC8, "Min Voltage for C8 ", HEX, + Help "PCODE MMIO Mailbox: Minimum voltage for C8. Valid if EnableMinVoltageOverride = 1. Range 0 to 1999mV. 0: 0mV " + "Valid range: 0x00 ~ 0x7CF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SmbiosType4MaxSpeedOverride, "Smbios Type4 Max Speed Override", HEX, + Help "Provide the option for platform to override the MaxSpeed field of Smbios Type 4. If this value is not zero, it dominates the field." + "Valid range: 0x0000 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_Irms, "Current root mean square", HEX, + Help "PCODE MMIO Mailbox: Current root mean square; 0: Disable; 1: Enable.For all VR Indexes" + "Valid range: 0x00 ~ 0xFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_AvxDisable, "AvxDisable", &gPlatformFspPkgTokenSpaceGuid_AvxDisable, + Help "Enable or Disable AVX Support. This only applicable when all small core is disabled." + Combo $gPlatformFspPkgTokenSpaceGuid_Avx3Disable, "Avx3Disable", &gPlatformFspPkgTokenSpaceGuid_Avx3Disable, + Help "DEPRECATED" + Combo $gPlatformFspPkgTokenSpaceGuid_X2ApicSupport, "X2ApicSupport", &EN_DIS, + Help "Enable or Disable X2APIC Support" + EditNum $gPlatformFspPkgTokenSpaceGuid_VrPowerDeliveryDesign, "CPU VR Power Delivery Design", HEX, + Help "Used to communicate the power delivery design capability of the board. This value is an enum of the available power delivery segments that are defined in the Platform Design Guide." + "Valid range: 0x00 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_EnableFastVmode, "Enable/Disable VR FastVmode. The VR will initiate reactive protection if Fast Vmode is enabled.", &gPlatformFspPkgTokenSpaceGuid_EnableFastVmode, + Help "Enable/Disable VR FastVmode; 0: Disable; 1: Enable.For all VR by domain" + Combo $gPlatformFspPkgTokenSpaceGuid_ReservedCpuPostMemProduction, "ReservedCpuPostMemProduction", &EN_DIS, + Help "Reserved for CPU Post-Mem Production" + EditNum $gPlatformFspPkgTokenSpaceGuid_BgpdtHash, "BgpdtHash[4]", HEX, + Help "BgpdtHash values" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_BiosGuardAttr, "BiosGuardAttr", HEX, + Help "BiosGuardAttr default values" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_BiosGuardModulePtr, "BiosGuardModulePtr", HEX, + Help "BiosGuardModulePtr default values" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_EnableRsr, "RSR feature", &EN_DIS, + Help "Enable or Disable RSR feature; 0: Disable; 1: Enable " + Combo $gPlatformFspPkgTokenSpaceGuid_ReservedCpuPostMem1, "ReservedCpuPostMem1", &EN_DIS, + Help "Reserved for CPU Post-Mem 1" + Combo $gPlatformFspPkgTokenSpaceGuid_Hwp, "Enable or Disable HWP", &EN_DIS, + Help "Enable or Disable HWP(Hardware P states) Support. 0: Disable; 1: Enable; 2-3:Reserved" + Combo $gPlatformFspPkgTokenSpaceGuid_HdcControl, "Hardware Duty Cycle Control", &EN_DIS, + Help "Hardware Duty Cycle Control configuration. 0: Disabled; 1: Enabled 2-3:Reserved" + EditNum $gPlatformFspPkgTokenSpaceGuid_PowerLimit1Time, "Package Long duration turbo mode time", HEX, + Help "Package Long duration turbo mode time window in seconds. Valid values(Unit in seconds) 0 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128" + "Valid range: 0x00 ~ 0x80" + Combo $gPlatformFspPkgTokenSpaceGuid_PowerLimit2, "Short Duration Turbo Mode", &EN_DIS, + Help "Enable or Disable short duration Turbo Mode. 0 : Disable; 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_TurboPowerLimitLock, "Turbo settings Lock", &EN_DIS, + Help "Lock all Turbo settings Enable/Disable; 0: Disable , 1: Enable" + EditNum $gPlatformFspPkgTokenSpaceGuid_PowerLimit3Time, "Package PL3 time window", HEX, + Help "Package PL3 time window range for this policy from 0 to 64ms" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PowerLimit3DutyCycle, "Package PL3 Duty Cycle", HEX, + Help "Package PL3 Duty Cycle; Valid Range is 0 to 100" + "Valid range: 0x00 ~ 0x64" + Combo $gPlatformFspPkgTokenSpaceGuid_PowerLimit3Lock, "Package PL3 Lock", &EN_DIS, + Help "Package PL3 Lock Enable/Disable; 0: Disable ; 1:Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_PowerLimit4Lock, "Package PL4 Lock", &EN_DIS, + Help "Package PL4 Lock Enable/Disable; 0: Disable ; 1:Enable" + EditNum $gPlatformFspPkgTokenSpaceGuid_TccActivationOffset, "TCC Activation Offset", HEX, + Help "TCC Activation Offset. Offset from factory set TCC activation temperature at which the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation Temperature, in volts.For SKL Y SKU, the recommended default for this policy is 10, For all other SKUs the recommended default are 0" + "Valid range: 0x00 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_TccOffsetClamp, "Tcc Offset Clamp Enable/Disable", &EN_DIS, + Help "Tcc Offset Clamp for Runtime Average Temperature Limit (RATL) allows CPU to throttle below P1.For SKL Y SKU, the recommended default for this policy is 1: Enabled, For all other SKUs the recommended default are 0: Disabled." + Combo $gPlatformFspPkgTokenSpaceGuid_TccOffsetLock, "Tcc Offset Lock", &EN_DIS, + Help "Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature target; 0: Disabled; 1: Enabled." + EditNum $gPlatformFspPkgTokenSpaceGuid_NumberOfEntries, "Custom Ratio State Entries", HEX, + Help "The number of custom ratio state entries, ranges from 0 to 40 for a valid custom ratio table.Sets the number of custom P-states. At least 2 states must be present" + "Valid range: 0x00 ~ 0x28" + EditNum $gPlatformFspPkgTokenSpaceGuid_Custom1PowerLimit1Time, "Custom Short term Power Limit time window", HEX, + Help "Short term Power Limit time window value for custom CTDP level 1. Valid Range 0 to 128" + "Valid range: 0x00 ~ 0x80" + EditNum $gPlatformFspPkgTokenSpaceGuid_Custom1TurboActivationRatio, "Custom Turbo Activation Ratio", HEX, + Help "Turbo Activation Ratio for custom cTDP level 1. Valid Range 0 to 255" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_Custom1ConfigTdpControl, "Custom Config Tdp Control", HEX, + Help "Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2" + "Valid range: 0x00 ~ 0x2" + EditNum $gPlatformFspPkgTokenSpaceGuid_Custom2PowerLimit1Time, "Custom Short term Power Limit time window", HEX, + Help "Short term Power Limit time window value for custom CTDP level 2. Valid Range 0 to 128" + "Valid range: 0x00 ~ 0x80" + EditNum $gPlatformFspPkgTokenSpaceGuid_Custom2TurboActivationRatio, "Custom Turbo Activation Ratio", HEX, + Help "Turbo Activation Ratio for custom cTDP level 2. Valid Range 0 to 255" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_Custom2ConfigTdpControl, "Custom Config Tdp Control", HEX, + Help "Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2" + "Valid range: 0x00 ~ 0x2" + EditNum $gPlatformFspPkgTokenSpaceGuid_Custom3PowerLimit1Time, "Custom Short term Power Limit time window", HEX, + Help "Short term Power Limit time window value for custom CTDP level 3. Valid Range 0 to 128" + "Valid range: 0x00 ~ 0x80" + EditNum $gPlatformFspPkgTokenSpaceGuid_Custom3TurboActivationRatio, "Custom Turbo Activation Ratio", HEX, + Help "Turbo Activation Ratio for custom cTDP level 3. Valid Range 0 to 255" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_Custom3ConfigTdpControl, "Custom Config Tdp Control", HEX, + Help "Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2" + "Valid range: 0x00 ~ 0x2" + Combo $gPlatformFspPkgTokenSpaceGuid_ConfigTdpLock, "ConfigTdp mode settings Lock", &EN_DIS, + Help "Lock the ConfigTdp mode settings from runtime changes; 0: Disable; 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_ConfigTdpBios, "Load Configurable TDP SSDT", &EN_DIS, + Help "Configure whether to load Configurable TDP SSDT; 0: Disable; 1: Enable." + Combo $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit1, "PL1 Enable value", &EN_DIS, + Help "PL1 Enable value to limit average platform power. 0: Disable; 1: Enable." + EditNum $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit1Time, "PL1 timewindow", HEX, + Help "PL1 timewindow in seconds.Valid values(Unit in seconds) 0 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128" + "Valid range: 0x00 ~ 0x80" + Combo $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit2, "PL2 Enable Value", &EN_DIS, + Help "PL2 Enable activates the PL2 value to limit average platform power.0: Disable; 1: Enable." + Combo $gPlatformFspPkgTokenSpaceGuid_MlcStreamerPrefetcher, "Enable or Disable MLC Streamer Prefetcher", &EN_DIS, + Help "Enable or Disable MLC Streamer Prefetcher; 0: Disable; 1: Enable." + Combo $gPlatformFspPkgTokenSpaceGuid_MlcSpatialPrefetcher, "Enable or Disable MLC Spatial Prefetcher", &EN_DIS, + Help "Enable or Disable MLC Spatial Prefetcher; 0: Disable; 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_MonitorMwaitEnable, "Enable or Disable Monitor /MWAIT instructions", &EN_DIS, + Help "Enable or Disable Monitor /MWAIT instructions; 0: Disable; 1: Enable." + Combo $gPlatformFspPkgTokenSpaceGuid_MachineCheckEnable, "Enable or Disable initialization of machine check registers", &EN_DIS, + Help "Enable or Disable initialization of machine check registers; 0: Disable; 1: Enable." + Combo $gPlatformFspPkgTokenSpaceGuid_ApIdleManner, "AP Idle Manner of waiting for SIPI", &gPlatformFspPkgTokenSpaceGuid_ApIdleManner, + Help "AP Idle Manner of waiting for SIPI; 1: HALT loop; 2: MWAIT loop; 3: RUN loop." + Combo $gPlatformFspPkgTokenSpaceGuid_ProcessorTraceOutputScheme, "Control on Processor Trace output scheme", &gPlatformFspPkgTokenSpaceGuid_ProcessorTraceOutputScheme, + Help "Control on Processor Trace output scheme; 0: Single Range Output; 1: ToPA Output." + Combo $gPlatformFspPkgTokenSpaceGuid_ProcessorTraceEnable, "Enable or Disable Processor Trace feature", &EN_DIS, + Help "Enable or Disable Processor Trace feature; 0: Disable; 1: Enable." + Combo $gPlatformFspPkgTokenSpaceGuid_Eist, "Enable or Disable Intel SpeedStep Technology", &EN_DIS, + Help "Enable or Disable Intel SpeedStep Technology. 0: Disable; 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_EnergyEfficientPState, "Enable or Disable Energy Efficient P-state", &EN_DIS, + Help "Enable or Disable Energy Efficient P-state will be applied in Turbo mode. Disable; 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_EnergyEfficientTurbo, "Enable or Disable Energy Efficient Turbo", &EN_DIS, + Help "Enable or Disable Energy Efficient Turbo, will be applied in Turbo mode. 0: Disable; 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_TStates, "Enable or Disable T states", &EN_DIS, + Help "Enable or Disable T states; 0: Disable; 1: Enable." + Combo $gPlatformFspPkgTokenSpaceGuid_BiProcHot, "Enable or Disable Bi-Directional PROCHOT#", &EN_DIS, + Help "Enable or Disable Bi-Directional PROCHOT#; 0: Disable; 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_DisableProcHotOut, "Enable or Disable PROCHOT# signal being driven externally", &EN_DIS, + Help "Enable or Disable PROCHOT# signal being driven externally; 0: Disable; 1: Enable." + Combo $gPlatformFspPkgTokenSpaceGuid_ProcHotResponse, "Enable or Disable PROCHOT# Response", &EN_DIS, + Help "Enable or Disable PROCHOT# Response; 0: Disable; 1: Enable." + Combo $gPlatformFspPkgTokenSpaceGuid_DisableVrThermalAlert, "Enable or Disable VR Thermal Alert", &EN_DIS, + Help "Enable or Disable VR Thermal Alert; 0: Disable; 1: Enable." + Combo $gPlatformFspPkgTokenSpaceGuid_EnableAllThermalFunctions, "Enable or Disable Thermal Reporting", &EN_DIS, + Help "Enable or Disable Thermal Reporting through ACPI tables; 0: Disable; 1: Enable." + Combo $gPlatformFspPkgTokenSpaceGuid_ThermalMonitor, "Enable or Disable Thermal Monitor", &EN_DIS, + Help "Enable or Disable Thermal Monitor; 0: Disable; 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_Cx, "Enable or Disable CPU power states (C-states)", &EN_DIS, + Help "Enable or Disable CPU power states (C-states). 0: Disable; 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_PmgCstCfgCtrlLock, "Configure C-State Configuration Lock", &EN_DIS, + Help "Configure C-State Configuration Lock; 0: Disable; 1: Enable." + Combo $gPlatformFspPkgTokenSpaceGuid_C1e, "Enable or Disable Enhanced C-states", &EN_DIS, + Help "Enable or Disable Enhanced C-states. 0: Disable; 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_PkgCStateDemotion, "Enable or Disable Package Cstate Demotion", &EN_DIS, + Help "Enable or Disable Package Cstate Demotion. 0: Disable; 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_PkgCStateUnDemotion, "Enable or Disable Package Cstate UnDemotion", &EN_DIS, + Help "Enable or Disable Package Cstate UnDemotion. 0: Disable; 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_CStatePreWake, "Enable or Disable CState-Pre wake", &EN_DIS, + Help "Enable or Disable CState-Pre wake. 0: Disable; 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_TimedMwait, "Enable or Disable TimedMwait Support.", &EN_DIS, + Help "Enable or Disable TimedMwait Support. 0: Disable; 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_CstCfgCtrIoMwaitRedirection, "Enable or Disable IO to MWAIT redirection", &EN_DIS, + Help "Enable or Disable IO to MWAIT redirection; 0: Disable; 1: Enable." + EditNum $gPlatformFspPkgTokenSpaceGuid_PkgCStateLimit, "Set the Max Pkg Cstate", HEX, + Help "Set the Max Pkg Cstate. Default set to Auto which limits the Max Pkg Cstate to deep C-state. Valid values 0 - C0/C1 , 1 - C2 , 2 - C3 , 3 - C6 , 4 - C7 , 5 - C7S , 6 - C8 , 7 - C9 , 8 - C10 , 254 - CPU Default , 255 - Auto" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl0TimeUnit, "TimeUnit for C-State Latency Control0", HEX, + Help "TimeUnit for C-State Latency Control0; Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns" + "Valid range: 0x00 ~ 0x5" + EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl1TimeUnit, "TimeUnit for C-State Latency Control1", HEX, + Help "TimeUnit for C-State Latency Control1;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns" + "Valid range: 0x00 ~ 0x5" + EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl2TimeUnit, "TimeUnit for C-State Latency Control2", HEX, + Help "TimeUnit for C-State Latency Control2;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns" + "Valid range: 0x00 ~ 0x5" + EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl3TimeUnit, "TimeUnit for C-State Latency Control3", HEX, + Help "TimeUnit for C-State Latency Control3;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns" + "Valid range: 0x00 ~ 0x5" + EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl4TimeUnit, "TimeUnit for C-State Latency Control4", HEX, + Help "Time - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns" + "Valid range: 0x00 ~ 0x5" + EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl5TimeUnit, "TimeUnit for C-State Latency Control5", HEX, + Help "TimeUnit for C-State Latency Control5;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns" + "Valid range: 0x00 ~ 0x5" + EditNum $gPlatformFspPkgTokenSpaceGuid_PpmIrmSetting, "Interrupt Redirection Mode Select", HEX, + Help "Interrupt Redirection Mode Select.0: Fixed priority; 1: Round robin;2: Hash vector;7: No change." + "Valid range: 0x00 ~ 0x7" + Combo $gPlatformFspPkgTokenSpaceGuid_ProcHotLock, "Lock prochot configuration", &EN_DIS, + Help "Lock prochot configuration Enable/Disable; 0: Disable; 1: Enable" + EditNum $gPlatformFspPkgTokenSpaceGuid_ConfigTdpLevel, "Configuration for boot TDP selection", HEX, + Help "Deprecated. Move to premem." + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_MaxRatio, "Max P-State Ratio", HEX, + Help "Max P-State Ratio, Valid Range 0 to 0x7F" + "Valid range: 0x00 ~ 0x7F" + EditNum $gPlatformFspPkgTokenSpaceGuid_StateRatio, "P-state ratios for custom P-state table", HEX, + Help "P-state ratios for custom P-state table. NumberOfEntries has valid range between 0 to 40. For no. of P-States supported(NumberOfEntries) , StateRatio[NumberOfEntries] are configurable. Valid Range of each entry is 0 to 0x7F" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_StateRatioMax16, "P-state ratios for max 16 version of custom P-state table", HEX, + Help "P-state ratios for max 16 version of custom P-state table. This table is used for OS versions limited to a max of 16 P-States. If the first entry of this table is 0, or if Number of Entries is 16 or less, then this table will be ignored, and up to the top 16 values of the StateRatio table will be used instead. Valid Range of each entry is 0 to 0x7F" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PsysPmax, "Platform Power Pmax", HEX, + Help "PCODE MMIO Mailbox: Platform Power Pmax. 0 - Auto Specified in 1/8 Watt increments. Range 0-1024 Watts. Value of 800 = 100W" + "Valid range: 0x00 ~ 0x400" + EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl1Irtl, "Interrupt Response Time Limit of C-State LatencyContol1", HEX, + Help "Interrupt Response Time Limit of C-State LatencyContol1.Range of value 0 to 0x3FF. 0 is Auto." + "Valid range: 0x00 ~ 0x3FF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl2Irtl, "Interrupt Response Time Limit of C-State LatencyContol2", HEX, + Help "Interrupt Response Time Limit of C-State LatencyContol2.Range of value 0 to 0x3FF. 0 is Auto." + "Valid range: 0x00 ~ 0x3FF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl3Irtl, "Interrupt Response Time Limit of C-State LatencyContol3", HEX, + Help "Interrupt Response Time Limit of C-State LatencyContol3.Range of value 0 to 0x3FF. 0 is Auto." + "Valid range: 0x00 ~ 0x3FF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl4Irtl, "Interrupt Response Time Limit of C-State LatencyContol4", HEX, + Help "Interrupt Response Time Limit of C-State LatencyContol4.Range of value 0 to 0x3FF. 0 is Auto." + "Valid range: 0x00 ~ 0x3FF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl5Irtl, "Interrupt Response Time Limit of C-State LatencyContol5", HEX, + Help "Interrupt Response Time Limit of C-State LatencyContol5.Range of value 0 to 0x3FF. 0 is Auto." + "Valid range: 0x00 ~ 0x3FF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PowerLimit1, "Package Long duration turbo mode power limit", HEX, + Help "Package Long duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. Valid Range 0 to 4095875 in Step size of 125" + "Valid range: 0x00 ~ 0x3E7F83" + EditNum $gPlatformFspPkgTokenSpaceGuid_PowerLimit2Power, "Package Short duration turbo mode power limit", HEX, + Help "Package Short duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125" + "Valid range: 0x00 ~ 0x3E7F83" + EditNum $gPlatformFspPkgTokenSpaceGuid_PowerLimit3, "Package PL3 power limit", HEX, + Help "Package PL3 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125" + "Valid range: 0x00 ~ 0x3E7F83" + EditNum $gPlatformFspPkgTokenSpaceGuid_PowerLimit4, "Package PL4 power limit", HEX, + Help "Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125" + "Valid range: 0x00 ~ 0x3E7F83" + EditNum $gPlatformFspPkgTokenSpaceGuid_TccOffsetTimeWindowForRatl, "Tcc Offset Time Window for RATL", HEX, + Help "Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_Custom1PowerLimit1, "Short term Power Limit value for custom cTDP level 1", HEX, + Help "Short term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125" + "Valid range: 0x00 ~ 0x3E7F83" + EditNum $gPlatformFspPkgTokenSpaceGuid_Custom1PowerLimit2, "Long term Power Limit value for custom cTDP level 1", HEX, + Help "Long term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125" + "Valid range: 0x00 ~ 0x3E7F83" + EditNum $gPlatformFspPkgTokenSpaceGuid_Custom2PowerLimit1, "Short term Power Limit value for custom cTDP level 2", HEX, + Help "Short term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125" + "Valid range: 0x00 ~ 0x3E7F83" + EditNum $gPlatformFspPkgTokenSpaceGuid_Custom2PowerLimit2, "Long term Power Limit value for custom cTDP level 2", HEX, + Help "Long term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125" + "Valid range: 0x00 ~ 0x3E7F83" + EditNum $gPlatformFspPkgTokenSpaceGuid_Custom3PowerLimit1, "Short term Power Limit value for custom cTDP level 3", HEX, + Help "Short term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125" + "Valid range: 0x00 ~ 0x3E7F83" + EditNum $gPlatformFspPkgTokenSpaceGuid_Custom3PowerLimit2, "Long term Power Limit value for custom cTDP level 3", HEX, + Help "Long term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125" + "Valid range: 0x00 ~ 0x3E7F83" + EditNum $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit1Power, "Platform PL1 power", HEX, + Help "Platform PL1 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125" + "Valid range: 0x00 ~ 0x3E7F83" + EditNum $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit2Power, "Platform PL2 power", HEX, + Help "Platform PL2 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125" + "Valid range: 0x00 ~ 0x3E7F83" + Combo $gPlatformFspPkgTokenSpaceGuid_RaceToHalt, "Race To Halt", &EN_DIS, + Help "Enable/Disable Race To Halt feature. RTH will dynamically increase CPU frequency in order to enter pkg C-State faster to reduce overall power. (RTH is controlled through MSR 1FC bit 20)Disable; 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_ThreeStrikeCounterDisable, "Set Three Strike Counter Disable", &gPlatformFspPkgTokenSpaceGuid_ThreeStrikeCounterDisable, + Help "False (default): Three Strike counter will be incremented and True: Prevents Three Strike counter from incrementing; 0: False; 1: True." + Combo $gPlatformFspPkgTokenSpaceGuid_HwpInterruptControl, "Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT", &EN_DIS, + Help "Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT; 0: Disable; 1: Enable." + Combo $gPlatformFspPkgTokenSpaceGuid_ReservedCpuPostMem2, "ReservedCpuPostMem2", &EN_DIS, + Help "Reserved for CPU Post-Mem 2" + Combo $gPlatformFspPkgTokenSpaceGuid_EnableItbm, "Intel Turbo Boost Max Technology 3.0", &EN_DIS, + Help "Intel Turbo Boost Max Technology 3.0. 0: Disabled; 1: Enabled" + Combo $gPlatformFspPkgTokenSpaceGuid_C1StateAutoDemotion, "Enable or Disable C1 Cstate Demotion", &EN_DIS, + Help "Enable or Disable C1 Cstate Demotion. Disable; 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_C1StateUnDemotion, "Enable or Disable C1 Cstate UnDemotion", &EN_DIS, + Help "Enable or Disable C1 Cstate UnDemotion. Disable; 1: Enable" + EditNum $gPlatformFspPkgTokenSpaceGuid_MinRingRatioLimit, "Minimum Ring ratio limit override", HEX, + Help "Minimum Ring ratio limit override. 0: Hardware defaults. Range: 0 - Max turbo ratio limit" + "Valid range: 0x00 ~ 0x53" + EditNum $gPlatformFspPkgTokenSpaceGuid_MaxRingRatioLimit, "Maximum Ring ratio limit override", HEX, + Help "Maximum Ring ratio limit override. 0: Hardware defaults. Range: 0 - Max turbo ratio limit" + "Valid range: 0x00 ~ 0x53" + Combo $gPlatformFspPkgTokenSpaceGuid_EnablePerCorePState, "Enable or Disable Per Core P State OS control", &EN_DIS, + Help "Enable or Disable Per Core P State OS control. 0: Disable; 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_EnableHwpAutoPerCorePstate, "Enable or Disable HwP Autonomous Per Core P State OS control", &EN_DIS, + Help "Enable or Disable HwP Autonomous Per Core P State OS control. 0: Disable; 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_EnableHwpAutoEppGrouping, "Enable or Disable HwP Autonomous EPP Grouping", &EN_DIS, + Help "Enable or Disable HwP Autonomous EPP Grouping. 0: Disable; 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_EnableEpbPeciOverride, "Enable or Disable EPB override over PECI", &EN_DIS, + Help "Enable or Disable EPB override over PECI. 0: Disable; 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_EnableFastMsrHwpReq, "Enable or Disable Fast MSR for IA32_HWP_REQUEST", &EN_DIS, + Help "Enable or Disable Fast MSR for IA32_HWP_REQUEST. 0: Disable; 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_ApplyConfigTdp, "Enable Configurable TDP", &EN_DIS, + Help "Applies TDP initialization settings based on non-cTDP or cTDP.; 0: Applies to non-cTDP; 1: Applies to cTDP" + Combo $gPlatformFspPkgTokenSpaceGuid_HwpLock, "Misc Power Management MSR Lock", &EN_DIS, + Help "Lock Misc Power Management MSR. Enable/Disable; 0: Disable , 1: Enable " + Combo $gPlatformFspPkgTokenSpaceGuid_DualTauBoost, "Dual Tau Boost", &EN_DIS, + Help "Enable, Disable Dual Tau Boost feature. This is only applicable for Desktop; 0: Disable; 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_ReservedCpuPostMemTest, "ReservedCpuPostMemTest", &EN_DIS, + Help "Reserved for CPU Post-Mem Test" +EndPage + +Page "System Agent (Pre-Mem)" + Combo $gPlatformFspPkgTokenSpaceGuid_CpuCrashLogDevice, "Enable/Disable CrashLog Device 10", &EN_DIS, + Help "Enable(Default): Enable CPU CrashLog Device 10, Disable: Disable CPU CrashLog" + Combo $gPlatformFspPkgTokenSpaceGuid_X2ApicOptOut, "State of X2APIC_OPT_OUT bit in the DMAR table", &EN_DIS, + Help "0=Disable/Clear, 1=Enable/Set" + Combo $gPlatformFspPkgTokenSpaceGuid_DmaControlGuarantee, "State of DMA_CONTROL_GUARANTEE bit in the DMAR table", &EN_DIS, + Help "0=Disable/Clear, 1=Enable/Set" + EditNum $gPlatformFspPkgTokenSpaceGuid_VtdBaseAddress, "Base addresses for VT-d function MMIO access", HEX, + Help "Base addresses for VT-d MMIO access per VT-d engine" + "Valid range: 0 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_VtdDisable, "Disable VT-d", &EN_DIS, + Help "0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled)" + Combo $gPlatformFspPkgTokenSpaceGuid_VtdIgdEnable, "Vtd Programming for Igd", &EN_DIS, + Help "1=Enable/TRUE (Igd VT-d Bar programming enabled), 0=Disable/FLASE (Igd VT-d Bar programming disabled)" + Combo $gPlatformFspPkgTokenSpaceGuid_VtdIpuEnable, "Vtd Programming for Ipu", &EN_DIS, + Help "1=Enable/TRUE (Ipu VT-d Bar programming enabled), 0=Disable/FLASE (Ipu VT-d Bar programming disabled)" + Combo $gPlatformFspPkgTokenSpaceGuid_VtdIopEnable, "Vtd Programming for Iop", &EN_DIS, + Help "1=Enable/TRUE (Iop VT-d Bar programming enabled), 0=Disable/FLASE (Iop VT-d Bar programming disabled)" + Combo $gPlatformFspPkgTokenSpaceGuid_VtdItbtEnable, "Vtd Programming for ITbt", &EN_DIS, + Help "DEPRECATED" + Combo $gPlatformFspPkgTokenSpaceGuid_IgdDvmt50PreAlloc, "Internal Graphics Pre-allocated Memory", &gPlatformFspPkgTokenSpaceGuid_IgdDvmt50PreAlloc, + Help "Size of memory preallocated for internal graphics." + Combo $gPlatformFspPkgTokenSpaceGuid_InternalGfx, "Internal Graphics", &EN_DIS, + Help "Enable/disable internal graphics." + Combo $gPlatformFspPkgTokenSpaceGuid_ApertureSize, "Aperture Size", &gPlatformFspPkgTokenSpaceGuid_ApertureSize, + Help "Select the Aperture Size." + EditNum $gPlatformFspPkgTokenSpaceGuid_HgDelayAfterPwrEn, "HG dGPU Power Delay", HEX, + Help "HG dGPU delay interval after power enabling: 0=Minimal, 1000=Maximum, default is 300=300 microseconds" + "Valid range: 0x00 ~ 0x3E8" + EditNum $gPlatformFspPkgTokenSpaceGuid_HgDelayAfterHoldReset, "HG dGPU Reset Delay", HEX, + Help "HG dGPU delay interval for Reset complete: 0=Minimal, 1000=Maximum, default is 100=100 microseconds" + "Valid range: 0x00 ~ 0x3E8" + EditNum $gPlatformFspPkgTokenSpaceGuid_MmioSizeAdjustment, "MMIO size adjustment for AUTO mode", HEX, + Help "Positive number means increasing MMIO size, Negative value means decreasing MMIO size: 0 (Default)=no change to AUTO mode MMIO size" + "Valid range: 0 ~ 0xFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_InitPcieAspmAfterOprom, "PCIe ASPM programming will happen in relation to the Oprom", &gPlatformFspPkgTokenSpaceGuid_InitPcieAspmAfterOprom, + Help "Select when PCIe ASPM programming will happen in relation to the Oprom. Before(0x0)(Default): Do PCIe ASPM programming before Oprom, After(0x1): Do PCIe ASPM programming after Oprom, requires an SMI handler to save/restore ASPM settings during S3 resume" + Combo $gPlatformFspPkgTokenSpaceGuid_PrimaryDisplay, "Selection of the primary display device", &gPlatformFspPkgTokenSpaceGuid_PrimaryDisplay, + Help "0=iGFX, 1=PEG, 2=PCIe Graphics on PCH, 3(Default)=AUTO, 4=Hybrid Graphics" + Combo $gPlatformFspPkgTokenSpaceGuid_PsmiRegionSize, "Selection of PSMI Region size", &gPlatformFspPkgTokenSpaceGuid_PsmiRegionSize, + Help "0=32MB, 1=288MB, 2=544MB, 3=800MB, 4=1024MB Default is 0" + EditNum $gPlatformFspPkgTokenSpaceGuid_GmAdr, "Temporary MMIO address for GMADR", HEX, + Help "Obsolete field now and it has been extended to 64 bit address, used GmAdr64 " + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_GttMmAdr, "Temporary MMIO address for GTTMMADR", HEX, + Help "The reference code will use this as Temporary MMIO address space to access GTTMMADR Registers.Platform should provide conflict free Temporary MMIO Range: GttMmAdr to (GttMmAdr + 2MB MMIO + 6MB Reserved + GttSize). Default is (GmAdr - (2MB MMIO + 6MB Reserved + GttSize)) to (GmAdr - 0x1) (Where GttSize = 8MB)" + "Valid range: 0x00 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_GttSize, "Selection of iGFX GTT Memory size", &gPlatformFspPkgTokenSpaceGuid_GttSize, + Help "1=2MB, 2=4MB, 3=8MB, Default is 3" + EditNum $gPlatformFspPkgTokenSpaceGuid_CpuPcie0Rtd3Gpio, "Hybrid Graphics GPIO information for PEG 0", HEX, + Help "Hybrid Graphics GPIO information for PEG 0, for Reset, power and wake GPIOs" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_SaOcSupport, "Enable/Disable SA OcSupport", &EN_DIS, + Help "Enable: Enable SA OcSupport, Disable(Default): Disable SA OcSupport" + Combo $gPlatformFspPkgTokenSpaceGuid_GtVoltageMode, "GT slice Voltage Mode", &gPlatformFspPkgTokenSpaceGuid_GtVoltageMode, + Help "0(Default): Adaptive, 1: Override" + EditNum $gPlatformFspPkgTokenSpaceGuid_GtMaxOcRatio, "Maximum GTs turbo ratio override", HEX, + Help "0(Default)=Minimal/Auto, 60=Maximum" + "Valid range: 0x00 ~ 0x3C" + EditNum $gPlatformFspPkgTokenSpaceGuid_GtVoltageOffset, "The voltage offset applied to GT slice", HEX, + Help "0(Default)=Minimal, 1000=Maximum" + "Valid range: 0x00 ~ 0x3E8" + EditNum $gPlatformFspPkgTokenSpaceGuid_GtVoltageOverride, "The GT slice voltage override which is applied to the entire range of GT frequencies", HEX, + Help "0(Default)=Minimal, 2000=Maximum" + "Valid range: 0x00 ~ 0x7D0" + EditNum $gPlatformFspPkgTokenSpaceGuid_GtExtraTurboVoltage, "adaptive voltage applied during turbo frequencies", HEX, + Help "0(Default)=Minimal, 2000=Maximum" + "Valid range: 0x00 ~ 0x7D0" + EditNum $gPlatformFspPkgTokenSpaceGuid_SaVoltageOffset, "voltage offset applied to the SA", HEX, + Help "0(Default)=Minimal, 1000=Maximum" + "Valid range: 0x00 ~ 0x3E8" + EditNum $gPlatformFspPkgTokenSpaceGuid_RootPortIndex, "PCIe root port Function number for Hybrid Graphics dGPU", HEX, + Help "Root port Index number to indicate which PCIe root port has dGPU" + "Valid range: 0x00 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_SaIpuEnable, "Enable/Disable SA IPU", &EN_DIS, + Help "Enable(Default): Enable SA IPU, Disable: Disable SA IPU" + Combo $gPlatformFspPkgTokenSpaceGuid_IpuLaneUsed, "Lane Used of CSI port", &gPlatformFspPkgTokenSpaceGuid_IpuLaneUsed, + Help " Lane Used of each CSI port" + Combo $gPlatformFspPkgTokenSpaceGuid_CsiSpeed, "Lane Used of CSI port", &gPlatformFspPkgTokenSpaceGuid_CsiSpeed, + Help " Speed of each CSI port" + Combo $gPlatformFspPkgTokenSpaceGuid_ImguClkOutEn, "IMGU CLKOUT Configuration", &EN_DIS, + Help "The configuration of IMGU CLKOUT, 0: Disable;1: Enable." + EditNum $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpEnableMask, "Enable PCIE RP Mask", HEX, + Help "Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 for port1, bit1 for port2, and so on." + "Valid range: 0x00 ~ 0x00FFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpLinkDownGpios, "Assertion on Link Down GPIOs", &gPlatformFspPkgTokenSpaceGuid_CpuPcieRpLinkDownGpios, + Help "GPIO Assertion on Link Down. Disabled(0x0)(Default): Disable assertion on Link Down GPIOs, Enabled(0x1): Enable assertion on Link Down GPIOs" + Combo $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpClockReqMsgEnable, "Enable ClockReq Messaging ", &gPlatformFspPkgTokenSpaceGuid_CpuPcieRpClockReqMsgEnable, + Help "ClockReq Messaging. Disabled(0x0): Disable ClockReq Messaging, Enabled(0x1)(Default): Enable ClockReq Messaging" + EditNum $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpPcieSpeed, "PCIE RP Pcie Speed", HEX, + Help "Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3; 4: Gen4 (see: CPU_PCIE_SPEED)." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_GtPsmiSupport, "Selection of PSMI Support On/Off", &EN_DIS, + Help "0(Default) = FALSE, 1 = TRUE. When TRUE, it will allow the PSMI Support" + Combo $gPlatformFspPkgTokenSpaceGuid_DdiPortAConfig, "Program GPIOs for LFP on DDI port-A device", &gPlatformFspPkgTokenSpaceGuid_DdiPortAConfig, + Help "0=Disabled,1(Default)=eDP, 2=MIPI DSI" + Combo $gPlatformFspPkgTokenSpaceGuid_DdiPortBConfig, "Program GPIOs for LFP on DDI port-B device", &gPlatformFspPkgTokenSpaceGuid_DdiPortBConfig, + Help "0(Default)=Disabled,1=eDP, 2=MIPI DSI" + Combo $gPlatformFspPkgTokenSpaceGuid_DdiPortAHpd, "Enable or disable HPD of DDI port A", &EN_DIS, + Help "0(Default)=Disable, 1=Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_DdiPortBHpd, "Enable or disable HPD of DDI port B", &EN_DIS, + Help "0=Disable, 1(Default)=Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_DdiPortCHpd, "Enable or disable HPD of DDI port C", &EN_DIS, + Help "0(Default)=Disable, 1=Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_DdiPort1Hpd, "Enable or disable HPD of DDI port 1", &EN_DIS, + Help "0=Disable, 1(Default)=Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_DdiPort2Hpd, "Enable or disable HPD of DDI port 2", &EN_DIS, + Help "0(Default)=Disable, 1=Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_DdiPort3Hpd, "Enable or disable HPD of DDI port 3", &EN_DIS, + Help "0(Default)=Disable, 1=Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_DdiPort4Hpd, "Enable or disable HPD of DDI port 4", &EN_DIS, + Help "0(Default)=Disable, 1=Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_DdiPortADdc, "Enable or disable DDC of DDI port A", &EN_DIS, + Help "0(Default)=Disable, 1=Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_DdiPortBDdc, "Enable or disable DDC of DDI port B", &EN_DIS, + Help "0=Disable, 1(Default)=Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_DdiPortCDdc, "Enable or disable DDC of DDI port C", &EN_DIS, + Help "0(Default)=Disable, 1=Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_DdiPort1Ddc, "Enable DDC setting of DDI Port 1", &EN_DIS, + Help "0(Default)=Disable, 1=Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_DdiPort2Ddc, "Enable DDC setting of DDI Port 2", &EN_DIS, + Help "0(Default)=Disable, 1=Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_DdiPort3Ddc, "Enable DDC setting of DDI Port 3", &EN_DIS, + Help "0(Default)=Disable, 1=Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_DdiPort4Ddc, "Enable DDC setting of DDI Port 4", &EN_DIS, + Help "0(Default)=Disable, 1=Enable" + EditNum $gPlatformFspPkgTokenSpaceGuid_GmAdr64, "Temporary MMIO address for GMADR", HEX, + Help "The reference code will use this as Temporary MMIO address space to access GMADR Registers.Platform should provide conflict free Temporary MMIO Range: GmAdr to (GmAdr + ApertureSize). Default is (PciExpressBaseAddress - ApertureSize) to (PciExpressBaseAddress - 0x1) (Where ApertureSize = 256MB, 512MB, 1024MB and 2048MB)" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PerCoreHtDisable, "Per-core HT Disable", HEX, + Help "Defines the per-core HT disable mask where: 1 - Disable selected logical core HT, 0 - is ignored. Input is in HEX and each bit maps to a logical core. Ex. A value of '1F' would disable HT for cores 4,3,2,1 and 0. Default is 0, all cores have HT enabled. Range is 0 - 0x7F for max 8 cores. You can only disable up to MAX_CORE_COUNT - 1." + "Valid range: 0x00 ~ 0x7F" + Combo $gPlatformFspPkgTokenSpaceGuid_SaVoltageMode, "SA/Uncore voltage mode", &EN_DIS, + Help "SA/Uncore voltage mode; 0: Adaptive; 1: Override." + EditNum $gPlatformFspPkgTokenSpaceGuid_SaVoltageOverride, "SA/Uncore Voltage Override", HEX, + Help "The SA/Uncore voltage override applicable when SA/Uncore voltage mode is in Override mode. Valid Range 0 to 2000" + "Valid range: 0x00 ~ 0x7D0" + EditNum $gPlatformFspPkgTokenSpaceGuid_SaExtraTurboVoltage, "SA/Uncore Extra Turbo voltage", HEX, + Help "Extra Turbo voltage applicable when SA/Uncore voltage mode is in Adaptive mode. Valid Range 0 to 2000" + "Valid range: 0x00 ~ 0x7D0" + Combo $gPlatformFspPkgTokenSpaceGuid_TvbRatioClipping, "Thermal Velocity Boost Ratio clipping", &gPlatformFspPkgTokenSpaceGuid_TvbRatioClipping, + Help "0(Default): Disabled, 1: Enabled. This service controls Core frequency reduction caused by high package temperatures for processors that implement the Intel Thermal Velocity Boost (TVB) feature" + Combo $gPlatformFspPkgTokenSpaceGuid_TvbVoltageOptimization, "Thermal Velocity Boost voltage optimization", &gPlatformFspPkgTokenSpaceGuid_TvbVoltageOptimization, + Help "0: Disabled, 1: Enabled(Default). This service controls thermal based voltage optimizations for processors that implement the Intel Thermal Velocity Boost (TVB) feature." + Combo $gPlatformFspPkgTokenSpaceGuid_DisplayAudioLink, "Enable/Disable Display Audio Link in Pre-OS", &gPlatformFspPkgTokenSpaceGuid_DisplayAudioLink, + Help "0(Default)= Disable, 1 = Enable" + EditNum $gPlatformFspPkgTokenSpaceGuid_GtPllVoltageOffset, "GT PLL voltage offset", HEX, + Help "Core PLL voltage offset. 0: No offset. Range 0-15" + "Valid range: 0x00 ~ 0x0F" + EditNum $gPlatformFspPkgTokenSpaceGuid_RingPllVoltageOffset, "Ring PLL voltage offset", HEX, + Help "Core PLL voltage offset. 0: No offset. Range 0-15" + "Valid range: 0x00 ~ 0x0F" + EditNum $gPlatformFspPkgTokenSpaceGuid_SaPllVoltageOffset, "System Agent PLL voltage offset", HEX, + Help "Core PLL voltage offset. 0: No offset. Range 0-15" + "Valid range: 0x00 ~ 0x0F" + EditNum $gPlatformFspPkgTokenSpaceGuid_McPllVoltageOffset, "Memory Controller PLL voltage offset", HEX, + Help "Core PLL voltage offset. 0: No offset. Range 0-15" + "Valid range: 0x00 ~ 0x0F" + Combo $gPlatformFspPkgTokenSpaceGuid_CridEnable, "Enable/Disable SA CRID", &EN_DIS, + Help "Enable: SA CRID, Disable (Default): SA CRID" + Combo $gPlatformFspPkgTokenSpaceGuid_WrcFeatureEnable, "WRC Feature", &EN_DIS, + Help "Enable/Disable WRC (Write Cache) feature of IOP. When feature is enabled, supports IO devices allocating onto the ring and into LLC. WRC is fused on by default." + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieImrSize, "Size of PCIe IMR.", HEX, + Help "Size of PCIe IMR in megabytes" + "Valid range: 0x00 ~ 0xFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PcieImrEnabled, "Enable PCIe IMR", &EN_DIS, + Help "0: Disable(AUTO), 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_PcieImrRpLocation, "Enable PCIe IMR", &EN_DIS, + Help "1: PCH PCIE, 2: SA PCIE. If PCIeImrEnabled is TRUE then this will use to select the Root port location from PCH PCIe or SA PCIe" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieImrRpSelection, "Root port number for IMR.", HEX, + Help "Root port number for IMR.If PCieImrRpLocation is PCH PCIe then select root port from 0 to 23 and if it is SA PCIe then select root port from 0 to 3" + "Valid range: 0x00 ~ 0x17" + Combo $gPlatformFspPkgTokenSpaceGuid_SkipExtGfxScan, "Skip external display device scanning", &EN_DIS, + Help "Enable: Do not scan for external display device, Disable (Default): Scan external display devices" + EditNum $gPlatformFspPkgTokenSpaceGuid_DmaBufferSize, "PMR Size", HEX, + Help "Size of PMR memory buffer. 0x400000 for normal boot and 0x200000 for S3 boot" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PreBootDmaMask, "VT-d/IOMMU Boot Policy", HEX, + Help "BIT0: Enable IOMMU during boot, BIT1: Enable IOMMU when transfer control to OS" + "Valid range: 0x00 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_DeltaT12PowerCycleDelay, "Delta T12 Power Cycle Delay required in ms", &gPlatformFspPkgTokenSpaceGuid_DeltaT12PowerCycleDelay, + Help "Select the value for delay required. 0= No delay, 0xFFFF(Default) = Auto calculate T12 Delay to max 500ms" + EditNum $gPlatformFspPkgTokenSpaceGuid_CpuPcie1Rtd3Gpio, "Hybrid Graphics GPIO information for PEG 1", HEX, + Help "Hybrid Graphics GPIO information for PEG 1, for Reset, power and wake GPIOs" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CpuPcie2Rtd3Gpio, "Hybrid Graphics GPIO information for PEG 2", HEX, + Help "Hybrid Graphics GPIO information for PEG 2, for Reset, power and wake GPIOs" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CpuPcie3Rtd3Gpio, "Hybrid Graphics GPIO information for PEG 3", HEX, + Help "Hybrid Graphics GPIO information for PEG 3, for Reset, power and wake GPIOs" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_Avx2VoltageScaleFactor, "Avx2 Voltage Guardband Scaling Factor", HEX, + Help "AVX2 Voltage Guardband Scale factor applied to AVX2 workloads. Range is 0-200 in 1/100 units, where a value of 125 would apply a 1.25 scale factor." + "Valid range: 0x00 ~ 0xC8" + EditNum $gPlatformFspPkgTokenSpaceGuid_Avx512VoltageScaleFactor, "Avx512 Voltage Guardband Scaling Factor", HEX, + Help "DEPRECATED" + "Valid range: 0x00 ~ 0xC8" +EndPage + +Page "System Agent (Post-Mem)" + EditNum $gPlatformFspPkgTokenSpaceGuid_LogoPtr, "Logo Pointer", HEX, + Help "Points to PEI Display Logo Image" + "Valid range: 0x0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_LogoSize, "Logo Size", HEX, + Help "Size of PEI Display Logo Image" + "Valid range: 0x0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_BltBufferAddress, "Blt Buffer Address", HEX, + Help "Address of Blt buffer" + "Valid range: 0x0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_BltBufferSize, "Blt Buffer Size", HEX, + Help "Size of Blt Buffer, is equal to PixelWidth * PixelHeight * 4 bytes (the size of EFI_GRAPHICS_OUTPUT_BLT_PIXEL)" + "Valid range: 0x0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_GraphicsConfigPtr, "Graphics Configuration Ptr", HEX, + Help "Points to VBT" + "Valid range: 0x0 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_Device4Enable, "Enable Device 4", &EN_DIS, + Help "Enable/disable Device 4" + Combo $gPlatformFspPkgTokenSpaceGuid_PavpEnable, "Enable/Disable PavpEnable", &EN_DIS, + Help "Enable(Default): Enable PavpEnable, Disable: Disable PavpEnable" + Combo $gPlatformFspPkgTokenSpaceGuid_CdClock, "CdClock Frequency selection", &gPlatformFspPkgTokenSpaceGuid_CdClock, + Help "0 (Default) Auto (Max based on reference clock frequency), 0: 192, 1: 307.2, 2: 312 Mhz, 3: 324Mhz, 4: 326.4 Mhz, 5: 552 Mhz, 6: 556.8 Mhz, 7: 648 Mhz, 8: 652.8 Mhz" + Combo $gPlatformFspPkgTokenSpaceGuid_PeiGraphicsPeimInit, "Enable/Disable PeiGraphicsPeimInit", &EN_DIS, + Help "Enable(Default): FSP will initialize the framebuffer and provide it via EFI_PEI_GRAPHICS_INFO_HOB. Disable: FSP will NOT initialize the framebuffer." + Combo $gPlatformFspPkgTokenSpaceGuid_GnaEnable, "Enable or disable GNA device", &EN_DIS, + Help "0=Disable, 1(Default)=Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_SkipFspGop, "Enable/Disable SkipFspGop", &EN_DIS, + Help "Enable: Skip FSP provided GOP driver, Disable(Default): Use FSP provided GOP driver" + Combo $gPlatformFspPkgTokenSpaceGuid_SaPostMemRsvd, "SaPostMemRsvd", &EN_DIS, + Help "Reserved for PCH Post-Mem" + EditNum $gPlatformFspPkgTokenSpaceGuid_SendEcCmd, "SendEcCmd", HEX, + Help "SendEcCmd function pointer. \n @code typedef EFI_STATUS (EFIAPI *PLATFORM_SEND_EC_COMMAND) (IN EC_COMMAND_TYPE EcCmdType, IN UINT8 EcCmd, IN UINT8 SendData, IN OUT UINT8 *ReceiveData); @endcode" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_EcCmdProvisionEav, "EcCmdProvisionEav", HEX, + Help "Ephemeral Authorization Value default values. Provisions an ephemeral shared secret to the EC" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_EcCmdLock, "EcCmdLock", HEX, + Help "EcCmdLock default values. Locks Ephemeral Authorization Value sent previously" + "Valid range: 0x00 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_SiSkipSsidProgramming, "Skip Ssid Programming.", &EN_DIS, + Help "When set to TRUE, silicon code will not do any SSID programming and platform code needs to handle that by itself properly." + EditNum $gPlatformFspPkgTokenSpaceGuid_SiCustomizedSvid, "Change Default SVID", HEX, + Help "Change the default SVID used in FSP to programming internal devices. This is only valid when SkipSsidProgramming is FALSE." + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SiCustomizedSsid, "Change Default SSID", HEX, + Help "Change the default SSID used in FSP to programming internal devices. This is only valid when SkipSsidProgramming is FALSE." + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SiSsidTablePtr, "SVID SDID table Poniter.", HEX, + Help "The address of the table of SVID SDID to customize each SVID SDID entry. This is only valid when SkipSsidProgramming is FALSE." + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SiNumberOfSsidTableEntry, "Number of ssid table.", HEX, + Help "SiNumberOfSsidTableEntry should match the table entries created in SiSsidTablePtr. This is only valid when SkipSsidProgramming is FALSE." + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PortResetMessageEnable, "USB2 Port Reset Message Enable", HEX, + Help "0: Disable USB2 Port Reset Message; 1: Enable USB2 Port Reset Message; This must be enable for USB2 Port those are paired with CPU XHCI Port" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_SataRstInterrupt, "SATA RST Interrupt Mode", &gPlatformFspPkgTokenSpaceGuid_SataRstInterrupt, + Help "Allowes to choose which interrupts will be implemented by SATA controller in RAID mode." + Combo $gPlatformFspPkgTokenSpaceGuid_SkipPamLock, "Skip PAM regsiter lock", &EN_DIS, + Help "Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): PAM registers will be locked by RC" + Combo $gPlatformFspPkgTokenSpaceGuid_EdramTestMode, "EDRAM Test Mode", &gPlatformFspPkgTokenSpaceGuid_EdramTestMode, + Help "Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): PAM registers will be locked by RC" + Combo $gPlatformFspPkgTokenSpaceGuid_RenderStandby, "Enable/Disable IGFX RenderStandby", &EN_DIS, + Help "Enable(Default): Enable IGFX RenderStandby, Disable: Disable IGFX RenderStandby" + Combo $gPlatformFspPkgTokenSpaceGuid_PmSupport, "Enable/Disable IGFX PmSupport", &EN_DIS, + Help "Enable(Default): Enable IGFX PmSupport, Disable: Disable IGFX PmSupport" + Combo $gPlatformFspPkgTokenSpaceGuid_CdynmaxClampEnable, "Enable/Disable CdynmaxClamp", &EN_DIS, + Help "Enable: Enable CdynmaxClamp, Disable(Default): Disable CdynmaxClamp" + Combo $gPlatformFspPkgTokenSpaceGuid_GtFreqMax, "GT Frequency Limit", &gPlatformFspPkgTokenSpaceGuid_GtFreqMax, + Help "0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD: 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz, 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz, 0x18: 1200 Mhz" + Combo $gPlatformFspPkgTokenSpaceGuid_DisableTurboGt, "Disable Turbo GT", &EN_DIS, + Help " 0=Disable: GT frequency is not limited, 1=Enable: Disables Turbo GT frequency" + Combo $gPlatformFspPkgTokenSpaceGuid_SkipCdClockInit, "Enable/Disable CdClock Init", &EN_DIS, + Help "Enable: Skip Full CD clock initializaton, Disable(Default): Initialize the full CD clock if not initialized by Gfx PEIM" + Combo $gPlatformFspPkgTokenSpaceGuid_RC1pFreqEnable, "Enable RC1p frequency request to PMA (provided all other conditions are met)", &EN_DIS, + Help "0(Default)=Disable, 1=Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_PchTsnMultiVcEnable, "Enable TSN Multi-VC", &EN_DIS, + Help "Enable/disable Multi Virtual Channels(VC) in TSN." + EditNum $gPlatformFspPkgTokenSpaceGuid_LogoPixelHeight, "LogoPixelHeight Address", HEX, + Help "Address of LogoPixelHeight" + "Valid range: 0x0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_LogoPixelWidth, "LogoPixelWidth Address", HEX, + Help "Address of LogoPixelWidth" + "Valid range: 0x0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_Usb4CmMode, "ITbt Usb4CmMode value", HEX, + Help "ITbt Usb4CmMode value. 0:Firmware CM, 1:Software CM" + "Valid range: 0x00 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_CpuPcieResizableBarSupport, "PCIE Resizable BAR Support", &EN_DIS, + Help "Enable/Disable PCIE Resizable BAR Support.0: Disable; 1: Enable; 2: Auto(Default)." + Combo $gPlatformFspPkgTokenSpaceGuid_SaPostMemTestRsvd, "SaPostMemTestRsvd", &EN_DIS, + Help "Reserved for SA Post-Mem Test" + EditNum $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpLtrMaxSnoopLatency, "PCIE RP Ltr Max Snoop Latency", HEX, + Help "Latency Tolerance Reporting, Max Snoop Latency." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpLtrMaxNoSnoopLatency, "PCIE RP Ltr Max No Snoop Latency", HEX, + Help "Latency Tolerance Reporting, Max Non-Snoop Latency." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpSnoopLatencyOverrideMode, "PCIE RP Snoop Latency Override Mode", HEX, + Help "Latency Tolerance Reporting, Snoop Latency Override Mode." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpSnoopLatencyOverrideMultiplier, "PCIE RP Snoop Latency Override Multiplier", HEX, + Help "Latency Tolerance Reporting, Snoop Latency Override Multiplier." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpSnoopLatencyOverrideValue, "PCIE RP Snoop Latency Override Value", HEX, + Help "Latency Tolerance Reporting, Snoop Latency Override Value." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpNonSnoopLatencyOverrideMode, "PCIE RP Non Snoop Latency Override Mode", HEX, + Help "Latency Tolerance Reporting, Non-Snoop Latency Override Mode." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpNonSnoopLatencyOverrideMultiplier, "PCIE RP Non Snoop Latency Override Multiplier", HEX, + Help "Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpNonSnoopLatencyOverrideValue, "PCIE RP Non Snoop Latency Override Value", HEX, + Help "Latency Tolerance Reporting, Non-Snoop Latency Override Value." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpGen3Uptp, "PCIE RP Upstream Port Transmiter Preset", HEX, + Help "Used during Gen3 Link Equalization. Used for all lanes. Default is 7." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpGen3Dptp, "PCIE RP Downstream Port Transmiter Preset", HEX, + Help "Used during Gen3 Link Equalization. Used for all lanes. Default is 7." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpGen4Uptp, "PCIE RP Upstream Port Transmiter Preset", HEX, + Help "Used during Gen4 Link Equalization. Used for all lanes. Default is 8." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpGen4Dptp, "PCIE RP Downstream Port Transmiter Preset", HEX, + Help "Used during Gen4 Link Equalization. Used for all lanes. Default is 9." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpGen5Uptp, "PCIE RP Upstream Port Transmiter Preset", HEX, + Help "Used during Gen5 Link Equalization. Used for all lanes. Default is 7." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpGen5Dptp, "PCIE RP Downstream Port Transmiter Preset", HEX, + Help "Used during Gen5 Link Equalization. Used for all lanes. Default is 7." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_CpuPcieFomsCp, "FOMS Control Policy", &gPlatformFspPkgTokenSpaceGuid_CpuPcieFomsCp, + Help "Choose the Foms Control Policy, Default = 0 " + Combo $gPlatformFspPkgTokenSpaceGuid_PmcC10DynamicThresholdAdjustment, "PMC C10 dynamic threshold dajustment enable", &EN_DIS, + Help "Set if you want to enable PMC C10 dynamic threshold adjustment. Only works on supported SKUs" + Combo $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpPeerToPeerMode, "P2P mode for PCIE RP", &gPlatformFspPkgTokenSpaceGuid_CpuPcieRpPeerToPeerMode, + Help "Enable/disable peer to peer mode for PCIE Root Ports. 0: Disable, 1: Enable." + EditNum $gPlatformFspPkgTokenSpaceGuid_TurboRatioLimitRatio, "Turbo Ratio Limit Ratio array", HEX, + Help "TurboRatioLimitRatio[7-0] will pair with TurboRatioLimitNumCore[7-0] to determine the active core ranges for each frequency point." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_TurboRatioLimitNumCore, "Turbo Ratio Limit Num Core array", HEX, + Help "TurboRatioLimitNumCore[7-0] will pair with TurboRatioLimitRatio[7-0] to determine the active core ranges for each frequency point." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_AtomTurboRatioLimitRatio, "ATOM Turbo Ratio Limit Ratio array", HEX, + Help "AtomTurboRatioLimitRatio[7-0] will pair with AtomTurboRatioLimitNumCore[7-0] to determine the active core ranges for each frequency point." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_AtomTurboRatioLimitNumCore, "ATOM Turbo Ratio Limit Num Core array", HEX, + Help "AtomTurboRatioLimitNumCore[7-0] will pair with AtomTurboRatioLimitRatio[7-0] to determine the active core ranges for each frequency point." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_FspEventHandler, "FspEventHandler", HEX, + Help "Optional pointer to the boot loader's implementation of FSP_EVENT_HANDLER." + "Valid range: 0x0 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_VmdGlobalMapping, "Enable VMD Global Mapping", &EN_DIS, + Help "Enable/disable to VMD controller.0: Disable; 1: Enable(Default)" + Combo $gPlatformFspPkgTokenSpaceGuid_CpuPcieFunc0LinkDisable, "CPU PCIE Port0 Link Disable", &EN_DIS, + Help "CPU PCIE Port0 Link Disable while Device attached into Port0 and Port1.0: Disable(Default); 1: Enable." + Combo $gPlatformFspPkgTokenSpaceGuid_PmcSkipVccInConfig, "Skip VccIn Configuration", &EN_DIS, + Help "Skips VccIn configuration when enabled" + Combo $gPlatformFspPkgTokenSpaceGuid_CseDataResilience, "CSE Data Resilience Support", &EN_DIS, + Help "0: Disable CSE Data Resilience Support. ; 1: Enable CSE Data Resilience Support." + EditNum $gPlatformFspPkgTokenSpaceGuid_HorizontalResolution, "HorizontalResolution for PEI Logo", HEX, + Help "HorizontalResolution from PEIm Gfx for PEI Logo" + "Valid range: 0x0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_VerticalResolution, "VerticalResolution for PEI Logo", HEX, + Help "VerticalResolution from PEIm Gfx for PEI Logo" + "Valid range: 0x0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcActiveLtr, "Touch Host Controller Active Ltr", HEX, + Help "Expose Active Ltr for OS driver to set" + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcIdleLtr, "Touch Host Controller Idle Ltr", HEX, + Help "Expose Idle Ltr for OS driver to set" + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcHidResetPad, "Touch Host Controller Hid Over Spi ResetPad", HEX, + Help "Hid Over Spi ResetPad 0x0 - Use THC HW default Pad, For other pad setting refer to GpioPins" + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcHidResetPadTrigger, "Touch Host Controller Hid Over Spi ResetPad Trigger", HEX, + Help "Hid Over Spi Reset Pad Trigger 0x0:Low, 0x1:High" + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcHidConnectionSpeed, "Touch Host Controller Hid Over Spi Connection Speed", HEX, + Help "Hid Over Spi Connection Speed - SPI Frequency" + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcLimitPacketSize, "Touch Host Controller Hid Over Spi Limit PacketSize", HEX, + Help "When set, limits SPI read & write packet size to 64B. Otherwise, THC uses Max Soc packet size for SPI Read and Write 0x0- Max Soc Packet Size, 0x11 - 64 Bytes" + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcPerformanceLimitation, "Touch Host Controller Hid Over Spi Limit PacketSize", HEX, + Help "Minimum amount of delay the THC/QUICKSPI driver must wait between end of write operation and begin of read operation. This value shall be in 10us multiples 0x0: Disabled, 1-65535 (0xFFFF) - up to 655350 us" + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcHidInputReportHeaderAddress, "Touch Host Controller Hid Over Spi Input Report Header Address", HEX, + Help "Hid Over Spi Input Report Header Address" + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcHidInputReportBodyAddress, "Touch Host Controller Hid Over Spi Input Report Body Address", HEX, + Help "Hid Over Spi Input Report Body Address" + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcHidOutputReportAddress, "Touch Host Controller Hid Over Spi Output Report Address", HEX, + Help "Hid Over Spi Output Report Address" + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcHidReadOpcode, "Touch Host Controller Hid Over Spi Read Opcode", HEX, + Help "Hid Over Spi Read Opcode" + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcHidWriteOpcode, "Touch Host Controller Hid Over Spi Write Opcode", HEX, + Help "Hid Over Spi Write Opcode" + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcHidFlags, "Touch Host Controller Hid Over Spi Flags", HEX, + Help "Hid Over Spi Flags 0x0:Single SPI Mode, 0x4000:Dual SPI Mode, 0x8000:Quad SPI Mode" + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFF" +EndPage + +Page "PCH (Pre-Mem)" + Combo $gPlatformFspPkgTokenSpaceGuid_SmbusEnable, "Enable SMBus", &EN_DIS, + Help "Enable/disable SMBus controller." + Combo $gPlatformFspPkgTokenSpaceGuid_PchTraceHubMode, "PCH Trace Hub Mode", &gPlatformFspPkgTokenSpaceGuid_PchTraceHubMode, + Help "Select 'Host Debugger' if Trace Hub is used with host debugger tool or 'Target Debugger' if Trace Hub is used by target debugger software or 'Disable' trace hub functionality." + Combo $gPlatformFspPkgTokenSpaceGuid_PchTraceHubMemReg0Size, "PCH Trace Hub Memory Region 0 buffer Size", &gPlatformFspPkgTokenSpaceGuid_PchTraceHubMemReg0Size, + Help "Specify size of Pch trace memory region 0 buffer, the size can be 0, 1MB, 8MB, 64MB, 128MB, 256MB, 512MB" + Combo $gPlatformFspPkgTokenSpaceGuid_PchTraceHubMemReg1Size, "PCH Trace Hub Memory Region 1 buffer Size", &gPlatformFspPkgTokenSpaceGuid_PchTraceHubMemReg1Size, + Help "Specify size of Pch trace memory region 1 buffer, the size can be 0, 1MB, 8MB, 64MB, 128MB, 256MB, 512MB" + Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkDmicClockSelect, "HD Audio DMIC Link Clock Select", &gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkDmicClockSelect, + Help "Determines DMIC Clock Source. 0: Both, 1: ClkA, 2: ClkB" + Combo $gPlatformFspPkgTokenSpaceGuid_PchPreMemRsvd, "PchPreMemRsvd", &EN_DIS, + Help "Reserved for PCH Pre-Mem Reserved" + Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaEnable, "Enable Intel HD Audio (Azalia)", &EN_DIS, + Help "0: Disable, 1: Enable (Default) Azalia controller" + Combo $gPlatformFspPkgTokenSpaceGuid_PchIshEnable, "Enable PCH ISH Controller", &EN_DIS, + Help "0: Disable, 1: Enable (Default) ISH Controller" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioRxSetCtleEnable, "Enable PCH HSIO PCIE Rx Set Ctle", HEX, + Help "Enable PCH PCIe Gen 3 Set CTLE Value." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioRxSetCtle, "PCH HSIO PCIE Rx Set Ctle Value", HEX, + Help "PCH PCIe Gen 3 Set CTLE Value." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen1DownscaleAmpEnable, "Enble PCH HSIO PCIE TX Gen 1 Downscale Amplitude Adjustment value override", HEX, + Help "0: Disable; 1: Enable." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen1DownscaleAmp, "PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value", HEX, + Help "PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DownscaleAmpEnable, "Enable PCH HSIO PCIE TX Gen 2 Downscale Amplitude Adjustment value override", HEX, + Help "0: Disable; 1: Enable." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DownscaleAmp, "PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value", HEX, + Help "PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen3DownscaleAmpEnable, "Enable PCH HSIO PCIE TX Gen 3 Downscale Amplitude Adjustment value override", HEX, + Help "0: Disable; 1: Enable." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen3DownscaleAmp, "PCH HSIO PCIE Gen 3 TX Output Downscale Amplitude Adjustment value", HEX, + Help "PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen1DeEmphEnable, "Enable PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment Setting value override", HEX, + Help "0: Disable; 1: Enable." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen1DeEmph, "PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment value", HEX, + Help "PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DeEmph3p5Enable, "Enable PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting value override", HEX, + Help "0: Disable; 1: Enable." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DeEmph3p5, "PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment value", HEX, + Help "PCH PCIe Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DeEmph6p0Enable, "Enable PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting value override", HEX, + Help "0: Disable; 1: Enable." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DeEmph6p0, "PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment value", HEX, + Help "PCH PCIe Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen1EqBoostMagEnable, "Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override", HEX, + Help "0: Disable; 1: Enable." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen1EqBoostMag, "PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value", HEX, + Help "PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen2EqBoostMagEnable, "Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override", HEX, + Help "0: Disable; 1: Enable." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen2EqBoostMag, "PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value", HEX, + Help "PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen3EqBoostMagEnable, "Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override", HEX, + Help "0: Disable; 1: Enable." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen3EqBoostMag, "PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value", HEX, + Help "PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen1DownscaleAmpEnable, "Enable PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value override", HEX, + Help "0: Disable; 1: Enable." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen1DownscaleAmp, "PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value", HEX, + Help "PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen2DownscaleAmpEnable, "Enable PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value override", HEX, + Help "0: Disable; 1: Enable." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen2DownscaleAmp, "PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value", HEX, + Help "PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen3DownscaleAmpEnable, "Enable PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value override", HEX, + Help "0: Disable; 1: Enable." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen3DownscaleAmp, "PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value", HEX, + Help "PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen1DeEmphEnable, "Enable PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting value override", HEX, + Help "0: Disable; 1: Enable." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen1DeEmph, "PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting", HEX, + Help "PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen2DeEmphEnable, "Enable PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting value override", HEX, + Help "0: Disable; 1: Enable." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen2DeEmph, "PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting", HEX, + Help "PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen3DeEmphEnable, "Enable PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override", HEX, + Help "0: Disable; 1: Enable." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen3DeEmph, "PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting", HEX, + Help "PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_SmbusArpEnable, "Enable SMBus ARP support", &EN_DIS, + Help "Enable SMBus ARP support." + EditNum $gPlatformFspPkgTokenSpaceGuid_PchNumRsvdSmbusAddresses, "Number of RsvdSmbusAddressTable.", HEX, + Help "The number of elements in the RsvdSmbusAddressTable." + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchSmbusIoBase, "SMBUS Base Address", HEX, + Help "SMBUS Base Address (IO space)." + "Valid range: 0x00 ~ 0xFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PchSmbAlertEnable, "Enable SMBus Alert Pin", &EN_DIS, + Help "Enable SMBus Alert Pin." + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieClkSrcUsage, "Usage type for ClkSrc", HEX, + Help "0-23: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use (free running), 0xFF: not used" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieClkSrcClkReq, "ClkReq-to-ClkSrc mapping", HEX, + Help "Number of ClkReq signal assigned to ClkSrc" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieClkReqGpioMux, "Clk Req GPIO Pin", HEX, + Help "Select Clk Req Pin. Refer to GPIO_*_MUXING_SRC_CLKREQ_x* for possible values." + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_RsvdSmbusAddressTablePtr, "Point of RsvdSmbusAddressTable", HEX, + Help "Array of addresses reserved for non-ARP-capable SMBus devices." + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpEnableMask, "Enable PCIE RP Mask", HEX, + Help "Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 for port1, bit1 for port2, and so on." + "Valid range: 0x00 ~ 0x00FFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaVcType, "VC Type", &gPlatformFspPkgTokenSpaceGuid_PchHdaVcType, + Help "Virtual Channel Type Select: 0: VC0, 1: VC1." + Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaDspUaaCompliance, "Universal Audio Architecture compliance for DSP enabled system", &EN_DIS, + Help "0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox driver or SST driver supported)." + Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkHdaEnable, "Enable HD Audio Link", &EN_DIS, + Help "Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1." + EditNum $gPlatformFspPkgTokenSpaceGuid_PchHdaSdiEnable, "Enable HDA SDI lanes", HEX, + Help "Enable/disable HDA SDI lanes." + "Valid range: 0x00 ~ 0xFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaTestPowerClockGating, "HDA Power/Clock Gating (PGD/CGD)", &gPlatformFspPkgTokenSpaceGuid_PchHdaTestPowerClockGating, + Help "Enable/Disable HD Audio Power and Clock Gating(POR: Enable). 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE." + EditNum $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkDmicEnable, "Enable HD Audio DMIC_N Link", HEX, + Help "Enable/disable HD Audio DMIC1 link. Muxed with SNDW3." + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkDmicClkAPinMux, "DMIC ClkA Pin Muxing (N - DMIC number)", HEX, + Help "Determines DMIC ClkA Pin muxing. See GPIO_*_MUXING_DMIC_CLKA_*" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkDmicClkBPinMux, "DMIC ClkB Pin Muxing", HEX, + Help "Determines DMIC ClkA Pin muxing. See GPIO_*_MUXING_DMIC_CLKB_*" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaDspEnable, "Enable HD Audio DSP", &EN_DIS, + Help "Enable/disable HD Audio DSP feature." + EditNum $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkDmicDataPinMux, "DMIC Data Pin Muxing", HEX, + Help "Determines DMIC Data Pin muxing. See GPIO_*_MUXING_DMIC_DATA_*" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSspEnable, "Enable HD Audio SSP0 Link", HEX, + Help "Enable/disable HD Audio SSP_N/I2S link. Muxed with HDA. N-number 0-5" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSndwEnable, "Enable HD Audio SoundWire#N Link", HEX, + Help "Enable/disable HD Audio SNDW#N link. Muxed with HDA." + "Valid range: 0x00 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaIDispLinkFrequency, "iDisp-Link Frequency", &gPlatformFspPkgTokenSpaceGuid_PchHdaIDispLinkFrequency, + Help "iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz." + Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaIDispLinkTmode, "iDisp-Link T-mode", &gPlatformFspPkgTokenSpaceGuid_PchHdaIDispLinkTmode, + Help "iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 2: 4T, 3: 8T, 4: 16T" + Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaIDispCodecDisconnect, "iDisplay Audio Codec disconnection", &EN_DIS, + Help "0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable." + Combo $gPlatformFspPkgTokenSpaceGuid_CnviDdrRfim, "CNVi DDR RFI Mitigation", &EN_DIS, + Help "Enable/Disable DDR RFI Mitigation. Default is ENABLE. 0: DISABLE, 1: ENABLE" + Combo $gPlatformFspPkgTokenSpaceGuid_PcdIsaSerialUartBase, "ISA Serial Base selection", &gPlatformFspPkgTokenSpaceGuid_PcdIsaSerialUartBase, + Help "Select ISA Serial Base address. Default is 0x3F8." + Combo $gPlatformFspPkgTokenSpaceGuid_SmbusDynamicPowerGating, "Smbus dynamic power gating", &EN_DIS, + Help "Disable or Enable Smbus dynamic power gating." + Combo $gPlatformFspPkgTokenSpaceGuid_WdtDisableAndLock, "Disable and Lock Watch Dog Register", &EN_DIS, + Help "Set 1 to clear WDT status, then disable and lock WDT registers." + Combo $gPlatformFspPkgTokenSpaceGuid_SmbusSpdWriteDisable, "SMBUS SPD Write Disable", &EN_DIS, + Help "Set/Clear Smbus SPD Write Disable. 0: leave SPD Write Disable bit; 1: set SPD Write Disable bit. For security recommendations, SPD write disable bit must be set." + Combo $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugMode, "Serial Io Uart Debug Mode", &gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugMode, + Help "Select SerialIo Uart Controller mode" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugRxPinMux, "SerialIoUartDebugRxPinMux - FSPT", HEX, + Help "Select RX pin muxing for SerialIo UART used for debug" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugTxPinMux, "SerialIoUartDebugTxPinMux - FSPM", HEX, + Help "Select TX pin muxing for SerialIo UART used for debug" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugRtsPinMux, "SerialIoUartDebugRtsPinMux - FSPM", HEX, + Help "Select SerialIo Uart used for debug Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS* for possible values." + "Valid range: 0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugCtsPinMux, "SerialIoUartDebugCtsPinMux - FSPM", HEX, + Help "Select SerialIo Uart used for debug Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS* for possible values." + "Valid range: 0 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PprEnable, "Ppr Enable Type", &gPlatformFspPkgTokenSpaceGuid_PprEnable, + Help "Enable Soft or Hard PPR 0:Disable, 2:Hard PPR" +EndPage + +Page "PCH (Post-Mem)" + Combo $gPlatformFspPkgTokenSpaceGuid_ShowSpiController, "Show SPI controller", &EN_DIS, + Help "Enable/disable to show SPI controller." + Combo $gPlatformFspPkgTokenSpaceGuid_SataSalpSupport, "Enable SATA SALP Support", &EN_DIS, + Help "Enable/disable SATA Aggressive Link Power Management." + EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsEnable, "Enable SATA ports", HEX, + Help "Enable/disable SATA ports. One byte for each port, byte0 for port0, byte1 for port1, and so on." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsDevSlp, "Enable SATA DEVSLP Feature", HEX, + Help "Enable/disable SATA DEVSLP per port. 0 is disable, 1 is enable. One byte for each port, byte0 for port0, byte1 for port1, and so on." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortDevSlpPinMux, "SATA DEVSLP GPIO Pin", HEX, + Help "Select SATA DEVSLP Pin. Refer to GPIO_*_MUXING_SATA_DEVSLP_x* for possible values." + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PortUsb20Enable, "Enable USB2 ports", HEX, + Help "Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PortUsb30Enable, "Enable USB3 ports", HEX, + Help "Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_XdciEnable, "Enable xDCI controller", &EN_DIS, + Help "Enable/disable to xDCI controller." + EditNum $gPlatformFspPkgTokenSpaceGuid_DevIntConfigPtr, "Address of PCH_DEVICE_INTERRUPT_CONFIG table.", HEX, + Help "The address of the table of PCH_DEVICE_INTERRUPT_CONFIG." + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_NumOfDevIntConfig, "Number of DevIntConfig Entry", HEX, + Help "Number of Device Interrupt Configuration Entry. If this is not zero, the DevIntConfigPtr must not be NULL." + "Valid range: 0x00 ~ 0x40" + EditNum $gPlatformFspPkgTokenSpaceGuid_PxRcConfig, "PIRQx to IRQx Map Config", HEX, + Help "PIRQx to IRQx mapping. The valid value is 0x00 to 0x0F for each. First byte is for PIRQA, second byte is for PIRQB, and so on. The setting is only available in Legacy 8259 PCI mode." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_GpioIrqRoute, "Select GPIO IRQ Route", HEX, + Help "GPIO IRQ Select. The valid value is 14 or 15." + "Valid range: 0x00 ~ 0x0F" + EditNum $gPlatformFspPkgTokenSpaceGuid_SciIrqSelect, "Select SciIrqSelect", HEX, + Help "SCI IRQ Select. The valid value is 9, 10, 11, and 20, 21, 22, 23 for APIC only." + "Valid range: 0x00 ~ 0x17" + EditNum $gPlatformFspPkgTokenSpaceGuid_TcoIrqSelect, "Select TcoIrqSelect", HEX, + Help "TCO IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23." + "Valid range: 0x00 ~ 0x17" + Combo $gPlatformFspPkgTokenSpaceGuid_TcoIrqEnable, "Enable/Disable Tco IRQ", &EN_DIS, + Help "Enable/disable TCO IRQ" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchHdaVerbTableEntryNum, "PCH HDA Verb Table Entry Number", HEX, + Help "Number of Entries in Verb Table." + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchHdaVerbTablePtr, "PCH HDA Verb Table Pointer", HEX, + Help "Pointer to Array of pointers to Verb Table." + "Valid range: 0x0 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_SataEnable, "Enable SATA", &EN_DIS, + Help "Enable/disable SATA controller." + Combo $gPlatformFspPkgTokenSpaceGuid_SataMode, "SATA Mode", &gPlatformFspPkgTokenSpaceGuid_SataMode, + Help "Select SATA controller working mode." + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoSpiMode, "SPIn Device Mode", HEX, + Help "Selects SPI operation mode. N represents controller index: SPI0, SPI1, ... Available modes: 0:SerialIoSpiDisabled, 1:SerialIoSpiPci, 2:SerialIoSpiHidden" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoSpiCsPolarity, "SPI Chip Select Polarity", HEX, + Help "Sets polarity for each chip Select. Available options: 0:SerialIoSpiCsActiveLow, 1:SerialIoSpiCsActiveHigh" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoSpiCsEnable, "SPI Chip Select Enable", HEX, + Help "0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoSpiDefaultCsOutput, "SPIn Default Chip Select Output", HEX, + Help "Sets Default CS as Output. N represents controller index: SPI0, SPI1, ... Available options: 0:CS0, 1:CS1" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoSpiCsMode, "SPIn Default Chip Select Mode HW/SW", HEX, + Help "Sets Default CS Mode Hardware or Software. N represents controller index: SPI0, SPI1, ... Available options: 0:HW, 1:SW" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoSpiCsState, "SPIn Default Chip Select State Low/High", HEX, + Help "Sets Default CS State Low or High. N represents controller index: SPI0, SPI1, ... Available options: 0:Low, 1:High" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartMode, "UARTn Device Mode", HEX, + Help "Selects Uart operation mode. N represents controller index: Uart0, Uart1, ... Available modes: 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom, 4:SerialIoUartSkipInit" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartBaudRate, "Default BaudRate for each Serial IO UART", HEX, + Help "Set default BaudRate Supported from 0 - default to 6000000" + "Valid range: 0x0 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartParity, "Default ParityType for each Serial IO UART", HEX, + Help "Set default Parity. 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity" + "Valid range: 0x0 ~ 0xFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDataBits, "Default DataBits for each Serial IO UART", HEX, + Help "Set default word length. 0: Default, 5,6,7,8" + "Valid range: 0x0 ~ 0xFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartStopBits, "Default StopBits for each Serial IO UART", HEX, + Help "Set default stop bits. 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits" + "Valid range: 0x0 ~ 0xFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartPowerGating, "Power Gating mode for each Serial IO UART that works in COM mode", HEX, + Help "Set Power Gating. 0: Disabled, 1: Enabled, 2: Auto" + "Valid range: 0x0 ~ 0xFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDmaEnable, "Enable Dma for each Serial IO UART that supports it", HEX, + Help "Set DMA/PIO mode. 0: Disabled, 1: Enabled" + "Valid range: 0x0 ~ 0xFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartAutoFlow, "Enables UART hardware flow control, CTS and RTS lines", HEX, + Help "Enables UART hardware flow control, CTS and RTS lines." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartRtsPinMuxPolicy, "SerialIoUartRtsPinMuxPolicy", HEX, + Help "Select SerialIo Uart Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS* for possible values." + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartCtsPinMuxPolicy, "SerialIoUartCtsPinMuxPolicy", HEX, + Help "Select SerialIo Uart Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS* for possible values." + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartRxPinMuxPolicy, "SerialIoUartRxPinMuxPolicy", HEX, + Help "Select SerialIo Uart Rx pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RX* for possible values." + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartTxPinMuxPolicy, "SerialIoUartTxPinMuxPolicy", HEX, + Help "Select SerialIo Uart Tx pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_TX* for possible values." + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoI2cMode, "I2Cn Device Mode", HEX, + Help "Selects I2c operation mode. N represents controller index: I2c0, I2c1, ... Available modes: 0:SerialIoI2cDisabled, 1:SerialIoI2cPci, 2:SerialIoI2cHidden" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchSerialIoI2cSdaPinMux, "Serial IO I2C SDA Pin Muxing", HEX, + Help "Select SerialIo I2c Sda pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SDA* for possible values." + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchSerialIoI2cSclPinMux, "Serial IO I2C SCL Pin Muxing", HEX, + Help "Select SerialIo I2c Scl pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SCL* for possible values." + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchSerialIoI2cPadsTermination, "PCH SerialIo I2C Pads Termination", HEX, + Help "0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C0,I2C1,... pads termination respectively. One byte for each controller, byte0 for I2C0, byte1 for I2C1, and so on." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IshGpGpioPinMuxing, "ISH GP GPIO Pin Muxing", HEX, + Help "Determines ISH GP GPIO Pin muxing. See GPIO_*_MUXING_ISH_GP_x_GPIO_*. 'x' are GP_NUMBER" + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IshUartRxPinMuxing, "ISH UART Rx Pin Muxing", HEX, + Help "Determines ISH UART Rx Pin muxing. See GPIO_*_MUXING_ISH_UARTx_TXD_*" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IshUartTxPinMuxing, "ISH UART Tx Pin Muxing", HEX, + Help "Determines ISH UART Tx Pin muxing. See GPIO_*_MUXING_ISH_UARTx_RXD_*" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IshUartRtsPinMuxing, "ISH UART Rts Pin Muxing", HEX, + Help "Select ISH UART Rts Pin muxing. Refer to GPIO_*_MUXING_ISH_UARTx_RTS_* for possible values." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IshUartCtsPinMuxing, "ISH UART Rts Pin Muxing", HEX, + Help "Select ISH UART Cts Pin muxing. Refer to GPIO_*_MUXING_ISH_UARTx_CTS_* for possible values." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IshI2cSdaPinMuxing, "ISH I2C SDA Pin Muxing", HEX, + Help "Select ISH I2C SDA Pin muxing. Refer to GPIO_*_MUXING_ISH_I2Cx_SDA_* for possible values." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IshI2cSclPinMuxing, "ISH I2C SCL Pin Muxing", HEX, + Help "Select ISH I2C SCL Pin muxing. Refer to GPIO_*_MUXING_ISH_I2Cx_SCL_* for possible values." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IshSpiMosiPinMuxing, "ISH SPI MOSI Pin Muxing", HEX, + Help "Select ISH SPI MOSI Pin muxing. Refer to GPIO_*_MUXING_ISH_SPIx_MOSI_* for possible values." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IshSpiMisoPinMuxing, "ISH SPI MISO Pin Muxing", HEX, + Help "Select ISH SPI MISO Pin muxing. Refer to GPIO_*_MUXING_ISH_SPIx_MISO_* for possible values." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IshSpiClkPinMuxing, "ISH SPI CLK Pin Muxing", HEX, + Help "Select ISH SPI CLK Pin muxing. Refer to GPIO_*_MUXING_ISH_SPIx_CLK_* for possible values." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IshSpiCsPinMuxing, "ISH SPI CS#N Pin Muxing", HEX, + Help "Select ISH SPI CS#N Pin muxing. Refer to GPIO_*_MUXING_ISH_SPIx_CS_* for possible values. N-SPI number, 0-1." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IshGpGpioPadTermination, "ISH GP GPIO Pad termination", HEX, + Help "0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, 0x19: 20kOhm weak pull-up - Enable/disable SerialIo GP#N GPIO pads termination respectively. #N are GP_NUMBER, not strictly relate to indexes of this table. Index 0-23 -> ISH_GP_0-23, Index 24-25 -> ISH_GP_30-31" + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IshUartRxPadTermination, "ISH UART Rx Pad termination", HEX, + Help "0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, 0x19: 20kOhm weak pull-up - Enable/disable SerialIo UART#N Rx pads termination respectively. #N-byte for each controller, byte0 for UART0 Rx, byte1 for UART1 Rx, and so on." + "Valid range: 0x00 ~ 0xFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IshUartTxPadTermination, "ISH UART Tx Pad termination", HEX, + Help "0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, 0x19: 20kOhm weak pull-up - Enable/disable SerialIo UART#N Tx pads termination respectively. #N-byte for each controller, byte0 for UART0 Tx, byte1 for UART1 Tx, and so on." + "Valid range: 0x00 ~ 0xFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IshUartRtsPadTermination, "ISH UART Rts Pad termination", HEX, + Help "0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, 0x19: 20kOhm weak pull-up - Enable/disable SerialIo UART#N Rts pads termination respectively. #N-byte for each controller, byte0 for UART0 Rts, byte1 for UART1 Rts, and so on." + "Valid range: 0x00 ~ 0xFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IshUartCtsPadTermination, "ISH UART Rts Pad termination", HEX, + Help "0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, 0x19: 20kOhm weak pull-up - Enable/disable SerialIo UART#N Cts pads termination respectively. #N-byte for each controller, byte0 for UART0 Cts, byte1 for UART1 Cts, and so on." + "Valid range: 0x00 ~ 0xFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IshI2cSdaPadTermination, "ISH I2C SDA Pad termination", HEX, + Help "0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C#N Sda pads termination respectively. #N-byte for each controller, byte0 for I2C0 Sda, byte1 for I2C1 Sda, and so on." + "Valid range: 0x00 ~ 0xFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IshI2cSclPadTermination, "ISH I2C SCL Pad termination", HEX, + Help "0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C#N Scl pads termination respectively. #N-byte for each controller, byte0 for I2C0 Scl, byte1 for I2C1 Scl, and so on." + "Valid range: 0x00 ~ 0xFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IshSpiMosiPadTermination, "ISH SPI MOSI Pad termination", HEX, + Help "0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, 0x19: 20kOhm weak pull-up - Enable/disable SerialIo SPI#N Mosi pads termination respectively. #N-byte for each controller, byte0 for SPI0 Mosi, byte1 for SPI1 Mosi, and so on." + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IshSpiMisoPadTermination, "ISH SPI MISO Pad termination", HEX, + Help "0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, 0x19: 20kOhm weak pull-up - Enable/disable SerialIo SPI#N Miso pads termination respectively. #N-byte for each controller, byte0 for SPI0 Miso, byte1 for SPI1 Miso, and so on." + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IshSpiClkPadTermination, "ISH SPI CLK Pad termination", HEX, + Help "0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, 0x19: 20kOhm weak pull-up - Enable/disable SerialIo SPI#N Clk pads termination respectively. #N-byte for each controller, byte0 for SPI0 Clk, byte1 for SPI1 Clk, and so on." + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IshSpiCsPadTermination, "ISH SPI CS#N Pad termination", HEX, + Help "0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, 0x19: 20kOhm weak pull-up - Enable/disable SerialIo SPI#N Cs#M pads termination respectively. N*M-byte for each controller, byte0 for SPI0 Cs0, byte1 for SPI1 Cs1, SPI1 Cs0, byte2, SPI1 Cs1, byte3" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchIshSpiCsEnable, "Enable PCH ISH SPI Cs#N pins assigned", HEX, + Help "Set if ISH SPI Cs#N pins are to be enabled by BIOS. 0: Disable; 1: Enable. N-Cs number: 0-1" + "Valid range: 0x0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_Usb2PhyPetxiset, "USB Per Port HS Preemphasis Bias", HEX, + Help "USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV. One byte for each port." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_Usb2PhyTxiset, "USB Per Port HS Transmitter Bias", HEX, + Help "USB Per Port HS Transmitter Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV, One byte for each port." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_Usb2PhyPredeemp, "USB Per Port HS Transmitter Emphasis", HEX, + Help "USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON, 10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_Usb2PhyPehalfbit, "USB Per Port Half Bit Pre-emphasis", HEX, + Help "USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis. One byte for each port." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxDeEmphEnable, "Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment", HEX, + Help "Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment. Each value in arrary can be between 0-1. One byte for each port." + "Valid range: 0x00 ~ 0x01010101010101010101" + EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxDeEmph, "USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting", HEX, + Help "USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16], Default = 29h (approximately -3.5dB De-Emphasis). One byte for each port." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxDownscaleAmpEnable, "Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment", HEX, + Help "Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value in arrary can be between 0-1. One byte for each port." + "Valid range: 0x00 ~ 0x01010101010101010101" + EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxDownscaleAmp, "USB 3.0 TX Output Downscale Amplitude Adjustment", HEX, + Help "USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], Default = 00h. One byte for each port." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PchLanEnable, "Enable LAN", &EN_DIS, + Help "Enable/disable LAN controller." + Combo $gPlatformFspPkgTokenSpaceGuid_PchTsnEnable, "Enable PCH TSN", &EN_DIS, + Help "Enable/disable TSN on the PCH." + Combo $gPlatformFspPkgTokenSpaceGuid_PchTsnLinkSpeed, "TSN Link Speed", &gPlatformFspPkgTokenSpaceGuid_PchTsnLinkSpeed, + Help "Set TSN Link Speed." + EditNum $gPlatformFspPkgTokenSpaceGuid_PchTsnMacAddressHigh, "PCH TSN MAC Address High Bits", HEX, + Help "Set TSN MAC Address High." + "Valid range: 0x0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchTsnMacAddressLow, "PCH TSN MAC Address Low Bits", HEX, + Help "Set TSN MAC Address Low." + "Valid range: 0x0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PciePtm, "PCIe PTM enable/disable", HEX, + Help "Enable/disable Precision Time Measurement for PCIE Root Ports." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieDpc, "PCIe DPC enable/disable", HEX, + Help "Enable/disable Downstream Port Containment for PCIE Root Ports." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieEdpc, "PCIe DPC extensions enable/disable", HEX, + Help "Enable/disable Downstream Port Containment Extensions for PCIE Root Ports." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_UsbPdoProgramming, "USB PDO Programming", &EN_DIS, + Help "Enable/disable PDO programming for USB in PEI phase. Disabling will allow for programming during later phase. 1: enable, 0: disable" + EditNum $gPlatformFspPkgTokenSpaceGuid_PmcPowerButtonDebounce, "Power button debounce configuration", HEX, + Help "Debounce time for PWRBTN in microseconds. For values not supported by HW, they will be rounded down to closest supported on. 0: disable, 250-1024000us: supported range" + "Valid range: 0x00 ~ 0x009C4000" + Combo $gPlatformFspPkgTokenSpaceGuid_PchEspiBmeMasterSlaveEnabled, "PCH eSPI Host and Device BME enabled", &EN_DIS, + Help "PCH eSPI Host and Device BME enabled" + Combo $gPlatformFspPkgTokenSpaceGuid_PchEspiLockLinkConfiguration, "PCH eSPI Link Configuration Lock (SBLCL)", &EN_DIS, + Help "Enable/Disable lock of communication through SET_CONFIG/GET_CONFIG to eSPI slaves addresseses from range 0x0 - 0x7FF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchFivrExtV1p05RailEnabledStates, "Mask to enable the usage of external V1p05 VR rail in specific S0ix or Sx states", HEX, + Help "Enable External V1P05 Rail in: BIT0:S0i1/S0i2, BIT1:S0i3, BIT2:S3, BIT3:S4, BIT4:S5, BIT5:S0" + "Valid range: 0x00 ~ 0x3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchFivrExtV1p05RailSupportedVoltageStates, "Mask to enable the platform configuration of external V1p05 VR rail", HEX, + Help "External V1P05 Rail Supported Configuration" + "Valid range: 0x00 ~ 0x0F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchFivrExtV1p05RailVoltage, "External V1P05 Voltage Value that will be used in S0i2/S0i3 states", HEX, + Help "Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...)" + "Valid range: 0x0 ~ 0x07FF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchFivrExtV1p05RailIccMax, "External V1P05 Icc Max Value", HEX, + Help "Granularity of this setting is 1mA and maximal possible value is 200mA" + "Valid range: 0x0 ~ 0xC8" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchFivrExtVnnRailEnabledStates, "Mask to enable the usage of external Vnn VR rail in specific S0ix or Sx states", HEX, + Help "Enable External Vnn Rail in: BIT0:S0i1/S0i2, BIT1:S0i3, BIT2:S3, BIT3:S4, BIT5:S5" + "Valid range: 0x00 ~ 0x1F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchFivrExtVnnRailSupportedVoltageStates, "Mask to enable the platform configuration of external Vnn VR rail", HEX, + Help "External Vnn Rail Supported Configuration" + "Valid range: 0x00 ~ 0x0F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchFivrExtVnnRailVoltage, "External Vnn Voltage Value that will be used in S0ix/Sx states", HEX, + Help "Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...), Default is set to 420" + "Valid range: 0x0 ~ 0x07FF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchFivrExtVnnRailIccMax, "External Vnn Icc Max Value that will be used in S0ix/Sx states", HEX, + Help "Granularity of this setting is 1mA and maximal possible value is 200mA" + "Valid range: 0x0 ~ 0xC8" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchFivrExtVnnRailSxEnabledStates, "Mask to enable the usage of external Vnn VR rail in Sx states", HEX, + Help "Use only if Ext Vnn Rail config is different in Sx. Enable External Vnn Rail in Sx: BIT0-1:Reserved, BIT2:S3, BIT3:S4, BIT4:S5, BIT5:S0" + "Valid range: 0x00 ~ 0x3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchFivrExtVnnRailSxVoltage, "External Vnn Voltage Value that will be used in Sx states", HEX, + Help "Use only if Ext Vnn Rail config is different in Sx. Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...)" + "Valid range: 0x0 ~ 0x07FF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchFivrExtVnnRailSxIccMax, "External Vnn Icc Max Value that will be used in Sx states", HEX, + Help "Use only if Ext Vnn Rail config is different in Sx. Granularity of this setting is 1mA and maximal possible value is 200mA" + "Valid range: 0x0 ~ 0xC8" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchFivrVccinAuxLowToHighCurModeVolTranTime, "Transition time in microseconds from Low Current Mode Voltage to High Current Mode Voltage", HEX, + Help "This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX to low current mode voltage." + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchFivrVccinAuxRetToHighCurModeVolTranTime, "Transition time in microseconds from Retention Mode Voltage to High Current Mode Voltage", HEX, + Help "This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX to retention mode voltage." + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchFivrVccinAuxRetToLowCurModeVolTranTime, "Transition time in microseconds from Retention Mode Voltage to Low Current Mode Voltage", HEX, + Help "This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX to retention mode voltage." + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchFivrVccinAuxOffToHighCurModeVolTranTime, "Transition time in microseconds from Off (0V) to High Current Mode Voltage", HEX, + Help "This field has 1us resolution. When value is 0 Transition to 0V is disabled." + "Valid range: 0x0 ~ 0x7FF" + Combo $gPlatformFspPkgTokenSpaceGuid_PmcDbgMsgEn, "PMC Debug Message Enable", &EN_DIS, + Help "When Enabled, PMC HW will send debug messages to trace hub; When Disabled, PMC HW will never send debug meesages to trace hub. Noted: When Enabled, may not enter S0ix" + EditNum $gPlatformFspPkgTokenSpaceGuid_ChipsetInitBinPtr, "Pointer of ChipsetInit Binary", HEX, + Help "ChipsetInit Binary Pointer." + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ChipsetInitBinLen, "Length of ChipsetInit Binary", HEX, + Help "ChipsetInit Binary Length." + "Valid range: 0x00 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PchFivrDynPm, "FIVR Dynamic Power Management", &EN_DIS, + Help "Enable/Disable FIVR Dynamic Power Management." + EditNum $gPlatformFspPkgTokenSpaceGuid_PchFivrExtV1p05RailIccMaximum, "External V1P05 Icc Max Value", HEX, + Help "Granularity of this setting is 1mA and maximal possible value is 500mA" + "Valid range: 0x0 ~ 0x1F4" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchFivrExtVnnRailIccMaximum, "External Vnn Icc Max Value that will be used in S0ix/Sx states", HEX, + Help "Granularity of this setting is 1mA and maximal possible value is 500mA" + "Valid range: 0x0 ~ 0x1F4" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchFivrExtVnnRailSxIccMaximum, "External Vnn Icc Max Value that will be used in Sx states", HEX, + Help "Use only if Ext Vnn Rail config is different in Sx. Granularity of this setting is 1mA and maximal possible value is 500mA" + "Valid range: 0x0 ~ 0x1F4" + Combo $gPlatformFspPkgTokenSpaceGuid_PchSpiExtendedBiosDecodeRangeEnable, "Extented BIOS Direct Read Decode enable", &EN_DIS, + Help "Enable/Disable access to bigger than 16MB BIOS Region through Direct Memory Reads. 0: disabled (default), 1: enabled" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchSpiExtendedBiosDecodeRangeBase, "Extended BIOS Direct Read Decode Range base", HEX, + Help "Bits of 31:16 of a memory address that'll be a base for Extended BIOS Direct Read Decode." + "Valid range: 0x0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchSpiExtendedBiosDecodeRangeLimit, "Extended BIOS Direct Read Decode Range limit", HEX, + Help "Bits of 31:16 of a memory address that'll be a limit for Extended BIOS Direct Read Decode." + "Valid range: 0x0 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PchXhciUaolEnable, "USB Audio Offload enable", &EN_DIS, + Help "Enable/Disable USB Audio Offload capabilites. 0: disabled, 1: enabled (default)" + EditNum $gPlatformFspPkgTokenSpaceGuid_SynpsPhyBinPtr, "Pointer of SYNPS PHY Binary", HEX, + Help "ChipsetInit Binary Pointer." + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SynpsPhyBinLen, "Length of SYNPS PHY Binary", HEX, + Help "ChipsetInit Binary Length." + "Valid range: 0x00 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_CnviMode, "CNVi Configuration", &gPlatformFspPkgTokenSpaceGuid_CnviMode, + Help "This option allows for automatic detection of Connectivity Solution. [Auto Detection] assumes that CNVi will be enabled when available, [Disable] allows for disabling CNVi." + Combo $gPlatformFspPkgTokenSpaceGuid_CnviWifiCore, "CNVi Wi-Fi Core", &EN_DIS, + Help "Enable/Disable CNVi Wi-Fi Core, Default is ENABLE. 0: DISABLE, 1: ENABLE" + Combo $gPlatformFspPkgTokenSpaceGuid_CnviBtCore, "CNVi BT Core", &EN_DIS, + Help "Enable/Disable CNVi BT Core, Default is ENABLE. 0: DISABLE, 1: ENABLE" + Combo $gPlatformFspPkgTokenSpaceGuid_CnviBtAudioOffload, "CNVi BT Audio Offload", &EN_DIS, + Help "Enable/Disable BT Audio Offload, Default is DISABLE. 0: DISABLE, 1: ENABLE" + EditNum $gPlatformFspPkgTokenSpaceGuid_CnviRfResetPinMux, "CNVi RF_RESET pin muxing", HEX, + Help "Select CNVi RF_RESET# pin depending on board routing. ADP-P/M: GPP_A8 = 0x2942E408(default) or GPP_F4 = 0x194CE404. ADP-S: 0. Refer to GPIO_*_MUXING_CNVI_RF_RESET_* in GpioPins*.h." + "Valid range: 0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CnviClkreqPinMux, "CNVi CLKREQ pin muxing", HEX, + Help "Select CNVi CLKREQ pin depending on board routing. ADP-P/M: GPP_A9 = 0x3942E609(default) or GPP_F5 = 0x394CE605. ADP-S: 0. Refer to GPIO_*_MUXING_CNVI_CRF_XTAL_CLKREQ_* in GpioPins*.h." + "Valid range: 0 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PchEspiHostC10ReportEnable, "Enable Host C10 reporting through eSPI", &EN_DIS, + Help "Enable/disable Host C10 reporting to Device via eSPI Virtual Wire." + Combo $gPlatformFspPkgTokenSpaceGuid_PmcUsb2PhySusPgEnable, "PCH USB2 PHY Power Gating enable", &EN_DIS, + Help "1: Will enable USB2 PHY SUS Well Power Gating, 0: Will not enable PG of USB2 PHY Sus Well PG" + Combo $gPlatformFspPkgTokenSpaceGuid_PchUsbOverCurrentEnable, "PCH USB OverCurrent mapping enable", &EN_DIS, + Help "1: Will program USB OC pin mapping in xHCI controller memory, 0: Will clear OC pin mapping allow for NOA usage of OC pins" + Combo $gPlatformFspPkgTokenSpaceGuid_PchEspiLgmrEnable, "Espi Lgmr Memory Range decode ", &EN_DIS, + Help "This option enables or disables espi lgmr " + EditNum $gPlatformFspPkgTokenSpaceGuid_PchFivrExtV1p05RailCtrlRampTmr, "External V1P05 Control Ramp Timer value", HEX, + Help "Hold off time to be used when changing the v1p05_ctrl for external bypass value in us" + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchFivrExtVnnRailCtrlRampTmr, "External VNN Control Ramp Timer value", HEX, + Help "Hold off time to be used when changing the vnn_ctrl for external bypass value in us" + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsDevSlpResetConfig, "Set SATA DEVSLP GPIO Reset Config", HEX, + Help "Set SATA DEVSLP GPIO Reset Config per port. 0x00 - GpioResetDefault, 0x01 - GpioResumeReset, 0x03 - GpioHostDeepReset, 0x05 - GpioPlatformReset, 0x07 - GpioDswReset. One byte for each port, byte0 for port0, byte1 for port1, and so on." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PchHotEnable, "PCHHOT# pin", &EN_DIS, + Help "Enable PCHHOT# pin assertion when temperature is higher than PchHotLevel. 0: disable, 1: enable" + Combo $gPlatformFspPkgTokenSpaceGuid_SataLedEnable, "SATA LED", &EN_DIS, + Help "SATA LED indicating SATA controller activity. 0: disable, 1: enable" + Combo $gPlatformFspPkgTokenSpaceGuid_PchPmVrAlert, "VRAlert# Pin", &EN_DIS, + Help "When VRAlert# feature pin is enabled and its state is '0', the PMC requests throttling to a T3 Tstate to the PCH throttling unit.. 0: disable, 1: enable" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpSlotImplemented, "PCH PCIe root port connection type", HEX, + Help "0: built-in device, 1:slot" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpAcsEnabled, "PCIE RP Access Control Services Extended Capability", HEX, + Help "Enable/Disable PCIE RP Access Control Services Extended Capability" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpEnableCpm, "PCIE RP Clock Power Management", HEX, + Help "Enable/Disable PCIE RP Clock Power Management, even if disabled, CLKREQ# signal can still be controlled by L1 PM substates mechanism" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpDetectTimeoutMs, "PCIE RP Detect Timeout Ms", HEX, + Help "The number of milliseconds within 0~65535 in reference code will wait for link to exit Detect state for enabled ports before assuming there is no device and potentially disabling the port." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PmcModPhySusPgEnable, "ModPHY SUS Power Domain Dynamic Gating", &EN_DIS, + Help "Enable/Disable ModPHY SUS Power Domain Dynamic Gating. Setting not supported on PCH-H. 0: disable, 1: enable" + Combo $gPlatformFspPkgTokenSpaceGuid_PmcV1p05PhyExtFetControlEn, "V1p05-PHY supply external FET control", &EN_DIS, + Help "Enable/Disable control using EXT_PWR_GATE# pin of external FET to power gate v1p05-PHY supply. 0: disable, 1: enable" + Combo $gPlatformFspPkgTokenSpaceGuid_PmcV1p05IsExtFetControlEn, "V1p05-IS supply external FET control", &EN_DIS, + Help "Enable/Disable control using EXT_PWR_GATE2# pin of external FET to power gate v1p05-IS supply. 0: disable, 1: enable" + Combo $gPlatformFspPkgTokenSpaceGuid_PchXhciHsiiEnable, "PCH xHCI enable HS Interrupt IN Alarm", &EN_DIS, + Help "PCH xHCI enable HS Interrupt IN Alarm. 0: disabled (default), 1: enabled" + Combo $gPlatformFspPkgTokenSpaceGuid_PchPwrOptEnable, "Enable Power Optimizer", &EN_DIS, + Help "Enable DMI Power Optimizer on PCH side." + EditNum $gPlatformFspPkgTokenSpaceGuid_PchWriteProtectionEnable, "PCH Flash Protection Ranges Write Enble", HEX, + Help "Write or erase is blocked by hardware." + "Valid range: 0x00 ~ 0xFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchReadProtectionEnable, "PCH Flash Protection Ranges Read Enble", HEX, + Help "Read is blocked by hardware." + "Valid range: 0x00 ~ 0xFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchProtectedRangeLimit, "PCH Protect Range Limit", HEX, + Help "Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for limit comparison." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchProtectedRangeBase, "PCH Protect Range Base", HEX, + Help "Left shifted address by 12 bits with address bits 11:0 are assumed to be 0." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaPme, "Enable Pme", &EN_DIS, + Help "Enable Azalia wake-on-ring." + Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaLinkFrequency, "HD Audio Link Frequency", &gPlatformFspPkgTokenSpaceGuid_PchHdaLinkFrequency, + Help "HDA Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 0: 6MHz, 1: 12MHz, 2: 24MHz." + EditNum $gPlatformFspPkgTokenSpaceGuid_PchIshSpiCs0Enable, "Enable PCH ISH SPI Cs0 pins assigned", HEX, + Help "Set if ISH SPI Cs0 pins are to be enabled by BIOS. 0: Disable; 1: Enable." + "Valid range: 0x0 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PchIoApicEntry24_119, "Enable PCH Io Apic Entry 24-119", &EN_DIS, + Help "0: Disable; 1: Enable." + EditNum $gPlatformFspPkgTokenSpaceGuid_PchIoApicId, "PCH Io Apic ID", HEX, + Help "This member determines IOAPIC ID. Default is 0x02." + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchIshSpiEnable, "Enable PCH ISH SPI pins assigned", HEX, + Help "Set if ISH SPI native pins are to be enabled by BIOS. 0: Disable; 1: Enable." + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchIshUartEnable, "Enable PCH ISH UART pins assigned", HEX, + Help "Set if ISH UART native pins are to be enabled by BIOS. 0: Disable; 1: Enable." + "Valid range: 0x0 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchIshI2cEnable, "Enable PCH ISH I2C pins assigned", HEX, + Help "Set if ISH I2C native pins are to be enabled by BIOS. 0: Disable; 1: Enable." + "Valid range: 0x0 ~ 0xFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchIshGpEnable, "Enable PCH ISH GP pins assigned", HEX, + Help "Set if ISH GP native pins are to be enabled by BIOS. 0: Disable; 1: Enable." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PchIshPdtUnlock, "PCH ISH PDT Unlock Msg", &EN_DIS, + Help "0: False; 1: True." + Combo $gPlatformFspPkgTokenSpaceGuid_PchLanLtrEnable, "Enable PCH Lan LTR capabilty of PCH internal LAN", &EN_DIS, + Help "0: Disable; 1: Enable." + Combo $gPlatformFspPkgTokenSpaceGuid_PchLockDownBiosLock, "Enable LOCKDOWN BIOS LOCK", &EN_DIS, + Help "Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region protection." + Combo $gPlatformFspPkgTokenSpaceGuid_PchCrid, "PCH Compatibility Revision ID", &EN_DIS, + Help "This member describes whether or not the CRID feature of PCH should be enabled." + Combo $gPlatformFspPkgTokenSpaceGuid_RtcBiosInterfaceLock, "RTC BIOS Interface Lock", &EN_DIS, + Help "Enable RTC BIOS interface lock. When set, prevents RTC TS (BUC.TS) from being changed." + Combo $gPlatformFspPkgTokenSpaceGuid_RtcMemoryLock, "RTC Cmos Memory Lock", &EN_DIS, + Help "Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper and and lower 128-byte bank of RTC RAM." + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpHotPlug, "Enable PCIE RP HotPlug", HEX, + Help "Indicate whether the root port is hot plug available." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpPmSci, "Enable PCIE RP Pm Sci", HEX, + Help "Indicate whether the root port power manager SCI is enabled." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpTransmitterHalfSwing, "Enable PCIE RP Transmitter Half Swing", HEX, + Help "Indicate whether the Transmitter Half Swing is enabled." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpClkReqDetect, "Enable PCIE RP Clk Req Detect", HEX, + Help "Probe CLKREQ# signal before enabling CLKREQ# based power management." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpAdvancedErrorReporting, "PCIE RP Advanced Error Report", HEX, + Help "Indicate whether the Advanced Error Reporting is enabled." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpUnsupportedRequestReport, "PCIE RP Unsupported Request Report", HEX, + Help "Indicate whether the Unsupported Request Report is enabled." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpFatalErrorReport, "PCIE RP Fatal Error Report", HEX, + Help "Indicate whether the Fatal Error Report is enabled." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpNoFatalErrorReport, "PCIE RP No Fatal Error Report", HEX, + Help "Indicate whether the No Fatal Error Report is enabled." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpCorrectableErrorReport, "PCIE RP Correctable Error Report", HEX, + Help "Indicate whether the Correctable Error Report is enabled." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpSystemErrorOnFatalError, "PCIE RP System Error On Fatal Error", HEX, + Help "Indicate whether the System Error on Fatal Error is enabled." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpSystemErrorOnNonFatalError, "PCIE RP System Error On Non Fatal Error", HEX, + Help "Indicate whether the System Error on Non Fatal Error is enabled." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpSystemErrorOnCorrectableError, "PCIE RP System Error On Correctable Error", HEX, + Help "Indicate whether the System Error on Correctable Error is enabled." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpMaxPayload, "PCIE RP Max Payload", HEX, + Help "Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_ThcPort0Assignment, "Touch Host Controller Port 0 Assignment", &gPlatformFspPkgTokenSpaceGuid_ThcPort0Assignment, + Help "Assign THC Port 0" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcPort0InterruptPinMuxing, "Touch Host Controller Port 0 Interrupt Pin Mux", HEX, + Help "Set THC Port 0 Pin Muxing Value if signal can be enabled on multiple pads. Refer to GPIO_*_MUXING_THC_SPIx_INTB_* for possible values." + "Valid range: 0 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_ThcPort0WakeOnTouch, "Touch Host Controller Port 0 Wake On Touch", &EN_DIS, + Help "Based on this setting vGPIO for given THC will be in native mode, and additional _CRS for wake will be exposed in ACPI" + Combo $gPlatformFspPkgTokenSpaceGuid_ThcPort1Assignment, "Touch Host Controller Port 1 Assignment", &gPlatformFspPkgTokenSpaceGuid_ThcPort1Assignment, + Help "Assign THC Port 1" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcPort1InterruptPinMuxing, "Touch Host Controller Port 1 Interrupt Pin Mux", HEX, + Help "Set THC Port 1 Pin Muxing Value if signal can be enabled on multiple pads. Refer to GPIO_*_MUXING_THC_SPIx_INTB_* for possible values." + "Valid range: 0 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_ThcPort1WakeOnTouch, "Touch Host Controller Port 1 Wake On Touch", &EN_DIS, + Help "Based on this setting vGPIO for given THC will be in native mode, and additional _CRS for wake will be exposed in ACPI" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpPcieSpeed, "PCIE RP Pcie Speed", HEX, + Help "Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3; 4: Gen4 (see: PCIE_SPEED)." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpPhysicalSlotNumber, "PCIE RP Physical Slot Number", HEX, + Help "Indicates the slot number for the root port. Default is the value as root port index." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpCompletionTimeout, "PCIE RP Completion Timeout", HEX, + Help "The root port completion timeout(see: PCIE_COMPLETION_TIMEOUT). Default is PchPcieCompletionTO_Default." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpAspm, "PCIE RP Aspm", HEX, + Help "The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is PchPcieAspmAutoConfig." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpL1Substates, "PCIE RP L1 Substates", HEX, + Help "The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL). Default is PchPcieL1SubstatesL1_1_2." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpL1Low, "PCIE RP L1 Low Substate", HEX, + Help "The L1 Low Substate configuration of the root port. 0: Disable; 1: Enable." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpLtrEnable, "PCIE RP Ltr Enable", HEX, + Help "Latency Tolerance Reporting Mechanism." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpLtrConfigLock, "PCIE RP Ltr Config Lock", HEX, + Help "0: Disable; 1: Enable." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PcieEqOverrideDefault, "PCIe override default settings for EQ", &EN_DIS, + Help "Choose PCIe EQ method" + Combo $gPlatformFspPkgTokenSpaceGuid_PcieEqMethod, "PCIe choose EQ method", &gPlatformFspPkgTokenSpaceGuid_PcieEqMethod, + Help "Choose PCIe EQ method" + Combo $gPlatformFspPkgTokenSpaceGuid_PcieEqMode, "PCIe choose EQ mode", &gPlatformFspPkgTokenSpaceGuid_PcieEqMode, + Help "Choose PCIe EQ mode" + Combo $gPlatformFspPkgTokenSpaceGuid_PcieEqLocalTransmitterOverrideEnable, "PCIe EQ local transmitter override", &EN_DIS, + Help "Enable/Disable local transmitter override" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieEqPh3NumberOfPresetsOrCoefficients, "PCIe number of valid list entries", HEX, + Help "Select number of presets or coefficients depending on the mode" + "Valid range: 0 ~ 11" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieEqPh3PreCursorList, "PCIe pre-cursor coefficient list", HEX, + Help "Provide a list of pre-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0x0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieEqPh3PostCursorList, "PCIe post-cursor coefficient list", HEX, + Help "Provide a list of post-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieEqPh3PresetList, "PCIe preset list", HEX, + Help "Provide a list of presets to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieEqPh1DownstreamPortTransmitterPreset, "PCIe EQ phase 1 downstream transmitter port preset", HEX, + Help "Allows to select the downstream port preset value that will be used during phase 1 of equalization" + "Valid range: 0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieEqPh1UpstreamPortTransmitterPreset, "PCIe EQ phase 1 upstream tranmitter port preset", HEX, + Help "Allows to select the upstream port preset value that will be used during phase 1 of equalization" + "Valid range: 0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieEqPh2LocalTransmitterOverridePreset, "PCIe EQ phase 2 local transmitter override preset", HEX, + Help "Allows to select the value of the preset used during phase 2 local transmitter override" + "Valid range: 0 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PcieEnablePeerMemoryWrite, "PCIE Enable Peer Memory Write", &EN_DIS, + Help "This member describes whether Peer Memory Writes are enabled on the platform." + Combo $gPlatformFspPkgTokenSpaceGuid_PcieComplianceTestMode, "PCIE Compliance Test Mode", &EN_DIS, + Help "Compliance Test Mode shall be enabled when using Compliance Load Board." + Combo $gPlatformFspPkgTokenSpaceGuid_PcieRpFunctionSwap, "PCIE Rp Function Swap", &EN_DIS, + Help "DEPRECATED. Allows BIOS to use root port function number swapping when root port of function 0 is disabled." + Combo $gPlatformFspPkgTokenSpaceGuid_CpuPcieGen3ProgramStaticEq, "Enable/Disable PEG GEN3 Static EQ Phase1 programming", &EN_DIS, + Help "Program Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming" + Combo $gPlatformFspPkgTokenSpaceGuid_CpuPcieGen4ProgramStaticEq, "Enable/Disable GEN4 Static EQ Phase1 programming", &EN_DIS, + Help "Program Gen4 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming" + Combo $gPlatformFspPkgTokenSpaceGuid_PchPmPmeB0S5Dis, "PCH Pm PME_B0_S5_DIS", &EN_DIS, + Help "When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1." + Combo $gPlatformFspPkgTokenSpaceGuid_PcieRpImrEnabled, "PCIE IMR", &EN_DIS, + Help "Enables Isolated Memory Region for PCIe." + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpImrSelection, "PCIE IMR port number", HEX, + Help "Selects PCIE root port number for IMR feature." + "Valid range: 0x0 ~ 23" + Combo $gPlatformFspPkgTokenSpaceGuid_PchPmWolEnableOverride, "PCH Pm Wol Enable Override", &EN_DIS, + Help "Corresponds to the WOL Enable Override bit in the General PM Configuration B (GEN_PMCON_B) register." + Combo $gPlatformFspPkgTokenSpaceGuid_PchPmPcieWakeFromDeepSx, "PCH Pm Pcie Wake From DeepSx", &EN_DIS, + Help "Determine if enable PCIe to wake from deep Sx." + Combo $gPlatformFspPkgTokenSpaceGuid_PchPmWoWlanEnable, "PCH Pm WoW lan Enable", &EN_DIS, + Help "Determine if WLAN wake from Sx, corresponds to the HOST_WLAN_PP_EN bit in the PWRM_CFG3 register." + Combo $gPlatformFspPkgTokenSpaceGuid_PchPmWoWlanDeepSxEnable, "PCH Pm WoW lan DeepSx Enable", &EN_DIS, + Help "Determine if WLAN wake from DeepSx, corresponds to the DSX_WLAN_PP_EN bit in the PWRM_CFG3 register." + Combo $gPlatformFspPkgTokenSpaceGuid_PchPmLanWakeFromDeepSx, "PCH Pm Lan Wake From DeepSx", &EN_DIS, + Help "Determine if enable LAN to wake from deep Sx." + Combo $gPlatformFspPkgTokenSpaceGuid_PchPmDeepSxPol, "PCH Pm Deep Sx Pol", &EN_DIS, + Help "Deep Sx Policy." + EditNum $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS3MinAssert, "PCH Pm Slp S3 Min Assert", HEX, + Help "SLP_S3 Minimum Assertion Width Policy. Default is PchSlpS350ms." + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS4MinAssert, "PCH Pm Slp S4 Min Assert", HEX, + Help "SLP_S4 Minimum Assertion Width Policy. Default is PchSlpS44s." + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchPmSlpSusMinAssert, "PCH Pm Slp Sus Min Assert", HEX, + Help "SLP_SUS Minimum Assertion Width Policy. Default is PchSlpSus4s." + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchPmSlpAMinAssert, "PCH Pm Slp A Min Assert", HEX, + Help "SLP_A Minimum Assertion Width Policy. Default is PchSlpA2s." + "Valid range: 0x0 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PchEnableDbcObs, "USB Overcurrent Override for VISA", &EN_DIS, + Help "This option overrides USB Over Current enablement state that USB OC will be disabled after enabling this option. Enable when VISA pin is muxed with USB OC" + Combo $gPlatformFspPkgTokenSpaceGuid_PchPmSlpStrchSusUp, "PCH Pm Slp Strch Sus Up", &EN_DIS, + Help "Enable SLP_X Stretching After SUS Well Power Up." + Combo $gPlatformFspPkgTokenSpaceGuid_PchPmSlpLanLowDc, "PCH Pm Slp Lan Low Dc", &EN_DIS, + Help "Enable/Disable SLP_LAN# Low on DC Power." + EditNum $gPlatformFspPkgTokenSpaceGuid_PchPmPwrBtnOverridePeriod, "PCH Pm Pwr Btn Override Period", HEX, + Help "PCH power button override period. 000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s." + "Valid range: 0x0 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PchPmDisableDsxAcPresentPulldown, "PCH Pm Disable Dsx Ac Present Pulldown", &EN_DIS, + Help "When Disable, PCH will internal pull down AC_PRESENT in deep SX and during G3 exit." + Combo $gPlatformFspPkgTokenSpaceGuid_PchPmDisableNativePowerButton, "PCH Pm Disable Native Power Button", &EN_DIS, + Help "Power button native mode disable." + Combo $gPlatformFspPkgTokenSpaceGuid_PchPmMeWakeSts, "PCH Pm ME_WAKE_STS", &EN_DIS, + Help "Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register." + Combo $gPlatformFspPkgTokenSpaceGuid_PchPmWolOvrWkSts, "PCH Pm WOL_OVR_WK_STS", &EN_DIS, + Help "Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register." + EditNum $gPlatformFspPkgTokenSpaceGuid_PchPmPwrCycDur, "PCH Pm Reset Power Cycle Duration", HEX, + Help "Could be customized in the unit of second. Please refer to EDS for all support settings. 0 is default, 1 is 1 second, 2 is 2 seconds, ..." + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchPmPciePllSsc, "PCH Pm Pcie Pll Ssc", HEX, + Help "Specifies the Pcie Pll Spread Spectrum Percentage. The default is 0xFF: AUTO - No BIOS override." + "Valid range: 0x0 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PchLegacyIoLowLatency, "PCH Legacy IO Low Latency Enable", &EN_DIS, + Help "Set to enable low latency of legacy IO. 0: Disable, 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_SataPwrOptEnable, "PCH Sata Pwr Opt Enable", &EN_DIS, + Help "SATA Power Optimizer on PCH side." + Combo $gPlatformFspPkgTokenSpaceGuid_EsataSpeedLimit, "PCH Sata eSATA Speed Limit", &EN_DIS, + Help "When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed." + EditNum $gPlatformFspPkgTokenSpaceGuid_SataSpeedLimit, "PCH Sata Speed Limit", HEX, + Help "Indicates the maximum speed the SATA controller can support 0h: PchSataSpeedDefault." + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsHotPlug, "Enable SATA Port HotPlug", HEX, + Help "Enable SATA Port HotPlug." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsInterlockSw, "Enable SATA Port Interlock Sw", HEX, + Help "Enable SATA Port Interlock Sw." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsExternal, "Enable SATA Port External", HEX, + Help "Enable SATA Port External." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsSpinUp, "Enable SATA Port SpinUp", HEX, + Help "Enable the COMRESET initialization Sequence to the device." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsSolidStateDrive, "Enable SATA Port Solid State Drive", HEX, + Help "0: HDD; 1: SSD." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsEnableDitoConfig, "Enable SATA Port Enable Dito Config", HEX, + Help "Enable DEVSLP Idle Timeout settings (DmVal, DitoVal)." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsDmVal, "Enable SATA Port DmVal", HEX, + Help "DITO multiplier. Default is 15." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsDitoVal, "Enable SATA Port DmVal", HEX, + Help "DEVSLP Idle Timeout (DITO), Default is 625." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsZpOdd, "Enable SATA Port ZpOdd", HEX, + Help "Support zero power ODD." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_SataRstRaidDeviceId, "PCH Sata Rst Raid Alternate Id", &EN_DIS, + Help "Enable RAID Alternate ID." + EditNum $gPlatformFspPkgTokenSpaceGuid_SataRstPcieEnable, "PCH Sata Rst Pcie Storage Remap enable", HEX, + Help "Enable Intel RST for PCIe Storage remapping." + "Valid range: 0x00 ~ 0xFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SataRstPcieStoragePort, "PCH Sata Rst Pcie Storage Port", HEX, + Help "Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, 0 = autodetect)." + "Valid range: 0x00 ~ 0xFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SataRstPcieDeviceResetDelay, "PCH Sata Rst Pcie Device Reset Delay", HEX, + Help "PCIe Storage Device Reset Delay in milliseconds. Default value is 100ms" + "Valid range: 0x00 ~ 0xFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_UfsEnable, "UFS enable/disable", &EN_DIS, + Help "PCIe Storage Device Reset Delay in milliseconds. Default value is 100ms" + Combo $gPlatformFspPkgTokenSpaceGuid_IehMode, "IEH Mode", &gPlatformFspPkgTokenSpaceGuid_IehMode, + Help "Integrated Error Handler Mode, 0: Bypass, 1: Enable" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchT0Level, "Thermal Throttling Custimized T0Level Value", HEX, + Help "Custimized T0Level value." + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchT1Level, "Thermal Throttling Custimized T1Level Value", HEX, + Help "Custimized T1Level value." + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchT2Level, "Thermal Throttling Custimized T2Level Value", HEX, + Help "Custimized T2Level value." + "Valid range: 0x00 ~ 0xFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PchTTEnable, "Enable The Thermal Throttle", &EN_DIS, + Help "Enable the thermal throttle function." + Combo $gPlatformFspPkgTokenSpaceGuid_PchTTState13Enable, "PMSync State 13", &EN_DIS, + Help "When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force at least T2 state." + Combo $gPlatformFspPkgTokenSpaceGuid_PchTTLock, "Thermal Throttle Lock", &EN_DIS, + Help "Thermal Throttle Lock." + Combo $gPlatformFspPkgTokenSpaceGuid_TTSuggestedSetting, "Thermal Throttling Suggested Setting", &EN_DIS, + Help "Thermal Throttling Suggested Setting." + Combo $gPlatformFspPkgTokenSpaceGuid_TTCrossThrottling, "Enable PCH Cross Throttling", &EN_DIS, + Help "Enable/Disable PCH Cross Throttling" + Combo $gPlatformFspPkgTokenSpaceGuid_PchDmiTsawEn, "DMI Thermal Sensor Autonomous Width Enable", &EN_DIS, + Help "DMI Thermal Sensor Autonomous Width Enable." + Combo $gPlatformFspPkgTokenSpaceGuid_DmiSuggestedSetting, "DMI Thermal Sensor Suggested Setting", &EN_DIS, + Help "DMT thermal sensor suggested representative values." + Combo $gPlatformFspPkgTokenSpaceGuid_DmiTS0TW, "Thermal Sensor 0 Target Width", &gPlatformFspPkgTokenSpaceGuid_DmiTS0TW, + Help "Thermal Sensor 0 Target Width." + Combo $gPlatformFspPkgTokenSpaceGuid_DmiTS1TW, "Thermal Sensor 1 Target Width", &gPlatformFspPkgTokenSpaceGuid_DmiTS1TW, + Help "Thermal Sensor 1 Target Width." + Combo $gPlatformFspPkgTokenSpaceGuid_DmiTS2TW, "Thermal Sensor 2 Target Width", &gPlatformFspPkgTokenSpaceGuid_DmiTS2TW, + Help "Thermal Sensor 2 Target Width." + Combo $gPlatformFspPkgTokenSpaceGuid_DmiTS3TW, "Thermal Sensor 3 Target Width", &gPlatformFspPkgTokenSpaceGuid_DmiTS3TW, + Help "Thermal Sensor 3 Target Width." + EditNum $gPlatformFspPkgTokenSpaceGuid_SataP0T1M, "Port 0 T1 Multipler", HEX, + Help "Port 0 T1 Multipler." + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SataP0T2M, "Port 0 T2 Multipler", HEX, + Help "Port 0 T2 Multipler." + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SataP0T3M, "Port 0 T3 Multipler", HEX, + Help "Port 0 T3 Multipler." + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SataP0TDisp, "Port 0 Tdispatch", HEX, + Help "Port 0 Tdispatch." + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SataP1T1M, "Port 1 T1 Multipler", HEX, + Help "Port 1 T1 Multipler." + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SataP1T2M, "Port 1 T2 Multipler", HEX, + Help "Port 1 T2 Multipler." + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SataP1T3M, "Port 1 T3 Multipler", HEX, + Help "Port 1 T3 Multipler." + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SataP1TDisp, "Port 1 Tdispatch", HEX, + Help "Port 1 Tdispatch." + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SataP0Tinact, "Port 0 Tinactive", HEX, + Help "Port 0 Tinactive." + "Valid range: 0x00 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_SataP0TDispFinit, "Port 0 Alternate Fast Init Tdispatch", &EN_DIS, + Help "Port 0 Alternate Fast Init Tdispatch." + EditNum $gPlatformFspPkgTokenSpaceGuid_SataP1Tinact, "Port 1 Tinactive", HEX, + Help "Port 1 Tinactive." + "Valid range: 0x00 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_SataP1TDispFinit, "Port 1 Alternate Fast Init Tdispatch", &EN_DIS, + Help "Port 1 Alternate Fast Init Tdispatch." + Combo $gPlatformFspPkgTokenSpaceGuid_SataThermalSuggestedSetting, "Sata Thermal Throttling Suggested Setting", &EN_DIS, + Help "Sata Thermal Throttling Suggested Setting." + Combo $gPlatformFspPkgTokenSpaceGuid_PchMemoryThrottlingEnable, "Enable Memory Thermal Throttling", &EN_DIS, + Help "Enable Memory Thermal Throttling." + EditNum $gPlatformFspPkgTokenSpaceGuid_PchMemoryPmsyncEnable, "Memory Thermal Throttling", HEX, + Help "Enable Memory Thermal Throttling." + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchMemoryC0TransmitEnable, "Enable Memory Thermal Throttling", HEX, + Help "Enable Memory Thermal Throttling." + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchMemoryPinSelection, "Enable Memory Thermal Throttling", HEX, + Help "Enable Memory Thermal Throttling." + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchTemperatureHotLevel, "Thermal Device Temperature", HEX, + Help "Decides the temperature." + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_Usb2OverCurrentPin, "USB2 Port Over Current Pin", HEX, + Help "Describe the specific over current pin number of USB 2.0 Port N." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3OverCurrentPin, "USB3 Port Over Current Pin", HEX, + Help "Describe the specific over current pin number of USB 3.0 Port N." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PchUsbLtrOverrideEnable, "Enable xHCI LTR override", &EN_DIS, + Help "Enables override of recommended LTR values for xHCI" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcMode, "Touch Host Controller Mode", HEX, + Help "Switch between Intel THC protocol and Industry standard HID Over SPI protocol. 0x0:Thc, 0x1:Hid" + "Valid range: 0 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchUsbLtrHighIdleTimeOverride, "xHCI High Idle Time LTR override", HEX, + Help "Value used for overriding LTR recommendation for xHCI High Idle Time LTR setting" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchUsbLtrMediumIdleTimeOverride, "xHCI Medium Idle Time LTR override", HEX, + Help "Value used for overriding LTR recommendation for xHCI Medium Idle Time LTR setting" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchUsbLtrLowIdleTimeOverride, "xHCI Low Idle Time LTR override", HEX, + Help "Value used for overriding LTR recommendation for xHCI Low Idle Time LTR setting" + "Valid range: 0x00 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_Enable8254ClockGating, "Enable 8254 Static Clock Gating", &EN_DIS, + Help "Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support legacy OS using 8254 timer. Also enable this while S0ix is enabled." + Combo $gPlatformFspPkgTokenSpaceGuid_Enable8254ClockGatingOnS3, "Enable 8254 Static Clock Gating On S3", &EN_DIS, + Help "This is only applicable when Enable8254ClockGating is disabled. FSP will do the 8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This avoids the SMI requirement for the programming." + Combo $gPlatformFspPkgTokenSpaceGuid_EnableTcoTimer, "Enable TCO timer.", &EN_DIS, + Help "When FALSE, it disables PCH ACPI timer, and stops TCO timer. NOTE: This will have huge power impact when it's enabled. If TCO timer is disabled, uCode ACPI timer emulation must be enabled, and WDAT table must not be exposed to the OS." + Combo $gPlatformFspPkgTokenSpaceGuid_HybridStorageMode, "Hybrid Storage Detection and Configuration Mode", &gPlatformFspPkgTokenSpaceGuid_HybridStorageMode, + Help "Enables support for Hybrid storage devices. 0: Disabled; 1: Dynamic Configuration. Default is 0: Disabled" + EditNum $gPlatformFspPkgTokenSpaceGuid_CpuRootportUsedForHybridStorage, "CPU Root Port used for Hybrid Storage", HEX, + Help "Specifies the CPU root port used for Hybrid storage." + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchRootportUsedForCpuAttach, "PCH Root Port used for Hybrid Storage when two lanes are connected to CPU", HEX, + Help "Specifies PCH Root Port used for Hybrid Storage when two lanes are connected to CPU." + "Valid range: 0x0 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PchAcpiL6dPmeHandling, "PCH GPE event handler", &EN_DIS, + Help "Enabled _L6D ACPI handler. PME GPE is shared by multiple devices So BIOS must verify the same in the ASL handler by reading offset for PMEENABLE and PMESTATUS bit" + Combo $gPlatformFspPkgTokenSpaceGuid_PsOnEnable, "Enable PS_ON.", &EN_DIS, + Help "PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power target that will be required by the California Energy Commission (CEC). When FALSE, PS_ON is to be disabled." + Combo $gPlatformFspPkgTokenSpaceGuid_PmcCpuC10GatePinEnable, "Pmc Cpu C10 Gate Pin Enable", &EN_DIS, + Help "Enable/Disable platform support for CPU_C10_GATE# pin to control gating of CPU VccIO and VccSTG rails instead of SLP_S0# pin." + Combo $gPlatformFspPkgTokenSpaceGuid_PchDmiAspmCtrl, "Pch Dmi Aspm Ctrl", &gPlatformFspPkgTokenSpaceGuid_PchDmiAspmCtrl, + Help "ASPM configuration on the PCH side of the DMI/OPI Link. Default is PchPcieAspmL1" + Combo $gPlatformFspPkgTokenSpaceGuid_PchDmiCwbEnable, "PchDmiCwbEnable", &EN_DIS, + Help "Central Write Buffer feature configurable and enabled by default" + Combo $gPlatformFspPkgTokenSpaceGuid_PmcOsIdleEnable, "OS IDLE Mode Enable", &EN_DIS, + Help "Enable/Disable OS Idle Mode" + Combo $gPlatformFspPkgTokenSpaceGuid_PchS0ixAutoDemotion, "S0ix Auto-Demotion", &EN_DIS, + Help "Enable/Disable the Low Power Mode Auto-Demotion Host Control feature." + Combo $gPlatformFspPkgTokenSpaceGuid_PchPmLatchEventsC10Exit, "Latch Events C10 Exit", &EN_DIS, + Help "When this bit is set to 1, SLP_S0# entry events in SLP_S0_DEBUG_REGx registers are captured on C10 exit (instead of C10 entry which is default)" + Combo $gPlatformFspPkgTokenSpaceGuid_PmcAdrEn, "PMC ADR enable", &EN_DIS, + Help "Enable/disable asynchronous DRAM refresh" + Combo $gPlatformFspPkgTokenSpaceGuid_PmcAdrTimerEn, "PMC ADR timer configuration enable", &EN_DIS, + Help "Enable/disable ADR timer configuration" + EditNum $gPlatformFspPkgTokenSpaceGuid_PmcAdrTimer1Val, "PMC ADR phase 1 timer value", HEX, + Help "Enable/disable ADR timer configuration" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PmcAdrMultiplier1Val, "PMC ADR phase 1 timer multiplier value", HEX, + Help "Specify the multiplier value for phase 1 ADR timer" + "Valid range: 0x00 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PmcAdrHostPartitionReset, "PMC ADR host reset partition enable", &EN_DIS, + Help "Specify whether PMC should set ADR_RST_STS bit after receiving Reset_Warn_Ack DMI message" + Combo $gPlatformFspPkgTokenSpaceGuid_PmcAdrSrcOverride, "PMC ADR source select override enable", &EN_DIS, + Help "Tells the FSP to update the source select with platform value" + EditNum $gPlatformFspPkgTokenSpaceGuid_PmcAdrSrcSel, "PMC ADR source selection", HEX, + Help "Specify which sources should cause ADR flow" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CpuPcieEqPh3LaneParamCm, "PCIE Eq Ph3 Lane Param Cm", HEX, + Help "CPU_PCIE_EQ_LANE_PARAM. Coefficient C-1." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CpuPcieEqPh3LaneParamCp, "PCIE Eq Ph3 Lane Param Cp", HEX, + Help "CPU_PCIE_EQ_LANE_PARAM. Coefficient C+1." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CpuPcieGen3RootPortPreset, "Gen3 Root port preset values per lane", HEX, + Help "Used for programming Pcie Gen3 preset values per lane. Range: 0-9, 8 is default for each lane" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CpuPcieGen4RootPortPreset, "Pcie Gen4 Root port preset values per lane", HEX, + Help "Used for programming Pcie Gen4 preset values per lane. Range: 0-9, 8 is default for each lane" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CpuPcieGen3EndPointPreset, "Pcie Gen3 End port preset values per lane", HEX, + Help "Used for programming Pcie Gen3 preset values per lane. Range: 0-9, 7 is default for each lane" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CpuPcieGen4EndPointPreset, "Pcie Gen4 End port preset values per lane", HEX, + Help "Used for programming Pcie Gen4 preset values per lane. Range: 0-9, 7 is default for each lane" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CpuPcieGen3EndPointHint, "Pcie Gen3 End port Hint values per lane", HEX, + Help "Used for programming Pcie Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CpuPcieGen4EndPointHint, "Pcie Gen4 End port Hint values per lane", HEX, + Help "Used for programming Pcie Gen4 Hint values per lane. Range: 0-6, 2 is default for each lane" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_CpuPcieFiaProgramming, "CPU PCIe Fia Programming", &EN_DIS, + Help "Load Fia configuration if enable. 0: Disable; 1: Enable(Default)." + Combo $gPlatformFspPkgTokenSpaceGuid_CpuPcieClockGating, "CPU PCIe RootPort Clock Gating", &EN_DIS, + Help "Describes whether the PCI Express Clock Gating for each root port is enabled by platform modules. 0: Disable; 1: Enable(Default)." + Combo $gPlatformFspPkgTokenSpaceGuid_CpuPciePowerGating, "CPU PCIe RootPort Power Gating", &EN_DIS, + Help "Describes whether the PCI Express Power Gating for each root port is enabled by platform modules. 0: Disable; 1: Enable(Default)." + Combo $gPlatformFspPkgTokenSpaceGuid_CpuPcieComplianceTestMode, "PCIE Compliance Test Mode", &EN_DIS, + Help "Compliance Test Mode shall be enabled when using Compliance Load Board." + Combo $gPlatformFspPkgTokenSpaceGuid_CpuPcieEnablePeerMemoryWrite, "PCIE Enable Peer Memory Write", &EN_DIS, + Help "This member describes whether Peer Memory Writes are enabled on the platform." + Combo $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpFunctionSwap, "PCIE Rp Function Swap", &EN_DIS, + Help "Allows BIOS to use root port function number swapping when root port of function 0 is disabled." + Combo $gPlatformFspPkgTokenSpaceGuid_CpuPcieSlotSelection, "PCI Express Slot Selection", &EN_DIS, + Help "Select the PCIe M2 or CEMx4 slot.0: CEMx4 slot; 1: M2 slot(Default)." + EditNum $gPlatformFspPkgTokenSpaceGuid_CpuPcieDeviceOverrideTablePtr, "CPU PCIE device override table pointer", HEX, + Help "The PCIe device table is being used to override PCIe device ASPM settings. This is a pointer points to a 32bit address. And it's only used in PostMem phase. Please refer to CPU_PCIE_DEVICE_OVERRIDE structure for the table. Last entry VendorId must be 0." + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpHotPlug, "Enable PCIE RP HotPlug", HEX, + Help "Indicate whether the root port is hot plug available." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpPmSci, "Enable PCIE RP Pm Sci", HEX, + Help "Indicate whether the root port power manager SCI is enabled." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpTransmitterHalfSwing, "Enable PCIE RP Transmitter Half Swing", HEX, + Help "Indicate whether the Transmitter Half Swing is enabled." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpAcsEnabled, "PCIE RP Access Control Services Extended Capability", HEX, + Help "Enable/Disable PCIE RP Access Control Services Extended Capability" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpEnableCpm, "PCIE RP Clock Power Management", HEX, + Help "Enable/Disable PCIE RP Clock Power Management, even if disabled, CLKREQ# signal can still be controlled by L1 PM substates mechanism" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpAdvancedErrorReporting, "PCIE RP Advanced Error Report", HEX, + Help "Indicate whether the Advanced Error Reporting is enabled." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpUnsupportedRequestReport, "PCIE RP Unsupported Request Report", HEX, + Help "Indicate whether the Unsupported Request Report is enabled." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpFatalErrorReport, "PCIE RP Fatal Error Report", HEX, + Help "Indicate whether the Fatal Error Report is enabled." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpNoFatalErrorReport, "PCIE RP No Fatal Error Report", HEX, + Help "Indicate whether the No Fatal Error Report is enabled." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpCorrectableErrorReport, "PCIE RP Correctable Error Report", HEX, + Help "Indicate whether the Correctable Error Report is enabled." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpSystemErrorOnFatalError, "PCIE RP System Error On Fatal Error", HEX, + Help "Indicate whether the System Error on Fatal Error is enabled." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpSystemErrorOnNonFatalError, "PCIE RP System Error On Non Fatal Error", HEX, + Help "Indicate whether the System Error on Non Fatal Error is enabled." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpSystemErrorOnCorrectableError, "PCIE RP System Error On Correctable Error", HEX, + Help "Indicate whether the System Error on Correctable Error is enabled." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpMaxPayload, "PCIE RP Max Payload", HEX, + Help "Max Payload Size supported, Default 128B, see enum CPU_PCIE_MAX_PAYLOAD." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpDpcEnabled, "DPC for PCIE RP Mask", HEX, + Help "Enable/disable Downstream Port Containment for PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 for port1, bit1 for port2, and so on." + "Valid range: 0x00 ~ 0x00FFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpDpcExtensionsEnabled, "DPC Extensions PCIE RP Mask", HEX, + Help "Enable/disable DPC Extensions for PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 for port1, bit1 for port2, and so on." + "Valid range: 0x00 ~ 0x00FFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpSlotImplemented, "CPU PCIe root port connection type", HEX, + Help "0: built-in device, 1:slot" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpGen3EqPh3Method, "PCIE RP Gen3 Equalization Phase Method", HEX, + Help "PCIe Gen3 Eq Ph3 Method (see CPU_PCIE_EQ_METHOD). 0: DEPRECATED, hardware equalization; 1: hardware equalization; 4: Fixed Coeficients." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpGen4EqPh3Method, "PCIE RP Gen4 Equalization Phase Method", HEX, + Help "PCIe Gen4 Eq Ph3 Method (see CPU_PCIE_EQ_METHOD). 0: DEPRECATED, hardware equalization; 1: hardware equalization; 4: Fixed Coeficients." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpPhysicalSlotNumber, "PCIE RP Physical Slot Number", HEX, + Help "Indicates the slot number for the root port. Default is the value as root port index." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpAspm, "PCIE RP Aspm", HEX, + Help "The ASPM configuration of the root port (see: CPU_PCIE_ASPM_CONTROL).0: Disable; 1: CpuPcieAspmL0s; 2: CpuPcieAspmL1; 3:CpuPcieAspmL0sL1(Default)" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpL1Substates, "PCIE RP L1 Substates", HEX, + Help "The L1 Substates configuration of the root port (see: CPU_PCIE_L1SUBSTATES_CONTROL). Default is CpuPcieL1SubstatesL1_1_2." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpLtrEnable, "PCIE RP Ltr Enable", HEX, + Help "Latency Tolerance Reporting Mechanism." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpLtrConfigLock, "PCIE RP Ltr Config Lock", HEX, + Help "0: Disable; 1: Enable." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpPtmEnabled, "PTM for PCIE RP Mask", HEX, + Help "Enable/disable Precision Time Measurement for PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 for port1, bit1 for port2, and so on." + "Valid range: 0x00 ~ 0x00FFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpDetectTimeoutMs, "PCIE RP Detect Timeout Ms", HEX, + Help "The number of milliseconds within 0~65535 in reference code will wait for link to exit Detect state for enabled ports before assuming there is no device and potentially disabling the port." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CpuPcieRpMultiVcEnabled, "Multi-VC for PCIE RP Mask", HEX, + Help "Enable/disable Multiple Virtual Channel for PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 for port1, bit1 for port2, and so on." + "Valid range: 0x00 ~ 0x00FFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate3UniqTranEnable, "Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3", HEX, + Help "Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3, Each value in array can be between 0-1. One byte for each port." + "Valid range: 0x00 ~ 0x01010101010101010101" + EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate3UniqTran, "USB 3.0 TX Output Unique Transition Bit Scale for rate 3", HEX, + Help "USB 3.0 TX Output Unique Transition Bit Scale for rate 3, HSIO_TX_DWORD9[6:0], Default = 4Ch. One byte for each port." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate2UniqTranEnable, "Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2", HEX, + Help "Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2, Each value in array can be between 0-1. One byte for each port." + "Valid range: 0x00 ~ 0x01010101010101010101" + EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate2UniqTran, "USB 3.0 TX Output Unique Transition Bit Scale for rate 2", HEX, + Help "USB 3.0 TX Output Unique Transition Bit Scale for rate 2, HSIO_TX_DWORD9[14:8], Default = 4Ch. One byte for each port." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate1UniqTranEnable, "Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1", HEX, + Help "Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1, Each value in array can be between 0-1. One byte for each port." + "Valid range: 0x00 ~ 0x01010101010101010101" + EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate1UniqTran, "USB 3.0 TX Output Unique Transition Bit Scale for rate 1", HEX, + Help "USB 3.0 TX Output Unique Transition Bit Scale for rate 1, HSIO_TX_DWORD9[22:16], Default = 4Ch. One byte for each port." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate0UniqTranEnable, "Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0", HEX, + Help "Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0, Each value in array can be between 0-1. One byte for each port." + "Valid range: 0x00 ~ 0x01010101010101010101" + EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate0UniqTran, "USB 3.0 TX Output Unique Transition Bit Scale for rate 0", HEX, + Help "USB 3.0 TX Output Unique Transition Bit Scale for rate 0, HSIO_TX_DWORD9[30:24], Default = 4Ch. One byte for each port." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PchLockDownGlobalSmi, "Enable LOCKDOWN SMI", &EN_DIS, + Help "Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit." + Combo $gPlatformFspPkgTokenSpaceGuid_PchLockDownBiosInterface, "Enable LOCKDOWN BIOS Interface", &EN_DIS, + Help "Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register." + Combo $gPlatformFspPkgTokenSpaceGuid_PchUnlockGpioPads, "Unlock all GPIO pads", &EN_DIS, + Help "Force all GPIO pads to be unlocked for debug purpose." + Combo $gPlatformFspPkgTokenSpaceGuid_PchSbAccessUnlock, "PCH Unlock SideBand access", &EN_DIS, + Help "The SideBand PortID mask for certain end point (e.g. PSFx) will be locked before 3rd party code execution. 0: Lock SideBand access; 1: Unlock SideBand access." + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpLtrMaxSnoopLatency, "PCIE RP Ltr Max Snoop Latency", HEX, + Help "Latency Tolerance Reporting, Max Snoop Latency." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpLtrMaxNoSnoopLatency, "PCIE RP Ltr Max No Snoop Latency", HEX, + Help "Latency Tolerance Reporting, Max Non-Snoop Latency." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpSnoopLatencyOverrideMode, "PCIE RP Snoop Latency Override Mode", HEX, + Help "Latency Tolerance Reporting, Snoop Latency Override Mode." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpSnoopLatencyOverrideMultiplier, "PCIE RP Snoop Latency Override Multiplier", HEX, + Help "Latency Tolerance Reporting, Snoop Latency Override Multiplier." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpSnoopLatencyOverrideValue, "PCIE RP Snoop Latency Override Value", HEX, + Help "Latency Tolerance Reporting, Snoop Latency Override Value." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpNonSnoopLatencyOverrideMode, "PCIE RP Non Snoop Latency Override Mode", HEX, + Help "Latency Tolerance Reporting, Non-Snoop Latency Override Mode." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpNonSnoopLatencyOverrideMultiplier, "PCIE RP Non Snoop Latency Override Multiplier", HEX, + Help "Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpNonSnoopLatencyOverrideValue, "PCIE RP Non Snoop Latency Override Value", HEX, + Help "Latency Tolerance Reporting, Non-Snoop Latency Override Value." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpSlotPowerLimitScale, "PCIE RP Slot Power Limit Scale", HEX, + Help "Specifies scale used for slot power limit value. Leave as 0 to set to default." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpSlotPowerLimitValue, "PCIE RP Slot Power Limit Value", HEX, + Help "Specifies upper limit on power supplie by slot. Leave as 0 to set to default." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PcieEnablePort8xhDecode, "PCIE RP Enable Port8xh Decode", &EN_DIS, + Help "This member describes whether PCIE root port Port 8xh Decode is enabled. 0: Disable; 1: Enable." + EditNum $gPlatformFspPkgTokenSpaceGuid_PchPciePort8xhDecodePortIndex, "PCIE Port8xh Decode Port Index", HEX, + Help "The Index of PCIe Port that is selected for Port8xh Decode (0 Based)." + "Valid range: 0x0 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PchPmDisableEnergyReport, "PCH Energy Reporting", &EN_DIS, + Help "Disable/Enable PCH to CPU energy report feature." + Combo $gPlatformFspPkgTokenSpaceGuid_SataTestMode, "PCH Sata Test Mode", &EN_DIS, + Help "Allow entrance to the PCH SATA test modes." + Combo $gPlatformFspPkgTokenSpaceGuid_PchXhciOcLock, "PCH USB OverCurrent mapping lock enable", &EN_DIS, + Help "If this policy option is enabled then BIOS will program OCCFDONE bit in xHCI meaning that OC mapping data will be consumed by xHCI and OC mapping registers will be locked." + EditNum $gPlatformFspPkgTokenSpaceGuid_PmcLpmS0ixSubStateEnableMask, "Low Power Mode Enable/Disable config mask", HEX, + Help "Configure if respective S0i2/3 sub-states are to be supported. Each bit corresponds to one sub-state (LPMx - BITx): LPM0-s0i2.0, LPM1-s0i2.1, LPM2-s0i2.2, LPM3-s0i3.0, LPM4-s0i3.1, LPM5-s0i3.2, LPM6-s0i3.3, LPM7-s0i3.4." + "Valid range: 0x00 ~ 0xFF" +EndPage + +Page "USB-C/Thunderbolt (Pre-Mem)" + Combo $gPlatformFspPkgTokenSpaceGuid_PcieMultipleSegmentEnabled, "iTBT PCIe Multiple Segment setting", &EN_DIS, + Help "DEPRECATED" + Combo $gPlatformFspPkgTokenSpaceGuid_TcssItbtPcie0En, "TCSS Thunderbolt PCIE Root Port 0 Enable", &EN_DIS, + Help "Set TCSS Thunderbolt PCIE Root Port 0. 0:Disabled 1:Enabled" + Combo $gPlatformFspPkgTokenSpaceGuid_TcssItbtPcie1En, "TCSS Thunderbolt PCIE Root Port 1 Enable", &EN_DIS, + Help "Set TCSS Thunderbolt PCIE Root Port 1. 0:Disabled 1:Enabled" + Combo $gPlatformFspPkgTokenSpaceGuid_TcssItbtPcie2En, "TCSS Thunderbolt PCIE Root Port 2 Enable", &EN_DIS, + Help "Set TCSS Thunderbolt PCIE Root Port 2. 0:Disabled 1:Enabled" + Combo $gPlatformFspPkgTokenSpaceGuid_TcssItbtPcie3En, "TCSS Thunderbolt PCIE Root Port 3 Enable", &EN_DIS, + Help "Set TCSS Thunderbolt PCIE Root Port 3. 0:Disabled 1:Enabled" + Combo $gPlatformFspPkgTokenSpaceGuid_TcssXhciEn, "TCSS USB HOST (xHCI) Enable", &EN_DIS, + Help "Set TCSS XHCI. 0:Disabled 1:Enabled - Must be enabled if xDCI is enabled below" + Combo $gPlatformFspPkgTokenSpaceGuid_TcssXdciEn, "TCSS USB DEVICE (xDCI) Enable", &EN_DIS, + Help "Set TCSS XDCI. 0:Disabled 1:Enabled - xHCI must be enabled if xDCI is enabled" + Combo $gPlatformFspPkgTokenSpaceGuid_TcssDma0En, "TCSS DMA0 Enable", &EN_DIS, + Help "Set TCSS DMA0. 0:Disabled 1:Enabled" + Combo $gPlatformFspPkgTokenSpaceGuid_TcssDma1En, "TCSS DMA1 Enable", &EN_DIS, + Help "Set TCSS DMA1. 0:Disabled 1:Enabled" + EditNum $gPlatformFspPkgTokenSpaceGuid_UsbTcPortEnPreMem, "TCSS USB Port Enable", HEX, + Help "Bitmap for per port enabling" + "Valid range: 0x0 ~ 0x000F" +EndPage + +Page "USB-C/Thunderbolt (Post-Mem)" + Combo $gPlatformFspPkgTokenSpaceGuid_D3HotEnable, "Enable D3 Hot in TCSS ", &EN_DIS, + Help "This policy will enable/disable D3 hot support in IOM" + EditNum $gPlatformFspPkgTokenSpaceGuid_IomTypeCPortPadCfg, "TypeC port GPIO setting", HEX, + Help "GPIO Ping number for Type C Aux Oritation setting, use the GpioPad that is defined in GpioPinsXXXH.h and GpioPinsXXXLp.h as argument.(XXX is platform name, Ex: Adl = AlderLake)" + "Valid range: 0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CpuUsb3OverCurrentPin, "CPU USB3 Port Over Current Pin", HEX, + Help "Describe the specific over current pin number of USBC Port N." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_D3ColdEnable, "Enable D3 Cold in TCSS ", &EN_DIS, + Help "This policy will enable/disable D3 cold support in IOM" + Combo $gPlatformFspPkgTokenSpaceGuid_ITbtPcieTunnelingForUsb4, "Enable/Disable PCIe tunneling for USB4", &EN_DIS, + Help "Enable/Disable PCIe tunneling for USB4, default is enable" + EditNum $gPlatformFspPkgTokenSpaceGuid_TcCstateLimit, "TC State in TCSS ", HEX, + Help "This TC C-State Limit in IOM" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_VbtSize, "Intel Graphics VBT (Video BIOS Table) Size", HEX, + Help "Size of Internal Graphics VBT Image" + "Valid range: 0x0 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_LidStatus, "Platform LID Status for LFP Displays.", &gPlatformFspPkgTokenSpaceGuid_LidStatus, + Help "LFP Display Lid Status (LID_STATUS enum): 0 (Default): LidClosed, 1: LidOpen." + EditNum $gPlatformFspPkgTokenSpaceGuid_IomStayInTCColdSeconds, "Set Iom stay in TC cold seconds in TCSS ", HEX, + Help "Set Iom stay in TC cold seconds in IOM" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IomBeforeEnteringTCColdSeconds, "Set Iom before entering TC cold seconds in TCSS ", HEX, + Help "Set Iom before entering TC cold seconds in IOM" + "Valid range: 0x00 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_VmdEnable, "Enable VMD controller", &EN_DIS, + Help "Enable/disable to VMD controller.0: Disable; 1: Enable(Default)" + Combo $gPlatformFspPkgTokenSpaceGuid_VmdPort, "Map port under VMD", &EN_DIS, + Help "Map/UnMap port under VMD" + EditNum $gPlatformFspPkgTokenSpaceGuid_VmdPortDev, "VMD Port Device", DEC, + Help "VMD Root port device number." + "Valid range: 0 ~ 31" + EditNum $gPlatformFspPkgTokenSpaceGuid_VmdPortFunc, "VMD Port Func", DEC, + Help "VMD Root port function number." + "Valid range: 0 ~ 7" + EditNum $gPlatformFspPkgTokenSpaceGuid_VmdCfgBarSize, "VMD Config Bar size", DEC, + Help "Set The VMD Config Bar Size." + "Valid range: 20 ~ 28" + Combo $gPlatformFspPkgTokenSpaceGuid_VmdCfgBarAttr, "VMD Config Bar Attributes", &gPlatformFspPkgTokenSpaceGuid_VmdCfgBarAttr, + Help "0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_NONPREFETCH(Default), 2: VMD_64BIT_PREFETCH" + EditNum $gPlatformFspPkgTokenSpaceGuid_VmdMemBarSize1, "VMD Mem Bar1 size", DEC, + Help "Set The VMD Mem Bar1 Size." + "Valid range: 12 ~ 47" + Combo $gPlatformFspPkgTokenSpaceGuid_VmdMemBar1Attr, "VMD Mem Bar1 Attributes", &gPlatformFspPkgTokenSpaceGuid_VmdMemBar1Attr, + Help "0: VMD_32BIT_NONPREFETCH(Default), 1: VMD_64BIT_NONPREFETCH, 2: VMD_64BIT_PREFETCH" + EditNum $gPlatformFspPkgTokenSpaceGuid_VmdMemBarSize2, "VMD Mem Bar2 size", DEC, + Help "Set The VMD Mem Bar2 Size." + "Valid range: 12 ~ 47" + Combo $gPlatformFspPkgTokenSpaceGuid_VmdMemBar2Attr, "VMD Mem Bar2 Attributes", &gPlatformFspPkgTokenSpaceGuid_VmdMemBar2Attr, + Help "0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_NONPREFETCH(Default), 2: VMD_64BIT_PREFETCH" + EditNum $gPlatformFspPkgTokenSpaceGuid_VmdVariablePtr, "VMD Variable", HEX, + Help "VMD Variable Pointer." + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_VmdCfgBarBase, "Temporary CfgBar address for VMD", HEX, + Help "VMD Variable Pointer." + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_VmdMemBar1Base, "Temporary MemBar1 address for VMD", HEX, + Help "VMD Variable Pointer." + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_VmdMemBar2Base, "Temporary MemBar2 address for VMD", HEX, + Help "VMD Variable Pointer." + "Valid range: 0x00 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_TcssCpuUsbPdoProgramming, "TCSS CPU USB PDO Programming", &EN_DIS, + Help "Enable/disable PDO programming for TCSS CPU USB in PEI phase. Disabling will allow for programming during later phase. 1: enable, 0: disable" + Combo $gPlatformFspPkgTokenSpaceGuid_PmcPdEnable, "Enable/Disable PMC-PD Solution ", &EN_DIS, + Help "This policy will enable/disable PMC-PD Solution vs EC-TCPC Solution" + EditNum $gPlatformFspPkgTokenSpaceGuid_TcssAuxOri, "TCSS Aux Orientation Override Enable", HEX, + Help "Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides" + "Valid range: 0x0 ~ 0x0FFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_TcssHslOri, "TCSS HSL Orientation Override Enable", HEX, + Help "Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides" + "Valid range: 0x0 ~ 0x0FFF" + Combo $gPlatformFspPkgTokenSpaceGuid_UsbOverride, "USB override in IOM ", &EN_DIS, + Help "This policy will enable/disable USB Connect override in IOM" + EditNum $gPlatformFspPkgTokenSpaceGuid_ITbtPcieRootPortEn, "ITBT Root Port Enable", HEX, + Help "ITBT Root Port Enable, 0:Disable, 1:Enable" + "Valid range: 0x00 ~ 0xFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_UsbTcPortEn, "TCSS USB Port Enable", HEX, + Help "Bits 0, 1, ... max Type C port control enables" + "Valid range: 0x0 ~ 0x000F" + EditNum $gPlatformFspPkgTokenSpaceGuid_ITbtForcePowerOnTimeoutInMs, "ITBTForcePowerOn Timeout value", HEX, + Help "ITBTForcePowerOn value. Specified increment values in miliseconds. Range is 0-1000. 100 = 100 ms." + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ITbtConnectTopologyTimeoutInMs, "ITbtConnectTopology Timeout value", HEX, + Help "ITbtConnectTopologyTimeout value. Specified increment values in miliseconds. Range is 0-10000. 100 = 100 ms." + "Valid range: 0x00 ~ 0xFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_VccSt, "VCCST request for IOM ", &EN_DIS, + Help "This policy will enable/disable VCCST and also decides if message would be replayed in S4/S5" + EditNum $gPlatformFspPkgTokenSpaceGuid_ITbtDmaLtr, "ITBT DMA LTR", HEX, + Help "TCSS DMA1, DMA2 LTR value" + "Valid range: 0x0 ~ 0xFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PtmEnabled, "Enable/Disable PTM", &EN_DIS, + Help "This policy will enable/disable Precision Time Measurement for TCSS PCIe Root Ports" + EditNum $gPlatformFspPkgTokenSpaceGuid_SaPcieItbtRpLtrEnable, "PCIE RP Ltr Enable", HEX, + Help "Latency Tolerance Reporting Mechanism." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SaPcieItbtRpSnoopLatencyOverrideMode, "PCIE RP Snoop Latency Override Mode", HEX, + Help "Latency Tolerance Reporting, Snoop Latency Override Mode." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SaPcieItbtRpSnoopLatencyOverrideMultiplier, "PCIE RP Snoop Latency Override Multiplier", HEX, + Help "Latency Tolerance Reporting, Snoop Latency Override Multiplier." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SaPcieItbtRpSnoopLatencyOverrideValue, "PCIE RP Snoop Latency Override Value", HEX, + Help "Latency Tolerance Reporting, Snoop Latency Override Value." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SaPcieItbtRpNonSnoopLatencyOverrideMode, "PCIE RP Non Snoop Latency Override Mode", HEX, + Help "Latency Tolerance Reporting, Non-Snoop Latency Override Mode." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SaPcieItbtRpNonSnoopLatencyOverrideMultiplier, "PCIE RP Non Snoop Latency Override Multiplier", HEX, + Help "Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SaPcieItbtRpNonSnoopLatencyOverrideValue, "PCIE RP Non Snoop Latency Override Value", HEX, + Help "Latency Tolerance Reporting, Non-Snoop Latency Override Value." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SaPcieItbtRpForceLtrOverride, "Force LTR Override", HEX, + Help "Force LTR Override." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SaPcieItbtRpLtrConfigLock, "PCIE RP Ltr Config Lock", HEX, + Help "0: Disable; 1: Enable." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_EnableTcssCovTypeA, "Type C Port x Convert to TypeA", &EN_DIS, + Help "Enable / Disable(default) Type C Port x Convert to TypeA" + EditNum $gPlatformFspPkgTokenSpaceGuid_MappingPchXhciUsbA, "PCH xhci port x for Type C Port x mapping", HEX, + Help "input PCH xhci port x for Type C Port 0 mapping." + "Valid range: 0x0 ~ 0xFF" +EndPage + +Page "Security (Pre-Mem)" + Combo $gPlatformFspPkgTokenSpaceGuid_BiosGuard, "BiosGuard", &EN_DIS, + Help "Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable" + Combo $gPlatformFspPkgTokenSpaceGuid_Txt, "Txt", &EN_DIS, + Help "Enable/Disable. 0: Disable, Enable/Disable Txt feature, 1: enable" + EditNum $gPlatformFspPkgTokenSpaceGuid_PrmrrSize, "PrmrrSize", HEX, + Help "Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SinitMemorySize, "SinitMemorySize", HEX, + Help "Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_TxtDprMemoryBase, "TxtDprMemoryBase", HEX, + Help "Enable/Disable. 0: Disable, define default value of TxtDprMemoryBase , 1: enable" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_TxtHeapMemorySize, "TxtHeapMemorySize", HEX, + Help "Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_TxtDprMemorySize, "TxtDprMemorySize", HEX, + Help "Enable/Disable. 0: Disable, define default value of TxtDprMemorySize , 1: enable" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_BiosAcmBase, "BiosAcmBase", HEX, + Help "Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_BiosAcmSize, "BiosAcmSize", HEX, + Help "Enable/Disable. 0: Disable, define default value of BiosAcmSize , 1: enable" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ApStartupBase, "ApStartupBase", HEX, + Help "Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_TgaSize, "TgaSize", HEX, + Help "Enable/Disable. 0: Disable, define default value of TgaSize , 1: enable" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_TxtLcpPdBase, "TxtLcpPdBase", HEX, + Help "Enable/Disable. 0: Disable, define default value of TxtLcpPdBase , 1: enable" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_TxtLcpPdSize, "TxtLcpPdSize", HEX, + Help "Enable/Disable. 0: Disable, define default value of TxtLcpPdSize , 1: enable" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IsTPMPresence, "IsTPMPresence", HEX, + Help "IsTPMPresence default values" + "Valid range: 0x00 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_ReservedSecurityPreMem, "ReservedSecurityPreMem", &EN_DIS, + Help "Reserved for Security Pre-Mem" + EditNum $gPlatformFspPkgTokenSpaceGuid_TotalFlashSize, "TotalFlashSize", HEX, + Help "Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable" + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_BiosSize, "BiosSize", HEX, + Help "The size of the BIOS region of the IFWI. Used if FspmUpd->FspmConfig.BiosGuard != 0. If BiosGuard is enabled, MRC will increase the size of the DPR (DMA Protected Range) so that a BIOS Update Script can be stored in the DPR." + "Valid range: 0x00 ~ 0xFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_SecurityTestRsvd, "SecurityTestRsvd", &EN_DIS, + Help "Reserved for SA Pre-Mem Test" +EndPage + +Page "ME (Pre-Mem)" + Combo $gPlatformFspPkgTokenSpaceGuid_HeciTimeouts, "HECI Timeouts", &EN_DIS, + Help "0: Disable, 1: Enable (Default) timeout check for HECI" + EditNum $gPlatformFspPkgTokenSpaceGuid_Heci1BarAddress, "HECI1 BAR address", HEX, + Help "BAR address of HECI1" + "Valid range: 0x00 ~ 0xFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_Heci2BarAddress, "HECI2 BAR address", HEX, + Help "BAR address of HECI2" + "Valid range: 0x00 ~ 0xFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_Heci3BarAddress, "HECI3 BAR address", HEX, + Help "BAR address of HECI3" + "Valid range: 0x00 ~ 0xFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_DidInitStat, "Force ME DID Init Status", &EN_DIS, + Help "Test, 0: disable, 1: Success, 2: No Memory in Channels, 3: Memory Init Error, Set ME DID init stat value" + Combo $gPlatformFspPkgTokenSpaceGuid_DisableCpuReplacedPolling, "CPU Replaced Polling Disable", &EN_DIS, + Help "Test, 0: disable, 1: enable, Setting this option disables CPU replacement polling loop" + Combo $gPlatformFspPkgTokenSpaceGuid_DisableMessageCheck, "Check HECI message before send", &EN_DIS, + Help "Test, 0: disable, 1: enable, Enable/Disable message check." + Combo $gPlatformFspPkgTokenSpaceGuid_SkipMbpHob, "Skip MBP HOB", &EN_DIS, + Help "Test, 0: disable, 1: enable, Enable/Disable MOB HOB." + Combo $gPlatformFspPkgTokenSpaceGuid_HeciCommunication2, "HECI2 Interface Communication", &EN_DIS, + Help "Test, 0: disable, 1: enable, Adds or Removes HECI2 Device from PCI space." + Combo $gPlatformFspPkgTokenSpaceGuid_KtDeviceEnable, "Enable KT device", &EN_DIS, + Help "Test, 0: disable, 1: enable, Enable or Disable KT device." + Combo $gPlatformFspPkgTokenSpaceGuid_SkipCpuReplacementCheck, "Skip CPU replacement check", &EN_DIS, + Help "Test, 0: disable, 1: enable, Setting this option to skip CPU replacement check" +EndPage + +Page "ME (Post-Mem)" + Combo $gPlatformFspPkgTokenSpaceGuid_AmtEnabled, "AMT Switch", &EN_DIS, + Help "Enable/Disable. 0: Disable, 1: enable, Enable or disable AMT functionality." + Combo $gPlatformFspPkgTokenSpaceGuid_WatchDogEnabled, "WatchDog Timer Switch", &EN_DIS, + Help "Enable/Disable. 0: Disable, 1: enable, Enable or disable WatchDog timer. Setting is invalid if AmtEnabled is 0." + Combo $gPlatformFspPkgTokenSpaceGuid_FwProgress, "PET Progress", &EN_DIS, + Help "Enable/Disable. 0: Disable, 1: enable, Enable/Disable PET Events Progress to receive PET Events. Setting is invalid if AmtEnabled is 0." + Combo $gPlatformFspPkgTokenSpaceGuid_AmtSolEnabled, "SOL Switch", &EN_DIS, + Help "Enable/Disable. 0: Disable, 1: enable, Serial Over Lan enable/disable state by Mebx. Setting is invalid if AmtEnabled is 0." + EditNum $gPlatformFspPkgTokenSpaceGuid_WatchDogTimerOs, "OS Timer", HEX, + Help "16 bits Value, Set OS watchdog timer. Setting is invalid if AmtEnabled is 0." + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_WatchDogTimerBios, "BIOS Timer", HEX, + Help "16 bits Value, Set BIOS watchdog timer. Setting is invalid if AmtEnabled is 0." + "Valid range: 0x00 ~ 0xFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_ForcMebxSyncUp, "Force MEBX execution", &EN_DIS, + Help "Enable/Disable. 0: Disable, 1: enable, Force MEBX execution." + Combo $gPlatformFspPkgTokenSpaceGuid_MeUnconfigOnRtcClear, "ME Unconfig on RTC clear", &gPlatformFspPkgTokenSpaceGuid_MeUnconfigOnRtcClear, + Help "0: Disable ME Unconfig On Rtc Clear. 1: Enable ME Unconfig On Rtc Clear. 2: Cmos is clear, status unkonwn. 3: Reserved" + Combo $gPlatformFspPkgTokenSpaceGuid_EnforceEDebugMode, "Enforce Enhanced Debug Mode", &EN_DIS, + Help "Determine if ME should enter Enhanced Debug Mode. 0: disable, 1: enable" + Combo $gPlatformFspPkgTokenSpaceGuid_EndOfPostMessage, "End of Post message", &gPlatformFspPkgTokenSpaceGuid_EndOfPostMessage, + Help "Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1): EOP send in PEI, Send in DXE(0x2)(Default): EOP send in DXE" + Combo $gPlatformFspPkgTokenSpaceGuid_DisableD0I3SettingForHeci, "D0I3 Setting for HECI Disable", &EN_DIS, + Help "Test, 0: disable, 1: enable, Setting this option disables setting D0I3 bit for all HECI devices" + Combo $gPlatformFspPkgTokenSpaceGuid_MctpBroadcastCycle, "Mctp Broadcast Cycle", &EN_DIS, + Help "Test, Determine if MCTP Broadcast is enabled 0: Disable; 1: Enable." +EndPage + +Page "Debug" + Combo $gPlatformFspPkgTokenSpaceGuid_PlatformDebugConsent, "Platform Debug Consent", &gPlatformFspPkgTokenSpaceGuid_PlatformDebugConsent, + Help "Enabled(All Probes+TraceHub) supports all probes with TraceHub enabled and blocks s0ix\n\nEnabled(Low Power) does not support DCI OOB 4-wire and Tracehub is powergated by default, s0ix is viable\n\nManual:user needs to configure Advanced Debug Settings manually, aimed at advanced users" + Combo $gPlatformFspPkgTokenSpaceGuid_DciEn, "DCI Enable", &EN_DIS, + Help "Determine if to enable DCI debug from host" + Combo $gPlatformFspPkgTokenSpaceGuid_DciDbcMode, "DCI DbC Mode", &gPlatformFspPkgTokenSpaceGuid_DciDbcMode, + Help "Disabled: Clear both USB2/3DBCEN; USB2: set USB2DBCEN; USB3: set USB3DBCEN; Both: Set both USB2/3DBCEN; No Change: Comply with HW value" + Combo $gPlatformFspPkgTokenSpaceGuid_DciModphyPg, "Enable DCI ModPHY Power Gate", &EN_DIS, + Help "DEPRECATED" + Combo $gPlatformFspPkgTokenSpaceGuid_DciUsb3TypecUfpDbg, "USB3 Type-C UFP2DFP Kernel/Platform Debug Support", &gPlatformFspPkgTokenSpaceGuid_DciUsb3TypecUfpDbg, + Help "This BIOS option enables kernel and platform debug for USB3 interface over a UFP Type-C receptacle, select 'No Change' will do nothing to UFP2DFP setting." + Combo $gPlatformFspPkgTokenSpaceGuid_SerialIoDebugUartNumber, "UART Number For Debug Purpose", &gPlatformFspPkgTokenSpaceGuid_SerialIoDebugUartNumber, + Help "UART number for debug purpose. 0:UART0, 1:UART1, 2:UART2, 3:UART3, 4:UART4, 5:UART5, 6:UART6. Note: If UART0 is selected as CNVi BT Core interface, it cannot be used for debug purpose." + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDbg2, "Serial IO UART DBG2 table", HEX, + Help "Enable or disable Serial Io UART DBG2 table, default is Disable; 0: Disable; 1: Enable." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_CpuCrashLogEnable, "Enable/Disable CrashLog", &EN_DIS, + Help "Enable(Default): Enable CPU CrashLog, Disable: Disable CPU CrashLog" + EditNum $gPlatformFspPkgTokenSpaceGuid_ProcessorTraceMemSize, "Memory size per thread allocated for Processor Trace", HEX, + Help "Memory size per thread for Processor Trace. Processor Trace requires 2^N alignment and size in bytes per thread, from 4KB to 128MB.\n 0xff:none , 0:4k, 0x1:8k, 0x2:16k, 0x3:32k, 0x4:64k, 0x5:128k, 0x6:256k, 0x7:512k, 0x8:1M, 0x9:2M, 0xa:4M. 0xb:8M, 0xc:16M, 0xd:32M, 0xe:64M, 0xf:128M" + "Valid range: 0x00 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PchLpcEnhancePort8xhDecoding, "PCH LPC Enhanced Port 80 Decoding", &EN_DIS, + Help "Original LPC only decodes one byte of port 80h." + Combo $gPlatformFspPkgTokenSpaceGuid_PchPort80Route, "PCH Port80 Route", &gPlatformFspPkgTokenSpaceGuid_PchPort80Route, + Help "Control where the Port 80h cycles are sent, 0: LPC; 1: PCI." + EditNum $gPlatformFspPkgTokenSpaceGuid_PcdDebugInterfaceFlags, "Debug Interfaces", HEX, + Help "Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, BIT2 - Not used." + "Valid range: 0x00 ~ 0x3F" + Combo $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugControllerNumber, "Serial Io Uart Debug Controller Number", &gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugControllerNumber, + Help "Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT Core interface, it cannot be used for debug purpose." + Combo $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugAutoFlow, "Serial Io Uart Debug Auto Flow", &EN_DIS, + Help "Enables UART hardware flow control, CTS and RTS lines." + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugBaudRate, "Serial Io Uart Debug BaudRate", DEC, + Help "Set default BaudRate Supported from 0 - default to 6000000. Recommended values 9600, 19200, 57600, 115200, 460800, 921600, 1500000, 1843200, 3000000, 3686400, 6000000" + "Valid range: 0 ~ 6000000" + Combo $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugParity, "Serial Io Uart Debug Parity", &gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugParity, + Help "Set default Parity." + Combo $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugStopBits, "Serial Io Uart Debug Stop Bits", &gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugStopBits, + Help "Set default stop bits." + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugDataBits, "Serial Io Uart Debug Data Bits", HEX, + Help "Set default word length. 0: Default, 5,6,7,8" + "Valid range: 0x0 ~ 0x08" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugMmioBase, "Serial Io Uart Debug Mmio Base", HEX, + Help "Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIoUartMode = SerialIoUartPci." + "Valid range: 0 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugBaudRate, "PcdSerialDebugBaudRate", &gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugBaudRate, + Help "Baud Rate for Serial Debug Messages. 3:9600, 4:19200, 6:56700, 7:115200." + Combo $gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugLevel, "PcdSerialDebugLevel", &gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugLevel, + Help "Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, Info & Verbose." + EditNum $gPlatformFspPkgTokenSpaceGuid_PostCodeOutputPort, "Post Code Output Port", HEX, + Help "This option configures Post Code Output Port" + "Valid range: 0x0 ~ 0xFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_SerialDebugMrcLevel, "SerialDebugMrcLevel", &gPlatformFspPkgTokenSpaceGuid_SerialDebugMrcLevel, + Help "MRC Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, Info & Verbose." + Combo $gPlatformFspPkgTokenSpaceGuid_Ddr4OneDpc, "Ddr4OneDpc", &gPlatformFspPkgTokenSpaceGuid_Ddr4OneDpc, + Help "DDR4 1DPC performance feature for 2R DIMMs. Can be enabled on DIMM0 or DIMM1 only, or on both (default)" + EditNum $gPlatformFspPkgTokenSpaceGuid_Lfsr1Mask, "RH pTRR LFSR1 Mask", HEX, + Help "Row Hammer pTRR LFSR1 Mask, 1/2^(value)" + "Valid range: 0x01 ~ 0xF" + EditNum $gPlatformFspPkgTokenSpaceGuid_LpddrRttWr, "LPDDR ODT RttWr", HEX, + Help "Initial RttWr for LP4/5 in Ohms. 0x0 - Auto" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_LpddrRttCa, "LPDDR ODT RttCa", HEX, + Help "Initial RttCa for LP4/5 in Ohms. 0x0 - Auto" + "Valid range: 0x00 ~ 0xFF" +EndPage + diff --git a/AlderLakeFspBinPkg/Client/AlderLakeP/Fsp.fd b/AlderLakeFspBinPkg/Client/AlderLakeP/Fsp.fd new file mode 100644 index 0000000000000000000000000000000000000000..4bac496758bfeb69646d0f3aa5f471ad6e72c15f GIT binary patch literal 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+# @copyright +# Copyright (c) 2022, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# @par Specification +## + +[PcdsDynamicExDefault] + + ## Specifies max supported number of Logical Processors. + # @Prompt Configure max supported number of Logical Processorss + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|16 + + gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress|0xC0000000 + gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000 + + ## Specifies the base address of the first microcode Patch in the microcode Region. + # @Prompt Microcode Region base address. + gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0x0 + + ## Specifies the size of the microcode Region. + # @Prompt Microcode Region size. + gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x0 + + ## Specifies the AP wait loop state during POST phase. + # The value is defined as below. + # 1: Place AP in the Hlt-Loop state. + # 2: Place AP in the Mwait-Loop state. + # 3: Place AP in the Run-Loop state. + # @Prompt The AP wait loop state. + gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|2 + + ## Specifies the AP target C-state for Mwait during POST phase. + # The default value 0 means C1 state. + # The value is defined as below.

+ # @Prompt The specified AP target C-state for Mwait. + gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate|0 + + # + # Enable ACPI S3 support in FSP by default + # + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiS3Enable|1 + + ## Contains the pointer to a CPU S3 data buffer of structure ACPI_CPU_DATA. + # @Prompt The pointer to a CPU S3 data buffer. + gUefiCpuPkgTokenSpaceGuid.PcdCpuS3DataAddress|0x00 + + ## As input, specifies user's desired settings for enabling/disabling processor features. + ## As output, specifies actual settings for processor features, each bit corresponding to a specific feature. + # @Prompt As input, specifies user's desired processor feature settings. As output, specifies actual processor feature settings. + gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesSetting|{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + + ## Contains the size of memory required when CPU processor trace is enabled.

+ # Processor trace is enabled through set BIT44(CPU_FEATURE_PROC_TRACE) in PcdCpuFeaturesSetting.

+ # @Prompt The memory size used for processor trace if processor trace is enabled. + gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceMemSize|0x0 + + ## Contains the processor trace output scheme when CPU processor trace is enabled.

+ # Processor trace is enabled through set BIT44(CPU_FEATURE_PROC_TRACE) in PcdCpuFeaturesSetting.

+ # @Prompt The processor trace output scheme used when processor trace is enabled. + gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceOutputScheme|0x0 + + ## Indicates processor feature capabilities, each bit corresponding to a specific feature. + # @Prompt Processor feature capabilities. + gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesCapability|{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + + # Set SEV-ES defaults + gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbSize|0 + gUefiCpuPkgTokenSpaceGuid.PcdSevEsIsEnabled|0 + + ## This dynamic PCD hold an address to point to private data structure used in DxeS3BootScriptLib library + # instance which records the S3 boot script table start address, length, etc. To introduce this PCD is + # only for DxeS3BootScriptLib instance implementation purpose. The platform developer should make sure the + # default value is set to Zero. And the PCD is assumed ONLY to be accessed in DxeS3BootScriptLib Library. + # @Prompt S3 Boot Script Table Private Data pointer. + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr|0 + + ## This dynamic PCD hold an address to point to private data structure SMM copy used in DxeS3BootScriptLib library + # instance which records the S3 boot script table start address, length, etc. To introduce this PCD is + # only for DxeS3BootScriptLib instance implementation purpose. The platform developer should make sure the + # default value is set to Zero. And the PCD is assumed ONLY to be accessed in DxeS3BootScriptLib Library. + # @Prompt S3 Boot Script Table Private Smm Data pointer. + # @ValidList 0x80000001 | 0x0 + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr|0 \ No newline at end of file diff --git a/AlderLakeFspBinPkg/Client/AlderLakeP/Include/FirmwareVersionInfo.h b/AlderLakeFspBinPkg/Client/AlderLakeP/Include/FirmwareVersionInfo.h new file mode 100644 index 0000000..980b31e --- /dev/null +++ b/AlderLakeFspBinPkg/Client/AlderLakeP/Include/FirmwareVersionInfo.h @@ -0,0 +1,54 @@ +/** @file + Intel Firmware Version Info (FVI) related definitions. + + @todo update document/spec reference + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +@par Specification Reference: + System Management BIOS (SMBIOS) Reference Specification v3.0.0 dated 2015-Feb-12 + http://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.0.0.pdf + +**/ + +#ifndef __FIRMWARE_VERSION_INFO_H__ +#define __FIRMWARE_VERSION_INFO_H__ + +#include + +#define INTEL_FIRMWARE_VERSION_INFO_GROUP_NAME "Firmware Version Info" + +#pragma pack(1) + +/// +/// Firmware Version Structure +/// +typedef struct { + UINT8 MajorVersion; + UINT8 MinorVersion; + UINT8 Revision; + UINT16 BuildNumber; +} INTEL_FIRMWARE_VERSION; + +/// +/// Firmware Version Info (FVI) Structure +/// +typedef struct { + SMBIOS_TABLE_STRING ComponentName; ///< String Index of Component Name + SMBIOS_TABLE_STRING VersionString; ///< String Index of Version String + INTEL_FIRMWARE_VERSION Version; ///< Firmware version +} INTEL_FIRMWARE_VERSION_INFO; + +/// +/// SMBIOS OEM Type Intel Firmware Version Info (FVI) Structure +/// +typedef struct { + SMBIOS_STRUCTURE Header; ///< SMBIOS structure header + UINT8 Count; ///< Number of FVI entries in this structure + INTEL_FIRMWARE_VERSION_INFO Fvi[1]; ///< FVI structure(s) +} SMBIOS_TABLE_TYPE_OEM_INTEL_FVI; + +#pragma pack() + +#endif diff --git a/AlderLakeFspBinPkg/Client/AlderLakeP/Include/FirmwareVersionInfoHob.h b/AlderLakeFspBinPkg/Client/AlderLakeP/Include/FirmwareVersionInfoHob.h new file mode 100644 index 0000000..970faf2 --- /dev/null +++ b/AlderLakeFspBinPkg/Client/AlderLakeP/Include/FirmwareVersionInfoHob.h @@ -0,0 +1,65 @@ +/** @file + Header file for Firmware Version Information + + @copyright + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _FIRMWARE_VERSION_INFO_HOB_H_ +#define _FIRMWARE_VERSION_INFO_HOB_H_ + +#include +#include +#include + +#pragma pack(1) +/// +/// Firmware Version Structure +/// +typedef struct { + UINT8 MajorVersion; + UINT8 MinorVersion; + UINT8 Revision; + UINT16 BuildNumber; +} FIRMWARE_VERSION; + +/// +/// Firmware Version Information Structure +/// +typedef struct { + UINT8 ComponentNameIndex; ///< Offset 0 Index of Component Name + UINT8 VersionStringIndex; ///< Offset 1 Index of Version String + FIRMWARE_VERSION Version; ///< Offset 2-6 Firmware version +} FIRMWARE_VERSION_INFO; + +#ifndef __SMBIOS_STANDARD_H__ +/// +/// The Smbios structure header. +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Handle; +} SMBIOS_STRUCTURE; +#endif + +/// +/// Firmware Version Information HOB Structure +/// +typedef struct { + EFI_HOB_GUID_TYPE Header; ///< Offset 0-23 The header of FVI HOB + SMBIOS_STRUCTURE SmbiosData; ///< Offset 24-27 The SMBIOS header of FVI HOB + UINT8 Count; ///< Offset 28 Number of FVI elements included. +/// +/// FIRMWARE_VERSION_INFO structures followed by the null terminated string buffer +/// +} FIRMWARE_VERSION_INFO_HOB; +#pragma pack() + +#endif // _FIRMWARE_VERSION_INFO_HOB_H_ diff --git a/AlderLakeFspBinPkg/Client/AlderLakeP/Include/FspInfoHob.h b/AlderLakeFspBinPkg/Client/AlderLakeP/Include/FspInfoHob.h new file mode 100644 index 0000000..f77434e --- /dev/null +++ b/AlderLakeFspBinPkg/Client/AlderLakeP/Include/FspInfoHob.h @@ -0,0 +1,32 @@ +/** @file + Header file for FSP Information HOB. + +@copyright + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +@par Specification Reference: +**/ + +#ifndef _FSP_INFO_HOB_H_ +#define _FSP_INFO_HOB_H_ + +extern EFI_GUID gFspInfoGuid; + +#pragma pack (push, 1) + +typedef struct { +UINT8 SiliconInitVersionMajor; +UINT8 SiliconInitVersionMinor; +UINT8 SiliconInitVersionRevision; +UINT8 SiliconInitVersionBuild; +UINT8 FspVersionRevision; +UINT8 FspVersionBuild; +UINT8 TimeStamp [12]; +UINT8 FspVersionMinor; +} FSP_INFO_HOB; + +#pragma pack (pop) + +#endif // _FSP_INFO_HOB_H_ diff --git a/AlderLakeFspBinPkg/Client/AlderLakeP/Include/FspUpd.h b/AlderLakeFspBinPkg/Client/AlderLakeP/Include/FspUpd.h new file mode 100644 index 0000000..2157ad5 --- /dev/null +++ b/AlderLakeFspBinPkg/Client/AlderLakeP/Include/FspUpd.h @@ -0,0 +1,48 @@ +/** @file + +Copyright (c) 2022, Intel Corporation. All rights reserved.
+ +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPUPD_H__ +#define __FSPUPD_H__ + +#include + +#pragma pack(1) + +#define FSPT_UPD_SIGNATURE 0x545F4450554C4441 /* 'ADLUPD_T' */ + +#define FSPM_UPD_SIGNATURE 0x4D5F4450554C4441 /* 'ADLUPD_M' */ + +#define FSPS_UPD_SIGNATURE 0x535F4450554C4441 /* 'ADLUPD_S' */ + +#pragma pack() + +#endif diff --git a/AlderLakeFspBinPkg/Client/AlderLakeP/Include/FspmUpd.h b/AlderLakeFspBinPkg/Client/AlderLakeP/Include/FspmUpd.h new file mode 100644 index 0000000..99cd1e2 --- /dev/null +++ b/AlderLakeFspBinPkg/Client/AlderLakeP/Include/FspmUpd.h @@ -0,0 +1,4029 @@ +/** @file + +Copyright (c) 2022, Intel Corporation. All rights reserved.
+ +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPMUPD_H__ +#define __FSPMUPD_H__ + +#include + +#pragma pack(1) + + +#include + +/// +/// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC. +/// +typedef struct { + UINT8 Revision; ///< Chipset Init Info Revision + UINT8 Rsvd[3]; ///< Reserved + UINT16 MeChipInitCrc; ///< 16 bit CRC value of MeChipInit Table + UINT16 BiosChipInitCrc; ///< 16 bit CRC value of PchChipInit Table +} CHIPSET_INIT_INFO; + + +/** Fsp M Configuration +**/ +typedef struct { + +/** Offset 0x0040 - Platform Reserved Memory Size + The minimum platform memory size required to pass control into DXE +**/ + UINT64 PlatformMemorySize; + +/** Offset 0x0048 - SPD Data Length + Length of SPD Data + 0x100:256 Bytes, 0x200:512 Bytes, 0x400:1024 Bytes +**/ + UINT16 MemorySpdDataLen; + +/** Offset 0x004A - Enable above 4GB MMIO resource support + Enable/disable above 4GB MMIO resource support + $EN_DIS +**/ + UINT8 EnableAbove4GBMmio; + +/** Offset 0x004B - Enable/Disable CrashLog Device 10 + Enable(Default): Enable CPU CrashLog Device 10, Disable: Disable CPU CrashLog + $EN_DIS +**/ + UINT8 CpuCrashLogDevice; + +/** Offset 0x004C - Memory SPD Pointer Controller 0 Channel 0 Dimm 0 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT32 MemorySpdPtr000; + +/** Offset 0x0050 - Memory SPD Pointer Controller 0 Channel 0 Dimm 1 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT32 MemorySpdPtr001; + +/** Offset 0x0054 - Memory SPD Pointer Controller 0 Channel 1 Dimm 0 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT32 MemorySpdPtr010; + +/** Offset 0x0058 - Memory SPD Pointer Controller 0 Channel 1 Dimm 1 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT32 MemorySpdPtr011; + +/** Offset 0x005C - Memory SPD Pointer Controller 0 Channel 2 Dimm 0 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT32 MemorySpdPtr020; + +/** Offset 0x0060 - Memory SPD Pointer Controller 0 Channel 2 Dimm 1 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT32 MemorySpdPtr021; + +/** Offset 0x0064 - Memory SPD Pointer Controller 0 Channel 3 Dimm 0 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT32 MemorySpdPtr030; + +/** Offset 0x0068 - Memory SPD Pointer Controller 0 Channel 3 Dimm 1 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT32 MemorySpdPtr031; + +/** Offset 0x006C - Memory SPD Pointer Controller 1 Channel 0 Dimm 0 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT32 MemorySpdPtr100; + +/** Offset 0x0070 - Memory SPD Pointer Controller 1 Channel 0 Dimm 1 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT32 MemorySpdPtr101; + +/** Offset 0x0074 - Memory SPD Pointer Controller 1 Channel 1 Dimm 0 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT32 MemorySpdPtr110; + +/** Offset 0x0078 - Memory SPD Pointer Controller 1 Channel 1 Dimm 1 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT32 MemorySpdPtr111; + +/** Offset 0x007C - Memory SPD Pointer Controller 1 Channel 2 Dimm 0 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT32 MemorySpdPtr120; + +/** Offset 0x0080 - Memory SPD Pointer Controller 1 Channel 2 Dimm 1 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT32 MemorySpdPtr121; + +/** Offset 0x0084 - Memory SPD Pointer Controller 1 Channel 3 Dimm 0 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT32 MemorySpdPtr130; + +/** Offset 0x0088 - Memory SPD Pointer Controller 1 Channel 3 Dimm 1 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT32 MemorySpdPtr131; + +/** Offset 0x008C - RcompResistor settings + Indicates RcompResistor settings: Board-dependent +**/ + UINT16 RcompResistor; + +/** Offset 0x008E - RcompTarget settings + RcompTarget settings: board-dependent +**/ + UINT16 RcompTarget[5]; + +/** Offset 0x0098 - Dqs Map CPU to DRAM MC 0 CH 0 + Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent +**/ + UINT8 DqsMapCpu2DramMc0Ch0[2]; + +/** Offset 0x009A - Dqs Map CPU to DRAM MC 0 CH 1 + Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent +**/ + UINT8 DqsMapCpu2DramMc0Ch1[2]; + +/** Offset 0x009C - Dqs Map CPU to DRAM MC 0 CH 2 + Set Dqs mapping relationship between CPU and DRAM, Channel 2: board-dependent +**/ + UINT8 DqsMapCpu2DramMc0Ch2[2]; + +/** Offset 0x009E - Dqs Map CPU to DRAM MC 0 CH 3 + Set Dqs mapping relationship between CPU and DRAM, Channel 3: board-dependent +**/ + UINT8 DqsMapCpu2DramMc0Ch3[2]; + +/** Offset 0x00A0 - Dqs Map CPU to DRAM MC 1 CH 0 + Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent +**/ + UINT8 DqsMapCpu2DramMc1Ch0[2]; + +/** Offset 0x00A2 - Dqs Map CPU to DRAM MC 1 CH 1 + Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent +**/ + UINT8 DqsMapCpu2DramMc1Ch1[2]; + +/** Offset 0x00A4 - Dqs Map CPU to DRAM MC 1 CH 2 + Set Dqs mapping relationship between CPU and DRAM, Channel 2: board-dependent +**/ + UINT8 DqsMapCpu2DramMc1Ch2[2]; + +/** Offset 0x00A6 - Dqs Map CPU to DRAM MC 1 CH 3 + Set Dqs mapping relationship between CPU and DRAM, Channel 3: board-dependent +**/ + UINT8 DqsMapCpu2DramMc1Ch3[2]; + +/** Offset 0x00A8 - Dq Map CPU to DRAM MC 0 CH 0 + Set Dq mapping relationship between CPU and DRAM, Channel 0: board-dependent +**/ + UINT8 DqMapCpu2DramMc0Ch0[16]; + +/** Offset 0x00B8 - Dq Map CPU to DRAM MC 0 CH 1 + Set Dq mapping relationship between CPU and DRAM, Channel 1: board-dependent +**/ + UINT8 DqMapCpu2DramMc0Ch1[16]; + +/** Offset 0x00C8 - Dq Map CPU to DRAM MC 0 CH 2 + Set Dq mapping relationship between CPU and DRAM, Channel 2: board-dependet +**/ + UINT8 DqMapCpu2DramMc0Ch2[16]; + +/** Offset 0x00D8 - Dq Map CPU to DRAM MC 0 CH 3 + Set Dq mapping relationship between CPU and DRAM, Channel 3: board-dependent +**/ + UINT8 DqMapCpu2DramMc0Ch3[16]; + +/** Offset 0x00E8 - Dq Map CPU to DRAM MC 1 CH 0 + Set Dq mapping relationship between CPU and DRAM, Channel 0: board-dependent +**/ + UINT8 DqMapCpu2DramMc1Ch0[16]; + +/** Offset 0x00F8 - Dq Map CPU to DRAM MC 1 CH 1 + Set Dq mapping relationship between CPU and DRAM, Channel 1: board-dependent +**/ + UINT8 DqMapCpu2DramMc1Ch1[16]; + +/** Offset 0x0108 - Dq Map CPU to DRAM MC 1 CH 2 + Set Dq mapping relationship between CPU and DRAM, Channel 2: board-dependent +**/ + UINT8 DqMapCpu2DramMc1Ch2[16]; + +/** Offset 0x0118 - Dq Map CPU to DRAM MC 1 CH 3 + Set Dq mapping relationship between CPU and DRAM, Channel 3: board-dependent +**/ + UINT8 DqMapCpu2DramMc1Ch3[16]; + +/** Offset 0x0128 - Dqs Pins Interleaved Setting + Indicates DqPinsInterleaved setting: board-dependent + $EN_DIS +**/ + UINT8 DqPinsInterleaved; + +/** Offset 0x0129 - Smram Mask + The SMM Regions AB-SEG and/or H-SEG reserved + 0: Neither, 1:AB-SEG, 2:H-SEG, 3: Both +**/ + UINT8 SmramMask; + +/** Offset 0x012A - Ibecc + Enable/Disable Ibecc + $EN_DIS +**/ + UINT8 Ibecc; + +/** Offset 0x012B - IbeccOperationMode + In-Band ECC Operation Mode + 0:Protect base on address range, 1:Non-protected, 2:All protected +**/ + UINT8 IbeccOperationMode; + +/** Offset 0x012C - IbeccProtectedRangeEnable + In-Band ECC Protected Region Enable + $EN_DIS +**/ + UINT8 IbeccProtectedRangeEnable[8]; + +/** Offset 0x0134 - IbeccProtectedRangeBase + IBECC Protected Region Base +**/ + UINT32 IbeccProtectedRangeBase[8]; + +/** Offset 0x0154 - IbeccProtectedRangeMask + IBECC Protected Region Mask +**/ + UINT32 IbeccProtectedRangeMask[8]; + +/** Offset 0x0174 - MRC Fast Boot + Enables/Disable the MRC fast path thru the MRC + $EN_DIS +**/ + UINT8 MrcFastBoot; + +/** Offset 0x0175 - Rank Margin Tool per Task + This option enables the user to execute Rank Margin Tool per major training step + in the MRC. + $EN_DIS +**/ + UINT8 RmtPerTask; + +/** Offset 0x0176 - Training Trace + This option enables the trained state tracing feature in MRC. This feature will + print out the key training parameters state across major training steps. + $EN_DIS +**/ + UINT8 TrainTrace; + +/** Offset 0x0177 +**/ + UINT8 UnusedUpdSpace0; + +/** Offset 0x0178 - Tseg Size + Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build + 0x0400000:4MB, 0x01000000:16MB +**/ + UINT32 TsegSize; + +/** Offset 0x017C - MMIO Size + Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB +**/ + UINT16 MmioSize; + +/** Offset 0x017E - Probeless Trace + Probeless Trace: 0=Disabled, 1=Enable. Enabling Probeless Trace will reserve 128MB. + This also requires IED to be enabled. + $EN_DIS +**/ + UINT8 ProbelessTrace; + +/** Offset 0x017F - Enable SMBus + Enable/disable SMBus controller. + $EN_DIS +**/ + UINT8 SmbusEnable; + +/** Offset 0x0180 - Spd Address Tabl + Specify SPD Address table for CH0D0/CH0D1/CH1D0&CH1D1. MemorySpdPtr will be used + if SPD Address is 00 +**/ + UINT8 SpdAddressTable[16]; + +/** Offset 0x0190 - Platform Debug Consent + Enabled(All Probes+TraceHub) supports all probes with TraceHub enabled and blocks + s0ix\n + \n + Enabled(Low Power) does not support DCI OOB 4-wire and Tracehub is powergated by + default, s0ix is viable\n + \n + Manual:user needs to configure Advanced Debug Settings manually, aimed at advanced users + 0:Disabled, 2:Enabled (All Probes+TraceHub), 6:Enable (Low Power), 7:Manual +**/ + UINT8 PlatformDebugConsent; + +/** Offset 0x0191 - DCI Enable + Determine if to enable DCI debug from host + $EN_DIS +**/ + UINT8 DciEn; + +/** Offset 0x0192 - DCI DbC Mode + Disabled: Clear both USB2/3DBCEN; USB2: set USB2DBCEN; USB3: set USB3DBCEN; Both: + Set both USB2/3DBCEN; No Change: Comply with HW value + 0:Disabled, 1:USB2 DbC, 2:USB3 DbC, 3:Both, 4:No Change +**/ + UINT8 DciDbcMode; + +/** Offset 0x0193 - Enable DCI ModPHY Power Gate + DEPRECATED + $EN_DIS +**/ + UINT8 DciModphyPg; + +/** Offset 0x0194 - USB3 Type-C UFP2DFP Kernel/Platform Debug Support + This BIOS option enables kernel and platform debug for USB3 interface over a UFP + Type-C receptacle, select 'No Change' will do nothing to UFP2DFP setting. + 0:Disabled, 1:Enabled, 2:No Change +**/ + UINT8 DciUsb3TypecUfpDbg; + +/** Offset 0x0195 - PCH Trace Hub Mode + Select 'Host Debugger' if Trace Hub is used with host debugger tool or 'Target Debugger' + if Trace Hub is used by target debugger software or 'Disable' trace hub functionality. + 0: Disable, 1: Target Debugger Mode, 2: Host Debugger Mode +**/ + UINT8 PchTraceHubMode; + +/** Offset 0x0196 - PCH Trace Hub Memory Region 0 buffer Size + Specify size of Pch trace memory region 0 buffer, the size can be 0, 1MB, 8MB, 64MB, + 128MB, 256MB, 512MB + 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB +**/ + UINT8 PchTraceHubMemReg0Size; + +/** Offset 0x0197 - PCH Trace Hub Memory Region 1 buffer Size + Specify size of Pch trace memory region 1 buffer, the size can be 0, 1MB, 8MB, 64MB, + 128MB, 256MB, 512MB + 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB +**/ + UINT8 PchTraceHubMemReg1Size; + +/** Offset 0x0198 - HD Audio DMIC Link Clock Select + Determines DMIC Clock Source. 0: Both, 1: ClkA, 2: ClkB + 0: Both, 1: ClkA, 2: ClkB +**/ + UINT8 PchHdaAudioLinkDmicClockSelect[2]; + +/** Offset 0x019A - PchPreMemRsvd + Reserved for PCH Pre-Mem Reserved + $EN_DIS +**/ + UINT8 PchPreMemRsvd[5]; + +/** Offset 0x019F - State of X2APIC_OPT_OUT bit in the DMAR table + 0=Disable/Clear, 1=Enable/Set + $EN_DIS +**/ + UINT8 X2ApicOptOut; + +/** Offset 0x01A0 - State of DMA_CONTROL_GUARANTEE bit in the DMAR table + 0=Disable/Clear, 1=Enable/Set + $EN_DIS +**/ + UINT8 DmaControlGuarantee; + +/** Offset 0x01A1 +**/ + UINT8 UnusedUpdSpace1[3]; + +/** Offset 0x01A4 - Base addresses for VT-d function MMIO access + Base addresses for VT-d MMIO access per VT-d engine +**/ + UINT32 VtdBaseAddress[9]; + +/** Offset 0x01C8 - Disable VT-d + 0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled) + $EN_DIS +**/ + UINT8 VtdDisable; + +/** Offset 0x01C9 - Vtd Programming for Igd + 1=Enable/TRUE (Igd VT-d Bar programming enabled), 0=Disable/FLASE (Igd VT-d Bar + programming disabled) + $EN_DIS +**/ + UINT8 VtdIgdEnable; + +/** Offset 0x01CA - Vtd Programming for Ipu + 1=Enable/TRUE (Ipu VT-d Bar programming enabled), 0=Disable/FLASE (Ipu VT-d Bar + programming disabled) + $EN_DIS +**/ + UINT8 VtdIpuEnable; + +/** Offset 0x01CB - Vtd Programming for Iop + 1=Enable/TRUE (Iop VT-d Bar programming enabled), 0=Disable/FLASE (Iop VT-d Bar + programming disabled) + $EN_DIS +**/ + UINT8 VtdIopEnable; + +/** Offset 0x01CC - Vtd Programming for ITbt + DEPRECATED + $EN_DIS +**/ + UINT8 VtdItbtEnable; + +/** Offset 0x01CD - Internal Graphics Pre-allocated Memory + Size of memory preallocated for internal graphics. + 0x00:0MB, 0x01:32MB, 0x02:64MB, 0x03:96MB, 0x04:128MB, 0x05:160MB, 0xF0:4MB, 0xF1:8MB, + 0xF2:12MB, 0xF3:16MB, 0xF4:20MB, 0xF5:24MB, 0xF6:28MB, 0xF7:32MB, 0xF8:36MB, 0xF9:40MB, + 0xFA:44MB, 0xFB:48MB, 0xFC:52MB, 0xFD:56MB, 0xFE:60MB +**/ + UINT8 IgdDvmt50PreAlloc; + +/** Offset 0x01CE - Internal Graphics + Enable/disable internal graphics. + $EN_DIS +**/ + UINT8 InternalGfx; + +/** Offset 0x01CF - Aperture Size + Select the Aperture Size. + 0:128 MB, 1:256 MB, 3:512 MB, 7:1024 MB, 15: 2048 MB +**/ + UINT8 ApertureSize; + +/** Offset 0x01D0 - Board Type + MrcBoardType, Options are 0:Mobile, 1:Desktop1Dpc, 2:Desktop2DpcDaisyChain, 3:Desktop2DpcTeeTopologyAsymmetrical, + 4:Desktop2DpcTeeTopology, 5:UltMobile, 7:UP Server + 0:Mobile, 1:Desktop1Dpc, 2:Desktop2DpcDaisyChain, 3:Desktop2DpcTeeTopologyAsymmetrical, + 4:Desktop2DpcTeeTopology, 5:UltMobile, 7:UP Server +**/ + UINT8 UserBd; + +/** Offset 0x01D1 - MRC Retraining on RTC Power Loss + Specifies whether MRC memory training will occur when RTC power loss is detected. + Options are 0=Memory will be re-trained if RTC power loss is detected. 1=Memory + will not be re-trained when RTC power loss is detected. (Typically used on board + designs without a dedicated RTC battery) + 0:Disabled, 1:Enabled +**/ + UINT8 DisableMrcRetrainingOnRtcPowerLoss; + +/** Offset 0x01D2 - DDR Frequency Limit + Maximum Memory Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, + 2133, 2400, 2667, 2933 and 0 for Auto. + 1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 2667:2667, 2933:2933, 0:Auto +**/ + UINT16 DdrFreqLimit; + +/** Offset 0x01D4 - SA GV + System Agent dynamic frequency support and when enabled memory will be training + at four different frequencies. + 0:Disabled, 1:FixedPoint0, 2:FixedPoint1, 3:FixedPoint2, 4:FixedPoint3, 5:Enabled +**/ + UINT8 SaGv; + +/** Offset 0x01D5 - Memory Test on Warm Boot + Run Base Memory Test on Warm Boot + 0:Disable, 1:Enable +**/ + UINT8 MemTestOnWarmBoot; + +/** Offset 0x01D6 - DDR Speed Control + DDR Frequency and Gear control for all SAGV points. + 0:Auto, 1:Manual +**/ + UINT8 DdrSpeedControl; + +/** Offset 0x01D7 - Rank Margin Tool + Enable/disable Rank Margin Tool. + $EN_DIS +**/ + UINT8 RMT; + +/** Offset 0x01D8 - Controller 0 Channel 0 DIMM Control + Enable / Disable DIMMs on Controller 0 Channel 0 + $EN_DIS +**/ + UINT8 DisableMc0Ch0; + +/** Offset 0x01D9 - Controller 0 Channel 1 DIMM Control + Enable / Disable DIMMs on Controller 0 Channel 1 + $EN_DIS +**/ + UINT8 DisableMc0Ch1; + +/** Offset 0x01DA - Controller 0 Channel 2 DIMM Control + Enable / Disable DIMMs on Controller 0 Channel 2 + $EN_DIS +**/ + UINT8 DisableMc0Ch2; + +/** Offset 0x01DB - Controller 0 Channel 3 DIMM Control + Enable / Disable DIMMs on Controller 0 Channel 3 + $EN_DIS +**/ + UINT8 DisableMc0Ch3; + +/** Offset 0x01DC - Controller 1 Channel 0 DIMM Control + Enable / Disable DIMMs on Controller 1 Channel 0 + $EN_DIS +**/ + UINT8 DisableMc1Ch0; + +/** Offset 0x01DD - Controller 1 Channel 1 DIMM Control + Enable / Disable DIMMs on Controller 1 Channel 1 + $EN_DIS +**/ + UINT8 DisableMc1Ch1; + +/** Offset 0x01DE - Controller 1 Channel 2 DIMM Control + Enable / Disable DIMMs on Controller 1 Channel 2 + $EN_DIS +**/ + UINT8 DisableMc1Ch2; + +/** Offset 0x01DF - Controller 1 Channel 3 DIMM Control + Enable / Disable DIMMs on Controller 1 Channel 3 + $EN_DIS +**/ + UINT8 DisableMc1Ch3; + +/** Offset 0x01E0 - Scrambler Support + This option enables data scrambling in memory. + $EN_DIS +**/ + UINT8 ScramblerSupport; + +/** Offset 0x01E1 - SPD Profile Selected + Select DIMM timing profile. Options are 0:Default SPD Profile, 1:Custom Profile, + 2:XMP Profile 1, 3:XMP Profile 2, 4:XMP Profile 3, 5:XMP User Profile 4, 6:XMP + User Profile 5 + 0:Default SPD Profile, 1:Custom Profile, 2:XMP Profile 1, 3:XMP Profile 2, 4:XMP + Profile 3, 5:XMP User Profile 4, 6:XMP User Profile 5 +**/ + UINT8 SpdProfileSelected; + +/** Offset 0x01E2 - Memory Reference Clock + 100MHz, 133MHz. + 0:133MHz, 1:100MHz +**/ + UINT8 RefClk; + +/** Offset 0x01E3 +**/ + UINT8 UnusedUpdSpace2; + +/** Offset 0x01E4 - Memory Voltage + DRAM voltage (Vdd) (supply voltage for input buffers and core logic of the DRAM + chips) in millivolts from 0 - default to 1435mv. +**/ + UINT16 VddVoltage; + +/** Offset 0x01E6 - Memory Ratio + Automatic or the frequency will equal ratio times reference clock. Set to Auto to + recalculate memory timings listed below. + 0:Auto, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, 12:12, 13:13, 14:14, 15:15 +**/ + UINT8 Ratio; + +/** Offset 0x01E7 - tCL + CAS Latency, 0: AUTO, max: 31. Only used if FspmUpd->FspmConfig.SpdProfileSelected + == 1 (Custom Profile). +**/ + UINT8 tCL; + +/** Offset 0x01E8 - tCWL + Min CAS Write Latency Delay Time, 0: AUTO, max: 34. Only used if FspmUpd->FspmConfig.SpdProfileSelected + == 1 (Custom Profile). +**/ + UINT8 tCWL; + +/** Offset 0x01E9 +**/ + UINT8 UnusedUpdSpace3; + +/** Offset 0x01EA - tFAW + Min Four Activate Window Delay Time, 0: AUTO, max: 63. Only used if FspmUpd->FspmConfig.SpdProfileSelected + == 1 (Custom Profile). +**/ + UINT16 tFAW; + +/** Offset 0x01EC - tRAS + RAS Active Time, 0: AUTO, max: 64. Only used if FspmUpd->FspmConfig.SpdProfileSelected + == 1 (Custom Profile). +**/ + UINT16 tRAS; + +/** Offset 0x01EE - tRCD/tRP + RAS to CAS delay time and Row Precharge delay time, 0: AUTO, max: 63. Only used + if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile). +**/ + UINT8 tRCDtRP; + +/** Offset 0x01EF +**/ + UINT8 UnusedUpdSpace4; + +/** Offset 0x01F0 - tREFI + Refresh Interval, 0: AUTO, max: 65535. Only used if FspmUpd->FspmConfig.SpdProfileSelected + == 1 (Custom Profile). +**/ + UINT16 tREFI; + +/** Offset 0x01F2 - tRFC + Min Refresh Recovery Delay Time, 0: AUTO, max: 1023. Only used if FspmUpd->FspmConfig.SpdProfileSelected + == 1 (Custom Profile). +**/ + UINT16 tRFC; + +/** Offset 0x01F4 - tRRD + Min Row Active to Row Active Delay Time, 0: AUTO, max: 15. Only used if FspmUpd->FspmConfig.SpdProfileSelected + == 1 (Custom Profile). +**/ + UINT8 tRRD; + +/** Offset 0x01F5 - tRTP + Min Internal Read to Precharge Command Delay Time, 0: AUTO, max: 15. DDR4 legal + values: 5, 6, 7, 8, 9, 10, 12. Only used if FspmUpd->FspmConfig.SpdProfileSelected + == 1 (Custom Profile). +**/ + UINT8 tRTP; + +/** Offset 0x01F6 - tWR + Min Write Recovery Time, 0: AUTO, legal values: 5, 6, 7, 8, 10, 12, 14, 16, 18, + 20, 24, 30, 34, 40. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile). + 0:Auto, 5:5, 6:6, 7:7, 8:8, 10:10, 12:12, 14:14, 16:16, 18:18, 20:20, 24:24, 30:30, + 34:34, 40:40 +**/ + UINT8 tWR; + +/** Offset 0x01F7 - tWTR + Min Internal Write to Read Command Delay Time, 0: AUTO, max: 28. Only used if FspmUpd->FspmConfig.SpdProfileSelected + == 1 (Custom Profile). +**/ + UINT8 tWTR; + +/** Offset 0x01F8 - NMode + System command rate, range 0-2, 0 means auto, 1 = 1N, 2 = 2N +**/ + UINT8 NModeSupport; + +/** Offset 0x01F9 - Enable Intel HD Audio (Azalia) + 0: Disable, 1: Enable (Default) Azalia controller + $EN_DIS +**/ + UINT8 PchHdaEnable; + +/** Offset 0x01FA - Enable PCH ISH Controller + 0: Disable, 1: Enable (Default) ISH Controller + $EN_DIS +**/ + UINT8 PchIshEnable; + +/** Offset 0x01FB - CPU Trace Hub Mode + Select 'Host Debugger' if Trace Hub is used with host debugger tool or 'Target Debugger' + if Trace Hub is used by target debugger software or 'Disable' trace hub functionality. + 0: Disable, 1:Target Debugger Mode, 2:Host Debugger Mode +**/ + UINT8 CpuTraceHubMode; + +/** Offset 0x01FC - CPU Trace Hub Memory Region 0 + CPU Trace Hub Memory Region 0, The avaliable memory size is : 0MB, 1MB, 8MB, 64MB, + 128MB, 256MB, 512MB + 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB +**/ + UINT8 CpuTraceHubMemReg0Size; + +/** Offset 0x01FD - CPU Trace Hub Memory Region 1 + CPU Trace Hub Memory Region 1. The avaliable memory size is : 0MB, 1MB, 8MB, 64MB, + 128MB, 256MB, 512MB + 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB +**/ + UINT8 CpuTraceHubMemReg1Size; + +/** Offset 0x01FE - SAGV Gear Ratio + Gear Selection for SAGV points. 0 - Auto, 1-1 Gear 1, 2-Gear 2 +**/ + UINT8 SaGvGear[4]; + +/** Offset 0x0202 - SAGV Frequency + SAGV Frequency per point in Mhz. 0 for Auto and a ratio of 133/100MHz: 1333/1300. +**/ + UINT16 SaGvFreq[4]; + +/** Offset 0x020A - SAGV Disabled Gear Ratio + Gear Selection for SAGV Disabled. 0 - Auto, 1-1 Gear 1, 2-Gear 2 +**/ + UINT8 GearRatio; + +/** Offset 0x020B - HECI Timeouts + 0: Disable, 1: Enable (Default) timeout check for HECI + $EN_DIS +**/ + UINT8 HeciTimeouts; + +/** Offset 0x020C - HECI1 BAR address + BAR address of HECI1 +**/ + UINT32 Heci1BarAddress; + +/** Offset 0x0210 - HECI2 BAR address + BAR address of HECI2 +**/ + UINT32 Heci2BarAddress; + +/** Offset 0x0214 - HECI3 BAR address + BAR address of HECI3 +**/ + UINT32 Heci3BarAddress; + +/** Offset 0x0218 - HG dGPU Power Delay + HG dGPU delay interval after power enabling: 0=Minimal, 1000=Maximum, default is + 300=300 microseconds +**/ + UINT16 HgDelayAfterPwrEn; + +/** Offset 0x021A - HG dGPU Reset Delay + HG dGPU delay interval for Reset complete: 0=Minimal, 1000=Maximum, default is 100=100 + microseconds +**/ + UINT16 HgDelayAfterHoldReset; + +/** Offset 0x021C - MMIO size adjustment for AUTO mode + Positive number means increasing MMIO size, Negative value means decreasing MMIO + size: 0 (Default)=no change to AUTO mode MMIO size +**/ + UINT16 MmioSizeAdjustment; + +/** Offset 0x021E - PCIe ASPM programming will happen in relation to the Oprom + Select when PCIe ASPM programming will happen in relation to the Oprom. Before(0x0)(Default): + Do PCIe ASPM programming before Oprom, After(0x1): Do PCIe ASPM programming after + Oprom, requires an SMI handler to save/restore ASPM settings during S3 resume + 0:Before, 1:After +**/ + UINT8 InitPcieAspmAfterOprom; + +/** Offset 0x021F - Selection of the primary display device + 0=iGFX, 1=PEG, 2=PCIe Graphics on PCH, 3(Default)=AUTO, 4=Hybrid Graphics + 0:iGFX, 1:PEG, 2:PCIe Graphics on PCH, 3:AUTO, 4:Hybrid Graphics +**/ + UINT8 PrimaryDisplay; + +/** Offset 0x0220 - Selection of PSMI Region size + 0=32MB, 1=288MB, 2=544MB, 3=800MB, 4=1024MB Default is 0 + 0:32MB, 1:288MB, 2:544MB, 3:800MB, 4:1024MB +**/ + UINT8 PsmiRegionSize; + +/** Offset 0x0221 +**/ + UINT8 UnusedUpdSpace5[3]; + +/** Offset 0x0224 - Temporary MMIO address for GMADR + Obsolete field now and it has been extended to 64 bit address, used GmAdr64 +**/ + UINT32 GmAdr; + +/** Offset 0x0228 - Temporary MMIO address for GTTMMADR + The reference code will use this as Temporary MMIO address space to access GTTMMADR + Registers.Platform should provide conflict free Temporary MMIO Range: GttMmAdr + to (GttMmAdr + 2MB MMIO + 6MB Reserved + GttSize). Default is (GmAdr - (2MB MMIO + + 6MB Reserved + GttSize)) to (GmAdr - 0x1) (Where GttSize = 8MB) +**/ + UINT32 GttMmAdr; + +/** Offset 0x022C - Selection of iGFX GTT Memory size + 1=2MB, 2=4MB, 3=8MB, Default is 3 + 1:2MB, 2:4MB, 3:8MB +**/ + UINT16 GttSize; + +/** Offset 0x022E - Hybrid Graphics GPIO information for PEG 0 + Hybrid Graphics GPIO information for PEG 0, for Reset, power and wake GPIOs +**/ + UINT8 CpuPcie0Rtd3Gpio[24]; + +/** Offset 0x0246 - Enable/Disable MRC TXT dependency + When enabled MRC execution will wait for TXT initialization to be done first. Disabled(0x0)(Default): + MRC will not wait for TXT initialization, Enabled(0x1): MRC will wait for TXT initialization + $EN_DIS +**/ + UINT8 TxtImplemented; + +/** Offset 0x0247 - Enable/Disable SA OcSupport + Enable: Enable SA OcSupport, Disable(Default): Disable SA OcSupport + $EN_DIS +**/ + UINT8 SaOcSupport; + +/** Offset 0x0248 - GT slice Voltage Mode + 0(Default): Adaptive, 1: Override + 0: Adaptive, 1: Override +**/ + UINT8 GtVoltageMode; + +/** Offset 0x0249 - Maximum GTs turbo ratio override + 0(Default)=Minimal/Auto, 60=Maximum +**/ + UINT8 GtMaxOcRatio; + +/** Offset 0x024A - The voltage offset applied to GT slice + 0(Default)=Minimal, 1000=Maximum +**/ + UINT16 GtVoltageOffset; + +/** Offset 0x024C - The GT slice voltage override which is applied to the entire range of GT frequencies + 0(Default)=Minimal, 2000=Maximum +**/ + UINT16 GtVoltageOverride; + +/** Offset 0x024E - adaptive voltage applied during turbo frequencies + 0(Default)=Minimal, 2000=Maximum +**/ + UINT16 GtExtraTurboVoltage; + +/** Offset 0x0250 - voltage offset applied to the SA + 0(Default)=Minimal, 1000=Maximum +**/ + UINT16 SaVoltageOffset; + +/** Offset 0x0252 - PCIe root port Function number for Hybrid Graphics dGPU + Root port Index number to indicate which PCIe root port has dGPU +**/ + UINT8 RootPortIndex; + +/** Offset 0x0253 - Realtime Memory Timing + 0(Default): Disabled, 1: Enabled. When enabled, it will allow the system to perform + realtime memory timing changes after MRC_DONE. + 0: Disabled, 1: Enabled +**/ + UINT8 RealtimeMemoryTiming; + +/** Offset 0x0254 - iTBT PCIe Multiple Segment setting + DEPRECATED + $EN_DIS +**/ + UINT8 PcieMultipleSegmentEnabled; + +/** Offset 0x0255 - Enable/Disable SA IPU + Enable(Default): Enable SA IPU, Disable: Disable SA IPU + $EN_DIS +**/ + UINT8 SaIpuEnable; + +/** Offset 0x0256 - Lane Used of CSI port + Lane Used of each CSI port + 1:x1, 2:x2, 3:x3, 4:x4, 8:x8 +**/ + UINT8 IpuLaneUsed[8]; + +/** Offset 0x025E - Lane Used of CSI port + Speed of each CSI port + 0:Sensor default, 1:<416Mbps, 2:<1.5Gbps, 3:<2Gbps, 4:<2.5Gbps, 5:<4Gbps, 6:>4Gbps +**/ + UINT8 CsiSpeed[8]; + +/** Offset 0x0266 - IMGU CLKOUT Configuration + The configuration of IMGU CLKOUT, 0: Disable;1: Enable. + $EN_DIS +**/ + UINT8 ImguClkOutEn[6]; + +/** Offset 0x026C - Enable PCIE RP Mask + Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 + for port1, bit1 for port2, and so on. +**/ + UINT32 CpuPcieRpEnableMask; + +/** Offset 0x0270 - Assertion on Link Down GPIOs + GPIO Assertion on Link Down. Disabled(0x0)(Default): Disable assertion on Link Down + GPIOs, Enabled(0x1): Enable assertion on Link Down GPIOs + 0:Disable, 1:Enable +**/ + UINT8 CpuPcieRpLinkDownGpios; + +/** Offset 0x0271 - Enable ClockReq Messaging + ClockReq Messaging. Disabled(0x0): Disable ClockReq Messaging, Enabled(0x1)(Default): + Enable ClockReq Messaging + 0:Disable, 1:Enable +**/ + UINT8 CpuPcieRpClockReqMsgEnable[3]; + +/** Offset 0x0274 - PCIE RP Pcie Speed + Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3; + 4: Gen4 (see: CPU_PCIE_SPEED). +**/ + UINT8 CpuPcieRpPcieSpeed[4]; + +/** Offset 0x0278 - Selection of PSMI Support On/Off + 0(Default) = FALSE, 1 = TRUE. When TRUE, it will allow the PSMI Support + $EN_DIS +**/ + UINT8 GtPsmiSupport; + +/** Offset 0x0279 - Program GPIOs for LFP on DDI port-A device + 0=Disabled,1(Default)=eDP, 2=MIPI DSI + 0:Disabled, 1:eDP, 2:MIPI DSI +**/ + UINT8 DdiPortAConfig; + +/** Offset 0x027A - Program GPIOs for LFP on DDI port-B device + 0(Default)=Disabled,1=eDP, 2=MIPI DSI + 0:Disabled, 1:eDP, 2:MIPI DSI +**/ + UINT8 DdiPortBConfig; + +/** Offset 0x027B - Enable or disable HPD of DDI port A + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPortAHpd; + +/** Offset 0x027C - Enable or disable HPD of DDI port B + 0=Disable, 1(Default)=Enable + $EN_DIS +**/ + UINT8 DdiPortBHpd; + +/** Offset 0x027D - Enable or disable HPD of DDI port C + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPortCHpd; + +/** Offset 0x027E - Enable or disable HPD of DDI port 1 + 0=Disable, 1(Default)=Enable + $EN_DIS +**/ + UINT8 DdiPort1Hpd; + +/** Offset 0x027F - Enable or disable HPD of DDI port 2 + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPort2Hpd; + +/** Offset 0x0280 - Enable or disable HPD of DDI port 3 + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPort3Hpd; + +/** Offset 0x0281 - Enable or disable HPD of DDI port 4 + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPort4Hpd; + +/** Offset 0x0282 - Enable or disable DDC of DDI port A + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPortADdc; + +/** Offset 0x0283 - Enable or disable DDC of DDI port B + 0=Disable, 1(Default)=Enable + $EN_DIS +**/ + UINT8 DdiPortBDdc; + +/** Offset 0x0284 - Enable or disable DDC of DDI port C + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPortCDdc; + +/** Offset 0x0285 - Enable DDC setting of DDI Port 1 + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPort1Ddc; + +/** Offset 0x0286 - Enable DDC setting of DDI Port 2 + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPort2Ddc; + +/** Offset 0x0287 - Enable DDC setting of DDI Port 3 + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPort3Ddc; + +/** Offset 0x0288 - Enable DDC setting of DDI Port 4 + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPort4Ddc; + +/** Offset 0x0289 +**/ + UINT8 UnusedUpdSpace6[7]; + +/** Offset 0x0290 - Temporary MMIO address for GMADR + The reference code will use this as Temporary MMIO address space to access GMADR + Registers.Platform should provide conflict free Temporary MMIO Range: GmAdr to + (GmAdr + ApertureSize). Default is (PciExpressBaseAddress - ApertureSize) to (PciExpressBaseAddress + - 0x1) (Where ApertureSize = 256MB, 512MB, 1024MB and 2048MB) +**/ + UINT64 GmAdr64; + +/** Offset 0x0298 - Per-core HT Disable + Defines the per-core HT disable mask where: 1 - Disable selected logical core HT, + 0 - is ignored. Input is in HEX and each bit maps to a logical core. Ex. A value + of '1F' would disable HT for cores 4,3,2,1 and 0. Default is 0, all cores have + HT enabled. Range is 0 - 0x7F for max 8 cores. You can only disable up to MAX_CORE_COUNT - 1. +**/ + UINT16 PerCoreHtDisable; + +/** Offset 0x029A - SA/Uncore voltage mode + SA/Uncore voltage mode; 0: Adaptive; 1: Override. + $EN_DIS +**/ + UINT8 SaVoltageMode; + +/** Offset 0x029B +**/ + UINT8 UnusedUpdSpace7; + +/** Offset 0x029C - SA/Uncore Voltage Override + The SA/Uncore voltage override applicable when SA/Uncore voltage mode is in Override + mode. Valid Range 0 to 2000 +**/ + UINT16 SaVoltageOverride; + +/** Offset 0x029E - SA/Uncore Extra Turbo voltage + Extra Turbo voltage applicable when SA/Uncore voltage mode is in Adaptive mode. + Valid Range 0 to 2000 +**/ + UINT16 SaExtraTurboVoltage; + +/** Offset 0x02A0 - Thermal Velocity Boost Ratio clipping + 0(Default): Disabled, 1: Enabled. This service controls Core frequency reduction + caused by high package temperatures for processors that implement the Intel Thermal + Velocity Boost (TVB) feature + 0: Disabled, 1: Enabled +**/ + UINT8 TvbRatioClipping; + +/** Offset 0x02A1 - Thermal Velocity Boost voltage optimization + 0: Disabled, 1: Enabled(Default). This service controls thermal based voltage optimizations + for processors that implement the Intel Thermal Velocity Boost (TVB) feature. + 0: Disabled, 1: Enabled +**/ + UINT8 TvbVoltageOptimization; + +/** Offset 0x02A2 - Enable/Disable Display Audio Link in Pre-OS + 0(Default)= Disable, 1 = Enable + 0: Disabled, 1: Enabled +**/ + UINT8 DisplayAudioLink; + +/** Offset 0x02A3 +**/ + UINT8 UnusedUpdSpace8; + +/** Offset 0x02A4 - Memory VDDQ Voltage + DRAM voltage (Vddq) (supply voltage for DQ/DQS of the DRAM chips) in millivolts + from 0 - default to 1435mv. +**/ + UINT16 VddqVoltage; + +/** Offset 0x02A6 - Memory VPP Voltage + DRAM voltage (Vpp) (supply voltage for VPP of the DRAM chips) in millivolts from + 0 - default to 2135mv. +**/ + UINT16 VppVoltage; + +/** Offset 0x02A8 - CPU PCIe New FOM + Enable/Disable NewFom for DEKEL Programming. 0: Disable(Default); 1: Enable + $EN_DIS +**/ + UINT8 CpuPcieNewFom[4]; + +/** Offset 0x02AC - DMI DEKEL New FOM + Enable/Disable NewFom for DEKEL Programming. 0: Disable(Default); 1: Enable + $EN_DIS +**/ + UINT8 DmiNewFom; + +/** Offset 0x02AD - Dynamic Memory Boost + 0(Default): Disable, 1: Enable. When enabled, MRC will train the Default SPD Profile, + and also the profile selected by SpdProfileSelected, to allow automatic switching + during runtime. Only valid if SpdProfileSelected is an XMP Profile, otherwise ignored. + $EN_DIS +**/ + UINT8 DynamicMemoryBoost; + +/** Offset 0x02AE - Hybrid Graphics Support + 0(Default): PEG10, 1: PEG60, 2:PEG62. Help to select Hybrid Graphics Support on Peg Port +**/ + UINT8 HgSupport; + +/** Offset 0x02AF - Realtime Memory Frequency + 0(Default): Disabled, 1: Enabled. Ignored unless SpdProfileSelected is an XMP Profile. + If enabled, MRC will train the Default SPD Profile, and also the selected XMP Profile, + to allow manually triggered switching between frequencies at runtime. + $EN_DIS +**/ + UINT8 RealtimeMemoryFrequency; + +/** Offset 0x02B0 - SaPreMemProductionRsvd + Reserved for SA Pre-Mem Production + $EN_DIS +**/ + UINT8 SaPreMemProductionRsvd[97]; + +/** Offset 0x0311 - Enable Gt CLOS + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 GtClosEnable; + +/** Offset 0x0312 - DMI Max Link Speed + Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 + Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed + 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3 +**/ + UINT8 DmiMaxLinkSpeed; + +/** Offset 0x0313 - DMI Equalization Phase 2 + DMI Equalization Phase 2. (0x0): Disable phase 2, (0x1): Enable phase 2, (0x2)(Default): + AUTO - Use the current default method + 0:Disable phase2, 1:Enable phase2, 2:Auto +**/ + UINT8 DmiGen3EqPh2Enable; + +/** Offset 0x0314 - DMI Gen3 Equalization Phase3 + DMI Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, + HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software + Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static + EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just + Phase1), Disabled(0x4): Bypass Equalization Phase 3 + 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3 +**/ + UINT8 DmiGen3EqPh3Method; + +/** Offset 0x0315 - Enable/Disable DMI GEN3 Static EQ Phase1 programming + Program DMI Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static + Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming + $EN_DIS +**/ + UINT8 DmiGen3ProgramStaticEq; + +/** Offset 0x0316 - DeEmphasis control for DMI + DeEmphasis control for DMI. 0=-6dB, 1(Default)=-3.5 dB + 0: -6dB, 1: -3.5dB +**/ + UINT8 DmiDeEmphasis; + +/** Offset 0x0317 - DMI Gen3 Root port preset values per lane + Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane +**/ + UINT8 DmiGen3RootPortPreset[8]; + +/** Offset 0x031F - DMI Gen3 End port preset values per lane + Used for programming DMI Gen3 preset values per lane. Range: 0-9, 7 is default for each lane +**/ + UINT8 DmiGen3EndPointPreset[8]; + +/** Offset 0x0327 - DMI Gen3 End port Hint values per lane + Used for programming DMI Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane +**/ + UINT8 DmiGen3EndPointHint[8]; + +/** Offset 0x032F - DMI Gen3 RxCTLEp per-Bundle control + Range: 0-15, 0 is default for each bundle, must be specified based upon platform design +**/ + UINT8 DmiGen3RxCtlePeaking[4]; + +/** Offset 0x0333 - DMI ASPM Configuration:{Combo + Set ASPM Configuration + 0:Disabled, 1:L0s, 2:L1, 3:L1L0s +**/ + UINT8 DmiAspm; + +/** Offset 0x0334 - Enable/Disable DMI GEN3 Hardware Eq + Enable/Disable DMI GEN3 Hardware Eq. Disabled(0x0)(Default): Disable Hardware Eq, + Enabled(0x1): Enable EQ Phase1 Static Presets Programming + $EN_DIS +**/ + UINT8 DmiHweq; + +/** Offset 0x0335 - Enable/Disable CPU DMI GEN3 Phase 23 Bypass + CPU DMI GEN3 Phase 23 Bypass. Disabled(0x0)(Default): Disable Phase 23 Bypass, Enabled(0x1): + Enable Phase 23 Bypass + $EN_DIS +**/ + UINT8 Gen3EqPhase23Bypass; + +/** Offset 0x0336 - Enable/Disable CPU DMI GEN3 Phase 3 Bypass + CPU DMI GEN3 Phase 3 Bypass. Disabled(0x0)(Default): Disable Phase 3 Bypass, Enabled(0x1): + Enable Phase 3 Bypass + $EN_DIS +**/ + UINT8 Gen3EqPhase3Bypass; + +/** Offset 0x0337 - Enable/Disable CPU DMI Gen3 EQ Local Transmitter Coefficient Override Enable + Program Gen3 EQ Local Transmitter Coefficient Override. Disabled(0x0)(Default): + Disable Local Transmitter Coefficient Override, Enabled(0x1): Enable Local Transmitter + Coefficient Override + $EN_DIS +**/ + UINT8 Gen3LtcoEnable; + +/** Offset 0x0338 - Enable/Disable CPU DMI Gen3 EQ Remote Transmitter Coefficient/Preset Override Enable + Program Remote Transmitter Coefficient/Preset Override. Disabled(0x0)(Default): + Disable Remote Transmitter Coefficient/Preset Override, Enabled(0x1): Enable Remote + Transmitter Coefficient/Preset Override + $EN_DIS +**/ + UINT8 Gen3RtcoRtpoEnable; + +/** Offset 0x0339 - DMI Gen3 Transmitter Pre-Cursor Coefficient + Used for programming DMI Gen3 Transmitter Pre-Cursor Coefficient . Range: 0-10, + 2 is default for each lane +**/ + UINT8 DmiGen3Ltcpre[8]; + +/** Offset 0x0341 - DMI Gen3 Transmitter Post-Cursor Coefficient + Used for programming Transmitter Post-Cursor Coefficient. Range: 0-9, 2 is default + for each lane +**/ + UINT8 DmiGen3Ltcpo[8]; + +/** Offset 0x0349 - PCIE Hw Eq Gen3 CoeffList Cm + CPU_PCIE_EQ_PARAM. Coefficient C-1. +**/ + UINT8 CpuDmiHwEqGen3CoeffListCm[8]; + +/** Offset 0x0351 - PCIE Hw Eq Gen3 CoeffList Cp + CPU_PCIE_EQ_PARAM. Coefficient C+1. +**/ + UINT8 CpuDmiHwEqGen3CoeffListCp[8]; + +/** Offset 0x0359 - Enable/Disable DMI GEN3 DmiGen3DsPresetEnable + Enable/Disable DMI GEN3 DmiGen3DsPreset. Auto(0x0)(Default): DmiGen3DsPresetEnable, + Manual(0x1): Enable DmiGen3DsPresetEnable + $EN_DIS +**/ + UINT8 DmiGen3DsPresetEnable; + +/** Offset 0x035A - DMI Gen3 Root port preset Rx values per lane + Used for programming DMI Gen3 preset values per lane. Range: 0-10, 1 is default + for each lane +**/ + UINT8 DmiGen3DsPortRxPreset[8]; + +/** Offset 0x0362 - DMI Gen3 Root port preset Tx values per lane + Used for programming DMI Gen3 preset values per lane. Range: 0-10, 7 is default + for each lane +**/ + UINT8 DmiGen3DsPortTxPreset[8]; + +/** Offset 0x036A - Enable/Disable DMI GEN3 DmiGen3UsPresetEnable + Enable/Disable DMI GEN3 DmiGen3UsPreset. Auto(0x0)(Default): DmiGen3UsPresetEnable, + Manual(0x1): Enable DmiGen3UsPresetEnable + $EN_DIS +**/ + UINT8 DmiGen3UsPresetEnable; + +/** Offset 0x036B - DMI Gen3 Root port preset Rx values per lane + Used for programming DMI Gen3 preset values per lane. Range: 0-10, 7 is default + for each lane +**/ + UINT8 DmiGen3UsPortRxPreset[8]; + +/** Offset 0x0373 - DMI Gen3 Root port preset Tx values per lane + Used for programming DMI Gen3 preset values per lane. Range: 0-10, 7 is default + for each lane +**/ + UINT8 DmiGen3UsPortTxPreset[8]; + +/** Offset 0x037B - DMI Hw Eq Gen4 CoeffList Cm + CPU_PCIE_EQ_PARAM. Coefficient C-1. +**/ + UINT8 CpuDmiHwEqGen4CoeffListCm[8]; + +/** Offset 0x0383 - DMI Hw Eq Gen4 CoeffList Cp + CPU_PCIE_EQ_PARAM. Coefficient C+1. +**/ + UINT8 CpuDmiHwEqGen4CoeffListCp[8]; + +/** Offset 0x038B - Enable/Disable CPU DMI GEN4 Phase 23 Bypass + CPU DMI GEN4 Phase 23 Bypass. Disabled(0x0)(Default): Disable Phase 23 Bypass, Enabled(0x1): + Enable Phase 23 Bypass + $EN_DIS +**/ + UINT8 Gen4EqPhase23Bypass; + +/** Offset 0x038C - Enable/Disable CPU DMI GEN4 Phase 3 Bypass + CPU DMI GEN3 Phase 4 Bypass. Disabled(0x0)(Default): Disable Phase 3 Bypass, Enabled(0x1): + Enable Phase 3 Bypass + $EN_DIS +**/ + UINT8 Gen4EqPhase3Bypass; + +/** Offset 0x038D - Enable/Disable DMI GEN4 DmiGen4DsPresetEnable + Enable/Disable DMI GEN4 DmiGen4DsPreset. Auto(0x0)(Default): DmiGen4DsPresetEnable, + Manual(0x1): Enable DmiGen4DsPresetEnable + $EN_DIS +**/ + UINT8 DmiGen4DsPresetEnable; + +/** Offset 0x038E - DMI Gen4 Root port preset Tx values per lane + Used for programming DMI Gen4 preset values per lane. Range: 0-10, 7 is default + for each lane +**/ + UINT8 DmiGen4DsPortTxPreset[8]; + +/** Offset 0x0396 - Enable/Disable CPU DMI Gen4 EQ Remote Transmitter Coefficient/Preset Override Enable + Program Remote Transmitter Coefficient/Preset Override. Disabled(0x0)(Default): + Disable Remote Transmitter Coefficient/Preset Override, Enabled(0x1): Enable Remote + Transmitter Coefficient/Preset Override + $EN_DIS +**/ + UINT8 Gen4RtcoRtpoEnable; + +/** Offset 0x0397 - Enable/Disable CPU DMI Gen4 EQ Local Transmitter Coefficient Override Enable + Program Gen3 EQ Local Transmitter Coefficient Override. Disabled(0x0)(Default): + Disable Local Transmitter Coefficient Override, Enabled(0x1): Enable Local Transmitter + Coefficient Override + $EN_DIS +**/ + UINT8 Gen4LtcoEnable; + +/** Offset 0x0398 - DMI Gen4 Transmitter Pre-Cursor Coefficient + Used for programming DMI Gen4 Transmitter Pre-Cursor Coefficient . Range: 0-10, + 7 is default for each lane +**/ + UINT8 DmiGen4Ltcpre[8]; + +/** Offset 0x03A0 - DMI Gen4 Transmitter Post-Cursor Coefficient + Used for programming DMI Gen4 Transmitter Post-Cursor Coefficient. Range: 0-9, 7 + is default for each lane +**/ + UINT8 DmiGen4Ltcpo[8]; + +/** Offset 0x03A8 - Enable/Disable DMI GEN4 DmiGen4UsPresetEnable + Enable/Disable DMI GEN4 DmiGen4UsPreset. Auto(0x0)(Default): DmiGen4UsPresetEnable, + Manual(0x1): Enable DmiGen4UsPresetEnable + $EN_DIS +**/ + UINT8 DmiGen4UsPresetEnable; + +/** Offset 0x03A9 - DMI Gen4 Root port preset Tx values per lane + Used for programming DMI Gen4 preset values per lane. Range: 0-10, 1 is default + for each lane +**/ + UINT8 DmiGen4UsPortTxPreset[8]; + +/** Offset 0x03B1 - DMI ASPM Control Configuration:{Combo + Set ASPM Control configuration + 0:Disabled, 1:L0s, 2:L1, 3:L1L0s +**/ + UINT8 DmiAspmCtrl; + +/** Offset 0x03B2 - DMI ASPM L1 exit Latency + Range: 0-7, 4 is default L1 exit Latency +**/ + UINT8 DmiAspmL1ExitLatency; + +/** Offset 0x03B3 - BIST on Reset + Enable or Disable BIST on Reset; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 BistOnReset; + +/** Offset 0x03B4 - Skip Stop PBET Timer Enable/Disable + Skip Stop PBET Timer; 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 SkipStopPbet; + +/** Offset 0x03B5 - C6DRAM power gating feature + This policy indicates whether or not BIOS should allocate PRMRR memory for C6DRAM + power gating feature.- 0: Don't allocate any PRMRR memory for C6DRAM power gating + feature.- 1: Allocate PRMRR memory for C6DRAM power gating feature. + $EN_DIS +**/ + UINT8 EnableC6Dram; + +/** Offset 0x03B6 - Over clocking support + Over clocking support; 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 OcSupport; + +/** Offset 0x03B7 - Over clocking Lock + Over clocking Lock Enable/Disable; 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 OcLock; + +/** Offset 0x03B8 - Maximum Core Turbo Ratio Override + Maximum core turbo ratio override allows to increase CPU core frequency beyond the + fused max turbo ratio limit. 0: Hardware defaults. Range: 0-85 +**/ + UINT8 CoreMaxOcRatio; + +/** Offset 0x03B9 - Core voltage mode + Core voltage mode; 0: Adaptive; 1: Override. + $EN_DIS +**/ + UINT8 CoreVoltageMode; + +/** Offset 0x03BA - Maximum clr turbo ratio override + Maximum clr turbo ratio override allows to increase CPU clr frequency beyond the + fused max turbo ratio limit. 0: Hardware defaults. Range: 0-85 +**/ + UINT8 RingMaxOcRatio; + +/** Offset 0x03BB - Hyper Threading Enable/Disable + Enable or Disable Hyper Threading; 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 HyperThreading; + +/** Offset 0x03BC - Enable or Disable CPU Ratio Override + Enable or Disable CPU Ratio Override; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 CpuRatioOverride; + +/** Offset 0x03BD - CPU ratio value + CPU ratio value. Valid Range 0 to 63 +**/ + UINT8 CpuRatio; + +/** Offset 0x03BE - Boot frequency + Sets the boot frequency starting from reset vector.- 0: Maximum battery performance. + 1: Maximum non-turbo performance. 2: Turbo performance + 0:0, 1:1, 2:2 +**/ + UINT8 BootFrequency; + +/** Offset 0x03BF - Number of active big cores + Number of active big cores(Depends on Number of big cores). Default 0xFF means to + active all system supported big cores. 0xFF: Active all big cores; 0: Disable + all big cores; 1: 1; 2: 2; 3: 3; + 0:Disable all big cores, 1:1, 2:2, 3:3, 0xFF:Active all big cores +**/ + UINT8 ActiveCoreCount; + +/** Offset 0x03C0 - Processor Early Power On Configuration FCLK setting + 0: 800 MHz (ULT/ULX). 1: 1 GHz (DT/Halo). Not supported on ULT/ULX.- + 2: 400 MHz. - 3: Reserved + 0:800 MHz, 1: 1 GHz, 2: 400 MHz, 3: Reserved +**/ + UINT8 FClkFrequency; + +/** Offset 0x03C1 - Set JTAG power in C10 and deeper power states + False: JTAG is power gated in C10 state. True: keeps the JTAG power up during C10 + and deeper power states for debug purpose. 0: False; 1: True. + 0: False, 1: True +**/ + UINT8 JtagC10PowerGateDisable; + +/** Offset 0x03C2 - Enable or Disable VMX + Enable or Disable VMX; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 VmxEnable; + +/** Offset 0x03C3 - AVX2 Ratio Offset + 0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio + vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B. +**/ + UINT8 Avx2RatioOffset; + +/** Offset 0x03C4 - AVX3 Ratio Offset + DEPRECATED +**/ + UINT8 Avx3RatioOffset; + +/** Offset 0x03C5 - BCLK Adaptive Voltage Enable + When enabled, the CPU V/F curves are aware of BCLK frequency when calculated. 0: + Disable; 1: Enable + $EN_DIS +**/ + UINT8 BclkAdaptiveVoltage; + +/** Offset 0x03C6 - core voltage override + The core voltage override which is applied to the entire range of cpu core frequencies. + Valid Range 0 to 2000 +**/ + UINT16 CoreVoltageOverride; + +/** Offset 0x03C8 - Core Turbo voltage Adaptive + Extra Turbo voltage applied to the cpu core when the cpu is operating in turbo mode. + Valid Range 0 to 2000 +**/ + UINT16 CoreVoltageAdaptive; + +/** Offset 0x03CA - Core Turbo voltage Offset + The voltage offset applied to the core while operating in turbo mode.Valid Range 0 to 1000 +**/ + UINT16 CoreVoltageOffset; + +/** Offset 0x03CC - Core PLL voltage offset + Core PLL voltage offset. 0: No offset. Range 0-15 +**/ + UINT8 CorePllVoltageOffset; + +/** Offset 0x03CD - Atom Core PLL voltage offset + Atom Core PLL voltage offset. 0: No offset. Range 0-15 +**/ + UINT8 AtomPllVoltageOffset; + +/** Offset 0x03CE - Ring Downbin + Ring Downbin enable/disable. When enabled, CPU will ensure the ring ratio is always + lower than the core ratio.0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 RingDownBin; + +/** Offset 0x03CF - Ring voltage mode + Ring voltage mode; 0: Adaptive; 1: Override. + $EN_DIS +**/ + UINT8 RingVoltageMode; + +/** Offset 0x03D0 - TjMax Offset + TjMax offset.Specified value here is clipped by pCode (125 - TjMax Offset) to support + TjMax in the range of 62 to 115 deg Celsius. Valid Range 10 - 63 +**/ + UINT8 TjMaxOffset; + +/** Offset 0x03D1 +**/ + UINT8 UnusedUpdSpace9; + +/** Offset 0x03D2 - Ring voltage override + The ring voltage override which is applied to the entire range of cpu ring frequencies. + Valid Range 0 to 2000 +**/ + UINT16 RingVoltageOverride; + +/** Offset 0x03D4 - Ring Turbo voltage Adaptive + Extra Turbo voltage applied to the cpu ring when the cpu is operating in turbo mode. + Valid Range 0 to 2000 +**/ + UINT16 RingVoltageAdaptive; + +/** Offset 0x03D6 - Ring Turbo voltage Offset + The voltage offset applied to the ring while operating in turbo mode. Valid Range 0 to 1000 +**/ + UINT16 RingVoltageOffset; + +/** Offset 0x03D8 - Enable or Disable TME + Enable or Disable TME; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 TmeEnable; + +/** Offset 0x03D9 - Enable CPU CrashLog + Enable or Disable CPU CrashLog; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 CpuCrashLogEnable; + +/** Offset 0x03DA - CPU Run Control + Enable, Disable or Do not configure CPU Run Control; 0: Disable; 1: Enable ; 2: + No Change + 0:Disabled, 1:Enabled, 2:No Change +**/ + UINT8 DebugInterfaceEnable; + +/** Offset 0x03DB - CPU Run Control Lock + Lock or Unlock CPU Run Control; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 DebugInterfaceLockEnable; + +/** Offset 0x03DC - Atom L2 voltage mode + Atom L2 voltage mode; 0: Adaptive; 1: Override. + $EN_DIS +**/ + UINT8 AtomL2VoltageMode; + +/** Offset 0x03DD +**/ + UINT8 UnusedUpdSpace10; + +/** Offset 0x03DE - Atom L2 Voltage Override + The atom L2 voltage override which is applied to the entire range of atom L2 frequencies. + Valid Range 0 to 2000 +**/ + UINT16 AtomL2VoltageOverride; + +/** Offset 0x03E0 - Atom L2 Turbo voltage Adaptive + Extra Turbo voltage applied to the atom L2 when the atom L2 is operating in turbo + mode. Valid Range 0 to 2000 +**/ + UINT16 AtomL2VoltageAdaptive; + +/** Offset 0x03E2 - Atom L2 Turbo voltage Offset + The voltage offset applied to the atom while operating in turbo mode.Valid Range 0 to 1000 +**/ + UINT16 AtomL2VoltageOffset; + +/** Offset 0x03E4 - Per-Atom-Cluster VF Offset + Array used to specifies the selected Atom Core Cluster Offset Voltage. This voltage + is specified in millivolts. +**/ + UINT16 PerAtomClusterVoltageOffset[4]; + +/** Offset 0x03EC - Per-Atom-Cluster VF Offset Prefix + Sets the PerAtomClusterVoltageOffset value as positive or negative for the selected + Core; 0: Positive ; 1: Negative. +**/ + UINT8 PerAtomClusterVoltageOffsetPrefix[4]; + +/** Offset 0x03F0 - Enable IA CEP + Control for enabling/disabling IA CEP (Current Excursion Protection)). 1: Enable; + 0: Disable + $EN_DIS +**/ + UINT8 IaCepEnable; + +/** Offset 0x03F1 - Enable GT CEP + Control for enabling/disabling GT CEP (Current Excursion Protection)). 1: Enable; + 0: Disable + $EN_DIS +**/ + UINT8 GtCepEnable; + +/** Offset 0x03F2 - Enable CPU DLVR bypass mode support + Control for enabling/disabling CPU DLVR bypass mode). 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 DlvrBypassModeEnable; + +/** Offset 0x03F3 - Number of active small cores + Number of active small cores(Depends on Number of small cores). Default 0xFF means + to active all system supported small cores. 0xFF: Active all small cores; + 0: Disable all small cores; 1: 1; 2: 2; 3: 3; + 0:Disable all small cores, 1:1, 2:2, 3:3, 0xFF:Active all small cores +**/ + UINT8 ActiveSmallCoreCount; + +/** Offset 0x03F4 - Core VF Point Offset Mode + Selects Core Voltage & Frequency Offset mode between Legacy and Selection modes. + In Legacy Mode, setting a global offset for the entire VF curve. In Selection Mode, + setting a selected VF point; 0: Legacy; 1: Selection. + 0:Legacy, 1:Selection +**/ + UINT8 CoreVfPointOffsetMode; + +/** Offset 0x03F5 +**/ + UINT8 UnusedUpdSpace11[1]; + +/** Offset 0x03F6 - Core VF Point Offset + Array used to specifies the Core Voltage Offset applied to the each selected VF + Point. This voltage is specified in millivolts. +**/ + UINT16 CoreVfPointOffset[15]; + +/** Offset 0x0414 - Core VF Point Offset Prefix + Sets the CoreVfPointOffset value as positive or negative for corresponding core + VF Point; 0: Positive ; 1: Negative. + 0:Positive, 1:Negative +**/ + UINT8 CoreVfPointOffsetPrefix[15]; + +/** Offset 0x0423 - Core VF Point Ratio + Array for the each selected Core VF Point to display the ration. +**/ + UINT8 CoreVfPointRatio[15]; + +/** Offset 0x0432 - Core VF Point Count + Number of supported Core Voltage & Frequency Point Offset +**/ + UINT8 CoreVfPointCount; + +/** Offset 0x0433 - Core VF Configuration Scope + Alows both all-core VF curve or per-core VF curve configuration; 0: All-core; + 1: Per-core. + 0:All-core, 1:Per-core +**/ + UINT8 CoreVfConfigScope; + +/** Offset 0x0434 - Per-core VF Offset + Array used to specifies the selected Core Offset Voltage. This voltage is specified + in millivolts. +**/ + UINT16 PerCoreVoltageOffset[8]; + +/** Offset 0x0444 - Per-core VF Offset Prefix + Sets the PerCoreVoltageOffset value as positive or negative for the selected Core; + 0: Positive ; 1: Negative. +**/ + UINT8 PerCoreVoltageOffsetPrefix[8]; + +/** Offset 0x044C - Per Core Max Ratio override + Enable or disable Per Core PState OC supported by writing OCMB 0x1D to program new + favored core ratio to each Core. 0: Disable, 1: enable + $EN_DIS +**/ + UINT8 PerCoreRatioOverride; + +/** Offset 0x044D - Per Core Current Max Ratio + Array for the Per Core Max Ratio +**/ + UINT8 PerCoreRatio[8]; + +/** Offset 0x0455 - Atom Cluster Max Ratio + Array for Atom Cluster Max Ratio, 4 ATOM cores are in the same Cluster and their + max core ratio will be aligned. +**/ + UINT8 AtomClusterRatio[4]; + +/** Offset 0x0459 - Core Ratio Extension Mode + Enable or disable Core Ratio above 85 Extension Mode by writing BIOS MB 0x37 to + enable FULL_RANGE_MULTIPLIER_UNLOCK_EN. 0: Disable, 1: enable + $EN_DIS +**/ + UINT8 CoreRatioExtensionMode; + +/** Offset 0x045A - Pvd Ratio Threshold + Select PVD Ratio Threshold Value from Range 1 to 40. 0 - Auto/Default. +**/ + UINT8 PvdRatioThreshold; + +/** Offset 0x045B - Support Unlimited ICCMAX + DEPRECATED + $EN_DIS +**/ + UINT8 UnlimitedIccMax; + +/** Offset 0x045C - Enable CPU CrashLog GPRs dump + Enable or Disable CPU CrashLog GPRs dump; 0: Disable; 1: Enable; 2: Only + disable Smm GPRs dump + 0:Disabled, 1:Enabled, 2:Only Smm GPRs Disabled +**/ + UINT8 CrashLogGprs; + +/** Offset 0x045D - Ring VF Point Offset Mode + Selects Ring Voltage & Frequency Offset mode between Legacy and Selection modes. + In Legacy Mode, setting a global offset for the entire VF curve. In Selection Mode, + setting a selected VF point; 0: Legacy; 1: Selection. + 0:Legacy, 1:Selection +**/ + UINT8 RingVfPointOffsetMode; + +/** Offset 0x045E - Ring VF Point Offset + Array used to specifies the Ring Voltage Offset applied to the each selected VF + Point. This voltage is specified in millivolts. +**/ + UINT16 RingVfPointOffset[15]; + +/** Offset 0x047C - Ring VF Point Offset Prefix + Sets the RingVfPointOffset value as positive or negative for corresponding core + VF Point; 0: Positive ; 1: Negative. +**/ + UINT8 RingVfPointOffsetPrefix[15]; + +/** Offset 0x048B - Ring VF Point Ratio + Array for the each selected Ring VF Point to display the ration. +**/ + UINT8 RingVfPointRatio[15]; + +/** Offset 0x049A - Ring VF Point Count + Number of supported Ring Voltage & Frequency Point Offset +**/ + UINT8 RingVfPointCount; + +/** Offset 0x049B - BCLK Frequency Source + Clock source of BCLK OC frequency, 1:CPU BCLK, 2:PCH BCLK, 3:External CLK + 1:CPU BCLK, 2:PCH BCLK, 3:External CLK +**/ + UINT8 BclkSource; + +/** Offset 0x049C - GPIO Override + Gpio Override Level - FSP will not configure any GPIOs and rely on GPIO setings + before moved to FSP. Available configurations 0: Disable; 1: Level 1 - Skips GPIO + configuration in PEI/FSPM/FSPT phase;2: Level 2 - Reserved for future use +**/ + UINT8 GpioOverride; + +/** Offset 0x049D +**/ + UINT8 UnusedUpdSpace12[3]; + +/** Offset 0x04A0 - CPU BCLK OC Frequency + CPU BCLK OC Frequency in 10KHz units increasing. Value 9800 (10KHz) = 98MHz 0 + - Auto. Range is 8000-50000 (10KHz). +**/ + UINT32 CpuBclkOcFrequency; + +/** Offset 0x04A4 - Bitmask of disable cores + Core mask is a bitwise indication of which core should be disabled. 0x00=Default; + Bit 0 - core 0, bit 7 - core 7. +**/ + UINT32 DisablePerCoreMask; + +/** Offset 0x04A8 - Bitmask of disable atoms + DEPRECATED +**/ + UINT32 DisablePerAtomMask; + +/** Offset 0x04AC - Sa PLL Frequency + Configure Sa PLL Frequency. 0: 3200MHz , 1: 1600MHz + 0: 3200MHz, 1: 1600MHz +**/ + UINT8 SaPllFreqOverride; + +/** Offset 0x04AD - Skip override boot mode When Fw Update. + When set to TRUE and boot mode is BOOT_ON_FLASH_UPDATE, skip setting boot mode to + BOOT_WITH_FULL_CONFIGURATION in PEI memory init. + $EN_DIS +**/ + UINT8 SiSkipOverrideBootModeWhenFwUpdate; + +/** Offset 0x04AE - TSC HW Fixup disable + TSC HW Fixup disable during TSC copy from PMA to APIC. 0: Enable; 1: Disable + 0:Enable, 1:Disable +**/ + UINT8 TscDisableHwFixup; + +/** Offset 0x04AF - Support IA Unlimited ICCMAX + Support IA Unlimited ICCMAX up to maximum value 512A; 0: Disabled; 1: Enabled. + $EN_DIS +**/ + UINT8 IaIccUnlimitedMode; + +/** Offset 0x04B0 - IA ICCMAX + IA ICCMAX value is represented in 1/4 A increments. A value of 400 = 100A. 4 + . Range is 4-2047. +**/ + UINT16 IaIccMax; + +/** Offset 0x04B2 - Support GT Unlimited ICCMAX + Support GT Unlimited ICCMAX up to maximum value 512A; 0: Disabled; 1: Enabled. + $EN_DIS +**/ + UINT8 GtIccUnlimitedMode; + +/** Offset 0x04B3 +**/ + UINT8 UnusedUpdSpace13; + +/** Offset 0x04B4 - GT ICCMAX + GT ICCMAX value is represented in 1/4 A increments. A value of 400 = 100A. 4 + . Range is 4-2047. +**/ + UINT16 GtIccMax; + +/** Offset 0x04B6 - TVB Down Bins for Temp Threshold 0 + Down Bins (delta) for Temperature Threshold 0. When running above Temperature Threshold + 0, the ratio will be clipped by MAX_RATIO[n]-This value, when TVB ratio clipping + is enabled. Default is 1. +**/ + UINT8 TvbDownBinsTempThreshold0; + +/** Offset 0x04B7 - TVB Temperature Threshold 0 + TVB Temp (degrees C) - Temperature Threshold 0. Running ABOVE this temperature will + clip delta Down Bins for Threshold 0 from the resolved OC Ratio, when TVB ratio + clipping is enabled. Default is 70. +**/ + UINT8 TvbTempThreshold0; + +/** Offset 0x04B8 - TVB Temperature Threshold 1 + TVB Temp (degrees C) - Temperature Threshold 1. Running ABOVE this temperature will + clip delta Down Bins for Threshold 1 from the resolved OC Ratio, when TVB ratio + clipping is enabled. Default is 100. +**/ + UINT8 TvbTempThreshold1; + +/** Offset 0x04B9 - TVB Down Bins for Temp Threshold 1 + Down Bins (delta) for Temperature Threshold 1. When running above Temperature Threshold + 1, the ratio will be clipped by MAX_RATIO[n]-Down Bin Threshold 1-This value, when + TVB ratio clipping is enabled. Default is 2. +**/ + UINT8 TvbDownBinsTempThreshold1; + +/** Offset 0x04BA - FLL Overclock Mode Enable + Select FLL Mode Value from 0 to 3. 0x0 = no overclocking, 0x1 = ratio overclocking + with nominal (0.5-1x) reference clock frequency, 0x2 = BCLK overclocking with elevated + (1-3x) reference clock frequency, 0x3 = BCLK overclocking with extreme elevated + (3-5x) reference clock frequency and ratio limited to 63. + $EN_DIS +**/ + UINT8 FllOcModeEn; + +/** Offset 0x04BB - FLL Overclock Mode + Select FLL Mode Value from 0 to 3. 0x0 = no overclocking, 0x1 = ratio overclocking + with nominal (0.5-1x) reference clock frequency, 0x2 = BCLK overclocking with elevated + (1-3x) reference clock frequency, 0x3 = BCLK overclocking with extreme elevated + (3-5x) reference clock frequency and ratio limited to 63. +**/ + UINT8 FllOverclockMode; + +/** Offset 0x04BC - Configuration for boot TDP selection + Configuration for boot TDP selection; 0: TDP Nominal; 1: TDP Down; 2: TDP + Up;0xFF : Deactivate +**/ + UINT8 ConfigTdpLevel; + +/** Offset 0x04BD +**/ + UINT8 UnusedUpdSpace14[3]; + +/** Offset 0x04C0 - Short term Power Limit value for custom cTDP level 1 + Short term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid + Range 0 to 4095875 in Step size of 125 +**/ + UINT32 CustomPowerLimit1; + +/** Offset 0x04C4 - Enhanced Thermal Turbo Mode + When eTVB mode is enabled user will be clipped when temperatures reach 70C 0: + Disabled; 1: Enabled. + $EN_DIS +**/ + UINT8 Etvb; + +/** Offset 0x04C5 - UnderVolt Protection + When UnderVolt Protection is enabled, user will be not be able to program under + voltage in OS runtime. 0: Disabled; 1: Enabled + $EN_DIS +**/ + UINT8 UnderVoltProtection; + +/** Offset 0x04C6 - ReservedCpuPreMem + Reserved for Cpu Pre-Mem + $EN_DIS +**/ + UINT8 ReservedCpuPreMem[6]; + +/** Offset 0x04CC - BiosGuard + Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable + $EN_DIS +**/ + UINT8 BiosGuard; + +/** Offset 0x04CD +**/ + UINT8 BiosGuardToolsInterface; + +/** Offset 0x04CE - Txt + Enable/Disable. 0: Disable, Enable/Disable Txt feature, 1: enable + $EN_DIS +**/ + UINT8 Txt; + +/** Offset 0x04CF +**/ + UINT8 UnusedUpdSpace15; + +/** Offset 0x04D0 - PrmrrSize + Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable +**/ + UINT32 PrmrrSize; + +/** Offset 0x04D4 - SinitMemorySize + Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable +**/ + UINT32 SinitMemorySize; + +/** Offset 0x04D8 - TxtDprMemoryBase + Enable/Disable. 0: Disable, define default value of TxtDprMemoryBase , 1: enable +**/ + UINT64 TxtDprMemoryBase; + +/** Offset 0x04E0 - TxtHeapMemorySize + Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable +**/ + UINT32 TxtHeapMemorySize; + +/** Offset 0x04E4 - TxtDprMemorySize + Enable/Disable. 0: Disable, define default value of TxtDprMemorySize , 1: enable +**/ + UINT32 TxtDprMemorySize; + +/** Offset 0x04E8 - BiosAcmBase + Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable +**/ + UINT32 BiosAcmBase; + +/** Offset 0x04EC - BiosAcmSize + Enable/Disable. 0: Disable, define default value of BiosAcmSize , 1: enable +**/ + UINT32 BiosAcmSize; + +/** Offset 0x04F0 - ApStartupBase + Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable +**/ + UINT32 ApStartupBase; + +/** Offset 0x04F4 - TgaSize + Enable/Disable. 0: Disable, define default value of TgaSize , 1: enable +**/ + UINT32 TgaSize; + +/** Offset 0x04F8 - TxtLcpPdBase + Enable/Disable. 0: Disable, define default value of TxtLcpPdBase , 1: enable +**/ + UINT64 TxtLcpPdBase; + +/** Offset 0x0500 - TxtLcpPdSize + Enable/Disable. 0: Disable, define default value of TxtLcpPdSize , 1: enable +**/ + UINT64 TxtLcpPdSize; + +/** Offset 0x0508 - IsTPMPresence + IsTPMPresence default values +**/ + UINT8 IsTPMPresence; + +/** Offset 0x0509 - ReservedSecurityPreMem + Reserved for Security Pre-Mem + $EN_DIS +**/ + UINT8 ReservedSecurityPreMem[32]; + +/** Offset 0x0529 - Enable PCH HSIO PCIE Rx Set Ctle + Enable PCH PCIe Gen 3 Set CTLE Value. +**/ + UINT8 PchPcieHsioRxSetCtleEnable[28]; + +/** Offset 0x0545 - PCH HSIO PCIE Rx Set Ctle Value + PCH PCIe Gen 3 Set CTLE Value. +**/ + UINT8 PchPcieHsioRxSetCtle[28]; + +/** Offset 0x0561 - Enble PCH HSIO PCIE TX Gen 1 Downscale Amplitude Adjustment value override + 0: Disable; 1: Enable. +**/ + UINT8 PchPcieHsioTxGen1DownscaleAmpEnable[28]; + +/** Offset 0x057D - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value + PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value. +**/ + UINT8 PchPcieHsioTxGen1DownscaleAmp[28]; + +/** Offset 0x0599 - Enable PCH HSIO PCIE TX Gen 2 Downscale Amplitude Adjustment value override + 0: Disable; 1: Enable. +**/ + UINT8 PchPcieHsioTxGen2DownscaleAmpEnable[28]; + +/** Offset 0x05B5 - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value + PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value. +**/ + UINT8 PchPcieHsioTxGen2DownscaleAmp[28]; + +/** Offset 0x05D1 - Enable PCH HSIO PCIE TX Gen 3 Downscale Amplitude Adjustment value override + 0: Disable; 1: Enable. +**/ + UINT8 PchPcieHsioTxGen3DownscaleAmpEnable[28]; + +/** Offset 0x05ED - PCH HSIO PCIE Gen 3 TX Output Downscale Amplitude Adjustment value + PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value. +**/ + UINT8 PchPcieHsioTxGen3DownscaleAmp[28]; + +/** Offset 0x0609 - Enable PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment Setting value override + 0: Disable; 1: Enable. +**/ + UINT8 PchPcieHsioTxGen1DeEmphEnable[28]; + +/** Offset 0x0625 - PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment value + PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting. +**/ + UINT8 PchPcieHsioTxGen1DeEmph[28]; + +/** Offset 0x0641 - Enable PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting value override + 0: Disable; 1: Enable. +**/ + UINT8 PchPcieHsioTxGen2DeEmph3p5Enable[28]; + +/** Offset 0x065D - PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment value + PCH PCIe Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting. +**/ + UINT8 PchPcieHsioTxGen2DeEmph3p5[28]; + +/** Offset 0x0679 - Enable PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting value override + 0: Disable; 1: Enable. +**/ + UINT8 PchPcieHsioTxGen2DeEmph6p0Enable[28]; + +/** Offset 0x0695 - PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment value + PCH PCIe Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting. +**/ + UINT8 PchPcieHsioTxGen2DeEmph6p0[28]; + +/** Offset 0x06B1 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override + 0: Disable; 1: Enable. +**/ + UINT8 PchSataHsioRxGen1EqBoostMagEnable[8]; + +/** Offset 0x06B9 - PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value + PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value. +**/ + UINT8 PchSataHsioRxGen1EqBoostMag[8]; + +/** Offset 0x06C1 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override + 0: Disable; 1: Enable. +**/ + UINT8 PchSataHsioRxGen2EqBoostMagEnable[8]; + +/** Offset 0x06C9 - PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value + PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value. +**/ + UINT8 PchSataHsioRxGen2EqBoostMag[8]; + +/** Offset 0x06D1 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override + 0: Disable; 1: Enable. +**/ + UINT8 PchSataHsioRxGen3EqBoostMagEnable[8]; + +/** Offset 0x06D9 - PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value + PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value. +**/ + UINT8 PchSataHsioRxGen3EqBoostMag[8]; + +/** Offset 0x06E1 - Enable PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value override + 0: Disable; 1: Enable. +**/ + UINT8 PchSataHsioTxGen1DownscaleAmpEnable[8]; + +/** Offset 0x06E9 - PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value + PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value. +**/ + UINT8 PchSataHsioTxGen1DownscaleAmp[8]; + +/** Offset 0x06F1 - Enable PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value override + 0: Disable; 1: Enable. +**/ + UINT8 PchSataHsioTxGen2DownscaleAmpEnable[8]; + +/** Offset 0x06F9 - PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value + PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value. +**/ + UINT8 PchSataHsioTxGen2DownscaleAmp[8]; + +/** Offset 0x0701 - Enable PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value override + 0: Disable; 1: Enable. +**/ + UINT8 PchSataHsioTxGen3DownscaleAmpEnable[8]; + +/** Offset 0x0709 - PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value + PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value. +**/ + UINT8 PchSataHsioTxGen3DownscaleAmp[8]; + +/** Offset 0x0711 - Enable PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting value override + 0: Disable; 1: Enable. +**/ + UINT8 PchSataHsioTxGen1DeEmphEnable[8]; + +/** Offset 0x0719 - PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting + PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting. +**/ + UINT8 PchSataHsioTxGen1DeEmph[8]; + +/** Offset 0x0721 - Enable PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting value override + 0: Disable; 1: Enable. +**/ + UINT8 PchSataHsioTxGen2DeEmphEnable[8]; + +/** Offset 0x0729 - PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting + PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting. +**/ + UINT8 PchSataHsioTxGen2DeEmph[8]; + +/** Offset 0x0731 - Enable PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override + 0: Disable; 1: Enable. +**/ + UINT8 PchSataHsioTxGen3DeEmphEnable[8]; + +/** Offset 0x0739 - PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting + PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting. +**/ + UINT8 PchSataHsioTxGen3DeEmph[8]; + +/** Offset 0x0741 - PCH LPC Enhanced Port 80 Decoding + Original LPC only decodes one byte of port 80h. + $EN_DIS +**/ + UINT8 PchLpcEnhancePort8xhDecoding; + +/** Offset 0x0742 - PCH Port80 Route + Control where the Port 80h cycles are sent, 0: LPC; 1: PCI. + 0:LPC, 1:PCI +**/ + UINT8 PchPort80Route; + +/** Offset 0x0743 - Enable SMBus ARP support + Enable SMBus ARP support. + $EN_DIS +**/ + UINT8 SmbusArpEnable; + +/** Offset 0x0744 - Number of RsvdSmbusAddressTable. + The number of elements in the RsvdSmbusAddressTable. +**/ + UINT8 PchNumRsvdSmbusAddresses; + +/** Offset 0x0745 +**/ + UINT8 UnusedUpdSpace16; + +/** Offset 0x0746 - SMBUS Base Address + SMBUS Base Address (IO space). +**/ + UINT16 PchSmbusIoBase; + +/** Offset 0x0748 - Enable SMBus Alert Pin + Enable SMBus Alert Pin. + $EN_DIS +**/ + UINT8 PchSmbAlertEnable; + +/** Offset 0x0749 - Usage type for ClkSrc + 0-23: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use + (free running), 0xFF: not used +**/ + UINT8 PcieClkSrcUsage[18]; + +/** Offset 0x075B +**/ + UINT8 PcieClkSrcUsageRsvd[14]; + +/** Offset 0x0769 - ClkReq-to-ClkSrc mapping + Number of ClkReq signal assigned to ClkSrc +**/ + UINT8 PcieClkSrcClkReq[18]; + +/** Offset 0x077B +**/ + UINT8 PcieClkSrcClkReqRsvd[14]; + +/** Offset 0x0789 +**/ + UINT8 UnusedUpdSpace17[3]; + +/** Offset 0x078C - Clk Req GPIO Pin + Select Clk Req Pin. Refer to GPIO_*_MUXING_SRC_CLKREQ_x* for possible values. +**/ + UINT32 PcieClkReqGpioMux[18]; + +/** Offset 0x07D4 - Point of RsvdSmbusAddressTable + Array of addresses reserved for non-ARP-capable SMBus devices. +**/ + UINT32 RsvdSmbusAddressTablePtr; + +/** Offset 0x07D8 - Enable PCIE RP Mask + Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 + for port1, bit1 for port2, and so on. +**/ + UINT32 PcieRpEnableMask; + +/** Offset 0x07DC - VC Type + Virtual Channel Type Select: 0: VC0, 1: VC1. + 0: VC0, 1: VC1 +**/ + UINT8 PchHdaVcType; + +/** Offset 0x07DD - Universal Audio Architecture compliance for DSP enabled system + 0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox + driver or SST driver supported). + $EN_DIS +**/ + UINT8 PchHdaDspUaaCompliance; + +/** Offset 0x07DE - Enable HD Audio Link + Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1. + $EN_DIS +**/ + UINT8 PchHdaAudioLinkHdaEnable; + +/** Offset 0x07DF - Enable HDA SDI lanes + Enable/disable HDA SDI lanes. +**/ + UINT8 PchHdaSdiEnable[2]; + +/** Offset 0x07E1 - HDA Power/Clock Gating (PGD/CGD) + Enable/Disable HD Audio Power and Clock Gating(POR: Enable). 0: PLATFORM_POR, 1: + FORCE_ENABLE, 2: FORCE_DISABLE. + 0: POR, 1: Force Enable, 2: Force Disable +**/ + UINT8 PchHdaTestPowerClockGating; + +/** Offset 0x07E2 - Enable HD Audio DMIC_N Link + Enable/disable HD Audio DMIC1 link. Muxed with SNDW3. +**/ + UINT8 PchHdaAudioLinkDmicEnable[2]; + +/** Offset 0x07E4 - DMIC ClkA Pin Muxing (N - DMIC number) + Determines DMIC ClkA Pin muxing. See GPIO_*_MUXING_DMIC_CLKA_* +**/ + UINT32 PchHdaAudioLinkDmicClkAPinMux[2]; + +/** Offset 0x07EC - DMIC ClkB Pin Muxing + Determines DMIC ClkA Pin muxing. See GPIO_*_MUXING_DMIC_CLKB_* +**/ + UINT32 PchHdaAudioLinkDmicClkBPinMux[2]; + +/** Offset 0x07F4 - Enable HD Audio DSP + Enable/disable HD Audio DSP feature. + $EN_DIS +**/ + UINT8 PchHdaDspEnable; + +/** Offset 0x07F5 +**/ + UINT8 UnusedUpdSpace18[3]; + +/** Offset 0x07F8 - DMIC Data Pin Muxing + Determines DMIC Data Pin muxing. See GPIO_*_MUXING_DMIC_DATA_* +**/ + UINT32 PchHdaAudioLinkDmicDataPinMux[2]; + +/** Offset 0x0800 - Enable HD Audio SSP0 Link + Enable/disable HD Audio SSP_N/I2S link. Muxed with HDA. N-number 0-5 +**/ + UINT8 PchHdaAudioLinkSspEnable[6]; + +/** Offset 0x0806 - Enable HD Audio SoundWire#N Link + Enable/disable HD Audio SNDW#N link. Muxed with HDA. +**/ + UINT8 PchHdaAudioLinkSndwEnable[4]; + +/** Offset 0x080A - iDisp-Link Frequency + iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz. + 4: 96MHz, 3: 48MHz +**/ + UINT8 PchHdaIDispLinkFrequency; + +/** Offset 0x080B - iDisp-Link T-mode + iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 2: 4T, 3: 8T, 4: 16T + 0: 2T, 2: 4T, 3: 8T, 4: 16T +**/ + UINT8 PchHdaIDispLinkTmode; + +/** Offset 0x080C - iDisplay Audio Codec disconnection + 0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable. + $EN_DIS +**/ + UINT8 PchHdaIDispCodecDisconnect; + +/** Offset 0x080D - CNVi DDR RFI Mitigation + Enable/Disable DDR RFI Mitigation. Default is ENABLE. 0: DISABLE, 1: ENABLE + $EN_DIS +**/ + UINT8 CnviDdrRfim; + +/** Offset 0x080E - Debug Interfaces + Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, + BIT2 - Not used. +**/ + UINT8 PcdDebugInterfaceFlags; + +/** Offset 0x080F - Serial Io Uart Debug Controller Number + Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT + Core interface, it cannot be used for debug purpose. + 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2 +**/ + UINT8 SerialIoUartDebugControllerNumber; + +/** Offset 0x0810 - Serial Io Uart Debug Auto Flow + Enables UART hardware flow control, CTS and RTS lines. + $EN_DIS +**/ + UINT8 SerialIoUartDebugAutoFlow; + +/** Offset 0x0811 +**/ + UINT8 UnusedUpdSpace19[3]; + +/** Offset 0x0814 - Serial Io Uart Debug BaudRate + Set default BaudRate Supported from 0 - default to 6000000. Recommended values 9600, + 19200, 57600, 115200, 460800, 921600, 1500000, 1843200, 3000000, 3686400, 6000000 +**/ + UINT32 SerialIoUartDebugBaudRate; + +/** Offset 0x0818 - Serial Io Uart Debug Parity + Set default Parity. + 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity +**/ + UINT8 SerialIoUartDebugParity; + +/** Offset 0x0819 - Serial Io Uart Debug Stop Bits + Set default stop bits. + 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits +**/ + UINT8 SerialIoUartDebugStopBits; + +/** Offset 0x081A - Serial Io Uart Debug Data Bits + Set default word length. 0: Default, 5,6,7,8 + 5:5BITS, 6:6BITS, 7:7BITS, 8:8BITS +**/ + UINT8 SerialIoUartDebugDataBits; + +/** Offset 0x081B +**/ + UINT8 UnusedUpdSpace20; + +/** Offset 0x081C - Serial Io Uart Debug Mmio Base + Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIoUartMode + = SerialIoUartPci. +**/ + UINT32 SerialIoUartDebugMmioBase; + +/** Offset 0x0820 - ISA Serial Base selection + Select ISA Serial Base address. Default is 0x3F8. + 0:0x3F8, 1:0x2F8 +**/ + UINT8 PcdIsaSerialUartBase; + +/** Offset 0x0821 - GT PLL voltage offset + Core PLL voltage offset. 0: No offset. Range 0-15 +**/ + UINT8 GtPllVoltageOffset; + +/** Offset 0x0822 - Ring PLL voltage offset + Core PLL voltage offset. 0: No offset. Range 0-15 +**/ + UINT8 RingPllVoltageOffset; + +/** Offset 0x0823 - System Agent PLL voltage offset + Core PLL voltage offset. 0: No offset. Range 0-15 +**/ + UINT8 SaPllVoltageOffset; + +/** Offset 0x0824 - Memory Controller PLL voltage offset + Core PLL voltage offset. 0: No offset. Range 0-15 +**/ + UINT8 McPllVoltageOffset; + +/** Offset 0x0825 - MRC Safe Config + Enables/Disable MRC Safe Config + $EN_DIS +**/ + UINT8 MrcSafeConfig; + +/** Offset 0x0826 - TCSS Thunderbolt PCIE Root Port 0 Enable + Set TCSS Thunderbolt PCIE Root Port 0. 0:Disabled 1:Enabled + $EN_DIS +**/ + UINT8 TcssItbtPcie0En; + +/** Offset 0x0827 - TCSS Thunderbolt PCIE Root Port 1 Enable + Set TCSS Thunderbolt PCIE Root Port 1. 0:Disabled 1:Enabled + $EN_DIS +**/ + UINT8 TcssItbtPcie1En; + +/** Offset 0x0828 - TCSS Thunderbolt PCIE Root Port 2 Enable + Set TCSS Thunderbolt PCIE Root Port 2. 0:Disabled 1:Enabled + $EN_DIS +**/ + UINT8 TcssItbtPcie2En; + +/** Offset 0x0829 - TCSS Thunderbolt PCIE Root Port 3 Enable + Set TCSS Thunderbolt PCIE Root Port 3. 0:Disabled 1:Enabled + $EN_DIS +**/ + UINT8 TcssItbtPcie3En; + +/** Offset 0x082A - TCSS USB HOST (xHCI) Enable + Set TCSS XHCI. 0:Disabled 1:Enabled - Must be enabled if xDCI is enabled below + $EN_DIS +**/ + UINT8 TcssXhciEn; + +/** Offset 0x082B - TCSS USB DEVICE (xDCI) Enable + Set TCSS XDCI. 0:Disabled 1:Enabled - xHCI must be enabled if xDCI is enabled + $EN_DIS +**/ + UINT8 TcssXdciEn; + +/** Offset 0x082C - TCSS DMA0 Enable + Set TCSS DMA0. 0:Disabled 1:Enabled + $EN_DIS +**/ + UINT8 TcssDma0En; + +/** Offset 0x082D - TCSS DMA1 Enable + Set TCSS DMA1. 0:Disabled 1:Enabled + $EN_DIS +**/ + UINT8 TcssDma1En; + +/** Offset 0x082E - PcdSerialDebugBaudRate + Baud Rate for Serial Debug Messages. 3:9600, 4:19200, 6:56700, 7:115200. + 3:9600, 4:19200, 6:56700, 7:115200 +**/ + UINT8 PcdSerialDebugBaudRate; + +/** Offset 0x082F - HobBufferSize + Size to set HOB Buffer. 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value(assuming 63KB + total HOB size). + 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value +**/ + UINT8 HobBufferSize; + +/** Offset 0x0830 - Early Command Training + Enables/Disable Early Command Training + $EN_DIS +**/ + UINT8 ECT; + +/** Offset 0x0831 - SenseAmp Offset Training + Enables/Disable SenseAmp Offset Training + $EN_DIS +**/ + UINT8 SOT; + +/** Offset 0x0832 - Early ReadMPR Timing Centering 2D + Enables/Disable Early ReadMPR Timing Centering 2D + $EN_DIS +**/ + UINT8 ERDMPRTC2D; + +/** Offset 0x0833 - Read MPR Training + Enables/Disable Read MPR Training + $EN_DIS +**/ + UINT8 RDMPRT; + +/** Offset 0x0834 - Receive Enable Training + Enables/Disable Receive Enable Training + $EN_DIS +**/ + UINT8 RCVET; + +/** Offset 0x0835 - Jedec Write Leveling + Enables/Disable Jedec Write Leveling + $EN_DIS +**/ + UINT8 JWRL; + +/** Offset 0x0836 - Early Write Time Centering 2D + Enables/Disable Early Write Time Centering 2D + $EN_DIS +**/ + UINT8 EWRTC2D; + +/** Offset 0x0837 - Early Read Time Centering 2D + Enables/Disable Early Read Time Centering 2D + $EN_DIS +**/ + UINT8 ERDTC2D; + +/** Offset 0x0838 - Write Timing Centering 1D + Enables/Disable Write Timing Centering 1D + $EN_DIS +**/ + UINT8 WRTC1D; + +/** Offset 0x0839 - Write Voltage Centering 1D + Enables/Disable Write Voltage Centering 1D + $EN_DIS +**/ + UINT8 WRVC1D; + +/** Offset 0x083A - Read Timing Centering 1D + Enables/Disable Read Timing Centering 1D + $EN_DIS +**/ + UINT8 RDTC1D; + +/** Offset 0x083B - Dimm ODT Training + Enables/Disable Dimm ODT Training + $EN_DIS +**/ + UINT8 DIMMODTT; + +/** Offset 0x083C - DIMM RON Training + Enables/Disable DIMM RON Training + $EN_DIS +**/ + UINT8 DIMMRONT; + +/** Offset 0x083D - Write Drive Strength/Equalization 2D + Enables/Disable Write Drive Strength/Equalization 2D + $EN_DIS +**/ + UINT8 WRDSEQT; + +/** Offset 0x083E - Write Slew Rate Training + Enables/Disable Write Slew Rate Training + $EN_DIS +**/ + UINT8 WRSRT; + +/** Offset 0x083F - Read ODT Training + Enables/Disable Read ODT Training + $EN_DIS +**/ + UINT8 RDODTT; + +/** Offset 0x0840 - Read Equalization Training + Enables/Disable Read Equalization Training + $EN_DIS +**/ + UINT8 RDEQT; + +/** Offset 0x0841 - Read Amplifier Training + Enables/Disable Read Amplifier Training + $EN_DIS +**/ + UINT8 RDAPT; + +/** Offset 0x0842 - Write Timing Centering 2D + Enables/Disable Write Timing Centering 2D + $EN_DIS +**/ + UINT8 WRTC2D; + +/** Offset 0x0843 - Read Timing Centering 2D + Enables/Disable Read Timing Centering 2D + $EN_DIS +**/ + UINT8 RDTC2D; + +/** Offset 0x0844 - Write Voltage Centering 2D + Enables/Disable Write Voltage Centering 2D + $EN_DIS +**/ + UINT8 WRVC2D; + +/** Offset 0x0845 - Read Voltage Centering 2D + Enables/Disable Read Voltage Centering 2D + $EN_DIS +**/ + UINT8 RDVC2D; + +/** Offset 0x0846 - Command Voltage Centering + Enables/Disable Command Voltage Centering + $EN_DIS +**/ + UINT8 CMDVC; + +/** Offset 0x0847 - Late Command Training + Enables/Disable Late Command Training + $EN_DIS +**/ + UINT8 LCT; + +/** Offset 0x0848 - Round Trip Latency Training + Enables/Disable Round Trip Latency Training + $EN_DIS +**/ + UINT8 RTL; + +/** Offset 0x0849 - Turn Around Timing Training + Enables/Disable Turn Around Timing Training + $EN_DIS +**/ + UINT8 TAT; + +/** Offset 0x084A - Memory Test + Enables/Disable Memory Test + $EN_DIS +**/ + UINT8 MEMTST; + +/** Offset 0x084B - DIMM SPD Alias Test + Enables/Disable DIMM SPD Alias Test + $EN_DIS +**/ + UINT8 ALIASCHK; + +/** Offset 0x084C - Receive Enable Centering 1D + Enables/Disable Receive Enable Centering 1D + $EN_DIS +**/ + UINT8 RCVENC1D; + +/** Offset 0x084D - Retrain Margin Check + Enables/Disable Retrain Margin Check + $EN_DIS +**/ + UINT8 RMC; + +/** Offset 0x084E - Write Drive Strength Up/Dn independently + Enables/Disable Write Drive Strength Up/Dn independently + $EN_DIS +**/ + UINT8 WRDSUDT; + +/** Offset 0x084F - ECC Support + Enables/Disable ECC Support + $EN_DIS +**/ + UINT8 EccSupport; + +/** Offset 0x0850 - Memory Remap + Enables/Disable Memory Remap + $EN_DIS +**/ + UINT8 RemapEnable; + +/** Offset 0x0851 - Rank Interleave support + Enables/Disable Rank Interleave support. NOTE: RI and HORI can not be enabled at + the same time. + $EN_DIS +**/ + UINT8 RankInterleave; + +/** Offset 0x0852 - Enhanced Interleave support + Enables/Disable Enhanced Interleave support + $EN_DIS +**/ + UINT8 EnhancedInterleave; + +/** Offset 0x0853 - Ch Hash Support + Enable/Disable Channel Hash Support. NOTE: ONLY if Memory interleaved Mode + $EN_DIS +**/ + UINT8 ChHashEnable; + +/** Offset 0x0854 - Ch Hash Settings Override + Channel Hash Settings Override + $EN_DIS +**/ + UINT8 ChHashOverride; + +/** Offset 0x0855 - Extern Therm Status + Enables/Disable Extern Therm Status + $EN_DIS +**/ + UINT8 EnableExtts; + +/** Offset 0x0856 - DDR PowerDown and idle counter + Enables/Disable DDR PowerDown and idle counter(For LPDDR Only) + $EN_DIS +**/ + UINT8 EnablePwrDn; + +/** Offset 0x0857 - DDR PowerDown and idle counter + Enables/Disable DDR PowerDown and idle counter(For LPDDR Only) + $EN_DIS +**/ + UINT8 EnablePwrDnLpddr; + +/** Offset 0x0858 - SelfRefresh Enable + Enables/Disable SelfRefresh Enable + $EN_DIS +**/ + UINT8 SrefCfgEna; + +/** Offset 0x0859 - Throttler CKEMin Defeature + Enables/Disable Throttler CKEMin Defeature(For LPDDR Only) + $EN_DIS +**/ + UINT8 ThrtCkeMinDefeatLpddr; + +/** Offset 0x085A - Throttler CKEMin Defeature + Enables/Disable Throttler CKEMin Defeature + $EN_DIS +**/ + UINT8 ThrtCkeMinDefeat; + +/** Offset 0x085B - Row Hammer Select + Row Hammer Select + 0:Disable, 1:RFM, 2:pTRR +**/ + UINT8 RhSelect; + +/** Offset 0x085C - Exit On Failure (MRC) + Enables/Disable Exit On Failure (MRC) + $EN_DIS +**/ + UINT8 ExitOnFailure; + +/** Offset 0x085D - New Features 1 - MRC + New Feature Enabling 1, 0:Disable, 1:Enable + 0:Disable, 1:Enable +**/ + UINT8 NewFeatureEnable1; + +/** Offset 0x085E - New Features 2 - MRC + New Feature Enabling 2, 0:Disable, 1:Enable + 0:Disable, 1:Enable +**/ + UINT8 NewFeatureEnable2; + +/** Offset 0x085F - Duty Cycle Correction Training + Enable/Disable Duty Cycle Correction Training + $EN_DIS +**/ + UINT8 DCC; + +/** Offset 0x0860 - Read Voltage Centering 1D + Enable/Disable Read Voltage Centering 1D + $EN_DIS +**/ + UINT8 RDVC1D; + +/** Offset 0x0861 - TxDqTCO Comp Training + Enable/Disable TxDqTCO Comp Training + $EN_DIS +**/ + UINT8 TXTCO; + +/** Offset 0x0862 - ClkTCO Comp Training + Enable/Disable ClkTCO Comp Training + $EN_DIS +**/ + UINT8 CLKTCO; + +/** Offset 0x0863 - CMD Slew Rate Training + Enable/Disable CMD Slew Rate Training + $EN_DIS +**/ + UINT8 CMDSR; + +/** Offset 0x0864 - CMD Drive Strength and Tx Equalization + Enable/Disable CMD Drive Strength and Tx Equalization + $EN_DIS +**/ + UINT8 CMDDSEQ; + +/** Offset 0x0865 - DIMM CA ODT Training + Enable/Disable DIMM CA ODT Training + $EN_DIS +**/ + UINT8 DIMMODTCA; + +/** Offset 0x0866 - TxDqsTCO Comp Training + Enable/Disable TxDqsTCO Comp Training + $EN_DIS +**/ + UINT8 TXTCODQS; + +/** Offset 0x0867 - CMD/CTL Drive Strength Up/Dn 2D + Enable/Disable CMD/CTL Drive Strength Up/Dn 2D + $EN_DIS +**/ + UINT8 CMDDRUD; + +/** Offset 0x0868 - VccDLL Bypass Training + Enable/Disable VccDLL Bypass Training + $EN_DIS +**/ + UINT8 VCCDLLBP; + +/** Offset 0x0869 - PanicVttDnLp Training + Enable/Disable PanicVttDnLp Training + $EN_DIS +**/ + UINT8 PVTTDNLP; + +/** Offset 0x086A - Read Vref Decap Training* + Enable/Disable Read Vref Decap Training* + $EN_DIS +**/ + UINT8 RDVREFDC; + +/** Offset 0x086B - Vddq Training + Enable/Disable Vddq Training + $EN_DIS +**/ + UINT8 VDDQT; + +/** Offset 0x086C - Rank Margin Tool Per Bit + Enable/Disable Rank Margin Tool Per Bit + $EN_DIS +**/ + UINT8 RMTBIT; + +/** Offset 0x086D - ECC DFT feature + Enables/Disable ECC DFT feature + $EN_DIS +**/ + UINT8 EccDftEn; + +/** Offset 0x086E - Write0 feature + Enables/Disable Write0 feature + $EN_DIS +**/ + UINT8 Write0; + +/** Offset 0x086F - Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP + Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP + $EN_DIS +**/ + UINT8 Ddr4DdpSharedClock; + +/** Offset 0x0870 - Select if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP + ESelect if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP + $EN_DIS +**/ + UINT8 Ddr4DdpSharedZq; + +/** Offset 0x0871 - Ch Hash Interleaved Bit + Select the BIT to be used for Channel Interleaved mode. NOTE: BIT7 will interlave + the channels at a 2 cacheline granularity, BIT8 at 4 and BIT9 at 8. Default is BIT8 + 0:BIT6, 1:BIT7, 2:BIT8, 3:BIT9, 4:BIT10, 5:BIT11, 6:BIT12, 7:BIT13 +**/ + UINT8 ChHashInterleaveBit; + +/** Offset 0x0872 - Ch Hash Mask + Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to + BITS [19:6] Default is 0x30CC +**/ + UINT16 ChHashMask; + +/** Offset 0x0874 - Base reference clock value + Base reference clock value, in Hertz(Default is 100Hz) + 100000000:100Hz, 125000000:125Hz, 167000000:167Hz, 250000000:250Hz +**/ + UINT32 BClkFrequency; + +/** Offset 0x0878 - EPG DIMM Idd3N + Active standby current (Idd3N) in milliamps from datasheet. Must be calculated on + a per DIMM basis. Default is 26 +**/ + UINT16 Idd3n; + +/** Offset 0x087A - EPG DIMM Idd3P + Active power-down current (Idd3P) in milliamps from datasheet. Must be calculated + on a per DIMM basis. Default is 11 +**/ + UINT16 Idd3p; + +/** Offset 0x087C - CMD Normalization + Enable/Disable CMD Normalization + $EN_DIS +**/ + UINT8 CMDNORM; + +/** Offset 0x087D - Early DQ Write Drive Strength and Equalization Training + Enable/Disable Early DQ Write Drive Strength and Equalization Training + $EN_DIS +**/ + UINT8 EWRDSEQ; + +/** Offset 0x087E - MC_REFRESH_2X_MODE + DEPRECATED + $EN_DIS +**/ + UINT8 McRefresh2X; + +/** Offset 0x087F - Idle Energy Mc0Ch0Dimm0 + Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) +**/ + UINT8 IdleEnergyMc0Ch0Dimm0; + +/** Offset 0x0880 - Idle Energy Mc0Ch0Dimm1 + Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) +**/ + UINT8 IdleEnergyMc0Ch0Dimm1; + +/** Offset 0x0881 - Idle Energy Mc0Ch1Dimm0 + Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) +**/ + UINT8 IdleEnergyMc0Ch1Dimm0; + +/** Offset 0x0882 - Idle Energy Mc0Ch1Dimm1 + Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) +**/ + UINT8 IdleEnergyMc0Ch1Dimm1; + +/** Offset 0x0883 - Idle Energy Mc1Ch0Dimm0 + Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) +**/ + UINT8 IdleEnergyMc1Ch0Dimm0; + +/** Offset 0x0884 - Idle Energy Mc1Ch0Dimm1 + Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) +**/ + UINT8 IdleEnergyMc1Ch0Dimm1; + +/** Offset 0x0885 - Idle Energy Mc1Ch1Dimm0 + Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) +**/ + UINT8 IdleEnergyMc1Ch1Dimm0; + +/** Offset 0x0886 - Idle Energy Mc1Ch1Dimm1 + Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) +**/ + UINT8 IdleEnergyMc1Ch1Dimm1; + +/** Offset 0x0887 - PowerDown Energy Mc0Ch0Dimm0 + PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def) +**/ + UINT8 PdEnergyMc0Ch0Dimm0; + +/** Offset 0x0888 - PowerDown Energy Mc0Ch0Dimm1 + PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def) +**/ + UINT8 PdEnergyMc0Ch0Dimm1; + +/** Offset 0x0889 - PowerDown Energy Mc0Ch1Dimm0 + PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def) +**/ + UINT8 PdEnergyMc0Ch1Dimm0; + +/** Offset 0x088A - PowerDown Energy Mc0Ch1Dimm1 + PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def) +**/ + UINT8 PdEnergyMc0Ch1Dimm1; + +/** Offset 0x088B - PowerDown Energy Mc1Ch0Dimm0 + PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def) +**/ + UINT8 PdEnergyMc1Ch0Dimm0; + +/** Offset 0x088C - PowerDown Energy Mc1Ch0Dimm1 + PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def) +**/ + UINT8 PdEnergyMc1Ch0Dimm1; + +/** Offset 0x088D - PowerDown Energy Mc1Ch1Dimm0 + PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def) +**/ + UINT8 PdEnergyMc1Ch1Dimm0; + +/** Offset 0x088E - PowerDown Energy Mc1Ch1Dimm1 + PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def) +**/ + UINT8 PdEnergyMc1Ch1Dimm1; + +/** Offset 0x088F - Activate Energy Mc0Ch0Dimm0 + Activate Energy Contribution, range[255;0],(172= Def) +**/ + UINT8 ActEnergyMc0Ch0Dimm0; + +/** Offset 0x0890 - Activate Energy Mc0Ch0Dimm1 + Activate Energy Contribution, range[255;0],(172= Def) +**/ + UINT8 ActEnergyMc0Ch0Dimm1; + +/** Offset 0x0891 - Activate Energy Mc0Ch1Dimm0 + Activate Energy Contribution, range[255;0],(172= Def) +**/ + UINT8 ActEnergyMc0Ch1Dimm0; + +/** Offset 0x0892 - Activate Energy Mc0Ch1Dimm1 + Activate Energy Contribution, range[255;0],(172= Def) +**/ + UINT8 ActEnergyMc0Ch1Dimm1; + +/** Offset 0x0893 - Activate Energy Mc1Ch0Dimm0 + Activate Energy Contribution, range[255;0],(172= Def) +**/ + UINT8 ActEnergyMc1Ch0Dimm0; + +/** Offset 0x0894 - Activate Energy Mc1Ch0Dimm1 + Activate Energy Contribution, range[255;0],(172= Def) +**/ + UINT8 ActEnergyMc1Ch0Dimm1; + +/** Offset 0x0895 - Activate Energy Mc1Ch1Dimm0 + Activate Energy Contribution, range[255;0],(172= Def) +**/ + UINT8 ActEnergyMc1Ch1Dimm0; + +/** Offset 0x0896 - Activate Energy Mc1Ch1Dimm1 + Activate Energy Contribution, range[255;0],(172= Def) +**/ + UINT8 ActEnergyMc1Ch1Dimm1; + +/** Offset 0x0897 - Read Energy Mc0Ch0Dimm0 + Read Energy Contribution, range[255;0],(212= Def) +**/ + UINT8 RdEnergyMc0Ch0Dimm0; + +/** Offset 0x0898 - Read Energy Mc0Ch0Dimm1 + Read Energy Contribution, range[255;0],(212= Def) +**/ + UINT8 RdEnergyMc0Ch0Dimm1; + +/** Offset 0x0899 - Read Energy Mc0Ch1Dimm0 + Read Energy Contribution, range[255;0],(212= Def) +**/ + UINT8 RdEnergyMc0Ch1Dimm0; + +/** Offset 0x089A - Read Energy Mc0Ch1Dimm1 + Read Energy Contribution, range[255;0],(212= Def) +**/ + UINT8 RdEnergyMc0Ch1Dimm1; + +/** Offset 0x089B - Read Energy Mc1Ch0Dimm0 + Read Energy Contribution, range[255;0],(212= Def) +**/ + UINT8 RdEnergyMc1Ch0Dimm0; + +/** Offset 0x089C - Read Energy Mc1Ch0Dimm1 + Read Energy Contribution, range[255;0],(212= Def) +**/ + UINT8 RdEnergyMc1Ch0Dimm1; + +/** Offset 0x089D - Read Energy Mc1Ch1Dimm0 + Read Energy Contribution, range[255;0],(212= Def) +**/ + UINT8 RdEnergyMc1Ch1Dimm0; + +/** Offset 0x089E - Read Energy Mc1Ch1Dimm1 + Read Energy Contribution, range[255;0],(212= Def) +**/ + UINT8 RdEnergyMc1Ch1Dimm1; + +/** Offset 0x089F - Write Energy Mc0Ch0Dimm0 + Write Energy Contribution, range[255;0],(221= Def) +**/ + UINT8 WrEnergyMc0Ch0Dimm0; + +/** Offset 0x08A0 - Write Energy Mc0Ch0Dimm1 + Write Energy Contribution, range[255;0],(221= Def) +**/ + UINT8 WrEnergyMc0Ch0Dimm1; + +/** Offset 0x08A1 - Write Energy Mc0Ch1Dimm0 + Write Energy Contribution, range[255;0],(221= Def) +**/ + UINT8 WrEnergyMc0Ch1Dimm0; + +/** Offset 0x08A2 - Write Energy Mc0Ch1Dimm1 + Write Energy Contribution, range[255;0],(221= Def) +**/ + UINT8 WrEnergyMc0Ch1Dimm1; + +/** Offset 0x08A3 - Write Energy Mc1Ch0Dimm0 + Write Energy Contribution, range[255;0],(221= Def) +**/ + UINT8 WrEnergyMc1Ch0Dimm0; + +/** Offset 0x08A4 - Write Energy Mc1Ch0Dimm1 + Write Energy Contribution, range[255;0],(221= Def) +**/ + UINT8 WrEnergyMc1Ch0Dimm1; + +/** Offset 0x08A5 - Write Energy Mc1Ch1Dimm0 + Write Energy Contribution, range[255;0],(221= Def) +**/ + UINT8 WrEnergyMc1Ch1Dimm0; + +/** Offset 0x08A6 - Write Energy Mc1Ch1Dimm1 + Write Energy Contribution, range[255;0],(221= Def) +**/ + UINT8 WrEnergyMc1Ch1Dimm1; + +/** Offset 0x08A7 - Throttler CKEMin Timer + Timer value for CKEMin, range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH (4). + Dfault is 0x00 +**/ + UINT8 ThrtCkeMinTmr; + +/** Offset 0x08A8 - Allow Opp Ref Below Write Threhold + Allow opportunistic refreshes while we don't exit power down. + $EN_DIS +**/ + UINT8 AllowOppRefBelowWriteThrehold; + +/** Offset 0x08A9 - Write Threshold + Number of writes that can be accumulated while CKE is low before CKE is asserted. +**/ + UINT8 WriteThreshold; + +/** Offset 0x08AA - Rapl Power Floor Ch0 + Power budget ,range[255;0],(0= 5.3W Def) +**/ + UINT8 RaplPwrFlCh0; + +/** Offset 0x08AB - Rapl Power Floor Ch1 + Power budget ,range[255;0],(0= 5.3W Def) +**/ + UINT8 RaplPwrFlCh1; + +/** Offset 0x08AC - Command Rate Support + CMD Rate and Limit Support Option. NOTE: ONLY supported in 1N Mode, Default is 3 CMDs + 0:Disable, 5:2 CMDS, 7:3 CMDS, 9:4 CMDS, 11:5 CMDS, 13:6 CMDS, 15:7 CMDS +**/ + UINT8 EnCmdRate; + +/** Offset 0x08AD - REFRESH_2X_MODE + 0- (Default)Disabled 1-iMC enables 2xRef when Warm and Hot 2- iMC enables 2xRef when Hot + 0:Disable, 1:Enabled for WARM or HOT, 2:Enabled HOT only +**/ + UINT8 Refresh2X; + +/** Offset 0x08AE - Energy Performance Gain + Enable/disable(default) Energy Performance Gain. + $EN_DIS +**/ + UINT8 EpgEnable; + +/** Offset 0x08AF - RH pTRR LFSR0 Mask + Row Hammer pTRR LFSR0 Mask, 1/2^(value) +**/ + UINT8 Lfsr0Mask; + +/** Offset 0x08B0 - User Manual Threshold + Disabled: Predefined threshold will be used.\n + Enabled: User Input will be used. + $EN_DIS +**/ + UINT8 UserThresholdEnable; + +/** Offset 0x08B1 - User Manual Budget + Disabled: Configuration of memories will defined the Budget value.\n + Enabled: User Input will be used. + $EN_DIS +**/ + UINT8 UserBudgetEnable; + +/** Offset 0x08B2 - Power Down Mode + This option controls command bus tristating during idle periods + 0x0:No Power Down, 0x1:APD, 0x6:PPD DLL OFF, 0xFF:Auto +**/ + UINT8 PowerDownMode; + +/** Offset 0x08B3 - Pwr Down Idle Timer + The minimum value should = to the worst case Roundtrip delay + Burst_Length. 0 means + AUTO: 64 for ULX/ULT, 128 for DT/Halo +**/ + UINT8 PwdwnIdleCounter; + +/** Offset 0x08B4 - Page Close Idle Timeout + This option controls Page Close Idle Timeout + 0:Enabled, 1:Disabled +**/ + UINT8 DisPgCloseIdleTimeout; + +/** Offset 0x08B5 - Bitmask of ranks that have CA bus terminated + Offset 225 LPDDR4: Bitmask of ranks that have CA bus terminated. 0x01=Default, + Rank0 is terminating and Rank1 is non-terminating +**/ + UINT8 CmdRanksTerminated; + +/** Offset 0x08B6 - PcdSerialDebugLevel + Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, + Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, + Info & Verbose. + 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load + Error Warnings and Info & Event, 5:Load Error Warnings Info and Verbose +**/ + UINT8 PcdSerialDebugLevel; + +/** Offset 0x08B7 - Safe Mode Support + This option configures the varous items in the IO and MC to be more conservative.(def=Disable) + $EN_DIS +**/ + UINT8 SafeMode; + +/** Offset 0x08B8 - Ask MRC to clear memory content + Ask MRC to clear memory content 0: Do not Clear Memory; 1: Clear Memory. + $EN_DIS +**/ + UINT8 CleanMemory; + +/** Offset 0x08B9 - LpDdrDqDqsReTraining + Enable/Disable TxDqDqs ReTraining for LP4/5 and DDR5 + $EN_DIS +**/ + UINT8 LpDdrDqDqsReTraining; + +/** Offset 0x08BA - TCSS USB Port Enable + Bitmap for per port enabling +**/ + UINT8 UsbTcPortEnPreMem; + +/** Offset 0x08BB +**/ + UINT8 UnusedUpdSpace21; + +/** Offset 0x08BC - Post Code Output Port + This option configures Post Code Output Port +**/ + UINT16 PostCodeOutputPort; + +/** Offset 0x08BE - RMTLoopCount + Specifies the Loop Count to be used during Rank Margin Tool Testing. 0 - AUTO +**/ + UINT8 RMTLoopCount; + +/** Offset 0x08BF - Enable/Disable SA CRID + Enable: SA CRID, Disable (Default): SA CRID + $EN_DIS +**/ + UINT8 CridEnable; + +/** Offset 0x08C0 - WRC Feature + Enable/Disable WRC (Write Cache) feature of IOP. When feature is enabled, supports + IO devices allocating onto the ring and into LLC. WRC is fused on by default. + $EN_DIS +**/ + UINT8 WrcFeatureEnable; + +/** Offset 0x08C1 +**/ + UINT8 UnusedUpdSpace22[3]; + +/** Offset 0x08C4 - BCLK RFI Frequency + Bclk RFI Frequency for each SAGV point in Hz units. 98000000Hz = 98MHz 0 - No + RFI Tuning. Range is 98Mhz-100Mhz. +**/ + UINT32 BclkRfiFreq[4]; + +/** Offset 0x08D4 - Size of PCIe IMR. + Size of PCIe IMR in megabytes +**/ + UINT16 PcieImrSize; + +/** Offset 0x08D6 - Enable PCIe IMR + 0: Disable(AUTO), 1: Enable + $EN_DIS +**/ + UINT8 PcieImrEnabled; + +/** Offset 0x08D7 - Enable PCIe IMR + 1: PCH PCIE, 2: SA PCIE. If PCIeImrEnabled is TRUE then this will use to select + the Root port location from PCH PCIe or SA PCIe + $EN_DIS +**/ + UINT8 PcieImrRpLocation; + +/** Offset 0x08D8 - Root port number for IMR. + Root port number for IMR.If PCieImrRpLocation is PCH PCIe then select root port + from 0 to 23 and if it is SA PCIe then select root port from 0 to 3 +**/ + UINT8 PcieImrRpSelection; + +/** Offset 0x08D9 - SerialDebugMrcLevel + MRC Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, + Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, + Info & Verbose. + 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load + Error Warnings and Info & Event, 5:Load Error Warnings Info and Verbose +**/ + UINT8 SerialDebugMrcLevel; + +/** Offset 0x08DA - Ddr4OneDpc + DDR4 1DPC performance feature for 2R DIMMs. Can be enabled on DIMM0 or DIMM1 only, + or on both (default) + 0: Disabled, 1: Enabled on DIMM0 only, 2: Enabled on DIMM1 only, 3: Enabled +**/ + UINT8 Ddr4OneDpc; + +/** Offset 0x08DB - RH pTRR LFSR1 Mask + Row Hammer pTRR LFSR1 Mask, 1/2^(value) +**/ + UINT8 Lfsr1Mask; + +/** Offset 0x08DC - LPDDR ODT RttWr + Initial RttWr for LP4/5 in Ohms. 0x0 - Auto +**/ + UINT8 LpddrRttWr; + +/** Offset 0x08DD - LPDDR ODT RttCa + Initial RttCa for LP4/5 in Ohms. 0x0 - Auto +**/ + UINT8 LpddrRttCa; + +/** Offset 0x08DE - REFRESH_PANIC_WM + DEPRECATED +**/ + UINT8 RefreshPanicWm; + +/** Offset 0x08DF - REFRESH_HP_WM + DEPRECATED +**/ + UINT8 RefreshHpWm; + +/** Offset 0x08E0 - Command Pins Mapping + BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller + 1 Channel [3:0]. 0 = CCC pin mapping is Ascending, 1 = CCC pin mapping is Descending. +**/ + UINT8 Lp5CccConfig; + +/** Offset 0x08E1 - Command Pins Mirrored + BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller + 1 Channel [3:0]. 0 = No Command Mirror and 1 = Command Mirror. +**/ + UINT8 CmdMirror; + +/** Offset 0x08E2 - DIMM DFE Training + Enable/Disable DIMM DFE Training + $EN_DIS +**/ + UINT8 DIMMDFE; + +/** Offset 0x08E3 - Extended Bank Hashing + Enable/Disable Extended Bank Hashing + $EN_DIS +**/ + UINT8 ExtendedBankHashing; + +/** Offset 0x08E4 - Refresh Watermarks + Refresh Watermarks: 0-Low, 1-High (default) + 0:Set Refresh Watermarks to Low, 1:Set Refresh Watermarks to High (Default) +**/ + UINT8 RefreshWm; + +/** Offset 0x08E5 - MC_REFRESH_RATE + Type of Refresh Rate used to prevent Row Hammer. Default is NORMAL Refresh + 0:NORMAL Refresh, 1:1x Refresh, 2:2x Refresh, 3:4x Refresh +**/ + UINT8 McRefreshRate; + +/** Offset 0x08E6 - Periodic DCC + Enable/Disable Periodic DCC; default: Disabled + $EN_DIS +**/ + UINT8 PeriodicDcc; + +/** Offset 0x08E7 - LpMode + LpMode feature + 0: Auto (default), 1: Enabled, 2: Disabled, 3: Reserved +**/ + UINT8 LpMode; + +/** Offset 0x08E8 - TX DQS DCC Training + Enable/Disable TX DQS DCC Training + $EN_DIS +**/ + UINT8 TXDQSDCC; + +/** Offset 0x08E9 - DRAM DCA Training + Enable/Disable DRAM DCA Training + $EN_DIS +**/ + UINT8 DRAMDCA; + +/** Offset 0x08EA - EARLY DIMM DFE Training + Enable/Disable EARLY DIMM DFE Training + $EN_DIS +**/ + UINT8 EARLYDIMMDFE; + +/** Offset 0x08EB - Skip external display device scanning + Enable: Do not scan for external display device, Disable (Default): Scan external + display devices + $EN_DIS +**/ + UINT8 SkipExtGfxScan; + +/** Offset 0x08EC - Generate BIOS Data ACPI Table + Enable: Generate BDAT for MRC RMT or SA PCIe data. Disable (Default): Do not generate it + $EN_DIS +**/ + UINT8 BdatEnable; + +/** Offset 0x08ED - Lock PCU Thermal Management registers + Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0 + $EN_DIS +**/ + UINT8 LockPTMregs; + +/** Offset 0x08EE - Rsvd + Disable(0x0)(Default): Normal Operation - RxCTLE adaptive behavior enabled, Enable(0x1): + Override RxCTLE - Disable RxCTLE adaptive behavior to keep the configured RxCTLE + peak values unmodified + $EN_DIS +**/ + UINT8 PegGen3Rsvd; + +/** Offset 0x08EF - Panel Power Enable + Control for enabling/disabling VDD force bit (Required only for early enabling of + eDP panel). 0=Disable, 1(Default)=Enable + $EN_DIS +**/ + UINT8 PanelPowerEnable; + +/** Offset 0x08F0 - BdatTestType + Indicates the type of Memory Training data to populate into the BDAT ACPI table. + 0:RMT per Rank, 1:RMT per Bit, 2:Margin2D +**/ + UINT8 BdatTestType; + +/** Offset 0x08F1 +**/ + UINT8 UnusedUpdSpace23[3]; + +/** Offset 0x08F4 - PMR Size + Size of PMR memory buffer. 0x400000 for normal boot and 0x200000 for S3 boot +**/ + UINT32 DmaBufferSize; + +/** Offset 0x08F8 - VT-d/IOMMU Boot Policy + BIT0: Enable IOMMU during boot, BIT1: Enable IOMMU when transfer control to OS +**/ + UINT8 PreBootDmaMask; + +/** Offset 0x08F9 +**/ + UINT8 UnusedUpdSpace24; + +/** Offset 0x08FA - Delta T12 Power Cycle Delay required in ms + Select the value for delay required. 0= No delay, 0xFFFF(Default) = Auto calculate + T12 Delay to max 500ms + 0 : No Delay, 0xFFFF : Auto Calulate T12 Delay +**/ + UINT16 DeltaT12PowerCycleDelay; + +/** Offset 0x08FC - Reuse Adl DDR5 Board or not + Indicate whether adl ddr5 board is reused. + 0 : no, 1 : yes +**/ + UINT8 ReuseAdlSDdr5Board; + +/** Offset 0x08FD - Oem T12 Delay Override + Oem T12 Delay Override. 0(Default)=Disable 1=Enable + $EN_DIS +**/ + UINT8 OemT12DelayOverride; + +/** Offset 0x08FE - SaPreMemTestRsvd + Reserved for SA Pre-Mem Test + $EN_DIS +**/ + UINT8 SaPreMemTestRsvd[89]; + +/** Offset 0x0957 +**/ + UINT8 UnusedUpdSpace25; + +/** Offset 0x0958 - TotalFlashSize + Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable +**/ + UINT16 TotalFlashSize; + +/** Offset 0x095A - BiosSize + The size of the BIOS region of the IFWI. Used if FspmUpd->FspmConfig.BiosGuard != + 0. If BiosGuard is enabled, MRC will increase the size of the DPR (DMA Protected + Range) so that a BIOS Update Script can be stored in the DPR. +**/ + UINT16 BiosSize; + +/** Offset 0x095C - SecurityTestRsvd + Reserved for SA Pre-Mem Test + $EN_DIS +**/ + UINT8 SecurityTestRsvd[12]; + +/** Offset 0x0968 - Smbus dynamic power gating + Disable or Enable Smbus dynamic power gating. + $EN_DIS +**/ + UINT8 SmbusDynamicPowerGating; + +/** Offset 0x0969 - Disable and Lock Watch Dog Register + Set 1 to clear WDT status, then disable and lock WDT registers. + $EN_DIS +**/ + UINT8 WdtDisableAndLock; + +/** Offset 0x096A - SMBUS SPD Write Disable + Set/Clear Smbus SPD Write Disable. 0: leave SPD Write Disable bit; 1: set SPD Write + Disable bit. For security recommendations, SPD write disable bit must be set. + $EN_DIS +**/ + UINT8 SmbusSpdWriteDisable; + +/** Offset 0x096B - Force ME DID Init Status + Test, 0: disable, 1: Success, 2: No Memory in Channels, 3: Memory Init Error, Set + ME DID init stat value + $EN_DIS +**/ + UINT8 DidInitStat; + +/** Offset 0x096C - CPU Replaced Polling Disable + Test, 0: disable, 1: enable, Setting this option disables CPU replacement polling loop + $EN_DIS +**/ + UINT8 DisableCpuReplacedPolling; + +/** Offset 0x096D - Check HECI message before send + Test, 0: disable, 1: enable, Enable/Disable message check. + $EN_DIS +**/ + UINT8 DisableMessageCheck; + +/** Offset 0x096E - Skip MBP HOB + Test, 0: disable, 1: enable, Enable/Disable MOB HOB. + $EN_DIS +**/ + UINT8 SkipMbpHob; + +/** Offset 0x096F - HECI2 Interface Communication + Test, 0: disable, 1: enable, Adds or Removes HECI2 Device from PCI space. + $EN_DIS +**/ + UINT8 HeciCommunication2; + +/** Offset 0x0970 - Enable KT device + Test, 0: disable, 1: enable, Enable or Disable KT device. + $EN_DIS +**/ + UINT8 KtDeviceEnable; + +/** Offset 0x0971 - Skip CPU replacement check + Test, 0: disable, 1: enable, Setting this option to skip CPU replacement check + $EN_DIS +**/ + UINT8 SkipCpuReplacementCheck; + +/** Offset 0x0972 +**/ + UINT8 UnusedUpdSpace26[2]; + +/** Offset 0x0974 - Hybrid Graphics GPIO information for PEG 1 + Hybrid Graphics GPIO information for PEG 1, for Reset, power and wake GPIOs +**/ + UINT32 CpuPcie1Rtd3Gpio[24]; + +/** Offset 0x09D4 - Hybrid Graphics GPIO information for PEG 2 + Hybrid Graphics GPIO information for PEG 2, for Reset, power and wake GPIOs +**/ + UINT32 CpuPcie2Rtd3Gpio[24]; + +/** Offset 0x0A34 - Hybrid Graphics GPIO information for PEG 3 + Hybrid Graphics GPIO information for PEG 3, for Reset, power and wake GPIOs +**/ + UINT32 CpuPcie3Rtd3Gpio[24]; + +/** Offset 0x0A94 - Avx2 Voltage Guardband Scaling Factor + AVX2 Voltage Guardband Scale factor applied to AVX2 workloads. Range is 0-200 in + 1/100 units, where a value of 125 would apply a 1.25 scale factor. +**/ + UINT8 Avx2VoltageScaleFactor; + +/** Offset 0x0A95 - Avx512 Voltage Guardband Scaling Factor + DEPRECATED +**/ + UINT8 Avx512VoltageScaleFactor; + +/** Offset 0x0A96 - Serial Io Uart Debug Mode + Select SerialIo Uart Controller mode + 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom, + 4:SerialIoUartSkipInit +**/ + UINT8 SerialIoUartDebugMode; + +/** Offset 0x0A97 +**/ + UINT8 UnusedUpdSpace27; + +/** Offset 0x0A98 - SerialIoUartDebugRxPinMux - FSPT + Select RX pin muxing for SerialIo UART used for debug +**/ + UINT32 SerialIoUartDebugRxPinMux; + +/** Offset 0x0A9C - SerialIoUartDebugTxPinMux - FSPM + Select TX pin muxing for SerialIo UART used for debug +**/ + UINT32 SerialIoUartDebugTxPinMux; + +/** Offset 0x0AA0 - SerialIoUartDebugRtsPinMux - FSPM + Select SerialIo Uart used for debug Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS* + for possible values. +**/ + UINT32 SerialIoUartDebugRtsPinMux; + +/** Offset 0x0AA4 - SerialIoUartDebugCtsPinMux - FSPM + Select SerialIo Uart used for debug Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS* + for possible values. +**/ + UINT32 SerialIoUartDebugCtsPinMux; + +/** Offset 0x0AA8 - Ppr Enable Type + Enable Soft or Hard PPR 0:Disable, 2:Hard PPR + 0:Disable, 2:Hard PPR +**/ + UINT8 PprEnable; + +/** Offset 0x0AA9 - Margin Limit Check + Margin Limit Check. Choose level of margin check + 0:Disable, 1:L1, 2:L2, 3:Both +**/ + UINT8 MarginLimitCheck; + +/** Offset 0x0AAA - Margin Limit L2 + % of L1 check for margin limit check +**/ + UINT16 MarginLimitL2; + +/** Offset 0x0AAC - DEKEL CDR Relock + Enable/Disable CDR Relock. 0: Disable(Default); 1: Enable +**/ + UINT8 CpuPcieRpCdrRelock[4]; + +/** Offset 0x0AB0 - DMI DEKEL CDR Relock + Enable/Disable CPU DMI CDR Relock. 0: Disable(Default); 1: Enable + $EN_DIS +**/ + UINT8 DmiCdrRelock; + +/** Offset 0x0AB1 - IbeccErrInjControl + IBECC Error Injection Control + 0: No Error Injection, 1:Inject Correctable Error Address match, 3:Inject Correctable + Error on insertion counter, 5: Inject Uncorrectable Error Address match, 7:Inject + Uncorrectable Error on insertion counter +**/ + UINT8 IbeccErrInjControl; + +/** Offset 0x0AB2 +**/ + UINT8 UnusedUpdSpace28[6]; + +/** Offset 0x0AB8 - IbeccErrInjAddress + Address to match against for ECC error injection +**/ + UINT64 IbeccErrInjAddress; + +/** Offset 0x0AC0 - IbeccErrInjMask + Mask to match against for ECC error injection +**/ + UINT64 IbeccErrInjMask; + +/** Offset 0x0AC8 - IbeccErrInjCount + Number of transactions between ECC error injection +**/ + UINT32 IbeccErrInjCount; + +/** Offset 0x0ACC - Pointer EnableDmaBuffer + Pointer of EnableDmaBuffer Callback Function. +**/ + UINT8 EnableDmaBuffer[8]; + +/** Offset 0x0AD4 - PLL Max Banding Ratio + DEPRECATED +**/ + UINT8 PllMaxBandingRatio; + +/** Offset 0x0AD5 +**/ + UINT8 UnusedUpdSpace29[3]; + +/** Offset 0x0AD8 - Debug Value + Debug Value +**/ + UINT32 DebugValue; + +/** Offset 0x0ADC - Pre-Mem GPIO table address + AlderLake S needs to assert PCIe SLOT RTD3 and PEG reset pins in early PreMem phase. + 0: Skip FSP PCIe pins programming. Refer to mAdlSPcieRstPinGpioTable[] in GpioSampleDef.h. +**/ + UINT32 BoardGpioTablePreMemAddress; + +/** Offset 0x0AE0 - tRFCpb + Min Internal per bank refresh recovery delay time, 0: AUTO, max: 0xFFFF. Only used + if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile). +**/ + UINT16 tRFCpb; + +/** Offset 0x0AE2 - tRFC2 + Min Internal refresh recovery delay time, 0: AUTO, max: 0xFFFF. Only used if FspmUpd->FspmConfig.SpdProfileSelected + == 1 (Custom Profile). +**/ + UINT16 tRFC2; + +/** Offset 0x0AE4 - tRFC4 + Min Internal refresh recovery delay time, 0: AUTO, max: 0xFFFF. Only used if FspmUpd->FspmConfig.SpdProfileSelected + == 1 (Custom Profile). +**/ + UINT16 tRFC4; + +/** Offset 0x0AE6 - tRRD_L + Min Internal row active to row active delay time for same bank groups, 0: AUTO, + max: 80. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile). +**/ + UINT8 tRRD_L; + +/** Offset 0x0AE7 - tRRD_S + Min Internal row active to row active delay time for different bank groups, 0: AUTO, + max: 80. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile). +**/ + UINT8 tRRD_S; + +/** Offset 0x0AE8 - tWTR_L + Min Internal write to read command delay time for same bank groups, 0: AUTO, max: + 127. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile). +**/ + UINT8 tWTR_L; + +/** Offset 0x0AE9 - tCCD_L + Min Internal CAS-to-CAS delay for same bank group, 0: AUTO, max: 80. Only used if + FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile). +**/ + UINT8 tCCD_L; + +/** Offset 0x0AEA - tWTR_S + Min Internal write to read command delay time for different bank groups, 0: AUTO, + max: 50. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile). +**/ + UINT8 tWTR_S; + +/** Offset 0x0AEB +**/ + UINT8 UnusedUpdSpace30[5]; + +/** Offset 0x0AF0 - EccErrInjAddress + Address to match against for ECC error injection +**/ + UINT64 EccErrInjAddress; + +/** Offset 0x0AF8 - EccErrInjMask + Mask to match against for ECC error injection +**/ + UINT64 EccErrInjMask; + +/** Offset 0x0B00 - EccErrInjCount + Number of transactions between ECC error injection +**/ + UINT32 EccErrInjCount; + +/** Offset 0x0B04 - Frequency Limit for 2DPC Mixed or non-POR Config + Frequency Limit for 2DPC Mixed or non-POR Config. 0: Auto (default), otherwise a + frequency in MT/s +**/ + UINT16 FreqLimitMixedConfig; + +/** Offset 0x0B06 - First Dimm BitMask + Defines which DIMM should be populated first on a 2DPC board. Bit0: MC0 DIMM0, Bit1: + MC0 DIMM1, Bit2: MC1 DIMM0, Bit3: MC1 DIMM1. For each MC, the first DIMM to be + populated should be set to '1' +**/ + UINT8 FirstDimmBitMask; + +/** Offset 0x0B07 - SAGV Switch Factor IA DDR BW + SAGV Switch Factor IA DDR BW: IA DDR load percentage when system switch to high + SAGV point from 1 to 50%. +**/ + UINT8 SagvSwitchFactorIA; + +/** Offset 0x0B08 - SAGV Switch Factor GT DDR BW + SAGV Switch Factor GT DDR BW: GT DDR load percentage when system switch to high + SAGV point from 1 to 50%. +**/ + UINT8 SagvSwitchFactorGT; + +/** Offset 0x0B09 - SAGV Switch Factor IO DDR BW + SAGV Switch Factor IO DDR BW: IO DDR load percentage when system switch to high + SAGV point from 1 to 50%. +**/ + UINT8 SagvSwitchFactorIO; + +/** Offset 0x0B0A - SAGV Switch Factor IA and GT Stall + SAGV Switch Factor IA and GT Stall: IA and GT percentage when system switch to high + SAGV point from 1 to 50%. +**/ + UINT8 SagvSwitchFactorStall; + +/** Offset 0x0B0B - Threshold For Switch Down + SAGV heuristics down control: Duration in ms of low activity after which SAGV will + switch down, from 1 to 50ms. +**/ + UINT8 SagvHeuristicsDownControl; + +/** Offset 0x0B0C - Threshold For Switch Up + SAGV heuristics up control: Duration in ms of low activity after which SAGV will + switch up, from 1 to 50ms. +**/ + UINT8 SagvHeuristicsUpControl; + +/** Offset 0x0B0D +**/ + UINT8 UnusedUpdSpace31; + +/** Offset 0x0B0E - Frequency Limit for Mixed 2DPC DDR5 1 Rank 8GB and 8GB + Frequency Limit for 2DPC Mixed or non-POR Config. 0: Auto, otherwise a frequency + in MT/s, default is 2000 +**/ + UINT16 FreqLimitMixedConfig_1R1R_8GB; + +/** Offset 0x0B10 - Frequency Limit for Mixed 2DPC DDR5 1 Rank 16GB and 16GB + Frequency Limit for 2DPC Mixed or non-POR Config. 0: Auto, otherwise a frequency + in MT/s, default is 2000 +**/ + UINT16 FreqLimitMixedConfig_1R1R_16GB; + +/** Offset 0x0B12 - Frequency Limit for Mixed 2DPC DDR5 1 Rank 8GB and 16GB + Frequency Limit for 2DPC Mixed or non-POR Config. 0: Auto, otherwise a frequency + in MT/s, default is 2000 +**/ + UINT16 FreqLimitMixedConfig_1R1R_8GB_16GB; + +/** Offset 0x0B14 - Frequency Limit for Mixed 2DPC DDR5 2 Rank + Frequency Limit for 2DPC Mixed or non-POR Config. 0: Auto, otherwise a frequency + in MT/s, default is 2000 +**/ + UINT16 FreqLimitMixedConfig_2R2R; + +/** Offset 0x0B16 - DMI Hw Eq Gen3 CoeffList Cm + PCH_DMI_EQ_PARAM. Coefficient C-1. +**/ + UINT8 PchDmiHwEqGen3CoeffListCm[8]; + +/** Offset 0x0B1E - DMI Hw Eq Gen3 CoeffList Cp + PCH_DMI_EQ_PARAM. Coefficient C+1. +**/ + UINT8 PchDmiHwEqGen3CoeffListCp[8]; + +/** Offset 0x0B26 - LCT Command eyewidth + LCT Command eyewidth. 0: Auto, otherwise eyewidth , default is 96 +**/ + UINT16 LctCmdEyeWidth; + +/** Offset 0x0B28 - For LPDDR Only: Throttler CKEMin Timer + For LPDDR Only: Timer value for CKEMin, range[255;0]. Reqd min of SC_ROUND_T + BYTE_LENGTH + (4). Dfault is 0x00 +**/ + UINT8 ThrtCkeMinTmrLpddr; + +/** Offset 0x0B29 - First ECC Dimm BitMask + Defines which ECC DIMM should be populated first on a 2DPC board. Bit0: MC0 DIMM0, + Bit1: MC0 DIMM1, Bit2: MC1 DIMM0, Bit3: MC1 DIMM1. For each MC, the first DIMM + to be populated should be set to '1' +**/ + UINT8 FirstDimmBitMaskEcc; + +/** Offset 0x0B2A - LP5 Bank Mode + LP5 Bank Mode. 0: Auto, 1: 8 Bank Mode, 2: 16 Bank Mode, 3: BG Mode, default is 0 + 0:Auto, 1:8 Bank Mode, 2:16 Bank Mode, 3:BG Mode +**/ + UINT8 Lp5BankMode; + +/** Offset 0x0B2B - Write DS Training + Enable/Disable Write DS Training + $EN_DIS +**/ + UINT8 WRDS; + +/** Offset 0x0B2C - SAM Overlaoding + Enable: copy the sagv frequency point. Disable: not copy. + $EN_DIS +**/ + UINT8 OverloadSAM; + +/** Offset 0x0B2D +**/ + UINT8 UnusedUpdSpace32[5]; + +/** Offset 0x0B32 +**/ + UINT8 ReservedFspmUpd2[6]; +} FSP_M_CONFIG; + +/** Fsp M UPD Configuration +**/ +typedef struct { + +/** Offset 0x0000 +**/ + FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + FSPM_ARCH_UPD FspmArchUpd; + +/** Offset 0x0040 +**/ + FSP_M_CONFIG FspmConfig; + +/** Offset 0x0B38 +**/ + UINT8 UnusedUpdSpace33[6]; + +/** Offset 0x0B3E +**/ + UINT16 UpdTerminator; +} FSPM_UPD; + +#pragma pack() + +#endif diff --git a/AlderLakeFspBinPkg/Client/AlderLakeP/Include/FspsUpd.h b/AlderLakeFspBinPkg/Client/AlderLakeP/Include/FspsUpd.h new file mode 100644 index 0000000..a551d32 --- /dev/null +++ b/AlderLakeFspBinPkg/Client/AlderLakeP/Include/FspsUpd.h @@ -0,0 +1,4280 @@ +/** @file + +Copyright (c) 2022, Intel Corporation. All rights reserved.
+ +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPSUPD_H__ +#define __FSPSUPD_H__ + +#include + +#pragma pack(1) + + +/// +/// Azalia Header structure +/// +typedef struct { + UINT16 VendorId; ///< Codec Vendor ID + UINT16 DeviceId; ///< Codec Device ID + UINT8 RevisionId; ///< Revision ID of the codec. 0xFF matches any revision. + UINT8 SdiNum; ///< SDI number, 0xFF matches any SDI. + UINT16 DataDwords; ///< Number of data DWORDs pointed by the codec data buffer. + UINT32 Reserved; ///< Reserved for future use. Must be set to 0. +} AZALIA_HEADER; + +/// +/// Audio Azalia Verb Table structure +/// +typedef struct { + AZALIA_HEADER Header; ///< AZALIA PCH header + UINT32 *Data; ///< Pointer to the data buffer. Its length is specified in the header +} AUDIO_AZALIA_VERB_TABLE; + +/// +/// Refer to the definition of PCH_INT_PIN +/// +typedef enum { + SiPchNoInt, ///< No Interrupt Pin + SiPchIntA, + SiPchIntB, + SiPchIntC, + SiPchIntD +} SI_PCH_INT_PIN; +/// +/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device. +/// +typedef struct { + UINT8 Device; ///< Device number + UINT8 Function; ///< Device function + UINT8 IntX; ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN) + UINT8 Irq; ///< IRQ to be set for device. +} SI_PCH_DEVICE_INTERRUPT_CONFIG; + +#define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices + + +/** Fsp S Configuration +**/ +typedef struct { + +/** Offset 0x0040 - Logo Pointer + Points to PEI Display Logo Image +**/ + UINT32 LogoPtr; + +/** Offset 0x0044 - Logo Size + Size of PEI Display Logo Image +**/ + UINT32 LogoSize; + +/** Offset 0x0048 - Blt Buffer Address + Address of Blt buffer +**/ + UINT32 BltBufferAddress; + +/** Offset 0x004C - Blt Buffer Size + Size of Blt Buffer, is equal to PixelWidth * PixelHeight * 4 bytes (the size of + EFI_GRAPHICS_OUTPUT_BLT_PIXEL) +**/ + UINT32 BltBufferSize; + +/** Offset 0x0050 - Graphics Configuration Ptr + Points to VBT +**/ + UINT32 GraphicsConfigPtr; + +/** Offset 0x0054 - Enable Device 4 + Enable/disable Device 4 + $EN_DIS +**/ + UINT8 Device4Enable; + +/** Offset 0x0055 - Show SPI controller + Enable/disable to show SPI controller. + $EN_DIS +**/ + UINT8 ShowSpiController; + +/** Offset 0x0056 +**/ + UINT8 UnusedUpdSpace0[2]; + +/** Offset 0x0058 - MicrocodeRegionBase + Memory Base of Microcode Updates +**/ + UINT32 MicrocodeRegionBase; + +/** Offset 0x005C - MicrocodeRegionSize + Size of Microcode Updates +**/ + UINT32 MicrocodeRegionSize; + +/** Offset 0x0060 - Turbo Mode + Enable/Disable Turbo mode. 0: disable, 1: enable + $EN_DIS +**/ + UINT8 TurboMode; + +/** Offset 0x0061 - Enable SATA SALP Support + Enable/disable SATA Aggressive Link Power Management. + $EN_DIS +**/ + UINT8 SataSalpSupport; + +/** Offset 0x0062 - Enable SATA ports + Enable/disable SATA ports. One byte for each port, byte0 for port0, byte1 for port1, + and so on. +**/ + UINT8 SataPortsEnable[8]; + +/** Offset 0x006A - Enable SATA DEVSLP Feature + Enable/disable SATA DEVSLP per port. 0 is disable, 1 is enable. One byte for each + port, byte0 for port0, byte1 for port1, and so on. +**/ + UINT8 SataPortsDevSlp[8]; + +/** Offset 0x0072 +**/ + UINT8 UnusedUpdSpace1[2]; + +/** Offset 0x0074 - SATA DEVSLP GPIO Pin + Select SATA DEVSLP Pin. Refer to GPIO_*_MUXING_SATA_DEVSLP_x* for possible values. +**/ + UINT32 SataPortDevSlpPinMux[8]; + +/** Offset 0x0094 - Enable USB2 ports + Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for + port1, and so on. +**/ + UINT8 PortUsb20Enable[16]; + +/** Offset 0x00A4 - Enable USB3 ports + Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for + port1, and so on. +**/ + UINT8 PortUsb30Enable[10]; + +/** Offset 0x00AE - Enable xDCI controller + Enable/disable to xDCI controller. + $EN_DIS +**/ + UINT8 XdciEnable; + +/** Offset 0x00AF +**/ + UINT8 UnusedUpdSpace2; + +/** Offset 0x00B0 - Address of PCH_DEVICE_INTERRUPT_CONFIG table. + The address of the table of PCH_DEVICE_INTERRUPT_CONFIG. +**/ + UINT32 DevIntConfigPtr; + +/** Offset 0x00B4 - Number of DevIntConfig Entry + Number of Device Interrupt Configuration Entry. If this is not zero, the DevIntConfigPtr + must not be NULL. +**/ + UINT8 NumOfDevIntConfig; + +/** Offset 0x00B5 - PIRQx to IRQx Map Config + PIRQx to IRQx mapping. The valid value is 0x00 to 0x0F for each. First byte is for + PIRQA, second byte is for PIRQB, and so on. The setting is only available in Legacy + 8259 PCI mode. +**/ + UINT8 PxRcConfig[8]; + +/** Offset 0x00BD - Select GPIO IRQ Route + GPIO IRQ Select. The valid value is 14 or 15. +**/ + UINT8 GpioIrqRoute; + +/** Offset 0x00BE - Select SciIrqSelect + SCI IRQ Select. The valid value is 9, 10, 11, and 20, 21, 22, 23 for APIC only. +**/ + UINT8 SciIrqSelect; + +/** Offset 0x00BF - Select TcoIrqSelect + TCO IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23. +**/ + UINT8 TcoIrqSelect; + +/** Offset 0x00C0 - Enable/Disable Tco IRQ + Enable/disable TCO IRQ + $EN_DIS +**/ + UINT8 TcoIrqEnable; + +/** Offset 0x00C1 - PCH HDA Verb Table Entry Number + Number of Entries in Verb Table. +**/ + UINT8 PchHdaVerbTableEntryNum; + +/** Offset 0x00C2 +**/ + UINT8 UnusedUpdSpace3[2]; + +/** Offset 0x00C4 - PCH HDA Verb Table Pointer + Pointer to Array of pointers to Verb Table. +**/ + UINT32 PchHdaVerbTablePtr; + +/** Offset 0x00C8 - PCH HDA Codec Sx Wake Capability + Capability to detect wake initiated by a codec in Sx +**/ + UINT8 PchHdaCodecSxWakeCapability; + +/** Offset 0x00C9 - Enable SATA + Enable/disable SATA controller. + $EN_DIS +**/ + UINT8 SataEnable; + +/** Offset 0x00CA - SATA Mode + Select SATA controller working mode. + 0:AHCI, 1:RAID +**/ + UINT8 SataMode; + +/** Offset 0x00CB - SPIn Device Mode + Selects SPI operation mode. N represents controller index: SPI0, SPI1, ... Available + modes: 0:SerialIoSpiDisabled, 1:SerialIoSpiPci, 2:SerialIoSpiHidden +**/ + UINT8 SerialIoSpiMode[7]; + +/** Offset 0x00D2 - SPI Chip Select Polarity + Sets polarity for each chip Select. Available options: 0:SerialIoSpiCsActiveLow, + 1:SerialIoSpiCsActiveHigh +**/ + UINT8 SerialIoSpiCsPolarity[14]; + +/** Offset 0x00E0 - SPI Chip Select Enable + 0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled +**/ + UINT8 SerialIoSpiCsEnable[14]; + +/** Offset 0x00EE - SPIn Default Chip Select Output + Sets Default CS as Output. N represents controller index: SPI0, SPI1, ... Available + options: 0:CS0, 1:CS1 +**/ + UINT8 SerialIoSpiDefaultCsOutput[7]; + +/** Offset 0x00F5 - SPIn Default Chip Select Mode HW/SW + Sets Default CS Mode Hardware or Software. N represents controller index: SPI0, + SPI1, ... Available options: 0:HW, 1:SW +**/ + UINT8 SerialIoSpiCsMode[7]; + +/** Offset 0x00FC - SPIn Default Chip Select State Low/High + Sets Default CS State Low or High. N represents controller index: SPI0, SPI1, ... + Available options: 0:Low, 1:High +**/ + UINT8 SerialIoSpiCsState[7]; + +/** Offset 0x0103 - UARTn Device Mode + Selects Uart operation mode. N represents controller index: Uart0, Uart1, ... Available + modes: 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom, + 4:SerialIoUartSkipInit +**/ + UINT8 SerialIoUartMode[7]; + +/** Offset 0x010A +**/ + UINT8 UnusedUpdSpace4[2]; + +/** Offset 0x010C - Default BaudRate for each Serial IO UART + Set default BaudRate Supported from 0 - default to 6000000 +**/ + UINT32 SerialIoUartBaudRate[7]; + +/** Offset 0x0128 - Default ParityType for each Serial IO UART + Set default Parity. 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity +**/ + UINT8 SerialIoUartParity[7]; + +/** Offset 0x012F - Default DataBits for each Serial IO UART + Set default word length. 0: Default, 5,6,7,8 +**/ + UINT8 SerialIoUartDataBits[7]; + +/** Offset 0x0136 - Default StopBits for each Serial IO UART + Set default stop bits. 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: + TwoStopBits +**/ + UINT8 SerialIoUartStopBits[7]; + +/** Offset 0x013D - Power Gating mode for each Serial IO UART that works in COM mode + Set Power Gating. 0: Disabled, 1: Enabled, 2: Auto +**/ + UINT8 SerialIoUartPowerGating[7]; + +/** Offset 0x0144 - Enable Dma for each Serial IO UART that supports it + Set DMA/PIO mode. 0: Disabled, 1: Enabled +**/ + UINT8 SerialIoUartDmaEnable[7]; + +/** Offset 0x014B - Enables UART hardware flow control, CTS and RTS lines + Enables UART hardware flow control, CTS and RTS lines. +**/ + UINT8 SerialIoUartAutoFlow[7]; + +/** Offset 0x0152 +**/ + UINT8 UnusedUpdSpace5[2]; + +/** Offset 0x0154 - SerialIoUartRtsPinMuxPolicy + Select SerialIo Uart Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS* + for possible values. +**/ + UINT32 SerialIoUartRtsPinMuxPolicy[7]; + +/** Offset 0x0170 - SerialIoUartCtsPinMuxPolicy + Select SerialIo Uart Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS* + for possible values. +**/ + UINT32 SerialIoUartCtsPinMuxPolicy[7]; + +/** Offset 0x018C - SerialIoUartRxPinMuxPolicy + Select SerialIo Uart Rx pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RX* for + possible values. +**/ + UINT32 SerialIoUartRxPinMuxPolicy[7]; + +/** Offset 0x01A8 - SerialIoUartTxPinMuxPolicy + Select SerialIo Uart Tx pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_TX* for + possible values. +**/ + UINT32 SerialIoUartTxPinMuxPolicy[7]; + +/** Offset 0x01C4 - UART Number For Debug Purpose + UART number for debug purpose. 0:UART0, 1:UART1, 2:UART2, 3:UART3, 4:UART4, 5:UART5, + 6:UART6. Note: If UART0 is selected as CNVi BT Core interface, it cannot be used + for debug purpose. + 0:UART0, 1:UART1, 2:UART2, 3:UART3, 4:UART4, 5:UART5, 6:UART6 +**/ + UINT8 SerialIoDebugUartNumber; + +/** Offset 0x01C5 - Serial IO UART DBG2 table + Enable or disable Serial Io UART DBG2 table, default is Disable; 0: Disable; + 1: Enable. +**/ + UINT8 SerialIoUartDbg2[7]; + +/** Offset 0x01CC - I2Cn Device Mode + Selects I2c operation mode. N represents controller index: I2c0, I2c1, ... Available + modes: 0:SerialIoI2cDisabled, 1:SerialIoI2cPci, 2:SerialIoI2cHidden +**/ + UINT8 SerialIoI2cMode[8]; + +/** Offset 0x01D4 - Serial IO I2C SDA Pin Muxing + Select SerialIo I2c Sda pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SDA* for + possible values. +**/ + UINT32 PchSerialIoI2cSdaPinMux[8]; + +/** Offset 0x01F4 - Serial IO I2C SCL Pin Muxing + Select SerialIo I2c Scl pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SCL* for + possible values. +**/ + UINT32 PchSerialIoI2cSclPinMux[8]; + +/** Offset 0x0214 - PCH SerialIo I2C Pads Termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C0,I2C1,... pads termination + respectively. One byte for each controller, byte0 for I2C0, byte1 for I2C1, and so on. +**/ + UINT8 PchSerialIoI2cPadsTermination[8]; + +/** Offset 0x021C - ISH GP GPIO Pin Muxing + Determines ISH GP GPIO Pin muxing. See GPIO_*_MUXING_ISH_GP_x_GPIO_*. 'x' are GP_NUMBER +**/ + UINT32 IshGpGpioPinMuxing[8]; + +/** Offset 0x023C - ISH UART Rx Pin Muxing + Determines ISH UART Rx Pin muxing. See GPIO_*_MUXING_ISH_UARTx_TXD_* +**/ + UINT32 IshUartRxPinMuxing[3]; + +/** Offset 0x0248 - ISH UART Tx Pin Muxing + Determines ISH UART Tx Pin muxing. See GPIO_*_MUXING_ISH_UARTx_RXD_* +**/ + UINT32 IshUartTxPinMuxing[3]; + +/** Offset 0x0254 - ISH UART Rts Pin Muxing + Select ISH UART Rts Pin muxing. Refer to GPIO_*_MUXING_ISH_UARTx_RTS_* for possible values. +**/ + UINT32 IshUartRtsPinMuxing[3]; + +/** Offset 0x0260 - ISH UART Rts Pin Muxing + Select ISH UART Cts Pin muxing. Refer to GPIO_*_MUXING_ISH_UARTx_CTS_* for possible values. +**/ + UINT32 IshUartCtsPinMuxing[3]; + +/** Offset 0x026C - ISH I2C SDA Pin Muxing + Select ISH I2C SDA Pin muxing. Refer to GPIO_*_MUXING_ISH_I2Cx_SDA_* for possible values. +**/ + UINT32 IshI2cSdaPinMuxing[3]; + +/** Offset 0x0278 - ISH I2C SCL Pin Muxing + Select ISH I2C SCL Pin muxing. Refer to GPIO_*_MUXING_ISH_I2Cx_SCL_* for possible values. +**/ + UINT32 IshI2cSclPinMuxing[3]; + +/** Offset 0x0284 - ISH SPI MOSI Pin Muxing + Select ISH SPI MOSI Pin muxing. Refer to GPIO_*_MUXING_ISH_SPIx_MOSI_* for possible values. +**/ + UINT32 IshSpiMosiPinMuxing[2]; + +/** Offset 0x028C - ISH SPI MISO Pin Muxing + Select ISH SPI MISO Pin muxing. Refer to GPIO_*_MUXING_ISH_SPIx_MISO_* for possible values. +**/ + UINT32 IshSpiMisoPinMuxing[2]; + +/** Offset 0x0294 - ISH SPI CLK Pin Muxing + Select ISH SPI CLK Pin muxing. Refer to GPIO_*_MUXING_ISH_SPIx_CLK_* for possible values. +**/ + UINT32 IshSpiClkPinMuxing[2]; + +/** Offset 0x029C - ISH SPI CS#N Pin Muxing + Select ISH SPI CS#N Pin muxing. Refer to GPIO_*_MUXING_ISH_SPIx_CS_* for possible + values. N-SPI number, 0-1. +**/ + UINT32 IshSpiCsPinMuxing[4]; + +/** Offset 0x02AC - ISH GP GPIO Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo GP#N GPIO pads termination + respectively. #N are GP_NUMBER, not strictly relate to indexes of this table. Index + 0-23 -> ISH_GP_0-23, Index 24-25 -> ISH_GP_30-31 +**/ + UINT8 IshGpGpioPadTermination[8]; + +/** Offset 0x02B4 - ISH UART Rx Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo UART#N Rx pads termination + respectively. #N-byte for each controller, byte0 for UART0 Rx, byte1 for UART1 + Rx, and so on. +**/ + UINT8 IshUartRxPadTermination[3]; + +/** Offset 0x02B7 - ISH UART Tx Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo UART#N Tx pads termination + respectively. #N-byte for each controller, byte0 for UART0 Tx, byte1 for UART1 + Tx, and so on. +**/ + UINT8 IshUartTxPadTermination[3]; + +/** Offset 0x02BA - ISH UART Rts Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo UART#N Rts pads termination + respectively. #N-byte for each controller, byte0 for UART0 Rts, byte1 for UART1 + Rts, and so on. +**/ + UINT8 IshUartRtsPadTermination[3]; + +/** Offset 0x02BD - ISH UART Rts Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo UART#N Cts pads termination + respectively. #N-byte for each controller, byte0 for UART0 Cts, byte1 for UART1 + Cts, and so on. +**/ + UINT8 IshUartCtsPadTermination[3]; + +/** Offset 0x02C0 - ISH I2C SDA Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C#N Sda pads termination + respectively. #N-byte for each controller, byte0 for I2C0 Sda, byte1 for I2C1 Sda, + and so on. +**/ + UINT8 IshI2cSdaPadTermination[3]; + +/** Offset 0x02C3 - ISH I2C SCL Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C#N Scl pads termination + respectively. #N-byte for each controller, byte0 for I2C0 Scl, byte1 for I2C1 Scl, + and so on. +**/ + UINT8 IshI2cSclPadTermination[3]; + +/** Offset 0x02C6 - ISH SPI MOSI Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo SPI#N Mosi pads termination + respectively. #N-byte for each controller, byte0 for SPI0 Mosi, byte1 for SPI1 + Mosi, and so on. +**/ + UINT8 IshSpiMosiPadTermination[2]; + +/** Offset 0x02C8 - ISH SPI MISO Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo SPI#N Miso pads termination + respectively. #N-byte for each controller, byte0 for SPI0 Miso, byte1 for SPI1 + Miso, and so on. +**/ + UINT8 IshSpiMisoPadTermination[2]; + +/** Offset 0x02CA - ISH SPI CLK Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo SPI#N Clk pads termination + respectively. #N-byte for each controller, byte0 for SPI0 Clk, byte1 for SPI1 Clk, + and so on. +**/ + UINT8 IshSpiClkPadTermination[2]; + +/** Offset 0x02CC - ISH SPI CS#N Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo SPI#N Cs#M pads termination + respectively. N*M-byte for each controller, byte0 for SPI0 Cs0, byte1 for SPI1 + Cs1, SPI1 Cs0, byte2, SPI1 Cs1, byte3 +**/ + UINT8 IshSpiCsPadTermination[4]; + +/** Offset 0x02D0 - Enable PCH ISH SPI Cs#N pins assigned + Set if ISH SPI Cs#N pins are to be enabled by BIOS. 0: Disable; 1: Enable. N-Cs + number: 0-1 +**/ + UINT8 PchIshSpiCsEnable[4]; + +/** Offset 0x02D4 - USB Per Port HS Preemphasis Bias + USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, + 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV. One byte for each port. +**/ + UINT8 Usb2PhyPetxiset[16]; + +/** Offset 0x02E4 - USB Per Port HS Transmitter Bias + USB Per Port HS Transmitter Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, + 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV, One byte for each port. +**/ + UINT8 Usb2PhyTxiset[16]; + +/** Offset 0x02F4 - USB Per Port HS Transmitter Emphasis + USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON, + 10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port. +**/ + UINT8 Usb2PhyPredeemp[16]; + +/** Offset 0x0304 - USB Per Port Half Bit Pre-emphasis + USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis. + One byte for each port. +**/ + UINT8 Usb2PhyPehalfbit[16]; + +/** Offset 0x0314 - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment + Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment. Each value + in arrary can be between 0-1. One byte for each port. +**/ + UINT8 Usb3HsioTxDeEmphEnable[10]; + +/** Offset 0x031E - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting + USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16], + Default = 29h (approximately -3.5dB De-Emphasis). One byte for each port. +**/ + UINT8 Usb3HsioTxDeEmph[10]; + +/** Offset 0x0328 - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment + Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value + in arrary can be between 0-1. One byte for each port. +**/ + UINT8 Usb3HsioTxDownscaleAmpEnable[10]; + +/** Offset 0x0332 - USB 3.0 TX Output Downscale Amplitude Adjustment + USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], Default + = 00h. One byte for each port. +**/ + UINT8 Usb3HsioTxDownscaleAmp[10]; + +/** Offset 0x033C +**/ + UINT8 PchUsb3HsioCtrlAdaptOffsetCfgEnable[10]; + +/** Offset 0x0346 +**/ + UINT8 PchUsb3HsioFilterSelNEnable[10]; + +/** Offset 0x0350 +**/ + UINT8 PchUsb3HsioFilterSelPEnable[10]; + +/** Offset 0x035A +**/ + UINT8 PchUsb3HsioOlfpsCfgPullUpDwnResEnable[10]; + +/** Offset 0x0364 +**/ + UINT8 PchUsb3HsioCtrlAdaptOffsetCfg[10]; + +/** Offset 0x036E +**/ + UINT8 PchUsb3HsioOlfpsCfgPullUpDwnRes[10]; + +/** Offset 0x0378 +**/ + UINT8 PchUsb3HsioFilterSelN[10]; + +/** Offset 0x0382 +**/ + UINT8 PchUsb3HsioFilterSelP[10]; + +/** Offset 0x038C - Enable LAN + Enable/disable LAN controller. + $EN_DIS +**/ + UINT8 PchLanEnable; + +/** Offset 0x038D - Enable PCH TSN + Enable/disable TSN on the PCH. + $EN_DIS +**/ + UINT8 PchTsnEnable; + +/** Offset 0x038E - TSN Link Speed + Set TSN Link Speed. + 0: 24Mhz 2.5Gbps, 1: 24Mhz 1Gbps, 2: 38.4Mhz 2.5Gbps, 3: 38.4Mhz 1Gbps +**/ + UINT8 PchTsnLinkSpeed; + +/** Offset 0x038F +**/ + UINT8 UnusedUpdSpace6; + +/** Offset 0x0390 - PCH TSN MAC Address High Bits + Set TSN MAC Address High. +**/ + UINT32 PchTsnMacAddressHigh; + +/** Offset 0x0394 - PCH TSN MAC Address Low Bits + Set TSN MAC Address Low. +**/ + UINT32 PchTsnMacAddressLow; + +/** Offset 0x0398 - PCIe PTM enable/disable + Enable/disable Precision Time Measurement for PCIE Root Ports. +**/ + UINT8 PciePtm[28]; + +/** Offset 0x03B4 - PCIe DPC enable/disable + Enable/disable Downstream Port Containment for PCIE Root Ports. +**/ + UINT8 PcieDpc[28]; + +/** Offset 0x03D0 - PCIe DPC extensions enable/disable + Enable/disable Downstream Port Containment Extensions for PCIE Root Ports. +**/ + UINT8 PcieEdpc[28]; + +/** Offset 0x03EC - USB PDO Programming + Enable/disable PDO programming for USB in PEI phase. Disabling will allow for programming + during later phase. 1: enable, 0: disable + $EN_DIS +**/ + UINT8 UsbPdoProgramming; + +/** Offset 0x03ED +**/ + UINT8 UnusedUpdSpace7[3]; + +/** Offset 0x03F0 - Power button debounce configuration + Debounce time for PWRBTN in microseconds. For values not supported by HW, they will + be rounded down to closest supported on. 0: disable, 250-1024000us: supported range +**/ + UINT32 PmcPowerButtonDebounce; + +/** Offset 0x03F4 - PCH eSPI Host and Device BME enabled + PCH eSPI Host and Device BME enabled + $EN_DIS +**/ + UINT8 PchEspiBmeMasterSlaveEnabled; + +/** Offset 0x03F5 - PCH eSPI Link Configuration Lock (SBLCL) + Enable/Disable lock of communication through SET_CONFIG/GET_CONFIG to eSPI slaves + addresseses from range 0x0 - 0x7FF + $EN_DIS +**/ + UINT8 PchEspiLockLinkConfiguration; + +/** Offset 0x03F6 - Mask to enable the usage of external V1p05 VR rail in specific S0ix or Sx states + Enable External V1P05 Rail in: BIT0:S0i1/S0i2, BIT1:S0i3, BIT2:S3, BIT3:S4, BIT4:S5, BIT5:S0 +**/ + UINT8 PchFivrExtV1p05RailEnabledStates; + +/** Offset 0x03F7 - Mask to enable the platform configuration of external V1p05 VR rail + External V1P05 Rail Supported Configuration +**/ + UINT8 PchFivrExtV1p05RailSupportedVoltageStates; + +/** Offset 0x03F8 - External V1P05 Voltage Value that will be used in S0i2/S0i3 states + Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...) +**/ + UINT16 PchFivrExtV1p05RailVoltage; + +/** Offset 0x03FA - External V1P05 Icc Max Value + Granularity of this setting is 1mA and maximal possible value is 200mA +**/ + UINT8 PchFivrExtV1p05RailIccMax; + +/** Offset 0x03FB - Mask to enable the usage of external Vnn VR rail in specific S0ix or Sx states + Enable External Vnn Rail in: BIT0:S0i1/S0i2, BIT1:S0i3, BIT2:S3, BIT3:S4, BIT5:S5 +**/ + UINT8 PchFivrExtVnnRailEnabledStates; + +/** Offset 0x03FC - Mask to enable the platform configuration of external Vnn VR rail + External Vnn Rail Supported Configuration +**/ + UINT8 PchFivrExtVnnRailSupportedVoltageStates; + +/** Offset 0x03FD +**/ + UINT8 UnusedUpdSpace8; + +/** Offset 0x03FE - External Vnn Voltage Value that will be used in S0ix/Sx states + Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...), Default is set to 420 +**/ + UINT16 PchFivrExtVnnRailVoltage; + +/** Offset 0x0400 - External Vnn Icc Max Value that will be used in S0ix/Sx states + Granularity of this setting is 1mA and maximal possible value is 200mA +**/ + UINT8 PchFivrExtVnnRailIccMax; + +/** Offset 0x0401 - Mask to enable the usage of external Vnn VR rail in Sx states + Use only if Ext Vnn Rail config is different in Sx. Enable External Vnn Rail in + Sx: BIT0-1:Reserved, BIT2:S3, BIT3:S4, BIT4:S5, BIT5:S0 +**/ + UINT8 PchFivrExtVnnRailSxEnabledStates; + +/** Offset 0x0402 - External Vnn Voltage Value that will be used in Sx states + Use only if Ext Vnn Rail config is different in Sx. Value is given in 2.5mV increments + (0=0mV, 1=2.5mV, 2=5mV...) +**/ + UINT16 PchFivrExtVnnRailSxVoltage; + +/** Offset 0x0404 - External Vnn Icc Max Value that will be used in Sx states + Use only if Ext Vnn Rail config is different in Sx. Granularity of this setting + is 1mA and maximal possible value is 200mA +**/ + UINT8 PchFivrExtVnnRailSxIccMax; + +/** Offset 0x0405 - Transition time in microseconds from Low Current Mode Voltage to High Current Mode Voltage + This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX + to low current mode voltage. +**/ + UINT8 PchFivrVccinAuxLowToHighCurModeVolTranTime; + +/** Offset 0x0406 - Transition time in microseconds from Retention Mode Voltage to High Current Mode Voltage + This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX + to retention mode voltage. +**/ + UINT8 PchFivrVccinAuxRetToHighCurModeVolTranTime; + +/** Offset 0x0407 - Transition time in microseconds from Retention Mode Voltage to Low Current Mode Voltage + This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX + to retention mode voltage. +**/ + UINT8 PchFivrVccinAuxRetToLowCurModeVolTranTime; + +/** Offset 0x0408 - Transition time in microseconds from Off (0V) to High Current Mode Voltage + This field has 1us resolution. When value is 0 Transition to 0V is disabled. +**/ + UINT16 PchFivrVccinAuxOffToHighCurModeVolTranTime; + +/** Offset 0x040A - PMC Debug Message Enable + When Enabled, PMC HW will send debug messages to trace hub; When Disabled, PMC HW + will never send debug meesages to trace hub. Noted: When Enabled, may not enter S0ix + $EN_DIS +**/ + UINT8 PmcDbgMsgEn; + +/** Offset 0x040B +**/ + UINT8 UnusedUpdSpace9; + +/** Offset 0x040C - Pointer of ChipsetInit Binary + ChipsetInit Binary Pointer. +**/ + UINT32 ChipsetInitBinPtr; + +/** Offset 0x0410 - Length of ChipsetInit Binary + ChipsetInit Binary Length. +**/ + UINT32 ChipsetInitBinLen; + +/** Offset 0x0414 - FIVR Dynamic Power Management + Enable/Disable FIVR Dynamic Power Management. + $EN_DIS +**/ + UINT8 PchFivrDynPm; + +/** Offset 0x0415 +**/ + UINT8 UnusedUpdSpace10; + +/** Offset 0x0416 - External V1P05 Icc Max Value + Granularity of this setting is 1mA and maximal possible value is 500mA +**/ + UINT16 PchFivrExtV1p05RailIccMaximum; + +/** Offset 0x0418 - External Vnn Icc Max Value that will be used in S0ix/Sx states + Granularity of this setting is 1mA and maximal possible value is 500mA +**/ + UINT16 PchFivrExtVnnRailIccMaximum; + +/** Offset 0x041A - External Vnn Icc Max Value that will be used in Sx states + Use only if Ext Vnn Rail config is different in Sx. Granularity of this setting + is 1mA and maximal possible value is 500mA +**/ + UINT16 PchFivrExtVnnRailSxIccMaximum; + +/** Offset 0x041C - Extented BIOS Direct Read Decode enable + Enable/Disable access to bigger than 16MB BIOS Region through Direct Memory Reads. + 0: disabled (default), 1: enabled + $EN_DIS +**/ + UINT8 PchSpiExtendedBiosDecodeRangeEnable; + +/** Offset 0x041D +**/ + UINT8 UnusedUpdSpace11[3]; + +/** Offset 0x0420 - Extended BIOS Direct Read Decode Range base + Bits of 31:16 of a memory address that'll be a base for Extended BIOS Direct Read Decode. +**/ + UINT32 PchSpiExtendedBiosDecodeRangeBase; + +/** Offset 0x0424 - Extended BIOS Direct Read Decode Range limit + Bits of 31:16 of a memory address that'll be a limit for Extended BIOS Direct Read Decode. +**/ + UINT32 PchSpiExtendedBiosDecodeRangeLimit; + +/** Offset 0x0428 - USB Audio Offload enable + Enable/Disable USB Audio Offload capabilites. 0: disabled, 1: enabled (default) + $EN_DIS +**/ + UINT8 PchXhciUaolEnable; + +/** Offset 0x0429 +**/ + UINT8 UnusedUpdSpace12[3]; + +/** Offset 0x042C - Pointer of SYNPS PHY Binary + ChipsetInit Binary Pointer. +**/ + UINT32 SynpsPhyBinPtr; + +/** Offset 0x0430 - Length of SYNPS PHY Binary + ChipsetInit Binary Length. +**/ + UINT32 SynpsPhyBinLen; + +/** Offset 0x0434 - CNVi Configuration + This option allows for automatic detection of Connectivity Solution. [Auto Detection] + assumes that CNVi will be enabled when available, [Disable] allows for disabling CNVi. + 0:Disable, 1:Auto +**/ + UINT8 CnviMode; + +/** Offset 0x0435 - CNVi Wi-Fi Core + Enable/Disable CNVi Wi-Fi Core, Default is ENABLE. 0: DISABLE, 1: ENABLE + $EN_DIS +**/ + UINT8 CnviWifiCore; + +/** Offset 0x0436 - CNVi BT Core + Enable/Disable CNVi BT Core, Default is ENABLE. 0: DISABLE, 1: ENABLE + $EN_DIS +**/ + UINT8 CnviBtCore; + +/** Offset 0x0437 - CNVi BT Audio Offload + Enable/Disable BT Audio Offload, Default is DISABLE. 0: DISABLE, 1: ENABLE + $EN_DIS +**/ + UINT8 CnviBtAudioOffload; + +/** Offset 0x0438 - CNVi RF_RESET pin muxing + Select CNVi RF_RESET# pin depending on board routing. ADP-P/M: GPP_A8 = 0x2942E408(default) + or GPP_F4 = 0x194CE404. ADP-S: 0. Refer to GPIO_*_MUXING_CNVI_RF_RESET_* in GpioPins*.h. +**/ + UINT32 CnviRfResetPinMux; + +/** Offset 0x043C - CNVi CLKREQ pin muxing + Select CNVi CLKREQ pin depending on board routing. ADP-P/M: GPP_A9 = 0x3942E609(default) + or GPP_F5 = 0x394CE605. ADP-S: 0. Refer to GPIO_*_MUXING_CNVI_CRF_XTAL_CLKREQ_* + in GpioPins*.h. +**/ + UINT32 CnviClkreqPinMux; + +/** Offset 0x0440 - Enable Host C10 reporting through eSPI + Enable/disable Host C10 reporting to Device via eSPI Virtual Wire. + $EN_DIS +**/ + UINT8 PchEspiHostC10ReportEnable; + +/** Offset 0x0441 - PCH USB2 PHY Power Gating enable + 1: Will enable USB2 PHY SUS Well Power Gating, 0: Will not enable PG of USB2 PHY + Sus Well PG + $EN_DIS +**/ + UINT8 PmcUsb2PhySusPgEnable; + +/** Offset 0x0442 - PCH USB OverCurrent mapping enable + 1: Will program USB OC pin mapping in xHCI controller memory, 0: Will clear OC pin + mapping allow for NOA usage of OC pins + $EN_DIS +**/ + UINT8 PchUsbOverCurrentEnable; + +/** Offset 0x0443 - Espi Lgmr Memory Range decode + This option enables or disables espi lgmr + $EN_DIS +**/ + UINT8 PchEspiLgmrEnable; + +/** Offset 0x0444 - External V1P05 Control Ramp Timer value + Hold off time to be used when changing the v1p05_ctrl for external bypass value in us +**/ + UINT8 PchFivrExtV1p05RailCtrlRampTmr; + +/** Offset 0x0445 - External VNN Control Ramp Timer value + Hold off time to be used when changing the vnn_ctrl for external bypass value in us +**/ + UINT8 PchFivrExtVnnRailCtrlRampTmr; + +/** Offset 0x0446 - Set SATA DEVSLP GPIO Reset Config + Set SATA DEVSLP GPIO Reset Config per port. 0x00 - GpioResetDefault, 0x01 - GpioResumeReset, + 0x03 - GpioHostDeepReset, 0x05 - GpioPlatformReset, 0x07 - GpioDswReset. One byte + for each port, byte0 for port0, byte1 for port1, and so on. +**/ + UINT8 SataPortsDevSlpResetConfig[8]; + +/** Offset 0x044E - PCHHOT# pin + Enable PCHHOT# pin assertion when temperature is higher than PchHotLevel. 0: disable, 1: enable + $EN_DIS +**/ + UINT8 PchHotEnable; + +/** Offset 0x044F - SATA LED + SATA LED indicating SATA controller activity. 0: disable, 1: enable + $EN_DIS +**/ + UINT8 SataLedEnable; + +/** Offset 0x0450 - VRAlert# Pin + When VRAlert# feature pin is enabled and its state is '0', the PMC requests throttling + to a T3 Tstate to the PCH throttling unit.. 0: disable, 1: enable + $EN_DIS +**/ + UINT8 PchPmVrAlert; + +/** Offset 0x0451 - AMT Switch + Enable/Disable. 0: Disable, 1: enable, Enable or disable AMT functionality. + $EN_DIS +**/ + UINT8 AmtEnabled; + +/** Offset 0x0452 - WatchDog Timer Switch + Enable/Disable. 0: Disable, 1: enable, Enable or disable WatchDog timer. Setting + is invalid if AmtEnabled is 0. + $EN_DIS +**/ + UINT8 WatchDogEnabled; + +/** Offset 0x0453 - PET Progress + Enable/Disable. 0: Disable, 1: enable, Enable/Disable PET Events Progress to receive + PET Events. Setting is invalid if AmtEnabled is 0. + $EN_DIS +**/ + UINT8 FwProgress; + +/** Offset 0x0454 - SOL Switch + Enable/Disable. 0: Disable, 1: enable, Serial Over Lan enable/disable state by Mebx. + Setting is invalid if AmtEnabled is 0. + $EN_DIS +**/ + UINT8 AmtSolEnabled; + +/** Offset 0x0455 +**/ + UINT8 UnusedUpdSpace13; + +/** Offset 0x0456 - OS Timer + 16 bits Value, Set OS watchdog timer. Setting is invalid if AmtEnabled is 0. +**/ + UINT16 WatchDogTimerOs; + +/** Offset 0x0458 - BIOS Timer + 16 bits Value, Set BIOS watchdog timer. Setting is invalid if AmtEnabled is 0. +**/ + UINT16 WatchDogTimerBios; + +/** Offset 0x045A - Force MEBX execution + Enable/Disable. 0: Disable, 1: enable, Force MEBX execution. + $EN_DIS +**/ + UINT8 ForcMebxSyncUp; + +/** Offset 0x045B - PCH PCIe root port connection type + 0: built-in device, 1:slot +**/ + UINT8 PcieRpSlotImplemented[28]; + +/** Offset 0x0477 - PCIE RP Access Control Services Extended Capability + Enable/Disable PCIE RP Access Control Services Extended Capability +**/ + UINT8 PcieRpAcsEnabled[28]; + +/** Offset 0x0493 - PCIE RP Clock Power Management + Enable/Disable PCIE RP Clock Power Management, even if disabled, CLKREQ# signal + can still be controlled by L1 PM substates mechanism +**/ + UINT8 PcieRpEnableCpm[28]; + +/** Offset 0x04AF +**/ + UINT8 UnusedUpdSpace14[1]; + +/** Offset 0x04B0 - PCIE RP Detect Timeout Ms + The number of milliseconds within 0~65535 in reference code will wait for link to + exit Detect state for enabled ports before assuming there is no device and potentially + disabling the port. +**/ + UINT16 PcieRpDetectTimeoutMs[28]; + +/** Offset 0x04E8 - ModPHY SUS Power Domain Dynamic Gating + Enable/Disable ModPHY SUS Power Domain Dynamic Gating. Setting not supported on + PCH-H. 0: disable, 1: enable + $EN_DIS +**/ + UINT8 PmcModPhySusPgEnable; + +/** Offset 0x04E9 - V1p05-PHY supply external FET control + Enable/Disable control using EXT_PWR_GATE# pin of external FET to power gate v1p05-PHY + supply. 0: disable, 1: enable + $EN_DIS +**/ + UINT8 PmcV1p05PhyExtFetControlEn; + +/** Offset 0x04EA - V1p05-IS supply external FET control + Enable/Disable control using EXT_PWR_GATE2# pin of external FET to power gate v1p05-IS + supply. 0: disable, 1: enable + $EN_DIS +**/ + UINT8 PmcV1p05IsExtFetControlEn; + +/** Offset 0x04EB - Enable/Disable PavpEnable + Enable(Default): Enable PavpEnable, Disable: Disable PavpEnable + $EN_DIS +**/ + UINT8 PavpEnable; + +/** Offset 0x04EC - CdClock Frequency selection + 0 (Default) Auto (Max based on reference clock frequency), 0: 192, 1: 307.2, 2: + 312 Mhz, 3: 324Mhz, 4: 326.4 Mhz, 5: 552 Mhz, 6: 556.8 Mhz, 7: 648 Mhz, 8: 652.8 Mhz + 0xFF: Auto (Max based on reference clock frequency), 0: 192, 1: 307.2, 2: 312 Mhz, + 3: 324Mhz, 4: 326.4 Mhz, 5: 552 Mhz, 6: 556.8 Mhz, 7: 648 Mhz, 8: 652.8 Mhz +**/ + UINT8 CdClock; + +/** Offset 0x04ED - Enable/Disable PeiGraphicsPeimInit + Enable(Default): FSP will initialize the framebuffer and provide it via EFI_PEI_GRAPHICS_INFO_HOB. + Disable: FSP will NOT initialize the framebuffer. + $EN_DIS +**/ + UINT8 PeiGraphicsPeimInit; + +/** Offset 0x04EE - Enable D3 Hot in TCSS + This policy will enable/disable D3 hot support in IOM + $EN_DIS +**/ + UINT8 D3HotEnable; + +/** Offset 0x04EF - Enable or disable GNA device + 0=Disable, 1(Default)=Enable + $EN_DIS +**/ + UINT8 GnaEnable; + +/** Offset 0x04F0 - TypeC port GPIO setting + GPIO Ping number for Type C Aux Oritation setting, use the GpioPad that is defined + in GpioPinsXXXH.h and GpioPinsXXXLp.h as argument.(XXX is platform name, Ex: Adl + = AlderLake) +**/ + UINT32 IomTypeCPortPadCfg[8]; + +/** Offset 0x0510 - CPU USB3 Port Over Current Pin + Describe the specific over current pin number of USBC Port N. +**/ + UINT8 CpuUsb3OverCurrentPin[8]; + +/** Offset 0x0518 - Enable D3 Cold in TCSS + This policy will enable/disable D3 cold support in IOM + $EN_DIS +**/ + UINT8 D3ColdEnable; + +/** Offset 0x0519 - Enable/Disable PCIe tunneling for USB4 + Enable/Disable PCIe tunneling for USB4, default is enable + $EN_DIS +**/ + UINT8 ITbtPcieTunnelingForUsb4; + +/** Offset 0x051A - Enable/Disable SkipFspGop + Enable: Skip FSP provided GOP driver, Disable(Default): Use FSP provided GOP driver + $EN_DIS +**/ + UINT8 SkipFspGop; + +/** Offset 0x051B - TC State in TCSS + This TC C-State Limit in IOM +**/ + UINT8 TcCstateLimit; + +/** Offset 0x051C - Intel Graphics VBT (Video BIOS Table) Size + Size of Internal Graphics VBT Image +**/ + UINT32 VbtSize; + +/** Offset 0x0520 - Platform LID Status for LFP Displays. + LFP Display Lid Status (LID_STATUS enum): 0 (Default): LidClosed, 1: LidOpen. + 0: LidClosed, 1: LidOpen +**/ + UINT8 LidStatus; + +/** Offset 0x0521 - Set Iom stay in TC cold seconds in TCSS + Set Iom stay in TC cold seconds in IOM +**/ + UINT8 IomStayInTCColdSeconds; + +/** Offset 0x0522 - Set Iom before entering TC cold seconds in TCSS + Set Iom before entering TC cold seconds in IOM +**/ + UINT8 IomBeforeEnteringTCColdSeconds; + +/** Offset 0x0523 - SaPostMemRsvd + Reserved for PCH Post-Mem + $EN_DIS +**/ + UINT8 SaPostMemRsvd[5]; + +/** Offset 0x0528 - PCH xHCI enable HS Interrupt IN Alarm + PCH xHCI enable HS Interrupt IN Alarm. 0: disabled (default), 1: enabled + $EN_DIS +**/ + UINT8 PchXhciHsiiEnable; + +/** Offset 0x0529 - Enable VMD controller + Enable/disable to VMD controller.0: Disable; 1: Enable(Default) + $EN_DIS +**/ + UINT8 VmdEnable; + +/** Offset 0x052A - Map port under VMD + Map/UnMap port under VMD + $EN_DIS +**/ + UINT8 VmdPort[31]; + +/** Offset 0x0549 - VMD Port Device + VMD Root port device number. +**/ + UINT8 VmdPortDev[31]; + +/** Offset 0x0568 - VMD Port Func + VMD Root port function number. +**/ + UINT8 VmdPortFunc[31]; + +/** Offset 0x0587 - VMD Config Bar size + Set The VMD Config Bar Size. +**/ + UINT8 VmdCfgBarSize; + +/** Offset 0x0588 - VMD Config Bar Attributes + 0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_NONPREFETCH(Default), 2: VMD_64BIT_PREFETCH + 0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_NONPREFETCH, 2: VMD_64BIT_PREFETCH +**/ + UINT8 VmdCfgBarAttr; + +/** Offset 0x0589 - VMD Mem Bar1 size + Set The VMD Mem Bar1 Size. +**/ + UINT8 VmdMemBarSize1; + +/** Offset 0x058A - VMD Mem Bar1 Attributes + 0: VMD_32BIT_NONPREFETCH(Default), 1: VMD_64BIT_NONPREFETCH, 2: VMD_64BIT_PREFETCH + 0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_NONPREFETCH, 2: VMD_64BIT_PREFETCH +**/ + UINT8 VmdMemBar1Attr; + +/** Offset 0x058B - VMD Mem Bar2 size + Set The VMD Mem Bar2 Size. +**/ + UINT8 VmdMemBarSize2; + +/** Offset 0x058C - VMD Mem Bar2 Attributes + 0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_NONPREFETCH(Default), 2: VMD_64BIT_PREFETCH + 0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_NONPREFETCH, 2: VMD_64BIT_PREFETCH +**/ + UINT8 VmdMemBar2Attr; + +/** Offset 0x058D +**/ + UINT8 UnusedUpdSpace15[3]; + +/** Offset 0x0590 - VMD Variable + VMD Variable Pointer. +**/ + UINT32 VmdVariablePtr; + +/** Offset 0x0594 - Temporary CfgBar address for VMD + VMD Variable Pointer. +**/ + UINT32 VmdCfgBarBase; + +/** Offset 0x0598 - Temporary MemBar1 address for VMD + VMD Variable Pointer. +**/ + UINT32 VmdMemBar1Base; + +/** Offset 0x059C - Temporary MemBar2 address for VMD + VMD Variable Pointer. +**/ + UINT32 VmdMemBar2Base; + +/** Offset 0x05A0 - TCSS CPU USB PDO Programming + Enable/disable PDO programming for TCSS CPU USB in PEI phase. Disabling will allow + for programming during later phase. 1: enable, 0: disable + $EN_DIS +**/ + UINT8 TcssCpuUsbPdoProgramming; + +/** Offset 0x05A1 - Enable/Disable PMC-PD Solution + This policy will enable/disable PMC-PD Solution vs EC-TCPC Solution + $EN_DIS +**/ + UINT8 PmcPdEnable; + +/** Offset 0x05A2 - TCSS Aux Orientation Override Enable + Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides +**/ + UINT16 TcssAuxOri; + +/** Offset 0x05A4 - TCSS HSL Orientation Override Enable + Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides +**/ + UINT16 TcssHslOri; + +/** Offset 0x05A6 - USB override in IOM + This policy will enable/disable USB Connect override in IOM + $EN_DIS +**/ + UINT8 UsbOverride; + +/** Offset 0x05A7 - ITBT Root Port Enable + ITBT Root Port Enable, 0:Disable, 1:Enable + 0:Disable, 1:Enable +**/ + UINT8 ITbtPcieRootPortEn[4]; + +/** Offset 0x05AB - TCSS USB Port Enable + Bits 0, 1, ... max Type C port control enables +**/ + UINT8 UsbTcPortEn; + +/** Offset 0x05AC - ITBTForcePowerOn Timeout value + ITBTForcePowerOn value. Specified increment values in miliseconds. Range is 0-1000. + 100 = 100 ms. +**/ + UINT16 ITbtForcePowerOnTimeoutInMs; + +/** Offset 0x05AE - ITbtConnectTopology Timeout value + ITbtConnectTopologyTimeout value. Specified increment values in miliseconds. Range + is 0-10000. 100 = 100 ms. +**/ + UINT16 ITbtConnectTopologyTimeoutInMs; + +/** Offset 0x05B0 - VCCST request for IOM + This policy will enable/disable VCCST and also decides if message would be replayed in S4/S5 + $EN_DIS +**/ + UINT8 VccSt; + +/** Offset 0x05B1 +**/ + UINT8 UnusedUpdSpace16[1]; + +/** Offset 0x05B2 - ITBT DMA LTR + TCSS DMA1, DMA2 LTR value +**/ + UINT16 ITbtDmaLtr[2]; + +/** Offset 0x05B6 - Enable/Disable CrashLog + Enable(Default): Enable CPU CrashLog, Disable: Disable CPU CrashLog + $EN_DIS +**/ + UINT8 CpuCrashLogEnable; + +/** Offset 0x05B7 - Enable/Disable PTM + This policy will enable/disable Precision Time Measurement for TCSS PCIe Root Ports + $EN_DIS +**/ + UINT8 PtmEnabled[4]; + +/** Offset 0x05BB - PCIE RP Ltr Enable + Latency Tolerance Reporting Mechanism. +**/ + UINT8 SaPcieItbtRpLtrEnable[4]; + +/** Offset 0x05BF - PCIE RP Snoop Latency Override Mode + Latency Tolerance Reporting, Snoop Latency Override Mode. +**/ + UINT8 SaPcieItbtRpSnoopLatencyOverrideMode[4]; + +/** Offset 0x05C3 - PCIE RP Snoop Latency Override Multiplier + Latency Tolerance Reporting, Snoop Latency Override Multiplier. +**/ + UINT8 SaPcieItbtRpSnoopLatencyOverrideMultiplier[4]; + +/** Offset 0x05C7 +**/ + UINT8 UnusedUpdSpace17[1]; + +/** Offset 0x05C8 - PCIE RP Snoop Latency Override Value + Latency Tolerance Reporting, Snoop Latency Override Value. +**/ + UINT16 SaPcieItbtRpSnoopLatencyOverrideValue[4]; + +/** Offset 0x05D0 - PCIE RP Non Snoop Latency Override Mode + Latency Tolerance Reporting, Non-Snoop Latency Override Mode. +**/ + UINT8 SaPcieItbtRpNonSnoopLatencyOverrideMode[4]; + +/** Offset 0x05D4 - PCIE RP Non Snoop Latency Override Multiplier + Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier. +**/ + UINT8 SaPcieItbtRpNonSnoopLatencyOverrideMultiplier[4]; + +/** Offset 0x05D8 - PCIE RP Non Snoop Latency Override Value + Latency Tolerance Reporting, Non-Snoop Latency Override Value. +**/ + UINT16 SaPcieItbtRpNonSnoopLatencyOverrideValue[4]; + +/** Offset 0x05E0 - Force LTR Override + Force LTR Override. +**/ + UINT8 SaPcieItbtRpForceLtrOverride[4]; + +/** Offset 0x05E4 - PCIE RP Ltr Config Lock + 0: Disable; 1: Enable. +**/ + UINT8 SaPcieItbtRpLtrConfigLock[4]; + +/** Offset 0x05E8 - Advanced Encryption Standard (AES) feature + Enable or Disable Advanced Encryption Standard (AES) feature; 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 AesEnable; + +/** Offset 0x05E9 - Power State 3 enable/disable + PCODE MMIO Mailbox: Power State 3 enable/disable; 0: Disable; 1: Enable. + For all VR Indexes +**/ + UINT8 Psi3Enable[5]; + +/** Offset 0x05EE - Power State 4 enable/disable + PCODE MMIO Mailbox: Power State 4 enable/disable; 0: Disable; 1: Enable.For + all VR Indexes +**/ + UINT8 Psi4Enable[5]; + +/** Offset 0x05F3 +**/ + UINT8 UnusedUpdSpace18[1]; + +/** Offset 0x05F4 - Imon slope correction + PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values. + Range is 0-200. 125 = 1.25. 0: Auto.For all VR Indexes +**/ + UINT16 ImonSlope[5]; + +/** Offset 0x05FE - Imon offset correction + PCODE MMIO Mailbox: Imon offset correction. Value is a 2's complement signed integer. + Units 1/1000, Range 0-63999. For an offset = 12.580, use 12580. 0: Auto +**/ + UINT16 ImonOffset[5]; + +/** Offset 0x0608 - Enable/Disable BIOS configuration of VR + Enable/Disable BIOS configuration of VR; 0: Disable; 1: Enable.For all VR Indexes +**/ + UINT8 VrConfigEnable[5]; + +/** Offset 0x060D - Thermal Design Current enable/disable + PCODE MMIO Mailbox: Thermal Design Current enable/disable; 0: Disable; 1: + Enable.For all VR Indexes +**/ + UINT8 TdcEnable[5]; + +/** Offset 0x0612 +**/ + UINT8 UnusedUpdSpace19[2]; + +/** Offset 0x0614 - Thermal Design Current time window + PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds. + Range 1ms to 448s +**/ + UINT32 TdcTimeWindow[5]; + +/** Offset 0x0628 - Thermal Design Current Lock + PCODE MMIO Mailbox: Thermal Design Current Lock; 0: Disable; 1: Enable.For + all VR Indexes +**/ + UINT8 TdcLock[5]; + +/** Offset 0x062D - Platform Psys slope correction + PCODE MMIO Mailbox: Platform Psys slope correction. 0 - Auto Specified in + 1/100 increment values. Range is 0-200. 125 = 1.25 +**/ + UINT8 PsysSlope; + +/** Offset 0x062E - Platform Psys offset correction + PCODE MMIO Mailbox: Platform Psys offset correction. 0 - Auto Units 1/1000, + Range 0-63999. For an offset of 25.348, enter 25348. +**/ + UINT16 PsysOffset; + +/** Offset 0x0630 - Acoustic Noise Mitigation feature + Enable or Disable Acoustic Noise Mitigation feature. 0: Disabled; 1: Enabled + $EN_DIS +**/ + UINT8 AcousticNoiseMitigation; + +/** Offset 0x0631 - Disable Fast Slew Rate for Deep Package C States for VR domains + Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation + feature enabled. 0: False; 1: True + $EN_DIS +**/ + UINT8 FastPkgCRampDisable[5]; + +/** Offset 0x0636 - Slew Rate configuration for Deep Package C States for VR domains + Slew Rate configuration for Deep Package C States for VR domains based on Acoustic + Noise Mitigation feature enabled. ADL supports VCCIA FAST/2/4/8/16, VCCGT FAST/2/4/8 + and VCCSA FAST/2 0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16 + 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16 +**/ + UINT8 SlowSlewRate[5]; + +/** Offset 0x063B +**/ + UINT8 UnusedUpdSpace20[1]; + +/** Offset 0x063C - Thermal Design Current current limit + PCODE MMIO Mailbox: Thermal Design Current current limit. Specified in 1/8A units. + Range is 0-4095. 1000 = 125A. 0: Auto. For all VR Indexes +**/ + UINT16 TdcCurrentLimit[5]; + +/** Offset 0x0646 - AcLoadline + PCODE MMIO Mailbox: AcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is + 0-6249. Intel Recommended Defaults vary by domain and SKU. +**/ + UINT16 AcLoadline[5]; + +/** Offset 0x0650 - DcLoadline + PCODE MMIO Mailbox: DcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is + 0-6249.Intel Recommended Defaults vary by domain and SKU. +**/ + UINT16 DcLoadline[5]; + +/** Offset 0x065A - Power State 1 Threshold current + PCODE MMIO Mailbox: Power State 1 current cuttof in 1/4 Amp increments. Range is 0-128A. +**/ + UINT16 Psi1Threshold[5]; + +/** Offset 0x0664 - Power State 2 Threshold current + PCODE MMIO Mailbox: Power State 2 current cuttof in 1/4 Amp increments. Range is 0-128A. +**/ + UINT16 Psi2Threshold[5]; + +/** Offset 0x066E - Power State 3 Threshold current + PCODE MMIO Mailbox: Power State 3 current cuttof in 1/4 Amp increments. Range is 0-128A. +**/ + UINT16 Psi3Threshold[5]; + +/** Offset 0x0678 - Icc Max limit + PCODE MMIO Mailbox: VR Icc Max limit. 0-512A in 1/4 A units. 400 = 100A +**/ + UINT16 IccMax[5]; + +/** Offset 0x0682 - Enable or Disable TXT + Enable or Disable TXT; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 TxtEnable; + +/** Offset 0x0683 - Skip Multi-Processor Initialization + When this is skipped, boot loader must initialize processors before SilicionInit + API. 0: Initialize; 1: Skip + $EN_DIS +**/ + UINT8 SkipMpInit; + +/** Offset 0x0684 - FIVR RFI Frequency + PCODE MMIO Mailbox: Set the desired RFI frequency, in increments of 100KHz. 0: + Auto. Range varies based on XTAL clock: 0-1918 (Up to 191.8HMz) for 24MHz clock; + 0-1535 (Up to 153.5MHz) for 19MHz clock. +**/ + UINT16 FivrRfiFrequency; + +/** Offset 0x0686 - FIVR RFI Spread Spectrum + Set the Spread Spectrum Range. 1.5%; Range: 0.5%, 1%, 1.5%, 2%, 3%, 4%, 5%, + 6%. Each Range is translated to an encoded value for FIVR register. 0.5% = 0, 1% + = 3, 1.5% = 8, 2% = 18, 3% = 28, 4% = 34, 5% = 39, 6% = 44. +**/ + UINT8 FivrSpreadSpectrum; + +/** Offset 0x0687 +**/ + UINT8 UnusedUpdSpace21; + +/** Offset 0x0688 - CpuBistData + Pointer CPU BIST Data +**/ + UINT32 CpuBistData; + +/** Offset 0x068C - CpuMpPpi + Optional pointer to the boot loader's implementation of EFI_PEI_MP_SERVICES_PPI. + If not NULL, FSP will use the boot loader's implementation of multiprocessing. + See section 5.1.4 of the FSP Integration Guide for more details. +**/ + UINT32 CpuMpPpi; + +/** Offset 0x0690 - Pre Wake Randomization time + PCODE MMIO Mailbox: Acoustic Noise Mitigation Range.Defines the maximum pre-wake + randomization time in micro ticks.This can be programmed only if AcousticNoiseMitigation + is enabled. Range 0-255 0. +**/ + UINT8 PreWake; + +/** Offset 0x0691 - Ramp Up Randomization time + PCODE MMIO Mailbox: Acoustic Noise Mitigation Range.Defines the maximum Ramp Up + randomization time in micro ticks.This can be programmed only if AcousticNoiseMitigation + is enabled.Range 0-255 0. +**/ + UINT8 RampUp; + +/** Offset 0x0692 - Ramp Down Randomization time + PCODE MMIO Mailbox: Acoustic Noise Mitigation Range.Defines the maximum Ramp Down + randomization time in micro ticks.This can be programmed only if AcousticNoiseMitigation + is enabled.Range 0-255 0. +**/ + UINT8 RampDown; + +/** Offset 0x0693 +**/ + UINT8 UnusedUpdSpace22[1]; + +/** Offset 0x0694 - VR Voltage Limit + PCODE MMIO Mailbox: Voltage Limit. Range is 0 - 7999mV +**/ + UINT16 VrVoltageLimit[5]; + +/** Offset 0x069E - VccIn Aux Imon IccMax + PCODE MMIO Mailbox: VccIn Aux Imon IccMax. 0 - Auto Values are in 1/4 Amp + increments. Range is 0-512. +**/ + UINT16 VccInAuxImonIccImax; + +/** Offset 0x06A0 - Vsys Critical + PCODE MMIO Mailbox: Vsys Critical. 0: Disable; 1: Enable Range is 0-255. +**/ + UINT8 EnableVsysCritical; + +/** Offset 0x06A1 - Vsys Full Scale + Vsys Full Scale, Range is 0-255 +**/ + UINT8 VsysFullScale; + +/** Offset 0x06A2 - Vsys Critical Threshold + Vsys Critical Threshold, Range is 0-255 +**/ + UINT8 VsysCriticalThreshold; + +/** Offset 0x06A3 - Assertion Deglitch Mantissa + Assertion Deglitch Mantissa, Range is 0-255 +**/ + UINT8 VsysAssertionDeglitchMantissa; + +/** Offset 0x06A4 - Assertion Deglitch Exponent + Assertion Deglitch Exponent, Range is 0-255 +**/ + UINT8 VsysAssertionDeglitchExponent; + +/** Offset 0x06A5 - De assertion Deglitch Mantissa + De assertion Deglitch Mantissa, Range is 0-255 +**/ + UINT8 VsysDeassertionDeglitchMantissa; + +/** Offset 0x06A6 - De assertion Deglitch Exponent + De assertion Deglitch Exponent, Range is 0-255 +**/ + UINT8 VsysDeassertionDeglitchExponent; + +/** Offset 0x06A7 - VccIn Aux Imon slope correction + PCODE MMIO Mailbox: VccIn Aux Imon slope correction. 0 - Auto Specified in + 1/100 increment values. Range is 0-200. 125 = 1.25 +**/ + UINT8 VccInAuxImonSlope; + +/** Offset 0x06A8 - VccIn Aux Imon offset correction + PCODE MMIO Mailbox: VccIn Aux Imon offset correction. 0 - Auto Units 1/1000, + Range 0-63999. For an offset of 25.348, enter 25348. +**/ + UINT16 VccInAuxImonOffset; + +/** Offset 0x06AA - FIVR RFI Spread Spectrum Enable or disable + Enable or Disable FIVR RFI Spread Spectrum. 0: Disable ; 1: Enable +**/ + UINT8 FivrSpectrumEnable; + +/** Offset 0x06AB +**/ + UINT8 UnusedUpdSpace23[1]; + +/** Offset 0x06AC - VR Fast Vmode ICC Limit support + PCODE MMIO Mailbox: VR Fast Vmode ICC Limit support. 0-255A in 1/4 A units. 400 = 100A +**/ + UINT16 IccLimit[5]; + +/** Offset 0x06B6 +**/ + UINT8 CpuPostMemRsvd[2]; + +/** Offset 0x06B8 - PpinSupport to view Protected Processor Inventory Number + Enable or Disable or Auto (Based on End of Manufacturing flag. Disabled if this + flag is set) for PPIN Support + 0: Disable, 1: Enable, 2: Auto +**/ + UINT8 PpinSupport; + +/** Offset 0x06B9 - Enable or Disable Minimum Voltage Override + Enable or disable Minimum Voltage overrides ; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 EnableMinVoltageOverride; + +/** Offset 0x06BA - Min Voltage for Runtime + PCODE MMIO Mailbox: Minimum voltage for runtime. Valid if EnableMinVoltageOverride + = 1. Range 0 to 1999mV. 0: 0mV +**/ + UINT16 MinVoltageRuntime; + +/** Offset 0x06BC - Memory size per thread allocated for Processor Trace + Memory size per thread for Processor Trace. Processor Trace requires 2^N alignment + and size in bytes per thread, from 4KB to 128MB.\n + 0xff:none , 0:4k, 0x1:8k, 0x2:16k, 0x3:32k, 0x4:64k, 0x5:128k, 0x6:256k, + 0x7:512k, 0x8:1M, 0x9:2M, 0xa:4M. 0xb:8M, 0xc:16M, 0xd:32M, 0xe:64M, 0xf:128M +**/ + UINT8 ProcessorTraceMemSize; + +/** Offset 0x06BD +**/ + UINT8 UnusedUpdSpace24; + +/** Offset 0x06BE - Min Voltage for C8 + PCODE MMIO Mailbox: Minimum voltage for C8. Valid if EnableMinVoltageOverride = + 1. Range 0 to 1999mV. 0: 0mV +**/ + UINT16 MinVoltageC8; + +/** Offset 0x06C0 - Smbios Type4 Max Speed Override + Provide the option for platform to override the MaxSpeed field of Smbios Type 4. + If this value is not zero, it dominates the field. +**/ + UINT16 SmbiosType4MaxSpeedOverride; + +/** Offset 0x06C2 - Current root mean square + PCODE MMIO Mailbox: Current root mean square; 0: Disable; 1: Enable.For all + VR Indexes +**/ + UINT8 Irms[5]; + +/** Offset 0x06C7 - AvxDisable + Enable or Disable AVX Support. This only applicable when all small core is disabled. + 0: Enable, 1: Disable +**/ + UINT8 AvxDisable; + +/** Offset 0x06C8 - Avx3Disable + DEPRECATED + 0: Enable, 1: Disable +**/ + UINT8 Avx3Disable; + +/** Offset 0x06C9 - X2ApicSupport + Enable or Disable X2APIC Support + $EN_DIS +**/ + UINT8 X2ApicSupport; + +/** Offset 0x06CA - CPU VR Power Delivery Design + Used to communicate the power delivery design capability of the board. This value + is an enum of the available power delivery segments that are defined in the Platform + Design Guide. +**/ + UINT8 VrPowerDeliveryDesign; + +/** Offset 0x06CB - Enable/Disable VR FastVmode. The VR will initiate reactive protection if Fast Vmode is enabled. + Enable/Disable VR FastVmode; 0: Disable; 1: Enable.For all VR by domain + 0: Disable, 1: Enable +**/ + UINT8 EnableFastVmode[5]; + +/** Offset 0x06D0 - ReservedCpuPostMemProduction + Reserved for CPU Post-Mem Production + $EN_DIS +**/ + UINT8 ReservedCpuPostMemProduction[32]; + +/** Offset 0x06F0 - Enable Power Optimizer + Enable DMI Power Optimizer on PCH side. + $EN_DIS +**/ + UINT8 PchPwrOptEnable; + +/** Offset 0x06F1 - PCH Flash Protection Ranges Write Enble + Write or erase is blocked by hardware. +**/ + UINT8 PchWriteProtectionEnable[5]; + +/** Offset 0x06F6 - PCH Flash Protection Ranges Read Enble + Read is blocked by hardware. +**/ + UINT8 PchReadProtectionEnable[5]; + +/** Offset 0x06FB +**/ + UINT8 UnusedUpdSpace25[1]; + +/** Offset 0x06FC - PCH Protect Range Limit + Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for + limit comparison. +**/ + UINT16 PchProtectedRangeLimit[5]; + +/** Offset 0x0706 - PCH Protect Range Base + Left shifted address by 12 bits with address bits 11:0 are assumed to be 0. +**/ + UINT16 PchProtectedRangeBase[5]; + +/** Offset 0x0710 - Enable Pme + Enable Azalia wake-on-ring. + $EN_DIS +**/ + UINT8 PchHdaPme; + +/** Offset 0x0711 - HD Audio Link Frequency + HDA Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 0: 6MHz, 1: 12MHz, 2: 24MHz. + 0: 6MHz, 1: 12MHz, 2: 24MHz +**/ + UINT8 PchHdaLinkFrequency; + +/** Offset 0x0712 - Enable PCH ISH SPI Cs0 pins assigned + Set if ISH SPI Cs0 pins are to be enabled by BIOS. 0: Disable; 1: Enable. +**/ + UINT8 PchIshSpiCs0Enable[1]; + +/** Offset 0x0713 - Enable PCH Io Apic Entry 24-119 + 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 PchIoApicEntry24_119; + +/** Offset 0x0714 - PCH Io Apic ID + This member determines IOAPIC ID. Default is 0x02. +**/ + UINT8 PchIoApicId; + +/** Offset 0x0715 - Enable PCH ISH SPI pins assigned + Set if ISH SPI native pins are to be enabled by BIOS. 0: Disable; 1: Enable. +**/ + UINT8 PchIshSpiEnable[1]; + +/** Offset 0x0716 - Enable PCH ISH UART pins assigned + Set if ISH UART native pins are to be enabled by BIOS. 0: Disable; 1: Enable. +**/ + UINT8 PchIshUartEnable[2]; + +/** Offset 0x0718 - Enable PCH ISH I2C pins assigned + Set if ISH I2C native pins are to be enabled by BIOS. 0: Disable; 1: Enable. +**/ + UINT8 PchIshI2cEnable[3]; + +/** Offset 0x071B - Enable PCH ISH GP pins assigned + Set if ISH GP native pins are to be enabled by BIOS. 0: Disable; 1: Enable. +**/ + UINT8 PchIshGpEnable[8]; + +/** Offset 0x0723 - PCH ISH PDT Unlock Msg + 0: False; 1: True. + $EN_DIS +**/ + UINT8 PchIshPdtUnlock; + +/** Offset 0x0724 - Enable PCH Lan LTR capabilty of PCH internal LAN + 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 PchLanLtrEnable; + +/** Offset 0x0725 - Enable LOCKDOWN BIOS LOCK + Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region + protection. + $EN_DIS +**/ + UINT8 PchLockDownBiosLock; + +/** Offset 0x0726 - PCH Compatibility Revision ID + This member describes whether or not the CRID feature of PCH should be enabled. + $EN_DIS +**/ + UINT8 PchCrid; + +/** Offset 0x0727 - RTC BIOS Interface Lock + Enable RTC BIOS interface lock. When set, prevents RTC TS (BUC.TS) from being changed. + $EN_DIS +**/ + UINT8 RtcBiosInterfaceLock; + +/** Offset 0x0728 - RTC Cmos Memory Lock + Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper + and and lower 128-byte bank of RTC RAM. + $EN_DIS +**/ + UINT8 RtcMemoryLock; + +/** Offset 0x0729 - Enable PCIE RP HotPlug + Indicate whether the root port is hot plug available. +**/ + UINT8 PcieRpHotPlug[28]; + +/** Offset 0x0745 - Enable PCIE RP Pm Sci + Indicate whether the root port power manager SCI is enabled. +**/ + UINT8 PcieRpPmSci[28]; + +/** Offset 0x0761 - Enable PCIE RP Transmitter Half Swing + Indicate whether the Transmitter Half Swing is enabled. +**/ + UINT8 PcieRpTransmitterHalfSwing[28]; + +/** Offset 0x077D - Enable PCIE RP Clk Req Detect + Probe CLKREQ# signal before enabling CLKREQ# based power management. +**/ + UINT8 PcieRpClkReqDetect[28]; + +/** Offset 0x0799 - PCIE RP Advanced Error Report + Indicate whether the Advanced Error Reporting is enabled. +**/ + UINT8 PcieRpAdvancedErrorReporting[28]; + +/** Offset 0x07B5 - PCIE RP Unsupported Request Report + Indicate whether the Unsupported Request Report is enabled. +**/ + UINT8 PcieRpUnsupportedRequestReport[28]; + +/** Offset 0x07D1 - PCIE RP Fatal Error Report + Indicate whether the Fatal Error Report is enabled. +**/ + UINT8 PcieRpFatalErrorReport[28]; + +/** Offset 0x07ED - PCIE RP No Fatal Error Report + Indicate whether the No Fatal Error Report is enabled. +**/ + UINT8 PcieRpNoFatalErrorReport[28]; + +/** Offset 0x0809 - PCIE RP Correctable Error Report + Indicate whether the Correctable Error Report is enabled. +**/ + UINT8 PcieRpCorrectableErrorReport[28]; + +/** Offset 0x0825 - PCIE RP System Error On Fatal Error + Indicate whether the System Error on Fatal Error is enabled. +**/ + UINT8 PcieRpSystemErrorOnFatalError[28]; + +/** Offset 0x0841 - PCIE RP System Error On Non Fatal Error + Indicate whether the System Error on Non Fatal Error is enabled. +**/ + UINT8 PcieRpSystemErrorOnNonFatalError[28]; + +/** Offset 0x085D - PCIE RP System Error On Correctable Error + Indicate whether the System Error on Correctable Error is enabled. +**/ + UINT8 PcieRpSystemErrorOnCorrectableError[28]; + +/** Offset 0x0879 - PCIE RP Max Payload + Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD. +**/ + UINT8 PcieRpMaxPayload[28]; + +/** Offset 0x0895 - Touch Host Controller Port 0 Assignment + Assign THC Port 0 + 0x0:ThcAssignmentNone, 0x1:ThcAssignmentThc0 +**/ + UINT8 ThcPort0Assignment; + +/** Offset 0x0896 +**/ + UINT8 UnusedUpdSpace26[2]; + +/** Offset 0x0898 - Touch Host Controller Port 0 Interrupt Pin Mux + Set THC Port 0 Pin Muxing Value if signal can be enabled on multiple pads. Refer + to GPIO_*_MUXING_THC_SPIx_INTB_* for possible values. +**/ + UINT32 ThcPort0InterruptPinMuxing; + +/** Offset 0x089C - Touch Host Controller Port 0 Wake On Touch + Based on this setting vGPIO for given THC will be in native mode, and additional + _CRS for wake will be exposed in ACPI + $EN_DIS +**/ + UINT8 ThcPort0WakeOnTouch; + +/** Offset 0x089D - Touch Host Controller Port 1 Assignment + Assign THC Port 1 + 0x0:ThcAssignmentNone, 0x1:ThcPort1AssignmentThc0, 0x2:ThcAssignmentThc1 +**/ + UINT8 ThcPort1Assignment; + +/** Offset 0x089E +**/ + UINT8 UnusedUpdSpace27[2]; + +/** Offset 0x08A0 - Touch Host Controller Port 1 Interrupt Pin Mux + Set THC Port 1 Pin Muxing Value if signal can be enabled on multiple pads. Refer + to GPIO_*_MUXING_THC_SPIx_INTB_* for possible values. +**/ + UINT32 ThcPort1InterruptPinMuxing; + +/** Offset 0x08A4 - Touch Host Controller Port 1 Wake On Touch + Based on this setting vGPIO for given THC will be in native mode, and additional + _CRS for wake will be exposed in ACPI + $EN_DIS +**/ + UINT8 ThcPort1WakeOnTouch; + +/** Offset 0x08A5 - PCIE RP Pcie Speed + Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3; + 4: Gen4 (see: PCIE_SPEED). +**/ + UINT8 PcieRpPcieSpeed[28]; + +/** Offset 0x08C1 - PCIE RP Physical Slot Number + Indicates the slot number for the root port. Default is the value as root port index. +**/ + UINT8 PcieRpPhysicalSlotNumber[28]; + +/** Offset 0x08DD - PCIE RP Completion Timeout + The root port completion timeout(see: PCIE_COMPLETION_TIMEOUT). Default is PchPcieCompletionTO_Default. +**/ + UINT8 PcieRpCompletionTimeout[28]; + +/** Offset 0x08F9 - PCIE RP Aspm + The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is + PchPcieAspmAutoConfig. +**/ + UINT8 PcieRpAspm[28]; + +/** Offset 0x0915 - PCIE RP L1 Substates + The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL). + Default is PchPcieL1SubstatesL1_1_2. +**/ + UINT8 PcieRpL1Substates[28]; + +/** Offset 0x0931 - PCIE RP L1 Low Substate + The L1 Low Substate configuration of the root port. 0: Disable; 1: Enable. +**/ + UINT8 PcieRpL1Low[28]; + +/** Offset 0x094D - PCIE RP Ltr Enable + Latency Tolerance Reporting Mechanism. +**/ + UINT8 PcieRpLtrEnable[28]; + +/** Offset 0x0969 - PCIE RP Ltr Config Lock + 0: Disable; 1: Enable. +**/ + UINT8 PcieRpLtrConfigLock[28]; + +/** Offset 0x0985 - PCIe override default settings for EQ + Choose PCIe EQ method + $EN_DIS +**/ + UINT8 PcieEqOverrideDefault; + +/** Offset 0x0986 - PCIe choose EQ method + Choose PCIe EQ method + 0: HardwareEq, 1: FixedEq +**/ + UINT8 PcieEqMethod; + +/** Offset 0x0987 - PCIe choose EQ mode + Choose PCIe EQ mode + 0: PresetEq, 1: CoefficientEq +**/ + UINT8 PcieEqMode; + +/** Offset 0x0988 - PCIe EQ local transmitter override + Enable/Disable local transmitter override + $EN_DIS +**/ + UINT8 PcieEqLocalTransmitterOverrideEnable; + +/** Offset 0x0989 - PCIe number of valid list entries + Select number of presets or coefficients depending on the mode +**/ + UINT8 PcieEqPh3NumberOfPresetsOrCoefficients; + +/** Offset 0x098A - PCIe pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieEqPh3PreCursorList[10]; + +/** Offset 0x0994 - PCIe post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieEqPh3PostCursorList[10]; + +/** Offset 0x099E - PCIe preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieEqPh3PresetList[11]; + +/** Offset 0x09A9 +**/ + UINT8 UnusedUpdSpace28[3]; + +/** Offset 0x09AC - PCIe EQ phase 1 downstream transmitter port preset + Allows to select the downstream port preset value that will be used during phase + 1 of equalization +**/ + UINT32 PcieEqPh1DownstreamPortTransmitterPreset; + +/** Offset 0x09B0 - PCIe EQ phase 1 upstream tranmitter port preset + Allows to select the upstream port preset value that will be used during phase 1 + of equalization +**/ + UINT32 PcieEqPh1UpstreamPortTransmitterPreset; + +/** Offset 0x09B4 - PCIe EQ phase 2 local transmitter override preset + Allows to select the value of the preset used during phase 2 local transmitter override +**/ + UINT8 PcieEqPh2LocalTransmitterOverridePreset; + +/** Offset 0x09B5 - PCIE Enable Peer Memory Write + This member describes whether Peer Memory Writes are enabled on the platform. + $EN_DIS +**/ + UINT8 PcieEnablePeerMemoryWrite[28]; + +/** Offset 0x09D1 - PCIE Compliance Test Mode + Compliance Test Mode shall be enabled when using Compliance Load Board. + $EN_DIS +**/ + UINT8 PcieComplianceTestMode; + +/** Offset 0x09D2 - PCIE Rp Function Swap + DEPRECATED. Allows BIOS to use root port function number swapping when root port + of function 0 is disabled. + $EN_DIS +**/ + UINT8 PcieRpFunctionSwap; + +/** Offset 0x09D3 - Enable/Disable PEG GEN3 Static EQ Phase1 programming + Program Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static Presets + Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming + $EN_DIS +**/ + UINT8 CpuPcieGen3ProgramStaticEq; + +/** Offset 0x09D4 - Enable/Disable GEN4 Static EQ Phase1 programming + Program Gen4 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static Presets + Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming + $EN_DIS +**/ + UINT8 CpuPcieGen4ProgramStaticEq; + +/** Offset 0x09D5 - PCH Pm PME_B0_S5_DIS + When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1. + $EN_DIS +**/ + UINT8 PchPmPmeB0S5Dis; + +/** Offset 0x09D6 - PCIE IMR + Enables Isolated Memory Region for PCIe. + $EN_DIS +**/ + UINT8 PcieRpImrEnabled; + +/** Offset 0x09D7 - PCIE IMR port number + Selects PCIE root port number for IMR feature. +**/ + UINT8 PcieRpImrSelection; + +/** Offset 0x09D8 - PCH Pm Wol Enable Override + Corresponds to the WOL Enable Override bit in the General PM Configuration B (GEN_PMCON_B) register. + $EN_DIS +**/ + UINT8 PchPmWolEnableOverride; + +/** Offset 0x09D9 - PCH Pm Pcie Wake From DeepSx + Determine if enable PCIe to wake from deep Sx. + $EN_DIS +**/ + UINT8 PchPmPcieWakeFromDeepSx; + +/** Offset 0x09DA - PCH Pm WoW lan Enable + Determine if WLAN wake from Sx, corresponds to the HOST_WLAN_PP_EN bit in the PWRM_CFG3 register. + $EN_DIS +**/ + UINT8 PchPmWoWlanEnable; + +/** Offset 0x09DB - PCH Pm WoW lan DeepSx Enable + Determine if WLAN wake from DeepSx, corresponds to the DSX_WLAN_PP_EN bit in the + PWRM_CFG3 register. + $EN_DIS +**/ + UINT8 PchPmWoWlanDeepSxEnable; + +/** Offset 0x09DC - PCH Pm Lan Wake From DeepSx + Determine if enable LAN to wake from deep Sx. + $EN_DIS +**/ + UINT8 PchPmLanWakeFromDeepSx; + +/** Offset 0x09DD - PCH Pm Deep Sx Pol + Deep Sx Policy. + $EN_DIS +**/ + UINT8 PchPmDeepSxPol; + +/** Offset 0x09DE - PCH Pm Slp S3 Min Assert + SLP_S3 Minimum Assertion Width Policy. Default is PchSlpS350ms. +**/ + UINT8 PchPmSlpS3MinAssert; + +/** Offset 0x09DF - PCH Pm Slp S4 Min Assert + SLP_S4 Minimum Assertion Width Policy. Default is PchSlpS44s. +**/ + UINT8 PchPmSlpS4MinAssert; + +/** Offset 0x09E0 - PCH Pm Slp Sus Min Assert + SLP_SUS Minimum Assertion Width Policy. Default is PchSlpSus4s. +**/ + UINT8 PchPmSlpSusMinAssert; + +/** Offset 0x09E1 - PCH Pm Slp A Min Assert + SLP_A Minimum Assertion Width Policy. Default is PchSlpA2s. +**/ + UINT8 PchPmSlpAMinAssert; + +/** Offset 0x09E2 - USB Overcurrent Override for VISA + This option overrides USB Over Current enablement state that USB OC will be disabled + after enabling this option. Enable when VISA pin is muxed with USB OC + $EN_DIS +**/ + UINT8 PchEnableDbcObs; + +/** Offset 0x09E3 - PCH Pm Slp Strch Sus Up + Enable SLP_X Stretching After SUS Well Power Up. + $EN_DIS +**/ + UINT8 PchPmSlpStrchSusUp; + +/** Offset 0x09E4 - PCH Pm Slp Lan Low Dc + Enable/Disable SLP_LAN# Low on DC Power. + $EN_DIS +**/ + UINT8 PchPmSlpLanLowDc; + +/** Offset 0x09E5 - PCH Pm Pwr Btn Override Period + PCH power button override period. 000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s. +**/ + UINT8 PchPmPwrBtnOverridePeriod; + +/** Offset 0x09E6 - PCH Pm Disable Dsx Ac Present Pulldown + When Disable, PCH will internal pull down AC_PRESENT in deep SX and during G3 exit. + $EN_DIS +**/ + UINT8 PchPmDisableDsxAcPresentPulldown; + +/** Offset 0x09E7 - PCH Pm Disable Native Power Button + Power button native mode disable. + $EN_DIS +**/ + UINT8 PchPmDisableNativePowerButton; + +/** Offset 0x09E8 - PCH Pm ME_WAKE_STS + Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register. + $EN_DIS +**/ + UINT8 PchPmMeWakeSts; + +/** Offset 0x09E9 - PCH Pm WOL_OVR_WK_STS + Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register. + $EN_DIS +**/ + UINT8 PchPmWolOvrWkSts; + +/** Offset 0x09EA - PCH Pm Reset Power Cycle Duration + Could be customized in the unit of second. Please refer to EDS for all support settings. + 0 is default, 1 is 1 second, 2 is 2 seconds, ... +**/ + UINT8 PchPmPwrCycDur; + +/** Offset 0x09EB - PCH Pm Pcie Pll Ssc + Specifies the Pcie Pll Spread Spectrum Percentage. The default is 0xFF: AUTO - No + BIOS override. +**/ + UINT8 PchPmPciePllSsc; + +/** Offset 0x09EC - PCH Legacy IO Low Latency Enable + Set to enable low latency of legacy IO. 0: Disable, 1: Enable + $EN_DIS +**/ + UINT8 PchLegacyIoLowLatency; + +/** Offset 0x09ED - PCH Sata Pwr Opt Enable + SATA Power Optimizer on PCH side. + $EN_DIS +**/ + UINT8 SataPwrOptEnable; + +/** Offset 0x09EE - PCH Sata eSATA Speed Limit + When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed. + $EN_DIS +**/ + UINT8 EsataSpeedLimit; + +/** Offset 0x09EF - PCH Sata Speed Limit + Indicates the maximum speed the SATA controller can support 0h: PchSataSpeedDefault. +**/ + UINT8 SataSpeedLimit; + +/** Offset 0x09F0 - Enable SATA Port HotPlug + Enable SATA Port HotPlug. +**/ + UINT8 SataPortsHotPlug[8]; + +/** Offset 0x09F8 - Enable SATA Port Interlock Sw + Enable SATA Port Interlock Sw. +**/ + UINT8 SataPortsInterlockSw[8]; + +/** Offset 0x0A00 - Enable SATA Port External + Enable SATA Port External. +**/ + UINT8 SataPortsExternal[8]; + +/** Offset 0x0A08 - Enable SATA Port SpinUp + Enable the COMRESET initialization Sequence to the device. +**/ + UINT8 SataPortsSpinUp[8]; + +/** Offset 0x0A10 - Enable SATA Port Solid State Drive + 0: HDD; 1: SSD. +**/ + UINT8 SataPortsSolidStateDrive[8]; + +/** Offset 0x0A18 - Enable SATA Port Enable Dito Config + Enable DEVSLP Idle Timeout settings (DmVal, DitoVal). +**/ + UINT8 SataPortsEnableDitoConfig[8]; + +/** Offset 0x0A20 - Enable SATA Port DmVal + DITO multiplier. Default is 15. +**/ + UINT8 SataPortsDmVal[8]; + +/** Offset 0x0A28 - Enable SATA Port DmVal + DEVSLP Idle Timeout (DITO), Default is 625. +**/ + UINT16 SataPortsDitoVal[8]; + +/** Offset 0x0A38 - Enable SATA Port ZpOdd + Support zero power ODD. +**/ + UINT8 SataPortsZpOdd[8]; + +/** Offset 0x0A40 - PCH Sata Rst Raid Alternate Id + Enable RAID Alternate ID. + $EN_DIS +**/ + UINT8 SataRstRaidDeviceId; + +/** Offset 0x0A41 - PCH Sata Rst Pcie Storage Remap enable + Enable Intel RST for PCIe Storage remapping. +**/ + UINT8 SataRstPcieEnable[3]; + +/** Offset 0x0A44 - PCH Sata Rst Pcie Storage Port + Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, 0 = autodetect). +**/ + UINT8 SataRstPcieStoragePort[3]; + +/** Offset 0x0A47 - PCH Sata Rst Pcie Device Reset Delay + PCIe Storage Device Reset Delay in milliseconds. Default value is 100ms +**/ + UINT8 SataRstPcieDeviceResetDelay[3]; + +/** Offset 0x0A4A - UFS enable/disable + PCIe Storage Device Reset Delay in milliseconds. Default value is 100ms + $EN_DIS +**/ + UINT8 UfsEnable[2]; + +/** Offset 0x0A4C - IEH Mode + Integrated Error Handler Mode, 0: Bypass, 1: Enable + 0: Bypass, 1:Enable +**/ + UINT8 IehMode; + +/** Offset 0x0A4D +**/ + UINT8 UnusedUpdSpace29; + +/** Offset 0x0A4E - Thermal Throttling Custimized T0Level Value + Custimized T0Level value. +**/ + UINT16 PchT0Level; + +/** Offset 0x0A50 - Thermal Throttling Custimized T1Level Value + Custimized T1Level value. +**/ + UINT16 PchT1Level; + +/** Offset 0x0A52 - Thermal Throttling Custimized T2Level Value + Custimized T2Level value. +**/ + UINT16 PchT2Level; + +/** Offset 0x0A54 - Enable The Thermal Throttle + Enable the thermal throttle function. + $EN_DIS +**/ + UINT8 PchTTEnable; + +/** Offset 0x0A55 - PMSync State 13 + When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force + at least T2 state. + $EN_DIS +**/ + UINT8 PchTTState13Enable; + +/** Offset 0x0A56 - Thermal Throttle Lock + Thermal Throttle Lock. + $EN_DIS +**/ + UINT8 PchTTLock; + +/** Offset 0x0A57 - Thermal Throttling Suggested Setting + Thermal Throttling Suggested Setting. + $EN_DIS +**/ + UINT8 TTSuggestedSetting; + +/** Offset 0x0A58 - Enable PCH Cross Throttling + Enable/Disable PCH Cross Throttling + $EN_DIS +**/ + UINT8 TTCrossThrottling; + +/** Offset 0x0A59 - DMI Thermal Sensor Autonomous Width Enable + DMI Thermal Sensor Autonomous Width Enable. + $EN_DIS +**/ + UINT8 PchDmiTsawEn; + +/** Offset 0x0A5A - DMI Thermal Sensor Suggested Setting + DMT thermal sensor suggested representative values. + $EN_DIS +**/ + UINT8 DmiSuggestedSetting; + +/** Offset 0x0A5B - Thermal Sensor 0 Target Width + Thermal Sensor 0 Target Width. + 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 +**/ + UINT8 DmiTS0TW; + +/** Offset 0x0A5C - Thermal Sensor 1 Target Width + Thermal Sensor 1 Target Width. + 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 +**/ + UINT8 DmiTS1TW; + +/** Offset 0x0A5D - Thermal Sensor 2 Target Width + Thermal Sensor 2 Target Width. + 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 +**/ + UINT8 DmiTS2TW; + +/** Offset 0x0A5E - Thermal Sensor 3 Target Width + Thermal Sensor 3 Target Width. + 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 +**/ + UINT8 DmiTS3TW; + +/** Offset 0x0A5F - Port 0 T1 Multipler + Port 0 T1 Multipler. +**/ + UINT8 SataP0T1M; + +/** Offset 0x0A60 - Port 0 T2 Multipler + Port 0 T2 Multipler. +**/ + UINT8 SataP0T2M; + +/** Offset 0x0A61 - Port 0 T3 Multipler + Port 0 T3 Multipler. +**/ + UINT8 SataP0T3M; + +/** Offset 0x0A62 - Port 0 Tdispatch + Port 0 Tdispatch. +**/ + UINT8 SataP0TDisp; + +/** Offset 0x0A63 - Port 1 T1 Multipler + Port 1 T1 Multipler. +**/ + UINT8 SataP1T1M; + +/** Offset 0x0A64 - Port 1 T2 Multipler + Port 1 T2 Multipler. +**/ + UINT8 SataP1T2M; + +/** Offset 0x0A65 - Port 1 T3 Multipler + Port 1 T3 Multipler. +**/ + UINT8 SataP1T3M; + +/** Offset 0x0A66 - Port 1 Tdispatch + Port 1 Tdispatch. +**/ + UINT8 SataP1TDisp; + +/** Offset 0x0A67 - Port 0 Tinactive + Port 0 Tinactive. +**/ + UINT8 SataP0Tinact; + +/** Offset 0x0A68 - Port 0 Alternate Fast Init Tdispatch + Port 0 Alternate Fast Init Tdispatch. + $EN_DIS +**/ + UINT8 SataP0TDispFinit; + +/** Offset 0x0A69 - Port 1 Tinactive + Port 1 Tinactive. +**/ + UINT8 SataP1Tinact; + +/** Offset 0x0A6A - Port 1 Alternate Fast Init Tdispatch + Port 1 Alternate Fast Init Tdispatch. + $EN_DIS +**/ + UINT8 SataP1TDispFinit; + +/** Offset 0x0A6B - Sata Thermal Throttling Suggested Setting + Sata Thermal Throttling Suggested Setting. + $EN_DIS +**/ + UINT8 SataThermalSuggestedSetting; + +/** Offset 0x0A6C - Enable Memory Thermal Throttling + Enable Memory Thermal Throttling. + $EN_DIS +**/ + UINT8 PchMemoryThrottlingEnable; + +/** Offset 0x0A6D - Memory Thermal Throttling + Enable Memory Thermal Throttling. +**/ + UINT8 PchMemoryPmsyncEnable[2]; + +/** Offset 0x0A6F - Enable Memory Thermal Throttling + Enable Memory Thermal Throttling. +**/ + UINT8 PchMemoryC0TransmitEnable[2]; + +/** Offset 0x0A71 - Enable Memory Thermal Throttling + Enable Memory Thermal Throttling. +**/ + UINT8 PchMemoryPinSelection[2]; + +/** Offset 0x0A73 +**/ + UINT8 UnusedUpdSpace30; + +/** Offset 0x0A74 - Thermal Device Temperature + Decides the temperature. +**/ + UINT16 PchTemperatureHotLevel; + +/** Offset 0x0A76 - USB2 Port Over Current Pin + Describe the specific over current pin number of USB 2.0 Port N. +**/ + UINT8 Usb2OverCurrentPin[16]; + +/** Offset 0x0A86 - USB3 Port Over Current Pin + Describe the specific over current pin number of USB 3.0 Port N. +**/ + UINT8 Usb3OverCurrentPin[10]; + +/** Offset 0x0A90 - Enable xHCI LTR override + Enables override of recommended LTR values for xHCI + $EN_DIS +**/ + UINT8 PchUsbLtrOverrideEnable; + +/** Offset 0x0A91 - Touch Host Controller Mode + Switch between Intel THC protocol and Industry standard HID Over SPI protocol. 0x0:Thc, 0x1:Hid +**/ + UINT8 ThcMode[2]; + +/** Offset 0x0A93 +**/ + UINT8 UnusedUpdSpace31; + +/** Offset 0x0A94 - xHCI High Idle Time LTR override + Value used for overriding LTR recommendation for xHCI High Idle Time LTR setting +**/ + UINT32 PchUsbLtrHighIdleTimeOverride; + +/** Offset 0x0A98 - xHCI Medium Idle Time LTR override + Value used for overriding LTR recommendation for xHCI Medium Idle Time LTR setting +**/ + UINT32 PchUsbLtrMediumIdleTimeOverride; + +/** Offset 0x0A9C - xHCI Low Idle Time LTR override + Value used for overriding LTR recommendation for xHCI Low Idle Time LTR setting +**/ + UINT32 PchUsbLtrLowIdleTimeOverride; + +/** Offset 0x0AA0 - Enable 8254 Static Clock Gating + Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time + might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support + legacy OS using 8254 timer. Also enable this while S0ix is enabled. + $EN_DIS +**/ + UINT8 Enable8254ClockGating; + +/** Offset 0x0AA1 - Enable 8254 Static Clock Gating On S3 + This is only applicable when Enable8254ClockGating is disabled. FSP will do the + 8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This + avoids the SMI requirement for the programming. + $EN_DIS +**/ + UINT8 Enable8254ClockGatingOnS3; + +/** Offset 0x0AA2 - Enable TCO timer. + When FALSE, it disables PCH ACPI timer, and stops TCO timer. NOTE: This will have + huge power impact when it's enabled. If TCO timer is disabled, uCode ACPI timer + emulation must be enabled, and WDAT table must not be exposed to the OS. + $EN_DIS +**/ + UINT8 EnableTcoTimer; + +/** Offset 0x0AA3 - Hybrid Storage Detection and Configuration Mode + Enables support for Hybrid storage devices. 0: Disabled; 1: Dynamic Configuration. + Default is 0: Disabled + 0: Disabled, 1: Dynamic Configuration +**/ + UINT8 HybridStorageMode; + +/** Offset 0x0AA4 - CPU Root Port used for Hybrid Storage + Specifies the CPU root port used for Hybrid storage. +**/ + UINT8 CpuRootportUsedForHybridStorage; + +/** Offset 0x0AA5 - PCH Root Port used for Hybrid Storage when two lanes are connected to CPU + Specifies PCH Root Port used for Hybrid Storage when two lanes are connected to CPU. +**/ + UINT8 PchRootportUsedForCpuAttach; + +/** Offset 0x0AA6 - PCH GPE event handler + Enabled _L6D ACPI handler. PME GPE is shared by multiple devices So BIOS must verify + the same in the ASL handler by reading offset for PMEENABLE and PMESTATUS bit + $EN_DIS +**/ + UINT8 PchAcpiL6dPmeHandling; + +/** Offset 0x0AA7 +**/ + UINT8 UnusedUpdSpace32[1]; + +/** Offset 0x0AA8 - BgpdtHash[4] + BgpdtHash values +**/ + UINT64 BgpdtHash[4]; + +/** Offset 0x0AC8 - BiosGuardAttr + BiosGuardAttr default values +**/ + UINT32 BiosGuardAttr; + +/** Offset 0x0ACC +**/ + UINT8 UnusedUpdSpace33[4]; + +/** Offset 0x0AD0 - BiosGuardModulePtr + BiosGuardModulePtr default values +**/ + UINT64 BiosGuardModulePtr; + +/** Offset 0x0AD8 - SendEcCmd + SendEcCmd function pointer. \n + @code typedef EFI_STATUS (EFIAPI *PLATFORM_SEND_EC_COMMAND) (IN EC_COMMAND_TYPE + EcCmdType, IN UINT8 EcCmd, IN UINT8 SendData, IN OUT UINT8 *ReceiveData); @endcode +**/ + UINT64 SendEcCmd; + +/** Offset 0x0AE0 - EcCmdProvisionEav + Ephemeral Authorization Value default values. Provisions an ephemeral shared secret to the EC +**/ + UINT8 EcCmdProvisionEav; + +/** Offset 0x0AE1 - EcCmdLock + EcCmdLock default values. Locks Ephemeral Authorization Value sent previously +**/ + UINT8 EcCmdLock; + +/** Offset 0x0AE2 - Skip Ssid Programming. + When set to TRUE, silicon code will not do any SSID programming and platform code + needs to handle that by itself properly. + $EN_DIS +**/ + UINT8 SiSkipSsidProgramming; + +/** Offset 0x0AE3 +**/ + UINT8 UnusedUpdSpace34; + +/** Offset 0x0AE4 - Change Default SVID + Change the default SVID used in FSP to programming internal devices. This is only + valid when SkipSsidProgramming is FALSE. +**/ + UINT16 SiCustomizedSvid; + +/** Offset 0x0AE6 - Change Default SSID + Change the default SSID used in FSP to programming internal devices. This is only + valid when SkipSsidProgramming is FALSE. +**/ + UINT16 SiCustomizedSsid; + +/** Offset 0x0AE8 - SVID SDID table Poniter. + The address of the table of SVID SDID to customize each SVID SDID entry. This is + only valid when SkipSsidProgramming is FALSE. +**/ + UINT32 SiSsidTablePtr; + +/** Offset 0x0AEC - Number of ssid table. + SiNumberOfSsidTableEntry should match the table entries created in SiSsidTablePtr. + This is only valid when SkipSsidProgramming is FALSE. +**/ + UINT16 SiNumberOfSsidTableEntry; + +/** Offset 0x0AEE - USB2 Port Reset Message Enable + 0: Disable USB2 Port Reset Message; 1: Enable USB2 Port Reset Message; This must + be enable for USB2 Port those are paired with CPU XHCI Port +**/ + UINT8 PortResetMessageEnable[16]; + +/** Offset 0x0AFE - SATA RST Interrupt Mode + Allowes to choose which interrupts will be implemented by SATA controller in RAID mode. + 0:Msix, 1:Msi, 2:Legacy +**/ + UINT8 SataRstInterrupt; + +/** Offset 0x0AFF - ME Unconfig on RTC clear + 0: Disable ME Unconfig On Rtc Clear. 1: Enable ME Unconfig On Rtc Clear. + 2: Cmos is clear, status unkonwn. 3: Reserved + 0: Disable ME Unconfig On Rtc Clear, 1: Enable ME Unconfig On Rtc Clear, 2: Cmos + is clear, 3: Reserved +**/ + UINT8 MeUnconfigOnRtcClear; + +/** Offset 0x0B00 - Enforce Enhanced Debug Mode + Determine if ME should enter Enhanced Debug Mode. 0: disable, 1: enable + $EN_DIS +**/ + UINT8 EnforceEDebugMode; + +/** Offset 0x0B01 - Enable PS_ON. + PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power + target that will be required by the California Energy Commission (CEC). When FALSE, + PS_ON is to be disabled. + $EN_DIS +**/ + UINT8 PsOnEnable; + +/** Offset 0x0B02 - Pmc Cpu C10 Gate Pin Enable + Enable/Disable platform support for CPU_C10_GATE# pin to control gating of CPU VccIO + and VccSTG rails instead of SLP_S0# pin. + $EN_DIS +**/ + UINT8 PmcCpuC10GatePinEnable; + +/** Offset 0x0B03 - Pch Dmi Aspm Ctrl + ASPM configuration on the PCH side of the DMI/OPI Link. Default is PchPcieAspmL1 + 0:Disabled, 1:L0s, 2:L1, 3:L0sL1, 4:Auto +**/ + UINT8 PchDmiAspmCtrl; + +/** Offset 0x0B04 - PchDmiCwbEnable + Central Write Buffer feature configurable and enabled by default + $EN_DIS +**/ + UINT8 PchDmiCwbEnable; + +/** Offset 0x0B05 - OS IDLE Mode Enable + Enable/Disable OS Idle Mode + $EN_DIS +**/ + UINT8 PmcOsIdleEnable; + +/** Offset 0x0B06 - S0ix Auto-Demotion + Enable/Disable the Low Power Mode Auto-Demotion Host Control feature. + $EN_DIS +**/ + UINT8 PchS0ixAutoDemotion; + +/** Offset 0x0B07 - Latch Events C10 Exit + When this bit is set to 1, SLP_S0# entry events in SLP_S0_DEBUG_REGx registers are + captured on C10 exit (instead of C10 entry which is default) + $EN_DIS +**/ + UINT8 PchPmLatchEventsC10Exit; + +/** Offset 0x0B08 - PMC ADR enable + Enable/disable asynchronous DRAM refresh + $EN_DIS +**/ + UINT8 PmcAdrEn; + +/** Offset 0x0B09 - PMC ADR timer configuration enable + Enable/disable ADR timer configuration + $EN_DIS +**/ + UINT8 PmcAdrTimerEn; + +/** Offset 0x0B0A - PMC ADR phase 1 timer value + Enable/disable ADR timer configuration +**/ + UINT8 PmcAdrTimer1Val; + +/** Offset 0x0B0B - PMC ADR phase 1 timer multiplier value + Specify the multiplier value for phase 1 ADR timer +**/ + UINT8 PmcAdrMultiplier1Val; + +/** Offset 0x0B0C - PMC ADR host reset partition enable + Specify whether PMC should set ADR_RST_STS bit after receiving Reset_Warn_Ack DMI message + $EN_DIS +**/ + UINT8 PmcAdrHostPartitionReset; + +/** Offset 0x0B0D - PMC ADR source select override enable + Tells the FSP to update the source select with platform value + $EN_DIS +**/ + UINT8 PmcAdrSrcOverride; + +/** Offset 0x0B0E +**/ + UINT8 UnusedUpdSpace35[2]; + +/** Offset 0x0B10 - PMC ADR source selection + Specify which sources should cause ADR flow +**/ + UINT32 PmcAdrSrcSel; + +/** Offset 0x0B14 - PCIE Eq Ph3 Lane Param Cm + CPU_PCIE_EQ_LANE_PARAM. Coefficient C-1. +**/ + UINT8 CpuPcieEqPh3LaneParamCm[32]; + +/** Offset 0x0B34 - PCIE Eq Ph3 Lane Param Cp + CPU_PCIE_EQ_LANE_PARAM. Coefficient C+1. +**/ + UINT8 CpuPcieEqPh3LaneParamCp[32]; + +/** Offset 0x0B54 - Gen3 Root port preset values per lane + Used for programming Pcie Gen3 preset values per lane. Range: 0-9, 8 is default + for each lane +**/ + UINT8 CpuPcieGen3RootPortPreset[20]; + +/** Offset 0x0B68 - Pcie Gen4 Root port preset values per lane + Used for programming Pcie Gen4 preset values per lane. Range: 0-9, 8 is default + for each lane +**/ + UINT8 CpuPcieGen4RootPortPreset[20]; + +/** Offset 0x0B7C - Pcie Gen3 End port preset values per lane + Used for programming Pcie Gen3 preset values per lane. Range: 0-9, 7 is default + for each lane +**/ + UINT8 CpuPcieGen3EndPointPreset[20]; + +/** Offset 0x0B90 - Pcie Gen4 End port preset values per lane + Used for programming Pcie Gen4 preset values per lane. Range: 0-9, 7 is default + for each lane +**/ + UINT8 CpuPcieGen4EndPointPreset[20]; + +/** Offset 0x0BA4 - Pcie Gen3 End port Hint values per lane + Used for programming Pcie Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane +**/ + UINT8 CpuPcieGen3EndPointHint[20]; + +/** Offset 0x0BB8 - Pcie Gen4 End port Hint values per lane + Used for programming Pcie Gen4 Hint values per lane. Range: 0-6, 2 is default for each lane +**/ + UINT8 CpuPcieGen4EndPointHint[20]; + +/** Offset 0x0BCC - CPU PCIe Fia Programming + Load Fia configuration if enable. 0: Disable; 1: Enable(Default). + $EN_DIS +**/ + UINT8 CpuPcieFiaProgramming; + +/** Offset 0x0BCD - CPU PCIe RootPort Clock Gating + Describes whether the PCI Express Clock Gating for each root port is enabled by + platform modules. 0: Disable; 1: Enable(Default). + $EN_DIS +**/ + UINT8 CpuPcieClockGating[4]; + +/** Offset 0x0BD1 - CPU PCIe RootPort Power Gating + Describes whether the PCI Express Power Gating for each root port is enabled by + platform modules. 0: Disable; 1: Enable(Default). + $EN_DIS +**/ + UINT8 CpuPciePowerGating[4]; + +/** Offset 0x0BD5 - PCIE Compliance Test Mode + Compliance Test Mode shall be enabled when using Compliance Load Board. + $EN_DIS +**/ + UINT8 CpuPcieComplianceTestMode; + +/** Offset 0x0BD6 - PCIE Enable Peer Memory Write + This member describes whether Peer Memory Writes are enabled on the platform. + $EN_DIS +**/ + UINT8 CpuPcieEnablePeerMemoryWrite; + +/** Offset 0x0BD7 - PCIE Rp Function Swap + Allows BIOS to use root port function number swapping when root port of function + 0 is disabled. + $EN_DIS +**/ + UINT8 CpuPcieRpFunctionSwap; + +/** Offset 0x0BD8 - PCI Express Slot Selection + Select the PCIe M2 or CEMx4 slot.0: CEMx4 slot; 1: M2 slot(Default). + $EN_DIS +**/ + UINT8 CpuPcieSlotSelection; + +/** Offset 0x0BD9 +**/ + UINT8 UnusedUpdSpace36[3]; + +/** Offset 0x0BDC - CPU PCIE device override table pointer + The PCIe device table is being used to override PCIe device ASPM settings. This + is a pointer points to a 32bit address. And it's only used in PostMem phase. Please + refer to CPU_PCIE_DEVICE_OVERRIDE structure for the table. Last entry VendorId + must be 0. +**/ + UINT32 CpuPcieDeviceOverrideTablePtr; + +/** Offset 0x0BE0 - Enable PCIE RP HotPlug + Indicate whether the root port is hot plug available. +**/ + UINT8 CpuPcieRpHotPlug[4]; + +/** Offset 0x0BE4 - Enable PCIE RP Pm Sci + Indicate whether the root port power manager SCI is enabled. +**/ + UINT8 CpuPcieRpPmSci[4]; + +/** Offset 0x0BE8 - Enable PCIE RP Transmitter Half Swing + Indicate whether the Transmitter Half Swing is enabled. +**/ + UINT8 CpuPcieRpTransmitterHalfSwing[4]; + +/** Offset 0x0BEC - PCIE RP Access Control Services Extended Capability + Enable/Disable PCIE RP Access Control Services Extended Capability +**/ + UINT8 CpuPcieRpAcsEnabled[4]; + +/** Offset 0x0BF0 - PCIE RP Clock Power Management + Enable/Disable PCIE RP Clock Power Management, even if disabled, CLKREQ# signal + can still be controlled by L1 PM substates mechanism +**/ + UINT8 CpuPcieRpEnableCpm[4]; + +/** Offset 0x0BF4 - PCIE RP Advanced Error Report + Indicate whether the Advanced Error Reporting is enabled. +**/ + UINT8 CpuPcieRpAdvancedErrorReporting[4]; + +/** Offset 0x0BF8 - PCIE RP Unsupported Request Report + Indicate whether the Unsupported Request Report is enabled. +**/ + UINT8 CpuPcieRpUnsupportedRequestReport[4]; + +/** Offset 0x0BFC - PCIE RP Fatal Error Report + Indicate whether the Fatal Error Report is enabled. +**/ + UINT8 CpuPcieRpFatalErrorReport[4]; + +/** Offset 0x0C00 - PCIE RP No Fatal Error Report + Indicate whether the No Fatal Error Report is enabled. +**/ + UINT8 CpuPcieRpNoFatalErrorReport[4]; + +/** Offset 0x0C04 - PCIE RP Correctable Error Report + Indicate whether the Correctable Error Report is enabled. +**/ + UINT8 CpuPcieRpCorrectableErrorReport[4]; + +/** Offset 0x0C08 - PCIE RP System Error On Fatal Error + Indicate whether the System Error on Fatal Error is enabled. +**/ + UINT8 CpuPcieRpSystemErrorOnFatalError[4]; + +/** Offset 0x0C0C - PCIE RP System Error On Non Fatal Error + Indicate whether the System Error on Non Fatal Error is enabled. +**/ + UINT8 CpuPcieRpSystemErrorOnNonFatalError[4]; + +/** Offset 0x0C10 - PCIE RP System Error On Correctable Error + Indicate whether the System Error on Correctable Error is enabled. +**/ + UINT8 CpuPcieRpSystemErrorOnCorrectableError[4]; + +/** Offset 0x0C14 - PCIE RP Max Payload + Max Payload Size supported, Default 128B, see enum CPU_PCIE_MAX_PAYLOAD. +**/ + UINT8 CpuPcieRpMaxPayload[4]; + +/** Offset 0x0C18 - DPC for PCIE RP Mask + Enable/disable Downstream Port Containment for PCIE Root Ports. 0: disable, 1: enable. + One bit for each port, bit0 for port1, bit1 for port2, and so on. +**/ + UINT8 CpuPcieRpDpcEnabled[4]; + +/** Offset 0x0C1C - DPC Extensions PCIE RP Mask + Enable/disable DPC Extensions for PCIE Root Ports. 0: disable, 1: enable. One bit + for each port, bit0 for port1, bit1 for port2, and so on. +**/ + UINT8 CpuPcieRpDpcExtensionsEnabled[4]; + +/** Offset 0x0C20 - CPU PCIe root port connection type + 0: built-in device, 1:slot +**/ + UINT8 CpuPcieRpSlotImplemented[4]; + +/** Offset 0x0C24 - PCIE RP Gen3 Equalization Phase Method + PCIe Gen3 Eq Ph3 Method (see CPU_PCIE_EQ_METHOD). 0: DEPRECATED, hardware equalization; + 1: hardware equalization; 4: Fixed Coeficients. +**/ + UINT8 CpuPcieRpGen3EqPh3Method[4]; + +/** Offset 0x0C28 - PCIE RP Gen4 Equalization Phase Method + PCIe Gen4 Eq Ph3 Method (see CPU_PCIE_EQ_METHOD). 0: DEPRECATED, hardware equalization; + 1: hardware equalization; 4: Fixed Coeficients. +**/ + UINT8 CpuPcieRpGen4EqPh3Method[4]; + +/** Offset 0x0C2C - PCIE RP Physical Slot Number + Indicates the slot number for the root port. Default is the value as root port index. +**/ + UINT8 CpuPcieRpPhysicalSlotNumber[4]; + +/** Offset 0x0C30 - PCIE RP Aspm + The ASPM configuration of the root port (see: CPU_PCIE_ASPM_CONTROL).0: Disable; + 1: CpuPcieAspmL0s; 2: CpuPcieAspmL1; 3:CpuPcieAspmL0sL1(Default) +**/ + UINT8 CpuPcieRpAspm[4]; + +/** Offset 0x0C34 - PCIE RP L1 Substates + The L1 Substates configuration of the root port (see: CPU_PCIE_L1SUBSTATES_CONTROL). + Default is CpuPcieL1SubstatesL1_1_2. +**/ + UINT8 CpuPcieRpL1Substates[4]; + +/** Offset 0x0C38 - PCIE RP Ltr Enable + Latency Tolerance Reporting Mechanism. +**/ + UINT8 CpuPcieRpLtrEnable[4]; + +/** Offset 0x0C3C - PCIE RP Ltr Config Lock + 0: Disable; 1: Enable. +**/ + UINT8 CpuPcieRpLtrConfigLock[4]; + +/** Offset 0x0C40 - PTM for PCIE RP Mask + Enable/disable Precision Time Measurement for PCIE Root Ports. 0: disable, 1: enable. + One bit for each port, bit0 for port1, bit1 for port2, and so on. +**/ + UINT8 CpuPcieRpPtmEnabled[4]; + +/** Offset 0x0C44 - PCIE RP Detect Timeout Ms + The number of milliseconds within 0~65535 in reference code will wait for link to + exit Detect state for enabled ports before assuming there is no device and potentially + disabling the port. +**/ + UINT16 CpuPcieRpDetectTimeoutMs[4]; + +/** Offset 0x0C4C - Multi-VC for PCIE RP Mask + Enable/disable Multiple Virtual Channel for PCIE Root Ports. 0: disable, 1: enable. + One bit for each port, bit0 for port1, bit1 for port2, and so on. +**/ + UINT8 CpuPcieRpMultiVcEnabled[4]; + +/** Offset 0x0C50 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3 + Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3, Each + value in array can be between 0-1. One byte for each port. +**/ + UINT8 Usb3HsioTxRate3UniqTranEnable[10]; + +/** Offset 0x0C5A - USB 3.0 TX Output Unique Transition Bit Scale for rate 3 + USB 3.0 TX Output Unique Transition Bit Scale for rate 3, HSIO_TX_DWORD9[6:0], Default + = 4Ch. One byte for each port. +**/ + UINT8 Usb3HsioTxRate3UniqTran[10]; + +/** Offset 0x0C64 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2 + Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2, Each + value in array can be between 0-1. One byte for each port. +**/ + UINT8 Usb3HsioTxRate2UniqTranEnable[10]; + +/** Offset 0x0C6E - USB 3.0 TX Output Unique Transition Bit Scale for rate 2 + USB 3.0 TX Output Unique Transition Bit Scale for rate 2, HSIO_TX_DWORD9[14:8], + Default = 4Ch. One byte for each port. +**/ + UINT8 Usb3HsioTxRate2UniqTran[10]; + +/** Offset 0x0C78 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1 + Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1, Each + value in array can be between 0-1. One byte for each port. +**/ + UINT8 Usb3HsioTxRate1UniqTranEnable[10]; + +/** Offset 0x0C82 - USB 3.0 TX Output Unique Transition Bit Scale for rate 1 + USB 3.0 TX Output Unique Transition Bit Scale for rate 1, HSIO_TX_DWORD9[22:16], + Default = 4Ch. One byte for each port. +**/ + UINT8 Usb3HsioTxRate1UniqTran[10]; + +/** Offset 0x0C8C - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0 + Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0, Each + value in array can be between 0-1. One byte for each port. +**/ + UINT8 Usb3HsioTxRate0UniqTranEnable[10]; + +/** Offset 0x0C96 - USB 3.0 TX Output Unique Transition Bit Scale for rate 0 + USB 3.0 TX Output Unique Transition Bit Scale for rate 0, HSIO_TX_DWORD9[30:24], + Default = 4Ch. One byte for each port. +**/ + UINT8 Usb3HsioTxRate0UniqTran[10]; + +/** Offset 0x0CA0 - Skip PAM regsiter lock + Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): + PAM registers will be locked by RC + $EN_DIS +**/ + UINT8 SkipPamLock; + +/** Offset 0x0CA1 - EDRAM Test Mode + Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): + PAM registers will be locked by RC + 0: EDRAM SW disable, 1: EDRAM SW Enable, 2: EDRAM HW mode +**/ + UINT8 EdramTestMode; + +/** Offset 0x0CA2 - Enable/Disable IGFX RenderStandby + Enable(Default): Enable IGFX RenderStandby, Disable: Disable IGFX RenderStandby + $EN_DIS +**/ + UINT8 RenderStandby; + +/** Offset 0x0CA3 - Enable/Disable IGFX PmSupport + Enable(Default): Enable IGFX PmSupport, Disable: Disable IGFX PmSupport + $EN_DIS +**/ + UINT8 PmSupport; + +/** Offset 0x0CA4 - Enable/Disable CdynmaxClamp + Enable: Enable CdynmaxClamp, Disable(Default): Disable CdynmaxClamp + $EN_DIS +**/ + UINT8 CdynmaxClampEnable; + +/** Offset 0x0CA5 - GT Frequency Limit + 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, + 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD: + 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz, + 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz, + 0x18: 1200 Mhz + 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, + 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD: + 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz, + 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz, + 0x18: 1200 Mhz +**/ + UINT8 GtFreqMax; + +/** Offset 0x0CA6 - Disable Turbo GT + 0=Disable: GT frequency is not limited, 1=Enable: Disables Turbo GT frequency + $EN_DIS +**/ + UINT8 DisableTurboGt; + +/** Offset 0x0CA7 - Enable/Disable CdClock Init + Enable: Skip Full CD clock initializaton, Disable(Default): Initialize the full + CD clock if not initialized by Gfx PEIM + $EN_DIS +**/ + UINT8 SkipCdClockInit; + +/** Offset 0x0CA8 - Enable RC1p frequency request to PMA (provided all other conditions are met) + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 RC1pFreqEnable; + +/** Offset 0x0CA9 - Enable TSN Multi-VC + Enable/disable Multi Virtual Channels(VC) in TSN. + $EN_DIS +**/ + UINT8 PchTsnMultiVcEnable; + +/** Offset 0x0CAA +**/ + UINT8 UnusedUpdSpace37[2]; + +/** Offset 0x0CAC - LogoPixelHeight Address + Address of LogoPixelHeight +**/ + UINT32 LogoPixelHeight; + +/** Offset 0x0CB0 - LogoPixelWidth Address + Address of LogoPixelWidth +**/ + UINT32 LogoPixelWidth; + +/** Offset 0x0CB4 - ITbt Usb4CmMode value + ITbt Usb4CmMode value. 0:Firmware CM, 1:Software CM +**/ + UINT8 Usb4CmMode; + +/** Offset 0x0CB5 - PCIE Resizable BAR Support + Enable/Disable PCIE Resizable BAR Support.0: Disable; 1: Enable; 2: Auto(Default). + $EN_DIS +**/ + UINT8 CpuPcieResizableBarSupport; + +/** Offset 0x0CB6 - SaPostMemTestRsvd + Reserved for SA Post-Mem Test + $EN_DIS +**/ + UINT8 SaPostMemTestRsvd[3]; + +/** Offset 0x0CB9 - RSR feature + Enable or Disable RSR feature; 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 EnableRsr; + +/** Offset 0x0CBA - ReservedCpuPostMem1 + Reserved for CPU Post-Mem 1 + $EN_DIS +**/ + UINT8 ReservedCpuPostMem1[4]; + +/** Offset 0x0CBE - Enable or Disable HWP + Enable or Disable HWP(Hardware P states) Support. 0: Disable; 1: Enable; + 2-3:Reserved + $EN_DIS +**/ + UINT8 Hwp; + +/** Offset 0x0CBF - Hardware Duty Cycle Control + Hardware Duty Cycle Control configuration. 0: Disabled; 1: Enabled 2-3:Reserved + $EN_DIS +**/ + UINT8 HdcControl; + +/** Offset 0x0CC0 - Package Long duration turbo mode time + Package Long duration turbo mode time window in seconds. Valid values(Unit in seconds) + 0 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128 +**/ + UINT8 PowerLimit1Time; + +/** Offset 0x0CC1 - Short Duration Turbo Mode + Enable or Disable short duration Turbo Mode. 0 : Disable; 1: Enable + $EN_DIS +**/ + UINT8 PowerLimit2; + +/** Offset 0x0CC2 - Turbo settings Lock + Lock all Turbo settings Enable/Disable; 0: Disable , 1: Enable + $EN_DIS +**/ + UINT8 TurboPowerLimitLock; + +/** Offset 0x0CC3 - Package PL3 time window + Package PL3 time window range for this policy from 0 to 64ms +**/ + UINT8 PowerLimit3Time; + +/** Offset 0x0CC4 - Package PL3 Duty Cycle + Package PL3 Duty Cycle; Valid Range is 0 to 100 +**/ + UINT8 PowerLimit3DutyCycle; + +/** Offset 0x0CC5 - Package PL3 Lock + Package PL3 Lock Enable/Disable; 0: Disable ; 1:Enable + $EN_DIS +**/ + UINT8 PowerLimit3Lock; + +/** Offset 0x0CC6 - Package PL4 Lock + Package PL4 Lock Enable/Disable; 0: Disable ; 1:Enable + $EN_DIS +**/ + UINT8 PowerLimit4Lock; + +/** Offset 0x0CC7 - TCC Activation Offset + TCC Activation Offset. Offset from factory set TCC activation temperature at which + the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation + Temperature, in volts.For SKL Y SKU, the recommended default for this policy is + 10, For all other SKUs the recommended default are 0 +**/ + UINT8 TccActivationOffset; + +/** Offset 0x0CC8 - Tcc Offset Clamp Enable/Disable + Tcc Offset Clamp for Runtime Average Temperature Limit (RATL) allows CPU to throttle + below P1.For SKL Y SKU, the recommended default for this policy is 1: Enabled, + For all other SKUs the recommended default are 0: Disabled. + $EN_DIS +**/ + UINT8 TccOffsetClamp; + +/** Offset 0x0CC9 - Tcc Offset Lock + Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature + target; 0: Disabled; 1: Enabled. + $EN_DIS +**/ + UINT8 TccOffsetLock; + +/** Offset 0x0CCA - Custom Ratio State Entries + The number of custom ratio state entries, ranges from 0 to 40 for a valid custom + ratio table.Sets the number of custom P-states. At least 2 states must be present +**/ + UINT8 NumberOfEntries; + +/** Offset 0x0CCB - Custom Short term Power Limit time window + Short term Power Limit time window value for custom CTDP level 1. Valid Range 0 to 128 +**/ + UINT8 Custom1PowerLimit1Time; + +/** Offset 0x0CCC - Custom Turbo Activation Ratio + Turbo Activation Ratio for custom cTDP level 1. Valid Range 0 to 255 +**/ + UINT8 Custom1TurboActivationRatio; + +/** Offset 0x0CCD - Custom Config Tdp Control + Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2 +**/ + UINT8 Custom1ConfigTdpControl; + +/** Offset 0x0CCE - Custom Short term Power Limit time window + Short term Power Limit time window value for custom CTDP level 2. Valid Range 0 to 128 +**/ + UINT8 Custom2PowerLimit1Time; + +/** Offset 0x0CCF - Custom Turbo Activation Ratio + Turbo Activation Ratio for custom cTDP level 2. Valid Range 0 to 255 +**/ + UINT8 Custom2TurboActivationRatio; + +/** Offset 0x0CD0 - Custom Config Tdp Control + Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2 +**/ + UINT8 Custom2ConfigTdpControl; + +/** Offset 0x0CD1 - Custom Short term Power Limit time window + Short term Power Limit time window value for custom CTDP level 3. Valid Range 0 to 128 +**/ + UINT8 Custom3PowerLimit1Time; + +/** Offset 0x0CD2 - Custom Turbo Activation Ratio + Turbo Activation Ratio for custom cTDP level 3. Valid Range 0 to 255 +**/ + UINT8 Custom3TurboActivationRatio; + +/** Offset 0x0CD3 - Custom Config Tdp Control + Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2 +**/ + UINT8 Custom3ConfigTdpControl; + +/** Offset 0x0CD4 - ConfigTdp mode settings Lock + Lock the ConfigTdp mode settings from runtime changes; 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 ConfigTdpLock; + +/** Offset 0x0CD5 - Load Configurable TDP SSDT + Configure whether to load Configurable TDP SSDT; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 ConfigTdpBios; + +/** Offset 0x0CD6 - PL1 Enable value + PL1 Enable value to limit average platform power. 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 PsysPowerLimit1; + +/** Offset 0x0CD7 - PL1 timewindow + PL1 timewindow in seconds.Valid values(Unit in seconds) 0 to 8 , 10 , 12 ,14 , 16 + , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128 +**/ + UINT8 PsysPowerLimit1Time; + +/** Offset 0x0CD8 - PL2 Enable Value + PL2 Enable activates the PL2 value to limit average platform power.0: Disable; + 1: Enable. + $EN_DIS +**/ + UINT8 PsysPowerLimit2; + +/** Offset 0x0CD9 - Enable or Disable MLC Streamer Prefetcher + Enable or Disable MLC Streamer Prefetcher; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 MlcStreamerPrefetcher; + +/** Offset 0x0CDA - Enable or Disable MLC Spatial Prefetcher + Enable or Disable MLC Spatial Prefetcher; 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 MlcSpatialPrefetcher; + +/** Offset 0x0CDB - Enable or Disable Monitor /MWAIT instructions + Enable or Disable Monitor /MWAIT instructions; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 MonitorMwaitEnable; + +/** Offset 0x0CDC - Enable or Disable initialization of machine check registers + Enable or Disable initialization of machine check registers; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 MachineCheckEnable; + +/** Offset 0x0CDD - AP Idle Manner of waiting for SIPI + AP Idle Manner of waiting for SIPI; 1: HALT loop; 2: MWAIT loop; 3: RUN loop. + 1: HALT loop, 2: MWAIT loop, 3: RUN loop +**/ + UINT8 ApIdleManner; + +/** Offset 0x0CDE - Control on Processor Trace output scheme + Control on Processor Trace output scheme; 0: Single Range Output; 1: ToPA Output. + 0: Single Range Output, 1: ToPA Output +**/ + UINT8 ProcessorTraceOutputScheme; + +/** Offset 0x0CDF - Enable or Disable Processor Trace feature + Enable or Disable Processor Trace feature; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 ProcessorTraceEnable; + +/** Offset 0x0CE0 - Enable or Disable Intel SpeedStep Technology + Enable or Disable Intel SpeedStep Technology. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 Eist; + +/** Offset 0x0CE1 - Enable or Disable Energy Efficient P-state + Enable or Disable Energy Efficient P-state will be applied in Turbo mode. Disable; + 1: Enable + $EN_DIS +**/ + UINT8 EnergyEfficientPState; + +/** Offset 0x0CE2 - Enable or Disable Energy Efficient Turbo + Enable or Disable Energy Efficient Turbo, will be applied in Turbo mode. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 EnergyEfficientTurbo; + +/** Offset 0x0CE3 - Enable or Disable T states + Enable or Disable T states; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 TStates; + +/** Offset 0x0CE4 - Enable or Disable Bi-Directional PROCHOT# + Enable or Disable Bi-Directional PROCHOT#; 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 BiProcHot; + +/** Offset 0x0CE5 - Enable or Disable PROCHOT# signal being driven externally + Enable or Disable PROCHOT# signal being driven externally; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 DisableProcHotOut; + +/** Offset 0x0CE6 - Enable or Disable PROCHOT# Response + Enable or Disable PROCHOT# Response; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 ProcHotResponse; + +/** Offset 0x0CE7 - Enable or Disable VR Thermal Alert + Enable or Disable VR Thermal Alert; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 DisableVrThermalAlert; + +/** Offset 0x0CE8 - Enable or Disable Thermal Reporting + Enable or Disable Thermal Reporting through ACPI tables; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 EnableAllThermalFunctions; + +/** Offset 0x0CE9 - Enable or Disable Thermal Monitor + Enable or Disable Thermal Monitor; 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 ThermalMonitor; + +/** Offset 0x0CEA - Enable or Disable CPU power states (C-states) + Enable or Disable CPU power states (C-states). 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 Cx; + +/** Offset 0x0CEB - Configure C-State Configuration Lock + Configure C-State Configuration Lock; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 PmgCstCfgCtrlLock; + +/** Offset 0x0CEC - Enable or Disable Enhanced C-states + Enable or Disable Enhanced C-states. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 C1e; + +/** Offset 0x0CED - Enable or Disable Package Cstate Demotion + Enable or Disable Package Cstate Demotion. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 PkgCStateDemotion; + +/** Offset 0x0CEE - Enable or Disable Package Cstate UnDemotion + Enable or Disable Package Cstate UnDemotion. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 PkgCStateUnDemotion; + +/** Offset 0x0CEF - Enable or Disable CState-Pre wake + Enable or Disable CState-Pre wake. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 CStatePreWake; + +/** Offset 0x0CF0 - Enable or Disable TimedMwait Support. + Enable or Disable TimedMwait Support. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 TimedMwait; + +/** Offset 0x0CF1 - Enable or Disable IO to MWAIT redirection + Enable or Disable IO to MWAIT redirection; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 CstCfgCtrIoMwaitRedirection; + +/** Offset 0x0CF2 - Set the Max Pkg Cstate + Set the Max Pkg Cstate. Default set to Auto which limits the Max Pkg Cstate to deep + C-state. Valid values 0 - C0/C1 , 1 - C2 , 2 - C3 , 3 - C6 , 4 - C7 , 5 - C7S , + 6 - C8 , 7 - C9 , 8 - C10 , 254 - CPU Default , 255 - Auto +**/ + UINT8 PkgCStateLimit; + +/** Offset 0x0CF3 - TimeUnit for C-State Latency Control0 + TimeUnit for C-State Latency Control0; Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns + , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns +**/ + UINT8 CstateLatencyControl0TimeUnit; + +/** Offset 0x0CF4 - TimeUnit for C-State Latency Control1 + TimeUnit for C-State Latency Control1;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns + , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns +**/ + UINT8 CstateLatencyControl1TimeUnit; + +/** Offset 0x0CF5 - TimeUnit for C-State Latency Control2 + TimeUnit for C-State Latency Control2;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns + , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns +**/ + UINT8 CstateLatencyControl2TimeUnit; + +/** Offset 0x0CF6 - TimeUnit for C-State Latency Control3 + TimeUnit for C-State Latency Control3;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns + , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns +**/ + UINT8 CstateLatencyControl3TimeUnit; + +/** Offset 0x0CF7 - TimeUnit for C-State Latency Control4 + Time - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns +**/ + UINT8 CstateLatencyControl4TimeUnit; + +/** Offset 0x0CF8 - TimeUnit for C-State Latency Control5 + TimeUnit for C-State Latency Control5;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns + , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns +**/ + UINT8 CstateLatencyControl5TimeUnit; + +/** Offset 0x0CF9 - Interrupt Redirection Mode Select + Interrupt Redirection Mode Select.0: Fixed priority; 1: Round robin;2: Hash vector;7: + No change. +**/ + UINT8 PpmIrmSetting; + +/** Offset 0x0CFA - Lock prochot configuration + Lock prochot configuration Enable/Disable; 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 ProcHotLock; + +/** Offset 0x0CFB - Configuration for boot TDP selection + Deprecated. Move to premem. +**/ + UINT8 ConfigTdpLevel; + +/** Offset 0x0CFC - Max P-State Ratio + Max P-State Ratio, Valid Range 0 to 0x7F +**/ + UINT8 MaxRatio; + +/** Offset 0x0CFD - P-state ratios for custom P-state table + P-state ratios for custom P-state table. NumberOfEntries has valid range between + 0 to 40. For no. of P-States supported(NumberOfEntries) , StateRatio[NumberOfEntries] + are configurable. Valid Range of each entry is 0 to 0x7F +**/ + UINT8 StateRatio[40]; + +/** Offset 0x0D25 - P-state ratios for max 16 version of custom P-state table + P-state ratios for max 16 version of custom P-state table. This table is used for + OS versions limited to a max of 16 P-States. If the first entry of this table is + 0, or if Number of Entries is 16 or less, then this table will be ignored, and + up to the top 16 values of the StateRatio table will be used instead. Valid Range + of each entry is 0 to 0x7F +**/ + UINT8 StateRatioMax16[16]; + +/** Offset 0x0D35 +**/ + UINT8 UnusedUpdSpace38; + +/** Offset 0x0D36 - Platform Power Pmax + PCODE MMIO Mailbox: Platform Power Pmax. 0 - Auto Specified in 1/8 Watt increments. + Range 0-1024 Watts. Value of 800 = 100W +**/ + UINT16 PsysPmax; + +/** Offset 0x0D38 - Interrupt Response Time Limit of C-State LatencyContol1 + Interrupt Response Time Limit of C-State LatencyContol1.Range of value 0 to 0x3FF. + 0 is Auto. +**/ + UINT16 CstateLatencyControl1Irtl; + +/** Offset 0x0D3A - Interrupt Response Time Limit of C-State LatencyContol2 + Interrupt Response Time Limit of C-State LatencyContol2.Range of value 0 to 0x3FF. + 0 is Auto. +**/ + UINT16 CstateLatencyControl2Irtl; + +/** Offset 0x0D3C - Interrupt Response Time Limit of C-State LatencyContol3 + Interrupt Response Time Limit of C-State LatencyContol3.Range of value 0 to 0x3FF. + 0 is Auto. +**/ + UINT16 CstateLatencyControl3Irtl; + +/** Offset 0x0D3E - Interrupt Response Time Limit of C-State LatencyContol4 + Interrupt Response Time Limit of C-State LatencyContol4.Range of value 0 to 0x3FF. + 0 is Auto. +**/ + UINT16 CstateLatencyControl4Irtl; + +/** Offset 0x0D40 - Interrupt Response Time Limit of C-State LatencyContol5 + Interrupt Response Time Limit of C-State LatencyContol5.Range of value 0 to 0x3FF. + 0 is Auto. +**/ + UINT16 CstateLatencyControl5Irtl; + +/** Offset 0x0D42 +**/ + UINT8 UnusedUpdSpace39[2]; + +/** Offset 0x0D44 - Package Long duration turbo mode power limit + Package Long duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. + Valid Range 0 to 4095875 in Step size of 125 +**/ + UINT32 PowerLimit1; + +/** Offset 0x0D48 - Package Short duration turbo mode power limit + Package Short duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid + Range 0 to 4095875 in Step size of 125 +**/ + UINT32 PowerLimit2Power; + +/** Offset 0x0D4C - Package PL3 power limit + Package PL3 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid + Range 0 to 4095875 in Step size of 125 +**/ + UINT32 PowerLimit3; + +/** Offset 0x0D50 - Package PL4 power limit + Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid + Range 0 to 4095875 in Step size of 125 +**/ + UINT32 PowerLimit4; + +/** Offset 0x0D54 - Tcc Offset Time Window for RATL + Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid + Range 0 to 4095875 in Step size of 125 +**/ + UINT32 TccOffsetTimeWindowForRatl; + +/** Offset 0x0D58 - Short term Power Limit value for custom cTDP level 1 + Short term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid + Range 0 to 4095875 in Step size of 125 +**/ + UINT32 Custom1PowerLimit1; + +/** Offset 0x0D5C - Long term Power Limit value for custom cTDP level 1 + Long term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid + Range 0 to 4095875 in Step size of 125 +**/ + UINT32 Custom1PowerLimit2; + +/** Offset 0x0D60 - Short term Power Limit value for custom cTDP level 2 + Short term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid + Range 0 to 4095875 in Step size of 125 +**/ + UINT32 Custom2PowerLimit1; + +/** Offset 0x0D64 - Long term Power Limit value for custom cTDP level 2 + Long term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid + Range 0 to 4095875 in Step size of 125 +**/ + UINT32 Custom2PowerLimit2; + +/** Offset 0x0D68 - Short term Power Limit value for custom cTDP level 3 + Short term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid + Range 0 to 4095875 in Step size of 125 +**/ + UINT32 Custom3PowerLimit1; + +/** Offset 0x0D6C - Long term Power Limit value for custom cTDP level 3 + Long term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid + Range 0 to 4095875 in Step size of 125 +**/ + UINT32 Custom3PowerLimit2; + +/** Offset 0x0D70 - Platform PL1 power + Platform PL1 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range + 0 to 4095875 in Step size of 125 +**/ + UINT32 PsysPowerLimit1Power; + +/** Offset 0x0D74 - Platform PL2 power + Platform PL2 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range + 0 to 4095875 in Step size of 125 +**/ + UINT32 PsysPowerLimit2Power; + +/** Offset 0x0D78 - Race To Halt + Enable/Disable Race To Halt feature. RTH will dynamically increase CPU frequency + in order to enter pkg C-State faster to reduce overall power. (RTH is controlled + through MSR 1FC bit 20)Disable; 1: Enable + $EN_DIS +**/ + UINT8 RaceToHalt; + +/** Offset 0x0D79 - Set Three Strike Counter Disable + False (default): Three Strike counter will be incremented and True: Prevents Three + Strike counter from incrementing; 0: False; 1: True. + 0: False, 1: True +**/ + UINT8 ThreeStrikeCounterDisable; + +/** Offset 0x0D7A - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT + Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 HwpInterruptControl; + +/** Offset 0x0D7B - ReservedCpuPostMem2 + Reserved for CPU Post-Mem 2 + $EN_DIS +**/ + UINT8 ReservedCpuPostMem2[4]; + +/** Offset 0x0D7F - Intel Turbo Boost Max Technology 3.0 + Intel Turbo Boost Max Technology 3.0. 0: Disabled; 1: Enabled + $EN_DIS +**/ + UINT8 EnableItbm; + +/** Offset 0x0D80 - Enable or Disable C1 Cstate Demotion + Enable or Disable C1 Cstate Demotion. Disable; 1: Enable + $EN_DIS +**/ + UINT8 C1StateAutoDemotion; + +/** Offset 0x0D81 - Enable or Disable C1 Cstate UnDemotion + Enable or Disable C1 Cstate UnDemotion. Disable; 1: Enable + $EN_DIS +**/ + UINT8 C1StateUnDemotion; + +/** Offset 0x0D82 - Minimum Ring ratio limit override + Minimum Ring ratio limit override. 0: Hardware defaults. Range: 0 - Max turbo + ratio limit +**/ + UINT8 MinRingRatioLimit; + +/** Offset 0x0D83 - Maximum Ring ratio limit override + Maximum Ring ratio limit override. 0: Hardware defaults. Range: 0 - Max turbo + ratio limit +**/ + UINT8 MaxRingRatioLimit; + +/** Offset 0x0D84 - Enable or Disable Per Core P State OS control + Enable or Disable Per Core P State OS control. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 EnablePerCorePState; + +/** Offset 0x0D85 - Enable or Disable HwP Autonomous Per Core P State OS control + Enable or Disable HwP Autonomous Per Core P State OS control. 0: Disable; 1: + Enable + $EN_DIS +**/ + UINT8 EnableHwpAutoPerCorePstate; + +/** Offset 0x0D86 - Enable or Disable HwP Autonomous EPP Grouping + Enable or Disable HwP Autonomous EPP Grouping. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 EnableHwpAutoEppGrouping; + +/** Offset 0x0D87 - Enable or Disable EPB override over PECI + Enable or Disable EPB override over PECI. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 EnableEpbPeciOverride; + +/** Offset 0x0D88 - Enable or Disable Fast MSR for IA32_HWP_REQUEST + Enable or Disable Fast MSR for IA32_HWP_REQUEST. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 EnableFastMsrHwpReq; + +/** Offset 0x0D89 - Enable Configurable TDP + Applies TDP initialization settings based on non-cTDP or cTDP.; 0: Applies to non-cTDP; + 1: Applies to cTDP + $EN_DIS +**/ + UINT8 ApplyConfigTdp; + +/** Offset 0x0D8A - Misc Power Management MSR Lock + Lock Misc Power Management MSR. Enable/Disable; 0: Disable , 1: Enable + $EN_DIS +**/ + UINT8 HwpLock; + +/** Offset 0x0D8B - Dual Tau Boost + Enable, Disable Dual Tau Boost feature. This is only applicable for Desktop; 0: + Disable; 1: Enable + $EN_DIS +**/ + UINT8 DualTauBoost; + +/** Offset 0x0D8C - ReservedCpuPostMemTest + Reserved for CPU Post-Mem Test + $EN_DIS +**/ + UINT8 ReservedCpuPostMemTest[16]; + +/** Offset 0x0D9C +**/ + UINT8 SecurityPostMemRsvd[16]; + +/** Offset 0x0DAC - End of Post message + Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1): + EOP send in PEI, Send in DXE(0x2)(Default): EOP send in DXE + 0:Disable, 1:Send in PEI, 2:Send in DXE, 3:Reserved +**/ + UINT8 EndOfPostMessage; + +/** Offset 0x0DAD - D0I3 Setting for HECI Disable + Test, 0: disable, 1: enable, Setting this option disables setting D0I3 bit for all + HECI devices + $EN_DIS +**/ + UINT8 DisableD0I3SettingForHeci; + +/** Offset 0x0DAE - Mctp Broadcast Cycle + Test, Determine if MCTP Broadcast is enabled 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 MctpBroadcastCycle; + +/** Offset 0x0DAF - Enable LOCKDOWN SMI + Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. + $EN_DIS +**/ + UINT8 PchLockDownGlobalSmi; + +/** Offset 0x0DB0 - Enable LOCKDOWN BIOS Interface + Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register. + $EN_DIS +**/ + UINT8 PchLockDownBiosInterface; + +/** Offset 0x0DB1 - Unlock all GPIO pads + Force all GPIO pads to be unlocked for debug purpose. + $EN_DIS +**/ + UINT8 PchUnlockGpioPads; + +/** Offset 0x0DB2 - PCH Unlock SideBand access + The SideBand PortID mask for certain end point (e.g. PSFx) will be locked before + 3rd party code execution. 0: Lock SideBand access; 1: Unlock SideBand access. + $EN_DIS +**/ + UINT8 PchSbAccessUnlock; + +/** Offset 0x0DB3 +**/ + UINT8 UnusedUpdSpace40[1]; + +/** Offset 0x0DB4 - PCIE RP Ltr Max Snoop Latency + Latency Tolerance Reporting, Max Snoop Latency. +**/ + UINT16 PcieRpLtrMaxSnoopLatency[28]; + +/** Offset 0x0DEC - PCIE RP Ltr Max No Snoop Latency + Latency Tolerance Reporting, Max Non-Snoop Latency. +**/ + UINT16 PcieRpLtrMaxNoSnoopLatency[28]; + +/** Offset 0x0E24 - PCIE RP Snoop Latency Override Mode + Latency Tolerance Reporting, Snoop Latency Override Mode. +**/ + UINT8 PcieRpSnoopLatencyOverrideMode[28]; + +/** Offset 0x0E40 - PCIE RP Snoop Latency Override Multiplier + Latency Tolerance Reporting, Snoop Latency Override Multiplier. +**/ + UINT8 PcieRpSnoopLatencyOverrideMultiplier[28]; + +/** Offset 0x0E5C - PCIE RP Snoop Latency Override Value + Latency Tolerance Reporting, Snoop Latency Override Value. +**/ + UINT16 PcieRpSnoopLatencyOverrideValue[28]; + +/** Offset 0x0E94 - PCIE RP Non Snoop Latency Override Mode + Latency Tolerance Reporting, Non-Snoop Latency Override Mode. +**/ + UINT8 PcieRpNonSnoopLatencyOverrideMode[28]; + +/** Offset 0x0EB0 - PCIE RP Non Snoop Latency Override Multiplier + Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier. +**/ + UINT8 PcieRpNonSnoopLatencyOverrideMultiplier[28]; + +/** Offset 0x0ECC - PCIE RP Non Snoop Latency Override Value + Latency Tolerance Reporting, Non-Snoop Latency Override Value. +**/ + UINT16 PcieRpNonSnoopLatencyOverrideValue[28]; + +/** Offset 0x0F04 - PCIE RP Slot Power Limit Scale + Specifies scale used for slot power limit value. Leave as 0 to set to default. +**/ + UINT8 PcieRpSlotPowerLimitScale[28]; + +/** Offset 0x0F20 - PCIE RP Slot Power Limit Value + Specifies upper limit on power supplie by slot. Leave as 0 to set to default. +**/ + UINT16 PcieRpSlotPowerLimitValue[28]; + +/** Offset 0x0F58 - PCIE RP Enable Port8xh Decode + This member describes whether PCIE root port Port 8xh Decode is enabled. 0: Disable; + 1: Enable. + $EN_DIS +**/ + UINT8 PcieEnablePort8xhDecode; + +/** Offset 0x0F59 - PCIE Port8xh Decode Port Index + The Index of PCIe Port that is selected for Port8xh Decode (0 Based). +**/ + UINT8 PchPciePort8xhDecodePortIndex; + +/** Offset 0x0F5A - PCH Energy Reporting + Disable/Enable PCH to CPU energy report feature. + $EN_DIS +**/ + UINT8 PchPmDisableEnergyReport; + +/** Offset 0x0F5B - PCH Sata Test Mode + Allow entrance to the PCH SATA test modes. + $EN_DIS +**/ + UINT8 SataTestMode; + +/** Offset 0x0F5C - PCH USB OverCurrent mapping lock enable + If this policy option is enabled then BIOS will program OCCFDONE bit in xHCI meaning + that OC mapping data will be consumed by xHCI and OC mapping registers will be locked. + $EN_DIS +**/ + UINT8 PchXhciOcLock; + +/** Offset 0x0F5D - Low Power Mode Enable/Disable config mask + Configure if respective S0i2/3 sub-states are to be supported. Each bit corresponds + to one sub-state (LPMx - BITx): LPM0-s0i2.0, LPM1-s0i2.1, LPM2-s0i2.2, LPM3-s0i3.0, + LPM4-s0i3.1, LPM5-s0i3.2, LPM6-s0i3.3, LPM7-s0i3.4. +**/ + UINT8 PmcLpmS0ixSubStateEnableMask; + +/** Offset 0x0F5E - PCIE RP Ltr Max Snoop Latency + Latency Tolerance Reporting, Max Snoop Latency. +**/ + UINT16 CpuPcieRpLtrMaxSnoopLatency[4]; + +/** Offset 0x0F66 - PCIE RP Ltr Max No Snoop Latency + Latency Tolerance Reporting, Max Non-Snoop Latency. +**/ + UINT16 CpuPcieRpLtrMaxNoSnoopLatency[4]; + +/** Offset 0x0F6E - PCIE RP Snoop Latency Override Mode + Latency Tolerance Reporting, Snoop Latency Override Mode. +**/ + UINT8 CpuPcieRpSnoopLatencyOverrideMode[4]; + +/** Offset 0x0F72 - PCIE RP Snoop Latency Override Multiplier + Latency Tolerance Reporting, Snoop Latency Override Multiplier. +**/ + UINT8 CpuPcieRpSnoopLatencyOverrideMultiplier[4]; + +/** Offset 0x0F76 - PCIE RP Snoop Latency Override Value + Latency Tolerance Reporting, Snoop Latency Override Value. +**/ + UINT16 CpuPcieRpSnoopLatencyOverrideValue[4]; + +/** Offset 0x0F7E - PCIE RP Non Snoop Latency Override Mode + Latency Tolerance Reporting, Non-Snoop Latency Override Mode. +**/ + UINT8 CpuPcieRpNonSnoopLatencyOverrideMode[4]; + +/** Offset 0x0F82 - PCIE RP Non Snoop Latency Override Multiplier + Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier. +**/ + UINT8 CpuPcieRpNonSnoopLatencyOverrideMultiplier[4]; + +/** Offset 0x0F86 - PCIE RP Non Snoop Latency Override Value + Latency Tolerance Reporting, Non-Snoop Latency Override Value. +**/ + UINT16 CpuPcieRpNonSnoopLatencyOverrideValue[4]; + +/** Offset 0x0F8E - PCIE RP Upstream Port Transmiter Preset + Used during Gen3 Link Equalization. Used for all lanes. Default is 7. +**/ + UINT8 CpuPcieRpGen3Uptp[4]; + +/** Offset 0x0F92 - PCIE RP Downstream Port Transmiter Preset + Used during Gen3 Link Equalization. Used for all lanes. Default is 7. +**/ + UINT8 CpuPcieRpGen3Dptp[4]; + +/** Offset 0x0F96 - PCIE RP Upstream Port Transmiter Preset + Used during Gen4 Link Equalization. Used for all lanes. Default is 8. +**/ + UINT8 CpuPcieRpGen4Uptp[4]; + +/** Offset 0x0F9A - PCIE RP Downstream Port Transmiter Preset + Used during Gen4 Link Equalization. Used for all lanes. Default is 9. +**/ + UINT8 CpuPcieRpGen4Dptp[4]; + +/** Offset 0x0F9E - PCIE RP Upstream Port Transmiter Preset + Used during Gen5 Link Equalization. Used for all lanes. Default is 7. +**/ + UINT8 CpuPcieRpGen5Uptp[4]; + +/** Offset 0x0FA2 - PCIE RP Downstream Port Transmiter Preset + Used during Gen5 Link Equalization. Used for all lanes. Default is 7. +**/ + UINT8 CpuPcieRpGen5Dptp[4]; + +/** Offset 0x0FA6 - Type C Port x Convert to TypeA + Enable / Disable(default) Type C Port x Convert to TypeA + $EN_DIS +**/ + UINT8 EnableTcssCovTypeA[4]; + +/** Offset 0x0FAA - PCH xhci port x for Type C Port x mapping + input PCH xhci port x for Type C Port 0 mapping. +**/ + UINT8 MappingPchXhciUsbA[4]; + +/** Offset 0x0FAE - FOMS Control Policy + Choose the Foms Control Policy, Default = 0 + 0: Auto, 1: Gen3 Foms, 2: Gen4 Foms, 3: Gen3 and Gen4 Foms +**/ + UINT8 CpuPcieFomsCp[4]; + +/** Offset 0x0FB2 - PMC C10 dynamic threshold dajustment enable + Set if you want to enable PMC C10 dynamic threshold adjustment. Only works on supported SKUs + $EN_DIS +**/ + UINT8 PmcC10DynamicThresholdAdjustment; + +/** Offset 0x0FB3 - P2P mode for PCIE RP + Enable/disable peer to peer mode for PCIE Root Ports. 0: Disable, 1: Enable. + 0: Disable, 1: Enable +**/ + UINT8 CpuPcieRpPeerToPeerMode[4]; + +/** Offset 0x0FB7 - Turbo Ratio Limit Ratio array + TurboRatioLimitRatio[7-0] will pair with TurboRatioLimitNumCore[7-0] to determine + the active core ranges for each frequency point. +**/ + UINT8 TurboRatioLimitRatio[8]; + +/** Offset 0x0FBF - Turbo Ratio Limit Num Core array + TurboRatioLimitNumCore[7-0] will pair with TurboRatioLimitRatio[7-0] to determine + the active core ranges for each frequency point. +**/ + UINT8 TurboRatioLimitNumCore[8]; + +/** Offset 0x0FC7 - ATOM Turbo Ratio Limit Ratio array + AtomTurboRatioLimitRatio[7-0] will pair with AtomTurboRatioLimitNumCore[7-0] to + determine the active core ranges for each frequency point. +**/ + UINT8 AtomTurboRatioLimitRatio[8]; + +/** Offset 0x0FCF - ATOM Turbo Ratio Limit Num Core array + AtomTurboRatioLimitNumCore[7-0] will pair with AtomTurboRatioLimitRatio[7-0] to + determine the active core ranges for each frequency point. +**/ + UINT8 AtomTurboRatioLimitNumCore[8]; + +/** Offset 0x0FD7 +**/ + UINT8 UnusedUpdSpace41; + +/** Offset 0x0FD8 - FspEventHandler + Optional pointer to the boot loader's implementation of FSP_EVENT_HANDLER. +**/ + UINT32 FspEventHandler; + +/** Offset 0x0FDC - Enable VMD Global Mapping + Enable/disable to VMD controller.0: Disable; 1: Enable(Default) + $EN_DIS +**/ + UINT8 VmdGlobalMapping; + +/** Offset 0x0FDD - CPU PCIE Port0 Link Disable + CPU PCIE Port0 Link Disable while Device attached into Port0 and Port1.0: Disable(Default); + 1: Enable. + $EN_DIS +**/ + UINT8 CpuPcieFunc0LinkDisable[4]; + +/** Offset 0x0FE1 - Skip VccIn Configuration + Skips VccIn configuration when enabled + $EN_DIS +**/ + UINT8 PmcSkipVccInConfig; + +/** Offset 0x0FE2 - CSE Data Resilience Support + 0: Disable CSE Data Resilience Support. ; 1: Enable CSE Data Resilience Support. + $EN_DIS +**/ + UINT8 CseDataResilience; + +/** Offset 0x0FE3 +**/ + UINT8 UnusedUpdSpace42; + +/** Offset 0x0FE4 - HorizontalResolution for PEI Logo + HorizontalResolution from PEIm Gfx for PEI Logo +**/ + UINT32 HorizontalResolution; + +/** Offset 0x0FE8 - VerticalResolution for PEI Logo + VerticalResolution from PEIm Gfx for PEI Logo +**/ + UINT32 VerticalResolution; + +/** Offset 0x0FEC - Touch Host Controller Active Ltr + Expose Active Ltr for OS driver to set +**/ + UINT32 ThcActiveLtr[2]; + +/** Offset 0x0FF4 - Touch Host Controller Idle Ltr + Expose Idle Ltr for OS driver to set +**/ + UINT32 ThcIdleLtr[2]; + +/** Offset 0x0FFC - Touch Host Controller Hid Over Spi ResetPad + Hid Over Spi ResetPad 0x0 - Use THC HW default Pad, For other pad setting refer + to GpioPins +**/ + UINT32 ThcHidResetPad[2]; + +/** Offset 0x1004 - Touch Host Controller Hid Over Spi ResetPad Trigger + Hid Over Spi Reset Pad Trigger 0x0:Low, 0x1:High +**/ + UINT32 ThcHidResetPadTrigger[2]; + +/** Offset 0x100C - Touch Host Controller Hid Over Spi Connection Speed + Hid Over Spi Connection Speed - SPI Frequency +**/ + UINT32 ThcHidConnectionSpeed[2]; + +/** Offset 0x1014 - Touch Host Controller Hid Over Spi Limit PacketSize + When set, limits SPI read & write packet size to 64B. Otherwise, THC uses Max Soc + packet size for SPI Read and Write 0x0- Max Soc Packet Size, 0x11 - 64 Bytes +**/ + UINT32 ThcLimitPacketSize[2]; + +/** Offset 0x101C - Touch Host Controller Hid Over Spi Limit PacketSize + Minimum amount of delay the THC/QUICKSPI driver must wait between end of write operation + and begin of read operation. This value shall be in 10us multiples 0x0: Disabled, + 1-65535 (0xFFFF) - up to 655350 us +**/ + UINT32 ThcPerformanceLimitation[2]; + +/** Offset 0x1024 - Touch Host Controller Hid Over Spi Input Report Header Address + Hid Over Spi Input Report Header Address +**/ + UINT32 ThcHidInputReportHeaderAddress[2]; + +/** Offset 0x102C - Touch Host Controller Hid Over Spi Input Report Body Address + Hid Over Spi Input Report Body Address +**/ + UINT32 ThcHidInputReportBodyAddress[2]; + +/** Offset 0x1034 - Touch Host Controller Hid Over Spi Output Report Address + Hid Over Spi Output Report Address +**/ + UINT32 ThcHidOutputReportAddress[2]; + +/** Offset 0x103C - Touch Host Controller Hid Over Spi Read Opcode + Hid Over Spi Read Opcode +**/ + UINT32 ThcHidReadOpcode[2]; + +/** Offset 0x1044 - Touch Host Controller Hid Over Spi Write Opcode + Hid Over Spi Write Opcode +**/ + UINT32 ThcHidWriteOpcode[2]; + +/** Offset 0x104C - Touch Host Controller Hid Over Spi Flags + Hid Over Spi Flags 0x0:Single SPI Mode, 0x4000:Dual SPI Mode, 0x8000:Quad SPI Mode +**/ + UINT32 ThcHidFlags[2]; + +/** Offset 0x1054 +**/ + UINT8 UnusedUpdSpace43[2]; + +/** Offset 0x1056 +**/ + UINT8 ReservedFspsUpd[2]; +} FSP_S_CONFIG; + +/** Fsp S UPD Configuration +**/ +typedef struct { + +/** Offset 0x0000 +**/ + FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + FSPS_ARCH_UPD FspsArchUpd; + +/** Offset 0x0040 +**/ + FSP_S_CONFIG FspsConfig; + +/** Offset 0x1058 +**/ + UINT8 UnusedUpdSpace44[6]; + +/** Offset 0x105E +**/ + UINT16 UpdTerminator; +} FSPS_UPD; + +#pragma pack() + +#endif diff --git a/AlderLakeFspBinPkg/Client/AlderLakeP/Include/FsptUpd.h b/AlderLakeFspBinPkg/Client/AlderLakeP/Include/FsptUpd.h new file mode 100644 index 0000000..61eb7aa --- /dev/null +++ b/AlderLakeFspBinPkg/Client/AlderLakeP/Include/FsptUpd.h @@ -0,0 +1,357 @@ +/** @file + +Copyright (c) 2022, Intel Corporation. All rights reserved.
+ +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPTUPD_H__ +#define __FSPTUPD_H__ + +#include + +#pragma pack(1) + + +/** Fsp T Core UPD +**/ +typedef struct { + +/** Offset 0x0040 +**/ + UINT32 MicrocodeRegionBase; + +/** Offset 0x0044 +**/ + UINT32 MicrocodeRegionSize; + +/** Offset 0x0048 +**/ + UINT32 CodeRegionBase; + +/** Offset 0x004C +**/ + UINT32 CodeRegionSize; + +/** Offset 0x0050 +**/ + UINT8 Reserved[16]; +} FSPT_CORE_UPD; + +/** Fsp T Configuration +**/ +typedef struct { + +/** Offset 0x0060 - PcdSerialIoUartDebugEnable + Enable SerialIo Uart debug library with/without initializing SerialIo Uart device in FSP. + 0:Disable, 1:Enable and Initialize, 2:Enable without Initializing +**/ + UINT8 PcdSerialIoUartDebugEnable; + +/** Offset 0x0061 - PcdSerialIoUartNumber + Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT + Core interface, it cannot be used for debug purpose. + 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2 +**/ + UINT8 PcdSerialIoUartNumber; + +/** Offset 0x0062 - PcdSerialIoUartMode - FSPT + Select SerialIo Uart Controller mode + 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom, + 4:SerialIoUartSkipInit +**/ + UINT8 PcdSerialIoUartMode; + +/** Offset 0x0063 +**/ + UINT8 UnusedUpdSpace0; + +/** Offset 0x0064 - PcdSerialIoUartBaudRate - FSPT + Set default BaudRate Supported from 0 - default to 6000000 +**/ + UINT32 PcdSerialIoUartBaudRate; + +/** Offset 0x0068 - Pci Express Base Address + Base address to be programmed for Pci Express +**/ + UINT64 PcdPciExpressBaseAddress; + +/** Offset 0x0070 - Pci Express Region Length + Region Length to be programmed for Pci Express +**/ + UINT32 PcdPciExpressRegionLength; + +/** Offset 0x0074 - PcdSerialIoUartParity - FSPT + Set default Parity. + 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity +**/ + UINT8 PcdSerialIoUartParity; + +/** Offset 0x0075 - PcdSerialIoUartDataBits - FSPT + Set default word length. 0: Default, 5,6,7,8 +**/ + UINT8 PcdSerialIoUartDataBits; + +/** Offset 0x0076 - PcdSerialIoUartStopBits - FSPT + Set default stop bits. + 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits +**/ + UINT8 PcdSerialIoUartStopBits; + +/** Offset 0x0077 - PcdSerialIoUartAutoFlow - FSPT + Enables UART hardware flow control, CTS and RTS lines. + 0: Disable, 1:Enable +**/ + UINT8 PcdSerialIoUartAutoFlow; + +/** Offset 0x0078 - PcdSerialIoUartRxPinMux - FSPT + Select RX pin muxing for SerialIo UART used for debug +**/ + UINT32 PcdSerialIoUartRxPinMux; + +/** Offset 0x007C - PcdSerialIoUartTxPinMux - FSPT + Select TX pin muxing for SerialIo UART used for debug +**/ + UINT32 PcdSerialIoUartTxPinMux; + +/** Offset 0x0080 - PcdSerialIoUartRtsPinMux - FSPT + Select SerialIo Uart used for debug Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS* + for possible values. +**/ + UINT32 PcdSerialIoUartRtsPinMux; + +/** Offset 0x0084 - PcdSerialIoUartCtsPinMux - FSPT + Select SerialIo Uart used for debug Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS* + for possible values. +**/ + UINT32 PcdSerialIoUartCtsPinMux; + +/** Offset 0x0088 - PcdSerialIoUartDebugMmioBase - FSPT + Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIoUartMode + = SerialIoUartPci. +**/ + UINT32 PcdSerialIoUartDebugMmioBase; + +/** Offset 0x008C - PcdLpcUartDebugEnable + Enable to initialize LPC Uart device in FSP. + 0:Disable, 1:Enable +**/ + UINT8 PcdLpcUartDebugEnable; + +/** Offset 0x008D - Debug Interfaces + Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, + BIT2 - Not used. +**/ + UINT8 PcdDebugInterfaceFlags; + +/** Offset 0x008E - PcdSerialDebugLevel + Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, + Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, + Info & Verbose. + 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load + Error Warnings and Info, 5:Load Error Warnings Info and Verbose +**/ + UINT8 PcdSerialDebugLevel; + +/** Offset 0x008F - ISA Serial Base selection + Select ISA Serial Base address. Default is 0x3F8. + 0:0x3F8, 1:0x2F8 +**/ + UINT8 PcdIsaSerialUartBase; + +/** Offset 0x0090 - PcdSerialIo2ndUartEnable + Enable Additional SerialIo Uart device in FSP. + 0:Disable, 1:Enable and Initialize, 2:Enable without Initializing +**/ + UINT8 PcdSerialIo2ndUartEnable; + +/** Offset 0x0091 - PcdSerialIo2ndUartNumber + Select SerialIo Uart Controller Number + 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2 +**/ + UINT8 PcdSerialIo2ndUartNumber; + +/** Offset 0x0092 - PcdSerialIo2ndUartMode - FSPT + Select SerialIo Uart Controller mode + 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom, + 4:SerialIoUartSkipInit +**/ + UINT8 PcdSerialIo2ndUartMode; + +/** Offset 0x0093 +**/ + UINT8 UnusedUpdSpace1; + +/** Offset 0x0094 - PcdSerialIo2ndUartBaudRate - FSPT + Set default BaudRate Supported from 0 - default to 6000000 +**/ + UINT32 PcdSerialIo2ndUartBaudRate; + +/** Offset 0x0098 - PcdSerialIo2ndUartParity - FSPT + Set default Parity. + 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity +**/ + UINT8 PcdSerialIo2ndUartParity; + +/** Offset 0x0099 - PcdSerialIo2ndUartDataBits - FSPT + Set default word length. 0: Default, 5,6,7,8 +**/ + UINT8 PcdSerialIo2ndUartDataBits; + +/** Offset 0x009A - PcdSerialIo2ndUartStopBits - FSPT + Set default stop bits. + 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits +**/ + UINT8 PcdSerialIo2ndUartStopBits; + +/** Offset 0x009B - PcdSerialIo2ndUartAutoFlow - FSPT + Enables UART hardware flow control, CTS and RTS lines. + 0: Disable, 1:Enable +**/ + UINT8 PcdSerialIo2ndUartAutoFlow; + +/** Offset 0x009C - PcdSerialIo2ndUartRxPinMux - FSPT + Select RX pin muxing for SerialIo UART +**/ + UINT32 PcdSerialIo2ndUartRxPinMux; + +/** Offset 0x00A0 - PcdSerialIo2ndUartTxPinMux - FSPT + Select TX pin muxing for SerialIo UART +**/ + UINT32 PcdSerialIo2ndUartTxPinMux; + +/** Offset 0x00A4 - PcdSerialIo2ndUartRtsPinMux - FSPT + Select SerialIo Uart Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS* + for possible values. +**/ + UINT32 PcdSerialIo2ndUartRtsPinMux; + +/** Offset 0x00A8 - PcdSerialIo2ndUartCtsPinMux - FSPT + Select SerialIo Uart Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS* + for possible values. +**/ + UINT32 PcdSerialIo2ndUartCtsPinMux; + +/** Offset 0x00AC - PcdSerialIo2ndUartMmioBase - FSPT + Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIo2ndUartMode + = SerialIoUartPci. +**/ + UINT32 PcdSerialIo2ndUartMmioBase; + +/** Offset 0x00B0 +**/ + UINT32 TopMemoryCacheSize; + +/** Offset 0x00B4 - FspDebugHandler + Optional pointer to the boot loader's implementation of FSP_DEBUG_HANDLER. +**/ + UINT32 FspDebugHandler; + +/** Offset 0x00B8 - Serial Io SPI Chip Select Polarity + Sets polarity for each chip Select. Available options: 0:SerialIoSpiCsActiveLow, + 1:SerialIoSpiCsActiveHigh +**/ + UINT8 PcdSerialIoSpiCsPolarity[2]; + +/** Offset 0x00BA - Serial Io SPI Chip Select Enable + 0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled +**/ + UINT8 PcdSerialIoSpiCsEnable[2]; + +/** Offset 0x00BC - Serial Io SPI Device Mode + When mode is set to Pci, controller is initalized in early stage. Available modes: + 0:SerialIoSpiDisabled, 1:SerialIoSpiPci. +**/ + UINT8 PcdSerialIoSpiMode; + +/** Offset 0x00BD - Serial Io SPI Default Chip Select Output + Sets Default CS as Output. Available options: 0:CS0, 1:CS1 +**/ + UINT8 PcdSerialIoSpiDefaultCsOutput; + +/** Offset 0x00BE - Serial Io SPI Default Chip Select Mode HW/SW + Sets Default CS Mode Hardware or Software. Available options: 0:HW, 1:SW +**/ + UINT8 PcdSerialIoSpiCsMode; + +/** Offset 0x00BF - Serial Io SPI Default Chip Select State Low/High + Sets Default CS State Low or High. Available options: 0:Low, 1:High +**/ + UINT8 PcdSerialIoSpiCsState; + +/** Offset 0x00C0 - Serial Io SPI Device Number + Select which Serial Io SPI controller is initalized in early stage. +**/ + UINT8 PcdSerialIoSpiNumber; + +/** Offset 0x00C1 +**/ + UINT8 UnusedUpdSpace2[3]; + +/** Offset 0x00C4 - Serial Io SPI Device MMIO Base + Assigns MMIO for Serial Io SPI controller usage in early stage. +**/ + UINT32 PcdSerialIoSpiMmioBase; + +/** Offset 0x00C8 +**/ + UINT8 ReservedFsptUpd1[16]; +} FSP_T_CONFIG; + +/** Fsp T UPD Configuration +**/ +typedef struct { + +/** Offset 0x0000 +**/ + FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + FSPT_ARCH_UPD FsptArchUpd; + +/** Offset 0x0040 +**/ + FSPT_CORE_UPD FsptCoreUpd; + +/** Offset 0x0060 +**/ + FSP_T_CONFIG FsptConfig; + +/** Offset 0x00D8 +**/ + UINT8 UnusedUpdSpace3[6]; + +/** Offset 0x00DE +**/ + UINT16 UpdTerminator; +} FSPT_UPD; + +#pragma pack() + +#endif diff --git a/AlderLakeFspBinPkg/Client/AlderLakeP/Include/GpioConfig.h b/AlderLakeFspBinPkg/Client/AlderLakeP/Include/GpioConfig.h new file mode 100644 index 0000000..ee81f48 --- /dev/null +++ b/AlderLakeFspBinPkg/Client/AlderLakeP/Include/GpioConfig.h @@ -0,0 +1,332 @@ +/** @file + Header file for GpioConfig structure used by GPIO library. + + @copyright + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +@par Specification Reference: +**/ +#ifndef _GPIO_CONFIG_H_ +#define _GPIO_CONFIG_H_ + +#pragma pack(push, 1) + +/// +/// For any GpioPad usage in code use GPIO_PAD type +/// +typedef UINT32 GPIO_PAD; + + +/// +/// For any GpioGroup usage in code use GPIO_GROUP type +/// +typedef UINT32 GPIO_GROUP; + +/** + GPIO configuration structure used for pin programming. + Structure contains fields that can be used to configure pad. +**/ +typedef struct { + /** + Pad Mode + Pad can be set as GPIO or one of its native functions. + When in native mode setting Direction (except Inversion), OutputState, + InterruptConfig, Host Software Pad Ownership and OutputStateLock are unnecessary. + Refer to definition of GPIO_PAD_MODE. + Refer to EDS for each native mode according to the pad. + **/ + UINT32 PadMode : 5; + /** + Host Software Pad Ownership + Set pad to ACPI mode or GPIO Driver Mode. + Refer to definition of GPIO_HOSTSW_OWN. + **/ + UINT32 HostSoftPadOwn : 2; + /** + GPIO Direction + Can choose between In, In with inversion, Out, both In and Out, both In with inversion and out or disabling both. + Refer to definition of GPIO_DIRECTION for supported settings. + **/ + UINT32 Direction : 6; + /** + Output State + Set Pad output value. + Refer to definition of GPIO_OUTPUT_STATE for supported settings. + This setting takes place when output is enabled. + **/ + UINT32 OutputState : 2; + /** + GPIO Interrupt Configuration + Set Pad to cause one of interrupts (IOxAPIC/SCI/SMI/NMI). + This setting is applicable only if GPIO is in GpioMode with input enabled. + Refer to definition of GPIO_INT_CONFIG for supported settings. + **/ + UINT32 InterruptConfig : 9; + /** + GPIO Power Configuration. + This setting controls Pad Reset Configuration. + Refer to definition of GPIO_RESET_CONFIG for supported settings. + **/ + UINT32 PowerConfig : 8; + /** + GPIO Electrical Configuration + This setting controls pads termination and voltage tolerance. + Refer to definition of GPIO_ELECTRICAL_CONFIG for supported settings. + **/ + UINT32 ElectricalConfig : 9; + /** + GPIO Lock Configuration + This setting controls pads lock. + Refer to definition of GPIO_LOCK_CONFIG for supported settings. + **/ + UINT32 LockConfig : 4; + /** + Additional GPIO configuration + Refer to definition of GPIO_OTHER_CONFIG for supported settings. + **/ + UINT32 OtherSettings : 2; + UINT32 RsvdBits : 17; ///< Reserved bits for future extension +} GPIO_CONFIG; + + +typedef enum { + GpioHardwareDefault = 0x0 ///< Leave setting unmodified +} GPIO_HARDWARE_DEFAULT; + +/** + GPIO Pad Mode + Refer to GPIO documentation on native functions available for certain pad. + If GPIO is set to one of NativeX modes then following settings are not applicable + and can be skipped: + - Interrupt related settings + - Host Software Ownership + - Output/Input enabling/disabling + - Output lock +**/ +typedef enum { + GpioPadModeGpio = 0x1, + GpioPadModeNative1 = 0x3, + GpioPadModeNative2 = 0x5, + GpioPadModeNative3 = 0x7, + GpioPadModeNative4 = 0x9 +} GPIO_PAD_MODE; + +/** + Host Software Pad Ownership modes + This setting affects GPIO interrupt status registers. Depending on chosen ownership + some GPIO Interrupt status register get updated and other masked. + Please refer to EDS for HOSTSW_OWN register description. +**/ +typedef enum { + GpioHostOwnDefault = 0x0, ///< Leave ownership value unmodified + /** + Set HOST ownership to ACPI. + Use this setting if pad is not going to be used by GPIO OS driver. + If GPIO is configured to generate SCI/SMI/NMI then this setting must be + used for interrupts to work + **/ + GpioHostOwnAcpi = 0x1, + /** + Set HOST ownership to GPIO Driver mode. + Use this setting only if GPIO pad should be controlled by GPIO OS Driver. + GPIO OS Driver will be able to control the pad if appropriate entry in + ACPI exists (refer to ACPI specification for GpioIo and GpioInt descriptors) + **/ + GpioHostOwnGpio = 0x3 +} GPIO_HOSTSW_OWN; + +/// +/// GPIO Direction +/// +typedef enum { + GpioDirDefault = 0x0, ///< Leave pad direction setting unmodified + GpioDirInOut = (0x1 | (0x1 << 3)), ///< Set pad for both output and input + GpioDirInInvOut = (0x1 | (0x3 << 3)), ///< Set pad for both output and input with inversion + GpioDirIn = (0x3 | (0x1 << 3)), ///< Set pad for input only + GpioDirInInv = (0x3 | (0x3 << 3)), ///< Set pad for input with inversion + GpioDirOut = 0x5, ///< Set pad for output only + GpioDirNone = 0x7 ///< Disable both output and input +} GPIO_DIRECTION; + +/** + GPIO Output State + This field is relevant only if output is enabled +**/ +typedef enum { + GpioOutDefault = 0x0, ///< Leave output value unmodified + GpioOutLow = 0x1, ///< Set output to low + GpioOutHigh = 0x3 ///< Set output to high +} GPIO_OUTPUT_STATE; + +/** + GPIO interrupt configuration + This setting is applicable only if pad is in GPIO mode and has input enabled. + GPIO_INT_CONFIG allows to choose which interrupt is generated (IOxAPIC/SCI/SMI/NMI) + and how it is triggered (edge or level). Refer to PADCFG_DW0 register description in + EDS for details on this settings. + Field from GpioIntNmi to GpioIntApic can be OR'ed with GpioIntLevel to GpioIntBothEdge + to describe an interrupt e.g. GpioIntApic | GpioIntLevel + If GPIO is set to cause an SCI then also GPI_GPE_EN is enabled for this pad. + If GPIO is set to cause an NMI then also GPI_NMI_EN is enabled for this pad. + Not all GPIO are capable of generating an SMI or NMI interrupt. + When routing GPIO to cause an IOxAPIC interrupt care must be taken, as this + interrupt cannot be shared and its IRQn number is not configurable. + Refer to EDS for GPIO pads IRQ numbers (PADCFG_DW1.IntSel) + If GPIO is under GPIO OS driver control and appropriate ACPI GpioInt descriptor + exist then use only trigger type setting (from GpioIntLevel to GpioIntBothEdge). + This type of GPIO Driver interrupt doesn't have any additional routing setting + required to be set by BIOS. Interrupt is handled by GPIO OS Driver. +**/ + +typedef enum { + GpioIntDefault = 0x0, ///< Leave value of interrupt routing unmodified + GpioIntDis = 0x1, ///< Disable IOxAPIC/SCI/SMI/NMI interrupt generation + GpioIntNmi = 0x3, ///< Enable NMI interrupt only + GpioIntSmi = 0x5, ///< Enable SMI interrupt only + GpioIntSci = 0x9, ///< Enable SCI interrupt only + GpioIntApic = 0x11, ///< Enable IOxAPIC interrupt only + GpioIntLevel = (0x1 << 5), ///< Set interrupt as level triggered + GpioIntEdge = (0x3 << 5), ///< Set interrupt as edge triggered (type of edge depends on input inversion) + GpioIntLvlEdgDis = (0x5 << 5), ///< Disable interrupt trigger + GpioIntBothEdge = (0x7 << 5) ///< Set interrupt as both edge triggered +} GPIO_INT_CONFIG; + +#define B_GPIO_INT_CONFIG_INT_SOURCE_MASK 0x1F ///< Mask for GPIO_INT_CONFIG for interrupt source +#define B_GPIO_INT_CONFIG_INT_TYPE_MASK 0xE0 ///< Mask for GPIO_INT_CONFIG for interrupt type + +/** + GPIO Power Configuration + GPIO_RESET_CONFIG allows to set GPIO Reset type (PADCFG_DW0.PadRstCfg) which will + be used to reset certain GPIO settings. + Refer to EDS for settings that are controllable by PadRstCfg. +**/ +typedef enum { + + + GpioResetDefault = 0x00, ///< Leave value of pad reset unmodified + /// + /// Deprecated settings. Maintained only for compatibility. + /// + GpioResetPwrGood = 0x09, ///< GPP: RSMRST; GPD: DSW_PWROK; (PadRstCfg = 00b = "Powergood") + GpioResetDeep = 0x0B, ///< Deep GPIO Reset (PadRstCfg = 01b = "Deep GPIO Reset") + GpioResetNormal = 0x0D, ///< GPIO Reset (PadRstCfg = 10b = "GPIO Reset" ) + GpioResetResume = 0x0F, ///< GPP: Reserved; GPD: RSMRST; (PadRstCfg = 11b = "Resume Reset" ) + + /// + /// New GPIO reset configuration options + /// + /** + Resume Reset (RSMRST) + GPP: PadRstCfg = 00b = "Powergood" + GPD: PadRstCfg = 11b = "Resume Reset" + Pad setting will reset on: + - DeepSx transition + - G3 + Pad settings will not reset on: + - S3/S4/S5 transition + - Warm/Cold/Global reset + **/ + GpioResumeReset = 0x01, + /** + Host Deep Reset + PadRstCfg = 01b = "Deep GPIO Reset" + Pad settings will reset on: + - Warm/Cold/Global reset + - DeepSx transition + - G3 + Pad settings will not reset on: + - S3/S4/S5 transition + **/ + GpioHostDeepReset = 0x03, + /** + Platform Reset (PLTRST) + PadRstCfg = 10b = "GPIO Reset" + Pad settings will reset on: + - S3/S4/S5 transition + - Warm/Cold/Global reset + - DeepSx transition + - G3 + **/ + GpioPlatformReset = 0x05, + /** + Deep Sleep Well Reset (DSW_PWROK) + GPP: not applicable + GPD: PadRstCfg = 00b = "Powergood" + Pad settings will reset on: + - G3 + Pad settings will not reset on: + - S3/S4/S5 transition + - Warm/Cold/Global reset + - DeepSx transition + **/ + GpioDswReset = 0x07 +} GPIO_RESET_CONFIG; + +/** + GPIO Electrical Configuration + Set GPIO termination and Pad Tolerance (applicable only for some pads) + Field from GpioTermNone to GpioTermNative can be OR'ed with GpioTolerance1v8. +**/ +typedef enum { + GpioTermDefault = 0x0, ///< Leave termination setting unmodified + GpioTermNone = 0x1, ///< none + GpioTermWpd5K = 0x5, ///< 5kOhm weak pull-down + GpioTermWpd20K = 0x9, ///< 20kOhm weak pull-down + GpioTermWpu1K = 0x13, ///< 1kOhm weak pull-up + GpioTermWpu2K = 0x17, ///< 2kOhm weak pull-up + GpioTermWpu5K = 0x15, ///< 5kOhm weak pull-up + GpioTermWpu20K = 0x19, ///< 20kOhm weak pull-up + GpioTermWpu1K2K = 0x1B, ///< 1kOhm & 2kOhm weak pull-up + /** + Native function controls pads termination + This setting is applicable only to some native modes. + Please check EDS to determine which native functionality + can control pads termination + **/ + GpioTermNative = 0x1F, + GpioNoTolerance1v8 = (0x1 << 5), ///< Disable 1.8V pad tolerance + GpioTolerance1v8 = (0x3 << 5) ///< Enable 1.8V pad tolerance +} GPIO_ELECTRICAL_CONFIG; + +#define B_GPIO_ELECTRICAL_CONFIG_TERMINATION_MASK 0x1F ///< Mask for GPIO_ELECTRICAL_CONFIG for termination value +#define B_GPIO_ELECTRICAL_CONFIG_1V8_TOLERANCE_MASK 0x60 ///< Mask for GPIO_ELECTRICAL_CONFIG for 1v8 tolerance setting + +/** + GPIO LockConfiguration + Set GPIO configuration lock and output state lock. + GpioLockPadConfig and GpioLockOutputState can be OR'ed. + Lock settings reset is in Powergood domain. Care must be taken when using this setting + as fields it locks may be reset by a different signal and can be controllable + by what is in GPIO_RESET_CONFIG (PADCFG_DW0.PadRstCfg). GPIO library provides + functions which allow to unlock a GPIO pad. +**/ +typedef enum { + GpioLockDefault = 0x0, ///< Leave lock setting unmodified + GpioPadConfigLock = 0x3, ///< Lock Pad Configuration + GpioOutputStateLock = 0x5 ///< Lock GPIO pad output value +} GPIO_LOCK_CONFIG; + +#define B_GPIO_LOCK_CONFIG_PAD_CONF_LOCK_MASK 0x3 ///< Mask for GPIO_LOCK_CONFIG for Pad Configuration Lock +#define B_GPIO_LOCK_CONFIG_OUTPUT_LOCK_MASK 0x5 ///< Mask for GPIO_LOCK_CONFIG for Pad Output Lock + +/** + Other GPIO Configuration + GPIO_OTHER_CONFIG is used for less often settings and for future extensions + Supported settings: + - RX raw override to '1' - allows to override input value to '1' + This setting is applicable only if in input mode (both in GPIO and native usage). + The override takes place at the internal pad state directly from buffer and before the RXINV. +**/ +typedef enum { + GpioRxRaw1Default = 0x0, ///< Use default input override value + GpioRxRaw1Dis = 0x1, ///< Don't override input + GpioRxRaw1En = 0x3 ///< Override input to '1' +} GPIO_OTHER_CONFIG; + +#define B_GPIO_OTHER_CONFIG_RXRAW_MASK 0x3 ///< Mask for GPIO_OTHER_CONFIG for RxRaw1 setting + +#pragma pack(pop) + +#endif //_GPIO_CONFIG_H_ diff --git a/AlderLakeFspBinPkg/Client/AlderLakeP/Include/GpioSampleDef.h b/AlderLakeFspBinPkg/Client/AlderLakeP/Include/GpioSampleDef.h new file mode 100644 index 0000000..eaa9233 --- /dev/null +++ b/AlderLakeFspBinPkg/Client/AlderLakeP/Include/GpioSampleDef.h @@ -0,0 +1,381 @@ +/** @file + + @copyright + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __GPIOCONFIG_H__ +#define __GPIOCONFIG_H__ +#include +#include +#include + +/* + SKL LP GPIO pins + Use below for functions from PCH GPIO Lib which + require GpioPad as argument. Encoding used here + has all information required by library functions +*/ +#define GPIO_SKL_LP_GPP_A0 0x02000000 +#define GPIO_SKL_LP_GPP_A1 0x02000001 +#define GPIO_SKL_LP_GPP_A2 0x02000002 +#define GPIO_SKL_LP_GPP_A3 0x02000003 +#define GPIO_SKL_LP_GPP_A4 0x02000004 +#define GPIO_SKL_LP_GPP_A5 0x02000005 +#define GPIO_SKL_LP_GPP_A6 0x02000006 +#define GPIO_SKL_LP_GPP_A7 0x02000007 +#define GPIO_SKL_LP_GPP_A8 0x02000008 +#define GPIO_SKL_LP_GPP_A9 0x02000009 +#define GPIO_SKL_LP_GPP_A10 0x0200000A +#define GPIO_SKL_LP_GPP_A11 0x0200000B +#define GPIO_SKL_LP_GPP_A12 0x0200000C +#define GPIO_SKL_LP_GPP_A13 0x0200000D +#define GPIO_SKL_LP_GPP_A14 0x0200000E +#define GPIO_SKL_LP_GPP_A15 0x0200000F +#define GPIO_SKL_LP_GPP_A16 0x02000010 +#define GPIO_SKL_LP_GPP_A17 0x02000011 +#define GPIO_SKL_LP_GPP_A18 0x02000012 +#define GPIO_SKL_LP_GPP_A19 0x02000013 +#define GPIO_SKL_LP_GPP_A20 0x02000014 +#define GPIO_SKL_LP_GPP_A21 0x02000015 +#define GPIO_SKL_LP_GPP_A22 0x02000016 +#define GPIO_SKL_LP_GPP_A23 0x02000017 +#define GPIO_SKL_LP_GPP_B0 0x02010000 +#define GPIO_SKL_LP_GPP_B1 0x02010001 +#define GPIO_SKL_LP_GPP_B2 0x02010002 +#define GPIO_SKL_LP_GPP_B3 0x02010003 +#define GPIO_SKL_LP_GPP_B4 0x02010004 +#define GPIO_SKL_LP_GPP_B5 0x02010005 +#define GPIO_SKL_LP_GPP_B6 0x02010006 +#define GPIO_SKL_LP_GPP_B7 0x02010007 +#define GPIO_SKL_LP_GPP_B8 0x02010008 +#define GPIO_SKL_LP_GPP_B9 0x02010009 +#define GPIO_SKL_LP_GPP_B10 0x0201000A +#define GPIO_SKL_LP_GPP_B11 0x0201000B +#define GPIO_SKL_LP_GPP_B12 0x0201000C +#define GPIO_SKL_LP_GPP_B13 0x0201000D +#define GPIO_SKL_LP_GPP_B14 0x0201000E +#define GPIO_SKL_LP_GPP_B15 0x0201000F +#define GPIO_SKL_LP_GPP_B16 0x02010010 +#define GPIO_SKL_LP_GPP_B17 0x02010011 +#define GPIO_SKL_LP_GPP_B18 0x02010012 +#define GPIO_SKL_LP_GPP_B19 0x02010013 +#define GPIO_SKL_LP_GPP_B20 0x02010014 +#define GPIO_SKL_LP_GPP_B21 0x02010015 +#define GPIO_SKL_LP_GPP_B22 0x02010016 +#define GPIO_SKL_LP_GPP_B23 0x02010017 +#define GPIO_SKL_LP_GPP_C0 0x02020000 +#define GPIO_SKL_LP_GPP_C1 0x02020001 +#define GPIO_SKL_LP_GPP_C2 0x02020002 +#define GPIO_SKL_LP_GPP_C3 0x02020003 +#define GPIO_SKL_LP_GPP_C4 0x02020004 +#define GPIO_SKL_LP_GPP_C5 0x02020005 +#define GPIO_SKL_LP_GPP_C6 0x02020006 +#define GPIO_SKL_LP_GPP_C7 0x02020007 +#define GPIO_SKL_LP_GPP_C8 0x02020008 +#define GPIO_SKL_LP_GPP_C9 0x02020009 +#define GPIO_SKL_LP_GPP_C10 0x0202000A +#define GPIO_SKL_LP_GPP_C11 0x0202000B +#define GPIO_SKL_LP_GPP_C12 0x0202000C +#define GPIO_SKL_LP_GPP_C13 0x0202000D +#define GPIO_SKL_LP_GPP_C14 0x0202000E +#define GPIO_SKL_LP_GPP_C15 0x0202000F +#define GPIO_SKL_LP_GPP_C16 0x02020010 +#define GPIO_SKL_LP_GPP_C17 0x02020011 +#define GPIO_SKL_LP_GPP_C18 0x02020012 +#define GPIO_SKL_LP_GPP_C19 0x02020013 +#define GPIO_SKL_LP_GPP_C20 0x02020014 +#define GPIO_SKL_LP_GPP_C21 0x02020015 +#define GPIO_SKL_LP_GPP_C22 0x02020016 +#define GPIO_SKL_LP_GPP_C23 0x02020017 +#define GPIO_SKL_LP_GPP_D0 0x02030000 +#define GPIO_SKL_LP_GPP_D1 0x02030001 +#define GPIO_SKL_LP_GPP_D2 0x02030002 +#define GPIO_SKL_LP_GPP_D3 0x02030003 +#define GPIO_SKL_LP_GPP_D4 0x02030004 +#define GPIO_SKL_LP_GPP_D5 0x02030005 +#define GPIO_SKL_LP_GPP_D6 0x02030006 +#define GPIO_SKL_LP_GPP_D7 0x02030007 +#define GPIO_SKL_LP_GPP_D8 0x02030008 +#define GPIO_SKL_LP_GPP_D9 0x02030009 +#define GPIO_SKL_LP_GPP_D10 0x0203000A +#define GPIO_SKL_LP_GPP_D11 0x0203000B +#define GPIO_SKL_LP_GPP_D12 0x0203000C +#define GPIO_SKL_LP_GPP_D13 0x0203000D +#define GPIO_SKL_LP_GPP_D14 0x0203000E +#define GPIO_SKL_LP_GPP_D15 0x0203000F +#define GPIO_SKL_LP_GPP_D16 0x02030010 +#define GPIO_SKL_LP_GPP_D17 0x02030011 +#define GPIO_SKL_LP_GPP_D18 0x02030012 +#define GPIO_SKL_LP_GPP_D19 0x02030013 +#define GPIO_SKL_LP_GPP_D20 0x02030014 +#define GPIO_SKL_LP_GPP_D21 0x02030015 +#define GPIO_SKL_LP_GPP_D22 0x02030016 +#define GPIO_SKL_LP_GPP_D23 0x02030017 +#define GPIO_SKL_LP_GPP_E0 0x02040000 +#define GPIO_SKL_LP_GPP_E1 0x02040001 +#define GPIO_SKL_LP_GPP_E2 0x02040002 +#define GPIO_SKL_LP_GPP_E3 0x02040003 +#define GPIO_SKL_LP_GPP_E4 0x02040004 +#define GPIO_SKL_LP_GPP_E5 0x02040005 +#define GPIO_SKL_LP_GPP_E6 0x02040006 +#define GPIO_SKL_LP_GPP_E7 0x02040007 +#define GPIO_SKL_LP_GPP_E8 0x02040008 +#define GPIO_SKL_LP_GPP_E9 0x02040009 +#define GPIO_SKL_LP_GPP_E10 0x0204000A +#define GPIO_SKL_LP_GPP_E11 0x0204000B +#define GPIO_SKL_LP_GPP_E12 0x0204000C +#define GPIO_SKL_LP_GPP_E13 0x0204000D +#define GPIO_SKL_LP_GPP_E14 0x0204000E +#define GPIO_SKL_LP_GPP_E15 0x0204000F +#define GPIO_SKL_LP_GPP_E16 0x02040010 +#define GPIO_SKL_LP_GPP_E17 0x02040011 +#define GPIO_SKL_LP_GPP_E18 0x02040012 +#define GPIO_SKL_LP_GPP_E19 0x02040013 +#define GPIO_SKL_LP_GPP_E20 0x02040014 +#define GPIO_SKL_LP_GPP_E21 0x02040015 +#define GPIO_SKL_LP_GPP_E22 0x02040016 +#define GPIO_SKL_LP_GPP_E23 0x02040017 +#define GPIO_SKL_LP_GPP_F0 0x02050000 +#define GPIO_SKL_LP_GPP_F1 0x02050001 +#define GPIO_SKL_LP_GPP_F2 0x02050002 +#define GPIO_SKL_LP_GPP_F3 0x02050003 +#define GPIO_SKL_LP_GPP_F4 0x02050004 +#define GPIO_SKL_LP_GPP_F5 0x02050005 +#define GPIO_SKL_LP_GPP_F6 0x02050006 +#define GPIO_SKL_LP_GPP_F7 0x02050007 +#define GPIO_SKL_LP_GPP_F8 0x02050008 +#define GPIO_SKL_LP_GPP_F9 0x02050009 +#define GPIO_SKL_LP_GPP_F10 0x0205000A +#define GPIO_SKL_LP_GPP_F11 0x0205000B +#define GPIO_SKL_LP_GPP_F12 0x0205000C +#define GPIO_SKL_LP_GPP_F13 0x0205000D +#define GPIO_SKL_LP_GPP_F14 0x0205000E +#define GPIO_SKL_LP_GPP_F15 0x0205000F +#define GPIO_SKL_LP_GPP_F16 0x02050010 +#define GPIO_SKL_LP_GPP_F17 0x02050011 +#define GPIO_SKL_LP_GPP_F18 0x02050012 +#define GPIO_SKL_LP_GPP_F19 0x02050013 +#define GPIO_SKL_LP_GPP_F20 0x02050014 +#define GPIO_SKL_LP_GPP_F21 0x02050015 +#define GPIO_SKL_LP_GPP_F22 0x02050016 +#define GPIO_SKL_LP_GPP_F23 0x02050017 +#define GPIO_SKL_LP_GPP_G0 0x02060000 +#define GPIO_SKL_LP_GPP_G1 0x02060001 +#define GPIO_SKL_LP_GPP_G2 0x02060002 +#define GPIO_SKL_LP_GPP_G3 0x02060003 +#define GPIO_SKL_LP_GPP_G4 0x02060004 +#define GPIO_SKL_LP_GPP_G5 0x02060005 +#define GPIO_SKL_LP_GPP_G6 0x02060006 +#define GPIO_SKL_LP_GPP_G7 0x02060007 +#define GPIO_SKL_LP_GPD0 0x02070000 +#define GPIO_SKL_LP_GPD1 0x02070001 +#define GPIO_SKL_LP_GPD2 0x02070002 +#define GPIO_SKL_LP_GPD3 0x02070003 +#define GPIO_SKL_LP_GPD4 0x02070004 +#define GPIO_SKL_LP_GPD5 0x02070005 +#define GPIO_SKL_LP_GPD6 0x02070006 +#define GPIO_SKL_LP_GPD7 0x02070007 +#define GPIO_SKL_LP_GPD8 0x02070008 +#define GPIO_SKL_LP_GPD9 0x02070009 +#define GPIO_SKL_LP_GPD10 0x0207000A +#define GPIO_SKL_LP_GPD11 0x0207000B + +#define END_OF_GPIO_TABLE 0xFFFFFFFF + +// +//AlderLake S GPIO PCIe SLOT RTD3 and PEG reset pins. +// +#define GPIO_VER4_S_GPP_E2 0x080E0002 +#define GPIO_VER4_S_GPP_E3 0x080E0003 +#define GPIO_VER4_S_GPP_F11 0x0810000B +#define GPIO_VER4_S_GPP_F12 0x0810000C +#define GPIO_VER4_S_GPP_F13 0x0810000D + +//Sample GPIO Table + +// +//AlderLake S Gpio table for assert PCIe SLOT RTD3 and PEG reset pins in early PreMem phase. +// +static GPIO_INIT_CONFIG mAdlSPcieRstPinGpioTable[] = +{ + { GPIO_VER4_S_GPP_E2, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }},// PEG_1 RTD3 Reset + { GPIO_VER4_S_GPP_E3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }},// PEG_2 RTD3 Reset Sinai DR0 (Rework) + { GPIO_VER4_S_GPP_F11, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }},// PCIe SLOT_1 RTD3 Reset MIPI60 (Rework) + { GPIO_VER4_S_GPP_F12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }},// PCIe SLOT_2 RTD3 Reset MIPI60 (Rework) + { GPIO_VER4_S_GPP_F13, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }},// PCIe SLOT_3 RTD3 Reset MIPI60 (Rework) + { 0x0 } // terminator +}; + +static GPIO_INIT_CONFIG mGpioTableLpDdr3Rvp3[] = +{ +//skip for eSPI function {GPIO_SKL_LP_GPP_A0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//H_RCIN_N +//skip for eSPI function {GPIO_SKL_LP_GPP_A1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD0_ESPI_IO0 +//skip for eSPI function {GPIO_SKL_LP_GPP_A2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD1_ESPI_IO1 +//skip for eSPI function {GPIO_SKL_LP_GPP_A3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD2_ESPI_IO2 +//skip for eSPI function {GPIO_SKL_LP_GPP_A4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD3_ESPI_IO3 +//skip for eSPI function {GPIO_SKL_LP_GPP_A5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//LPC_FRAME_ESPI_CS_N +//skip for eSPI function {GPIO_SKL_LP_GPP_A6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//INT_SERIRQ +//skip for eSPI function {GPIO_SKL_LP_GPP_A7, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PM_SLP_S0ix_R_N + {GPIO_SKL_LP_GPP_A8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PM_CLKRUN_N +//skip for eSPI function {GPIO_SKL_LP_GPP_A9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_CLK_ESPI_CLK + {GPIO_SKL_LP_GPP_A10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//PCH_CLK_PCI_TPM + {GPIO_SKL_LP_GPP_A11, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//EC_HID_INTR + {GPIO_SKL_LP_GPP_A12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//M.2_WWAN_GNSS_UART_RST_N + {GPIO_SKL_LP_GPP_A13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SUS_PWR_ACK_R +//skip for eSPI function {GPIO_SKL_LP_GPP_A14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PM_SUS_STAT_ESPI_RST_N + {GPIO_SKL_LP_GPP_A15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SUSACK_R_N + {GPIO_SKL_LP_GPP_A16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_1P8_SEL + {GPIO_SKL_LP_GPP_A17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_PWR_EN_N + {GPIO_SKL_LP_GPP_A18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_GP_0_SENSOR + {GPIO_SKL_LP_GPP_A19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_GP_1_SENSOR + {GPIO_SKL_LP_GPP_A20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_GP_2_SENSOR + {GPIO_SKL_LP_GPP_A21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//GNSS_CHUB_IRQ + {GPIO_SKL_LP_GPP_A22, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//FPS_SLP_N + {GPIO_SKL_LP_GPP_A23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//FPS_DRDY + {GPIO_SKL_LP_GPP_B0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//V0.85A_VID0 + {GPIO_SKL_LP_GPP_B1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//V0.85A_VID1 + {GPIO_SKL_LP_GPP_B2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//GP_VRALERTB + {GPIO_SKL_LP_GPP_B3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioPlatformReset, GpioTermNone}},//TCH_PAD_INTR_R_N + {GPIO_SKL_LP_GPP_B4, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//BT_RF_KILL_N + {GPIO_SKL_LP_GPP_B5, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//M.2_BT_UART_WAKE_N + // {GPIO_SKL_LP_GPP_B6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_SLOT1_N + // {GPIO_SKL_LP_GPP_B7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_SLOT2_LAN_N + // {GPIO_SKL_LP_GPP_B8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_M.2_SSD_SLOT3_N + // {GPIO_SKL_LP_GPP_B9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_M.2_WIGIG_N + // {GPIO_SKL_LP_GPP_B10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_M.2_WLAN_N + {GPIO_SKL_LP_GPP_B11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//MPHY_EXT_PWR_GATEB + {GPIO_SKL_LP_GPP_B12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_SLP_S0_N + {GPIO_SKL_LP_GPP_B13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PLT_RST_N + {GPIO_SKL_LP_GPP_B14, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//TCH_PNL_PWREN + {GPIO_SKL_LP_GPP_B15, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_NFC_DFU + {GPIO_SKL_LP_GPP_B16, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, GpioTermNone}},//M.2_WLAN_WIFI_WAKE_N + {GPIO_SKL_LP_GPP_B17, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntSci, GpioHostDeepReset, GpioTermWpd20K}},//TBT_CIO_PLUG_EVENT_N + {GPIO_SKL_LP_GPP_B18, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, GpioTermWpu20K}},//PCH_SLOT1_WAKE_N + {GPIO_SKL_LP_GPP_B19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//FPS_GSPI1_CS_R1_N + {GPIO_SKL_LP_GPP_B20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//FPS_GSPI1_CLK_R1 + {GPIO_SKL_LP_GPP_B21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//FPS_GSPI1_MISO_R1 + {GPIO_SKL_LP_GPP_B22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//FPS_GSPI1_MOSI_R1 + {GPIO_SKL_LP_GPP_B23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DISCRETE_GNSS_RESET_N + {GPIO_SKL_LP_GPP_C0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SMB_CLK + {GPIO_SKL_LP_GPP_C1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SMB_DATA + {GPIO_SKL_LP_GPP_C2, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SKIN_THRM_SNSR_ALERT_N + {GPIO_SKL_LP_GPP_C3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SML0_CLK + {GPIO_SKL_LP_GPP_C4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SML0_DATA + {GPIO_SKL_LP_GPP_C5, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermWpd20K}},//M.2_WIGIG_WAKE_N + {GPIO_SKL_LP_GPP_C6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SML1_CLK + {GPIO_SKL_LP_GPP_C7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SML1_DATA + {GPIO_SKL_LP_GPP_C8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_RXD + {GPIO_SKL_LP_GPP_C9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_TXD + {GPIO_SKL_LP_GPP_C10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_RTS_N + {GPIO_SKL_LP_GPP_C11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_CTS_N + {GPIO_SKL_LP_GPP_C12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_RXD + {GPIO_SKL_LP_GPP_C13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_TXD + {GPIO_SKL_LP_GPP_C14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_RTS_N + {GPIO_SKL_LP_GPP_C15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_CTS_N + {GPIO_SKL_LP_GPP_C16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C0_SDA + {GPIO_SKL_LP_GPP_C17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C0_SCL + {GPIO_SKL_LP_GPP_C18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C1_SDA + {GPIO_SKL_LP_GPP_C19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C1_SCL + {GPIO_SKL_LP_GPP_C20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_RXD + {GPIO_SKL_LP_GPP_C21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_TXD + {GPIO_SKL_LP_GPP_C22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_RTS_N + {GPIO_SKL_LP_GPP_C23, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_CTS_N + {GPIO_SKL_LP_GPP_D0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_CS_N + {GPIO_SKL_LP_GPP_D1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_CLK + {GPIO_SKL_LP_GPP_D2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_MISO + {GPIO_SKL_LP_GPP_D3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_MOSI + {GPIO_SKL_LP_GPP_D4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CSI2_FLASH_STROBE + {GPIO_SKL_LP_GPP_D5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C0_SDA + {GPIO_SKL_LP_GPP_D6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C0_SCL + {GPIO_SKL_LP_GPP_D7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C1_SDA + {GPIO_SKL_LP_GPP_D8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C1_SCL + {GPIO_SKL_LP_GPP_D9, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//HOME_BTN + {GPIO_SKL_LP_GPP_D10, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SCREEN_LOCK_PCH + {GPIO_SKL_LP_GPP_D11, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//VOL_UP_PCH + {GPIO_SKL_LP_GPP_D12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//VOL_DOWN_PCH + {GPIO_SKL_LP_GPP_D13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_RXD_SML0B_DATA + {GPIO_SKL_LP_GPP_D14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_TXD_SML0B_CLK + {GPIO_SKL_LP_GPP_D15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_RTS_N + {GPIO_SKL_LP_GPP_D16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_CTS_SML0B_ALERT_N + {GPIO_SKL_LP_GPP_D17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DMIC_CLK_1 + {GPIO_SKL_LP_GPP_D18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DMIC_DATA_1 + {GPIO_SKL_LP_GPP_D19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DMIC_CLK_0 + {GPIO_SKL_LP_GPP_D20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DMIC_DATA_0 + {GPIO_SKL_LP_GPP_D21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_IO2 + {GPIO_SKL_LP_GPP_D22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_IO3 + {GPIO_SKL_LP_GPP_D23, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP_MCLK + {GPIO_SKL_LP_GPP_E0, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//SPI_TPM_HDR_IRQ_N + {GPIO_SKL_LP_GPP_E1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SATA_ODD_PRSNT_N + {GPIO_SKL_LP_GPP_E2, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntLvlEdgDis | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//M.2_SSD_SATA2_PCIE3_DET_N + {GPIO_SKL_LP_GPP_E3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone}},//EINK_SSR_DFU_N + {GPIO_SKL_LP_GPP_E4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_NFC_RESET + {GPIO_SKL_LP_GPP_E5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SATA1_PHYSLP1_DIRECT_R + {GPIO_SKL_LP_GPP_E6, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SATA2_PHYSLP2_M.2SSD_R + {GPIO_SKL_LP_GPP_E8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_SATA_LED_N + {GPIO_SKL_LP_GPP_E9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//USB_OC_0_WP1_OTG_N + {GPIO_SKL_LP_GPP_E10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//USB_OC_1_WP4_N + {GPIO_SKL_LP_GPP_E11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//USB_OC_2_WP2_WP3_WP5_R_N + {GPIO_SKL_LP_GPP_E12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_NFC_IRQ + {GPIO_SKL_LP_GPP_E13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI1_HPD_Q + {GPIO_SKL_LP_GPP_E14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI2_HPD_Q + {GPIO_SKL_LP_GPP_E15, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntSmi, GpioHostDeepReset, GpioTermNone}},//SMC_EXTSMI_R_N + {GPIO_SKL_LP_GPP_E16, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, GpioTermNone}},//SMC_RUNTIME_SCI_R_N + {GPIO_SKL_LP_GPP_E17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EDP_HPD + {GPIO_SKL_LP_GPP_E18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI1_CTRL_CLK + {GPIO_SKL_LP_GPP_E19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DDI1_CTRL_DATA + {GPIO_SKL_LP_GPP_E20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI2_CTRL_CLK + {GPIO_SKL_LP_GPP_E21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DDI2_CTRL_DATA + {GPIO_SKL_LP_GPP_E22, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//PCH_CODEC_IRQ + {GPIO_SKL_LP_GPP_E23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//TCH_PNL_RST_N + {GPIO_SKL_LP_GPP_F0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_SCLK + {GPIO_SKL_LP_GPP_F1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_SFRM + {GPIO_SKL_LP_GPP_F2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_TXD + {GPIO_SKL_LP_GPP_F3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_RXD + {GPIO_SKL_LP_GPP_F4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C2_SDA + {GPIO_SKL_LP_GPP_F5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C2_SCL + {GPIO_SKL_LP_GPP_F6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C3_SDA + {GPIO_SKL_LP_GPP_F7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C3_SCL + {GPIO_SKL_LP_GPP_F8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C4_SDA + {GPIO_SKL_LP_GPP_F9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C4_SCL + {GPIO_SKL_LP_GPP_F10, {GpioPadModeNative2, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C5_ISH_12C2_SDA + {GPIO_SKL_LP_GPP_F11, {GpioPadModeNative2, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C5_ISH_12C2_SCL + {GPIO_SKL_LP_GPP_F12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_CMD + {GPIO_SKL_LP_GPP_F13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA0 + {GPIO_SKL_LP_GPP_F14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA1 + {GPIO_SKL_LP_GPP_F15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA2 + {GPIO_SKL_LP_GPP_F16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA3 + {GPIO_SKL_LP_GPP_F17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA4 + {GPIO_SKL_LP_GPP_F18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA5 + {GPIO_SKL_LP_GPP_F19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA6 + {GPIO_SKL_LP_GPP_F20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA7 + {GPIO_SKL_LP_GPP_F21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_RCLK + {GPIO_SKL_LP_GPP_F22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_CLK + {GPIO_SKL_LP_GPP_F23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//PCH_M.2_WWAN_UIM_SIM_DET + {GPIO_SKL_LP_GPP_G0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_CMD + {GPIO_SKL_LP_GPP_G1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA0 + {GPIO_SKL_LP_GPP_G2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA1 + {GPIO_SKL_LP_GPP_G3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA2 + {GPIO_SKL_LP_GPP_G4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA3 + {GPIO_SKL_LP_GPP_G5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_CDB + {GPIO_SKL_LP_GPP_G6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_CLK + {GPIO_SKL_LP_GPP_G7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_WP + {GPIO_SKL_LP_GPD0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//PM_BATLOW_R_N + {GPIO_SKL_LP_GPD1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//AC_PRESENT_R + {GPIO_SKL_LP_GPD2, {GpioPadModeNative1, GpioHostOwnAcpi, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioDswReset, GpioTermNone}},//LANWAKE_SMC_WAKE_SCI_N + {GPIO_SKL_LP_GPD3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermWpu20K}},//PM_PWRBTN_R_N + {GPIO_SKL_LP_GPD4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_S3_R_N + {GPIO_SKL_LP_GPD5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_S4_R_N + {GPIO_SKL_LP_GPD6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_M_R_N + {GPIO_SKL_LP_GPD7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//USB_WAKEOUT_INTRUDET_N + {GPIO_SKL_LP_GPD8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SUS_CLK + {GPIO_SKL_LP_GPD9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//PCH_SLP_WLAN_N + {GPIO_SKL_LP_GPD10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_S5_R_N + {GPIO_SKL_LP_GPD11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//PM_LANPHY_ENABLE + {END_OF_GPIO_TABLE, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//Marking End of Table +}; + +#endif //_GPIO_CONFIG_H_ diff --git a/AlderLakeFspBinPkg/Client/AlderLakeP/Include/HobUsageDataHob.h b/AlderLakeFspBinPkg/Client/AlderLakeP/Include/HobUsageDataHob.h new file mode 100644 index 0000000..195e709 --- /dev/null +++ b/AlderLakeFspBinPkg/Client/AlderLakeP/Include/HobUsageDataHob.h @@ -0,0 +1,35 @@ +/** @file + Definitions for Hob Usage data HOB + +@copyright + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +@par Specification Reference: +**/ + +#ifndef _HOB_USAGE_DATA_HOB_H_ +#define _HOB_USAGE_DATA_HOB_H_ + +extern EFI_GUID gHobUsageDataGuid; + +#pragma pack (push, 1) + +/** + Hob Usage Data Hob + + Revision 1: + - Initial version. +**/ +typedef struct { + EFI_PHYSICAL_ADDRESS EfiMemoryTop; + EFI_PHYSICAL_ADDRESS EfiMemoryBottom; + EFI_PHYSICAL_ADDRESS EfiFreeMemoryTop; + EFI_PHYSICAL_ADDRESS EfiFreeMemoryBottom; + UINTN FreeMemory; +} HOB_USAGE_DATA_HOB; + +#pragma pack (pop) + +#endif // _HOB_USAGE_DATA_HOB_H_ diff --git a/AlderLakeFspBinPkg/Client/AlderLakeP/Include/MemInfoHob.h b/AlderLakeFspBinPkg/Client/AlderLakeP/Include/MemInfoHob.h new file mode 100644 index 0000000..35a5554 --- /dev/null +++ b/AlderLakeFspBinPkg/Client/AlderLakeP/Include/MemInfoHob.h @@ -0,0 +1,315 @@ +/** @file + This file contains definitions required for creation of + Memory S3 Save data, Memory Info data and Memory Platform + data hobs. + +@copyright + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +@par Specification Reference: +**/ +#ifndef _MEM_INFO_HOB_H_ +#define _MEM_INFO_HOB_H_ + + +#pragma pack (push, 1) + +extern EFI_GUID gSiMemoryS3DataGuid; +extern EFI_GUID gSiMemoryInfoDataGuid; +extern EFI_GUID gSiMemoryPlatformDataGuid; + +#define MAX_NODE 2 +#define MAX_CH 4 +#define MAX_DIMM 2 +// Must match definitions in +// Intel\ClientOneSiliconPkg\IpBlock\MemoryInit\Mtl\Include\MrcInterface.h +#define HOB_MAX_SAGV_POINTS 4 + +/// +/// Host reset states from MRC. +/// +#define WARM_BOOT 2 + +#define R_MC_CHNL_RANK_PRESENT 0x7C +#define B_RANK0_PRS BIT0 +#define B_RANK1_PRS BIT1 +#define B_RANK2_PRS BIT4 +#define B_RANK3_PRS BIT5 + +// @todo remove and use the MdePkg\Include\Pi\PiHob.h +#if !defined(_PEI_HOB_H_) && !defined(__PI_HOB_H__) +#ifndef __HOB__H__ +typedef struct _EFI_HOB_GENERIC_HEADER { + UINT16 HobType; + UINT16 HobLength; + UINT32 Reserved; +} EFI_HOB_GENERIC_HEADER; + +typedef struct _EFI_HOB_GUID_TYPE { + EFI_HOB_GENERIC_HEADER Header; + EFI_GUID Name; + /// + /// Guid specific data goes here + /// +} EFI_HOB_GUID_TYPE; +#endif +#endif + +/// +/// Defines taken from MRC so avoid having to include MrcInterface.h +/// + +// +// Matches MAX_SPD_SAVE define in MRC +// +#ifndef MAX_SPD_SAVE +#define MAX_SPD_SAVE 29 +#endif + +// +// MRC version description. +// +typedef struct { + UINT8 Major; ///< Major version number + UINT8 Minor; ///< Minor version number + UINT8 Rev; ///< Revision number + UINT8 Build; ///< Build number +} SiMrcVersion; + +// +// Matches MrcChannelSts enum in MRC +// +#ifndef CHANNEL_NOT_PRESENT +#define CHANNEL_NOT_PRESENT 0 // There is no channel present on the controller. +#endif +#ifndef CHANNEL_DISABLED +#define CHANNEL_DISABLED 1 // There is a channel present but it is disabled. +#endif +#ifndef CHANNEL_PRESENT +#define CHANNEL_PRESENT 2 // There is a channel present and it is enabled. +#endif + +// +// Matches MrcDimmSts enum in MRC +// +#ifndef DIMM_ENABLED +#define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be detected. +#endif +#ifndef DIMM_DISABLED +#define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of presence. +#endif +#ifndef DIMM_PRESENT +#define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pair and it will be used. +#endif +#ifndef DIMM_NOT_PRESENT +#define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank pair. +#endif + +// +// Matches MrcBootMode enum in MRC +// +#ifndef __MRC_BOOT_MODE__ +#define __MRC_BOOT_MODE__ //The below values are originated from MrcCommonTypes.h + #ifndef INT32_MAX + #define INT32_MAX (0x7FFFFFFF) + #endif //INT32_MAX +typedef enum { + bmCold, ///< Cold boot + bmWarm, ///< Warm boot + bmS3, ///< S3 resume + bmFast, ///< Fast boot + MrcBootModeMax, ///< MRC_BOOT_MODE enumeration maximum value. + MrcBootModeDelim = INT32_MAX ///< This value ensures the enum size is consistent on both sides of the PPI. +} MRC_BOOT_MODE; +#endif //__MRC_BOOT_MODE__ + +// +// Matches MrcDdrType enum in MRC +// +#ifndef MRC_DDR_TYPE_DDR5 +#define MRC_DDR_TYPE_DDR5 1 +#endif +#ifndef MRC_DDR_TYPE_LPDDR5 +#define MRC_DDR_TYPE_LPDDR5 2 +#endif +#ifndef MRC_DDR_TYPE_LPDDR4 +#define MRC_DDR_TYPE_LPDDR4 3 +#endif +#ifndef MRC_DDR_TYPE_UNKNOWN +#define MRC_DDR_TYPE_UNKNOWN 4 +#endif + +#define MAX_PROFILE_NUM 7 // number of memory profiles supported +#define MAX_XMP_PROFILE_NUM 5 // number of XMP profiles supported + +#define MAX_TRACE_REGION 5 +#define MAX_TRACE_CACHE_TYPE 2 + +// +// DIMM timings +// +typedef struct { + UINT32 tCK; ///< Memory cycle time, in femtoseconds. + UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's command rate mode. + UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS latency. + UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time. + UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time. + UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time. + UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time. + UINT16 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval. + UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. + UINT16 tRFCpb; ///< Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time. + UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. + UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. + UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks. + UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time. + UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups. + UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups. + UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time. + UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time. + UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time. + UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups. + UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups. + UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group. +} MRC_CH_TIMING; + +typedef struct { + UINT16 tRDPRE; ///< Read CAS to Precharge cmd delay +} MRC_IP_TIMING; + +/// +/// Memory SMBIOS & OC Memory Data Hob +/// +typedef struct { + UINT8 Status; ///< See MrcDimmStatus for the definition of this field. + UINT8 DimmId; + UINT32 DimmCapacity; ///< DIMM size in MBytes. + UINT16 MfgId; + UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes + UINT8 RankInDimm; ///< The number of ranks in this DIMM. + UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation. + UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation. + UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation. + UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation. + UINT16 Speed; ///< The maximum capable speed of the device, in MHz + UINT8 MdSocket; ///< MdSocket: 0 = Memory Down, 1 = Socketed. Needed for SMBIOS structure creation. +} DIMM_INFO; + +typedef struct { + UINT8 Status; ///< Indicates whether this channel should be used. + UINT8 ChannelId; + UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel. + MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values. + DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output characteristics. +} CHANNEL_INFO; + +typedef struct { + UINT8 Status; ///< Indicates whether this controller should be used. + UINT16 DeviceId; ///< The PCI device id of this memory controller. + UINT8 RevisionId; ///< The PCI revision id of this memory controller. + UINT8 ChannelCount; ///< Number of valid channels that exist on the controller. + CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions. +} CONTROLLER_INFO; + +typedef struct { + UINT64 BaseAddress; ///< Trace Base Address + UINT64 TotalSize; ///< Total Trace Region of Same Cache type + UINT8 CacheType; ///< Trace Cache Type + UINT8 ErrorCode; ///< Trace Region Allocation Fail Error code + UINT8 Rsvd[2]; +} PSMI_MEM_INFO; + +/// This data structure contains per-SaGv timing values that are considered output by the MRC. +typedef struct { + UINT32 DataRate; ///< The memory rate for the current SaGv Point in units of MT/s + MRC_CH_TIMING JedecTiming; ///< Timings used for this entry's corresponding SaGv Point - derived from JEDEC SPD spec + MRC_IP_TIMING IpTiming; ///< Timings used for this entry's corresponding SaGv Point - IP specific +} HOB_SAGV_TIMING_OUT; + +/// This data structure contains SAGV config values that are considered output by the MRC. +typedef struct { + UINT32 NumSaGvPointsEnabled; ///< Count of the total number of SAGV Points enabled. + UINT32 SaGvPointMask; ///< Bit mask where each bit indicates an enabled SAGV point. + HOB_SAGV_TIMING_OUT SaGvTiming[HOB_MAX_SAGV_POINTS]; +} HOB_SAGV_INFO; + +typedef struct { + UINT8 Revision; + UINT16 DataWidth; ///< Data width, in bits, of this memory device + /** As defined in SMBIOS 3.0 spec + Section 7.18.2 and Table 75 + **/ + UINT8 MemoryType; ///< DDR type: DDR3, DDR4, or LPDDR3 + UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz) + UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz) + /** As defined in SMBIOS 3.0 spec + Section 7.17.3 and Table 72 + **/ + UINT8 ErrorCorrectionType; + + SiMrcVersion Version; + BOOLEAN EccSupport; + UINT8 MemoryProfile; + UINT8 IsDMBRunning; ///< Deprecated. + UINT32 TotalPhysicalMemorySize; + UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist. + /// + /// Set of bit flags showing XMP and User Profile capability status for the DIMMs detected in system. For each bit, 1 is supported, 0 is unsupported. + /// Bit 0: XMP Profile 1 capability status + /// Bit 1: XMP Profile 2 capability status + /// Bit 2: XMP Profile 3 capability status + /// Bit 3: User Profile 4 capability status + /// Bit 4: User Profile 5 capability status + /// + UINT8 XmpProfileEnable; + UINT8 XmpConfigWarning; ///< If XMP capable DIMMs config support only 1DPC, but 2DPC is installed + UINT8 Ratio; ///< DDR Frequency Ratio, Max Value 255 + UINT8 RefClk; + UINT32 VddVoltage[MAX_PROFILE_NUM]; + UINT32 VddqVoltage[MAX_PROFILE_NUM]; + UINT32 VppVoltage[MAX_PROFILE_NUM]; + CONTROLLER_INFO Controller[MAX_NODE]; + UINT16 Ratio_UINT16; ///< DDR Frequency Ratio, used for programs that require ratios higher then 255 + UINT32 NumPopulatedChannels; ///< Total number of memory channels populated + HOB_SAGV_INFO SagvConfigInfo; ///< This data structure contains SAGV config values that are considered output by the MRC. + UINT16 TotalMemWidth; ///< Total Memory Width in bits from all populated channels + BOOLEAN MemorySpeedReducedWrongDimmSlot; ///< Can be used by OEM BIOS to display a warning on the screen that DDR speed was reduced due to wrong DIMM population + BOOLEAN MemorySpeedReducedMixedConfig; ///< Can be used by OEM BIOS to display a warning on the screen that DDR speed was reduced due to mixed DIMM config + BOOLEAN DynamicMemoryBoostTrainingFailed; ///< TRUE if Dynamic Memory Boost failed to train and was force disabled on the last full training boot. FALSE otherwise. +} MEMORY_INFO_DATA_HOB; + +/** + Memory Platform Data Hob + + Revision 1: + - Initial version. + Revision 2: + - Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddress fields +**/ +typedef struct { + UINT8 Revision; + UINT8 Reserved[3]; + UINT32 BootMode; + UINT32 TsegSize; + UINT32 TsegBase; + UINT32 PrmrrSize; + UINT64 PrmrrBase; + UINT32 GttBase; + UINT32 MmioSize; + UINT32 PciEBaseAddress; + PSMI_MEM_INFO PsmiInfo[MAX_TRACE_CACHE_TYPE]; + PSMI_MEM_INFO PsmiRegionInfo[MAX_TRACE_REGION]; + BOOLEAN MrcBasicMemoryTestPass; +} MEMORY_PLATFORM_DATA; + +typedef struct { + EFI_HOB_GUID_TYPE EfiHobGuidType; + MEMORY_PLATFORM_DATA Data; + UINT8 *Buffer; +} MEMORY_PLATFORM_DATA_HOB; + +#pragma pack (pop) + +#endif // _MEM_INFO_HOB_H_ diff --git a/AlderLakeFspBinPkg/Client/AlderLakeP/Include/SmbiosCacheInfoHob.h b/AlderLakeFspBinPkg/Client/AlderLakeP/Include/SmbiosCacheInfoHob.h new file mode 100644 index 0000000..bfa0d80 --- /dev/null +++ b/AlderLakeFspBinPkg/Client/AlderLakeP/Include/SmbiosCacheInfoHob.h @@ -0,0 +1,47 @@ +/** @file + Header file for SMBIOS Cache Info HOB + +@copyright + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +@par Specification Reference: +**/ + +#ifndef _SMBIOS_CACHE_INFO_HOB_H_ +#define _SMBIOS_CACHE_INFO_HOB_H_ + +#include +#include + +#pragma pack(1) +/// +/// SMBIOS Cache Info HOB Structure +/// +typedef struct { + UINT16 ProcessorSocketNumber; + UINT16 NumberOfCacheLevels; ///< Based on Number of Cache Types L1/L2/L3 + UINT8 SocketDesignationStrIndex; ///< String Index in the string Buffer. Example "L1-CACHE" + UINT16 CacheConfiguration; ///< Format defined in SMBIOS Spec v3.1 Section7.8 Table36 + UINT16 MaxCacheSize; ///< Format defined in SMBIOS Spec v3.1 Section7.8.1 + UINT16 InstalledSize; ///< Format defined in SMBIOS Spec v3.1 Section7.8.1 + UINT16 SupportedSramType; ///< Format defined in SMBIOS Spec v3.1 Section7.8.2 + UINT16 CurrentSramType; ///< Format defined in SMBIOS Spec v3.1 Section7.8.2 + UINT8 CacheSpeed; ///< Cache Speed in nanoseconds. 0 if speed is unknown. + UINT8 ErrorCorrectionType; ///< ENUM Format defined in SMBIOS Spec v3.1 Section 7.8.3 + UINT8 SystemCacheType; ///< ENUM Format defined in SMBIOS Spec v3.1 Section 7.8.4 + UINT8 Associativity; ///< ENUM Format defined in SMBIOS Spec v3.1 Section 7.8.5 + // + // Add for smbios 3.1.0 + // + UINT32 MaximumCacheSize2; ///< Format defined in SMBIOS Spec v3.1 Section7.8.1 + UINT32 InstalledSize2; ///< Format defined in SMBIOS Spec v3.1 Section7.8.1 + /** + String Buffer - each string terminated by NULL "0x00" + String buffer terminated by double NULL "0x0000" + **/ +} SMBIOS_CACHE_INFO; +#pragma pack() + +#endif // _SMBIOS_CACHE_INFO_HOB_H_ diff --git a/AlderLakeFspBinPkg/Client/AlderLakeP/Include/SmbiosProcessorInfoHob.h b/AlderLakeFspBinPkg/Client/AlderLakeP/Include/SmbiosProcessorInfoHob.h new file mode 100644 index 0000000..90c1230 --- /dev/null +++ b/AlderLakeFspBinPkg/Client/AlderLakeP/Include/SmbiosProcessorInfoHob.h @@ -0,0 +1,62 @@ +/** @file + Header file for SMBIOS Processor Info HOB + +@copyright + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +@par Specification Reference: + System Management BIOS (SMBIOS) Reference Specification v3.1.0 + dated 2016-Nov-16 (DSP0134) + http://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.1.0.pdf +**/ + +#ifndef _SMBIOS_PROCESSOR_INFO_HOB_H_ +#define _SMBIOS_PROCESSOR_INFO_HOB_H_ + +#include +#include + +#pragma pack(1) +/// +/// SMBIOS Processor Info HOB Structure +/// +typedef struct { + UINT16 TotalNumberOfSockets; + UINT16 CurrentSocketNumber; + UINT8 ProcessorType; ///< ENUM defined in SMBIOS Spec v3.1 Section 7.5.1 + /** This info is used for both ProcessorFamily and ProcessorFamily2 fields + See ENUM defined in SMBIOS Spec v3.1 Section 7.5.2 + **/ + UINT16 ProcessorFamily; + UINT8 ProcessorManufacturerStrIndex; ///< Index of the String in the String Buffer + UINT64 ProcessorId; ///< ENUM defined in SMBIOS Spec v3.1 Section 7.5.3 + UINT8 ProcessorVersionStrIndex; ///< Index of the String in the String Buffer + UINT8 Voltage; ///< Format defined in SMBIOS Spec v3.1 Section 7.5.4 + UINT16 ExternalClockInMHz; ///< External Clock Frequency. Set to 0 if unknown. + UINT16 MaxSpeedInMHz; ///< Snapshot of Max processor speed during boot + UINT16 CurrentSpeedInMHz; ///< Snapshot of current processor speed during boot + UINT8 Status; ///< Format defined in the SMBIOS Spec v3.1 Table 21 + UINT8 ProcessorUpgrade; ///< ENUM defined in SMBIOS Spec v3.1 Section 7.5.5 + /** This info is used for both CoreCount & CoreCount2 fields + See detailed description in SMBIOS Spec v3.1 Section 7.5.6 + **/ + UINT16 CoreCount; + /** This info is used for both CoreEnabled & CoreEnabled2 fields + See detailed description in SMBIOS Spec v3.1 Section 7.5.7 + **/ + UINT16 EnabledCoreCount; + /** This info is used for both ThreadCount & ThreadCount2 fields + See detailed description in SMBIOS Spec v3.1 Section 7.5.8 + **/ + UINT16 ThreadCount; + UINT16 ProcessorCharacteristics; ///< Format defined in SMBIOS Spec v3.1 Section 7.5.9 + /** + String Buffer - each string terminated by NULL "0x00" + String buffer terminated by double NULL "0x0000" + **/ +} SMBIOS_PROCESSOR_INFO; +#pragma pack() + +#endif // _SMBIOS_PROCESSOR_INFO_HOB_H_ diff --git a/AlderLakeFspBinPkg/Client/AlderLakeP/Library/FspPcdListLib/FspPcdListLibNull.c b/AlderLakeFspBinPkg/Client/AlderLakeP/Library/FspPcdListLib/FspPcdListLibNull.c new file mode 100644 index 0000000..74e7bcb --- /dev/null +++ b/AlderLakeFspBinPkg/Client/AlderLakeP/Library/FspPcdListLib/FspPcdListLibNull.c @@ -0,0 +1,25 @@ +/** @file + Library instance to list all DynamicEx PCD FSP consumes. + No real functionality. + +@copyright + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +@par Specification Reference: +**/ + +#include + +/** + Do nothing function. + +**/ +VOID +FspPcdListLibNull ( + VOID + ) +{ + return; +} diff --git a/AlderLakeFspBinPkg/Client/AlderLakeP/Library/FspPcdListLib/FspPcdListLibNull.inf b/AlderLakeFspBinPkg/Client/AlderLakeP/Library/FspPcdListLib/FspPcdListLibNull.inf new file mode 100644 index 0000000..bce5c98 --- /dev/null +++ b/AlderLakeFspBinPkg/Client/AlderLakeP/Library/FspPcdListLib/FspPcdListLibNull.inf @@ -0,0 +1,61 @@ +## @file +# Library instance to list all DynamicEx PCD FSP consumes. +# +# @copyright +# Copyright (c) 2022, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# @par Specification Reference: +# +## + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = FspPcdListLibNull + FILE_GUID = C5D4D79E-3D5C-4EB6-899E-6F1563CB0B32 + VERSION_STRING = 1.0 + MODULE_TYPE = BASE + LIBRARY_CLASS = NULL +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 IPF EBC +# + +[LibraryClasses] + BaseLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + ClientOneSiliconPkg/SiPkg.dec + +[Sources] + FspPcdListLibNull.c + +[Pcd] + # + # List all the DynamicEx PCDs that FSP will consume. + # FSP Dispatch mode bootloader will include this INF to ensure all the PCDs are + # built into PCD database. + # + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr ## CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr ## CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase ## CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbSize ## CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber ## CONSUMES + gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress ## CONSUMES + gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength ## CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress ## CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize ## CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode ## CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate ## CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdSevEsIsEnabled ## CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiS3Enable ## CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdCpuS3DataAddress ## CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesSetting ## CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceMemSize ## CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceOutputScheme ## CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesCapability ## CONSUMES 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"Value": "64" + }, + { + "Key": "EFP3", + "Value": "32" + }, + { + "Key": "EFP4", + "Value": "16" + }, + { + "Key": "EFP5", + "Value": "2" + }, + { + "Key": "EFP6", + "Value": "1" + }, + { + "Key": "EFP7", + "Value": "256" + }, + { + "Key": "None", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Secondary display: ", + "Visibility": "", + "Data": [ + "253", + "ChildDevice12Secondary" + ], + "HelpText": "Secondary Display", + "WidgetValues": [ + { + "Key": "LFP1", + "Value": "8" + }, + { + "Key": "LFP2", + "Value": "128" + }, + { + "Key": "EFP1", + "Value": "4" + }, + { + "Key": "EFP2", + "Value": "64" + }, + { + "Key": "EFP3", + "Value": "32" + }, + { + "Key": "EFP4", + "Value": "16" + }, + { + "Key": "EFP5", + "Value": "2" + }, + { + "Key": "EFP6", + "Value": "1" + }, + { + "Key": "EFP7", + "Value": "256" + }, + { + "Key": "None", + "Value": "0" + } + ] + }, + { + "WidgetType": "Label", + "WidgetName": "Child Device 13: ", + "Visibility": "", + "Data": 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"EFP7", + "Value": "256" + }, + { + "Key": "None", + "Value": "0" + } + ] + }, + { + "WidgetType": "Label", + "WidgetName": "Child Device 16: ", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Primary display: ", + "Visibility": "", + "Data": [ + "253", + "ChildDevice16Primary" + ], + "HelpText": "Primary Display", + "WidgetValues": [ + { + "Key": "LFP1", + "Value": "8" + }, + { + "Key": "LFP2", + "Value": "128" + }, + { + "Key": "EFP1", + "Value": "4" + }, + { + "Key": "EFP2", + "Value": "64" + }, + { + "Key": "EFP3", + "Value": "32" + }, + { + "Key": "EFP4", + "Value": "16" + }, + { + "Key": "EFP5", + "Value": "2" + }, + { + "Key": "EFP6", + "Value": "1" + }, + { + "Key": "EFP7", + "Value": "256" + }, + { + "Key": "None", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Secondary display: ", + "Visibility": "", + "Data": [ + "253", + "ChildDevice16Secondary" + ], + "HelpText": "Secondary Display", + "WidgetValues": [ + { + "Key": "LFP1", + "Value": "8" + }, + { + "Key": "LFP2", + "Value": "128" + }, + { + "Key": "EFP1", + "Value": "4" + }, + { + "Key": "EFP2", + "Value": "64" + }, + { + "Key": "EFP3", + "Value": "32" + }, + { + "Key": "EFP4", + "Value": "16" + }, + { + "Key": "EFP5", + "Value": "2" + }, + { + "Key": "EFP6", + "Value": "1" + }, + { + "Key": "EFP7", + "Value": "256" + }, + { + "Key": "None", + "Value": "0" + } + ] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "3-2", + "PageName": "Fixed Mode Feature", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Enable Feature: ", + "Visibility": "", + "Data": [ + "51", + "Feature_Enable" + ], + "HelpText": "Fixed Mode Feature allows user to fix a mode during POST such that only that particular mode will be always set.This field specifies if user wants to enable/disable the feature.When enabled user is expected to provide a valid input.", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Pixels: ", + "Visibility": "", + "Data": [ + "51", + "X_res" + ], + "HelpText": "This value specifies the horizontal pixels of the mode.It should be always less than or equal to the native horizontal resolution.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Pixels: ", + "Visibility": "", + "Data": [ + "51", + "Y_res" + ], + "HelpText": "This value specifies the vertical pixels of the mode.It should be always less than or equal to the native vertical resolution.", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + } + ] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "4", + "PageName": "OS Graphics driver Configuration", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "General Features", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Display Features", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Power Conservation", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + } + ], + "NestedPages": [ + { + "Type": "Block", + "Block": { + "PageNum": "4-1", + "PageName": "General Features", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "VBT Customization Version: ", + "Visibility": "", + "Data": [ + "12", + "VBT_Customization_Version" + ], + "HelpText": "This feature allows the OEM to have a customized VBT version number.he permissible values for VBT Customization version is from 0 to 255.", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Display subsystem disabled: ", + "Visibility": "", + "Data": [ + "12", + "Disable_DisplayEnum" + ], + "HelpText": "This option allows windows driver to be aware that display subsystem is not needed.\nDriver could choose not to activate any display hardware if this bit is set.\nHowever this is only valid if there's no LFP on system or no force projectable connector.\nplease check driver documentation for detailed driver behaviour.", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "4-2", + "PageName": "Display Features", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Enable 'Maintain Aspect Ratio': ", + "Visibility": "", + "Data": [ + "12", + "CUI_Maintain_Aspect" + ], + "HelpText": "This feature allows the OEM to enable or disable the 'Maintain Aspect Ratio' feature.\nWhen the option is set to Yes, the feature will be enabled and CUI will show \nfor end user selection 'Maintain Aspect Ratio'. When the option is set to No,\nthe complete 'Maintain Aspect Ratio' feature will be disabled.", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "Label", + "WidgetName": "Legacy Monitor Mode Limit: ", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Maximum X Resolution (Pixels): ", + "Visibility": "", + "Data": [ + "12", + "Legacy_Monitor_Max_X" + ], + "HelpText": "This feature allows the limiting of selectable display modes\nwhen a legacy monitor is detected. The maximum resolution is specified by a maximum number of horizontal active pixels.\nNote: A legacy monitor is defined as a monitor with no DDC available.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Maximum Y Resolution (Pixels): ", + "Visibility": "", + "Data": [ + "12", + "Legacy_Monitor_Max_Y" + ], + "HelpText": "This feature allows the limiting of selectable display modes when a legacy monitor is detected. The maximum resolution is specified by a maximum number of vertical active pixels.\nNote: A legacy monitor is defined as a monitor with no DDC available.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Maximum Refresh Rate (Hz): ", + "Visibility": "", + "Data": [ + "12", + "Legacy_Monitor_Max_RR" + ], + "HelpText": "This feature allows the limiting of selectable display modes when a legacy monitor is detected. The maximum refresh rate is specified in Hz.\nNote: A legacy monitor is defined as a monitor with no DDC available.", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "4-3", + "PageName": "Power Conservation", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " PC Features Control Options: ", + "Visibility": "", + "Data": [ + "12", + "PC_Fields_Enable" + ], + "HelpText": "This feature determines the validity of the following PC Features Control Options.\n\n1. Intel Rapid Memory Power Management (RMPM)\n2. Intel Smart 2D Display Technology (S2DDT)\n3. DxgkDDI Backlight Control (DxgkDdiBLC) (Mobile only)\n4. Graphics Render Standby (RS)\n5. Intel Turbo Boost Technology\n6. Dynamic Frames Per Second (DFPS)\nNote: Enable and Save the changes to display all the PC Features Control Options", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Intel Rapid Memory Power Management (RMPM): ", + "Visibility": "", + "Data": [ + "12", + "PM_RMPM_Enable" + ], + "HelpText": "This feature determines whether Intel Rapid Memory Power Management (RMPM) is to be enabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Intel Smart 2D Display Technology (S2DDT): ", + "Visibility": "", + "Data": [ + "12", + "PM_S2DDT_Enable" + ], + "HelpText": "This feature determines whether Intel Smart 2D Display Technology (S2DDT) is to be enabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " DxgkDDI Brightness Control Method (Mobile only): ", + "Visibility": "", + "Data": [ + "12", + "PM_BLC_Enable" + ], + "HelpText": "This option determines whether the Vista, Win7, and future version DxgkDDI LFP Brightness Control method is to be enabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Graphics Render Standby (RS): ", + "Visibility": "", + "Data": [ + "12", + "PM_RS_Enable" + ], + "HelpText": "This feature determines whether Graphics Render Standby (RS)is to be enabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Intel Turbo Boost Technology: ", + "Visibility": "", + "Data": [ + "12", + "PM_Turbo_Enable" + ], + "HelpText": "This feature determines whether Intel Turbo Boost Technology is to be enabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Dynamic Frames Per Second (DFPS): ", + "Visibility": "", + "Data": [ + "12", + "Dynamic_FPS_Enable" + ], + "HelpText": "This feature determines whether Dynamic Frames Per Second is to be enabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + } + ], + "NestedPages": [ + { + "Type": "Block", + "Block": { + "PageNum": "4-3-1", + "PageName": "ADB Response Data (Mobile only)", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Table", + "WidgetName": "", + "Visibility": "", + "Data": [ + "44", + "ALS_Response_Data" + ], + "HelpText": "This feature defines values used to calibrate the Intel Automatic Display Brightness policy's response to account for specific hardware implementation details such as sensor placement and optics. Up to five points can be specified, where each point indicates a given ambient light illuminance to display luminance mapping specified as (<%BacklightAdjust>, ). Points should be listed in monotonically increasing order by ambient light illuminance (lux). A minimum of two points are required (min and max).", + "WidgetValues": [ + { + "ColumnName": "Backlight Adjust", + "SizeinBytes": "2" + }, + { + "ColumnName": "Lux", + "SizeinBytes": "2" + } + ] + } + ], + "NestedPages": [] + } + } + ] + } + } + ] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5", + "PageName": "Integrated Display Configuration", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Label", + "WidgetName": "Integrated DP, HDMI, DVI, eDP, MIPI Configuration", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Integrated LFP Configuration", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "LFP Panel Configuration", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Integrated DisplayPort/HDMI Configuration", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + } + ], + "NestedPages": [ + { + "Type": "Block", + "Block": { + "PageNum": "5-1", + "PageName": "Integrated LFP Configuration", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Device 1(LFP1) Configuration", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Device 2(LFP2) Configuration", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + } + ], + "NestedPages": [ + { + "Type": "Block", + "Block": { + "PageNum": "5-1-1", + "PageName": "Device 1(LFP1) Configuration", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Active Local Flat Panel Configuration (Save The Configuration After Selecting This Field): ", + "Visibility": "", + "Data": [ + "2", + "LFP_Device_Class" + ], + "HelpText": "This feature is for configuring LFP type. Save the configuration after selecting this field to see display related settings.", + "WidgetValues": [ + { + "Key": "No Local Flat Panel", + "Value": "0" + }, + { + "Key": "eDP(LFP Driven by Int-DisplayPort Encoder)", + "Value": "6150" + }, + { + "Key": "MIPI", + "Value": "5120" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Select Output Port: ", + "Visibility": "", + "Data": [ + "2", + "LFP_Port" + ], + "HelpText": "This feature, when enabled, will activate support for an eDP Driver also uses the same data for enabling eDP on the selected port.\nNote: Do not enable any other digital ports on the same Port as eDP.", + "WidgetValues": [ + { + "Key": "Embedded DisplayPort-A", + "Value": "10" + }, + { + "Key": "Embedded DisplayPort-B", + "Value": "7" + }, + { + "Key": "MIPI DSI-0", + "Value": "21" + }, + { + "Key": "MIPI DSI-1", + "Value": "23" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Select AUX Channel: ", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150", + "Data": [ + "2", + "Int_LFP_AUX_Channel" + ], + "HelpText": "This feature specifies the AUX Channel for embedded-DisplayPort. This field is valid only if integrated eDP is selected for Device Type.", + "WidgetValues": [ + { + "Key": "N/A", + "Value": "0" + }, + { + "Key": "DisplayPort-A AUX Channel", + "Value": "64" + }, + { + "Key": "DisplayPort-B AUX Channel", + "Value": "16" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Select Panel Type: ", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150", + "Data": [ + "40", + "bmp_Panel_type" + ], + "HelpText": "Select the Local Flat Panel (LFP) which display driver will enable.\n\nIf panel type is selected as 0xFF, Graphics Software will populate panel index by comparing actual PNP ID Data from panel to that of PNP ID Data for each panel in VBT.\nThe panel index for which PNP ID Data matches with actual connected panel PNP ID Data is used by driver for all further references. EDID Read is assumed to be enabled if panel index is selected as 0xFF.\nPANEL #01: 640x480 LFP\nPANEL #02: 800x600 LFP\nPANEL #03: 1024x768 LFP\nPANEL #04: 1280x1024 LFP\nPANEL #05: 1400x1050 Reduced Blanking LFP\nPANEL #06: 1400x1050 Non-Reduced Blanking LFP\nPANEL #07: 1600x1200 LFP\nPANEL #08: 1280x768 LFP\nPANEL #09: 1680x1050 LFP\nPANEL #10: 1920x1200 LFP\nPANEL #11: 1440x900 LFP\nPANEL #12: 1600x900 LFP\nPANEL #13: 1024x768 LFP\nPANEL #14: 1280x800 LFP\nPANEL #15: 1920x6108 LFP\nPANEL #16: 2048x1536", + "WidgetValues": [ + { + "Key": "PANEL #01", + "Value": "0" + }, + { + "Key": "PANEL #02", + "Value": "1" + }, + { + "Key": "PANEL #03", + "Value": "2" + }, + { + "Key": "PANEL #04", + "Value": "3" + }, + { + "Key": "PANEL #05", + "Value": "4" + }, + { + "Key": "PANEL #06", + "Value": "5" + }, + { + "Key": "PANEL #07", + "Value": "6" + }, + { + "Key": "PANEL #08", + "Value": "7" + }, + { + "Key": "PANEL #09", + "Value": "8" + }, + { + "Key": "PANEL #10", + "Value": "9" + }, + { + "Key": "PANEL #11", + "Value": "10" + }, + { + "Key": "PANEL #12", + "Value": "11" + }, + { + "Key": "PANEL #13", + "Value": "12" + }, + { + "Key": "PANEL #14", + "Value": "13" + }, + { + "Key": "PANEL #15", + "Value": "14" + }, + { + "Key": "PANEL #16", + "Value": "15" + }, + { + "Key": "PANEL #FF", + "Value": "255" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Select Panel Type: ", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:5120", + "Data": [ + "40", + "bmp_Panel_type" + ], + "HelpText": "Select the Local Flat Panel (LFP) which display driver will enable.\n\nIf panel type is selected as 0xFF, Graphics Software will populate panel index by comparing actual PNP ID Data from panel to that of PNP ID Data for each panel in VBT.\nThe panel index for which PNP ID Data matches with actual connected panel PNP ID Data is used by driver for all further references. EDID Read is assumed to be enabled if panel index is selected as 0xFF.\nPANEL #01: 640x480 LFP\nPANEL #02: 800x600 LFP\nPANEL #03: 1024x768 LFP\nPANEL #04: 1280x1024 LFP\nPANEL #05: 1400x1050 Reduced Blanking LFP\nPANEL #06: 1400x1050 Non-Reduced Blanking LFP", + "WidgetValues": [ + { + "Key": "PANEL #01", + "Value": "0" + }, + { + "Key": "PANEL #02", + "Value": "1" + }, + { + "Key": "PANEL #03", + "Value": "2" + }, + { + "Key": "PANEL #04", + "Value": "3" + }, + { + "Key": "PANEL #05", + "Value": "4" + }, + { + "Key": "PANEL #06", + "Value": "5" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Enable VESA DSC feature: ", + "Visibility": "", + "Data": [ + "2", + "Int_LFP_Compression_Enable" + ], + "HelpText": "This feature when set to yes, will enable VESA DSC compression feature for LFP display.\nFor eDP displays, the field is not used and feature is controlled through panel DPCDs\nFor MIPI displays, the fields is used to enable the feature.\nNote: When enabled, DSC parameters must be configured properly in the DSC parameters page in VBT.", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "DDI Lane Reversal: ", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150", + "Data": [ + "2", + "LFP_Lane_Reversal" + ], + "HelpText": "This feature, when enabled, will set lane reversal bit for Selected Port.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Select eDP Port Max Lane Count Supported: ", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150", + "Data": [ + "2", + "Int_LFP_EDP_DP_Port_Max_LaneCount" + ], + "HelpText": "This feature allows for the selection of the Port Max Lane Count (Port Width) for the EDP/DP link.", + "WidgetValues": [ + { + "Key": "x1", + "Value": "0" + }, + { + "Key": "x2", + "Value": "1" + }, + { + "Key": "x4", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Vswing PreEmphasis Table Override: ", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150", + "Data": [ + "2", + "INT_LFP_Vswing_Override_Enable" + ], + "HelpText": "This feature, when enabled, will allow Graphics driver to use the Vswing and Pre-emphasis values from VBT.\nOEM's must not enable or disable this on their own and work with the Intel CE team to change any settings in this page.\nWhen this field is enabled, corresponding table must be populated in the VBT for PHY Vswing parameters too.", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-1-2", + "PageName": "Device 2(LFP2) Configuration", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Active Local Flat Panel Configuration (Save The Configuration After Selecting This Field): ", + "Visibility": "", + "Data": [ + "2", + "LFP2_Device_Class" + ], + "HelpText": "This feature is for configuring LFP type. Save the configuration after selecting this field to see display related settings.", + "WidgetValues": [ + { + "Key": "No Local Flat Panel", + "Value": "0" + }, + { + "Key": "eDP(LFP Driven by Int-DisplayPort Encoder)", + "Value": "6150" + }, + { + "Key": "MIPI", + "Value": "5120" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Select Output Port: ", + "Visibility": "", + "Data": [ + "2", + "LFP2_Port" + ], + "HelpText": "This feature, when enabled, will activate support for an eDP Driver also uses the same data for enabling eDP on the selected port.\nNote: Do not enable any other digital ports on the same Port as eDP.", + "WidgetValues": [ + { + "Key": "Embedded DisplayPort-A", + "Value": "10" + }, + { + "Key": "Embedded DisplayPort-B", + "Value": "7" + }, + { + "Key": "MIPI DSI-0", + "Value": "21" + }, + { + "Key": "MIPI DSI-1", + "Value": "23" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Select AUX Channel: ", + "Visibility": "Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [ + "2", + "Int_LFP2_AUX_Channel" + ], + "HelpText": "This feature specifies the AUX Channel for embedded-DisplayPort. This field is valid only if integrated eDP is selected for Device Type.", + "WidgetValues": [ + { + "Key": "N/A", + "Value": "0" + }, + { + "Key": "DisplayPort-A AUX Channel", + "Value": "64" + }, + { + "Key": "DisplayPort-B AUX Channel", + "Value": "16" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Select Panel Type: ", + "Visibility": "Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [ + "40", + "bmp_Panel2_type" + ], + "HelpText": "Default LFP parameter values:\nPANEL #01: 640x480 LFP\nPANEL #02: 800x600 LFP\nPANEL #03: 1024x768 LFP\nPANEL #04: 1280x1024 LFP\nPANEL #05: 1400x1050 Reduced Blanking LFP\nPANEL #06: 1400x1050 Non-Reduced Blanking LFP\nPANEL #07: 1600x1200 LFP\nPANEL #08: 1280x768 LFP\nPANEL #09: 1680x1050 LFP\nPANEL #10: 1920x1200 LFP\nPANEL #11: 1440x900 LFP\nPANEL #12: 1600x900 LFP\nPANEL #13: 1024x768 LFP\nPANEL #14: 1280x800 LFP\nPANEL #15: 1920x6108 LFP\nPANEL #16: 2048x1536", + "WidgetValues": [ + { + "Key": "PANEL #01", + "Value": "0" + }, + { + "Key": "PANEL #02", + "Value": "1" + }, + { + "Key": "PANEL #03", + "Value": "2" + }, + { + "Key": "PANEL #04", + "Value": "3" + }, + { + "Key": "PANEL #05", + "Value": "4" + }, + { + "Key": "PANEL #06", + "Value": "5" + }, + { + "Key": "PANEL #07", + "Value": "6" + }, + { + "Key": "PANEL #08", + "Value": "7" + }, + { + "Key": "PANEL #09", + "Value": "8" + }, + { + "Key": "PANEL #10", + "Value": "9" + }, + { + "Key": "PANEL #11", + "Value": "10" + }, + { + "Key": "PANEL #12", + "Value": "11" + }, + { + "Key": "PANEL #13", + "Value": "12" + }, + { + "Key": "PANEL #14", + "Value": "13" + }, + { + "Key": "PANEL #15", + "Value": "14" + }, + { + "Key": "PANEL #16", + "Value": "15" + }, + { + "Key": "PANEL #FF", + "Value": "255" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Select Panel Type: ", + "Visibility": "Block:2, Field:LFP2_Device_Class, Value:5120", + "Data": [ + "40", + "bmp_Panel2_type" + ], + "HelpText": "This feature selects the Local Flat Panel (LFP) the GOP and driver is to enable.\n\nDefault LFP parameter values:\nPANEL #01: 640x480 LFP\nPANEL #02: 800x600 LFP\nPANEL #03: 1024x768 LFP\nPANEL #04: 1280x1024 LFP\nPANEL #05: 1400x1050 Reduced Blanking LFP\nPANEL #06: 1400x1050 Non-Reduced Blanking LFP", + "WidgetValues": [ + { + "Key": "PANEL #01", + "Value": "0" + }, + { + "Key": "PANEL #02", + "Value": "1" + }, + { + "Key": "PANEL #03", + "Value": "2" + }, + { + "Key": "PANEL #04", + "Value": "3" + }, + { + "Key": "PANEL #05", + "Value": "4" + }, + { + "Key": "PANEL #06", + "Value": "5" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Enable VESA DSC feature: ", + "Visibility": "", + "Data": [ + "2", + "Int_LFP2_Compression_Enable" + ], + "HelpText": "This feature when set to yes, will enable VESA DSC compression feature for LFP display.\nFor eDP displays, the field is not used and feature is controlled through panel DPCDs\nFor MIPI displays, the fields is used to enable the feature.\nNote: When enabled, DSC parameters must be configured properly in the DSC parameters page in VBT.", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "DDI Lane Reversal: ", + "Visibility": "Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [ + "2", + "LFP2_Lane_Reversal" + ], + "HelpText": "This feature, when enabled, will set lane reversal bit for Selected Port", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Select eDP Port Max Lane Count Supported: ", + "Visibility": "Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [ + "2", + "Int_LFP2_EDP_DP_Port_Max_LaneCount" + ], + "HelpText": "This feature allows for the selection of the Port Max Lane Count (Port Width) for the EDP/DP link.", + "WidgetValues": [ + { + "Key": "x1", + "Value": "0" + }, + { + "Key": "x2", + "Value": "1" + }, + { + "Key": "x4", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Vswing PreEmphasis Table Override: ", + "Visibility": "Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [ + "2", + "INT_LFP2_Vswing_Override_Enable" + ], + "HelpText": "This feature, when enabled, will allow Graphics driver to use the Vswing and Pre-emphasis values from VBT.\nOEM's must not enable or disable this on their own and work with the Intel CE team to change any settings in this page.\nWhen this field is enabled, corresponding table must be populated in the VBT for PHY Vswing parameters too.", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + } + ], + "NestedPages": [] + } + } + ] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2", + "PageName": "LFP Panel Configuration", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Panel #01", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Panel #02", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Panel #03", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Panel #04", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Panel #05", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Panel #06", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Panel #07", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Panel #08", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Panel #09", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Panel #10", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Panel #11", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Panel #12", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Panel #13", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Panel #14", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Panel #15", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Panel #16", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [], + "HelpText": "", + "WidgetValues": [] + } + ], + "NestedPages": [ + { + "Type": "Block", + "Block": { + "PageNum": "5-2-1", + "PageName": "Panel #01", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "LabelHeading", + "WidgetName": "Common LFP Features", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryAsci", + "WidgetName": " LFP Panel Name: ", + "Visibility": "", + "Data": [ + "42", + "Panel_Name_01" + ], + "HelpText": "This feature defines the LFP panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Target X-Res: ", + "Visibility": "", + "Data": [ + "42", + "Panel_Width_01" + ], + "HelpText": "This value specifies the Target X-Resolution for this panel.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Target Y-Res: ", + "Visibility": "", + "Data": [ + "42", + "Panel_Height_01" + ], + "HelpText": "This value specifies the Target Y-Resolution for this panel.", + "WidgetValues": [] + }, + { + "WidgetType": "LabelHeading", + "WidgetName": " DPS Panel Type Features", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Seamless DRRS Minimum Refresh Rate (Hz): ", + "Visibility": "", + "Data": [ + "42", + "Seamless_DRRS_Min_RR_01" + ], + "HelpText": "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\nNote: Graphics driver will use this field only when EDID support is disabled in VBT configuration.", + "WidgetValues": [] + }, + { + "WidgetType": "LabelHeading", + "WidgetName": " BackLight Technology Type Features", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " BackLight Technology: ", + "Visibility": "", + "Data": [ + "40", + "Blt_Control_01" + ], + "HelpText": "This feature allows OEM to select the Backlight Technology.", + "WidgetValues": [ + { + "Key": "LED Backlight", + "Value": "2" + }, + { + "Key": "CCFL Backlight", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Panel Rotation: ", + "Visibility": "", + "Data": [ + "40", + "Panel_Rotation_01" + ], + "HelpText": "This feature specifies the Panel Rotation of LFP panel used.", + "WidgetValues": [ + { + "Key": "0 degree", + "Value": "0" + }, + { + "Key": "180 degree", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Panel Position: ", + "Visibility": "", + "Data": [ + "40", + "Panel_Position_01" + ], + "HelpText": "This feature specifies the Panel Position of LFP panel used.", + "WidgetValues": [ + { + "Key": "Inside Shell", + "Value": "0" + }, + { + "Key": "Outside Shell", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Dual LFP Port Sync: ", + "Visibility": "", + "Data": [ + "42", + "EnablePortSync_Bit_01" + ], + "HelpText": "This feature will allow users to disable/enable Dual LFP Port Sync and it is applicable for DDI-A, DDI-B in case of eDP and DSI-0, DSI-1 in case of MIPI. \r\n.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " GPU Dithering for Banding artifacts: ", + "Visibility": "", + "Data": [ + "42", + "EnableDithering_Bit_01" + ], + "HelpText": "This field can be used to enable dithering from the source side for reducing banding artifacts on the visual quality features like DPST.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "Button", + "WidgetName": "Power Features", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Generic DTD Timings", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "LFP PnP ID Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Backlight Control Parameters", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Chromaticity Control", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "VESA DSC Parameters", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "LabelHeading", + "WidgetName": "Integrated MIPI DSI Settings", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:5120 or Block:2, Field:LFP2_Device_Class, Value:5120", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "MIPI Display Settings", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:5120 or Block:2, Field:LFP2_Device_Class, Value:5120", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "LabelHeading", + "WidgetName": "Integrated eDP Settings", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "eDP Fast Link Training Configuration Parameters", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "eDP Panel Power Sequencing Parameters", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Edp Max Port Link Rate (in 200 Khz): ", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [ + "27", + "eDP_Max_Port_Link_Rate_01" + ], + "HelpText": "This field specifies EDP Max Port Link Rate supported by the port in unit of 200KHz.\nDefault value would be \"0\", in which case Display Drivers should consider EDP Max Port Link Rate to be the Platform supported Max Link Rate.\nOnly when OEM's need to limit to particular Link Rate can enter the value as mentioned in below table.\n\nNote:\n1) OEM's need to enter the values mentioned from below table only.\n2) If value entered is not matching with any of the below values then Platform supported Max Link Rate should be considere as EDP Max Port Link Rate by the display drivers.\n3) In case of EDP Fast Link Training Params(FLT), if user enters FLT Link Rate value greater than the \"eDP Max Port Link Rate\" then we need to use \n Fast Link training Link Rate = MIN (FLT Link Rate , eDP Max Port Link Rate)\n---------------------------------------------------------\n|\tLink Rate(Gbps)\t|\t Value to enter in text field\t|\n|\t \t\t|\t in terms of 200KHZ \t|\n---------------------------------------------------------\n|\t 1.62 \t\t|\t 8100 \t|\n|\t 2.16 \t\t|\t 10800 \t|\n|\t 2.43 \t\t|\t 12150 \t|\n|\t 2.7 \t\t|\t 13500 \t|\n|\t 3.24 \t\t|\t 16200 \t|\n|\t 3.78 \t\t|\t 18900 \t|\n|\t 4.32 \t\t|\t 21600 \t|\n|\t 5.4 \t\t|\t 27000 \t|\n|\t 6.48 \t\t|\t 32400 \t|\n|\t 6.75 \t\t|\t 33750 \t|\n|\t 8.1 \t\t|\t 40500 \t|\n", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Panel Color Depth: ", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [ + "27", + "eDP_Panel_Color_Depth_01" + ], + "HelpText": "This feature specifies the color depth of eDP panel used.", + "WidgetValues": [ + { + "Key": "18-bit Color Depth", + "Value": "0" + }, + { + "Key": "24-bit Color Depth", + "Value": "1" + }, + { + "Key": "30-bit Color Depth", + "Value": "2" + }, + { + "Key": "36-bit Color Depth", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Select VSwing/Pre-Emphasis table : ", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [ + "27", + "eDP_VswingPreEmph_1" + ], + "HelpText": "This feature selects the VSwing Pre-Emphasis setting table to be used. For Tigerlake, based on the selection respective table will be used.\nTables for Tigerlake:\nLow Power VSwing Pre-Emphasis Setting Table:\nFor HBR2:\n\t\t\t\t\t\t Pre-Emphasis (db)\n\t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\nVoltage \t\t Level-0/200mV \t\t 200mV, 0.0db \t\t 200mV, 1.9db \t\t 200mV, 3.5db \t\t 200mV, 4.9db\nSwing \t\t Level-1/250mV \t\t 250mV, 0.0db \t\t 250mV, 1.6db \t\t 250mV, 2.9db \t\t N/A\n(mV) \t\t Level-2/300mV \t\t 300mV, 0.0db \t\t 300mV, 1.3db \t\t N/A \t\t N/A\n\t\t Level-3/350mV \t\t 350mV, 0.0db \t\t N/A \t\t N/A \t\t N/A\n\n\nFor HBR3:\n\t\t\t\t\t\t Pre-Emphasis (db)\n\t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\nVoltage \t\t Level-0/350mV \t\t 350mV, 0.0db \t\t 350mV, 3.1db \t\t 350mV, 6.0db \t\t 350mV, 8.2db\nSwing \t\t Level-1/500mV \t\t 500mV, 0.0db \t\t 500mV, 2.9db \t\t 500mV, 5.1db \t\t N/A\n(mV) \t\t Level-2/650mV \t\t 650mV, 0.6db \t\t 600mV, 3.5db \t\t N/A \t\t N/A\n\t\t Level-3/900mV \t\t 900mV, 0.0db \t\t N/A \t\t N/A \t\t N/A\n\n\nDefault VSwing Pre-Emphasis Setting Table:\nFor HBR:\n\t\t\t\t\t\t Pre-Emphasis (db)\n\t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\nVoltage \t\t Level-0/350mV \t\t 350mV, 0.0db \t\t 350mV, 3.1db \t\t 350mV, 6.0db \t\t 350mV, 8.2db\nSwing \t\t Level-1/500mV \t\t 500mV, 0.0db \t\t 500mV, 2.9db \t\t 500mV, 5.1db \t\t N/A\n(mV) \t\t Level-2/650mV \t\t 650mV, 0.6db \t\t 600mV, 3.5db \t\t N/A \t\t N/A\n\t\t Level-3/900mV \t\t 900mV, 0.0db \t\t N/A \t\t N/A \t\t N/A\n\n\nFor HBR2:\n\t\t\t\t\t\t Pre-Emphasis (db)\n\t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\nVoltage \t\t Level-0/350mV \t\t 350mV, 0.0db \t\t 350mV, 3.1db \t\t 350mV, 6.0db \t\t 350mV, 8.2db\nSwing \t\t Level-1/500mV \t\t 500mV, 0.0db \t\t 500mV, 2.9db \t\t 500mV, 5.1db \t\t N/A\n(mV) \t\t Level-2/650mV \t\t 650mV, 0.6db \t\t 600mV, 3.5db \t\t N/A \t\t N/A\n\t\t Level-3/900mV \t\t 900mV, 0.0db \t\t N/A \t\t N/A \t\t N/A", + "WidgetValues": [ + { + "Key": "Default VSwing/Pre-Emphasis Table", + "Value": "1" + }, + { + "Key": "Low Power VSwing/Pre-Emphasis Table", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " eDP Spread Spectrum Clock: ", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [ + "40", + "Enable_SSC01" + ], + "HelpText": "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Pixel Overlap Count: ", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [ + "42", + "PixelOverlapCount_01" + ], + "HelpText": "Select the number of Pixels to be overlapped per half of Scanline while using Edp Multi-SST(MSO) feature.", + "WidgetValues": [ + { + "Key": "Zero Pixel Overlap", + "Value": "0" + }, + { + "Key": "One Pixel Overlap", + "Value": "1" + }, + { + "Key": "Two Pixel Overlap", + "Value": "2" + }, + { + "Key": "Three Pixel Overlap", + "Value": "3" + }, + { + "Key": "Four Pixel Overlap", + "Value": "4" + }, + { + "Key": "Five Pixel Overlap", + "Value": "5" + }, + { + "Key": "Six Pixel Overlap", + "Value": "6" + }, + { + "Key": "Seven Pixel Overlap", + "Value": "7" + }, + { + "Key": "Eight Pixel Overlap", + "Value": "8" + } + ] + }, + { + "WidgetType": "Button", + "WidgetName": "PSR Feature", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Apical Feature", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [], + "HelpText": "", + "WidgetValues": [] + } + ], + "NestedPages": [ + { + "Type": "Block", + "Block": { + "PageNum": "5-2-1-1", + "PageName": "eDP Panel Power Sequencing Parameters", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " T3 optimization: ", + "Visibility": "", + "Data": [ + "27", + "eDP_T3_Optimization_01" + ], + "HelpText": "This feature enables or disables T3 optimization.\nWhen enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\nWhen disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "LCDVCC to HPD high delay (T3): ", + "Visibility": "", + "Data": [ + "27", + "eDP_Vcc_To_Hpd_Delay_01" + ], + "HelpText": "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\nValid Range: 0 to 200msec", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Valid video data to Backlight Enable delay (T8): ", + "Visibility": "", + "Data": [ + "27", + "eDP_DataOn_To_BkltEnable_Delay_01" + ], + "HelpText": "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\nT8 is inclusive of T7.\nValid Range of T7: 0 to 50msec", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "PWM-On To Backlight Enable delay: ", + "Visibility": "", + "Data": [ + "27", + "eDP_PwmOn_To_Bklt_Enable_Delay_01" + ], + "HelpText": "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\nDelay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\nSo it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Backlight Disable to PWM-Off delay: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Bklt_Disable_To_PwmOff_Delay_01" + ], + "HelpText": "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\nDelay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\nSo it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Backlight Disable to End of Valid video data delay (T9): ", + "Visibility": "", + "Data": [ + "27", + "eDP_BkltDisable_To_DataOff_Delay_01" + ], + "HelpText": "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "End of Valid video data to Power-Off delay (T10): ", + "Visibility": "", + "Data": [ + "27", + "eDP_DataOff_To_PowerOff_Delay_01" + ], + "HelpText": "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\nValid Range: 0 to 500 msec", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Power-off time (T12): ", + "Visibility": "", + "Data": [ + "27", + "eDP_PowerCycle_Delay_01" + ], + "HelpText": "Using this field Power-off time can be specified in 100uS.", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-1-2", + "PageName": "eDP Fast Link Training Configuration Parameters", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Is FastLinkTraining Feature Supported: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Fast_Link_Training_Supported_01" + ], + "HelpText": "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled.", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Data Rate: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Fast_Link_Training_Data_Rate_01" + ], + "HelpText": "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. It will be used if the sink indicates that no aux handshake is required during link training.\n\nIn case of EDP Fast Link Training Params(FLT), if user enters FLT Link Rate value greater than the \"eDP Max Port Link Rate\" then driver would use \n Fast Link training Link Rate = MIN (FLT Link Rate , eDP Max Port Link Rate).", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Lane Count: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Link_LaneCount_01" + ], + "HelpText": "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. It will be used if the sink indicates that no aux handshake is required during link training.", + "WidgetValues": [ + { + "Key": "x1", + "Value": "0" + }, + { + "Key": "x2", + "Value": "1" + }, + { + "Key": "x4", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Pre-Emphasis: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Link_PreEmp_01" + ], + "HelpText": "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. It will be used if the sink indicates that no aux handshake is required during link training.", + "WidgetValues": [ + { + "Key": "Level-0", + "Value": "0" + }, + { + "Key": "Level-1", + "Value": "1" + }, + { + "Key": "Level-2", + "Value": "2" + }, + { + "Key": "Level-3", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Voltage Swing: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Link_Vswing_01" + ], + "HelpText": "This feature allows for the selection of the Voltage Swing value for the embedded DP link. It will be used if the sink indicates that no aux handshake is required during link training.", + "WidgetValues": [ + { + "Key": "Swing-0", + "Value": "0" + }, + { + "Key": "Swing-1", + "Value": "1" + }, + { + "Key": "Swing-2", + "Value": "2" + }, + { + "Key": "Swing-3", + "Value": "3" + } + ] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-1-3", + "PageName": "PSR Feature", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Full Link enable: ", + "Visibility": "", + "Data": [ + "9", + "PSR_FullLink_Enable_01" + ], + "HelpText": "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state.", + "WidgetValues": [ + { + "Key": "No", + "Value": "0" + }, + { + "Key": "Yes", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Require AUX to wake up: ", + "Visibility": "", + "Data": [ + "9", + "PSR_Require_AUX2Wakeup_01" + ], + "HelpText": "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used.", + "WidgetValues": [ + { + "Key": "No", + "Value": "0" + }, + { + "Key": "Yes", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Lines to wait before link standby: ", + "Visibility": "", + "Data": [ + "9", + "PSR_Lines2Wait_B4LinkS3_01" + ], + "HelpText": "This field determines Lines to wait before link standby\n0 lines to wait (Default)\n1 lines to wait\n4 lines to wait\n8 lines to wait\nOthers Reserved", + "WidgetValues": [ + { + "Key": "0 lines to wait", + "Value": "0" + }, + { + "Key": "1 lines to wait", + "Value": "1" + }, + { + "Key": "4 lines to wait", + "Value": "2" + }, + { + "Key": "8 lines to wait", + "Value": "3" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Idle frames to wait: ", + "Visibility": "", + "Data": [ + "9", + "PSR_IdleFrames2Wait_01" + ], + "HelpText": "Idle frames to wait for PSR enable.\nAllowed values 0-15. Default value is 0.", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Clock Recovery Time: ", + "Visibility": "", + "Data": [ + "9", + "PSR_TP1_WaitTime_01" + ], + "HelpText": "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)", + "WidgetValues": [ + { + "Key": "500 usec", + "Value": "0" + }, + { + "Key": "100 usec", + "Value": "1" + }, + { + "Key": "2.5 msec", + "Value": "2" + }, + { + "Key": "0 (Skip)", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Channel Equalization Time for PSR1 panel: ", + "Visibility": "", + "Data": [ + "9", + "PSR1_TP_2_3_4_WaitTime_01" + ], + "HelpText": "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) or TP4(Training Pattern4) time during PSR1 exit(wake up)", + "WidgetValues": [ + { + "Key": "500 usec", + "Value": "0" + }, + { + "Key": "100 usec", + "Value": "1" + }, + { + "Key": "2.5 msec", + "Value": "2" + }, + { + "Key": "0 (Skip)", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Channel Equalization Time for PSR2 panel: ", + "Visibility": "", + "Data": [ + "9", + "PSR2_TP_2_3_4_WaitTime_01" + ], + "HelpText": "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) or TP4(Training Pattern4) time during PSR2 exit(wake up)", + "WidgetValues": [ + { + "Key": "500 usec", + "Value": "0" + }, + { + "Key": "100 usec", + "Value": "1" + }, + { + "Key": "2.5 msec", + "Value": "2" + }, + { + "Key": "50 usec", + "Value": "3" + } + ] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-1-4", + "PageName": "Apical Feature", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Apical Assertive Display IP: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Apical_Display_Ip_Enable_01" + ], + "HelpText": "This field enables/disables the Apical Assertive Display IP for this panel.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Panel OUI (IEEE OUI): ", + "Visibility": "", + "Data": [ + "27", + "eDP_Panel_Oui_01" + ], + "HelpText": "This field specifies the Apical IP specific Panel OUI field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " DPCD Base Address: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Dpcd_Base_Address_01" + ], + "HelpText": "This field specifies the Apical IP specific DPCD base address field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " DPCD Irdidix Control 0: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Dpcd_Irdidix_Control0_01" + ], + "HelpText": "This field specifies the Apical IP specific DPCD Irdidix control 0 field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " DPCD Option Select: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Dpcd_Option_Select_01" + ], + "HelpText": "This field specifies the Apical IP specific DPCD option select field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " DPCD Backlight: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Dpcd_Backlight_01" + ], + "HelpText": "This field specifies the Apical IP specific backlight value.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Ambient Light: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Ambient_Light_01" + ], + "HelpText": "This field specifies the Apical IP specific Ambient light value.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Backlight scale: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Backlight_Scale_01" + ], + "HelpText": "This field specifies the Apical IP specific backlight scale field.", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-1-5", + "PageName": "Power Features", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Intel Display Power Saving Technology (DPST) (Mobile only): ", + "Visibility": "", + "Data": [ + "44", + "DPST_Enable_01" + ], + "HelpText": "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled.\nIntel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power.\nNote: This technology is only active when the system is running in battery mode and the LFP is the only active display device.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Intel Display Refresh Rate Switching (DRRS) (Mobile only): ", + "Visibility": "", + "Data": [ + "44", + "DRRS_Enable_01" + ], + "HelpText": "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Edge Luminance Profile (ELP) : ", + "Visibility": "", + "Data": [ + "44", + "ELP_Enable_01" + ], + "HelpText": "This feature determines whether the ELP feature is enabled or disabled.\nEdge Luminance Profile (ELP) is a panel technology which reduce luminance on the edge of screen to save panel power.\nNote:This technology cannot co-exist with DPST and OPST ((i.e.) OPST, DPST and ELP cannot exist together.They are all mutually exclusive to each other.)", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " OLED Power Saving Technology (OPST) : ", + "Visibility": "", + "Data": [ + "44", + "OPST_Enable_01" + ], + "HelpText": "This feature determines whether the OPST feature is enabled or disabled.\nOLED Power Saving Technology (OPST) is a panel technology which saves power by intelligent, adaptive dimming of midrange pixel values more aggressively than the extremes without compromising the viewability.\nNote: This technology cannot co-exist with ELP and DPST ((i.e.) OPST, DPST and ELP cannot exist together.They are all mutually exclusive to each other.)", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Dynamic Media Refresh Rate Switching Enable/Disable ", + "Visibility": "", + "Data": [ + "44", + "DMRRS_Enable_01" + ], + "HelpText": "This feature determines whether Dynamic media refresh rate switching is to be enabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Enable Display Lace Support: ", + "Visibility": "", + "Data": [ + "44", + "LACE_Enable_01" + ], + "HelpText": "This feature, when enabled, will set Display Lace Support otherwise, the functionality will be disabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Panel Self Refresh (PSR): ", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [ + "44", + "PSR_Enable_01" + ], + "HelpText": "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Assertive Display Technology Enable/Disable: ", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [ + "44", + "ADT_Enable_01" + ], + "HelpText": "This feature determines whether Assertive display technology is to be enabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Intel Automatic Display Brightness (ADB) (Mobile only): ", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [ + "44", + "ADB_Enable_01" + ], + "HelpText": "This feature determines whether Intel Automatic Display Brightness is to be enabled. Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) depending on the current ambient light environment.\nWhen enabled, the driver and VBIOS will control the backlight brightness of the LFP depending on the ambient environment if and only if the LFP is the only active display. When disabled, the driver will perform no action.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "EDP 4k/2k HOBL Feature: ", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [ + "44", + "eDP_4k_2k_HOBL_feature_Enable_01" + ], + "HelpText": "This feature will allow users to disable/enable the edp 4k/2k HOBL(Hours Of Battery Life) feature by programming relevant registers specific for a platform.\r\n.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Default Display LACE Enabled status: ", + "Visibility": "", + "Data": [ + "44", + "LACE_Status_01" + ], + "HelpText": "This feature, when enabled, will set Default Display LACE Enabled status otherwise, the functionality will be disabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "DPST Aggressiveness Level: ", + "Visibility": "", + "Data": [ + "44", + "DPST_Aggressiveness_Profile_01" + ], + "HelpText": "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n1 (Maximum Quality with No DPST)\n2\n3\n4\n5\n6 (Maximum Battery)", + "WidgetValues": [ + { + "Key": "1 - Maximum Quality with No DPST", + "Value": "1" + }, + { + "Key": "2", + "Value": "2" + }, + { + "Key": "3", + "Value": "3" + }, + { + "Key": "4", + "Value": "4" + }, + { + "Key": "5", + "Value": "5" + }, + { + "Key": "6 - Maximum Battery", + "Value": "6" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "LACE Aggressiveness Level: ", + "Visibility": "", + "Data": [ + "44", + "LACE_Aggressiveness_Profile_01" + ], + "HelpText": "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\nMinimum 0\nModerate 1\nHigh 2", + "WidgetValues": [ + { + "Key": "Minimum", + "Value": "0" + }, + { + "Key": "Moderate", + "Value": "1" + }, + { + "Key": "High", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "ELP Aggressiveness Level: ", + "Visibility": "", + "Data": [ + "44", + "ELP_Aggressiveness_Profile_01" + ], + "HelpText": "This feature allows for the selection of ELP Aggressiveness level for this Panel Type.\nMinimum Power Savings\nMedium Power Savings \nMaximum Power Savings", + "WidgetValues": [ + { + "Key": "Minimum Power Savings", + "Value": "0" + }, + { + "Key": "Medium Power Savings", + "Value": "1" + }, + { + "Key": "Maximum Power Savings", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "OPST Aggressiveness Level: ", + "Visibility": "", + "Data": [ + "44", + "OPST_Aggressiveness_Profile_01" + ], + "HelpText": "This feature allows for the selection of OPST Aggressiveness level for this Panel Type.\nMinimum Power Savings\nMedium Power Savings \nMaximum Power Savings", + "WidgetValues": [ + { + "Key": "Minimum Power Savings", + "Value": "0" + }, + { + "Key": "Medium Power Savings", + "Value": "1" + }, + { + "Key": "Maximum Power Savings", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Default Display VRR Enabled status: ", + "Visibility": "", + "Data": [ + "44", + "VRR_Status_01" + ], + "HelpText": "VRR (Variable Refresh Rate) is a feature that can continuously and seamlessly vary Refresh Rate on the fly, on displays that support Variable Refresh rate Technologies.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-1-6", + "PageName": "Generic DTD Timings", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Pixel Clock in KHz: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_Pixel_CLK_01" + ], + "HelpText": "Pixel Clock (in KHz) Range from 0.001 to 4294967.295 MP/s.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Active: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_Active_01" + ], + "HelpText": "Horizontal Active Image Pixels Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Active: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_Active_01" + ], + "HelpText": "Vertical Active Image Lines Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Blank: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_Blank_01" + ], + "HelpText": "Horizontal Blank Pixels Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Blank: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_Blank_01" + ], + "HelpText": "Vertical Blank lines Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Front Porch: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_FrontPorch_01" + ], + "HelpText": "Horizontal Front Porch Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Front Porch: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_FrontPorch_01" + ], + "HelpText": "Vertical Front Porch Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Sync: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_Sync_01" + ], + "HelpText": "Horizontal Sync Width Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Sync: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_Sync_01" + ], + "HelpText": "Vertical Sync Width Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Image Size: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_Image_Size_01" + ], + "HelpText": "Horizontal Addressable Video Image Size in mm represented by 16bits. Image size multiplier 1.00 mm precision.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Image Size: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_Image_Size_01" + ], + "HelpText": "Vertical Addressable Video Image Size in mm represented by 16bits. Image size multiplier 1.00 mm precision.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryBin", + "WidgetName": "Common Flag: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_Common_Flag_01" + ], + "HelpText": "Common DTD Flags:\nBit 7 : Horizontal Sync Polarity\n1 : Positive\n0 : Negative\nBit 6 : Vertical Sync polarity\n1 : Positive\n0 : Negative\nBit 5 - 0: Reserved (Default value 0)", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-1-7", + "PageName": "LFP PnP ID Table", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Table", + "WidgetName": "", + "Visibility": "", + "Data": [ + "42", + "LFP_Panel_PnP_ID_01" + ], + "HelpText": "This feature allows the 10 bytes of EDID Vendor/Product ID starting at offset 08h to be used as a PnP ID.\n\nTable Definition:\n\tWord: ID Manufacturer Name\n\tWord: ID Product Code\n\tDWord: ID Serial Number\n\tByte: Week of Manufacture\n\tByte: Year of Manufacture", + "WidgetValues": [ + { + "ColumnName": "PnP ID", + "SizeinBytes": "1" + } + ] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-1-8", + "PageName": "Backlight Control Parameters", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Inverter Type: ", + "Visibility": "", + "Data": [ + "43", + "BLC_Inv_Type_01" + ], + "HelpText": "This feature allows for the selection of the Backlight Inverter type that is to be used to control the backlight brightness of the LFP.\nWhen PWM is selected, the driver and VBIOS will control the backlight brightness via the integrated PWM solution for the applicable chipsets.\nWhen None/External is selected, the system BIOS will control the backlight brightness via the external solution.", + "WidgetValues": [ + { + "Key": "None/External", + "Value": "0" + }, + { + "Key": "PWM", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Pwm Source Selection: ", + "Visibility": "", + "Data": [ + "43", + "Lfp_Pwm_Source_Selection_01" + ], + "HelpText": "If panel supports 'Intel HDR AUX Interface', it will always be chosen by default. If not, value in 'PWM Source Selection' will be used", + "WidgetValues": [ + { + "Key": "PWM From Display Engine", + "Value": "2" + }, + { + "Key": "PWM From LCD Panel", + "Value": "3" + }, + { + "Key": "Panel Driver Interface", + "Value": "4" + }, + { + "Key": "VESA eDP AUX Interface", + "Value": "5" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Pwm Controller Selection: ", + "Visibility": "", + "Data": [ + "43", + "Lfp_Pwm_Controller_Selection_01" + ], + "HelpText": "This field allows to select the PWM Controller to be used for the selected Local Flat Panel.This field allows to select the PWM Controller to be used for the selected Local Flat Panel.If Two LFPs are connected then PWM0 and PWM1 must be selected accordingly.", + "WidgetValues": [ + { + "Key": "PWM0", + "Value": "0" + }, + { + "Key": "PWM1", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Inverter Polarity: ", + "Visibility": "", + "Data": [ + "43", + "BLC_Inv_Polarity_01" + ], + "HelpText": "This feature allows the backlight inverter polarity to be specified.\nNormal means 0 value is minimum brightness.\nInverted means 0 value is maximum brightness.", + "WidgetValues": [ + { + "Key": "Normal", + "Value": "0" + }, + { + "Key": "Inverted", + "Value": "1" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Minimum Brightness: ", + "Visibility": "", + "Data": [ + "43", + "Post_Min_Brightness_01" + ], + "HelpText": "This feature allows defining the absolute minimum backlight brightness. The driver will never decrease the backlight less than this value. The value must be specified using normal polarity semantics. The value should range from 0 to 255 if the brightness precision bit is chosen to be 8, and it should range from 0 to 65535 if the precision bit is chosen to be 16.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "POST Backlight Intensity: ", + "Visibility": "", + "Data": [ + "43", + "Post_Brightness_01" + ], + "HelpText": "This feature is used to set default backlight brightness value of the panel at POST. The value should range from 0 to 255 if the bit precision is chosen to be 8 and it should range from 0 to 65535 if the brightness bit precision is chosent to be 16.", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Brightness Precision Bits: ", + "Visibility": "", + "Data": [ + "43", + "BrightnessPrecisionBits_01" + ], + "HelpText": "This field represents the range of brightness in terms of bit precision.\n 8 = Brightness range of 0 to 255.\n 16 = Brightness range of 0 to 65535", + "WidgetValues": [ + { + "Key": "8", + "Value": "8" + }, + { + "Key": "16", + "Value": "16" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "PWM Inverter Frequency (Hz): ", + "Visibility": "", + "Data": [ + "43", + "PWM_Frequency_01" + ], + "HelpText": "This feature allows for the definition of the frequency needed for PWM Inverter.\nNote: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Intel HDR DPCD Refresh Timeout (unit - 10 micro seconds): ", + "Visibility": "", + "Data": [ + "43", + "HdrDpcdRefreshTimeout_01" + ], + "HelpText": "This field allows to configure the refresh timeout of Intel HDR DPCDs for different TCON Vendors.\nNote:\n\tThe value is in units of 10 microseconds.\n\tThe range (entered as a decimal number), for the timeout is 0-65535", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-1-9", + "PageName": "Chromaticity Control", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Chromaticity Control Feature: ", + "Visibility": "", + "Data": [ + "46", + "Chromacity_Enable_01" + ], + "HelpText": "This bit enables Chromaticity feature.\nIf this bit is enabled, EDID values for chromaticity will be used, else feature is disabled.\nFeature will be supported for Panels that support EDID version 1.4 or higher.\nPlease refer to section 3.7 of EDID Specification 1.4.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Override the EDID values: ", + "Visibility": "", + "Data": [ + "46", + "Override_EDID_Data_01" + ], + "HelpText": "This option when enabled along with Chromaticity feature will override EDID values through following VBT data", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Red_Green_bits (Bits 1:0 at 19h): ", + "Visibility": "", + "Data": [ + "46", + "Red_Green_01" + ], + "HelpText": "Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Blue_White_bits (Bits 1:0 at 1Ah): ", + "Visibility": "", + "Data": [ + "46", + "Blue_White_01" + ], + "HelpText": "Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Red_x (Bits 9:2 at 1Bh): ", + "Visibility": "", + "Data": [ + "46", + "Red_x_01" + ], + "HelpText": "Bits 9:2 of red color x coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Red_y (Bits 9:2 at 1Ch): ", + "Visibility": "", + "Data": [ + "46", + "Red_y_01" + ], + "HelpText": "Bits 9:2 of red color y coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Green_x (Bits 9:2 at 1Dh): ", + "Visibility": "", + "Data": [ + "46", + "Green_x_01" + ], + "HelpText": "Bits 9:2 of Green color x coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Green_y (Bits 9:2 at 1Eh): ", + "Visibility": "", + "Data": [ + "46", + "Green_y_01" + ], + "HelpText": "Bits 9:2 of Green color y coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Blue_x (Bits 9:2 at 1Fh): ", + "Visibility": "", + "Data": [ + "46", + "Blue_x_01" + ], + "HelpText": "Bits 9:2 of Blue color x coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Blue_y (Bits 9:2 at 20h): ", + "Visibility": "", + "Data": [ + "46", + "Blue_y_01" + ], + "HelpText": "Bits 9:2 of Blue color y coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " White_x (Bits 9:2 at 21h): ", + "Visibility": "", + "Data": [ + "46", + "White_x_01" + ], + "HelpText": "Bits 9:2 of White color x coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " White_y (Bits 9:2 at 22h): ", + "Visibility": "", + "Data": [ + "46", + "White_y_01" + ], + "HelpText": "Bits 9:2 of White color y coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Override Luminance values ", + "Visibility": "", + "Data": [ + "46", + "Override_LUM_Data_01" + ], + "HelpText": "This option when enabled along with Chromaticity feature will override luminance values following VBT values", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Minimum Luminance: ", + "Visibility": "", + "Data": [ + "46", + "MinLuminance_01" + ], + "HelpText": "Minimum luminance value.\n2 byte value, encoded in IEEE 754 half-precision binary floating point format,", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Maximum full frame luminance: ", + "Visibility": "", + "Data": [ + "46", + "MaxFullLuminance_01" + ], + "HelpText": "Maximum Full frame luminance value.\n2 byte value, encoded in IEEE 754 half-precision binary floating point format,", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Maximum Luminance: ", + "Visibility": "", + "Data": [ + "46", + "MaxLuminance_01" + ], + "HelpText": "Maximum luminance value(Relatively smaller portion of screen).\n2 byte value, encoded in IEEE 754 half-precision binary floating point format.", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Override Gamma values: ", + "Visibility": "", + "Data": [ + "46", + "Override_Gamma_Data_01" + ], + "HelpText": "This option when enabled along with Chromaticity feature will override gamma values through following VBT data", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Panel gamma: ", + "Visibility": "", + "Data": [ + "46", + "Gamma_01" + ], + "HelpText": "Value shall define the gamma range, from 1.00 to 3.54, as follows:\nField Value = (Gamma (value in float) x 100) - 100\nField values range from 00h through FFh.\nFFh = No gamma information shall be provided", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-1-10", + "PageName": "VESA DSC Parameters", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "DSC Major Version: ", + "Visibility": "", + "Data": [ + "56", + "C1_Major_Dsc_Version" + ], + "HelpText": "VESA DSC Major revision field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "DSC Minor Version: ", + "Visibility": "", + "Data": [ + "56", + "C1_Minor_Dsc_Version" + ], + "HelpText": "VESA DSC Minor revision field.", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Block prediction supported: ", + "Visibility": "", + "Data": [ + "56", + "C1_Blk_Prediction_En" + ], + "HelpText": "Sink supports block prediction as per the VESA DSC Spec.", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "RC Buffer Block size as per VESA DSC Spec: ", + "Visibility": "", + "Data": [ + "56", + "C1_RC_Block_Size" + ], + "HelpText": "RC buffer block size for a single RC buffer as defined by the VESA DSC spec.", + "WidgetValues": [ + { + "Key": "1 KB", + "Value": "0" + }, + { + "Key": "4 KB", + "Value": "1" + }, + { + "Key": "16 KB", + "Value": "2" + }, + { + "Key": "64 KB", + "Value": "3" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Number of RC buffer blocks as per VESA DSC Spec: ", + "Visibility": "", + "Data": [ + "56", + "C1_Dsc_RC_Buf_Size" + ], + "HelpText": "This field defines the number of RC buffers as per VESA DSC spec.\nThe number of RC buffers used by the software shall be (Value + 1) where Value is in range 0 to 127.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryBin", + "WidgetName": "Slices per line supported by the sink device: ", + "Visibility": "", + "Data": [ + "56", + "C1_Dsc_Slices_Per_Line" + ], + "HelpText": "This field defines the slices per line supported by the sink device.\nThe field is defined in bitmap fashion and details of each bits are as defined below:\n\tBits 31-10\t\t Bit 9\tBit 8\tBit 7\tBit 6\tBit 5\tBit 4\t Bit 3\t Bit 2\t Bit 1\t Bit 0\n\tReserved\t\t 24\t 20\t 16\t 12\t 10\t 8\t 6\t 4\t 2\t 1\nBit = 0, not supported. Bit = 1, supported\nNote: Assumption is that sink shall support all lower slices per line than maximum selected field. i.e. If it supports say 8 slices per line, it will also support 4/2/1 slices per line", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Line buffer depth as per VESA DSC Spec: ", + "Visibility": "", + "Data": [ + "56", + "C1_Line_Buffer_Depth" + ], + "HelpText": "Line buffer depth in bits as per VESA DSC spec.", + "WidgetValues": [ + { + "Key": "8 bits", + "Value": "0" + }, + { + "Key": "9 bits", + "Value": "1" + }, + { + "Key": "10 bits", + "Value": "2" + }, + { + "Key": "11 bits", + "Value": "3" + }, + { + "Key": "12 bits", + "Value": "4" + }, + { + "Key": "13 bits", + "Value": "5" + }, + { + "Key": "14 bits", + "Value": "6" + }, + { + "Key": "15 bits", + "Value": "7" + }, + { + "Key": "16 bits", + "Value": "8" + } + ] + }, + { + "WidgetType": "EntryBin", + "WidgetName": "Input compression BPC supported by the sink device: ", + "Visibility": "", + "Data": [ + "56", + "C1_Dsc_Bpc" + ], + "HelpText": "This field defines the compression input bpc supported by the sink device.\nThe field is defined in bitmap fashion and details of each bits are as defined below:\n\tBits 7-4\t Bit 3\t Bit 2\t Bit 1\t Bit 0\n\tRsvd\t 12 bpc\t 10bpc\t 8bpc\t Rsvd\nBit = 0, not supported. Bit = 1, supported\nNote: Assumption is that sink shall support all lower bpc values than the maximum selected field. i.e. If it supports say 12bpc, it will also support 10 and 8bpc as well", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Maximum supported compression BPP: ", + "Visibility": "", + "Data": [ + "56", + "C1_Dsc_Max_Bpp" + ], + "HelpText": "As of today, we are supporting 6/8/10/12 BPP for compression output.\nSelect the most appropriate BPP as supported by the sink.", + "WidgetValues": [ + { + "Key": "6 Bits per pixel", + "Value": "0" + }, + { + "Key": "8 Bits per pixel", + "Value": "1" + }, + { + "Key": "10 Bits per pixel", + "Value": "2" + }, + { + "Key": "12 Bits per pixel", + "Value": "3" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Slice height supported by the sink device: ", + "Visibility": "", + "Data": [ + "56", + "C1_Dsc_Slice_Height" + ], + "HelpText": "Slice height supported by the sink device for DSC slice.\nNote: Slice height must divide the picture height uniformly.", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-1-11", + "PageName": "MIPI Display Settings", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:5120 or Block:2, Field:LFP2_Device_Class, Value:5120", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Label", + "WidgetName": "MIPI DSI Controller Configuration Settings", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Video/Command Mode: ", + "Visibility": "", + "Data": [ + "52", + "Video_Command_Mode_01" + ], + "HelpText": "This feature helps in selecting Video/Command Mode.", + "WidgetValues": [ + { + "Key": "Video Mode", + "Value": "0" + }, + { + "Key": "Command Mode", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Packet Sequence For Video Mode: ", + "Visibility": "", + "Data": [ + "52", + "Packet_Sequence_Video_Mode_01" + ], + "HelpText": "This feature helps in selecting packet sequence for Video Mode.\nNon-burst with sync pulse\nNon-burst with sync events\nBurst mode", + "WidgetValues": [ + { + "Key": "Non-burst with sync pulse", + "Value": "1" + }, + { + "Key": "Non-burst with sync events", + "Value": "2" + }, + { + "Key": "Burst Mode", + "Value": "3" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Required Burst Mode Rate (in Kbps): ", + "Visibility": "", + "Data": [ + "52", + "RequiredBurstModeRate_01" + ], + "HelpText": "This feature allows to enter Required Burst Mode Rate in Kilo bits per sec. This should be greater than Non-Burst Mode Rate\nThis value is valid only if packet sequence for video mode is Burst Mode.", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Colour Format In Video Mode: ", + "Visibility": "", + "Data": [ + "52", + "Colour_Format_Video_Mode_01" + ], + "HelpText": "This feature helps in selecting supported colour format in Video Mode.", + "WidgetValues": [ + { + "Key": "RGB565", + "Value": "1" + }, + { + "Key": "RGB666", + "Value": "2" + }, + { + "Key": "RGB 666(Loosely Packed Format)", + "Value": "3" + }, + { + "Key": "RGB888", + "Value": "4" + }, + { + "Key": "RGB101010", + "Value": "5" + }, + { + "Key": "RGB121212", + "Value": "6" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Dual Link Support: ", + "Visibility": "", + "Data": [ + "52", + "Dual_Link_01" + ], + "HelpText": "This feature allows to select type of dual link.", + "WidgetValues": [ + { + "Key": "Dual Link Not Supported", + "Value": "0" + }, + { + "Key": "Dual Link Front Back Mode", + "Value": "1" + }, + { + "Key": "Dual Link Pixel Alternative Mode", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Pixel Overlap Count(Z-Inversion): ", + "Visibility": "", + "Data": [ + "42", + "PixelOverlapCount_01" + ], + "HelpText": "Select the number of Pixels to be overlapped per half of Scanline while using\nMIPI Dual Link Front-Back video mode.", + "WidgetValues": [ + { + "Key": "Zero Pixel Overlap", + "Value": "0" + }, + { + "Key": "One Pixel Overlap", + "Value": "1" + }, + { + "Key": "Two Pixels Overlap", + "Value": "2" + }, + { + "Key": "Three Pixels Overlap", + "Value": "3" + }, + { + "Key": "Four Pixel Overlap", + "Value": "4" + }, + { + "Key": "Five Pixel Overlap", + "Value": "5" + }, + { + "Key": "Six Pixels Overlap", + "Value": "6" + }, + { + "Key": "Seven Pixels Overlap", + "Value": "7" + }, + { + "Key": "Eight Pixel Overlap", + "Value": "8" + }, + { + "Key": "Nine Pixel Overlap", + "Value": "9" + }, + { + "Key": "Ten Pixels Overlap", + "Value": "10" + }, + { + "Key": "Eleven Pixels Overlap", + "Value": "11" + }, + { + "Key": "Twelve Pixel Overlap", + "Value": "12" + }, + { + "Key": "Thirteen Pixels Overlap", + "Value": "13" + }, + { + "Key": "Fourteen Pixels Overlap", + "Value": "14" + }, + { + "Key": "Fifteen Pixels Overlap", + "Value": "15" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " CABC Support: ", + "Visibility": "", + "Data": [ + "52", + "CABC_Support_01" + ], + "HelpText": "This feature helps in selecting CABC_Support.", + "WidgetValues": [ + { + "Key": "Disabled", + "Value": "0" + }, + { + "Key": "Enabled", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " CABC On/Off Commands: ", + "Visibility": "", + "Data": [ + "52", + "CabcCmdsPort_01" + ], + "HelpText": "Select the MIPI Port for sending CABC On/Off Commands in case of Dual link MIPI panels\nThis field is ignored in single link MIPI case", + "WidgetValues": [ + { + "Key": "MIPI DSI-0", + "Value": "0" + }, + { + "Key": "MIPI DSI-1", + "Value": "1" + }, + { + "Key": "Both MIPI DSI-0 and DSI-1", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Panel PWM/BkltController On/Off Commands: ", + "Visibility": "", + "Data": [ + "52", + "PanelPwmCmdsPort_01" + ], + "HelpText": "Select the MIPI Port for sending Panel PWM/BkltController On/Off Commands in case of Dual link MIPI panels\nThis field is ignored in single link MIPI case", + "WidgetValues": [ + { + "Key": "MIPI DSI-0", + "Value": "0" + }, + { + "Key": "MIPI DSI-1", + "Value": "1" + }, + { + "Key": "Both MIPI DSI-0 and DSI-1", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " RGB/BGR Panel Selection: ", + "Visibility": "", + "Data": [ + "52", + "RgbFlip_01" + ], + "HelpText": "Select if the panel is RGB or BGR", + "WidgetValues": [ + { + "Key": "RGB Panel", + "Value": "0" + }, + { + "Key": "BGR Panel", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Number Of Data Lanes: ", + "Visibility": "", + "Data": [ + "52", + "Number_Of_Lanes_01" + ], + "HelpText": "This feature allows to select number of data lanes going to use for MIPI DSI", + "WidgetValues": [ + { + "Key": "1", + "Value": "0" + }, + { + "Key": "2", + "Value": "1" + }, + { + "Key": "3", + "Value": "2" + }, + { + "Key": "4", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Sending Bus Turn Around (BTA): ", + "Visibility": "", + "Data": [ + "52", + "Bta_Disable_01" + ], + "HelpText": "Enable or Disable sending Bus Turn Around to the Peripheral", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "0" + }, + { + "Key": "Disabled", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Escape Clock: ", + "Visibility": "", + "Data": [ + "52", + "EscapeClk_01" + ], + "HelpText": "This feature helps to select frequency of Escape Clk.", + "WidgetValues": [ + { + "Key": "20 MHz", + "Value": "0" + }, + { + "Key": "10 MHz", + "Value": "1" + }, + { + "Key": "5 MHz", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " EoT Packet Transmission: ", + "Visibility": "", + "Data": [ + "52", + "EoTpSupport_01" + ], + "HelpText": "This feature helps to either enable or disable EoT packet Transmission", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "0" + }, + { + "Key": "Disabled", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Clock Stop Feature: ", + "Visibility": "", + "Data": [ + "52", + "ClockStop_01" + ], + "HelpText": "To enable or disable clock stopping feature during BLLP timing in a MIPI DPI (video) mode", + "WidgetValues": [ + { + "Key": "Disabled", + "Value": "0" + }, + { + "Key": "Enabled", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " LP Clock During LPM: ", + "Visibility": "", + "Data": [ + "52", + "LpClockDuringLpm_01" + ], + "HelpText": "In continuous clock mode (Clock Stop Feature disabled), Clock lane will always be in HS mode.\nIf this feature is enabled, Clock lane also goes to LP state once per frame during the mandated data lane LPM\nin MIPI DSI DPI (video) mode", + "WidgetValues": [ + { + "Key": "Disabled", + "Value": "0" + }, + { + "Key": "Enabled", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Blanking During BLLP: ", + "Visibility": "", + "Data": [ + "52", + "BlankingDuringBllp_01" + ], + "HelpText": "This feature helps to send Blanking packets during BLLP regions in a MIPI DSI DPI (video) mode.", + "WidgetValues": [ + { + "Key": "Disabled", + "Value": "0" + }, + { + "Key": "Enabled", + "Value": "1" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " TClkPrepare: ", + "Visibility": "", + "Data": [ + "52", + "TClkPrepare_01" + ], + "HelpText": "This feature allows to enter TClkPrepare in ns.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " TClkTrail: ", + "Visibility": "", + "Data": [ + "52", + "TClkTrail_01" + ], + "HelpText": "This feature allows to enter TClkTrail in ns.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " TClkPrepare + TClkZero: ", + "Visibility": "", + "Data": [ + "52", + "TClkPrepareTClkZero_01" + ], + "HelpText": "This feature allows to enter TClkPrepare + TClkZero in ns.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " THsPrepare: ", + "Visibility": "", + "Data": [ + "52", + "THsPrepare_01" + ], + "HelpText": "This feature allows to enter THsPrepare in ns.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " THsTrail: ", + "Visibility": "", + "Data": [ + "52", + "THsTrail_01" + ], + "HelpText": "This feature allows to enter THsTrail in ns.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " THsPrepare + THsZero: ", + "Visibility": "", + "Data": [ + "52", + "THsPrepareTHsZero_01" + ], + "HelpText": "This feature allows to enter THsPrepare + THsZero in ns.", + "WidgetValues": [] + }, + { + "WidgetType": "Label", + "WidgetName": "MIPI DSI Panel Power On/Off Sequence(delays)", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Power-Up Delay: ", + "Visibility": "", + "Data": [ + "52", + "PowerUpDelay_01" + ], + "HelpText": "Delay to be given after panel power up in 100uS", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Data Turn-On To Panel Backlight Enable Delay: ", + "Visibility": "", + "Data": [ + "52", + "DataTurnOnToPanelBacklightEnableDelay_01" + ], + "HelpText": "Delay to be given after MIPI DATA TURN ON and before backlight enabling in 100uS", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Pwm-On To Backlight Enable Delay: ", + "Visibility": "", + "Data": [ + "52", + "Mipi_PwmOn_To_Bklt_Enable_Delay_01" + ], + "HelpText": "Delay to be given after PWM-On and before Backlight Enable in 100uS\nDelay from PWM-On to Backlight Enable is included in delay from Data Turn-On to Panel Backlight Enable.\nSo it is expected that delay from PWM-On to Backlight Enable is less than the delay from Data Turn-On to Panel Backlight Enable.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Backlight Disable To Pwm-Off Delay: ", + "Visibility": "", + "Data": [ + "52", + "Mipi_Bklt_Disable_To_PwmOff_Delay_01" + ], + "HelpText": "Delay to be given after Backlight Disable and before Pwm-Off in 100uS\nDelay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to Data Turn-Off.\nSo it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to Data Turn-Off.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Backlight Disable To Data Turn-Off Delay: ", + "Visibility": "", + "Data": [ + "52", + "BacklightOffToDataTurnOffDelay_01" + ], + "HelpText": "Delay to be given after Backlight Disable and before MIPI DATA TURN OFF in 100uS", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Power-Down Delay: ", + "Visibility": "", + "Data": [ + "52", + "PowerDownDelay_01" + ], + "HelpText": "Delay to be given before panel power down in 100uS", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Power-Cycle Delay: ", + "Visibility": "", + "Data": [ + "52", + "PowerCycleDelay_01" + ], + "HelpText": "Delay to be given before panel power up and after panel power down in 100uS", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + } + ] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-2", + "PageName": "Panel #02", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "LabelHeading", + "WidgetName": "Common LFP Features", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryAsci", + "WidgetName": " LFP Panel Name: ", + "Visibility": "", + "Data": [ + "42", + "Panel_Name_02" + ], + "HelpText": "This feature defines the LFP panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Target X-Res: ", + "Visibility": "", + "Data": [ + "42", + "Panel_Width_02" + ], + "HelpText": "This value specifies the Target X-Resolution for this panel.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Target Y-Res: ", + "Visibility": "", + "Data": [ + "42", + "Panel_Height_02" + ], + "HelpText": "This value specifies the Target Y-Resolution for this panel.", + "WidgetValues": [] + }, + { + "WidgetType": "LabelHeading", + "WidgetName": " DPS Panel Type Features", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Seamless DRRS Minimum Refresh Rate (Hz): ", + "Visibility": "", + "Data": [ + "42", + "Seamless_DRRS_Min_RR_02" + ], + "HelpText": "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\nNote: Graphics driver will use this field only when EDID support is disabled in VBT configuration.", + "WidgetValues": [] + }, + { + "WidgetType": "LabelHeading", + "WidgetName": " BackLight Technology Type Features", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " BackLight Technology: ", + "Visibility": "", + "Data": [ + "40", + "Blt_Control_02" + ], + "HelpText": "This feature allows OEM to select the Backlight Technology.", + "WidgetValues": [ + { + "Key": "LED Backlight", + "Value": "2" + }, + { + "Key": "CCFL Backlight", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Panel Rotation: ", + "Visibility": "", + "Data": [ + "40", + "Panel_Rotation_02" + ], + "HelpText": "This feature specifies the Panel Rotation of LFP panel used.", + "WidgetValues": [ + { + "Key": "0 degree", + "Value": "0" + }, + { + "Key": "180 degree", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Panel Position: ", + "Visibility": "", + "Data": [ + "40", + "Panel_Position_02" + ], + "HelpText": "This feature specifies the Panel Position of LFP panel used.", + "WidgetValues": [ + { + "Key": "Inside Shell", + "Value": "0" + }, + { + "Key": "Outside Shell", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Dual LFP Port Sync: ", + "Visibility": "", + "Data": [ + "42", + "EnablePortSync_Bit_02" + ], + "HelpText": "This feature will allow users to disable/enable Dual LFP Port Sync and it is applicable for DDI-A, DDI-B in case of eDP and DSI-0, DSI-1 in case of MIPI. \r\n.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " GPU Dithering for Banding artifacts: ", + "Visibility": "", + "Data": [ + "42", + "EnableDithering_Bit_02" + ], + "HelpText": "This field can be used to enable dithering from the source side for reducing banding artifacts on the visual quality features like DPST.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "Button", + "WidgetName": "Power Features", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Generic DTD Timings", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "LFP PnP ID Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Backlight Control Parameters", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Chromaticity Control", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "VESA DSC Parameters", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "LabelHeading", + "WidgetName": "Integrated MIPI DSI Settings", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:5120 or Block:2, Field:LFP2_Device_Class, Value:5120", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "MIPI Display Settings", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:5120 or Block:2, Field:LFP2_Device_Class, Value:5120", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "LabelHeading", + "WidgetName": "Integrated eDP Settings", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "eDP Fast Link Training Configuration Parameters", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "eDP Panel Power Sequencing Parameters", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Edp Max Port Link Rate (in 200 Khz): ", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [ + "27", + "eDP_Max_Port_Link_Rate_02" + ], + "HelpText": "This field specifies EDP Max Port Link Rate supported by the port in unit of 200KHz.\nDefault value would be \"0\", in which case Display Drivers should consider EDP Max Port Link Rate to be the Platform supported Max Link Rate.\nOnly when OEM's need to limit to particular Link Rate can enter the value as mentioned in below table.\n\nNote:\n1) OEM's need to enter the values mentioned from below table only.\n2) If value entered is not matching with any of the below values then Platform supported Max Link Rate should be considere as EDP Max Port Link Rate by the display drivers.\n3) In case of EDP Fast Link Training Params(FLT), if user enters FLT Link Rate value greater than the \"eDP Max Port Link Rate\" then we need to use \n Fast Link training Link Rate = MIN (FLT Link Rate , eDP Max Port Link Rate)\n---------------------------------------------------------\n|\tLink Rate(Gbps)\t|\t Value to enter in text field\t|\n|\t \t\t|\t in terms of 200KHZ \t|\n---------------------------------------------------------\n|\t 1.62 \t\t|\t 8100 \t|\n|\t 2.16 \t\t|\t 10800 \t|\n|\t 2.43 \t\t|\t 12150 \t|\n|\t 2.7 \t\t|\t 13500 \t|\n|\t 3.24 \t\t|\t 16200 \t|\n|\t 3.78 \t\t|\t 18900 \t|\n|\t 4.32 \t\t|\t 21600 \t|\n|\t 5.4 \t\t|\t 27000 \t|\n|\t 6.48 \t\t|\t 32400 \t|\n|\t 6.75 \t\t|\t 33750 \t|\n|\t 8.1 \t\t|\t 40500 \t|\n", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Panel Color Depth: ", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [ + "27", + "eDP_Panel_Color_Depth_02" + ], + "HelpText": "This feature specifies the color depth of eDP panel used.", + "WidgetValues": [ + { + "Key": "18-bit Color Depth", + "Value": "0" + }, + { + "Key": "24-bit Color Depth", + "Value": "1" + }, + { + "Key": "30-bit Color Depth", + "Value": "2" + }, + { + "Key": "36-bit Color Depth", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Select VSwing/Pre-Emphasis table : ", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [ + "27", + "eDP_VswingPreEmph_2" + ], + "HelpText": "This feature selects the VSwing Pre-Emphasis setting table to be used. For Tigerlake, based on the selection respective table will be used.\nTables for Tigerlake:\nLow Power VSwing Pre-Emphasis Setting Table:\nFor HBR2:\n\t\t\t\t\t\t Pre-Emphasis (db)\n\t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\nVoltage \t\t Level-0/200mV \t\t 200mV, 0.0db \t\t 200mV, 1.9db \t\t 200mV, 3.5db \t\t 200mV, 4.9db\nSwing \t\t Level-1/250mV \t\t 250mV, 0.0db \t\t 250mV, 1.6db \t\t 250mV, 2.9db \t\t N/A\n(mV) \t\t Level-2/300mV \t\t 300mV, 0.0db \t\t 300mV, 1.3db \t\t N/A \t\t N/A\n\t\t Level-3/350mV \t\t 350mV, 0.0db \t\t N/A \t\t N/A \t\t N/A\n\n\nFor HBR3:\n\t\t\t\t\t\t Pre-Emphasis (db)\n\t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\nVoltage \t\t Level-0/350mV \t\t 350mV, 0.0db \t\t 350mV, 3.1db \t\t 350mV, 6.0db \t\t 350mV, 8.2db\nSwing \t\t Level-1/500mV \t\t 500mV, 0.0db \t\t 500mV, 2.9db \t\t 500mV, 5.1db \t\t N/A\n(mV) \t\t Level-2/650mV \t\t 650mV, 0.6db \t\t 600mV, 3.5db \t\t N/A \t\t N/A\n\t\t Level-3/900mV \t\t 900mV, 0.0db \t\t N/A \t\t N/A \t\t N/A\n\n\nDefault VSwing Pre-Emphasis Setting Table:\nFor HBR:\n\t\t\t\t\t\t Pre-Emphasis (db)\n\t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\nVoltage \t\t Level-0/350mV \t\t 350mV, 0.0db \t\t 350mV, 3.1db \t\t 350mV, 6.0db \t\t 350mV, 8.2db\nSwing \t\t Level-1/500mV \t\t 500mV, 0.0db \t\t 500mV, 2.9db \t\t 500mV, 5.1db \t\t N/A\n(mV) \t\t Level-2/650mV \t\t 650mV, 0.6db \t\t 600mV, 3.5db \t\t N/A \t\t N/A\n\t\t Level-3/900mV \t\t 900mV, 0.0db \t\t N/A \t\t N/A \t\t N/A\n\n\nFor HBR2:\n\t\t\t\t\t\t Pre-Emphasis (db)\n\t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\nVoltage \t\t Level-0/350mV \t\t 350mV, 0.0db \t\t 350mV, 3.1db \t\t 350mV, 6.0db \t\t 350mV, 8.2db\nSwing \t\t Level-1/500mV \t\t 500mV, 0.0db \t\t 500mV, 2.9db \t\t 500mV, 5.1db \t\t N/A\n(mV) \t\t Level-2/650mV \t\t 650mV, 0.6db \t\t 600mV, 3.5db \t\t N/A \t\t N/A\n\t\t Level-3/900mV \t\t 900mV, 0.0db \t\t N/A \t\t N/A \t\t N/A", + "WidgetValues": [ + { + "Key": "Default VSwing/Pre-Emphasis Table", + "Value": "1" + }, + { + "Key": "Low Power VSwing/Pre-Emphasis Table", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " eDP Spread Spectrum Clock: ", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [ + "40", + "Enable_SSC02" + ], + "HelpText": "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Pixel Overlap Count: ", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [ + "42", + "PixelOverlapCount_02" + ], + "HelpText": "Select the number of Pixels to be overlapped per half of Scanline while using Edp Multi-SST(MSO) feature.", + "WidgetValues": [ + { + "Key": "Zero Pixel Overlap", + "Value": "0" + }, + { + "Key": "One Pixel Overlap", + "Value": "1" + }, + { + "Key": "Two Pixel Overlap", + "Value": "2" + }, + { + "Key": "Three Pixel Overlap", + "Value": "3" + }, + { + "Key": "Four Pixel Overlap", + "Value": "4" + }, + { + "Key": "Five Pixel Overlap", + "Value": "5" + }, + { + "Key": "Six Pixel Overlap", + "Value": "6" + }, + { + "Key": "Seven Pixel Overlap", + "Value": "7" + }, + { + "Key": "Eight Pixel Overlap", + "Value": "8" + } + ] + }, + { + "WidgetType": "Button", + "WidgetName": "PSR Feature", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Apical Feature", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [], + "HelpText": "", + "WidgetValues": [] + } + ], + "NestedPages": [ + { + "Type": "Block", + "Block": { + "PageNum": "5-2-2-1", + "PageName": "eDP Panel Power Sequencing Parameters", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " T3 optimization: ", + "Visibility": "", + "Data": [ + "27", + "eDP_T3_Optimization_02" + ], + "HelpText": "This feature enables or disables T3 optimization.\nWhen enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\nWhen disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "LCDVCC to HPD high delay (T3): ", + "Visibility": "", + "Data": [ + "27", + "eDP_Vcc_To_Hpd_Delay_02" + ], + "HelpText": "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\nValid Range: 0 to 200msec", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Valid video data to Backlight Enable delay (T8): ", + "Visibility": "", + "Data": [ + "27", + "eDP_DataOn_To_BkltEnable_Delay_02" + ], + "HelpText": "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\nT8 is inclusive of T7.\nValid Range of T7: 0 to 50msec", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "PWM-On To Backlight Enable delay: ", + "Visibility": "", + "Data": [ + "27", + "eDP_PwmOn_To_Bklt_Enable_Delay_02" + ], + "HelpText": "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\nDelay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\nSo it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Backlight Disable to PWM-Off delay: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Bklt_Disable_To_PwmOff_Delay_02" + ], + "HelpText": "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\nDelay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\nSo it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Backlight Disable to End of Valid video data delay (T9): ", + "Visibility": "", + "Data": [ + "27", + "eDP_BkltDisable_To_DataOff_Delay_02" + ], + "HelpText": "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "End of Valid video data to Power-Off delay (T10): ", + "Visibility": "", + "Data": [ + "27", + "eDP_DataOff_To_PowerOff_Delay_02" + ], + "HelpText": "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\nValid Range: 0 to 500 msec", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Power-off time (T12): ", + "Visibility": "", + "Data": [ + "27", + "eDP_PowerCycle_Delay_02" + ], + "HelpText": "Using this field Power-off time can be specified in 100uS.", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-2-2", + "PageName": "eDP Fast Link Training Configuration Parameters", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Is FastLinkTraining Feature Supported: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Fast_Link_Training_Supported_02" + ], + "HelpText": "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled.", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Data Rate: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Fast_Link_Training_Data_Rate_02" + ], + "HelpText": "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. It will be used if the sink indicates that no aux handshake is required during link training.\n\nIn case of EDP Fast Link Training Params(FLT), if user enters FLT Link Rate value greater than the \"eDP Max Port Link Rate\" then driver would use \n Fast Link training Link Rate = MIN (FLT Link Rate , eDP Max Port Link Rate).", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Lane Count: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Link_LaneCount_02" + ], + "HelpText": "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. It will be used if the sink indicates that no aux handshake is required during link training.", + "WidgetValues": [ + { + "Key": "x1", + "Value": "0" + }, + { + "Key": "x2", + "Value": "1" + }, + { + "Key": "x4", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Pre-Emphasis: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Link_PreEmp_02" + ], + "HelpText": "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. It will be used if the sink indicates that no aux handshake is required during link training.", + "WidgetValues": [ + { + "Key": "Level-0", + "Value": "0" + }, + { + "Key": "Level-1", + "Value": "1" + }, + { + "Key": "Level-2", + "Value": "2" + }, + { + "Key": "Level-3", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Voltage Swing: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Link_Vswing_02" + ], + "HelpText": "This feature allows for the selection of the Voltage Swing value for the embedded DP link. It will be used if the sink indicates that no aux handshake is required during link training.", + "WidgetValues": [ + { + "Key": "Swing-0", + "Value": "0" + }, + { + "Key": "Swing-1", + "Value": "1" + }, + { + "Key": "Swing-2", + "Value": "2" + }, + { + "Key": "Swing-3", + "Value": "3" + } + ] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-2-3", + "PageName": "PSR Feature", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Full Link enable: ", + "Visibility": "", + "Data": [ + "9", + "PSR_FullLink_Enable_02" + ], + "HelpText": "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state.", + "WidgetValues": [ + { + "Key": "No", + "Value": "0" + }, + { + "Key": "Yes", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Require AUX to wake up: ", + "Visibility": "", + "Data": [ + "9", + "PSR_Require_AUX2Wakeup_02" + ], + "HelpText": "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used.", + "WidgetValues": [ + { + "Key": "No", + "Value": "0" + }, + { + "Key": "Yes", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Lines to wait before link standby: ", + "Visibility": "", + "Data": [ + "9", + "PSR_Lines2Wait_B4LinkS3_02" + ], + "HelpText": "This field determines Lines to wait before link standby\n0 lines to wait (Default)\n1 lines to wait\n4 lines to wait\n8 lines to wait\nOthers Reserved", + "WidgetValues": [ + { + "Key": "0 lines to wait", + "Value": "0" + }, + { + "Key": "1 lines to wait", + "Value": "1" + }, + { + "Key": "4 lines to wait", + "Value": "2" + }, + { + "Key": "8 lines to wait", + "Value": "3" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Idle frames to wait: ", + "Visibility": "", + "Data": [ + "9", + "PSR_IdleFrames2Wait_02" + ], + "HelpText": "Idle frames to wait for PSR enable.\nAllowed values 0-15. Default value is 0.", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Clock Recovery Time: ", + "Visibility": "", + "Data": [ + "9", + "PSR_TP1_WaitTime_02" + ], + "HelpText": "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)", + "WidgetValues": [ + { + "Key": "500 usec", + "Value": "0" + }, + { + "Key": "100 usec", + "Value": "1" + }, + { + "Key": "2.5 msec", + "Value": "2" + }, + { + "Key": "0 (Skip)", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Channel Equalization Time for PSR1 panel: ", + "Visibility": "", + "Data": [ + "9", + "PSR1_TP_2_3_4_WaitTime_02" + ], + "HelpText": "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) or TP4(Training Pattern4) time during PSR1 exit(wake up)", + "WidgetValues": [ + { + "Key": "500 usec", + "Value": "0" + }, + { + "Key": "100 usec", + "Value": "1" + }, + { + "Key": "2.5 msec", + "Value": "2" + }, + { + "Key": "0 (Skip)", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Channel Equalization Time for PSR2 panel: ", + "Visibility": "", + "Data": [ + "9", + "PSR2_TP_2_3_4_WaitTime_02" + ], + "HelpText": "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) or TP4(Training Pattern4) time during PSR2 exit(wake up)", + "WidgetValues": [ + { + "Key": "500 usec", + "Value": "0" + }, + { + "Key": "100 usec", + "Value": "1" + }, + { + "Key": "2.5 msec", + "Value": "2" + }, + { + "Key": "50 usec", + "Value": "3" + } + ] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-2-4", + "PageName": "Apical Feature", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Apical Assertive Display IP: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Apical_Display_Ip_Enable_02" + ], + "HelpText": "This field enables/disables the Apical Assertive Display IP for this panel.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Panel OUI (IEEE OUI): ", + "Visibility": "", + "Data": [ + "27", + "eDP_Panel_Oui_02" + ], + "HelpText": "This field specifies the Apical IP specific Panel OUI field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " DPCD Base Address: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Dpcd_Base_Address_02" + ], + "HelpText": "This field specifies the Apical IP specific DPCD base address field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " DPCD Irdidix Control 0: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Dpcd_Irdidix_Control0_02" + ], + "HelpText": "This field specifies the Apical IP specific DPCD Irdidix control 0 field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " DPCD Option Select: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Dpcd_Option_Select_02" + ], + "HelpText": "This field specifies the Apical IP specific DPCD option select field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " DPCD Backlight: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Dpcd_Backlight_02" + ], + "HelpText": "This field specifies the Apical IP specific backlight value.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Ambient Light: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Ambient_Light_02" + ], + "HelpText": "This field specifies the Apical IP specific Ambient light value.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Backlight scale: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Backlight_Scale_02" + ], + "HelpText": "This field specifies the Apical IP specific backlight scale field.", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-2-5", + "PageName": "Power Features", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Intel Display Power Saving Technology (DPST) (Mobile only): ", + "Visibility": "", + "Data": [ + "44", + "DPST_Enable_02" + ], + "HelpText": "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled.\nIntel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power.\nNote: This technology is only active when the system is running in battery mode and the LFP is the only active display device.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Intel Display Refresh Rate Switching (DRRS) (Mobile only): ", + "Visibility": "", + "Data": [ + "44", + "DRRS_Enable_02" + ], + "HelpText": "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Edge Luminance Profile (ELP) : ", + "Visibility": "", + "Data": [ + "44", + "ELP_Enable_02" + ], + "HelpText": "This feature determines whether the ELP feature is enabled or disabled.\nEdge Luminance Profile (ELP) is a panel technology which reduce luminance on the edge of screen to save panel power.\nNote:This technology cannot co-exist with DPST and OPST ((i.e.) OPST, DPST and ELP cannot exist together.They are all mutually exclusive to each other.)", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " OLED Power Saving Technology (OPST) : ", + "Visibility": "", + "Data": [ + "44", + "OPST_Enable_02" + ], + "HelpText": "This feature determines whether the OPST feature is enabled or disabled.\nOLED Power Saving Technology (OPST) is a panel technology which saves power by intelligent, adaptive dimming of midrange pixel values more aggressively than the extremes without compromising the viewability.\nNote: This technology cannot co-exist with ELP and DPST ((i.e.) OPST, DPST and ELP cannot exist together.They are all mutually exclusive to each other.)", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Dynamic Media Refresh Rate Switching Enable/Disable ", + "Visibility": "", + "Data": [ + "44", + "DMRRS_Enable_02" + ], + "HelpText": "This feature determines whether Dynamic media refresh rate switching is to be enabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Enable Display Lace Support: ", + "Visibility": "", + "Data": [ + "44", + "LACE_Enable_02" + ], + "HelpText": "This feature, when enabled, will set Display Lace Support otherwise, the functionality will be disabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Panel Self Refresh (PSR): ", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [ + "44", + "PSR_Enable_02" + ], + "HelpText": "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Assertive Display Technology Enable/Disable: ", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [ + "44", + "ADT_Enable_02" + ], + "HelpText": "This feature determines whether Assertive display technology is to be enabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Intel Automatic Display Brightness (ADB) (Mobile only): ", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [ + "44", + "ADB_Enable_02" + ], + "HelpText": "This feature determines whether Intel Automatic Display Brightness is to be enabled. Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) depending on the current ambient light environment.\nWhen enabled, the driver and VBIOS will control the backlight brightness of the LFP depending on the ambient environment if and only if the LFP is the only active display. When disabled, the driver will perform no action.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "EDP 4k/2k HOBL Feature: ", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [ + "44", + "eDP_4k_2k_HOBL_feature_Enable_02" + ], + "HelpText": "This feature will allow users to disable/enable the edp 4k/2k HOBL(Hours Of Battery Life) feature by programming relevant registers specific for a platform.\r\n.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Default Display LACE Enabled status: ", + "Visibility": "", + "Data": [ + "44", + "LACE_Status_02" + ], + "HelpText": "This feature, when enabled, will set Default Display LACE Enabled status otherwise, the functionality will be disabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "DPST Aggressiveness Level: ", + "Visibility": "", + "Data": [ + "44", + "DPST_Aggressiveness_Profile_02" + ], + "HelpText": "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n1 (Maximum Quality with No DPST)\n2\n3\n4\n5\n6 (Maximum Battery)", + "WidgetValues": [ + { + "Key": "1 - Maximum Quality with No DPST", + "Value": "1" + }, + { + "Key": "2", + "Value": "2" + }, + { + "Key": "3", + "Value": "3" + }, + { + "Key": "4", + "Value": "4" + }, + { + "Key": "5", + "Value": "5" + }, + { + "Key": "6 - Maximum Battery", + "Value": "6" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "LACE Aggressiveness Level: ", + "Visibility": "", + "Data": [ + "44", + "LACE_Aggressiveness_Profile_02" + ], + "HelpText": "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\nMinimum 0\nModerate 1\nHigh 2", + "WidgetValues": [ + { + "Key": "Minimum", + "Value": "0" + }, + { + "Key": "Moderate", + "Value": "1" + }, + { + "Key": "High", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "ELP Aggressiveness Level: ", + "Visibility": "", + "Data": [ + "44", + "ELP_Aggressiveness_Profile_02" + ], + "HelpText": "This feature allows for the selection of ELP Aggressiveness level for this Panel Type.\nMinimum Power Savings\nMedium Power Savings \nMaximum Power Savings", + "WidgetValues": [ + { + "Key": "Minimum Power Savings", + "Value": "0" + }, + { + "Key": "Medium Power Savings", + "Value": "1" + }, + { + "Key": "Maximum Power Savings", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "OPST Aggressiveness Level: ", + "Visibility": "", + "Data": [ + "44", + "OPST_Aggressiveness_Profile_02" + ], + "HelpText": "This feature allows for the selection of OPST Aggressiveness level for this Panel Type.\nMinimum Power Savings\nMedium Power Savings \nMaximum Power Savings", + "WidgetValues": [ + { + "Key": "Minimum Power Savings", + "Value": "0" + }, + { + "Key": "Medium Power Savings", + "Value": "1" + }, + { + "Key": "Maximum Power Savings", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Default Display VRR Enabled status: ", + "Visibility": "", + "Data": [ + "44", + "VRR_Status_02" + ], + "HelpText": "VRR (Variable Refresh Rate) is a feature that can continuously and seamlessly vary Refresh Rate on the fly, on displays that support Variable Refresh rate Technologies.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-2-6", + "PageName": "Generic DTD Timings", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Pixel Clock in KHz: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_Pixel_CLK_02" + ], + "HelpText": "Pixel Clock (in KHz) Range from 0.001 to 4294967.295 MP/s.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Active: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_Active_02" + ], + "HelpText": "Horizontal Active Image Pixels Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Active: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_Active_02" + ], + "HelpText": "Vertical Active Image Lines Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Blank: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_Blank_02" + ], + "HelpText": "Horizontal Blank Pixels Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Blank: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_Blank_02" + ], + "HelpText": "Vertical Blank lines Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Front Porch: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_FrontPorch_02" + ], + "HelpText": "Horizontal Front Porch Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Front Porch: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_FrontPorch_02" + ], + "HelpText": "Vertical Front Porch Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Sync: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_Sync_02" + ], + "HelpText": "Horizontal Sync Width Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Sync: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_Sync_02" + ], + "HelpText": "Vertical Sync Width Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Image Size: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_Image_Size_02" + ], + "HelpText": "Horizontal Addressable Video Image Size in mm represented by 16bits. Image size multiplier 1.00 mm precision.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Image Size: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_Image_Size_02" + ], + "HelpText": "Vertical Addressable Video Image Size in mm represented by 16bits. Image size multiplier 1.00 mm precision.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryBin", + "WidgetName": "Common Flag: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_Common_Flag_02" + ], + "HelpText": "Common DTD Flags:\nBit 7 : Horizontal Sync Polarity\n1 : Positive\n0 : Negative\nBit 6 : Vertical Sync polarity\n1 : Positive\n0 : Negative\nBit 5 - 0: Reserved (Default value 0)", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-2-7", + "PageName": "LFP PnP ID Table", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Table", + "WidgetName": "", + "Visibility": "", + "Data": [ + "42", + "LFP_Panel_PnP_ID_02" + ], + "HelpText": "This feature allows the 10 bytes of EDID Vendor/Product ID starting at offset 08h to be used as a PnP ID.\n\nTable Definition:\n\tWord: ID Manufacturer Name\n\tWord: ID Product Code\n\tDWord: ID Serial Number\n\tByte: Week of Manufacture\n\tByte: Year of Manufacture", + "WidgetValues": [ + { + "ColumnName": "PnP ID", + "SizeinBytes": "1" + } + ] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-2-8", + "PageName": "Backlight Control Parameters", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Inverter Type: ", + "Visibility": "", + "Data": [ + "43", + "BLC_Inv_Type_02" + ], + "HelpText": "This feature allows for the selection of the Backlight Inverter type that is to be used to control the backlight brightness of the LFP.\nWhen PWM is selected, the driver and VBIOS will control the backlight brightness via the integrated PWM solution for the applicable chipsets.\nWhen None/External is selected, the system BIOS will control the backlight brightness via the external solution.", + "WidgetValues": [ + { + "Key": "None/External", + "Value": "0" + }, + { + "Key": "PWM", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Pwm Source Selection: ", + "Visibility": "", + "Data": [ + "43", + "Lfp_Pwm_Source_Selection_02" + ], + "HelpText": "If panel supports 'Intel HDR AUX Interface', it will always be chosen by default. If not, value in 'PWM Source Selection' will be used", + "WidgetValues": [ + { + "Key": "PWM From Display Engine", + "Value": "2" + }, + { + "Key": "PWM From LCD Panel", + "Value": "3" + }, + { + "Key": "Panel Driver Interface", + "Value": "4" + }, + { + "Key": "VESA eDP AUX Interface", + "Value": "5" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Pwm Controller Selection: ", + "Visibility": "", + "Data": [ + "43", + "Lfp_Pwm_Controller_Selection_02" + ], + "HelpText": "This field allows to select the PWM Controller to be used for the selected Local Flat Panel.This field allows to select the PWM Controller to be used for the selected Local Flat Panel.If Two LFPs are connected then PWM0 and PWM1 must be selected accordingly.", + "WidgetValues": [ + { + "Key": "PWM0", + "Value": "0" + }, + { + "Key": "PWM1", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Inverter Polarity: ", + "Visibility": "", + "Data": [ + "43", + "BLC_Inv_Polarity_02" + ], + "HelpText": "This feature allows the backlight inverter polarity to be specified.\nNormal means 0 value is minimum brightness.\nInverted means 0 value is maximum brightness.", + "WidgetValues": [ + { + "Key": "Normal", + "Value": "0" + }, + { + "Key": "Inverted", + "Value": "1" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Minimum Brightness: ", + "Visibility": "", + "Data": [ + "43", + "Post_Min_Brightness_02" + ], + "HelpText": "This feature allows defining the absolute minimum backlight brightness. The driver will never decrease the backlight less than this value. The value must be specified using normal polarity semantics. The value should range from 0 to 255 if the brightness precision bit is chosen to be 8, and it should range from 0 to 65535 if the precision bit is chosen to be 16.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "POST Backlight Intensity: ", + "Visibility": "", + "Data": [ + "43", + "Post_Brightness_02" + ], + "HelpText": "This feature is used to set default backlight brightness value of the panel at POST. The value should range from 0 to 255 if the bit precision is chosen to be 8 and it should range from 0 to 65535 if the brightness bit precision is chosent to be 16.", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Brightness Precision Bits: ", + "Visibility": "", + "Data": [ + "43", + "BrightnessPrecisionBits_02" + ], + "HelpText": "This field represents the range of brightness in terms of bit precision.\n 8 = Brightness range of 0 to 255.\n 16 = Brightness range of 0 to 65535", + "WidgetValues": [ + { + "Key": "8", + "Value": "8" + }, + { + "Key": "16", + "Value": "16" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "PWM Inverter Frequency (Hz): ", + "Visibility": "", + "Data": [ + "43", + "PWM_Frequency_02" + ], + "HelpText": "This feature allows for the definition of the frequency needed for PWM Inverter.\nNote: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Intel HDR DPCD Refresh Timeout (unit - 10 micro seconds): ", + "Visibility": "", + "Data": [ + "43", + "HdrDpcdRefreshTimeout_02" + ], + "HelpText": "This field allows to configure the refresh timeout of Intel HDR DPCDs for different TCON Vendors.\nNote:\n\tThe value is in units of 10 microseconds.\n\tThe range (entered as a decimal number), for the timeout is 0-65535", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-2-9", + "PageName": "Chromaticity Control", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Chromaticity Control Feature: ", + "Visibility": "", + "Data": [ + "46", + "Chromacity_Enable_02" + ], + "HelpText": "This bit enables Chromaticity feature.\nIf this bit is enabled, EDID values for chromaticity will be used, else feature is disabled.\nFeature will be supported for Panels that support EDID version 1.4 or higher.\nPlease refer to section 3.7 of EDID Specification 1.4.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Override the EDID values: ", + "Visibility": "", + "Data": [ + "46", + "Override_EDID_Data_02" + ], + "HelpText": "This option when enabled along with Chromaticity feature will override EDID values through following VBT data", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Red_Green_bits (Bits 1:0 at 19h): ", + "Visibility": "", + "Data": [ + "46", + "Red_Green_02" + ], + "HelpText": "Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Blue_White_bits (Bits 1:0 at 1Ah): ", + "Visibility": "", + "Data": [ + "46", + "Blue_White_02" + ], + "HelpText": "Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Red_x (Bits 9:2 at 1Bh): ", + "Visibility": "", + "Data": [ + "46", + "Red_x_02" + ], + "HelpText": "Bits 9:2 of red color x coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Red_y (Bits 9:2 at 1Ch): ", + "Visibility": "", + "Data": [ + "46", + "Red_y_02" + ], + "HelpText": "Bits 9:2 of red color y coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Green_x (Bits 9:2 at 1Dh): ", + "Visibility": "", + "Data": [ + "46", + "Green_x_02" + ], + "HelpText": "Bits 9:2 of Green color x coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Green_y (Bits 9:2 at 1Eh): ", + "Visibility": "", + "Data": [ + "46", + "Green_y_02" + ], + "HelpText": "Bits 9:2 of Green color y coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Blue_x (Bits 9:2 at 1Fh): ", + "Visibility": "", + "Data": [ + "46", + "Blue_x_02" + ], + "HelpText": "Bits 9:2 of Blue color x coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Blue_y (Bits 9:2 at 20h): ", + "Visibility": "", + "Data": [ + "46", + "Blue_y_02" + ], + "HelpText": "Bits 9:2 of Blue color y coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " White_x (Bits 9:2 at 21h): ", + "Visibility": "", + "Data": [ + "46", + "White_x_02" + ], + "HelpText": "Bits 9:2 of White color x coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " White_y (Bits 9:2 at 22h): ", + "Visibility": "", + "Data": [ + "46", + "White_y_02" + ], + "HelpText": "Bits 9:2 of White color y coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Override Luminance values ", + "Visibility": "", + "Data": [ + "46", + "Override_LUM_Data_02" + ], + "HelpText": "This option when enabled along with Chromaticity feature will override luminance values following VBT values", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Minimum Luminance: ", + "Visibility": "", + "Data": [ + "46", + "MinLuminance_02" + ], + "HelpText": "Minimum luminance value.\n2 byte value, encoded in IEEE 754 half-precision binary floating point format,", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Maximum full frame luminance: ", + "Visibility": "", + "Data": [ + "46", + "MaxFullLuminance_02" + ], + "HelpText": "Maximum Full frame luminance value.\n2 byte value, encoded in IEEE 754 half-precision binary floating point format,", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Maximum Luminance: ", + "Visibility": "", + "Data": [ + "46", + "MaxLuminance_02" + ], + "HelpText": "Maximum luminance value(Relatively smaller portion of screen).\n2 byte value, encoded in IEEE 754 half-precision binary floating point format.", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Override Gamma values: ", + "Visibility": "", + "Data": [ + "46", + "Override_Gamma_Data_02" + ], + "HelpText": "This option when enabled along with Chromaticity feature will override gamma values through following VBT data", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Panel gamma: ", + "Visibility": "", + "Data": [ + "46", + "Gamma_02" + ], + "HelpText": "Value shall define the gamma range, from 1.00 to 3.54, as follows:\nField Value = (Gamma (value in float) x 100) - 100\nField values range from 00h through FFh.\nFFh = No gamma information shall be provided", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-2-10", + "PageName": "VESA DSC Parameters", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "DSC Major Version: ", + "Visibility": "", + "Data": [ + "56", + "C2_Major_Dsc_Version" + ], + "HelpText": "VESA DSC Major revision field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "DSC Minor Version: ", + "Visibility": "", + "Data": [ + "56", + "C2_Minor_Dsc_Version" + ], + "HelpText": "VESA DSC Minor revision field.", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Block prediction supported: ", + "Visibility": "", + "Data": [ + "56", + "C2_Blk_Prediction_En" + ], + "HelpText": "Sink supports block prediction as per the VESA DSC Spec.", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "RC Buffer Block size as per VESA DSC Spec: ", + "Visibility": "", + "Data": [ + "56", + "C2_RC_Block_Size" + ], + "HelpText": "RC buffer block size for a single RC buffer as defined by the VESA DSC spec.", + "WidgetValues": [ + { + "Key": "1 KB", + "Value": "0" + }, + { + "Key": "4 KB", + "Value": "1" + }, + { + "Key": "16 KB", + "Value": "2" + }, + { + "Key": "64 KB", + "Value": "3" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Number of RC buffer blocks as per VESA DSC Spec: ", + "Visibility": "", + "Data": [ + "56", + "C2_Dsc_RC_Buf_Size" + ], + "HelpText": "This field defines the number of RC buffers as per VESA DSC spec.\nThe number of RC buffers used by the software shall be (Value + 1) where Value is in range 0 to 127.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryBin", + "WidgetName": "Slices per line supported by the sink device: ", + "Visibility": "", + "Data": [ + "56", + "C2_Dsc_Slices_Per_Line" + ], + "HelpText": "This field defines the slices per line supported by the sink device.\nThe field is defined in bitmap fashion and details of each bits are as defined below:\n\tBits 31-10\t\t Bit 9\tBit 8\tBit 7\tBit 6\tBit 5\tBit 4\t Bit 3\t Bit 2\t Bit 1\t Bit 0\n\tReserved\t\t 24\t 20\t 16\t 12\t 10\t 8\t 6\t 4\t 2\t 1\nBit = 0, not supported. Bit = 1, supported\nNote: Assumption is that sink shall support all lower slices per line than maximum selected field. i.e. If it supports say 8 slices per line, it will also support 4/2/1 slices per line", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Line buffer depth as per VESA DSC Spec: ", + "Visibility": "", + "Data": [ + "56", + "C2_Line_Buffer_Depth" + ], + "HelpText": "Line buffer depth in bits as per VESA DSC spec.", + "WidgetValues": [ + { + "Key": "8 bits", + "Value": "0" + }, + { + "Key": "9 bits", + "Value": "1" + }, + { + "Key": "10 bits", + "Value": "2" + }, + { + "Key": "11 bits", + "Value": "3" + }, + { + "Key": "12 bits", + "Value": "4" + }, + { + "Key": "13 bits", + "Value": "5" + }, + { + "Key": "14 bits", + "Value": "6" + }, + { + "Key": "15 bits", + "Value": "7" + }, + { + "Key": "16 bits", + "Value": "8" + } + ] + }, + { + "WidgetType": "EntryBin", + "WidgetName": "Input compression BPC supported by the sink device: ", + "Visibility": "", + "Data": [ + "56", + "C2_Dsc_Bpc" + ], + "HelpText": "This field defines the compression input bpc supported by the sink device.\nThe field is defined in bitmap fashion and details of each bits are as defined below:\n\tBits 7-4\t Bit 3\t Bit 2\t Bit 1\t Bit 0\n\tRsvd\t 12 bpc\t 10bpc\t 8bpc\t Rsvd\nBit = 0, not supported. Bit = 1, supported\nNote: Assumption is that sink shall support all lower bpc values than the maximum selected field. i.e. If it supports say 12bpc, it will also support 10 and 8bpc as well", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Maximum supported compression BPP: ", + "Visibility": "", + "Data": [ + "56", + "C2_Dsc_Max_Bpp" + ], + "HelpText": "As of today, we are supporting 6/8/10/12 BPP for compression output.\nSelect the most appropriate BPP as supported by the sink.", + "WidgetValues": [ + { + "Key": "6 Bits per pixel", + "Value": "0" + }, + { + "Key": "8 Bits per pixel", + "Value": "1" + }, + { + "Key": "10 Bits per pixel", + "Value": "2" + }, + { + "Key": "12 Bits per pixel", + "Value": "3" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Slice height supported by the sink device: ", + "Visibility": "", + "Data": [ + "56", + "C2_Dsc_Slice_Height" + ], + "HelpText": "Slice height supported by the sink device for DSC slice.\nNote: Slice height must divide the picture height uniformly.", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-2-11", + "PageName": "MIPI Display Settings", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:5120 or Block:2, Field:LFP2_Device_Class, Value:5120", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Label", + "WidgetName": "MIPI DSI Controller Configuration Settings", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Video/Command Mode: ", + "Visibility": "", + "Data": [ + "52", + "Video_Command_Mode_02" + ], + "HelpText": "This feature helps in selecting Video/Command Mode.", + "WidgetValues": [ + { + "Key": "Video Mode", + "Value": "0" + }, + { + "Key": "Command Mode", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Packet Sequence For Video Mode: ", + "Visibility": "", + "Data": [ + "52", + "Packet_Sequence_Video_Mode_02" + ], + "HelpText": "This feature helps in selecting packet sequence for Video Mode.\nNon-burst with sync pulse\nNon-burst with sync events\nBurst mode", + "WidgetValues": [ + { + "Key": "Non-burst with sync pulse", + "Value": "1" + }, + { + "Key": "Non-burst with sync events", + "Value": "2" + }, + { + "Key": "Burst Mode", + "Value": "3" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Required Burst Mode Rate (in Kbps): ", + "Visibility": "", + "Data": [ + "52", + "RequiredBurstModeRate_02" + ], + "HelpText": "This feature allows to enter Required Burst Mode Rate in Kilo bits per sec. This should be greater than Non-Burst Mode Rate\nThis value is valid only if packet sequence for video mode is Burst Mode.", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Colour Format In Video Mode: ", + "Visibility": "", + "Data": [ + "52", + "Colour_Format_Video_Mode_02" + ], + "HelpText": "This feature helps in selecting supported colour format in Video Mode.", + "WidgetValues": [ + { + "Key": "RGB565", + "Value": "1" + }, + { + "Key": "RGB666", + "Value": "2" + }, + { + "Key": "RGB 666(Loosely Packed Format)", + "Value": "3" + }, + { + "Key": "RGB888", + "Value": "4" + }, + { + "Key": "RGB101010", + "Value": "5" + }, + { + "Key": "RGB121212", + "Value": "6" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Dual Link Support: ", + "Visibility": "", + "Data": [ + "52", + "Dual_Link_02" + ], + "HelpText": "This feature allows to select type of dual link.", + "WidgetValues": [ + { + "Key": "Dual Link Not Supported", + "Value": "0" + }, + { + "Key": "Dual Link Front Back Mode", + "Value": "1" + }, + { + "Key": "Dual Link Pixel Alternative Mode", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Pixel Overlap Count(Z-Inversion): ", + "Visibility": "", + "Data": [ + "42", + "PixelOverlapCount_02" + ], + "HelpText": "Select the number of Pixels to be overlapped per half of Scanline while using\nMIPI Dual Link Front-Back video mode.", + "WidgetValues": [ + { + "Key": "Zero Pixel Overlap", + "Value": "0" + }, + { + "Key": "One Pixel Overlap", + "Value": "1" + }, + { + "Key": "Two Pixels Overlap", + "Value": "2" + }, + { + "Key": "Three Pixels Overlap", + "Value": "3" + }, + { + "Key": "Four Pixel Overlap", + "Value": "4" + }, + { + "Key": "Five Pixel Overlap", + "Value": "5" + }, + { + "Key": "Six Pixels Overlap", + "Value": "6" + }, + { + "Key": "Seven Pixels Overlap", + "Value": "7" + }, + { + "Key": "Eight Pixel Overlap", + "Value": "8" + }, + { + "Key": "Nine Pixel Overlap", + "Value": "9" + }, + { + "Key": "Ten Pixels Overlap", + "Value": "10" + }, + { + "Key": "Eleven Pixels Overlap", + "Value": "11" + }, + { + "Key": "Twelve Pixel Overlap", + "Value": "12" + }, + { + "Key": "Thirteen Pixels Overlap", + "Value": "13" + }, + { + "Key": "Fourteen Pixels Overlap", + "Value": "14" + }, + { + "Key": "Fifteen Pixels Overlap", + "Value": "15" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " CABC Support: ", + "Visibility": "", + "Data": [ + "52", + "CABC_Support_02" + ], + "HelpText": "This feature helps in selecting CABC_Support.", + "WidgetValues": [ + { + "Key": "Disabled", + "Value": "0" + }, + { + "Key": "Enabled", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " CABC On/Off Commands: ", + "Visibility": "", + "Data": [ + "52", + "CabcCmdsPort_02" + ], + "HelpText": "Select the MIPI Port for sending CABC On/Off Commands in case of Dual link MIPI panels\nThis field is ignored in single link MIPI case", + "WidgetValues": [ + { + "Key": "MIPI DSI-0", + "Value": "0" + }, + { + "Key": "MIPI DSI-1", + "Value": "1" + }, + { + "Key": "Both MIPI DSI-0 and DSI-1", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Panel PWM/BkltController On/Off Commands: ", + "Visibility": "", + "Data": [ + "52", + "PanelPwmCmdsPort_02" + ], + "HelpText": "Select the MIPI Port for sending Panel PWM/BkltController On/Off Commands in case of Dual link MIPI panels\nThis field is ignored in single link MIPI case", + "WidgetValues": [ + { + "Key": "MIPI DSI-0", + "Value": "0" + }, + { + "Key": "MIPI DSI-1", + "Value": "1" + }, + { + "Key": "Both MIPI DSI-0 and DSI-1", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " RGB/BGR Panel Selection: ", + "Visibility": "", + "Data": [ + "52", + "RgbFlip_02" + ], + "HelpText": "Select if the panel is RGB or BGR", + "WidgetValues": [ + { + "Key": "RGB Panel", + "Value": "0" + }, + { + "Key": "BGR Panel", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Number Of Data Lanes: ", + "Visibility": "", + "Data": [ + "52", + "Number_Of_Lanes_02" + ], + "HelpText": "This feature allows to select number of data lanes going to use for MIPI DSI", + "WidgetValues": [ + { + "Key": "1", + "Value": "0" + }, + { + "Key": "2", + "Value": "1" + }, + { + "Key": "3", + "Value": "2" + }, + { + "Key": "4", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Sending Bus Turn Around (BTA): ", + "Visibility": "", + "Data": [ + "52", + "Bta_Disable_02" + ], + "HelpText": "Enable or Disable sending Bus Turn Around to the Peripheral", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "0" + }, + { + "Key": "Disabled", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Escape Clock: ", + "Visibility": "", + "Data": [ + "52", + "EscapeClk_02" + ], + "HelpText": "This feature helps to select frequency of Escape Clk.", + "WidgetValues": [ + { + "Key": "20 MHz", + "Value": "0" + }, + { + "Key": "10 MHz", + "Value": "1" + }, + { + "Key": "5 MHz", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " EoT Packet Transmission: ", + "Visibility": "", + "Data": [ + "52", + "EoTpSupport_02" + ], + "HelpText": "This feature helps to either enable or disable EoT packet Transmission", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "0" + }, + { + "Key": "Disabled", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Clock Stop Feature: ", + "Visibility": "", + "Data": [ + "52", + "ClockStop_02" + ], + "HelpText": "To enable or disable clock stopping feature during BLLP timing in a MIPI DPI (video) mode", + "WidgetValues": [ + { + "Key": "Disabled", + "Value": "0" + }, + { + "Key": "Enabled", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " LP Clock During LPM: ", + "Visibility": "", + "Data": [ + "52", + "LpClockDuringLpm_02" + ], + "HelpText": "In continuous clock mode (Clock Stop Feature disabled), Clock lane will always be in HS mode.\nIf this feature is enabled, Clock lane also goes to LP state once per frame during the mandated data lane LPM\nin MIPI DSI DPI (video) mode", + "WidgetValues": [ + { + "Key": "Disabled", + "Value": "0" + }, + { + "Key": "Enabled", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Blanking During BLLP: ", + "Visibility": "", + "Data": [ + "52", + "BlankingDuringBllp_02" + ], + "HelpText": "This feature helps to send Blanking packets during BLLP regions in a MIPI DSI DPI (video) mode.", + "WidgetValues": [ + { + "Key": "Disabled", + "Value": "0" + }, + { + "Key": "Enabled", + "Value": "1" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " TClkPrepare: ", + "Visibility": "", + "Data": [ + "52", + "TClkPrepare_02" + ], + "HelpText": "This feature allows to enter TClkPrepare in ns.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " TClkTrail: ", + "Visibility": "", + "Data": [ + "52", + "TClkTrail_02" + ], + "HelpText": "This feature allows to enter TClkTrail in ns.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " TClkPrepare + TClkZero: ", + "Visibility": "", + "Data": [ + "52", + "TClkPrepareTClkZero_02" + ], + "HelpText": "This feature allows to enter TClkPrepare + TClkZero in ns.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " THsPrepare: ", + "Visibility": "", + "Data": [ + "52", + "THsPrepare_02" + ], + "HelpText": "This feature allows to enter THsPrepare in ns.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " THsTrail: ", + "Visibility": "", + "Data": [ + "52", + "THsTrail_02" + ], + "HelpText": "This feature allows to enter THsTrail in ns.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " THsPrepare + THsZero: ", + "Visibility": "", + "Data": [ + "52", + "THsPrepareTHsZero_02" + ], + "HelpText": "This feature allows to enter THsPrepare + THsZero in ns.", + "WidgetValues": [] + }, + { + "WidgetType": "Label", + "WidgetName": "MIPI DSI Panel Power On/Off Sequence(delays)", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Power-Up Delay: ", + "Visibility": "", + "Data": [ + "52", + "PowerUpDelay_02" + ], + "HelpText": "Delay to be given after panel power up in 100uS", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Data Turn-On To Panel Backlight Enable Delay: ", + "Visibility": "", + "Data": [ + "52", + "DataTurnOnToPanelBacklightEnableDelay_02" + ], + "HelpText": "Delay to be given after MIPI DATA TURN ON and before backlight enabling in 100uS", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Pwm-On To Backlight Enable Delay: ", + "Visibility": "", + "Data": [ + "52", + "Mipi_PwmOn_To_Bklt_Enable_Delay_02" + ], + "HelpText": "Delay to be given after PWM-On and before Backlight Enable in 100uS\nDelay from PWM-On to Backlight Enable is included in delay from Data Turn-On to Panel Backlight Enable.\nSo it is expected that delay from PWM-On to Backlight Enable is less than the delay from Data Turn-On to Panel Backlight Enable.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Backlight Disable To Pwm-Off Delay: ", + "Visibility": "", + "Data": [ + "52", + "Mipi_Bklt_Disable_To_PwmOff_Delay_02" + ], + "HelpText": "Delay to be given after Backlight Disable and before Pwm-Off in 100uS\nDelay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to Data Turn-Off.\nSo it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to Data Turn-Off.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Backlight Disable To Data Turn-Off Delay: ", + "Visibility": "", + "Data": [ + "52", + "BacklightOffToDataTurnOffDelay_02" + ], + "HelpText": "Delay to be given after Backlight Disable and before MIPI DATA TURN OFF in 100uS", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Power-Down Delay: ", + "Visibility": "", + "Data": [ + "52", + "PowerDownDelay_02" + ], + "HelpText": "Delay to be given before panel power down in 100uS", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Power-Cycle Delay: ", + "Visibility": "", + "Data": [ + "52", + "PowerCycleDelay_02" + ], + "HelpText": "Delay to be given before panel power up and after panel power down in 100uS", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + } + ] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-3", + "PageName": "Panel #03", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "LabelHeading", + "WidgetName": "Common LFP Features", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryAsci", + "WidgetName": " LFP Panel Name: ", + "Visibility": "", + "Data": [ + "42", + "Panel_Name_03" + ], + "HelpText": "This feature defines the LFP panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Target X-Res: ", + "Visibility": "", + "Data": [ + "42", + "Panel_Width_03" + ], + "HelpText": "This value specifies the Target X-Resolution for this panel.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Target Y-Res: ", + "Visibility": "", + "Data": [ + "42", + "Panel_Height_03" + ], + "HelpText": "This value specifies the Target Y-Resolution for this panel.", + "WidgetValues": [] + }, + { + "WidgetType": "LabelHeading", + "WidgetName": " DPS Panel Type Features", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Seamless DRRS Minimum Refresh Rate (Hz): ", + "Visibility": "", + "Data": [ + "42", + "Seamless_DRRS_Min_RR_03" + ], + "HelpText": "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\nNote: Graphics driver will use this field only when EDID support is disabled in VBT configuration.", + "WidgetValues": [] + }, + { + "WidgetType": "LabelHeading", + "WidgetName": " BackLight Technology Type Features", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " BackLight Technology: ", + "Visibility": "", + "Data": [ + "40", + "Blt_Control_03" + ], + "HelpText": "This feature allows OEM to select the Backlight Technology.", + "WidgetValues": [ + { + "Key": "LED Backlight", + "Value": "2" + }, + { + "Key": "CCFL Backlight", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Panel Rotation: ", + "Visibility": "", + "Data": [ + "40", + "Panel_Rotation_03" + ], + "HelpText": "This feature specifies the Panel Rotation of LFP panel used.", + "WidgetValues": [ + { + "Key": "0 degree", + "Value": "0" + }, + { + "Key": "180 degree", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Panel Position: ", + "Visibility": "", + "Data": [ + "40", + "Panel_Position_03" + ], + "HelpText": "This feature specifies the Panel Position of LFP panel used.", + "WidgetValues": [ + { + "Key": "Inside Shell", + "Value": "0" + }, + { + "Key": "Outside Shell", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Dual LFP Port Sync: ", + "Visibility": "", + "Data": [ + "42", + "EnablePortSync_Bit_03" + ], + "HelpText": "This feature will allow users to disable/enable Dual LFP Port Sync and it is applicable for DDI-A, DDI-B in case of eDP and DSI-0, DSI-1 in case of MIPI. \r\n.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " GPU Dithering for Banding artifacts: ", + "Visibility": "", + "Data": [ + "42", + "EnableDithering_Bit_03" + ], + "HelpText": "This field can be used to enable dithering from the source side for reducing banding artifacts on the visual quality features like DPST.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "Button", + "WidgetName": "Power Features", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Generic DTD Timings", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "LFP PnP ID Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Backlight Control Parameters", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Chromaticity Control", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "VESA DSC Parameters", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "LabelHeading", + "WidgetName": "Integrated MIPI DSI Settings", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:5120 or Block:2, Field:LFP2_Device_Class, Value:5120", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "MIPI Display Settings", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:5120 or Block:2, Field:LFP2_Device_Class, Value:5120", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "LabelHeading", + "WidgetName": "Integrated eDP Settings", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "eDP Fast Link Training Configuration Parameters", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "eDP Panel Power Sequencing Parameters", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Edp Max Port Link Rate (in 200 Khz): ", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [ + "27", + "eDP_Max_Port_Link_Rate_03" + ], + "HelpText": "This field specifies EDP Max Port Link Rate supported by the port in unit of 200KHz.\nDefault value would be \"0\", in which case Display Drivers should consider EDP Max Port Link Rate to be the Platform supported Max Link Rate.\nOnly when OEM's need to limit to particular Link Rate can enter the value as mentioned in below table.\n\nNote:\n1) OEM's need to enter the values mentioned from below table only.\n2) If value entered is not matching with any of the below values then Platform supported Max Link Rate should be considere as EDP Max Port Link Rate by the display drivers.\n3) In case of EDP Fast Link Training Params(FLT), if user enters FLT Link Rate value greater than the \"eDP Max Port Link Rate\" then we need to use \n Fast Link training Link Rate = MIN (FLT Link Rate , eDP Max Port Link Rate)\n---------------------------------------------------------\n|\tLink Rate(Gbps)\t|\t Value to enter in text field\t|\n|\t \t\t|\t in terms of 200KHZ \t|\n---------------------------------------------------------\n|\t 1.62 \t\t|\t 8100 \t|\n|\t 2.16 \t\t|\t 10800 \t|\n|\t 2.43 \t\t|\t 12150 \t|\n|\t 2.7 \t\t|\t 13500 \t|\n|\t 3.24 \t\t|\t 16200 \t|\n|\t 3.78 \t\t|\t 18900 \t|\n|\t 4.32 \t\t|\t 21600 \t|\n|\t 5.4 \t\t|\t 27000 \t|\n|\t 6.48 \t\t|\t 32400 \t|\n|\t 6.75 \t\t|\t 33750 \t|\n|\t 8.1 \t\t|\t 40500 \t|\n", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Panel Color Depth: ", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [ + "27", + "eDP_Panel_Color_Depth_03" + ], + "HelpText": "This feature specifies the color depth of eDP panel used.", + "WidgetValues": [ + { + "Key": "18-bit Color Depth", + "Value": "0" + }, + { + "Key": "24-bit Color Depth", + "Value": "1" + }, + { + "Key": "30-bit Color Depth", + "Value": "2" + }, + { + "Key": "36-bit Color Depth", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Select VSwing/Pre-Emphasis table : ", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [ + "27", + "eDP_VswingPreEmph_3" + ], + "HelpText": "This feature selects the VSwing Pre-Emphasis setting table to be used. For Tigerlake, based on the selection respective table will be used.\nTables for Tigerlake:\nLow Power VSwing Pre-Emphasis Setting Table:\nFor HBR2:\n\t\t\t\t\t\t Pre-Emphasis (db)\n\t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\nVoltage \t\t Level-0/200mV \t\t 200mV, 0.0db \t\t 200mV, 1.9db \t\t 200mV, 3.5db \t\t 200mV, 4.9db\nSwing \t\t Level-1/250mV \t\t 250mV, 0.0db \t\t 250mV, 1.6db \t\t 250mV, 2.9db \t\t N/A\n(mV) \t\t Level-2/300mV \t\t 300mV, 0.0db \t\t 300mV, 1.3db \t\t N/A \t\t N/A\n\t\t Level-3/350mV \t\t 350mV, 0.0db \t\t N/A \t\t N/A \t\t N/A\n\n\nFor HBR3:\n\t\t\t\t\t\t Pre-Emphasis (db)\n\t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\nVoltage \t\t Level-0/350mV \t\t 350mV, 0.0db \t\t 350mV, 3.1db \t\t 350mV, 6.0db \t\t 350mV, 8.2db\nSwing \t\t Level-1/500mV \t\t 500mV, 0.0db \t\t 500mV, 2.9db \t\t 500mV, 5.1db \t\t N/A\n(mV) \t\t Level-2/650mV \t\t 650mV, 0.6db \t\t 600mV, 3.5db \t\t N/A \t\t N/A\n\t\t Level-3/900mV \t\t 900mV, 0.0db \t\t N/A \t\t N/A \t\t N/A\n\n\nDefault VSwing Pre-Emphasis Setting Table:\nFor HBR:\n\t\t\t\t\t\t Pre-Emphasis (db)\n\t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\nVoltage \t\t Level-0/350mV \t\t 350mV, 0.0db \t\t 350mV, 3.1db \t\t 350mV, 6.0db \t\t 350mV, 8.2db\nSwing \t\t Level-1/500mV \t\t 500mV, 0.0db \t\t 500mV, 2.9db \t\t 500mV, 5.1db \t\t N/A\n(mV) \t\t Level-2/650mV \t\t 650mV, 0.6db \t\t 600mV, 3.5db \t\t N/A \t\t N/A\n\t\t Level-3/900mV \t\t 900mV, 0.0db \t\t N/A \t\t N/A \t\t N/A\n\n\nFor HBR2:\n\t\t\t\t\t\t Pre-Emphasis (db)\n\t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\nVoltage \t\t Level-0/350mV \t\t 350mV, 0.0db \t\t 350mV, 3.1db \t\t 350mV, 6.0db \t\t 350mV, 8.2db\nSwing \t\t Level-1/500mV \t\t 500mV, 0.0db \t\t 500mV, 2.9db \t\t 500mV, 5.1db \t\t N/A\n(mV) \t\t Level-2/650mV \t\t 650mV, 0.6db \t\t 600mV, 3.5db \t\t N/A \t\t N/A\n\t\t Level-3/900mV \t\t 900mV, 0.0db \t\t N/A \t\t N/A \t\t N/A", + "WidgetValues": [ + { + "Key": "Default VSwing/Pre-Emphasis Table", + "Value": "1" + }, + { + "Key": "Low Power VSwing/Pre-Emphasis Table", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " eDP Spread Spectrum Clock: ", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [ + "40", + "Enable_SSC03" + ], + "HelpText": "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Pixel Overlap Count: ", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [ + "42", + "PixelOverlapCount_03" + ], + "HelpText": "Select the number of Pixels to be overlapped per half of Scanline while using Edp Multi-SST(MSO) feature.", + "WidgetValues": [ + { + "Key": "Zero Pixel Overlap", + "Value": "0" + }, + { + "Key": "One Pixel Overlap", + "Value": "1" + }, + { + "Key": "Two Pixel Overlap", + "Value": "2" + }, + { + "Key": "Three Pixel Overlap", + "Value": "3" + }, + { + "Key": "Four Pixel Overlap", + "Value": "4" + }, + { + "Key": "Five Pixel Overlap", + "Value": "5" + }, + { + "Key": "Six Pixel Overlap", + "Value": "6" + }, + { + "Key": "Seven Pixel Overlap", + "Value": "7" + }, + { + "Key": "Eight Pixel Overlap", + "Value": "8" + } + ] + }, + { + "WidgetType": "Button", + "WidgetName": "PSR Feature", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Apical Feature", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [], + "HelpText": "", + "WidgetValues": [] + } + ], + "NestedPages": [ + { + "Type": "Block", + "Block": { + "PageNum": "5-2-3-1", + "PageName": "eDP Panel Power Sequencing Parameters", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " T3 optimization: ", + "Visibility": "", + "Data": [ + "27", + "eDP_T3_Optimization_03" + ], + "HelpText": "This feature enables or disables T3 optimization.\nWhen enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\nWhen disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "LCDVCC to HPD high delay (T3): ", + "Visibility": "", + "Data": [ + "27", + "eDP_Vcc_To_Hpd_Delay_03" + ], + "HelpText": "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\nValid Range: 0 to 200msec", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Valid video data to Backlight Enable delay (T8): ", + "Visibility": "", + "Data": [ + "27", + "eDP_DataOn_To_BkltEnable_Delay_03" + ], + "HelpText": "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\nT8 is inclusive of T7.\nValid Range of T7: 0 to 50msec", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "PWM-On To Backlight Enable delay: ", + "Visibility": "", + "Data": [ + "27", + "eDP_PwmOn_To_Bklt_Enable_Delay_03" + ], + "HelpText": "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\nDelay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\nSo it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Backlight Disable to PWM-Off delay: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Bklt_Disable_To_PwmOff_Delay_03" + ], + "HelpText": "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\nDelay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\nSo it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Backlight Disable to End of Valid video data delay (T9): ", + "Visibility": "", + "Data": [ + "27", + "eDP_BkltDisable_To_DataOff_Delay_03" + ], + "HelpText": "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "End of Valid video data to Power-Off delay (T10): ", + "Visibility": "", + "Data": [ + "27", + "eDP_DataOff_To_PowerOff_Delay_03" + ], + "HelpText": "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\nValid Range: 0 to 500 msec", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Power-off time (T12): ", + "Visibility": "", + "Data": [ + "27", + "eDP_PowerCycle_Delay_03" + ], + "HelpText": "Using this field Power-off time can be specified in 100uS.", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-3-2", + "PageName": "eDP Fast Link Training Configuration Parameters", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Is FastLinkTraining Feature Supported: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Fast_Link_Training_Supported_03" + ], + "HelpText": "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled.", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Data Rate: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Fast_Link_Training_Data_Rate_03" + ], + "HelpText": "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. It will be used if the sink indicates that no aux handshake is required during link training.\n\nIn case of EDP Fast Link Training Params(FLT), if user enters FLT Link Rate value greater than the \"eDP Max Port Link Rate\" then driver would use \n Fast Link training Link Rate = MIN (FLT Link Rate , eDP Max Port Link Rate).", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Lane Count: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Link_LaneCount_03" + ], + "HelpText": "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. It will be used if the sink indicates that no aux handshake is required during link training.", + "WidgetValues": [ + { + "Key": "x1", + "Value": "0" + }, + { + "Key": "x2", + "Value": "1" + }, + { + "Key": "x4", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Pre-Emphasis: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Link_PreEmp_03" + ], + "HelpText": "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. It will be used if the sink indicates that no aux handshake is required during link training.", + "WidgetValues": [ + { + "Key": "Level-0", + "Value": "0" + }, + { + "Key": "Level-1", + "Value": "1" + }, + { + "Key": "Level-2", + "Value": "2" + }, + { + "Key": "Level-3", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Voltage Swing: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Link_Vswing_03" + ], + "HelpText": "This feature allows for the selection of the Voltage Swing value for the embedded DP link. It will be used if the sink indicates that no aux handshake is required during link training.", + "WidgetValues": [ + { + "Key": "Swing-0", + "Value": "0" + }, + { + "Key": "Swing-1", + "Value": "1" + }, + { + "Key": "Swing-2", + "Value": "2" + }, + { + "Key": "Swing-3", + "Value": "3" + } + ] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-3-3", + "PageName": "PSR Feature", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Full Link enable: ", + "Visibility": "", + "Data": [ + "9", + "PSR_FullLink_Enable_03" + ], + "HelpText": "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state.", + "WidgetValues": [ + { + "Key": "No", + "Value": "0" + }, + { + "Key": "Yes", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Require AUX to wake up: ", + "Visibility": "", + "Data": [ + "9", + "PSR_Require_AUX2Wakeup_03" + ], + "HelpText": "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used.", + "WidgetValues": [ + { + "Key": "No", + "Value": "0" + }, + { + "Key": "Yes", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Lines to wait before link standby: ", + "Visibility": "", + "Data": [ + "9", + "PSR_Lines2Wait_B4LinkS3_03" + ], + "HelpText": "This field determines Lines to wait before link standby\n0 lines to wait (Default)\n1 lines to wait\n4 lines to wait\n8 lines to wait\nOthers Reserved", + "WidgetValues": [ + { + "Key": "0 lines to wait", + "Value": "0" + }, + { + "Key": "1 lines to wait", + "Value": "1" + }, + { + "Key": "4 lines to wait", + "Value": "2" + }, + { + "Key": "8 lines to wait", + "Value": "3" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Idle frames to wait: ", + "Visibility": "", + "Data": [ + "9", + "PSR_IdleFrames2Wait_03" + ], + "HelpText": "Idle frames to wait for PSR enable.\nAllowed values 0-15. Default value is 0.", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Clock Recovery Time: ", + "Visibility": "", + "Data": [ + "9", + "PSR_TP1_WaitTime_03" + ], + "HelpText": "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)", + "WidgetValues": [ + { + "Key": "500 usec", + "Value": "0" + }, + { + "Key": "100 usec", + "Value": "1" + }, + { + "Key": "2.5 msec", + "Value": "2" + }, + { + "Key": "0 (Skip)", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Channel Equalization Time for PSR1 panel: ", + "Visibility": "", + "Data": [ + "9", + "PSR1_TP_2_3_4_WaitTime_03" + ], + "HelpText": "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) or TP4(Training Pattern4) time during PSR1 exit(wake up)", + "WidgetValues": [ + { + "Key": "500 usec", + "Value": "0" + }, + { + "Key": "100 usec", + "Value": "1" + }, + { + "Key": "2.5 msec", + "Value": "2" + }, + { + "Key": "0 (Skip)", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Channel Equalization Time for PSR2 panel: ", + "Visibility": "", + "Data": [ + "9", + "PSR2_TP_2_3_4_WaitTime_03" + ], + "HelpText": "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) or TP4(Training Pattern4) time during PSR2 exit(wake up)", + "WidgetValues": [ + { + "Key": "500 usec", + "Value": "0" + }, + { + "Key": "100 usec", + "Value": "1" + }, + { + "Key": "2.5 msec", + "Value": "2" + }, + { + "Key": "50 usec", + "Value": "3" + } + ] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-3-4", + "PageName": "Apical Feature", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Apical Assertive Display IP: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Apical_Display_Ip_Enable_03" + ], + "HelpText": "This field enables/disables the Apical Assertive Display IP for this panel.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Panel OUI (IEEE OUI): ", + "Visibility": "", + "Data": [ + "27", + "eDP_Panel_Oui_03" + ], + "HelpText": "This field specifies the Apical IP specific Panel OUI field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " DPCD Base Address: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Dpcd_Base_Address_03" + ], + "HelpText": "This field specifies the Apical IP specific DPCD base address field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " DPCD Irdidix Control 0: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Dpcd_Irdidix_Control0_03" + ], + "HelpText": "This field specifies the Apical IP specific DPCD Irdidix control 0 field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " DPCD Option Select: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Dpcd_Option_Select_03" + ], + "HelpText": "This field specifies the Apical IP specific DPCD option select field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " DPCD Backlight: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Dpcd_Backlight_03" + ], + "HelpText": "This field specifies the Apical IP specific backlight value.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Ambient Light: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Ambient_Light_03" + ], + "HelpText": "This field specifies the Apical IP specific Ambient light value.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Backlight scale: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Backlight_Scale_03" + ], + "HelpText": "This field specifies the Apical IP specific backlight scale field.", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-3-5", + "PageName": "Power Features", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Intel Display Power Saving Technology (DPST) (Mobile only): ", + "Visibility": "", + "Data": [ + "44", + "DPST_Enable_03" + ], + "HelpText": "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled.\nIntel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power.\nNote: This technology is only active when the system is running in battery mode and the LFP is the only active display device.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Intel Display Refresh Rate Switching (DRRS) (Mobile only): ", + "Visibility": "", + "Data": [ + "44", + "DRRS_Enable_03" + ], + "HelpText": "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Edge Luminance Profile (ELP) : ", + "Visibility": "", + "Data": [ + "44", + "ELP_Enable_03" + ], + "HelpText": "This feature determines whether the ELP feature is enabled or disabled.\nEdge Luminance Profile (ELP) is a panel technology which reduce luminance on the edge of screen to save panel power.\nNote:This technology cannot co-exist with DPST and OPST ((i.e.) OPST, DPST and ELP cannot exist together.They are all mutually exclusive to each other.)", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " OLED Power Saving Technology (OPST) : ", + "Visibility": "", + "Data": [ + "44", + "OPST_Enable_03" + ], + "HelpText": "This feature determines whether the OPST feature is enabled or disabled.\nOLED Power Saving Technology (OPST) is a panel technology which saves power by intelligent, adaptive dimming of midrange pixel values more aggressively than the extremes without compromising the viewability.\nNote: This technology cannot co-exist with ELP and DPST ((i.e.) OPST, DPST and ELP cannot exist together.They are all mutually exclusive to each other.)", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Dynamic Media Refresh Rate Switching Enable/Disable ", + "Visibility": "", + "Data": [ + "44", + "DMRRS_Enable_03" + ], + "HelpText": "This feature determines whether Dynamic media refresh rate switching is to be enabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Enable Display Lace Support: ", + "Visibility": "", + "Data": [ + "44", + "LACE_Enable_03" + ], + "HelpText": "This feature, when enabled, will set Display Lace Support otherwise, the functionality will be disabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Panel Self Refresh (PSR): ", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [ + "44", + "PSR_Enable_03" + ], + "HelpText": "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Assertive Display Technology Enable/Disable: ", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [ + "44", + "ADT_Enable_03" + ], + "HelpText": "This feature determines whether Assertive display technology is to be enabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Intel Automatic Display Brightness (ADB) (Mobile only): ", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [ + "44", + "ADB_Enable_03" + ], + "HelpText": "This feature determines whether Intel Automatic Display Brightness is to be enabled. Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) depending on the current ambient light environment.\nWhen enabled, the driver and VBIOS will control the backlight brightness of the LFP depending on the ambient environment if and only if the LFP is the only active display. When disabled, the driver will perform no action.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "EDP 4k/2k HOBL Feature: ", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [ + "44", + "eDP_4k_2k_HOBL_feature_Enable_03" + ], + "HelpText": "This feature will allow users to disable/enable the edp 4k/2k HOBL(Hours Of Battery Life) feature by programming relevant registers specific for a platform.\r\n.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Default Display LACE Enabled status: ", + "Visibility": "", + "Data": [ + "44", + "LACE_Status_03" + ], + "HelpText": "This feature, when enabled, will set Default Display LACE Enabled status otherwise, the functionality will be disabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "DPST Aggressiveness Level: ", + "Visibility": "", + "Data": [ + "44", + "DPST_Aggressiveness_Profile_03" + ], + "HelpText": "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n1 (Maximum Quality with No DPST)\n2\n3\n4\n5\n6 (Maximum Battery)", + "WidgetValues": [ + { + "Key": "1 - Maximum Quality with No DPST", + "Value": "1" + }, + { + "Key": "2", + "Value": "2" + }, + { + "Key": "3", + "Value": "3" + }, + { + "Key": "4", + "Value": "4" + }, + { + "Key": "5", + "Value": "5" + }, + { + "Key": "6 - Maximum Battery", + "Value": "6" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "LACE Aggressiveness Level: ", + "Visibility": "", + "Data": [ + "44", + "LACE_Aggressiveness_Profile_03" + ], + "HelpText": "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\nMinimum 0\nModerate 1\nHigh 2", + "WidgetValues": [ + { + "Key": "Minimum", + "Value": "0" + }, + { + "Key": "Moderate", + "Value": "1" + }, + { + "Key": "High", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "ELP Aggressiveness Level: ", + "Visibility": "", + "Data": [ + "44", + "ELP_Aggressiveness_Profile_03" + ], + "HelpText": "This feature allows for the selection of ELP Aggressiveness level for this Panel Type.\nMinimum Power Savings\nMedium Power Savings \nMaximum Power Savings", + "WidgetValues": [ + { + "Key": "Minimum Power Savings", + "Value": "0" + }, + { + "Key": "Medium Power Savings", + "Value": "1" + }, + { + "Key": "Maximum Power Savings", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "OPST Aggressiveness Level: ", + "Visibility": "", + "Data": [ + "44", + "OPST_Aggressiveness_Profile_03" + ], + "HelpText": "This feature allows for the selection of OPST Aggressiveness level for this Panel Type.\nMinimum Power Savings\nMedium Power Savings \nMaximum Power Savings", + "WidgetValues": [ + { + "Key": "Minimum Power Savings", + "Value": "0" + }, + { + "Key": "Medium Power Savings", + "Value": "1" + }, + { + "Key": "Maximum Power Savings", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Default Display VRR Enabled status: ", + "Visibility": "", + "Data": [ + "44", + "VRR_Status_03" + ], + "HelpText": "VRR (Variable Refresh Rate) is a feature that can continuously and seamlessly vary Refresh Rate on the fly, on displays that support Variable Refresh rate Technologies.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-3-6", + "PageName": "Generic DTD Timings", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Pixel Clock in KHz: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_Pixel_CLK_03" + ], + "HelpText": "Pixel Clock (in KHz) Range from 0.001 to 4294967.295 MP/s.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Active: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_Active_03" + ], + "HelpText": "Horizontal Active Image Pixels Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Active: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_Active_03" + ], + "HelpText": "Vertical Active Image Lines Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Blank: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_Blank_03" + ], + "HelpText": "Horizontal Blank Pixels Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Blank: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_Blank_03" + ], + "HelpText": "Vertical Blank lines Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Front Porch: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_FrontPorch_03" + ], + "HelpText": "Horizontal Front Porch Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Front Porch: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_FrontPorch_03" + ], + "HelpText": "Vertical Front Porch Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Sync: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_Sync_03" + ], + "HelpText": "Horizontal Sync Width Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Sync: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_Sync_03" + ], + "HelpText": "Vertical Sync Width Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Image Size: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_Image_Size_03" + ], + "HelpText": "Horizontal Addressable Video Image Size in mm represented by 16bits. Image size multiplier 1.00 mm precision.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Image Size: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_Image_Size_03" + ], + "HelpText": "Vertical Addressable Video Image Size in mm represented by 16bits. Image size multiplier 1.00 mm precision.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryBin", + "WidgetName": "Common Flag: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_Common_Flag_03" + ], + "HelpText": "Common DTD Flags:\nBit 7 : Horizontal Sync Polarity\n1 : Positive\n0 : Negative\nBit 6 : Vertical Sync polarity\n1 : Positive\n0 : Negative\nBit 5 - 0: Reserved (Default value 0)", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-3-7", + "PageName": "LFP PnP ID Table", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Table", + "WidgetName": "", + "Visibility": "", + "Data": [ + "42", + "LFP_Panel_PnP_ID_03" + ], + "HelpText": "This feature allows the 10 bytes of EDID Vendor/Product ID starting at offset 08h to be used as a PnP ID.\n\nTable Definition:\n\tWord: ID Manufacturer Name\n\tWord: ID Product Code\n\tDWord: ID Serial Number\n\tByte: Week of Manufacture\n\tByte: Year of Manufacture", + "WidgetValues": [ + { + "ColumnName": "PnP ID", + "SizeinBytes": "1" + } + ] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-1-8", + "PageName": "Backlight Control Parameters", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Inverter Type: ", + "Visibility": "", + "Data": [ + "43", + "BLC_Inv_Type_03" + ], + "HelpText": "This feature allows for the selection of the Backlight Inverter type that is to be used to control the backlight brightness of the LFP.\nWhen PWM is selected, the driver and VBIOS will control the backlight brightness via the integrated PWM solution for the applicable chipsets.\nWhen None/External is selected, the system BIOS will control the backlight brightness via the external solution.", + "WidgetValues": [ + { + "Key": "None/External", + "Value": "0" + }, + { + "Key": "PWM", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Pwm Source Selection: ", + "Visibility": "", + "Data": [ + "43", + "Lfp_Pwm_Source_Selection_03" + ], + "HelpText": "If panel supports 'Intel HDR AUX Interface', it will always be chosen by default. If not, value in 'PWM Source Selection' will be used", + "WidgetValues": [ + { + "Key": "PWM From Display Engine", + "Value": "2" + }, + { + "Key": "PWM From LCD Panel", + "Value": "3" + }, + { + "Key": "Panel Driver Interface", + "Value": "4" + }, + { + "Key": "VESA eDP AUX Interface", + "Value": "5" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Pwm Controller Selection: ", + "Visibility": "", + "Data": [ + "43", + "Lfp_Pwm_Controller_Selection_03" + ], + "HelpText": "This field allows to select the PWM Controller to be used for the selected Local Flat Panel.This field allows to select the PWM Controller to be used for the selected Local Flat Panel.If Two LFPs are connected then PWM0 and PWM1 must be selected accordingly.", + "WidgetValues": [ + { + "Key": "PWM0", + "Value": "0" + }, + { + "Key": "PWM1", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Inverter Polarity: ", + "Visibility": "", + "Data": [ + "43", + "BLC_Inv_Polarity_03" + ], + "HelpText": "This feature allows the backlight inverter polarity to be specified.\nNormal means 0 value is minimum brightness.\nInverted means 0 value is maximum brightness.", + "WidgetValues": [ + { + "Key": "Normal", + "Value": "0" + }, + { + "Key": "Inverted", + "Value": "1" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Minimum Brightness: ", + "Visibility": "", + "Data": [ + "43", + "Post_Min_Brightness_03" + ], + "HelpText": "This feature allows defining the absolute minimum backlight brightness. The driver will never decrease the backlight less than this value. The value must be specified using normal polarity semantics. The value should range from 0 to 255 if the brightness precision bit is chosen to be 8, and it should range from 0 to 65535 if the precision bit is chosen to be 16.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "POST Backlight Intensity: ", + "Visibility": "", + "Data": [ + "43", + "Post_Brightness_03" + ], + "HelpText": "This feature is used to set default backlight brightness value of the panel at POST. The value should range from 0 to 255 if the bit precision is chosen to be 8 and it should range from 0 to 65535 if the brightness bit precision is chosent to be 16.", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Brightness Precision Bits: ", + "Visibility": "", + "Data": [ + "43", + "BrightnessPrecisionBits_03" + ], + "HelpText": "This field represents the range of brightness in terms of bit precision.\n 8 = Brightness range of 0 to 255.\n 16 = Brightness range of 0 to 65535", + "WidgetValues": [ + { + "Key": "8", + "Value": "8" + }, + { + "Key": "16", + "Value": "16" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "PWM Inverter Frequency (Hz): ", + "Visibility": "", + "Data": [ + "43", + "PWM_Frequency_03" + ], + "HelpText": "This feature allows for the definition of the frequency needed for PWM Inverter.\nNote: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Intel HDR DPCD Refresh Timeout (unit - 10 micro seconds): ", + "Visibility": "", + "Data": [ + "43", + "HdrDpcdRefreshTimeout_03" + ], + "HelpText": "This field allows to configure the refresh timeout of Intel HDR DPCDs for different TCON Vendors.\nNote:\n\tThe value is in units of 10 microseconds.\n\tThe range (entered as a decimal number), for the timeout is 0-65535", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-3-9", + "PageName": "Chromaticity Control", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Chromaticity Control Feature: ", + "Visibility": "", + "Data": [ + "46", + "Chromacity_Enable_03" + ], + "HelpText": "This bit enables Chromaticity feature.\nIf this bit is enabled, EDID values for chromaticity will be used, else feature is disabled.\nFeature will be supported for Panels that support EDID version 1.4 or higher.\nPlease refer to section 3.7 of EDID Specification 1.4.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Override the EDID values: ", + "Visibility": "", + "Data": [ + "46", + "Override_EDID_Data_03" + ], + "HelpText": "This option when enabled along with Chromaticity feature will override EDID values through following VBT data", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Red_Green_bits (Bits 1:0 at 19h): ", + "Visibility": "", + "Data": [ + "46", + "Red_Green_03" + ], + "HelpText": "Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Blue_White_bits (Bits 1:0 at 1Ah): ", + "Visibility": "", + "Data": [ + "46", + "Blue_White_03" + ], + "HelpText": "Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Red_x (Bits 9:2 at 1Bh): ", + "Visibility": "", + "Data": [ + "46", + "Red_x_03" + ], + "HelpText": "Bits 9:2 of red color x coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Red_y (Bits 9:2 at 1Ch): ", + "Visibility": "", + "Data": [ + "46", + "Red_y_03" + ], + "HelpText": "Bits 9:2 of red color y coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Green_x (Bits 9:2 at 1Dh): ", + "Visibility": "", + "Data": [ + "46", + "Green_x_03" + ], + "HelpText": "Bits 9:2 of Green color x coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Green_y (Bits 9:2 at 1Eh): ", + "Visibility": "", + "Data": [ + "46", + "Green_y_03" + ], + "HelpText": "Bits 9:2 of Green color y coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Blue_x (Bits 9:2 at 1Fh): ", + "Visibility": "", + "Data": [ + "46", + "Blue_x_03" + ], + "HelpText": "Bits 9:2 of Blue color x coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Blue_y (Bits 9:2 at 20h): ", + "Visibility": "", + "Data": [ + "46", + "Blue_y_03" + ], + "HelpText": "Bits 9:2 of Blue color y coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " White_x (Bits 9:2 at 21h): ", + "Visibility": "", + "Data": [ + "46", + "White_x_03" + ], + "HelpText": "Bits 9:2 of White color x coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " White_y (Bits 9:2 at 22h): ", + "Visibility": "", + "Data": [ + "46", + "White_y_03" + ], + "HelpText": "Bits 9:2 of White color y coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Override Luminance values ", + "Visibility": "", + "Data": [ + "46", + "Override_LUM_Data_03" + ], + "HelpText": "This option when enabled along with Chromaticity feature will override luminance values following VBT values", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Minimum Luminance: ", + "Visibility": "", + "Data": [ + "46", + "MinLuminance_03" + ], + "HelpText": "Minimum luminance value.\n2 byte value, encoded in IEEE 754 half-precision binary floating point format,", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Maximum full frame luminance: ", + "Visibility": "", + "Data": [ + "46", + "MaxFullLuminance_03" + ], + "HelpText": "Maximum Full frame luminance value.\n2 byte value, encoded in IEEE 754 half-precision binary floating point format,", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Maximum Luminance: ", + "Visibility": "", + "Data": [ + "46", + "MaxLuminance_03" + ], + "HelpText": "Maximum luminance value(Relatively smaller portion of screen).\n2 byte value, encoded in IEEE 754 half-precision binary floating point format.", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Override Gamma values: ", + "Visibility": "", + "Data": [ + "46", + "Override_Gamma_Data_03" + ], + "HelpText": "This option when enabled along with Chromaticity feature will override gamma values through following VBT data", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Panel gamma: ", + "Visibility": "", + "Data": [ + "46", + "Gamma_03" + ], + "HelpText": "Value shall define the gamma range, from 1.00 to 3.54, as follows:\nField Value = (Gamma (value in float) x 100) - 100\nField values range from 00h through FFh.\nFFh = No gamma information shall be provided", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-3-10", + "PageName": "VESA DSC Parameters", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "DSC Major Version: ", + "Visibility": "", + "Data": [ + "56", + "C3_Major_Dsc_Version" + ], + "HelpText": "VESA DSC Major revision field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "DSC Minor Version: ", + "Visibility": "", + "Data": [ + "56", + "C3_Minor_Dsc_Version" + ], + "HelpText": "VESA DSC Minor revision field.", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Block prediction supported: ", + "Visibility": "", + "Data": [ + "56", + "C3_Blk_Prediction_En" + ], + "HelpText": "Sink supports block prediction as per the VESA DSC Spec.", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "RC Buffer Block size as per VESA DSC Spec: ", + "Visibility": "", + "Data": [ + "56", + "C3_RC_Block_Size" + ], + "HelpText": "RC buffer block size for a single RC buffer as defined by the VESA DSC spec.", + "WidgetValues": [ + { + "Key": "1 KB", + "Value": "0" + }, + { + "Key": "4 KB", + "Value": "1" + }, + { + "Key": "16 KB", + "Value": "2" + }, + { + "Key": "64 KB", + "Value": "3" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Number of RC buffer blocks as per VESA DSC Spec: ", + "Visibility": "", + "Data": [ + "56", + "C3_Dsc_RC_Buf_Size" + ], + "HelpText": "This field defines the number of RC buffers as per VESA DSC spec.\nThe number of RC buffers used by the software shall be (Value + 1) where Value is in range 0 to 127.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryBin", + "WidgetName": "Slices per line supported by the sink device: ", + "Visibility": "", + "Data": [ + "56", + "C3_Dsc_Slices_Per_Line" + ], + "HelpText": "This field defines the slices per line supported by the sink device.\nThe field is defined in bitmap fashion and details of each bits are as defined below:\n\tBits 31-10\t\t Bit 9\tBit 8\tBit 7\tBit 6\tBit 5\tBit 4\t Bit 3\t Bit 2\t Bit 1\t Bit 0\n\tReserved\t\t 24\t 20\t 16\t 12\t 10\t 8\t 6\t 4\t 2\t 1\nBit = 0, not supported. Bit = 1, supported\nNote: Assumption is that sink shall support all lower slices per line than maximum selected field. i.e. If it supports say 8 slices per line, it will also support 4/2/1 slices per line", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Line buffer depth as per VESA DSC Spec: ", + "Visibility": "", + "Data": [ + "56", + "C3_Line_Buffer_Depth" + ], + "HelpText": "Line buffer depth in bits as per VESA DSC spec.", + "WidgetValues": [ + { + "Key": "8 bits", + "Value": "0" + }, + { + "Key": "9 bits", + "Value": "1" + }, + { + "Key": "10 bits", + "Value": "2" + }, + { + "Key": "11 bits", + "Value": "3" + }, + { + "Key": "12 bits", + "Value": "4" + }, + { + "Key": "13 bits", + "Value": "5" + }, + { + "Key": "14 bits", + "Value": "6" + }, + { + "Key": "15 bits", + "Value": "7" + }, + { + "Key": "16 bits", + "Value": "8" + } + ] + }, + { + "WidgetType": "EntryBin", + "WidgetName": "Input compression BPC supported by the sink device: ", + "Visibility": "", + "Data": [ + "56", + "C3_Dsc_Bpc" + ], + "HelpText": "This field defines the compression input bpc supported by the sink device.\nThe field is defined in bitmap fashion and details of each bits are as defined below:\n\tBits 7-4\t Bit 3\t Bit 2\t Bit 1\t Bit 0\n\tRsvd\t 12 bpc\t 10bpc\t 8bpc\t Rsvd\nBit = 0, not supported. Bit = 1, supported\nNote: Assumption is that sink shall support all lower bpc values than the maximum selected field. i.e. If it supports say 12bpc, it will also support 10 and 8bpc as well", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Maximum supported compression BPP: ", + "Visibility": "", + "Data": [ + "56", + "C3_Dsc_Max_Bpp" + ], + "HelpText": "As of today, we are supporting 6/8/10/12 BPP for compression output.\nSelect the most appropriate BPP as supported by the sink.", + "WidgetValues": [ + { + "Key": "6 Bits per pixel", + "Value": "0" + }, + { + "Key": "8 Bits per pixel", + "Value": "1" + }, + { + "Key": "10 Bits per pixel", + "Value": "2" + }, + { + "Key": "12 Bits per pixel", + "Value": "3" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Slice height supported by the sink device: ", + "Visibility": "", + "Data": [ + "56", + "C3_Dsc_Slice_Height" + ], + "HelpText": "Slice height supported by the sink device for DSC slice.\nNote: Slice height must divide the picture height uniformly.", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-3-11", + "PageName": "MIPI Display Settings", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:5120 or Block:2, Field:LFP2_Device_Class, Value:5120", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Label", + "WidgetName": "MIPI DSI Controller Configuration Settings", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Video/Command Mode: ", + "Visibility": "", + "Data": [ + "52", + "Video_Command_Mode_03" + ], + "HelpText": "This feature helps in selecting Video/Command Mode.", + "WidgetValues": [ + { + "Key": "Video Mode", + "Value": "0" + }, + { + "Key": "Command Mode", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Packet Sequence For Video Mode: ", + "Visibility": "", + "Data": [ + "52", + "Packet_Sequence_Video_Mode_03" + ], + "HelpText": "This feature helps in selecting packet sequence for Video Mode.\nNon-burst with sync pulse\nNon-burst with sync events\nBurst mode", + "WidgetValues": [ + { + "Key": "Non-burst with sync pulse", + "Value": "1" + }, + { + "Key": "Non-burst with sync events", + "Value": "2" + }, + { + "Key": "Burst Mode", + "Value": "3" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Required Burst Mode Rate (in Kbps): ", + "Visibility": "", + "Data": [ + "52", + "RequiredBurstModeRate_03" + ], + "HelpText": "This feature allows to enter Required Burst Mode Rate in Kilo bits per sec. This should be greater than Non-Burst Mode Rate\nThis value is valid only if packet sequence for video mode is Burst Mode.", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Colour Format In Video Mode: ", + "Visibility": "", + "Data": [ + "52", + "Colour_Format_Video_Mode_03" + ], + "HelpText": "This feature helps in selecting supported colour format in Video Mode.", + "WidgetValues": [ + { + "Key": "RGB565", + "Value": "1" + }, + { + "Key": "RGB666", + "Value": "2" + }, + { + "Key": "RGB 666(Loosely Packed Format)", + "Value": "3" + }, + { + "Key": "RGB888", + "Value": "4" + }, + { + "Key": "RGB101010", + "Value": "5" + }, + { + "Key": "RGB121212", + "Value": "6" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Dual Link Support: ", + "Visibility": "", + "Data": [ + "52", + "Dual_Link_03" + ], + "HelpText": "This feature allows to select type of dual link.", + "WidgetValues": [ + { + "Key": "Dual Link Not Supported", + "Value": "0" + }, + { + "Key": "Dual Link Front Back Mode", + "Value": "1" + }, + { + "Key": "Dual Link Pixel Alternative Mode", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Pixel Overlap Count(Z-Inversion): ", + "Visibility": "", + "Data": [ + "42", + "PixelOverlapCount_03" + ], + "HelpText": "Select the number of Pixels to be overlapped per half of Scanline while using\nMIPI Dual Link Front-Back video mode.", + "WidgetValues": [ + { + "Key": "Zero Pixel Overlap", + "Value": "0" + }, + { + "Key": "One Pixel Overlap", + "Value": "1" + }, + { + "Key": "Two Pixels Overlap", + "Value": "2" + }, + { + "Key": "Three Pixels Overlap", + "Value": "3" + }, + { + "Key": "Four Pixel Overlap", + "Value": "4" + }, + { + "Key": "Five Pixel Overlap", + "Value": "5" + }, + { + "Key": "Six Pixels Overlap", + "Value": "6" + }, + { + "Key": "Seven Pixels Overlap", + "Value": "7" + }, + { + "Key": "Eight Pixel Overlap", + "Value": "8" + }, + { + "Key": "Nine Pixel Overlap", + "Value": "9" + }, + { + "Key": "Ten Pixels Overlap", + "Value": "10" + }, + { + "Key": "Eleven Pixels Overlap", + "Value": "11" + }, + { + "Key": "Twelve Pixel Overlap", + "Value": "12" + }, + { + "Key": "Thirteen Pixels Overlap", + "Value": "13" + }, + { + "Key": "Fourteen Pixels Overlap", + "Value": "14" + }, + { + "Key": "Fifteen Pixels Overlap", + "Value": "15" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " CABC Support: ", + "Visibility": "", + "Data": [ + "52", + "CABC_Support_03" + ], + "HelpText": "This feature helps in selecting CABC_Support.", + "WidgetValues": [ + { + "Key": "Disabled", + "Value": "0" + }, + { + "Key": "Enabled", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " CABC On/Off Commands: ", + "Visibility": "", + "Data": [ + "52", + "CabcCmdsPort_03" + ], + "HelpText": "Select the MIPI Port for sending CABC On/Off Commands in case of Dual link MIPI panels\nThis field is ignored in single link MIPI case", + "WidgetValues": [ + { + "Key": "MIPI DSI-0", + "Value": "0" + }, + { + "Key": "MIPI DSI-1", + "Value": "1" + }, + { + "Key": "Both MIPI DSI-0 and DSI-1", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Panel PWM/BkltController On/Off Commands: ", + "Visibility": "", + "Data": [ + "52", + "PanelPwmCmdsPort_03" + ], + "HelpText": "Select the MIPI Port for sending Panel PWM/BkltController On/Off Commands in case of Dual link MIPI panels\nThis field is ignored in single link MIPI case", + "WidgetValues": [ + { + "Key": "MIPI DSI-0", + "Value": "0" + }, + { + "Key": "MIPI DSI-1", + "Value": "1" + }, + { + "Key": "Both MIPI DSI-0 and DSI-1", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " RGB/BGR Panel Selection: ", + "Visibility": "", + "Data": [ + "52", + "RgbFlip_03" + ], + "HelpText": "Select if the panel is RGB or BGR", + "WidgetValues": [ + { + "Key": "RGB Panel", + "Value": "0" + }, + { + "Key": "BGR Panel", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Number Of Data Lanes: ", + "Visibility": "", + "Data": [ + "52", + "Number_Of_Lanes_03" + ], + "HelpText": "This feature allows to select number of data lanes going to use for MIPI DSI", + "WidgetValues": [ + { + "Key": "1", + "Value": "0" + }, + { + "Key": "2", + "Value": "1" + }, + { + "Key": "3", + "Value": "2" + }, + { + "Key": "4", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Sending Bus Turn Around (BTA): ", + "Visibility": "", + "Data": [ + "52", + "Bta_Disable_03" + ], + "HelpText": "Enable or Disable sending Bus Turn Around to the Peripheral", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "0" + }, + { + "Key": "Disabled", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Escape Clock: ", + "Visibility": "", + "Data": [ + "52", + "EscapeClk_03" + ], + "HelpText": "This feature helps to select frequency of Escape Clk.", + "WidgetValues": [ + { + "Key": "20 MHz", + "Value": "0" + }, + { + "Key": "10 MHz", + "Value": "1" + }, + { + "Key": "5 MHz", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " EoT Packet Transmission: ", + "Visibility": "", + "Data": [ + "52", + "EoTpSupport_03" + ], + "HelpText": "This feature helps to either enable or disable EoT packet Transmission", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "0" + }, + { + "Key": "Disabled", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Clock Stop Feature: ", + "Visibility": "", + "Data": [ + "52", + "ClockStop_03" + ], + "HelpText": "To enable or disable clock stopping feature during BLLP timing in a MIPI DPI (video) mode", + "WidgetValues": [ + { + "Key": "Disabled", + "Value": "0" + }, + { + "Key": "Enabled", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " LP Clock During LPM: ", + "Visibility": "", + "Data": [ + "52", + "LpClockDuringLpm_03" + ], + "HelpText": "In continuous clock mode (Clock Stop Feature disabled), Clock lane will always be in HS mode.\nIf this feature is enabled, Clock lane also goes to LP state once per frame during the mandated data lane LPM\nin MIPI DSI DPI (video) mode", + "WidgetValues": [ + { + "Key": "Disabled", + "Value": "0" + }, + { + "Key": "Enabled", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Blanking During BLLP: ", + "Visibility": "", + "Data": [ + "52", + "BlankingDuringBllp_03" + ], + "HelpText": "This feature helps to send Blanking packets during BLLP regions in a MIPI DSI DPI (video) mode.", + "WidgetValues": [ + { + "Key": "Disabled", + "Value": "0" + }, + { + "Key": "Enabled", + "Value": "1" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " TClkPrepare: ", + "Visibility": "", + "Data": [ + "52", + "TClkPrepare_03" + ], + "HelpText": "This feature allows to enter TClkPrepare in ns.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " TClkTrail: ", + "Visibility": "", + "Data": [ + "52", + "TClkTrail_03" + ], + "HelpText": "This feature allows to enter TClkTrail in ns.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " TClkPrepare + TClkZero: ", + "Visibility": "", + "Data": [ + "52", + "TClkPrepareTClkZero_03" + ], + "HelpText": "This feature allows to enter TClkPrepare + TClkZero in ns.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " THsPrepare: ", + "Visibility": "", + "Data": [ + "52", + "THsPrepare_03" + ], + "HelpText": "This feature allows to enter THsPrepare in ns.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " THsTrail: ", + "Visibility": "", + "Data": [ + "52", + "THsTrail_03" + ], + "HelpText": "This feature allows to enter THsTrail in ns.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " THsPrepare + THsZero: ", + "Visibility": "", + "Data": [ + "52", + "THsPrepareTHsZero_03" + ], + "HelpText": "This feature allows to enter THsPrepare + THsZero in ns.", + "WidgetValues": [] + }, + { + "WidgetType": "Label", + "WidgetName": "MIPI DSI Panel Power On/Off Sequence(delays)", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Power-Up Delay: ", + "Visibility": "", + "Data": [ + "52", + "PowerUpDelay_03" + ], + "HelpText": "Delay to be given after panel power up in 100uS", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Data Turn-On To Panel Backlight Enable Delay: ", + "Visibility": "", + "Data": [ + "52", + "DataTurnOnToPanelBacklightEnableDelay_03" + ], + "HelpText": "Delay to be given after MIPI DATA TURN ON and before backlight enabling in 100uS", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Pwm-On To Backlight Enable Delay: ", + "Visibility": "", + "Data": [ + "52", + "Mipi_PwmOn_To_Bklt_Enable_Delay_03" + ], + "HelpText": "Delay to be given after PWM-On and before Backlight Enable in 100uS\nDelay from PWM-On to Backlight Enable is included in delay from Data Turn-On to Panel Backlight Enable.\nSo it is expected that delay from PWM-On to Backlight Enable is less than the delay from Data Turn-On to Panel Backlight Enable.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Backlight Disable To Pwm-Off Delay: ", + "Visibility": "", + "Data": [ + "52", + "Mipi_Bklt_Disable_To_PwmOff_Delay_03" + ], + "HelpText": "Delay to be given after Backlight Disable and before Pwm-Off in 100uS\nDelay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to Data Turn-Off.\nSo it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to Data Turn-Off.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Backlight Disable To Data Turn-Off Delay: ", + "Visibility": "", + "Data": [ + "52", + "BacklightOffToDataTurnOffDelay_03" + ], + "HelpText": "Delay to be given after Backlight Disable and before MIPI DATA TURN OFF in 100uS", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Power-Down Delay: ", + "Visibility": "", + "Data": [ + "52", + "PowerDownDelay_03" + ], + "HelpText": "Delay to be given before panel power down in 100uS", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Power-Cycle Delay: ", + "Visibility": "", + "Data": [ + "52", + "PowerCycleDelay_03" + ], + "HelpText": "Delay to be given before panel power up and after panel power down in 100uS", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + } + ] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-4", + "PageName": "Panel #04", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "LabelHeading", + "WidgetName": "Common LFP Features", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryAsci", + "WidgetName": " LFP Panel Name: ", + "Visibility": "", + "Data": [ + "42", + "Panel_Name_04" + ], + "HelpText": "This feature defines the LFP panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Target X-Res: ", + "Visibility": "", + "Data": [ + "42", + "Panel_Width_04" + ], + "HelpText": "This value specifies the Target X-Resolution for this panel.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Target Y-Res: ", + "Visibility": "", + "Data": [ + "42", + "Panel_Height_04" + ], + "HelpText": "This value specifies the Target Y-Resolution for this panel.", + "WidgetValues": [] + }, + { + "WidgetType": "LabelHeading", + "WidgetName": " DPS Panel Type Features", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Seamless DRRS Minimum Refresh Rate (Hz): ", + "Visibility": "", + "Data": [ + "42", + "Seamless_DRRS_Min_RR_04" + ], + "HelpText": "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\nNote: Graphics driver will use this field only when EDID support is disabled in VBT configuration.", + "WidgetValues": [] + }, + { + "WidgetType": "LabelHeading", + "WidgetName": " BackLight Technology Type Features", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " BackLight Technology: ", + "Visibility": "", + "Data": [ + "40", + "Blt_Control_04" + ], + "HelpText": "This feature allows OEM to select the Backlight Technology.", + "WidgetValues": [ + { + "Key": "LED Backlight", + "Value": "2" + }, + { + "Key": "CCFL Backlight", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Panel Rotation: ", + "Visibility": "", + "Data": [ + "40", + "Panel_Rotation_04" + ], + "HelpText": "This feature specifies the Panel Rotation of LFP panel used.", + "WidgetValues": [ + { + "Key": "0 degree", + "Value": "0" + }, + { + "Key": "180 degree", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Panel Position: ", + "Visibility": "", + "Data": [ + "40", + "Panel_Position_04" + ], + "HelpText": "This feature specifies the Panel Position of LFP panel used.", + "WidgetValues": [ + { + "Key": "Inside Shell", + "Value": "0" + }, + { + "Key": "Outside Shell", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Dual LFP Port Sync: ", + "Visibility": "", + "Data": [ + "42", + "EnablePortSync_Bit_04" + ], + "HelpText": "This feature will allow users to disable/enable Dual LFP Port Sync and it is applicable for DDI-A, DDI-B in case of eDP and DSI-0, DSI-1 in case of MIPI. \r\n.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " GPU Dithering for Banding artifacts: ", + "Visibility": "", + "Data": [ + "42", + "EnableDithering_Bit_04" + ], + "HelpText": "This field can be used to enable dithering from the source side for reducing banding artifacts on the visual quality features like DPST.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "Button", + "WidgetName": "Power Features", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Generic DTD Timings", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "LFP PnP ID Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Backlight Control Parameters", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Chromaticity Control", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "VESA DSC Parameters", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "LabelHeading", + "WidgetName": "Integrated MIPI DSI Settings", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:5120 or Block:2, Field:LFP2_Device_Class, Value:5120", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "MIPI Display Settings", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:5120 or Block:2, Field:LFP2_Device_Class, Value:5120", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "LabelHeading", + "WidgetName": "Integrated eDP Settings", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "eDP Fast Link Training Configuration Parameters", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "eDP Panel Power Sequencing Parameters", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Edp Max Port Link Rate (in 200 Khz): ", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [ + "27", + "eDP_Max_Port_Link_Rate_04" + ], + "HelpText": "This field specifies EDP Max Port Link Rate supported by the port in unit of 200KHz.\nDefault value would be \"0\", in which case Display Drivers should consider EDP Max Port Link Rate to be the Platform supported Max Link Rate.\nOnly when OEM's need to limit to particular Link Rate can enter the value as mentioned in below table.\n\nNote:\n1) OEM's need to enter the values mentioned from below table only.\n2) If value entered is not matching with any of the below values then Platform supported Max Link Rate should be considere as EDP Max Port Link Rate by the display drivers.\n3) In case of EDP Fast Link Training Params(FLT), if user enters FLT Link Rate value greater than the \"eDP Max Port Link Rate\" then we need to use \n Fast Link training Link Rate = MIN (FLT Link Rate , eDP Max Port Link Rate)\n---------------------------------------------------------\n|\tLink Rate(Gbps)\t|\t Value to enter in text field\t|\n|\t \t\t|\t in terms of 200KHZ \t|\n---------------------------------------------------------\n|\t 1.62 \t\t|\t 8100 \t|\n|\t 2.16 \t\t|\t 10800 \t|\n|\t 2.43 \t\t|\t 12150 \t|\n|\t 2.7 \t\t|\t 13500 \t|\n|\t 3.24 \t\t|\t 16200 \t|\n|\t 3.78 \t\t|\t 18900 \t|\n|\t 4.32 \t\t|\t 21600 \t|\n|\t 5.4 \t\t|\t 27000 \t|\n|\t 6.48 \t\t|\t 32400 \t|\n|\t 6.75 \t\t|\t 33750 \t|\n|\t 8.1 \t\t|\t 40500 \t|\n", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Panel Color Depth: ", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [ + "27", + "eDP_Panel_Color_Depth_04" + ], + "HelpText": "This feature specifies the color depth of eDP panel used.", + "WidgetValues": [ + { + "Key": "18-bit Color Depth", + "Value": "0" + }, + { + "Key": "24-bit Color Depth", + "Value": "1" + }, + { + "Key": "30-bit Color Depth", + "Value": "2" + }, + { + "Key": "36-bit Color Depth", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Select VSwing/Pre-Emphasis table : ", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [ + "27", + "eDP_VswingPreEmph_4" + ], + "HelpText": "This feature selects the VSwing Pre-Emphasis setting table to be used. For Tigerlake, based on the selection respective table will be used.\nTables for Tigerlake:\nLow Power VSwing Pre-Emphasis Setting Table:\nFor HBR2:\n\t\t\t\t\t\t Pre-Emphasis (db)\n\t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\nVoltage \t\t Level-0/200mV \t\t 200mV, 0.0db \t\t 200mV, 1.9db \t\t 200mV, 3.5db \t\t 200mV, 4.9db\nSwing \t\t Level-1/250mV \t\t 250mV, 0.0db \t\t 250mV, 1.6db \t\t 250mV, 2.9db \t\t N/A\n(mV) \t\t Level-2/300mV \t\t 300mV, 0.0db \t\t 300mV, 1.3db \t\t N/A \t\t N/A\n\t\t Level-3/350mV \t\t 350mV, 0.0db \t\t N/A \t\t N/A \t\t N/A\n\n\nFor HBR3:\n\t\t\t\t\t\t Pre-Emphasis (db)\n\t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\nVoltage \t\t Level-0/350mV \t\t 350mV, 0.0db \t\t 350mV, 3.1db \t\t 350mV, 6.0db \t\t 350mV, 8.2db\nSwing \t\t Level-1/500mV \t\t 500mV, 0.0db \t\t 500mV, 2.9db \t\t 500mV, 5.1db \t\t N/A\n(mV) \t\t Level-2/650mV \t\t 650mV, 0.6db \t\t 600mV, 3.5db \t\t N/A \t\t N/A\n\t\t Level-3/900mV \t\t 900mV, 0.0db \t\t N/A \t\t N/A \t\t N/A\n\n\nDefault VSwing Pre-Emphasis Setting Table:\nFor HBR:\n\t\t\t\t\t\t Pre-Emphasis (db)\n\t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\nVoltage \t\t Level-0/350mV \t\t 350mV, 0.0db \t\t 350mV, 3.1db \t\t 350mV, 6.0db \t\t 350mV, 8.2db\nSwing \t\t Level-1/500mV \t\t 500mV, 0.0db \t\t 500mV, 2.9db \t\t 500mV, 5.1db \t\t N/A\n(mV) \t\t Level-2/650mV \t\t 650mV, 0.6db \t\t 600mV, 3.5db \t\t N/A \t\t N/A\n\t\t Level-3/900mV \t\t 900mV, 0.0db \t\t N/A \t\t N/A \t\t N/A\n\n\nFor HBR2:\n\t\t\t\t\t\t Pre-Emphasis (db)\n\t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\nVoltage \t\t Level-0/350mV \t\t 350mV, 0.0db \t\t 350mV, 3.1db \t\t 350mV, 6.0db \t\t 350mV, 8.2db\nSwing \t\t Level-1/500mV \t\t 500mV, 0.0db \t\t 500mV, 2.9db \t\t 500mV, 5.1db \t\t N/A\n(mV) \t\t Level-2/650mV \t\t 650mV, 0.6db \t\t 600mV, 3.5db \t\t N/A \t\t N/A\n\t\t Level-3/900mV \t\t 900mV, 0.0db \t\t N/A \t\t N/A \t\t N/A", + "WidgetValues": [ + { + "Key": "Default VSwing/Pre-Emphasis Table", + "Value": "1" + }, + { + "Key": "Low Power VSwing/Pre-Emphasis Table", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " eDP Spread Spectrum Clock: ", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [ + "40", + "Enable_SSC04" + ], + "HelpText": "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Pixel Overlap Count: ", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [ + "42", + "PixelOverlapCount_04" + ], + "HelpText": "Select the number of Pixels to be overlapped per half of Scanline while using Edp Multi-SST(MSO) feature.", + "WidgetValues": [ + { + "Key": "Zero Pixel Overlap", + "Value": "0" + }, + { + "Key": "One Pixel Overlap", + "Value": "1" + }, + { + "Key": "Two Pixel Overlap", + "Value": "2" + }, + { + "Key": "Three Pixel Overlap", + "Value": "3" + }, + { + "Key": "Four Pixel Overlap", + "Value": "4" + }, + { + "Key": "Five Pixel Overlap", + "Value": "5" + }, + { + "Key": "Six Pixel Overlap", + "Value": "6" + }, + { + "Key": "Seven Pixel Overlap", + "Value": "7" + }, + { + "Key": "Eight Pixel Overlap", + "Value": "8" + } + ] + }, + { + "WidgetType": "Button", + "WidgetName": "PSR Feature", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Apical Feature", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [], + "HelpText": "", + "WidgetValues": [] + } + ], + "NestedPages": [ + { + "Type": "Block", + "Block": { + "PageNum": "5-2-4-1", + "PageName": "eDP Panel Power Sequencing Parameters", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " T3 optimization: ", + "Visibility": "", + "Data": [ + "27", + "eDP_T3_Optimization_04" + ], + "HelpText": "This feature enables or disables T3 optimization.\nWhen enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\nWhen disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "LCDVCC to HPD high delay (T3): ", + "Visibility": "", + "Data": [ + "27", + "eDP_Vcc_To_Hpd_Delay_04" + ], + "HelpText": "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\nValid Range: 0 to 200msec", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Valid video data to Backlight Enable delay (T8): ", + "Visibility": "", + "Data": [ + "27", + "eDP_DataOn_To_BkltEnable_Delay_04" + ], + "HelpText": "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\nT8 is inclusive of T7.\nValid Range of T7: 0 to 50msec", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "PWM-On To Backlight Enable delay: ", + "Visibility": "", + "Data": [ + "27", + "eDP_PwmOn_To_Bklt_Enable_Delay_04" + ], + "HelpText": "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\nDelay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\nSo it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Backlight Disable to PWM-Off delay: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Bklt_Disable_To_PwmOff_Delay_04" + ], + "HelpText": "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\nDelay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\nSo it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Backlight Disable to End of Valid video data delay (T9): ", + "Visibility": "", + "Data": [ + "27", + "eDP_BkltDisable_To_DataOff_Delay_04" + ], + "HelpText": "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "End of Valid video data to Power-Off delay (T10): ", + "Visibility": "", + "Data": [ + "27", + "eDP_DataOff_To_PowerOff_Delay_04" + ], + "HelpText": "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\nValid Range: 0 to 500 msec", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Power-off time (T12): ", + "Visibility": "", + "Data": [ + "27", + "eDP_PowerCycle_Delay_04" + ], + "HelpText": "Using this field Power-off time can be specified in 100uS.", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-4-2", + "PageName": "eDP Fast Link Training Configuration Parameters", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Is FastLinkTraining Feature Supported: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Fast_Link_Training_Supported_04" + ], + "HelpText": "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled.", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Data Rate: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Fast_Link_Training_Data_Rate_04" + ], + "HelpText": "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. It will be used if the sink indicates that no aux handshake is required during link training.\n\nIn case of EDP Fast Link Training Params(FLT), if user enters FLT Link Rate value greater than the \"eDP Max Port Link Rate\" then driver would use \n Fast Link training Link Rate = MIN (FLT Link Rate , eDP Max Port Link Rate).", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Lane Count: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Link_LaneCount_04" + ], + "HelpText": "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. It will be used if the sink indicates that no aux handshake is required during link training.", + "WidgetValues": [ + { + "Key": "x1", + "Value": "0" + }, + { + "Key": "x2", + "Value": "1" + }, + { + "Key": "x4", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Pre-Emphasis: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Link_PreEmp_04" + ], + "HelpText": "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. It will be used if the sink indicates that no aux handshake is required during link training.", + "WidgetValues": [ + { + "Key": "Level-0", + "Value": "0" + }, + { + "Key": "Level-1", + "Value": "1" + }, + { + "Key": "Level-2", + "Value": "2" + }, + { + "Key": "Level-3", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Voltage Swing: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Link_Vswing_04" + ], + "HelpText": "This feature allows for the selection of the Voltage Swing value for the embedded DP link. It will be used if the sink indicates that no aux handshake is required during link training.", + "WidgetValues": [ + { + "Key": "Swing-0", + "Value": "0" + }, + { + "Key": "Swing-1", + "Value": "1" + }, + { + "Key": "Swing-2", + "Value": "2" + }, + { + "Key": "Swing-3", + "Value": "3" + } + ] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-4-3", + "PageName": "PSR Feature", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Full Link enable: ", + "Visibility": "", + "Data": [ + "9", + "PSR_FullLink_Enable_04" + ], + "HelpText": "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state.", + "WidgetValues": [ + { + "Key": "No", + "Value": "0" + }, + { + "Key": "Yes", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Require AUX to wake up: ", + "Visibility": "", + "Data": [ + "9", + "PSR_Require_AUX2Wakeup_04" + ], + "HelpText": "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used.", + "WidgetValues": [ + { + "Key": "No", + "Value": "0" + }, + { + "Key": "Yes", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Lines to wait before link standby: ", + "Visibility": "", + "Data": [ + "9", + "PSR_Lines2Wait_B4LinkS3_04" + ], + "HelpText": "This field determines Lines to wait before link standby\n0 lines to wait (Default)\n1 lines to wait\n4 lines to wait\n8 lines to wait\nOthers Reserved", + "WidgetValues": [ + { + "Key": "0 lines to wait", + "Value": "0" + }, + { + "Key": "1 lines to wait", + "Value": "1" + }, + { + "Key": "4 lines to wait", + "Value": "2" + }, + { + "Key": "8 lines to wait", + "Value": "3" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Idle frames to wait: ", + "Visibility": "", + "Data": [ + "9", + "PSR_IdleFrames2Wait_04" + ], + "HelpText": "Idle frames to wait for PSR enable.\nAllowed values 0-15. Default value is 0.", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Clock Recovery Time: ", + "Visibility": "", + "Data": [ + "9", + "PSR_TP1_WaitTime_04" + ], + "HelpText": "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)", + "WidgetValues": [ + { + "Key": "500 usec", + "Value": "0" + }, + { + "Key": "100 usec", + "Value": "1" + }, + { + "Key": "2.5 msec", + "Value": "2" + }, + { + "Key": "0 (Skip)", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Channel Equalization Time for PSR1 panel: ", + "Visibility": "", + "Data": [ + "9", + "PSR1_TP_2_3_4_WaitTime_04" + ], + "HelpText": "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) or TP4(Training Pattern4) time during PSR1 exit(wake up)", + "WidgetValues": [ + { + "Key": "500 usec", + "Value": "0" + }, + { + "Key": "100 usec", + "Value": "1" + }, + { + "Key": "2.5 msec", + "Value": "2" + }, + { + "Key": "0 (Skip)", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Channel Equalization Time for PSR2 panel: ", + "Visibility": "", + "Data": [ + "9", + "PSR2_TP_2_3_4_WaitTime_04" + ], + "HelpText": "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) or TP4(Training Pattern4) time during PSR2 exit(wake up)", + "WidgetValues": [ + { + "Key": "500 usec", + "Value": "0" + }, + { + "Key": "100 usec", + "Value": "1" + }, + { + "Key": "2.5 msec", + "Value": "2" + }, + { + "Key": "50 usec", + "Value": "3" + } + ] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-4-4", + "PageName": "Apical Feature", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Apical Assertive Display IP: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Apical_Display_Ip_Enable_04" + ], + "HelpText": "This field enables/disables the Apical Assertive Display IP for this panel.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Panel OUI (IEEE OUI): ", + "Visibility": "", + "Data": [ + "27", + "eDP_Panel_Oui_04" + ], + "HelpText": "This field specifies the Apical IP specific Panel OUI field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " DPCD Base Address: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Dpcd_Base_Address_04" + ], + "HelpText": "This field specifies the Apical IP specific DPCD base address field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " DPCD Irdidix Control 0: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Dpcd_Irdidix_Control0_04" + ], + "HelpText": "This field specifies the Apical IP specific DPCD Irdidix control 0 field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " DPCD Option Select: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Dpcd_Option_Select_04" + ], + "HelpText": "This field specifies the Apical IP specific DPCD option select field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " DPCD Backlight: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Dpcd_Backlight_04" + ], + "HelpText": "This field specifies the Apical IP specific backlight value.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Ambient Light: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Ambient_Light_04" + ], + "HelpText": "This field specifies the Apical IP specific Ambient light value.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Backlight scale: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Backlight_Scale_04" + ], + "HelpText": "This field specifies the Apical IP specific backlight scale field.", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-4-5", + "PageName": "Power Features", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Intel Display Power Saving Technology (DPST) (Mobile only): ", + "Visibility": "", + "Data": [ + "44", + "DPST_Enable_04" + ], + "HelpText": "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled.\nIntel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power.\nNote: This technology is only active when the system is running in battery mode and the LFP is the only active display device.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Intel Display Refresh Rate Switching (DRRS) (Mobile only): ", + "Visibility": "", + "Data": [ + "44", + "DRRS_Enable_04" + ], + "HelpText": "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Edge Luminance Profile (ELP) : ", + "Visibility": "", + "Data": [ + "44", + "ELP_Enable_04" + ], + "HelpText": "This feature determines whether the ELP feature is enabled or disabled.\nEdge Luminance Profile (ELP) is a panel technology which reduce luminance on the edge of screen to save panel power.\nNote:This technology cannot co-exist with DPST and OPST ((i.e.) OPST, DPST and ELP cannot exist together.They are all mutually exclusive to each other.)", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " OLED Power Saving Technology (OPST) : ", + "Visibility": "", + "Data": [ + "44", + "OPST_Enable_04" + ], + "HelpText": "This feature determines whether the OPST feature is enabled or disabled.\nOLED Power Saving Technology (OPST) is a panel technology which saves power by intelligent, adaptive dimming of midrange pixel values more aggressively than the extremes without compromising the viewability.\nNote: This technology cannot co-exist with ELP and DPST ((i.e.) OPST, DPST and ELP cannot exist together.They are all mutually exclusive to each other.)", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Dynamic Media Refresh Rate Switching Enable/Disable ", + "Visibility": "", + "Data": [ + "44", + "DMRRS_Enable_04" + ], + "HelpText": "This feature determines whether Dynamic media refresh rate switching is to be enabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Enable Display Lace Support: ", + "Visibility": "", + "Data": [ + "44", + "LACE_Enable_04" + ], + "HelpText": "This feature, when enabled, will set Display Lace Support otherwise, the functionality will be disabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Panel Self Refresh (PSR): ", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [ + "44", + "PSR_Enable_04" + ], + "HelpText": "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Assertive Display Technology Enable/Disable: ", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [ + "44", + "ADT_Enable_04" + ], + "HelpText": "This feature determines whether Assertive display technology is to be enabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Intel Automatic Display Brightness (ADB) (Mobile only): ", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [ + "44", + "ADB_Enable_04" + ], + "HelpText": "This feature determines whether Intel Automatic Display Brightness is to be enabled. Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) depending on the current ambient light environment.\nWhen enabled, the driver and VBIOS will control the backlight brightness of the LFP depending on the ambient environment if and only if the LFP is the only active display. When disabled, the driver will perform no action.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "EDP 4k/2k HOBL Feature: ", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [ + "44", + "eDP_4k_2k_HOBL_feature_Enable_04" + ], + "HelpText": "This feature will allow users to disable/enable the edp 4k/2k HOBL(Hours Of Battery Life) feature by programming relevant registers specific for a platform.\r\n.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Default Display LACE Enabled status: ", + "Visibility": "", + "Data": [ + "44", + "LACE_Status_04" + ], + "HelpText": "This feature, when enabled, will set Default Display LACE Enabled status otherwise, the functionality will be disabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "DPST Aggressiveness Level: ", + "Visibility": "", + "Data": [ + "44", + "DPST_Aggressiveness_Profile_04" + ], + "HelpText": "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n1 (Maximum Quality with No DPST)\n2\n3\n4\n5\n6 (Maximum Battery)", + "WidgetValues": [ + { + "Key": "1 - Maximum Quality with No DPST", + "Value": "1" + }, + { + "Key": "2", + "Value": "2" + }, + { + "Key": "3", + "Value": "3" + }, + { + "Key": "4", + "Value": "4" + }, + { + "Key": "5", + "Value": "5" + }, + { + "Key": "6 - Maximum Battery", + "Value": "6" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "LACE Aggressiveness Level: ", + "Visibility": "", + "Data": [ + "44", + "LACE_Aggressiveness_Profile_04" + ], + "HelpText": "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\nMinimum 0\nModerate 1\nHigh 2", + "WidgetValues": [ + { + "Key": "Minimum", + "Value": "0" + }, + { + "Key": "Moderate", + "Value": "1" + }, + { + "Key": "High", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "ELP Aggressiveness Level: ", + "Visibility": "", + "Data": [ + "44", + "ELP_Aggressiveness_Profile_04" + ], + "HelpText": "This feature allows for the selection of ELP Aggressiveness level for this Panel Type.\nMinimum Power Savings\nMedium Power Savings \nMaximum Power Savings", + "WidgetValues": [ + { + "Key": "Minimum Power Savings", + "Value": "0" + }, + { + "Key": "Medium Power Savings", + "Value": "1" + }, + { + "Key": "Maximum Power Savings", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "OPST Aggressiveness Level: ", + "Visibility": "", + "Data": [ + "44", + "OPST_Aggressiveness_Profile_04" + ], + "HelpText": "This feature allows for the selection of OPST Aggressiveness level for this Panel Type.\nMinimum Power Savings\nMedium Power Savings \nMaximum Power Savings", + "WidgetValues": [ + { + "Key": "Minimum Power Savings", + "Value": "0" + }, + { + "Key": "Medium Power Savings", + "Value": "1" + }, + { + "Key": "Maximum Power Savings", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Default Display VRR Enabled status: ", + "Visibility": "", + "Data": [ + "44", + "VRR_Status_04" + ], + "HelpText": "VRR (Variable Refresh Rate) is a feature that can continuously and seamlessly vary Refresh Rate on the fly, on displays that support Variable Refresh rate Technologies.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-4-6", + "PageName": "Generic DTD Timings", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Pixel Clock in KHz: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_Pixel_CLK_04" + ], + "HelpText": "Pixel Clock (in KHz) Range from 0.001 to 4294967.295 MP/s.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Active: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_Active_04" + ], + "HelpText": "Horizontal Active Image Pixels Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Active: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_Active_04" + ], + "HelpText": "Vertical Active Image Lines Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Blank: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_Blank_04" + ], + "HelpText": "Horizontal Blank Pixels Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Blank: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_Blank_04" + ], + "HelpText": "Vertical Blank lines Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Front Porch: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_FrontPorch_04" + ], + "HelpText": "Horizontal Front Porch Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Front Porch: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_FrontPorch_04" + ], + "HelpText": "Vertical Front Porch Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Sync: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_Sync_04" + ], + "HelpText": "Horizontal Sync Width Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Sync: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_Sync_04" + ], + "HelpText": "Vertical Sync Width Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Image Size: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_Image_Size_04" + ], + "HelpText": "Horizontal Addressable Video Image Size in mm represented by 16bits. Image size multiplier 1.00 mm precision.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Image Size: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_Image_Size_04" + ], + "HelpText": "Vertical Addressable Video Image Size in mm represented by 16bits. Image size multiplier 1.00 mm precision.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryBin", + "WidgetName": "Common Flag: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_Common_Flag_04" + ], + "HelpText": "Common DTD Flags:\nBit 7 : Horizontal Sync Polarity\n1 : Positive\n0 : Negative\nBit 6 : Vertical Sync polarity\n1 : Positive\n0 : Negative\nBit 5 - 0: Reserved (Default value 0)", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-4-7", + "PageName": "LFP PnP ID Table", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Table", + "WidgetName": "", + "Visibility": "", + "Data": [ + "42", + "LFP_Panel_PnP_ID_04" + ], + "HelpText": "This feature allows the 10 bytes of EDID Vendor/Product ID starting at offset 08h to be used as a PnP ID.\n\nTable Definition:\n\tWord: ID Manufacturer Name\n\tWord: ID Product Code\n\tDWord: ID Serial Number\n\tByte: Week of Manufacture\n\tByte: Year of Manufacture", + "WidgetValues": [ + { + "ColumnName": "PnP ID", + "SizeinBytes": "1" + } + ] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-4-8", + "PageName": "Backlight Control Parameters", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Inverter Type: ", + "Visibility": "", + "Data": [ + "43", + "BLC_Inv_Type_04" + ], + "HelpText": "This feature allows for the selection of the Backlight Inverter type that is to be used to control the backlight brightness of the LFP.\nWhen PWM is selected, the driver and VBIOS will control the backlight brightness via the integrated PWM solution for the applicable chipsets.\nWhen None/External is selected, the system BIOS will control the backlight brightness via the external solution.", + "WidgetValues": [ + { + "Key": "None/External", + "Value": "0" + }, + { + "Key": "PWM", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Pwm Source Selection: ", + "Visibility": "", + "Data": [ + "43", + "Lfp_Pwm_Source_Selection_04" + ], + "HelpText": "If panel supports 'Intel HDR AUX Interface', it will always be chosen by default. If not, value in 'PWM Source Selection' will be used", + "WidgetValues": [ + { + "Key": "PWM From Display Engine", + "Value": "2" + }, + { + "Key": "PWM From LCD Panel", + "Value": "3" + }, + { + "Key": "Panel Driver Interface", + "Value": "4" + }, + { + "Key": "VESA eDP AUX Interface", + "Value": "5" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Pwm Controller Selection: ", + "Visibility": "", + "Data": [ + "43", + "Lfp_Pwm_Controller_Selection_04" + ], + "HelpText": "This field allows to select the PWM Controller to be used for the selected Local Flat Panel.This field allows to select the PWM Controller to be used for the selected Local Flat Panel.If Two LFPs are connected then PWM0 and PWM1 must be selected accordingly.", + "WidgetValues": [ + { + "Key": "PWM0", + "Value": "0" + }, + { + "Key": "PWM1", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Inverter Polarity: ", + "Visibility": "", + "Data": [ + "43", + "BLC_Inv_Polarity_04" + ], + "HelpText": "This feature allows the backlight inverter polarity to be specified.\nNormal means 0 value is minimum brightness.\nInverted means 0 value is maximum brightness.", + "WidgetValues": [ + { + "Key": "Normal", + "Value": "0" + }, + { + "Key": "Inverted", + "Value": "1" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Minimum Brightness: ", + "Visibility": "", + "Data": [ + "43", + "Post_Min_Brightness_04" + ], + "HelpText": "This feature allows defining the absolute minimum backlight brightness. The driver will never decrease the backlight less than this value. The value must be specified using normal polarity semantics. The value should range from 0 to 255 if the brightness precision bit is chosen to be 8, and it should range from 0 to 65535 if the precision bit is chosen to be 16.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "POST Backlight Intensity: ", + "Visibility": "", + "Data": [ + "43", + "Post_Brightness_04" + ], + "HelpText": "This feature is used to set default backlight brightness value of the panel at POST. The value should range from 0 to 255 if the bit precision is chosen to be 8 and it should range from 0 to 65535 if the brightness bit precision is chosent to be 16.", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Brightness Precision Bits: ", + "Visibility": "", + "Data": [ + "43", + "BrightnessPrecisionBits_04" + ], + "HelpText": "This field represents the range of brightness in terms of bit precision.\n 8 = Brightness range of 0 to 255.\n 16 = Brightness range of 0 to 65535", + "WidgetValues": [ + { + "Key": "8", + "Value": "8" + }, + { + "Key": "16", + "Value": "16" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "PWM Inverter Frequency (Hz): ", + "Visibility": "", + "Data": [ + "43", + "PWM_Frequency_04" + ], + "HelpText": "This feature allows for the definition of the frequency needed for PWM Inverter.\nNote: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Intel HDR DPCD Refresh Timeout (unit - 10 micro seconds): ", + "Visibility": "", + "Data": [ + "43", + "HdrDpcdRefreshTimeout_04" + ], + "HelpText": "This field allows to configure the refresh timeout of Intel HDR DPCDs for different TCON Vendors.\nNote:\n\tThe value is in units of 10 microseconds.\n\tThe range (entered as a decimal number), for the timeout is 0-65535", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-4-9", + "PageName": "Chromaticity Control", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Chromaticity Control Feature: ", + "Visibility": "", + "Data": [ + "46", + "Chromacity_Enable_04" + ], + "HelpText": "This bit enables Chromaticity feature.\nIf this bit is enabled, EDID values for chromaticity will be used, else feature is disabled.\nFeature will be supported for Panels that support EDID version 1.4 or higher.\nPlease refer to section 3.7 of EDID Specification 1.4.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Override the EDID values: ", + "Visibility": "", + "Data": [ + "46", + "Override_EDID_Data_04" + ], + "HelpText": "This option when enabled along with Chromaticity feature will override EDID values through following VBT data", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Red_Green_bits (Bits 1:0 at 19h): ", + "Visibility": "", + "Data": [ + "46", + "Red_Green_04" + ], + "HelpText": "Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Blue_White_bits (Bits 1:0 at 1Ah): ", + "Visibility": "", + "Data": [ + "46", + "Blue_White_04" + ], + "HelpText": "Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Red_x (Bits 9:2 at 1Bh): ", + "Visibility": "", + "Data": [ + "46", + "Red_x_04" + ], + "HelpText": "Bits 9:2 of red color x coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Red_y (Bits 9:2 at 1Ch): ", + "Visibility": "", + "Data": [ + "46", + "Red_y_04" + ], + "HelpText": "Bits 9:2 of red color y coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Green_x (Bits 9:2 at 1Dh): ", + "Visibility": "", + "Data": [ + "46", + "Green_x_04" + ], + "HelpText": "Bits 9:2 of Green color x coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Green_y (Bits 9:2 at 1Eh): ", + "Visibility": "", + "Data": [ + "46", + "Green_y_04" + ], + "HelpText": "Bits 9:2 of Green color y coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Blue_x (Bits 9:2 at 1Fh): ", + "Visibility": "", + "Data": [ + "46", + "Blue_x_04" + ], + "HelpText": "Bits 9:2 of Blue color x coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Blue_y (Bits 9:2 at 20h): ", + "Visibility": "", + "Data": [ + "46", + "Blue_y_04" + ], + "HelpText": "Bits 9:2 of Blue color y coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " White_x (Bits 9:2 at 21h): ", + "Visibility": "", + "Data": [ + "46", + "White_x_04" + ], + "HelpText": "Bits 9:2 of White color x coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " White_y (Bits 9:2 at 22h): ", + "Visibility": "", + "Data": [ + "46", + "White_y_04" + ], + "HelpText": "Bits 9:2 of White color y coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Override Luminance values ", + "Visibility": "", + "Data": [ + "46", + "Override_LUM_Data_04" + ], + "HelpText": "This option when enabled along with Chromaticity feature will override luminance values following VBT values", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Minimum Luminance: ", + "Visibility": "", + "Data": [ + "46", + "MinLuminance_04" + ], + "HelpText": "Minimum luminance value.\n2 byte value, encoded in IEEE 754 half-precision binary floating point format,", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Maximum full frame luminance: ", + "Visibility": "", + "Data": [ + "46", + "MaxFullLuminance_04" + ], + "HelpText": "Maximum Full frame luminance value.\n2 byte value, encoded in IEEE 754 half-precision binary floating point format,", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Maximum Luminance: ", + "Visibility": "", + "Data": [ + "46", + "MaxLuminance_04" + ], + "HelpText": "Maximum luminance value(Relatively smaller portion of screen).\n2 byte value, encoded in IEEE 754 half-precision binary floating point format.", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Override Gamma values: ", + "Visibility": "", + "Data": [ + "46", + "Override_Gamma_Data_04" + ], + "HelpText": "This option when enabled along with Chromaticity feature will override gamma values through following VBT data", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Panel gamma: ", + "Visibility": "", + "Data": [ + "46", + "Gamma_04" + ], + "HelpText": "Value shall define the gamma range, from 1.00 to 3.54, as follows:\nField Value = (Gamma (value in float) x 100) - 100\nField values range from 00h through FFh.\nFFh = No gamma information shall be provided", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-4-10", + "PageName": "VESA DSC Parameters", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "DSC Major Version: ", + "Visibility": "", + "Data": [ + "56", + "C4_Major_Dsc_Version" + ], + "HelpText": "VESA DSC Major revision field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "DSC Minor Version: ", + "Visibility": "", + "Data": [ + "56", + "C4_Minor_Dsc_Version" + ], + "HelpText": "VESA DSC Minor revision field.", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Block prediction supported: ", + "Visibility": "", + "Data": [ + "56", + "C4_Blk_Prediction_En" + ], + "HelpText": "Sink supports block prediction as per the VESA DSC Spec.", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "RC Buffer Block size as per VESA DSC Spec: ", + "Visibility": "", + "Data": [ + "56", + "C4_RC_Block_Size" + ], + "HelpText": "RC buffer block size for a single RC buffer as defined by the VESA DSC spec.", + "WidgetValues": [ + { + "Key": "1 KB", + "Value": "0" + }, + { + "Key": "4 KB", + "Value": "1" + }, + { + "Key": "16 KB", + "Value": "2" + }, + { + "Key": "64 KB", + "Value": "3" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Number of RC buffer blocks as per VESA DSC Spec: ", + "Visibility": "", + "Data": [ + "56", + "C4_Dsc_RC_Buf_Size" + ], + "HelpText": "This field defines the number of RC buffers as per VESA DSC spec.\nThe number of RC buffers used by the software shall be (Value + 1) where Value is in range 0 to 127.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryBin", + "WidgetName": "Slices per line supported by the sink device: ", + "Visibility": "", + "Data": [ + "56", + "C4_Dsc_Slices_Per_Line" + ], + "HelpText": "This field defines the slices per line supported by the sink device.\nThe field is defined in bitmap fashion and details of each bits are as defined below:\n\tBits 31-10\t\t Bit 9\tBit 8\tBit 7\tBit 6\tBit 5\tBit 4\t Bit 3\t Bit 2\t Bit 1\t Bit 0\n\tReserved\t\t 24\t 20\t 16\t 12\t 10\t 8\t 6\t 4\t 2\t 1\nBit = 0, not supported. Bit = 1, supported\nNote: Assumption is that sink shall support all lower slices per line than maximum selected field. i.e. If it supports say 8 slices per line, it will also support 4/2/1 slices per line", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Line buffer depth as per VESA DSC Spec: ", + "Visibility": "", + "Data": [ + "56", + "C4_Line_Buffer_Depth" + ], + "HelpText": "Line buffer depth in bits as per VESA DSC spec.", + "WidgetValues": [ + { + "Key": "8 bits", + "Value": "0" + }, + { + "Key": "9 bits", + "Value": "1" + }, + { + "Key": "10 bits", + "Value": "2" + }, + { + "Key": "11 bits", + "Value": "3" + }, + { + "Key": "12 bits", + "Value": "4" + }, + { + "Key": "13 bits", + "Value": "5" + }, + { + "Key": "14 bits", + "Value": "6" + }, + { + "Key": "15 bits", + "Value": "7" + }, + { + "Key": "16 bits", + "Value": "8" + } + ] + }, + { + "WidgetType": "EntryBin", + "WidgetName": "Input compression BPC supported by the sink device: ", + "Visibility": "", + "Data": [ + "56", + "C4_Dsc_Bpc" + ], + "HelpText": "This field defines the compression input bpc supported by the sink device.\nThe field is defined in bitmap fashion and details of each bits are as defined below:\n\tBits 7-4\t Bit 3\t Bit 2\t Bit 1\t Bit 0\n\tRsvd\t 12 bpc\t 10bpc\t 8bpc\t Rsvd\nBit = 0, not supported. Bit = 1, supported\nNote: Assumption is that sink shall support all lower bpc values than the maximum selected field. i.e. If it supports say 12bpc, it will also support 10 and 8bpc as well", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Maximum supported compression BPP: ", + "Visibility": "", + "Data": [ + "56", + "C4_Dsc_Max_Bpp" + ], + "HelpText": "As of today, we are supporting 6/8/10/12 BPP for compression output.\nSelect the most appropriate BPP as supported by the sink.", + "WidgetValues": [ + { + "Key": "6 Bits per pixel", + "Value": "0" + }, + { + "Key": "8 Bits per pixel", + "Value": "1" + }, + { + "Key": "10 Bits per pixel", + "Value": "2" + }, + { + "Key": "12 Bits per pixel", + "Value": "3" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Slice height supported by the sink device: ", + "Visibility": "", + "Data": [ + "56", + "C4_Dsc_Slice_Height" + ], + "HelpText": "Slice height supported by the sink device for DSC slice.\nNote: Slice height must divide the picture height uniformly.", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-4-11", + "PageName": "MIPI Display Settings", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:5120 or Block:2, Field:LFP2_Device_Class, Value:5120", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Label", + "WidgetName": "MIPI DSI Controller Configuration Settings", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Video/Command Mode: ", + "Visibility": "", + "Data": [ + "52", + "Video_Command_Mode_04" + ], + "HelpText": "This feature helps in selecting Video/Command Mode.", + "WidgetValues": [ + { + "Key": "Video Mode", + "Value": "0" + }, + { + "Key": "Command Mode", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Packet Sequence For Video Mode: ", + "Visibility": "", + "Data": [ + "52", + "Packet_Sequence_Video_Mode_04" + ], + "HelpText": "This feature helps in selecting packet sequence for Video Mode.\nNon-burst with sync pulse\nNon-burst with sync events\nBurst mode", + "WidgetValues": [ + { + "Key": "Non-burst with sync pulse", + "Value": "1" + }, + { + "Key": "Non-burst with sync events", + "Value": "2" + }, + { + "Key": "Burst Mode", + "Value": "3" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Required Burst Mode Rate (in Kbps): ", + "Visibility": "", + "Data": [ + "52", + "RequiredBurstModeRate_04" + ], + "HelpText": "This feature allows to enter Required Burst Mode Rate in Kilo bits per sec. This should be greater than Non-Burst Mode Rate\nThis value is valid only if packet sequence for video mode is Burst Mode.", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Colour Format In Video Mode: ", + "Visibility": "", + "Data": [ + "52", + "Colour_Format_Video_Mode_04" + ], + "HelpText": "This feature helps in selecting supported colour format in Video Mode.", + "WidgetValues": [ + { + "Key": "RGB565", + "Value": "1" + }, + { + "Key": "RGB666", + "Value": "2" + }, + { + "Key": "RGB 666(Loosely Packed Format)", + "Value": "3" + }, + { + "Key": "RGB888", + "Value": "4" + }, + { + "Key": "RGB101010", + "Value": "5" + }, + { + "Key": "RGB121212", + "Value": "6" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Dual Link Support: ", + "Visibility": "", + "Data": [ + "52", + "Dual_Link_04" + ], + "HelpText": "This feature allows to select type of dual link.", + "WidgetValues": [ + { + "Key": "Dual Link Not Supported", + "Value": "0" + }, + { + "Key": "Dual Link Front Back Mode", + "Value": "1" + }, + { + "Key": "Dual Link Pixel Alternative Mode", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Pixel Overlap Count(Z-Inversion): ", + "Visibility": "", + "Data": [ + "42", + "PixelOverlapCount_04" + ], + "HelpText": "Select the number of Pixels to be overlapped per half of Scanline while using\nMIPI Dual Link Front-Back video mode.", + "WidgetValues": [ + { + "Key": "Zero Pixel Overlap", + "Value": "0" + }, + { + "Key": "One Pixel Overlap", + "Value": "1" + }, + { + "Key": "Two Pixels Overlap", + "Value": "2" + }, + { + "Key": "Three Pixels Overlap", + "Value": "3" + }, + { + "Key": "Four Pixel Overlap", + "Value": "4" + }, + { + "Key": "Five Pixel Overlap", + "Value": "5" + }, + { + "Key": "Six Pixels Overlap", + "Value": "6" + }, + { + "Key": "Seven Pixels Overlap", + "Value": "7" + }, + { + "Key": "Eight Pixel Overlap", + "Value": "8" + }, + { + "Key": "Nine Pixel Overlap", + "Value": "9" + }, + { + "Key": "Ten Pixels Overlap", + "Value": "10" + }, + { + "Key": "Eleven Pixels Overlap", + "Value": "11" + }, + { + "Key": "Twelve Pixel Overlap", + "Value": "12" + }, + { + "Key": "Thirteen Pixels Overlap", + "Value": "13" + }, + { + "Key": "Fourteen Pixels Overlap", + "Value": "14" + }, + { + "Key": "Fifteen Pixels Overlap", + "Value": "15" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " CABC Support: ", + "Visibility": "", + "Data": [ + "52", + "CABC_Support_04" + ], + "HelpText": "This feature helps in selecting CABC_Support.", + "WidgetValues": [ + { + "Key": "Disabled", + "Value": "0" + }, + { + "Key": "Enabled", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " CABC On/Off Commands: ", + "Visibility": "", + "Data": [ + "52", + "CabcCmdsPort_04" + ], + "HelpText": "Select the MIPI Port for sending CABC On/Off Commands in case of Dual link MIPI panels\nThis field is ignored in single link MIPI case", + "WidgetValues": [ + { + "Key": "MIPI DSI-0", + "Value": "0" + }, + { + "Key": "MIPI DSI-1", + "Value": "1" + }, + { + "Key": "Both MIPI DSI-0 and DSI-1", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Panel PWM/BkltController On/Off Commands: ", + "Visibility": "", + "Data": [ + "52", + "PanelPwmCmdsPort_04" + ], + "HelpText": "Select the MIPI Port for sending Panel PWM/BkltController On/Off Commands in case of Dual link MIPI panels\nThis field is ignored in single link MIPI case", + "WidgetValues": [ + { + "Key": "MIPI DSI-0", + "Value": "0" + }, + { + "Key": "MIPI DSI-1", + "Value": "1" + }, + { + "Key": "Both MIPI DSI-0 and DSI-1", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " RGB/BGR Panel Selection: ", + "Visibility": "", + "Data": [ + "52", + "RgbFlip_04" + ], + "HelpText": "Select if the panel is RGB or BGR", + "WidgetValues": [ + { + "Key": "RGB Panel", + "Value": "0" + }, + { + "Key": "BGR Panel", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Number Of Data Lanes: ", + "Visibility": "", + "Data": [ + "52", + "Number_Of_Lanes_04" + ], + "HelpText": "This feature allows to select number of data lanes going to use for MIPI DSI", + "WidgetValues": [ + { + "Key": "1", + "Value": "0" + }, + { + "Key": "2", + "Value": "1" + }, + { + "Key": "3", + "Value": "2" + }, + { + "Key": "4", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Sending Bus Turn Around (BTA): ", + "Visibility": "", + "Data": [ + "52", + "Bta_Disable_04" + ], + "HelpText": "Enable or Disable sending Bus Turn Around to the Peripheral", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "0" + }, + { + "Key": "Disabled", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Escape Clock: ", + "Visibility": "", + "Data": [ + "52", + "EscapeClk_04" + ], + "HelpText": "This feature helps to select frequency of Escape Clk.", + "WidgetValues": [ + { + "Key": "20 MHz", + "Value": "0" + }, + { + "Key": "10 MHz", + "Value": "1" + }, + { + "Key": "5 MHz", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " EoT Packet Transmission: ", + "Visibility": "", + "Data": [ + "52", + "EoTpSupport_04" + ], + "HelpText": "This feature helps to either enable or disable EoT packet Transmission", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "0" + }, + { + "Key": "Disabled", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Clock Stop Feature: ", + "Visibility": "", + "Data": [ + "52", + "ClockStop_04" + ], + "HelpText": "To enable or disable clock stopping feature during BLLP timing in a MIPI DPI (video) mode", + "WidgetValues": [ + { + "Key": "Disabled", + "Value": "0" + }, + { + "Key": "Enabled", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " LP Clock During LPM: ", + "Visibility": "", + "Data": [ + "52", + "LpClockDuringLpm_04" + ], + "HelpText": "In continuous clock mode (Clock Stop Feature disabled), Clock lane will always be in HS mode.\nIf this feature is enabled, Clock lane also goes to LP state once per frame during the mandated data lane LPM\nin MIPI DSI DPI (video) mode", + "WidgetValues": [ + { + "Key": "Disabled", + "Value": "0" + }, + { + "Key": "Enabled", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Blanking During BLLP: ", + "Visibility": "", + "Data": [ + "52", + "BlankingDuringBllp_04" + ], + "HelpText": "This feature helps to send Blanking packets during BLLP regions in a MIPI DSI DPI (video) mode.", + "WidgetValues": [ + { + "Key": "Disabled", + "Value": "0" + }, + { + "Key": "Enabled", + "Value": "1" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " TClkPrepare: ", + "Visibility": "", + "Data": [ + "52", + "TClkPrepare_04" + ], + "HelpText": "This feature allows to enter TClkPrepare in ns.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " TClkTrail: ", + "Visibility": "", + "Data": [ + "52", + "TClkTrail_04" + ], + "HelpText": "This feature allows to enter TClkTrail in ns.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " TClkPrepare + TClkZero: ", + "Visibility": "", + "Data": [ + "52", + "TClkPrepareTClkZero_04" + ], + "HelpText": "This feature allows to enter TClkPrepare + TClkZero in ns.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " THsPrepare: ", + "Visibility": "", + "Data": [ + "52", + "THsPrepare_04" + ], + "HelpText": "This feature allows to enter THsPrepare in ns.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " THsTrail: ", + "Visibility": "", + "Data": [ + "52", + "THsTrail_04" + ], + "HelpText": "This feature allows to enter THsTrail in ns.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " THsPrepare + THsZero: ", + "Visibility": "", + "Data": [ + "52", + "THsPrepareTHsZero_04" + ], + "HelpText": "This feature allows to enter THsPrepare + THsZero in ns.", + "WidgetValues": [] + }, + { + "WidgetType": "Label", + "WidgetName": "MIPI DSI Panel Power On/Off Sequence(delays)", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Power-Up Delay: ", + "Visibility": "", + "Data": [ + "52", + "PowerUpDelay_04" + ], + "HelpText": "Delay to be given after panel power up in 100uS", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Data Turn-On To Panel Backlight Enable Delay: ", + "Visibility": "", + "Data": [ + "52", + "DataTurnOnToPanelBacklightEnableDelay_04" + ], + "HelpText": "Delay to be given after MIPI DATA TURN ON and before backlight enabling in 100uS", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Pwm-On To Backlight Enable Delay: ", + "Visibility": "", + "Data": [ + "52", + "Mipi_PwmOn_To_Bklt_Enable_Delay_04" + ], + "HelpText": "Delay to be given after PWM-On and before Backlight Enable in 100uS\nDelay from PWM-On to Backlight Enable is included in delay from Data Turn-On to Panel Backlight Enable.\nSo it is expected that delay from PWM-On to Backlight Enable is less than the delay from Data Turn-On to Panel Backlight Enable.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Backlight Disable To Pwm-Off Delay: ", + "Visibility": "", + "Data": [ + "52", + "Mipi_Bklt_Disable_To_PwmOff_Delay_04" + ], + "HelpText": "Delay to be given after Backlight Disable and before Pwm-Off in 100uS\nDelay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to Data Turn-Off.\nSo it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to Data Turn-Off.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Backlight Disable To Data Turn-Off Delay: ", + "Visibility": "", + "Data": [ + "52", + "BacklightOffToDataTurnOffDelay_04" + ], + "HelpText": "Delay to be given after Backlight Disable and before MIPI DATA TURN OFF in 100uS", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Power-Down Delay: ", + "Visibility": "", + "Data": [ + "52", + "PowerDownDelay_04" + ], + "HelpText": "Delay to be given before panel power down in 100uS", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Power-Cycle Delay: ", + "Visibility": "", + "Data": [ + "52", + "PowerCycleDelay_04" + ], + "HelpText": "Delay to be given before panel power up and after panel power down in 100uS", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + } + ] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-5", + "PageName": "Panel #05", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "LabelHeading", + "WidgetName": "Common LFP Features", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryAsci", + "WidgetName": " LFP Panel Name: ", + "Visibility": "", + "Data": [ + "42", + "Panel_Name_05" + ], + "HelpText": "This feature defines the LFP panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Target X-Res: ", + "Visibility": "", + "Data": [ + "42", + "Panel_Width_05" + ], + "HelpText": "This value specifies the Target X-Resolution for this panel.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Target Y-Res: ", + "Visibility": "", + "Data": [ + "42", + "Panel_Height_05" + ], + "HelpText": "This value specifies the Target Y-Resolution for this panel.", + "WidgetValues": [] + }, + { + "WidgetType": "LabelHeading", + "WidgetName": " DPS Panel Type Features", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Seamless DRRS Minimum Refresh Rate (Hz): ", + "Visibility": "", + "Data": [ + "42", + "Seamless_DRRS_Min_RR_05" + ], + "HelpText": "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\nNote: Graphics driver will use this field only when EDID support is disabled in VBT configuration.", + "WidgetValues": [] + }, + { + "WidgetType": "LabelHeading", + "WidgetName": " BackLight Technology Type Features", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " BackLight Technology: ", + "Visibility": "", + "Data": [ + "40", + "Blt_Control_05" + ], + "HelpText": "This feature allows OEM to select the Backlight Technology.", + "WidgetValues": [ + { + "Key": "LED Backlight", + "Value": "2" + }, + { + "Key": "CCFL Backlight", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Panel Rotation: ", + "Visibility": "", + "Data": [ + "40", + "Panel_Rotation_05" + ], + "HelpText": "This feature specifies the Panel Rotation of LFP panel used.", + "WidgetValues": [ + { + "Key": "0 degree", + "Value": "0" + }, + { + "Key": "180 degree", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Panel Position: ", + "Visibility": "", + "Data": [ + "40", + "Panel_Position_05" + ], + "HelpText": "This feature specifies the Panel Position of LFP panel used.", + "WidgetValues": [ + { + "Key": "Inside Shell", + "Value": "0" + }, + { + "Key": "Outside Shell", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Dual LFP Port Sync: ", + "Visibility": "", + "Data": [ + "42", + "EnablePortSync_Bit_05" + ], + "HelpText": "This feature will allow users to disable/enable Dual LFP Port Sync and it is applicable for DDI-A, DDI-B in case of eDP and DSI-0, DSI-1 in case of MIPI. \r\n.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " GPU Dithering for Banding artifacts: ", + "Visibility": "", + "Data": [ + "42", + "EnableDithering_Bit_05" + ], + "HelpText": "This field can be used to enable dithering from the source side for reducing banding artifacts on the visual quality features like DPST.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "Button", + "WidgetName": "Power Features", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Generic DTD Timings", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "LFP PnP ID Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Backlight Control Parameters", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Chromaticity Control", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "VESA DSC Parameters", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "LabelHeading", + "WidgetName": "Integrated MIPI DSI Settings", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:5120 or Block:2, Field:LFP2_Device_Class, Value:5120", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "MIPI Display Settings", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:5120 or Block:2, Field:LFP2_Device_Class, Value:5120", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "LabelHeading", + "WidgetName": "Integrated eDP Settings", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "eDP Fast Link Training Configuration Parameters", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "eDP Panel Power Sequencing Parameters", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Edp Max Port Link Rate (in 200 Khz): ", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [ + "27", + "eDP_Max_Port_Link_Rate_05" + ], + "HelpText": "This field specifies EDP Max Port Link Rate supported by the port in unit of 200KHz.\nDefault value would be \"0\", in which case Display Drivers should consider EDP Max Port Link Rate to be the Platform supported Max Link Rate.\nOnly when OEM's need to limit to particular Link Rate can enter the value as mentioned in below table.\n\nNote:\n1) OEM's need to enter the values mentioned from below table only.\n2) If value entered is not matching with any of the below values then Platform supported Max Link Rate should be considere as EDP Max Port Link Rate by the display drivers.\n3) In case of EDP Fast Link Training Params(FLT), if user enters FLT Link Rate value greater than the \"eDP Max Port Link Rate\" then we need to use \n Fast Link training Link Rate = MIN (FLT Link Rate , eDP Max Port Link Rate)\n---------------------------------------------------------\n|\tLink Rate(Gbps)\t|\t Value to enter in text field\t|\n|\t \t\t|\t in terms of 200KHZ \t|\n---------------------------------------------------------\n|\t 1.62 \t\t|\t 8100 \t|\n|\t 2.16 \t\t|\t 10800 \t|\n|\t 2.43 \t\t|\t 12150 \t|\n|\t 2.7 \t\t|\t 13500 \t|\n|\t 3.24 \t\t|\t 16200 \t|\n|\t 3.78 \t\t|\t 18900 \t|\n|\t 4.32 \t\t|\t 21600 \t|\n|\t 5.4 \t\t|\t 27000 \t|\n|\t 6.48 \t\t|\t 32400 \t|\n|\t 6.75 \t\t|\t 33750 \t|\n|\t 8.1 \t\t|\t 40500 \t|\n", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Panel Color Depth: ", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [ + "27", + "eDP_Panel_Color_Depth_05" + ], + "HelpText": "This feature specifies the color depth of eDP panel used.", + "WidgetValues": [ + { + "Key": "18-bit Color Depth", + "Value": "0" + }, + { + "Key": "24-bit Color Depth", + "Value": "1" + }, + { + "Key": "30-bit Color Depth", + "Value": "2" + }, + { + "Key": "36-bit Color Depth", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Select VSwing/Pre-Emphasis table : ", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [ + "27", + "eDP_VswingPreEmph_5" + ], + "HelpText": "This feature selects the VSwing Pre-Emphasis setting table to be used. For Tigerlake, based on the selection respective table will be used.\nTables for Tigerlake:\nLow Power VSwing Pre-Emphasis Setting Table:\nFor HBR2:\n\t\t\t\t\t\t Pre-Emphasis (db)\n\t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\nVoltage \t\t Level-0/200mV \t\t 200mV, 0.0db \t\t 200mV, 1.9db \t\t 200mV, 3.5db \t\t 200mV, 4.9db\nSwing \t\t Level-1/250mV \t\t 250mV, 0.0db \t\t 250mV, 1.6db \t\t 250mV, 2.9db \t\t N/A\n(mV) \t\t Level-2/300mV \t\t 300mV, 0.0db \t\t 300mV, 1.3db \t\t N/A \t\t N/A\n\t\t Level-3/350mV \t\t 350mV, 0.0db \t\t N/A \t\t N/A \t\t N/A\n\n\nFor HBR3:\n\t\t\t\t\t\t Pre-Emphasis (db)\n\t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\nVoltage \t\t Level-0/350mV \t\t 350mV, 0.0db \t\t 350mV, 3.1db \t\t 350mV, 6.0db \t\t 350mV, 8.2db\nSwing \t\t Level-1/500mV \t\t 500mV, 0.0db \t\t 500mV, 2.9db \t\t 500mV, 5.1db \t\t N/A\n(mV) \t\t Level-2/650mV \t\t 650mV, 0.6db \t\t 600mV, 3.5db \t\t N/A \t\t N/A\n\t\t Level-3/900mV \t\t 900mV, 0.0db \t\t N/A \t\t N/A \t\t N/A\n\n\nDefault VSwing Pre-Emphasis Setting Table:\nFor HBR:\n\t\t\t\t\t\t Pre-Emphasis (db)\n\t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\nVoltage \t\t Level-0/350mV \t\t 350mV, 0.0db \t\t 350mV, 3.1db \t\t 350mV, 6.0db \t\t 350mV, 8.2db\nSwing \t\t Level-1/500mV \t\t 500mV, 0.0db \t\t 500mV, 2.9db \t\t 500mV, 5.1db \t\t N/A\n(mV) \t\t Level-2/650mV \t\t 650mV, 0.6db \t\t 600mV, 3.5db \t\t N/A \t\t N/A\n\t\t Level-3/900mV \t\t 900mV, 0.0db \t\t N/A \t\t N/A \t\t N/A\n\n\nFor HBR2:\n\t\t\t\t\t\t Pre-Emphasis (db)\n\t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\nVoltage \t\t Level-0/350mV \t\t 350mV, 0.0db \t\t 350mV, 3.1db \t\t 350mV, 6.0db \t\t 350mV, 8.2db\nSwing \t\t Level-1/500mV \t\t 500mV, 0.0db \t\t 500mV, 2.9db \t\t 500mV, 5.1db \t\t N/A\n(mV) \t\t Level-2/650mV \t\t 650mV, 0.6db \t\t 600mV, 3.5db \t\t N/A \t\t N/A\n\t\t Level-3/900mV \t\t 900mV, 0.0db \t\t N/A \t\t N/A \t\t N/A", + "WidgetValues": [ + { + "Key": "Default VSwing/Pre-Emphasis Table", + "Value": "1" + }, + { + "Key": "Low Power VSwing/Pre-Emphasis Table", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " eDP Spread Spectrum Clock: ", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [ + "40", + "Enable_SSC05" + ], + "HelpText": "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Pixel Overlap Count: ", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [ + "42", + "PixelOverlapCount_05" + ], + "HelpText": "Select the number of Pixels to be overlapped per half of Scanline while using Edp Multi-SST(MSO) feature.", + "WidgetValues": [ + { + "Key": "Zero Pixel Overlap", + "Value": "0" + }, + { + "Key": "One Pixel Overlap", + "Value": "1" + }, + { + "Key": "Two Pixel Overlap", + "Value": "2" + }, + { + "Key": "Three Pixel Overlap", + "Value": "3" + }, + { + "Key": "Four Pixel Overlap", + "Value": "4" + }, + { + "Key": "Five Pixel Overlap", + "Value": "5" + }, + { + "Key": "Six Pixel Overlap", + "Value": "6" + }, + { + "Key": "Seven Pixel Overlap", + "Value": "7" + }, + { + "Key": "Eight Pixel Overlap", + "Value": "8" + } + ] + }, + { + "WidgetType": "Button", + "WidgetName": "PSR Feature", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Apical Feature", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [], + "HelpText": "", + "WidgetValues": [] + } + ], + "NestedPages": [ + { + "Type": "Block", + "Block": { + "PageNum": "5-2-5-1", + "PageName": "eDP Panel Power Sequencing Parameters", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " T3 optimization: ", + "Visibility": "", + "Data": [ + "27", + "eDP_T3_Optimization_05" + ], + "HelpText": "This feature enables or disables T3 optimization.\nWhen enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\nWhen disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "LCDVCC to HPD high delay (T3): ", + "Visibility": "", + "Data": [ + "27", + "eDP_Vcc_To_Hpd_Delay_05" + ], + "HelpText": "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\nValid Range: 0 to 200msec", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Valid video data to Backlight Enable delay (T8): ", + "Visibility": "", + "Data": [ + "27", + "eDP_DataOn_To_BkltEnable_Delay_05" + ], + "HelpText": "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\nT8 is inclusive of T7.\nValid Range of T7: 0 to 50msec", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "PWM-On To Backlight Enable delay: ", + "Visibility": "", + "Data": [ + "27", + "eDP_PwmOn_To_Bklt_Enable_Delay_05" + ], + "HelpText": "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\nDelay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\nSo it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Backlight Disable to PWM-Off delay: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Bklt_Disable_To_PwmOff_Delay_05" + ], + "HelpText": "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\nDelay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\nSo it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Backlight Disable to End of Valid video data delay (T9): ", + "Visibility": "", + "Data": [ + "27", + "eDP_BkltDisable_To_DataOff_Delay_05" + ], + "HelpText": "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "End of Valid video data to Power-Off delay (T10): ", + "Visibility": "", + "Data": [ + "27", + "eDP_DataOff_To_PowerOff_Delay_05" + ], + "HelpText": "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\nValid Range: 0 to 500 msec", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Power-off time (T12): ", + "Visibility": "", + "Data": [ + "27", + "eDP_PowerCycle_Delay_05" + ], + "HelpText": "Using this field Power-off time can be specified in 100uS.", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-5-2", + "PageName": "eDP Fast Link Training Configuration Parameters", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Is FastLinkTraining Feature Supported: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Fast_Link_Training_Supported_05" + ], + "HelpText": "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled.", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Data Rate: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Fast_Link_Training_Data_Rate_05" + ], + "HelpText": "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. It will be used if the sink indicates that no aux handshake is required during link training.\n\nIn case of EDP Fast Link Training Params(FLT), if user enters FLT Link Rate value greater than the \"eDP Max Port Link Rate\" then driver would use \n Fast Link training Link Rate = MIN (FLT Link Rate , eDP Max Port Link Rate).", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Lane Count: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Link_LaneCount_05" + ], + "HelpText": "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. It will be used if the sink indicates that no aux handshake is required during link training.", + "WidgetValues": [ + { + "Key": "x1", + "Value": "0" + }, + { + "Key": "x2", + "Value": "1" + }, + { + "Key": "x4", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Pre-Emphasis: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Link_PreEmp_05" + ], + "HelpText": "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. It will be used if the sink indicates that no aux handshake is required during link training.", + "WidgetValues": [ + { + "Key": "Level-0", + "Value": "0" + }, + { + "Key": "Level-1", + "Value": "1" + }, + { + "Key": "Level-2", + "Value": "2" + }, + { + "Key": "Level-3", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Voltage Swing: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Link_Vswing_05" + ], + "HelpText": "This feature allows for the selection of the Voltage Swing value for the embedded DP link. It will be used if the sink indicates that no aux handshake is required during link training.", + "WidgetValues": [ + { + "Key": "Swing-0", + "Value": "0" + }, + { + "Key": "Swing-1", + "Value": "1" + }, + { + "Key": "Swing-2", + "Value": "2" + }, + { + "Key": "Swing-3", + "Value": "3" + } + ] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-5-3", + "PageName": "PSR Feature", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Full Link enable: ", + "Visibility": "", + "Data": [ + "9", + "PSR_FullLink_Enable_05" + ], + "HelpText": "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state.", + "WidgetValues": [ + { + "Key": "No", + "Value": "0" + }, + { + "Key": "Yes", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Require AUX to wake up: ", + "Visibility": "", + "Data": [ + "9", + "PSR_Require_AUX2Wakeup_05" + ], + "HelpText": "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used.", + "WidgetValues": [ + { + "Key": "No", + "Value": "0" + }, + { + "Key": "Yes", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Lines to wait before link standby: ", + "Visibility": "", + "Data": [ + "9", + "PSR_Lines2Wait_B4LinkS3_05" + ], + "HelpText": "This field determines Lines to wait before link standby\n0 lines to wait (Default)\n1 lines to wait\n4 lines to wait\n8 lines to wait\nOthers Reserved", + "WidgetValues": [ + { + "Key": "0 lines to wait", + "Value": "0" + }, + { + "Key": "1 lines to wait", + "Value": "1" + }, + { + "Key": "4 lines to wait", + "Value": "2" + }, + { + "Key": "8 lines to wait", + "Value": "3" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Idle frames to wait: ", + "Visibility": "", + "Data": [ + "9", + "PSR_IdleFrames2Wait_05" + ], + "HelpText": "Idle frames to wait for PSR enable.\nAllowed values 0-15. Default value is 0.", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Clock Recovery Time: ", + "Visibility": "", + "Data": [ + "9", + "PSR_TP1_WaitTime_05" + ], + "HelpText": "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)", + "WidgetValues": [ + { + "Key": "500 usec", + "Value": "0" + }, + { + "Key": "100 usec", + "Value": "1" + }, + { + "Key": "2.5 msec", + "Value": "2" + }, + { + "Key": "0 (Skip)", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Channel Equalization Time for PSR1 panel: ", + "Visibility": "", + "Data": [ + "9", + "PSR1_TP_2_3_4_WaitTime_05" + ], + "HelpText": "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) or TP4(Training Pattern4) time during PSR1 exit(wake up)", + "WidgetValues": [ + { + "Key": "500 usec", + "Value": "0" + }, + { + "Key": "100 usec", + "Value": "1" + }, + { + "Key": "2.5 msec", + "Value": "2" + }, + { + "Key": "0 (Skip)", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Channel Equalization Time for PSR2 panel: ", + "Visibility": "", + "Data": [ + "9", + "PSR2_TP_2_3_4_WaitTime_05" + ], + "HelpText": "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) or TP4(Training Pattern4) time during PSR2 exit(wake up)", + "WidgetValues": [ + { + "Key": "500 usec", + "Value": "0" + }, + { + "Key": "100 usec", + "Value": "1" + }, + { + "Key": "2.5 msec", + "Value": "2" + }, + { + "Key": "50 usec", + "Value": "3" + } + ] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-5-4", + "PageName": "Apical Feature", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Apical Assertive Display IP: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Apical_Display_Ip_Enable_05" + ], + "HelpText": "This field enables/disables the Apical Assertive Display IP for this panel.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Panel OUI (IEEE OUI): ", + "Visibility": "", + "Data": [ + "27", + "eDP_Panel_Oui_05" + ], + "HelpText": "This field specifies the Apical IP specific Panel OUI field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " DPCD Base Address: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Dpcd_Base_Address_05" + ], + "HelpText": "This field specifies the Apical IP specific DPCD base address field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " DPCD Irdidix Control 0: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Dpcd_Irdidix_Control0_05" + ], + "HelpText": "This field specifies the Apical IP specific DPCD Irdidix control 0 field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " DPCD Option Select: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Dpcd_Option_Select_05" + ], + "HelpText": "This field specifies the Apical IP specific DPCD option select field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " DPCD Backlight: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Dpcd_Backlight_05" + ], + "HelpText": "This field specifies the Apical IP specific backlight value.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Ambient Light: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Ambient_Light_05" + ], + "HelpText": "This field specifies the Apical IP specific Ambient light value.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Backlight scale: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Backlight_Scale_05" + ], + "HelpText": "This field specifies the Apical IP specific backlight scale field.", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-5-5", + "PageName": "Power Features", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Intel Display Power Saving Technology (DPST) (Mobile only): ", + "Visibility": "", + "Data": [ + "44", + "DPST_Enable_05" + ], + "HelpText": "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled.\nIntel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power.\nNote: This technology is only active when the system is running in battery mode and the LFP is the only active display device.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Intel Display Refresh Rate Switching (DRRS) (Mobile only): ", + "Visibility": "", + "Data": [ + "44", + "DRRS_Enable_05" + ], + "HelpText": "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Edge Luminance Profile (ELP) : ", + "Visibility": "", + "Data": [ + "44", + "ELP_Enable_05" + ], + "HelpText": "This feature determines whether the ELP feature is enabled or disabled.\nEdge Luminance Profile (ELP) is a panel technology which reduce luminance on the edge of screen to save panel power.\nNote:This technology cannot co-exist with DPST and OPST ((i.e.) OPST, DPST and ELP cannot exist together.They are all mutually exclusive to each other.)", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " OLED Power Saving Technology (OPST) : ", + "Visibility": "", + "Data": [ + "44", + "OPST_Enable_05" + ], + "HelpText": "This feature determines whether the OPST feature is enabled or disabled.\nOLED Power Saving Technology (OPST) is a panel technology which saves power by intelligent, adaptive dimming of midrange pixel values more aggressively than the extremes without compromising the viewability.\nNote: This technology cannot co-exist with ELP and DPST ((i.e.) OPST, DPST and ELP cannot exist together.They are all mutually exclusive to each other.)", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Dynamic Media Refresh Rate Switching Enable/Disable ", + "Visibility": "", + "Data": [ + "44", + "DMRRS_Enable_05" + ], + "HelpText": "This feature determines whether Dynamic media refresh rate switching is to be enabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Enable Display Lace Support: ", + "Visibility": "", + "Data": [ + "44", + "LACE_Enable_05" + ], + "HelpText": "This feature, when enabled, will set Display Lace Support otherwise, the functionality will be disabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Panel Self Refresh (PSR): ", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [ + "44", + "PSR_Enable_05" + ], + "HelpText": "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Assertive Display Technology Enable/Disable: ", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [ + "44", + "ADT_Enable_05" + ], + "HelpText": "This feature determines whether Assertive display technology is to be enabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Intel Automatic Display Brightness (ADB) (Mobile only): ", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [ + "44", + "ADB_Enable_05" + ], + "HelpText": "This feature determines whether Intel Automatic Display Brightness is to be enabled. Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) depending on the current ambient light environment.\nWhen enabled, the driver and VBIOS will control the backlight brightness of the LFP depending on the ambient environment if and only if the LFP is the only active display. When disabled, the driver will perform no action.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "EDP 4k/2k HOBL Feature: ", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [ + "44", + "eDP_4k_2k_HOBL_feature_Enable_05" + ], + "HelpText": "This feature will allow users to disable/enable the edp 4k/2k HOBL(Hours Of Battery Life) feature by programming relevant registers specific for a platform.\r\n.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Default Display LACE Enabled status: ", + "Visibility": "", + "Data": [ + "44", + "LACE_Status_05" + ], + "HelpText": "This feature, when enabled, will set Default Display LACE Enabled status otherwise, the functionality will be disabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "DPST Aggressiveness Level: ", + "Visibility": "", + "Data": [ + "44", + "DPST_Aggressiveness_Profile_05" + ], + "HelpText": "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n1 (Maximum Quality with No DPST)\n2\n3\n4\n5\n6 (Maximum Battery)", + "WidgetValues": [ + { + "Key": "1 - Maximum Quality with No DPST", + "Value": "1" + }, + { + "Key": "2", + "Value": "2" + }, + { + "Key": "3", + "Value": "3" + }, + { + "Key": "4", + "Value": "4" + }, + { + "Key": "5", + "Value": "5" + }, + { + "Key": "6 - Maximum Battery", + "Value": "6" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "LACE Aggressiveness Level: ", + "Visibility": "", + "Data": [ + "44", + "LACE_Aggressiveness_Profile_05" + ], + "HelpText": "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\nMinimum 0\nModerate 1\nHigh 2", + "WidgetValues": [ + { + "Key": "Minimum", + "Value": "0" + }, + { + "Key": "Moderate", + "Value": "1" + }, + { + "Key": "High", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "ELP Aggressiveness Level: ", + "Visibility": "", + "Data": [ + "44", + "ELP_Aggressiveness_Profile_05" + ], + "HelpText": "This feature allows for the selection of ELP Aggressiveness level for this Panel Type.\nMinimum Power Savings\nMedium Power Savings \nMaximum Power Savings", + "WidgetValues": [ + { + "Key": "Minimum Power Savings", + "Value": "0" + }, + { + "Key": "Medium Power Savings", + "Value": "1" + }, + { + "Key": "Maximum Power Savings", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "OPST Aggressiveness Level: ", + "Visibility": "", + "Data": [ + "44", + "OPST_Aggressiveness_Profile_05" + ], + "HelpText": "This feature allows for the selection of OPST Aggressiveness level for this Panel Type.\nMinimum Power Savings\nMedium Power Savings \nMaximum Power Savings", + "WidgetValues": [ + { + "Key": "Minimum Power Savings", + "Value": "0" + }, + { + "Key": "Medium Power Savings", + "Value": "1" + }, + { + "Key": "Maximum Power Savings", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Default Display VRR Enabled status: ", + "Visibility": "", + "Data": [ + "44", + "VRR_Status_05" + ], + "HelpText": "VRR (Variable Refresh Rate) is a feature that can continuously and seamlessly vary Refresh Rate on the fly, on displays that support Variable Refresh rate Technologies.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-5-6", + "PageName": "Generic DTD Timings", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Pixel Clock in KHz: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_Pixel_CLK_05" + ], + "HelpText": "Pixel Clock (in KHz) Range from 0.001 to 4294967.295 MP/s.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Active: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_Active_05" + ], + "HelpText": "Horizontal Active Image Pixels Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Active: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_Active_05" + ], + "HelpText": "Vertical Active Image Lines Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Blank: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_Blank_05" + ], + "HelpText": "Horizontal Blank Pixels Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Blank: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_Blank_05" + ], + "HelpText": "Vertical Blank lines Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Front Porch: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_FrontPorch_05" + ], + "HelpText": "Horizontal Front Porch Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Front Porch: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_FrontPorch_05" + ], + "HelpText": "Vertical Front Porch Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Sync: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_Sync_05" + ], + "HelpText": "Horizontal Sync Width Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Sync: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_Sync_05" + ], + "HelpText": "Vertical Sync Width Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Image Size: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_Image_Size_05" + ], + "HelpText": "Horizontal Addressable Video Image Size in mm represented by 16bits. Image size multiplier 1.00 mm precision.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Image Size: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_Image_Size_05" + ], + "HelpText": "Vertical Addressable Video Image Size in mm represented by 16bits. Image size multiplier 1.00 mm precision.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryBin", + "WidgetName": "Common Flag: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_Common_Flag_05" + ], + "HelpText": "Common DTD Flags:\nBit 7 : Horizontal Sync Polarity\n1 : Positive\n0 : Negative\nBit 6 : Vertical Sync polarity\n1 : Positive\n0 : Negative\nBit 5 - 0: Reserved (Default value 0)", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-5-7", + "PageName": "LFP PnP ID Table", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Table", + "WidgetName": "", + "Visibility": "", + "Data": [ + "42", + "LFP_Panel_PnP_ID_05" + ], + "HelpText": "This feature allows the 10 bytes of EDID Vendor/Product ID starting at offset 08h to be used as a PnP ID.\n\nTable Definition:\n\tWord: ID Manufacturer Name\n\tWord: ID Product Code\n\tDWord: ID Serial Number\n\tByte: Week of Manufacture\n\tByte: Year of Manufacture", + "WidgetValues": [ + { + "ColumnName": "PnP ID", + "SizeinBytes": "1" + } + ] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-5-8", + "PageName": "Backlight Control Parameters", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Inverter Type: ", + "Visibility": "", + "Data": [ + "43", + "BLC_Inv_Type_05" + ], + "HelpText": "This feature allows for the selection of the Backlight Inverter type that is to be used to control the backlight brightness of the LFP.\nWhen PWM is selected, the driver and VBIOS will control the backlight brightness via the integrated PWM solution for the applicable chipsets.\nWhen None/External is selected, the system BIOS will control the backlight brightness via the external solution.", + "WidgetValues": [ + { + "Key": "None/External", + "Value": "0" + }, + { + "Key": "PWM", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Pwm Source Selection: ", + "Visibility": "", + "Data": [ + "43", + "Lfp_Pwm_Source_Selection_05" + ], + "HelpText": "If panel supports 'Intel HDR AUX Interface', it will always be chosen by default. If not, value in 'PWM Source Selection' will be used", + "WidgetValues": [ + { + "Key": "PWM From Display Engine", + "Value": "2" + }, + { + "Key": "PWM From LCD Panel", + "Value": "3" + }, + { + "Key": "Panel Driver Interface", + "Value": "4" + }, + { + "Key": "VESA eDP AUX Interface", + "Value": "5" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Pwm Controller Selection: ", + "Visibility": "", + "Data": [ + "43", + "Lfp_Pwm_Controller_Selection_05" + ], + "HelpText": "This field allows to select the PWM Controller to be used for the selected Local Flat Panel.This field allows to select the PWM Controller to be used for the selected Local Flat Panel.If Two LFPs are connected then PWM0 and PWM1 must be selected accordingly.", + "WidgetValues": [ + { + "Key": "PWM0", + "Value": "0" + }, + { + "Key": "PWM1", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Inverter Polarity: ", + "Visibility": "", + "Data": [ + "43", + "BLC_Inv_Polarity_05" + ], + "HelpText": "This feature allows the backlight inverter polarity to be specified.\nNormal means 0 value is minimum brightness.\nInverted means 0 value is maximum brightness.", + "WidgetValues": [ + { + "Key": "Normal", + "Value": "0" + }, + { + "Key": "Inverted", + "Value": "1" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Minimum Brightness: ", + "Visibility": "", + "Data": [ + "43", + "Post_Min_Brightness_05" + ], + "HelpText": "This feature allows defining the absolute minimum backlight brightness. The driver will never decrease the backlight less than this value. The value must be specified using normal polarity semantics. The value should range from 0 to 255 if the brightness precision bit is chosen to be 8, and it should range from 0 to 65535 if the precision bit is chosen to be 16.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "POST Backlight Intensity: ", + "Visibility": "", + "Data": [ + "43", + "Post_Brightness_05" + ], + "HelpText": "This feature is used to set default backlight brightness value of the panel at POST. The value should range from 0 to 255 if the bit precision is chosen to be 8 and it should range from 0 to 65535 if the brightness bit precision is chosent to be 16.", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Brightness Precision Bits: ", + "Visibility": "", + "Data": [ + "43", + "BrightnessPrecisionBits_05" + ], + "HelpText": "This field represents the range of brightness in terms of bit precision.\n 8 = Brightness range of 0 to 255.\n 16 = Brightness range of 0 to 65535", + "WidgetValues": [ + { + "Key": "8", + "Value": "8" + }, + { + "Key": "16", + "Value": "16" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "PWM Inverter Frequency (Hz): ", + "Visibility": "", + "Data": [ + "43", + "PWM_Frequency_05" + ], + "HelpText": "This feature allows for the definition of the frequency needed for PWM Inverter.\nNote: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Intel HDR DPCD Refresh Timeout (unit - 10 micro seconds): ", + "Visibility": "", + "Data": [ + "43", + "HdrDpcdRefreshTimeout_05" + ], + "HelpText": "This field allows to configure the refresh timeout of Intel HDR DPCDs for different TCON Vendors.\nNote:\n\tThe value is in units of 10 microseconds.\n\tThe range (entered as a decimal number), for the timeout is 0-65535", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-5-9", + "PageName": "Chromaticity Control", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Chromaticity Control Feature: ", + "Visibility": "", + "Data": [ + "46", + "Chromacity_Enable_05" + ], + "HelpText": "This bit enables Chromaticity feature.\nIf this bit is enabled, EDID values for chromaticity will be used, else feature is disabled.\nFeature will be supported for Panels that support EDID version 1.4 or higher.\nPlease refer to section 3.7 of EDID Specification 1.4.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Override the EDID values: ", + "Visibility": "", + "Data": [ + "46", + "Override_EDID_Data_05" + ], + "HelpText": "This option when enabled along with Chromaticity feature will override EDID values through following VBT data", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Red_Green_bits (Bits 1:0 at 19h): ", + "Visibility": "", + "Data": [ + "46", + "Red_Green_05" + ], + "HelpText": "Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Blue_White_bits (Bits 1:0 at 1Ah): ", + "Visibility": "", + "Data": [ + "46", + "Blue_White_05" + ], + "HelpText": "Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Red_x (Bits 9:2 at 1Bh): ", + "Visibility": "", + "Data": [ + "46", + "Red_x_05" + ], + "HelpText": "Bits 9:2 of red color x coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Red_y (Bits 9:2 at 1Ch): ", + "Visibility": "", + "Data": [ + "46", + "Red_y_05" + ], + "HelpText": "Bits 9:2 of red color y coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Green_x (Bits 9:2 at 1Dh): ", + "Visibility": "", + "Data": [ + "46", + "Green_x_05" + ], + "HelpText": "Bits 9:2 of Green color x coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Green_y (Bits 9:2 at 1Eh): ", + "Visibility": "", + "Data": [ + "46", + "Green_y_05" + ], + "HelpText": "Bits 9:2 of Green color y coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Blue_x (Bits 9:2 at 1Fh): ", + "Visibility": "", + "Data": [ + "46", + "Blue_x_05" + ], + "HelpText": "Bits 9:2 of Blue color x coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Blue_y (Bits 9:2 at 20h): ", + "Visibility": "", + "Data": [ + "46", + "Blue_y_05" + ], + "HelpText": "Bits 9:2 of Blue color y coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " White_x (Bits 9:2 at 21h): ", + "Visibility": "", + "Data": [ + "46", + "White_x_05" + ], + "HelpText": "Bits 9:2 of White color x coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " White_y (Bits 9:2 at 22h): ", + "Visibility": "", + "Data": [ + "46", + "White_y_05" + ], + "HelpText": "Bits 9:2 of White color y coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Override Luminance values ", + "Visibility": "", + "Data": [ + "46", + "Override_LUM_Data_05" + ], + "HelpText": "This option when enabled along with Chromaticity feature will override luminance values following VBT values", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Minimum Luminance: ", + "Visibility": "", + "Data": [ + "46", + "MinLuminance_05" + ], + "HelpText": "Minimum luminance value.\n2 byte value, encoded in IEEE 754 half-precision binary floating point format,", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Maximum full frame luminance: ", + "Visibility": "", + "Data": [ + "46", + "MaxFullLuminance_05" + ], + "HelpText": "Maximum Full frame luminance value.\n2 byte value, encoded in IEEE 754 half-precision binary floating point format,", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Maximum Luminance: ", + "Visibility": "", + "Data": [ + "46", + "MaxLuminance_05" + ], + "HelpText": "Maximum luminance value(Relatively smaller portion of screen).\n2 byte value, encoded in IEEE 754 half-precision binary floating point format.", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Override Gamma values: ", + "Visibility": "", + "Data": [ + "46", + "Override_Gamma_Data_05" + ], + "HelpText": "This option when enabled along with Chromaticity feature will override gamma values through following VBT data", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Panel gamma: ", + "Visibility": "", + "Data": [ + "46", + "Gamma_05" + ], + "HelpText": "Value shall define the gamma range, from 1.00 to 3.54, as follows:\nField Value = (Gamma (value in float) x 100) - 100\nField values range from 00h through FFh.\nFFh = No gamma information shall be provided", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-5-10", + "PageName": "VESA DSC Parameters", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "DSC Major Version: ", + "Visibility": "", + "Data": [ + "56", + "C5_Major_Dsc_Version" + ], + "HelpText": "VESA DSC Major revision field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "DSC Minor Version: ", + "Visibility": "", + "Data": [ + "56", + "C5_Minor_Dsc_Version" + ], + "HelpText": "VESA DSC Minor revision field.", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Block prediction supported: ", + "Visibility": "", + "Data": [ + "56", + "C5_Blk_Prediction_En" + ], + "HelpText": "Sink supports block prediction as per the VESA DSC Spec.", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "RC Buffer Block size as per VESA DSC Spec: ", + "Visibility": "", + "Data": [ + "56", + "C5_RC_Block_Size" + ], + "HelpText": "RC buffer block size for a single RC buffer as defined by the VESA DSC spec.", + "WidgetValues": [ + { + "Key": "1 KB", + "Value": "0" + }, + { + "Key": "4 KB", + "Value": "1" + }, + { + "Key": "16 KB", + "Value": "2" + }, + { + "Key": "64 KB", + "Value": "3" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Number of RC buffer blocks as per VESA DSC Spec: ", + "Visibility": "", + "Data": [ + "56", + "C5_Dsc_RC_Buf_Size" + ], + "HelpText": "This field defines the number of RC buffers as per VESA DSC spec.\nThe number of RC buffers used by the software shall be (Value + 1) where Value is in range 0 to 127.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryBin", + "WidgetName": "Slices per line supported by the sink device: ", + "Visibility": "", + "Data": [ + "56", + "C5_Dsc_Slices_Per_Line" + ], + "HelpText": "This field defines the slices per line supported by the sink device.\nThe field is defined in bitmap fashion and details of each bits are as defined below:\n\tBits 31-10\t\t Bit 9\tBit 8\tBit 7\tBit 6\tBit 5\tBit 4\t Bit 3\t Bit 2\t Bit 1\t Bit 0\n\tReserved\t\t 24\t 20\t 16\t 12\t 10\t 8\t 6\t 4\t 2\t 1\nBit = 0, not supported. Bit = 1, supported\nNote: Assumption is that sink shall support all lower slices per line than maximum selected field. i.e. If it supports say 8 slices per line, it will also support 4/2/1 slices per line", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Line buffer depth as per VESA DSC Spec: ", + "Visibility": "", + "Data": [ + "56", + "C5_Line_Buffer_Depth" + ], + "HelpText": "Line buffer depth in bits as per VESA DSC spec.", + "WidgetValues": [ + { + "Key": "8 bits", + "Value": "0" + }, + { + "Key": "9 bits", + "Value": "1" + }, + { + "Key": "10 bits", + "Value": "2" + }, + { + "Key": "11 bits", + "Value": "3" + }, + { + "Key": "12 bits", + "Value": "4" + }, + { + "Key": "13 bits", + "Value": "5" + }, + { + "Key": "14 bits", + "Value": "6" + }, + { + "Key": "15 bits", + "Value": "7" + }, + { + "Key": "16 bits", + "Value": "8" + } + ] + }, + { + "WidgetType": "EntryBin", + "WidgetName": "Input compression BPC supported by the sink device: ", + "Visibility": "", + "Data": [ + "56", + "C5_Dsc_Bpc" + ], + "HelpText": "This field defines the compression input bpc supported by the sink device.\nThe field is defined in bitmap fashion and details of each bits are as defined below:\n\tBits 7-4\t Bit 3\t Bit 2\t Bit 1\t Bit 0\n\tRsvd\t 12 bpc\t 10bpc\t 8bpc\t Rsvd\nBit = 0, not supported. Bit = 1, supported\nNote: Assumption is that sink shall support all lower bpc values than the maximum selected field. i.e. If it supports say 12bpc, it will also support 10 and 8bpc as well", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Maximum supported compression BPP: ", + "Visibility": "", + "Data": [ + "56", + "C5_Dsc_Max_Bpp" + ], + "HelpText": "As of today, we are supporting 6/8/10/12 BPP for compression output.\nSelect the most appropriate BPP as supported by the sink.", + "WidgetValues": [ + { + "Key": "6 Bits per pixel", + "Value": "0" + }, + { + "Key": "8 Bits per pixel", + "Value": "1" + }, + { + "Key": "10 Bits per pixel", + "Value": "2" + }, + { + "Key": "12 Bits per pixel", + "Value": "3" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Slice height supported by the sink device: ", + "Visibility": "", + "Data": [ + "56", + "C5_Dsc_Slice_Height" + ], + "HelpText": "Slice height supported by the sink device for DSC slice.\nNote: Slice height must divide the picture height uniformly.", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-5-11", + "PageName": "MIPI Display Settings", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:5120 or Block:2, Field:LFP2_Device_Class, Value:5120", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Label", + "WidgetName": "MIPI DSI Controller Configuration Settings", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Video/Command Mode: ", + "Visibility": "", + "Data": [ + "52", + "Video_Command_Mode_05" + ], + "HelpText": "This feature helps in selecting Video/Command Mode.", + "WidgetValues": [ + { + "Key": "Video Mode", + "Value": "0" + }, + { + "Key": "Command Mode", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Packet Sequence For Video Mode: ", + "Visibility": "", + "Data": [ + "52", + "Packet_Sequence_Video_Mode_05" + ], + "HelpText": "This feature helps in selecting packet sequence for Video Mode.\nNon-burst with sync pulse\nNon-burst with sync events\nBurst mode", + "WidgetValues": [ + { + "Key": "Non-burst with sync pulse", + "Value": "1" + }, + { + "Key": "Non-burst with sync events", + "Value": "2" + }, + { + "Key": "Burst Mode", + "Value": "3" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Required Burst Mode Rate (in Kbps): ", + "Visibility": "", + "Data": [ + "52", + "RequiredBurstModeRate_05" + ], + "HelpText": "This feature allows to enter Required Burst Mode Rate in Kilo bits per sec. This should be greater than Non-Burst Mode Rate\nThis value is valid only if packet sequence for video mode is Burst Mode.", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Colour Format In Video Mode: ", + "Visibility": "", + "Data": [ + "52", + "Colour_Format_Video_Mode_05" + ], + "HelpText": "This feature helps in selecting supported colour format in Video Mode.", + "WidgetValues": [ + { + "Key": "RGB565", + "Value": "1" + }, + { + "Key": "RGB666", + "Value": "2" + }, + { + "Key": "RGB 666(Loosely Packed Format)", + "Value": "3" + }, + { + "Key": "RGB888", + "Value": "4" + }, + { + "Key": "RGB101010", + "Value": "5" + }, + { + "Key": "RGB121212", + "Value": "6" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Dual Link Support: ", + "Visibility": "", + "Data": [ + "52", + "Dual_Link_05" + ], + "HelpText": "This feature allows to select type of dual link.", + "WidgetValues": [ + { + "Key": "Dual Link Not Supported", + "Value": "0" + }, + { + "Key": "Dual Link Front Back Mode", + "Value": "1" + }, + { + "Key": "Dual Link Pixel Alternative Mode", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Pixel Overlap Count(Z-Inversion): ", + "Visibility": "", + "Data": [ + "42", + "PixelOverlapCount_05" + ], + "HelpText": "Select the number of Pixels to be overlapped per half of Scanline while using\nMIPI Dual Link Front-Back video mode.", + "WidgetValues": [ + { + "Key": "Zero Pixel Overlap", + "Value": "0" + }, + { + "Key": "One Pixel Overlap", + "Value": "1" + }, + { + "Key": "Two Pixels Overlap", + "Value": "2" + }, + { + "Key": "Three Pixels Overlap", + "Value": "3" + }, + { + "Key": "Four Pixel Overlap", + "Value": "4" + }, + { + "Key": "Five Pixel Overlap", + "Value": "5" + }, + { + "Key": "Six Pixels Overlap", + "Value": "6" + }, + { + "Key": "Seven Pixels Overlap", + "Value": "7" + }, + { + "Key": "Eight Pixel Overlap", + "Value": "8" + }, + { + "Key": "Nine Pixel Overlap", + "Value": "9" + }, + { + "Key": "Ten Pixels Overlap", + "Value": "10" + }, + { + "Key": "Eleven Pixels Overlap", + "Value": "11" + }, + { + "Key": "Twelve Pixel Overlap", + "Value": "12" + }, + { + "Key": "Thirteen Pixels Overlap", + "Value": "13" + }, + { + "Key": "Fourteen Pixels Overlap", + "Value": "14" + }, + { + "Key": "Fifteen Pixels Overlap", + "Value": "15" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " CABC Support: ", + "Visibility": "", + "Data": [ + "52", + "CABC_Support_05" + ], + "HelpText": "This feature helps in selecting CABC_Support.", + "WidgetValues": [ + { + "Key": "Disabled", + "Value": "0" + }, + { + "Key": "Enabled", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " CABC On/Off Commands: ", + "Visibility": "", + "Data": [ + "52", + "CabcCmdsPort_05" + ], + "HelpText": "Select the MIPI Port for sending CABC On/Off Commands in case of Dual link MIPI panels\nThis field is ignored in single link MIPI case", + "WidgetValues": [ + { + "Key": "MIPI DSI-0", + "Value": "0" + }, + { + "Key": "MIPI DSI-1", + "Value": "1" + }, + { + "Key": "Both MIPI DSI-0 and DSI-1", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Panel PWM/BkltController On/Off Commands: ", + "Visibility": "", + "Data": [ + "52", + "PanelPwmCmdsPort_05" + ], + "HelpText": "Select the MIPI Port for sending Panel PWM/BkltController On/Off Commands in case of Dual link MIPI panels\nThis field is ignored in single link MIPI case", + "WidgetValues": [ + { + "Key": "MIPI DSI-0", + "Value": "0" + }, + { + "Key": "MIPI DSI-1", + "Value": "1" + }, + { + "Key": "Both MIPI DSI-0 and DSI-1", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " RGB/BGR Panel Selection: ", + "Visibility": "", + "Data": [ + "52", + "RgbFlip_05" + ], + "HelpText": "Select if the panel is RGB or BGR", + "WidgetValues": [ + { + "Key": "RGB Panel", + "Value": "0" + }, + { + "Key": "BGR Panel", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Number Of Data Lanes: ", + "Visibility": "", + "Data": [ + "52", + "Number_Of_Lanes_05" + ], + "HelpText": "This feature allows to select number of data lanes going to use for MIPI DSI", + "WidgetValues": [ + { + "Key": "1", + "Value": "0" + }, + { + "Key": "2", + "Value": "1" + }, + { + "Key": "3", + "Value": "2" + }, + { + "Key": "4", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Sending Bus Turn Around (BTA): ", + "Visibility": "", + "Data": [ + "52", + "Bta_Disable_05" + ], + "HelpText": "Enable or Disable sending Bus Turn Around to the Peripheral", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "0" + }, + { + "Key": "Disabled", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Escape Clock: ", + "Visibility": "", + "Data": [ + "52", + "EscapeClk_05" + ], + "HelpText": "This feature helps to select frequency of Escape Clk.", + "WidgetValues": [ + { + "Key": "20 MHz", + "Value": "0" + }, + { + "Key": "10 MHz", + "Value": "1" + }, + { + "Key": "5 MHz", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " EoT Packet Transmission: ", + "Visibility": "", + "Data": [ + "52", + "EoTpSupport_05" + ], + "HelpText": "This feature helps to either enable or disable EoT packet Transmission", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "0" + }, + { + "Key": "Disabled", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Clock Stop Feature: ", + "Visibility": "", + "Data": [ + "52", + "ClockStop_05" + ], + "HelpText": "To enable or disable clock stopping feature during BLLP timing in a MIPI DPI (video) mode", + "WidgetValues": [ + { + "Key": "Disabled", + "Value": "0" + }, + { + "Key": "Enabled", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " LP Clock During LPM: ", + "Visibility": "", + "Data": [ + "52", + "LpClockDuringLpm_05" + ], + "HelpText": "In continuous clock mode (Clock Stop Feature disabled), Clock lane will always be in HS mode.\nIf this feature is enabled, Clock lane also goes to LP state once per frame during the mandated data lane LPM\nin MIPI DSI DPI (video) mode", + "WidgetValues": [ + { + "Key": "Disabled", + "Value": "0" + }, + { + "Key": "Enabled", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Blanking During BLLP: ", + "Visibility": "", + "Data": [ + "52", + "BlankingDuringBllp_05" + ], + "HelpText": "This feature helps to send Blanking packets during BLLP regions in a MIPI DSI DPI (video) mode.", + "WidgetValues": [ + { + "Key": "Disabled", + "Value": "0" + }, + { + "Key": "Enabled", + "Value": "1" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " TClkPrepare: ", + "Visibility": "", + "Data": [ + "52", + "TClkPrepare_05" + ], + "HelpText": "This feature allows to enter TClkPrepare in ns.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " TClkTrail: ", + "Visibility": "", + "Data": [ + "52", + "TClkTrail_05" + ], + "HelpText": "This feature allows to enter TClkTrail in ns.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " TClkPrepare + TClkZero: ", + "Visibility": "", + "Data": [ + "52", + "TClkPrepareTClkZero_05" + ], + "HelpText": "This feature allows to enter TClkPrepare + TClkZero in ns.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " THsPrepare: ", + "Visibility": "", + "Data": [ + "52", + "THsPrepare_05" + ], + "HelpText": "This feature allows to enter THsPrepare in ns.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " THsTrail: ", + "Visibility": "", + "Data": [ + "52", + "THsTrail_05" + ], + "HelpText": "This feature allows to enter THsTrail in ns.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " THsPrepare + THsZero: ", + "Visibility": "", + "Data": [ + "52", + "THsPrepareTHsZero_05" + ], + "HelpText": "This feature allows to enter THsPrepare + THsZero in ns.", + "WidgetValues": [] + }, + { + "WidgetType": "Label", + "WidgetName": "MIPI DSI Panel Power On/Off Sequence(delays)", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Power-Up Delay: ", + "Visibility": "", + "Data": [ + "52", + "PowerUpDelay_05" + ], + "HelpText": "Delay to be given after panel power up in 100uS", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Data Turn-On To Panel Backlight Enable Delay: ", + "Visibility": "", + "Data": [ + "52", + "DataTurnOnToPanelBacklightEnableDelay_05" + ], + "HelpText": "Delay to be given after MIPI DATA TURN ON and before backlight enabling in 100uS", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Pwm-On To Backlight Enable Delay: ", + "Visibility": "", + "Data": [ + "52", + "Mipi_PwmOn_To_Bklt_Enable_Delay_05" + ], + "HelpText": "Delay to be given after PWM-On and before Backlight Enable in 100uS\nDelay from PWM-On to Backlight Enable is included in delay from Data Turn-On to Panel Backlight Enable.\nSo it is expected that delay from PWM-On to Backlight Enable is less than the delay from Data Turn-On to Panel Backlight Enable.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Backlight Disable To Pwm-Off Delay: ", + "Visibility": "", + "Data": [ + "52", + "Mipi_Bklt_Disable_To_PwmOff_Delay_05" + ], + "HelpText": "Delay to be given after Backlight Disable and before Pwm-Off in 100uS\nDelay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to Data Turn-Off.\nSo it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to Data Turn-Off.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Backlight Disable To Data Turn-Off Delay: ", + "Visibility": "", + "Data": [ + "52", + "BacklightOffToDataTurnOffDelay_05" + ], + "HelpText": "Delay to be given after Backlight Disable and before MIPI DATA TURN OFF in 100uS", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Power-Down Delay: ", + "Visibility": "", + "Data": [ + "52", + "PowerDownDelay_05" + ], + "HelpText": "Delay to be given before panel power down in 100uS", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Power-Cycle Delay: ", + "Visibility": "", + "Data": [ + "52", + "PowerCycleDelay_05" + ], + "HelpText": "Delay to be given before panel power up and after panel power down in 100uS", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + } + ] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-6", + "PageName": "Panel #06", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "LabelHeading", + "WidgetName": "Common LFP Features", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryAsci", + "WidgetName": " LFP Panel Name: ", + "Visibility": "", + "Data": [ + "42", + "Panel_Name_06" + ], + "HelpText": "This feature defines the LFP panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Target X-Res: ", + "Visibility": "", + "Data": [ + "42", + "Panel_Width_06" + ], + "HelpText": "This value specifies the Target X-Resolution for this panel.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Target Y-Res: ", + "Visibility": "", + "Data": [ + "42", + "Panel_Height_06" + ], + "HelpText": "This value specifies the Target Y-Resolution for this panel.", + "WidgetValues": [] + }, + { + "WidgetType": "LabelHeading", + "WidgetName": " DPS Panel Type Features", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Seamless DRRS Minimum Refresh Rate (Hz): ", + "Visibility": "", + "Data": [ + "42", + "Seamless_DRRS_Min_RR_06" + ], + "HelpText": "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\nNote: Graphics driver will use this field only when EDID support is disabled in VBT configuration.", + "WidgetValues": [] + }, + { + "WidgetType": "LabelHeading", + "WidgetName": " BackLight Technology Type Features", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " BackLight Technology: ", + "Visibility": "", + "Data": [ + "40", + "Blt_Control_06" + ], + "HelpText": "This feature allows OEM to select the Backlight Technology.", + "WidgetValues": [ + { + "Key": "LED Backlight", + "Value": "2" + }, + { + "Key": "CCFL Backlight", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Panel Rotation: ", + "Visibility": "", + "Data": [ + "40", + "Panel_Rotation_06" + ], + "HelpText": "This feature specifies the Panel Rotation of LFP panel used.", + "WidgetValues": [ + { + "Key": "0 degree", + "Value": "0" + }, + { + "Key": "180 degree", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Panel Position: ", + "Visibility": "", + "Data": [ + "40", + "Panel_Position_06" + ], + "HelpText": "This feature specifies the Panel Position of LFP panel used.", + "WidgetValues": [ + { + "Key": "Inside Shell", + "Value": "0" + }, + { + "Key": "Outside Shell", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Dual LFP Port Sync: ", + "Visibility": "", + "Data": [ + "42", + "EnablePortSync_Bit_06" + ], + "HelpText": "This feature will allow users to disable/enable Dual LFP Port Sync and it is applicable for DDI-A, DDI-B in case of eDP and DSI-0, DSI-1 in case of MIPI. \r\n.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " GPU Dithering for Banding artifacts: ", + "Visibility": "", + "Data": [ + "42", + "EnableDithering_Bit_06" + ], + "HelpText": "This field can be used to enable dithering from the source side for reducing banding artifacts on the visual quality features like DPST.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "Button", + "WidgetName": "Power Features", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Generic DTD Timings", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "LFP PnP ID Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Backlight Control Parameters", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Chromaticity Control", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "VESA DSC Parameters", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "LabelHeading", + "WidgetName": "Integrated MIPI DSI Settings", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:5120 or Block:2, Field:LFP2_Device_Class, Value:5120", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "MIPI Display Settings", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:5120 or Block:2, Field:LFP2_Device_Class, Value:5120", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "LabelHeading", + "WidgetName": "Integrated eDP Settings", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "eDP Fast Link Training Configuration Parameters", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "eDP Panel Power Sequencing Parameters", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Edp Max Port Link Rate (in 200 Khz): ", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [ + "27", + "eDP_Max_Port_Link_Rate_06" + ], + "HelpText": "This field specifies EDP Max Port Link Rate supported by the port in unit of 200KHz.\nDefault value would be \"0\", in which case Display Drivers should consider EDP Max Port Link Rate to be the Platform supported Max Link Rate.\nOnly when OEM's need to limit to particular Link Rate can enter the value as mentioned in below table.\n\nNote:\n1) OEM's need to enter the values mentioned from below table only.\n2) If value entered is not matching with any of the below values then Platform supported Max Link Rate should be considere as EDP Max Port Link Rate by the display drivers.\n3) In case of EDP Fast Link Training Params(FLT), if user enters FLT Link Rate value greater than the \"eDP Max Port Link Rate\" then we need to use \n Fast Link training Link Rate = MIN (FLT Link Rate , eDP Max Port Link Rate)\n---------------------------------------------------------\n|\tLink Rate(Gbps)\t|\t Value to enter in text field\t|\n|\t \t\t|\t in terms of 200KHZ \t|\n---------------------------------------------------------\n|\t 1.62 \t\t|\t 8100 \t|\n|\t 2.16 \t\t|\t 10800 \t|\n|\t 2.43 \t\t|\t 12150 \t|\n|\t 2.7 \t\t|\t 13500 \t|\n|\t 3.24 \t\t|\t 16200 \t|\n|\t 3.78 \t\t|\t 18900 \t|\n|\t 4.32 \t\t|\t 21600 \t|\n|\t 5.4 \t\t|\t 27000 \t|\n|\t 6.48 \t\t|\t 32400 \t|\n|\t 6.75 \t\t|\t 33750 \t|\n|\t 8.1 \t\t|\t 40500 \t|\n", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Panel Color Depth: ", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [ + "27", + "eDP_Panel_Color_Depth_06" + ], + "HelpText": "This feature specifies the color depth of eDP panel used.", + "WidgetValues": [ + { + "Key": "18-bit Color Depth", + "Value": "0" + }, + { + "Key": "24-bit Color Depth", + "Value": "1" + }, + { + "Key": "30-bit Color Depth", + "Value": "2" + }, + { + "Key": "36-bit Color Depth", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Select VSwing/Pre-Emphasis table : ", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [ + "27", + "eDP_VswingPreEmph_6" + ], + "HelpText": "This feature selects the VSwing Pre-Emphasis setting table to be used. For Tigerlake, based on the selection respective table will be used.\nTables for Tigerlake:\nLow Power VSwing Pre-Emphasis Setting Table:\nFor HBR2:\n\t\t\t\t\t\t Pre-Emphasis (db)\n\t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\nVoltage \t\t Level-0/200mV \t\t 200mV, 0.0db \t\t 200mV, 1.9db \t\t 200mV, 3.5db \t\t 200mV, 4.9db\nSwing \t\t Level-1/250mV \t\t 250mV, 0.0db \t\t 250mV, 1.6db \t\t 250mV, 2.9db \t\t N/A\n(mV) \t\t Level-2/300mV \t\t 300mV, 0.0db \t\t 300mV, 1.3db \t\t N/A \t\t N/A\n\t\t Level-3/350mV \t\t 350mV, 0.0db \t\t N/A \t\t N/A \t\t N/A\n\n\nFor HBR3:\n\t\t\t\t\t\t Pre-Emphasis (db)\n\t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\nVoltage \t\t Level-0/350mV \t\t 350mV, 0.0db \t\t 350mV, 3.1db \t\t 350mV, 6.0db \t\t 350mV, 8.2db\nSwing \t\t Level-1/500mV \t\t 500mV, 0.0db \t\t 500mV, 2.9db \t\t 500mV, 5.1db \t\t N/A\n(mV) \t\t Level-2/650mV \t\t 650mV, 0.6db \t\t 600mV, 3.5db \t\t N/A \t\t N/A\n\t\t Level-3/900mV \t\t 900mV, 0.0db \t\t N/A \t\t N/A \t\t N/A\n\n\nDefault VSwing Pre-Emphasis Setting Table:\nFor HBR:\n\t\t\t\t\t\t Pre-Emphasis (db)\n\t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\nVoltage \t\t Level-0/350mV \t\t 350mV, 0.0db \t\t 350mV, 3.1db \t\t 350mV, 6.0db \t\t 350mV, 8.2db\nSwing \t\t Level-1/500mV \t\t 500mV, 0.0db \t\t 500mV, 2.9db \t\t 500mV, 5.1db \t\t N/A\n(mV) \t\t Level-2/650mV \t\t 650mV, 0.6db \t\t 600mV, 3.5db \t\t N/A \t\t N/A\n\t\t Level-3/900mV \t\t 900mV, 0.0db \t\t N/A \t\t N/A \t\t N/A\n\n\nFor HBR2:\n\t\t\t\t\t\t Pre-Emphasis (db)\n\t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\nVoltage \t\t Level-0/350mV \t\t 350mV, 0.0db \t\t 350mV, 3.1db \t\t 350mV, 6.0db \t\t 350mV, 8.2db\nSwing \t\t Level-1/500mV \t\t 500mV, 0.0db \t\t 500mV, 2.9db \t\t 500mV, 5.1db \t\t N/A\n(mV) \t\t Level-2/650mV \t\t 650mV, 0.6db \t\t 600mV, 3.5db \t\t N/A \t\t N/A\n\t\t Level-3/900mV \t\t 900mV, 0.0db \t\t N/A \t\t N/A \t\t N/A", + "WidgetValues": [ + { + "Key": "Default VSwing/Pre-Emphasis Table", + "Value": "1" + }, + { + "Key": "Low Power VSwing/Pre-Emphasis Table", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " eDP Spread Spectrum Clock: ", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [ + "40", + "Enable_SSC06" + ], + "HelpText": "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Pixel Overlap Count: ", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [ + "42", + "PixelOverlapCount_06" + ], + "HelpText": "Select the number of Pixels to be overlapped per half of Scanline while using Edp Multi-SST(MSO) feature.", + "WidgetValues": [ + { + "Key": "Zero Pixel Overlap", + "Value": "0" + }, + { + "Key": "One Pixel Overlap", + "Value": "1" + }, + { + "Key": "Two Pixel Overlap", + "Value": "2" + }, + { + "Key": "Three Pixel Overlap", + "Value": "3" + }, + { + "Key": "Four Pixel Overlap", + "Value": "4" + }, + { + "Key": "Five Pixel Overlap", + "Value": "5" + }, + { + "Key": "Six Pixel Overlap", + "Value": "6" + }, + { + "Key": "Seven Pixel Overlap", + "Value": "7" + }, + { + "Key": "Eight Pixel Overlap", + "Value": "8" + } + ] + }, + { + "WidgetType": "Button", + "WidgetName": "PSR Feature", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Apical Feature", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [], + "HelpText": "", + "WidgetValues": [] + } + ], + "NestedPages": [ + { + "Type": "Block", + "Block": { + "PageNum": "5-2-6-1", + "PageName": "eDP Panel Power Sequencing Parameters", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " T3 optimization: ", + "Visibility": "", + "Data": [ + "27", + "eDP_T3_Optimization_06" + ], + "HelpText": "This feature enables or disables T3 optimization.\nWhen enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\nWhen disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "LCDVCC to HPD high delay (T3): ", + "Visibility": "", + "Data": [ + "27", + "eDP_Vcc_To_Hpd_Delay_06" + ], + "HelpText": "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\nValid Range: 0 to 200msec", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Valid video data to Backlight Enable delay (T8): ", + "Visibility": "", + "Data": [ + "27", + "eDP_DataOn_To_BkltEnable_Delay_06" + ], + "HelpText": "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\nT8 is inclusive of T7.\nValid Range of T7: 0 to 50msec", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "PWM-On To Backlight Enable delay: ", + "Visibility": "", + "Data": [ + "27", + "eDP_PwmOn_To_Bklt_Enable_Delay_06" + ], + "HelpText": "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\nDelay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\nSo it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Backlight Disable to PWM-Off delay: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Bklt_Disable_To_PwmOff_Delay_06" + ], + "HelpText": "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\nDelay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\nSo it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Backlight Disable to End of Valid video data delay (T9): ", + "Visibility": "", + "Data": [ + "27", + "eDP_BkltDisable_To_DataOff_Delay_06" + ], + "HelpText": "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "End of Valid video data to Power-Off delay (T10): ", + "Visibility": "", + "Data": [ + "27", + "eDP_DataOff_To_PowerOff_Delay_06" + ], + "HelpText": "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\nValid Range: 0 to 500 msec", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Power-off time (T12): ", + "Visibility": "", + "Data": [ + "27", + "eDP_PowerCycle_Delay_06" + ], + "HelpText": "Using this field Power-off time can be specified in 100uS.", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-6-2", + "PageName": "eDP Fast Link Training Configuration Parameters", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Is FastLinkTraining Feature Supported: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Fast_Link_Training_Supported_06" + ], + "HelpText": "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled.", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Data Rate: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Fast_Link_Training_Data_Rate_06" + ], + "HelpText": "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. It will be used if the sink indicates that no aux handshake is required during link training.\n\nIn case of EDP Fast Link Training Params(FLT), if user enters FLT Link Rate value greater than the \"eDP Max Port Link Rate\" then driver would use \n Fast Link training Link Rate = MIN (FLT Link Rate , eDP Max Port Link Rate).", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Lane Count: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Link_LaneCount_06" + ], + "HelpText": "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. It will be used if the sink indicates that no aux handshake is required during link training.", + "WidgetValues": [ + { + "Key": "x1", + "Value": "0" + }, + { + "Key": "x2", + "Value": "1" + }, + { + "Key": "x4", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Pre-Emphasis: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Link_PreEmp_06" + ], + "HelpText": "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. It will be used if the sink indicates that no aux handshake is required during link training.", + "WidgetValues": [ + { + "Key": "Level-0", + "Value": "0" + }, + { + "Key": "Level-1", + "Value": "1" + }, + { + "Key": "Level-2", + "Value": "2" + }, + { + "Key": "Level-3", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Voltage Swing: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Link_Vswing_06" + ], + "HelpText": "This feature allows for the selection of the Voltage Swing value for the embedded DP link. It will be used if the sink indicates that no aux handshake is required during link training.", + "WidgetValues": [ + { + "Key": "Swing-0", + "Value": "0" + }, + { + "Key": "Swing-1", + "Value": "1" + }, + { + "Key": "Swing-2", + "Value": "2" + }, + { + "Key": "Swing-3", + "Value": "3" + } + ] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-6-3", + "PageName": "PSR Feature", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Full Link enable: ", + "Visibility": "", + "Data": [ + "9", + "PSR_FullLink_Enable_06" + ], + "HelpText": "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state.", + "WidgetValues": [ + { + "Key": "No", + "Value": "0" + }, + { + "Key": "Yes", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Require AUX to wake up: ", + "Visibility": "", + "Data": [ + "9", + "PSR_Require_AUX2Wakeup_06" + ], + "HelpText": "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used.", + "WidgetValues": [ + { + "Key": "No", + "Value": "0" + }, + { + "Key": "Yes", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Lines to wait before link standby: ", + "Visibility": "", + "Data": [ + "9", + "PSR_Lines2Wait_B4LinkS3_06" + ], + "HelpText": "This field determines Lines to wait before link standby\n0 lines to wait (Default)\n1 lines to wait\n4 lines to wait\n8 lines to wait\nOthers Reserved", + "WidgetValues": [ + { + "Key": "0 lines to wait", + "Value": "0" + }, + { + "Key": "1 lines to wait", + "Value": "1" + }, + { + "Key": "4 lines to wait", + "Value": "2" + }, + { + "Key": "8 lines to wait", + "Value": "3" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Idle frames to wait: ", + "Visibility": "", + "Data": [ + "9", + "PSR_IdleFrames2Wait_06" + ], + "HelpText": "Idle frames to wait for PSR enable.\nAllowed values 0-15. Default value is 0.", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Clock Recovery Time: ", + "Visibility": "", + "Data": [ + "9", + "PSR_TP1_WaitTime_06" + ], + "HelpText": "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)", + "WidgetValues": [ + { + "Key": "500 usec", + "Value": "0" + }, + { + "Key": "100 usec", + "Value": "1" + }, + { + "Key": "2.5 msec", + "Value": "2" + }, + { + "Key": "0 (Skip)", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Channel Equalization Time for PSR1 panel: ", + "Visibility": "", + "Data": [ + "9", + "PSR1_TP_2_3_4_WaitTime_06" + ], + "HelpText": "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) or TP4(Training Pattern4) time during PSR1 exit(wake up)", + "WidgetValues": [ + { + "Key": "500 usec", + "Value": "0" + }, + { + "Key": "100 usec", + "Value": "1" + }, + { + "Key": "2.5 msec", + "Value": "2" + }, + { + "Key": "0 (Skip)", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Channel Equalization Time for PSR2 panel: ", + "Visibility": "", + "Data": [ + "9", + "PSR2_TP_2_3_4_WaitTime_06" + ], + "HelpText": "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) or TP4(Training Pattern4) time during PSR2 exit(wake up)", + "WidgetValues": [ + { + "Key": "500 usec", + "Value": "0" + }, + { + "Key": "100 usec", + "Value": "1" + }, + { + "Key": "2.5 msec", + "Value": "2" + }, + { + "Key": "50 usec", + "Value": "3" + } + ] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-6-4", + "PageName": "Apical Feature", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Apical Assertive Display IP: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Apical_Display_Ip_Enable_06" + ], + "HelpText": "This field enables/disables the Apical Assertive Display IP for this panel.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Panel OUI (IEEE OUI): ", + "Visibility": "", + "Data": [ + "27", + "eDP_Panel_Oui_06" + ], + "HelpText": "This field specifies the Apical IP specific Panel OUI field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " DPCD Base Address: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Dpcd_Base_Address_06" + ], + "HelpText": "This field specifies the Apical IP specific DPCD base address field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " DPCD Irdidix Control 0: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Dpcd_Irdidix_Control0_06" + ], + "HelpText": "This field specifies the Apical IP specific DPCD Irdidix control 0 field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " DPCD Option Select: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Dpcd_Option_Select_06" + ], + "HelpText": "This field specifies the Apical IP specific DPCD option select field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " DPCD Backlight: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Dpcd_Backlight_06" + ], + "HelpText": "This field specifies the Apical IP specific backlight value.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Ambient Light: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Ambient_Light_06" + ], + "HelpText": "This field specifies the Apical IP specific Ambient light value.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Backlight scale: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Backlight_Scale_06" + ], + "HelpText": "This field specifies the Apical IP specific backlight scale field.", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-6-5", + "PageName": "Power Features", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Intel Display Power Saving Technology (DPST) (Mobile only): ", + "Visibility": "", + "Data": [ + "44", + "DPST_Enable_06" + ], + "HelpText": "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled.\nIntel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power.\nNote: This technology is only active when the system is running in battery mode and the LFP is the only active display device.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Intel Display Refresh Rate Switching (DRRS) (Mobile only): ", + "Visibility": "", + "Data": [ + "44", + "DRRS_Enable_06" + ], + "HelpText": "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Edge Luminance Profile (ELP) : ", + "Visibility": "", + "Data": [ + "44", + "ELP_Enable_06" + ], + "HelpText": "This feature determines whether the ELP feature is enabled or disabled.\nEdge Luminance Profile (ELP) is a panel technology which reduce luminance on the edge of screen to save panel power.\nNote:This technology cannot co-exist with DPST and OPST ((i.e.) OPST, DPST and ELP cannot exist together.They are all mutually exclusive to each other.)", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " OLED Power Saving Technology (OPST) : ", + "Visibility": "", + "Data": [ + "44", + "OPST_Enable_06" + ], + "HelpText": "This feature determines whether the OPST feature is enabled or disabled.\nOLED Power Saving Technology (OPST) is a panel technology which saves power by intelligent, adaptive dimming of midrange pixel values more aggressively than the extremes without compromising the viewability.\nNote: This technology cannot co-exist with ELP and DPST ((i.e.) OPST, DPST and ELP cannot exist together.They are all mutually exclusive to each other.)", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Dynamic Media Refresh Rate Switching Enable/Disable ", + "Visibility": "", + "Data": [ + "44", + "DMRRS_Enable_06" + ], + "HelpText": "This feature determines whether Dynamic media refresh rate switching is to be enabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Enable Display Lace Support: ", + "Visibility": "", + "Data": [ + "44", + "LACE_Enable_06" + ], + "HelpText": "This feature, when enabled, will set Display Lace Support otherwise, the functionality will be disabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Panel Self Refresh (PSR): ", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [ + "44", + "PSR_Enable_06" + ], + "HelpText": "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Assertive Display Technology Enable/Disable: ", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [ + "44", + "ADT_Enable_06" + ], + "HelpText": "This feature determines whether Assertive display technology is to be enabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Intel Automatic Display Brightness (ADB) (Mobile only): ", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [ + "44", + "ADB_Enable_06" + ], + "HelpText": "This feature determines whether Intel Automatic Display Brightness is to be enabled. Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) depending on the current ambient light environment.\nWhen enabled, the driver and VBIOS will control the backlight brightness of the LFP depending on the ambient environment if and only if the LFP is the only active display. When disabled, the driver will perform no action.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "EDP 4k/2k HOBL Feature: ", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [ + "44", + "eDP_4k_2k_HOBL_feature_Enable_06" + ], + "HelpText": "This feature will allow users to disable/enable the edp 4k/2k HOBL(Hours Of Battery Life) feature by programming relevant registers specific for a platform.\r\n.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Default Display LACE Enabled status: ", + "Visibility": "", + "Data": [ + "44", + "LACE_Status_06" + ], + "HelpText": "This feature, when enabled, will set Default Display LACE Enabled status otherwise, the functionality will be disabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "DPST Aggressiveness Level: ", + "Visibility": "", + "Data": [ + "44", + "DPST_Aggressiveness_Profile_06" + ], + "HelpText": "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n1 (Maximum Quality with No DPST)\n2\n3\n4\n5\n6 (Maximum Battery)", + "WidgetValues": [ + { + "Key": "1 - Maximum Quality with No DPST", + "Value": "1" + }, + { + "Key": "2", + "Value": "2" + }, + { + "Key": "3", + "Value": "3" + }, + { + "Key": "4", + "Value": "4" + }, + { + "Key": "5", + "Value": "5" + }, + { + "Key": "6 - Maximum Battery", + "Value": "6" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "LACE Aggressiveness Level: ", + "Visibility": "", + "Data": [ + "44", + "LACE_Aggressiveness_Profile_06" + ], + "HelpText": "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\nMinimum 0\nModerate 1\nHigh 2", + "WidgetValues": [ + { + "Key": "Minimum", + "Value": "0" + }, + { + "Key": "Moderate", + "Value": "1" + }, + { + "Key": "High", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "ELP Aggressiveness Level: ", + "Visibility": "", + "Data": [ + "44", + "ELP_Aggressiveness_Profile_06" + ], + "HelpText": "This feature allows for the selection of ELP Aggressiveness level for this Panel Type.\nMinimum Power Savings\nMedium Power Savings \nMaximum Power Savings", + "WidgetValues": [ + { + "Key": "Minimum Power Savings", + "Value": "0" + }, + { + "Key": "Medium Power Savings", + "Value": "1" + }, + { + "Key": "Maximum Power Savings", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "OPST Aggressiveness Level: ", + "Visibility": "", + "Data": [ + "44", + "OPST_Aggressiveness_Profile_06" + ], + "HelpText": "This feature allows for the selection of OPST Aggressiveness level for this Panel Type.\nMinimum Power Savings\nMedium Power Savings \nMaximum Power Savings", + "WidgetValues": [ + { + "Key": "Minimum Power Savings", + "Value": "0" + }, + { + "Key": "Medium Power Savings", + "Value": "1" + }, + { + "Key": "Maximum Power Savings", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Default Display VRR Enabled status: ", + "Visibility": "", + "Data": [ + "44", + "VRR_Status_06" + ], + "HelpText": "VRR (Variable Refresh Rate) is a feature that can continuously and seamlessly vary Refresh Rate on the fly, on displays that support Variable Refresh rate Technologies.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-6-6", + "PageName": "Generic DTD Timings", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Pixel Clock in KHz: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_Pixel_CLK_06" + ], + "HelpText": "Pixel Clock (in KHz) Range from 0.001 to 4294967.295 MP/s.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Active: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_Active_06" + ], + "HelpText": "Horizontal Active Image Pixels Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Active: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_Active_06" + ], + "HelpText": "Vertical Active Image Lines Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Blank: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_Blank_06" + ], + "HelpText": "Horizontal Blank Pixels Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Blank: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_Blank_06" + ], + "HelpText": "Vertical Blank lines Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Front Porch: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_FrontPorch_06" + ], + "HelpText": "Horizontal Front Porch Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Front Porch: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_FrontPorch_06" + ], + "HelpText": "Vertical Front Porch Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Sync: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_Sync_06" + ], + "HelpText": "Horizontal Sync Width Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Sync: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_Sync_06" + ], + "HelpText": "Vertical Sync Width Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Image Size: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_Image_Size_06" + ], + "HelpText": "Horizontal Addressable Video Image Size in mm represented by 16bits. Image size multiplier 1.00 mm precision.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Image Size: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_Image_Size_06" + ], + "HelpText": "Vertical Addressable Video Image Size in mm represented by 16bits. Image size multiplier 1.00 mm precision.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryBin", + "WidgetName": "Common Flag: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_Common_Flag_06" + ], + "HelpText": "Common DTD Flags:\nBit 7 : Horizontal Sync Polarity\n1 : Positive\n0 : Negative\nBit 6 : Vertical Sync polarity\n1 : Positive\n0 : Negative\nBit 5 - 0: Reserved (Default value 0)", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-6-7", + "PageName": "LFP PnP ID Table", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Table", + "WidgetName": "", + "Visibility": "", + "Data": [ + "42", + "LFP_Panel_PnP_ID_06" + ], + "HelpText": "This feature allows the 10 bytes of EDID Vendor/Product ID starting at offset 08h to be used as a PnP ID.\n\nTable Definition:\n\tWord: ID Manufacturer Name\n\tWord: ID Product Code\n\tDWord: ID Serial Number\n\tByte: Week of Manufacture\n\tByte: Year of Manufacture", + "WidgetValues": [ + { + "ColumnName": "PnP ID", + "SizeinBytes": "1" + } + ] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-6-8", + "PageName": "Backlight Control Parameters", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Inverter Type: ", + "Visibility": "", + "Data": [ + "43", + "BLC_Inv_Type_06" + ], + "HelpText": "This feature allows for the selection of the Backlight Inverter type that is to be used to control the backlight brightness of the LFP.\nWhen PWM is selected, the driver and VBIOS will control the backlight brightness via the integrated PWM solution for the applicable chipsets.\nWhen None/External is selected, the system BIOS will control the backlight brightness via the external solution.", + "WidgetValues": [ + { + "Key": "None/External", + "Value": "0" + }, + { + "Key": "PWM", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Pwm Source Selection: ", + "Visibility": "", + "Data": [ + "43", + "Lfp_Pwm_Source_Selection_06" + ], + "HelpText": "If panel supports 'Intel HDR AUX Interface', it will always be chosen by default. If not, value in 'PWM Source Selection' will be used", + "WidgetValues": [ + { + "Key": "PWM From Display Engine", + "Value": "2" + }, + { + "Key": "PWM From LCD Panel", + "Value": "3" + }, + { + "Key": "Panel Driver Interface", + "Value": "4" + }, + { + "Key": "VESA eDP AUX Interface", + "Value": "5" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Pwm Controller Selection: ", + "Visibility": "", + "Data": [ + "43", + "Lfp_Pwm_Controller_Selection_06" + ], + "HelpText": "This field allows to select the PWM Controller to be used for the selected Local Flat Panel.This field allows to select the PWM Controller to be used for the selected Local Flat Panel.If Two LFPs are connected then PWM0 and PWM1 must be selected accordingly.", + "WidgetValues": [ + { + "Key": "PWM0", + "Value": "0" + }, + { + "Key": "PWM1", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Inverter Polarity: ", + "Visibility": "", + "Data": [ + "43", + "BLC_Inv_Polarity_06" + ], + "HelpText": "This feature allows the backlight inverter polarity to be specified.\nNormal means 0 value is minimum brightness.\nInverted means 0 value is maximum brightness.", + "WidgetValues": [ + { + "Key": "Normal", + "Value": "0" + }, + { + "Key": "Inverted", + "Value": "1" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Minimum Brightness: ", + "Visibility": "", + "Data": [ + "43", + "Post_Min_Brightness_06" + ], + "HelpText": "This feature allows defining the absolute minimum backlight brightness. The driver will never decrease the backlight less than this value. The value must be specified using normal polarity semantics. The value should range from 0 to 255 if the brightness precision bit is chosen to be 8, and it should range from 0 to 65535 if the precision bit is chosen to be 16.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "POST Backlight Intensity: ", + "Visibility": "", + "Data": [ + "43", + "Post_Brightness_06" + ], + "HelpText": "This feature is used to set default backlight brightness value of the panel at POST. The value should range from 0 to 255 if the bit precision is chosen to be 8 and it should range from 0 to 65535 if the brightness bit precision is chosent to be 16.", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Brightness Precision Bits: ", + "Visibility": "", + "Data": [ + "43", + "BrightnessPrecisionBits_06" + ], + "HelpText": "This field represents the range of brightness in terms of bit precision.\n 8 = Brightness range of 0 to 255.\n 16 = Brightness range of 0 to 65535", + "WidgetValues": [ + { + "Key": "8", + "Value": "8" + }, + { + "Key": "16", + "Value": "16" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "PWM Inverter Frequency (Hz): ", + "Visibility": "", + "Data": [ + "43", + "PWM_Frequency_06" + ], + "HelpText": "This feature allows for the definition of the frequency needed for PWM Inverter.\nNote: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Intel HDR DPCD Refresh Timeout (unit - 10 micro seconds): ", + "Visibility": "", + "Data": [ + "43", + "HdrDpcdRefreshTimeout_06" + ], + "HelpText": "This field allows to configure the refresh timeout of Intel HDR DPCDs for different TCON Vendors.\nNote:\n\tThe value is in units of 10 microseconds.\n\tThe range (entered as a decimal number), for the timeout is 0-65535", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-6-9", + "PageName": "Chromaticity Control", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Chromaticity Control Feature: ", + "Visibility": "", + "Data": [ + "46", + "Chromacity_Enable_06" + ], + "HelpText": "This bit enables Chromaticity feature.\nIf this bit is enabled, EDID values for chromaticity will be used, else feature is disabled.\nFeature will be supported for Panels that support EDID version 1.4 or higher.\nPlease refer to section 3.7 of EDID Specification 1.4.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Override the EDID values: ", + "Visibility": "", + "Data": [ + "46", + "Override_EDID_Data_06" + ], + "HelpText": "This option when enabled along with Chromaticity feature will override EDID values through following VBT data", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Red_Green_bits (Bits 1:0 at 19h): ", + "Visibility": "", + "Data": [ + "46", + "Red_Green_06" + ], + "HelpText": "Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Blue_White_bits (Bits 1:0 at 1Ah): ", + "Visibility": "", + "Data": [ + "46", + "Blue_White_06" + ], + "HelpText": "Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Red_x (Bits 9:2 at 1Bh): ", + "Visibility": "", + "Data": [ + "46", + "Red_x_06" + ], + "HelpText": "Bits 9:2 of red color x coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Red_y (Bits 9:2 at 1Ch): ", + "Visibility": "", + "Data": [ + "46", + "Red_y_06" + ], + "HelpText": "Bits 9:2 of red color y coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Green_x (Bits 9:2 at 1Dh): ", + "Visibility": "", + "Data": [ + "46", + "Green_x_06" + ], + "HelpText": "Bits 9:2 of Green color x coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Green_y (Bits 9:2 at 1Eh): ", + "Visibility": "", + "Data": [ + "46", + "Green_y_06" + ], + "HelpText": "Bits 9:2 of Green color y coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Blue_x (Bits 9:2 at 1Fh): ", + "Visibility": "", + "Data": [ + "46", + "Blue_x_06" + ], + "HelpText": "Bits 9:2 of Blue color x coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Blue_y (Bits 9:2 at 20h): ", + "Visibility": "", + "Data": [ + "46", + "Blue_y_06" + ], + "HelpText": "Bits 9:2 of Blue color y coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " White_x (Bits 9:2 at 21h): ", + "Visibility": "", + "Data": [ + "46", + "White_x_06" + ], + "HelpText": "Bits 9:2 of White color x coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " White_y (Bits 9:2 at 22h): ", + "Visibility": "", + "Data": [ + "46", + "White_y_06" + ], + "HelpText": "Bits 9:2 of White color y coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Override Luminance values ", + "Visibility": "", + "Data": [ + "46", + "Override_LUM_Data_06" + ], + "HelpText": "This option when enabled along with Chromaticity feature will override luminance values following VBT values", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Minimum Luminance: ", + "Visibility": "", + "Data": [ + "46", + "MinLuminance_06" + ], + "HelpText": "Minimum luminance value.\n2 byte value, encoded in IEEE 754 half-precision binary floating point format,", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Maximum full frame luminance: ", + "Visibility": "", + "Data": [ + "46", + "MaxFullLuminance_06" + ], + "HelpText": "Maximum Full frame luminance value.\n2 byte value, encoded in IEEE 754 half-precision binary floating point format,", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Maximum Luminance: ", + "Visibility": "", + "Data": [ + "46", + "MaxLuminance_06" + ], + "HelpText": "Maximum luminance value(Relatively smaller portion of screen).\n2 byte value, encoded in IEEE 754 half-precision binary floating point format.", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Override Gamma values: ", + "Visibility": "", + "Data": [ + "46", + "Override_Gamma_Data_06" + ], + "HelpText": "This option when enabled along with Chromaticity feature will override gamma values through following VBT data", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Panel gamma: ", + "Visibility": "", + "Data": [ + "46", + "Gamma_06" + ], + "HelpText": "Value shall define the gamma range, from 1.00 to 3.54, as follows:\nField Value = (Gamma (value in float) x 100) - 100\nField values range from 00h through FFh.\nFFh = No gamma information shall be provided", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-6-10", + "PageName": "VESA DSC Parameters", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "DSC Major Version: ", + "Visibility": "", + "Data": [ + "56", + "C6_Major_Dsc_Version" + ], + "HelpText": "VESA DSC Major revision field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "DSC Minor Version: ", + "Visibility": "", + "Data": [ + "56", + "C6_Minor_Dsc_Version" + ], + "HelpText": "VESA DSC Minor revision field.", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Block prediction supported: ", + "Visibility": "", + "Data": [ + "56", + "C6_Blk_Prediction_En" + ], + "HelpText": "Sink supports block prediction as per the VESA DSC Spec.", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "RC Buffer Block size as per VESA DSC Spec: ", + "Visibility": "", + "Data": [ + "56", + "C6_RC_Block_Size" + ], + "HelpText": "RC buffer block size for a single RC buffer as defined by the VESA DSC spec.", + "WidgetValues": [ + { + "Key": "1 KB", + "Value": "0" + }, + { + "Key": "4 KB", + "Value": "1" + }, + { + "Key": "16 KB", + "Value": "2" + }, + { + "Key": "64 KB", + "Value": "3" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Number of RC buffer blocks as per VESA DSC Spec: ", + "Visibility": "", + "Data": [ + "56", + "C6_Dsc_RC_Buf_Size" + ], + "HelpText": "This field defines the number of RC buffers as per VESA DSC spec.\nThe number of RC buffers used by the software shall be (Value + 1) where Value is in range 0 to 127.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryBin", + "WidgetName": "Slices per line supported by the sink device: ", + "Visibility": "", + "Data": [ + "56", + "C6_Dsc_Slices_Per_Line" + ], + "HelpText": "This field defines the slices per line supported by the sink device.\nThe field is defined in bitmap fashion and details of each bits are as defined below:\n\tBits 31-10\t\t Bit 9\tBit 8\tBit 7\tBit 6\tBit 5\tBit 4\t Bit 3\t Bit 2\t Bit 1\t Bit 0\n\tReserved\t\t 24\t 20\t 16\t 12\t 10\t 8\t 6\t 4\t 2\t 1\nBit = 0, not supported. Bit = 1, supported\nNote: Assumption is that sink shall support all lower slices per line than maximum selected field. i.e. If it supports say 8 slices per line, it will also support 4/2/1 slices per line", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Line buffer depth as per VESA DSC Spec: ", + "Visibility": "", + "Data": [ + "56", + "C6_Line_Buffer_Depth" + ], + "HelpText": "Line buffer depth in bits as per VESA DSC spec.", + "WidgetValues": [ + { + "Key": "8 bits", + "Value": "0" + }, + { + "Key": "9 bits", + "Value": "1" + }, + { + "Key": "10 bits", + "Value": "2" + }, + { + "Key": "11 bits", + "Value": "3" + }, + { + "Key": "12 bits", + "Value": "4" + }, + { + "Key": "13 bits", + "Value": "5" + }, + { + "Key": "14 bits", + "Value": "6" + }, + { + "Key": "15 bits", + "Value": "7" + }, + { + "Key": "16 bits", + "Value": "8" + } + ] + }, + { + "WidgetType": "EntryBin", + "WidgetName": "Input compression BPC supported by the sink device: ", + "Visibility": "", + "Data": [ + "56", + "C6_Dsc_Bpc" + ], + "HelpText": "This field defines the compression input bpc supported by the sink device.\nThe field is defined in bitmap fashion and details of each bits are as defined below:\n\tBits 7-4\t Bit 3\t Bit 2\t Bit 1\t Bit 0\n\tRsvd\t 12 bpc\t 10bpc\t 8bpc\t Rsvd\nBit = 0, not supported. Bit = 1, supported\nNote: Assumption is that sink shall support all lower bpc values than the maximum selected field. i.e. If it supports say 12bpc, it will also support 10 and 8bpc as well", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Maximum supported compression BPP: ", + "Visibility": "", + "Data": [ + "56", + "C6_Dsc_Max_Bpp" + ], + "HelpText": "As of today, we are supporting 6/8/10/12 BPP for compression output.\nSelect the most appropriate BPP as supported by the sink.", + "WidgetValues": [ + { + "Key": "6 Bits per pixel", + "Value": "0" + }, + { + "Key": "8 Bits per pixel", + "Value": "1" + }, + { + "Key": "10 Bits per pixel", + "Value": "2" + }, + { + "Key": "12 Bits per pixel", + "Value": "3" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Slice height supported by the sink device: ", + "Visibility": "", + "Data": [ + "56", + "C6_Dsc_Slice_Height" + ], + "HelpText": "Slice height supported by the sink device for DSC slice.\nNote: Slice height must divide the picture height uniformly.", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-6-11", + "PageName": "MIPI Display Settings", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:5120 or Block:2, Field:LFP2_Device_Class, Value:5120", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Label", + "WidgetName": "MIPI DSI Controller Configuration Settings", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Video/Command Mode: ", + "Visibility": "", + "Data": [ + "52", + "Video_Command_Mode_06" + ], + "HelpText": "This feature helps in selecting Video/Command Mode.", + "WidgetValues": [ + { + "Key": "Video Mode", + "Value": "0" + }, + { + "Key": "Command Mode", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Packet Sequence For Video Mode: ", + "Visibility": "", + "Data": [ + "52", + "Packet_Sequence_Video_Mode_06" + ], + "HelpText": "This feature helps in selecting packet sequence for Video Mode.\nNon-burst with sync pulse\nNon-burst with sync events\nBurst mode", + "WidgetValues": [ + { + "Key": "Non-burst with sync pulse", + "Value": "1" + }, + { + "Key": "Non-burst with sync events", + "Value": "2" + }, + { + "Key": "Burst Mode", + "Value": "3" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Required Burst Mode Rate (in Kbps): ", + "Visibility": "", + "Data": [ + "52", + "RequiredBurstModeRate_06" + ], + "HelpText": "This feature allows to enter Required Burst Mode Rate in Kilo bits per sec. This should be greater than Non-Burst Mode Rate\nThis value is valid only if packet sequence for video mode is Burst Mode.", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Colour Format In Video Mode: ", + "Visibility": "", + "Data": [ + "52", + "Colour_Format_Video_Mode_06" + ], + "HelpText": "This feature helps in selecting supported colour format in Video Mode.", + "WidgetValues": [ + { + "Key": "RGB565", + "Value": "1" + }, + { + "Key": "RGB666", + "Value": "2" + }, + { + "Key": "RGB 666(Loosely Packed Format)", + "Value": "3" + }, + { + "Key": "RGB888", + "Value": "4" + }, + { + "Key": "RGB101010", + "Value": "5" + }, + { + "Key": "RGB121212", + "Value": "6" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Dual Link Support: ", + "Visibility": "", + "Data": [ + "52", + "Dual_Link_06" + ], + "HelpText": "This feature allows to select type of dual link.", + "WidgetValues": [ + { + "Key": "Dual Link Not Supported", + "Value": "0" + }, + { + "Key": "Dual Link Front Back Mode", + "Value": "1" + }, + { + "Key": "Dual Link Pixel Alternative Mode", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Pixel Overlap Count(Z-Inversion): ", + "Visibility": "", + "Data": [ + "42", + "PixelOverlapCount_06" + ], + "HelpText": "Select the number of Pixels to be overlapped per half of Scanline while using\nMIPI Dual Link Front-Back video mode.", + "WidgetValues": [ + { + "Key": "Zero Pixel Overlap", + "Value": "0" + }, + { + "Key": "One Pixel Overlap", + "Value": "1" + }, + { + "Key": "Two Pixels Overlap", + "Value": "2" + }, + { + "Key": "Three Pixels Overlap", + "Value": "3" + }, + { + "Key": "Four Pixel Overlap", + "Value": "4" + }, + { + "Key": "Five Pixel Overlap", + "Value": "5" + }, + { + "Key": "Six Pixels Overlap", + "Value": "6" + }, + { + "Key": "Seven Pixels Overlap", + "Value": "7" + }, + { + "Key": "Eight Pixel Overlap", + "Value": "8" + }, + { + "Key": "Nine Pixel Overlap", + "Value": "9" + }, + { + "Key": "Ten Pixels Overlap", + "Value": "10" + }, + { + "Key": "Eleven Pixels Overlap", + "Value": "11" + }, + { + "Key": "Twelve Pixel Overlap", + "Value": "12" + }, + { + "Key": "Thirteen Pixels Overlap", + "Value": "13" + }, + { + "Key": "Fourteen Pixels Overlap", + "Value": "14" + }, + { + "Key": "Fifteen Pixels Overlap", + "Value": "15" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " CABC Support: ", + "Visibility": "", + "Data": [ + "52", + "CABC_Support_06" + ], + "HelpText": "This feature helps in selecting CABC_Support.", + "WidgetValues": [ + { + "Key": "Disabled", + "Value": "0" + }, + { + "Key": "Enabled", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " CABC On/Off Commands: ", + "Visibility": "", + "Data": [ + "52", + "CabcCmdsPort_06" + ], + "HelpText": "Select the MIPI Port for sending CABC On/Off Commands in case of Dual link MIPI panels\nThis field is ignored in single link MIPI case", + "WidgetValues": [ + { + "Key": "MIPI DSI-0", + "Value": "0" + }, + { + "Key": "MIPI DSI-1", + "Value": "1" + }, + { + "Key": "Both MIPI DSI-0 and DSI-1", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Panel PWM/BkltController On/Off Commands: ", + "Visibility": "", + "Data": [ + "52", + "PanelPwmCmdsPort_06" + ], + "HelpText": "Select the MIPI Port for sending Panel PWM/BkltController On/Off Commands in case of Dual link MIPI panels\nThis field is ignored in single link MIPI case", + "WidgetValues": [ + { + "Key": "MIPI DSI-0", + "Value": "0" + }, + { + "Key": "MIPI DSI-1", + "Value": "1" + }, + { + "Key": "Both MIPI DSI-0 and DSI-1", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " RGB/BGR Panel Selection: ", + "Visibility": "", + "Data": [ + "52", + "RgbFlip_06" + ], + "HelpText": "Select if the panel is RGB or BGR", + "WidgetValues": [ + { + "Key": "RGB Panel", + "Value": "0" + }, + { + "Key": "BGR Panel", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Number Of Data Lanes: ", + "Visibility": "", + "Data": [ + "52", + "Number_Of_Lanes_06" + ], + "HelpText": "This feature allows to select number of data lanes going to use for MIPI DSI", + "WidgetValues": [ + { + "Key": "1", + "Value": "0" + }, + { + "Key": "2", + "Value": "1" + }, + { + "Key": "3", + "Value": "2" + }, + { + "Key": "4", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Sending Bus Turn Around (BTA): ", + "Visibility": "", + "Data": [ + "52", + "Bta_Disable_06" + ], + "HelpText": "Enable or Disable sending Bus Turn Around to the Peripheral", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "0" + }, + { + "Key": "Disabled", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Escape Clock: ", + "Visibility": "", + "Data": [ + "52", + "EscapeClk_06" + ], + "HelpText": "This feature helps to select frequency of Escape Clk.", + "WidgetValues": [ + { + "Key": "20 MHz", + "Value": "0" + }, + { + "Key": "10 MHz", + "Value": "1" + }, + { + "Key": "5 MHz", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " EoT Packet Transmission: ", + "Visibility": "", + "Data": [ + "52", + "EoTpSupport_06" + ], + "HelpText": "This feature helps to either enable or disable EoT packet Transmission", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "0" + }, + { + "Key": "Disabled", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Clock Stop Feature: ", + "Visibility": "", + "Data": [ + "52", + "ClockStop_06" + ], + "HelpText": "To enable or disable clock stopping feature during BLLP timing in a MIPI DPI (video) mode", + "WidgetValues": [ + { + "Key": "Disabled", + "Value": "0" + }, + { + "Key": "Enabled", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " LP Clock During LPM: ", + "Visibility": "", + "Data": [ + "52", + "LpClockDuringLpm_06" + ], + "HelpText": "In continuous clock mode (Clock Stop Feature disabled), Clock lane will always be in HS mode.\nIf this feature is enabled, Clock lane also goes to LP state once per frame during the mandated data lane LPM\nin MIPI DSI DPI (video) mode", + "WidgetValues": [ + { + "Key": "Disabled", + "Value": "0" + }, + { + "Key": "Enabled", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Blanking During BLLP: ", + "Visibility": "", + "Data": [ + "52", + "BlankingDuringBllp_06" + ], + "HelpText": "This feature helps to send Blanking packets during BLLP regions in a MIPI DSI DPI (video) mode.", + "WidgetValues": [ + { + "Key": "Disabled", + "Value": "0" + }, + { + "Key": "Enabled", + "Value": "1" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " TClkPrepare: ", + "Visibility": "", + "Data": [ + "52", + "TClkPrepare_06" + ], + "HelpText": "This feature allows to enter TClkPrepare in ns.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " TClkTrail: ", + "Visibility": "", + "Data": [ + "52", + "TClkTrail_06" + ], + "HelpText": "This feature allows to enter TClkTrail in ns.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " TClkPrepare + TClkZero: ", + "Visibility": "", + "Data": [ + "52", + "TClkPrepareTClkZero_06" + ], + "HelpText": "This feature allows to enter TClkPrepare + TClkZero in ns.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " THsPrepare: ", + "Visibility": "", + "Data": [ + "52", + "THsPrepare_06" + ], + "HelpText": "This feature allows to enter THsPrepare in ns.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " THsTrail: ", + "Visibility": "", + "Data": [ + "52", + "THsTrail_06" + ], + "HelpText": "This feature allows to enter THsTrail in ns.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " THsPrepare + THsZero: ", + "Visibility": "", + "Data": [ + "52", + "THsPrepareTHsZero_06" + ], + "HelpText": "This feature allows to enter THsPrepare + THsZero in ns.", + "WidgetValues": [] + }, + { + "WidgetType": "Label", + "WidgetName": "MIPI DSI Panel Power On/Off Sequence(delays)", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Power-Up Delay: ", + "Visibility": "", + "Data": [ + "52", + "PowerUpDelay_06" + ], + "HelpText": "Delay to be given after panel power up in 100uS", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Data Turn-On To Panel Backlight Enable Delay: ", + "Visibility": "", + "Data": [ + "52", + "DataTurnOnToPanelBacklightEnableDelay_06" + ], + "HelpText": "Delay to be given after MIPI DATA TURN ON and before backlight enabling in 100uS", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Pwm-On To Backlight Enable Delay: ", + "Visibility": "", + "Data": [ + "52", + "Mipi_PwmOn_To_Bklt_Enable_Delay_06" + ], + "HelpText": "Delay to be given after PWM-On and before Backlight Enable in 100uS\nDelay from PWM-On to Backlight Enable is included in delay from Data Turn-On to Panel Backlight Enable.\nSo it is expected that delay from PWM-On to Backlight Enable is less than the delay from Data Turn-On to Panel Backlight Enable.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Backlight Disable To Pwm-Off Delay: ", + "Visibility": "", + "Data": [ + "52", + "Mipi_Bklt_Disable_To_PwmOff_Delay_06" + ], + "HelpText": "Delay to be given after Backlight Disable and before Pwm-Off in 100uS\nDelay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to Data Turn-Off.\nSo it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to Data Turn-Off.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Backlight Disable To Data Turn-Off Delay: ", + "Visibility": "", + "Data": [ + "52", + "BacklightOffToDataTurnOffDelay_06" + ], + "HelpText": "Delay to be given after Backlight Disable and before MIPI DATA TURN OFF in 100uS", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Power-Down Delay: ", + "Visibility": "", + "Data": [ + "52", + "PowerDownDelay_06" + ], + "HelpText": "Delay to be given before panel power down in 100uS", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Power-Cycle Delay: ", + "Visibility": "", + "Data": [ + "52", + "PowerCycleDelay_06" + ], + "HelpText": "Delay to be given before panel power up and after panel power down in 100uS", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + } + ] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-7", + "PageName": "Panel #07", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "LabelHeading", + "WidgetName": "Common LFP Features", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryAsci", + "WidgetName": " LFP Panel Name: ", + "Visibility": "", + "Data": [ + "42", + "Panel_Name_07" + ], + "HelpText": "This feature defines the LFP panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Target X-Res: ", + "Visibility": "", + "Data": [ + "42", + "Panel_Width_07" + ], + "HelpText": "This value specifies the Target X-Resolution for this panel.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Target Y-Res: ", + "Visibility": "", + "Data": [ + "42", + "Panel_Height_07" + ], + "HelpText": "This value specifies the Target Y-Resolution for this panel.", + "WidgetValues": [] + }, + { + "WidgetType": "LabelHeading", + "WidgetName": " DPS Panel Type Features", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Seamless DRRS Minimum Refresh Rate (Hz): ", + "Visibility": "", + "Data": [ + "42", + "Seamless_DRRS_Min_RR_07" + ], + "HelpText": "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\nNote: Graphics driver will use this field only when EDID support is disabled in VBT configuration.", + "WidgetValues": [] + }, + { + "WidgetType": "LabelHeading", + "WidgetName": " BackLight Technology Type Features", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " BackLight Technology: ", + "Visibility": "", + "Data": [ + "40", + "Blt_Control_07" + ], + "HelpText": "This feature allows OEM to select the Backlight Technology.", + "WidgetValues": [ + { + "Key": "LED Backlight", + "Value": "2" + }, + { + "Key": "CCFL Backlight", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Panel Rotation: ", + "Visibility": "", + "Data": [ + "40", + "Panel_Rotation_07" + ], + "HelpText": "This feature specifies the Panel Rotation of LFP panel used.", + "WidgetValues": [ + { + "Key": "0 degree", + "Value": "0" + }, + { + "Key": "180 degree", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Panel Position: ", + "Visibility": "", + "Data": [ + "40", + "Panel_Position_07" + ], + "HelpText": "This feature specifies the Panel Position of LFP panel used.", + "WidgetValues": [ + { + "Key": "Inside Shell", + "Value": "0" + }, + { + "Key": "Outside Shell", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Dual LFP Port Sync: ", + "Visibility": "", + "Data": [ + "42", + "EnablePortSync_Bit_07" + ], + "HelpText": "This feature will allow users to disable/enable Dual LFP Port Sync and it is applicable for DDI-A, DDI-B in case of eDP and DSI-0, DSI-1 in case of MIPI. \r\n.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " GPU Dithering for Banding artifacts: ", + "Visibility": "", + "Data": [ + "42", + "EnableDithering_Bit_07" + ], + "HelpText": "This field can be used to enable dithering from the source side for reducing banding artifacts on the visual quality features like DPST.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "Button", + "WidgetName": "Power Features", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Generic DTD Timings", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "LFP PnP ID Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Backlight Control Parameters", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Chromaticity Control", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "VESA DSC Parameters", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "LabelHeading", + "WidgetName": "Integrated eDP Settings", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "eDP Fast Link Training Configuration Parameters", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "eDP Panel Power Sequencing Parameters", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Edp Max Port Link Rate (in 200 Khz): ", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [ + "27", + "eDP_Max_Port_Link_Rate_07" + ], + "HelpText": "This field specifies EDP Max Port Link Rate supported by the port in unit of 200KHz.\nDefault value would be \"0\", in which case Display Drivers should consider EDP Max Port Link Rate to be the Platform supported Max Link Rate.\nOnly when OEM's need to limit to particular Link Rate can enter the value as mentioned in below table.\n\nNote:\n1) OEM's need to enter the values mentioned from below table only.\n2) If value entered is not matching with any of the below values then Platform supported Max Link Rate should be considere as EDP Max Port Link Rate by the display drivers.\n3) In case of EDP Fast Link Training Params(FLT), if user enters FLT Link Rate value greater than the \"eDP Max Port Link Rate\" then we need to use \n Fast Link training Link Rate = MIN (FLT Link Rate , eDP Max Port Link Rate)\n---------------------------------------------------------\n|\tLink Rate(Gbps)\t|\t Value to enter in text field\t|\n|\t \t\t|\t in terms of 200KHZ \t|\n---------------------------------------------------------\n|\t 1.62 \t\t|\t 8100 \t|\n|\t 2.16 \t\t|\t 10800 \t|\n|\t 2.43 \t\t|\t 12150 \t|\n|\t 2.7 \t\t|\t 13500 \t|\n|\t 3.24 \t\t|\t 16200 \t|\n|\t 3.78 \t\t|\t 18900 \t|\n|\t 4.32 \t\t|\t 21600 \t|\n|\t 5.4 \t\t|\t 27000 \t|\n|\t 6.48 \t\t|\t 32400 \t|\n|\t 6.75 \t\t|\t 33750 \t|\n|\t 8.1 \t\t|\t 40500 \t|\n", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Panel Color Depth: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Panel_Color_Depth_07" + ], + "HelpText": "This feature specifies the color depth of eDP panel used.", + "WidgetValues": [ + { + "Key": "18-bit Color Depth", + "Value": "0" + }, + { + "Key": "24-bit Color Depth", + "Value": "1" + }, + { + "Key": "30-bit Color Depth", + "Value": "2" + }, + { + "Key": "36-bit Color Depth", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Select VSwing/Pre-Emphasis table : ", + "Visibility": "", + "Data": [ + "27", + "eDP_VswingPreEmph_7" + ], + "HelpText": "This feature selects the VSwing Pre-Emphasis setting table to be used. For Tigerlake, based on the selection respective table will be used.\nTables for Tigerlake:\nLow Power VSwing Pre-Emphasis Setting Table:\nFor HBR2:\n\t\t\t\t\t\t Pre-Emphasis (db)\n\t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\nVoltage \t\t Level-0/200mV \t\t 200mV, 0.0db \t\t 200mV, 1.9db \t\t 200mV, 3.5db \t\t 200mV, 4.9db\nSwing \t\t Level-1/250mV \t\t 250mV, 0.0db \t\t 250mV, 1.6db \t\t 250mV, 2.9db \t\t N/A\n(mV) \t\t Level-2/300mV \t\t 300mV, 0.0db \t\t 300mV, 1.3db \t\t N/A \t\t N/A\n\t\t Level-3/350mV \t\t 350mV, 0.0db \t\t N/A \t\t N/A \t\t N/A\n\n\nFor HBR3:\n\t\t\t\t\t\t Pre-Emphasis (db)\n\t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\nVoltage \t\t Level-0/350mV \t\t 350mV, 0.0db \t\t 350mV, 3.1db \t\t 350mV, 6.0db \t\t 350mV, 8.2db\nSwing \t\t Level-1/500mV \t\t 500mV, 0.0db \t\t 500mV, 2.9db \t\t 500mV, 5.1db \t\t N/A\n(mV) \t\t Level-2/650mV \t\t 650mV, 0.6db \t\t 600mV, 3.5db \t\t N/A \t\t N/A\n\t\t Level-3/900mV \t\t 900mV, 0.0db \t\t N/A \t\t N/A \t\t N/A\n\n\nDefault VSwing Pre-Emphasis Setting Table:\nFor HBR:\n\t\t\t\t\t\t Pre-Emphasis (db)\n\t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\nVoltage \t\t Level-0/350mV \t\t 350mV, 0.0db \t\t 350mV, 3.1db \t\t 350mV, 6.0db \t\t 350mV, 8.2db\nSwing \t\t Level-1/500mV \t\t 500mV, 0.0db \t\t 500mV, 2.9db \t\t 500mV, 5.1db \t\t N/A\n(mV) \t\t Level-2/650mV \t\t 650mV, 0.6db \t\t 600mV, 3.5db \t\t N/A \t\t N/A\n\t\t Level-3/900mV \t\t 900mV, 0.0db \t\t N/A \t\t N/A \t\t N/A\n\n\nFor HBR2:\n\t\t\t\t\t\t Pre-Emphasis (db)\n\t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\nVoltage \t\t Level-0/350mV \t\t 350mV, 0.0db \t\t 350mV, 3.1db \t\t 350mV, 6.0db \t\t 350mV, 8.2db\nSwing \t\t Level-1/500mV \t\t 500mV, 0.0db \t\t 500mV, 2.9db \t\t 500mV, 5.1db \t\t N/A\n(mV) \t\t Level-2/650mV \t\t 650mV, 0.6db \t\t 600mV, 3.5db \t\t N/A \t\t N/A\n\t\t Level-3/900mV \t\t 900mV, 0.0db \t\t N/A \t\t N/A \t\t N/A", + "WidgetValues": [ + { + "Key": "Default VSwing/Pre-Emphasis Table", + "Value": "1" + }, + { + "Key": "Low Power VSwing/Pre-Emphasis Table", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " eDP Spread Spectrum Clock: ", + "Visibility": "", + "Data": [ + "40", + "Enable_SSC07" + ], + "HelpText": "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Pixel Overlap Count: ", + "Visibility": "", + "Data": [ + "42", + "PixelOverlapCount_07" + ], + "HelpText": "Select the number of Pixels to be overlapped per half of Scanline while using Edp Multi-SST(MSO) feature.", + "WidgetValues": [ + { + "Key": "Zero Pixel Overlap", + "Value": "0" + }, + { + "Key": "One Pixel Overlap", + "Value": "1" + }, + { + "Key": "Two Pixel Overlap", + "Value": "2" + }, + { + "Key": "Three Pixel Overlap", + "Value": "3" + }, + { + "Key": "Four Pixel Overlap", + "Value": "4" + }, + { + "Key": "Five Pixel Overlap", + "Value": "5" + }, + { + "Key": "Six Pixel Overlap", + "Value": "6" + }, + { + "Key": "Seven Pixel Overlap", + "Value": "7" + }, + { + "Key": "Eight Pixel Overlap", + "Value": "8" + } + ] + }, + { + "WidgetType": "Button", + "WidgetName": "PSR Feature", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Apical Feature", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + } + ], + "NestedPages": [ + { + "Type": "Block", + "Block": { + "PageNum": "5-2-7-1", + "PageName": "eDP Panel Power Sequencing Parameters", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " T3 optimization: ", + "Visibility": "", + "Data": [ + "27", + "eDP_T3_Optimization_07" + ], + "HelpText": "This feature enables or disables T3 optimization.\nWhen enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\nWhen disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "LCDVCC to HPD high delay (T3): ", + "Visibility": "", + "Data": [ + "27", + "eDP_Vcc_To_Hpd_Delay_07" + ], + "HelpText": "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\nValid Range: 0 to 200msec", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Valid video data to Backlight Enable delay (T8): ", + "Visibility": "", + "Data": [ + "27", + "eDP_DataOn_To_BkltEnable_Delay_07" + ], + "HelpText": "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\nT8 is inclusive of T7.\nValid Range of T7: 0 to 50msec", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "PWM-On To Backlight Enable delay: ", + "Visibility": "", + "Data": [ + "27", + "eDP_PwmOn_To_Bklt_Enable_Delay_07" + ], + "HelpText": "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\nDelay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\nSo it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Backlight Disable to PWM-Off delay: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Bklt_Disable_To_PwmOff_Delay_07" + ], + "HelpText": "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\nDelay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\nSo it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Backlight Disable to End of Valid video data delay (T9): ", + "Visibility": "", + "Data": [ + "27", + "eDP_BkltDisable_To_DataOff_Delay_07" + ], + "HelpText": "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "End of Valid video data to Power-Off delay (T10): ", + "Visibility": "", + "Data": [ + "27", + "eDP_DataOff_To_PowerOff_Delay_07" + ], + "HelpText": "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\nValid Range: 0 to 500 msec", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Power-off time (T12): ", + "Visibility": "", + "Data": [ + "27", + "eDP_PowerCycle_Delay_07" + ], + "HelpText": "Using this field Power-off time can be specified in 100uS.", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-7-2", + "PageName": "eDP Fast Link Training Configuration Parameters", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Is FastLinkTraining Feature Supported: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Fast_Link_Training_Supported_07" + ], + "HelpText": "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled.", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Data Rate: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Fast_Link_Training_Data_Rate_07" + ], + "HelpText": "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. It will be used if the sink indicates that no aux handshake is required during link training.\n\nIn case of EDP Fast Link Training Params(FLT), if user enters FLT Link Rate value greater than the \"eDP Max Port Link Rate\" then driver would use \n Fast Link training Link Rate = MIN (FLT Link Rate , eDP Max Port Link Rate).", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Lane Count: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Link_LaneCount_07" + ], + "HelpText": "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. It will be used if the sink indicates that no aux handshake is required during link training.", + "WidgetValues": [ + { + "Key": "x1", + "Value": "0" + }, + { + "Key": "x2", + "Value": "1" + }, + { + "Key": "x4", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Pre-Emphasis: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Link_PreEmp_07" + ], + "HelpText": "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. It will be used if the sink indicates that no aux handshake is required during link training.", + "WidgetValues": [ + { + "Key": "Level-0", + "Value": "0" + }, + { + "Key": "Level-1", + "Value": "1" + }, + { + "Key": "Level-2", + "Value": "2" + }, + { + "Key": "Level-3", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Voltage Swing: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Link_Vswing_07" + ], + "HelpText": "This feature allows for the selection of the Voltage Swing value for the embedded DP link. It will be used if the sink indicates that no aux handshake is required during link training.", + "WidgetValues": [ + { + "Key": "Swing-0", + "Value": "0" + }, + { + "Key": "Swing-1", + "Value": "1" + }, + { + "Key": "Swing-2", + "Value": "2" + }, + { + "Key": "Swing-3", + "Value": "3" + } + ] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-7-3", + "PageName": "PSR Feature", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Full Link enable: ", + "Visibility": "", + "Data": [ + "9", + "PSR_FullLink_Enable_07" + ], + "HelpText": "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state.", + "WidgetValues": [ + { + "Key": "No", + "Value": "0" + }, + { + "Key": "Yes", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Require AUX to wake up: ", + "Visibility": "", + "Data": [ + "9", + "PSR_Require_AUX2Wakeup_07" + ], + "HelpText": "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used.", + "WidgetValues": [ + { + "Key": "No", + "Value": "0" + }, + { + "Key": "Yes", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Lines to wait before link standby: ", + "Visibility": "", + "Data": [ + "9", + "PSR_Lines2Wait_B4LinkS3_07" + ], + "HelpText": "This field determines Lines to wait before link standby\n0 lines to wait (Default)\n1 lines to wait\n4 lines to wait\n8 lines to wait\nOthers Reserved", + "WidgetValues": [ + { + "Key": "0 lines to wait", + "Value": "0" + }, + { + "Key": "1 lines to wait", + "Value": "1" + }, + { + "Key": "4 lines to wait", + "Value": "2" + }, + { + "Key": "8 lines to wait", + "Value": "3" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Idle frames to wait: ", + "Visibility": "", + "Data": [ + "9", + "PSR_IdleFrames2Wait_07" + ], + "HelpText": "Idle frames to wait for PSR enable.\nAllowed values 0-15. Default value is 0.", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Clock Recovery Time: ", + "Visibility": "", + "Data": [ + "9", + "PSR_TP1_WaitTime_07" + ], + "HelpText": "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)", + "WidgetValues": [ + { + "Key": "500 usec", + "Value": "0" + }, + { + "Key": "100 usec", + "Value": "1" + }, + { + "Key": "2.5 msec", + "Value": "2" + }, + { + "Key": "0 (Skip)", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Channel Equalization Time for PSR1 panel: ", + "Visibility": "", + "Data": [ + "9", + "PSR1_TP_2_3_4_WaitTime_07" + ], + "HelpText": "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) or TP4(Training Pattern4) time during PSR1 exit(wake up)", + "WidgetValues": [ + { + "Key": "500 usec", + "Value": "0" + }, + { + "Key": "100 usec", + "Value": "1" + }, + { + "Key": "2.5 msec", + "Value": "2" + }, + { + "Key": "0 (Skip)", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Channel Equalization Time for PSR2 panel: ", + "Visibility": "", + "Data": [ + "9", + "PSR2_TP_2_3_4_WaitTime_07" + ], + "HelpText": "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) or TP4(Training Pattern4) time during PSR2 exit(wake up)", + "WidgetValues": [ + { + "Key": "500 usec", + "Value": "0" + }, + { + "Key": "100 usec", + "Value": "1" + }, + { + "Key": "2.5 msec", + "Value": "2" + }, + { + "Key": "50 usec", + "Value": "3" + } + ] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-7-4", + "PageName": "Apical Feature", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Apical Assertive Display IP: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Apical_Display_Ip_Enable_07" + ], + "HelpText": "This field enables/disables the Apical Assertive Display IP for this panel.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Panel OUI (IEEE OUI): ", + "Visibility": "", + "Data": [ + "27", + "eDP_Panel_Oui_07" + ], + "HelpText": "This field specifies the Apical IP specific Panel OUI field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " DPCD Base Address: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Dpcd_Base_Address_07" + ], + "HelpText": "This field specifies the Apical IP specific DPCD base address field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " DPCD Irdidix Control 0: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Dpcd_Irdidix_Control0_07" + ], + "HelpText": "This field specifies the Apical IP specific DPCD Irdidix control 0 field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " DPCD Option Select: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Dpcd_Option_Select_07" + ], + "HelpText": "This field specifies the Apical IP specific DPCD option select field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " DPCD Backlight: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Dpcd_Backlight_07" + ], + "HelpText": "This field specifies the Apical IP specific backlight value.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Ambient Light: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Ambient_Light_07" + ], + "HelpText": "This field specifies the Apical IP specific Ambient light value.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Backlight scale: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Backlight_Scale_07" + ], + "HelpText": "This field specifies the Apical IP specific backlight scale field.", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-7-5", + "PageName": "Power Features", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Intel Display Power Saving Technology (DPST) (Mobile only): ", + "Visibility": "", + "Data": [ + "44", + "DPST_Enable_07" + ], + "HelpText": "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled.\nIntel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power.\nNote: This technology is only active when the system is running in battery mode and the LFP is the only active display device.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Intel Display Refresh Rate Switching (DRRS) (Mobile only): ", + "Visibility": "", + "Data": [ + "44", + "DRRS_Enable_07" + ], + "HelpText": "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Edge Luminance Profile (ELP) : ", + "Visibility": "", + "Data": [ + "44", + "ELP_Enable_07" + ], + "HelpText": "This feature determines whether the ELP feature is enabled or disabled.\nEdge Luminance Profile (ELP) is a panel technology which reduce luminance on the edge of screen to save panel power.\nNote:This technology cannot co-exist with DPST and OPST ((i.e.) OPST, DPST and ELP cannot exist together.They are all mutually exclusive to each other.)", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " OLED Power Saving Technology (OPST) : ", + "Visibility": "", + "Data": [ + "44", + "OPST_Enable_07" + ], + "HelpText": "This feature determines whether the OPST feature is enabled or disabled.\nOLED Power Saving Technology (OPST) is a panel technology which saves power by intelligent, adaptive dimming of midrange pixel values more aggressively than the extremes without compromising the viewability.\nNote: This technology cannot co-exist with ELP and DPST ((i.e.) OPST, DPST and ELP cannot exist together.They are all mutually exclusive to each other.)", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Dynamic Media Refresh Rate Switching Enable/Disable ", + "Visibility": "", + "Data": [ + "44", + "DMRRS_Enable_07" + ], + "HelpText": "This feature determines whether Dynamic media refresh rate switching is to be enabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Enable Display Lace Support: ", + "Visibility": "", + "Data": [ + "44", + "LACE_Enable_07" + ], + "HelpText": "This feature, when enabled, will set Display Lace Support otherwise, the functionality will be disabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Panel Self Refresh (PSR): ", + "Visibility": "", + "Data": [ + "44", + "PSR_Enable_07" + ], + "HelpText": "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Assertive Display Technology Enable/Disable: ", + "Visibility": "", + "Data": [ + "44", + "ADT_Enable_07" + ], + "HelpText": "This feature determines whether Assertive display technology is to be enabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Intel Automatic Display Brightness (ADB) (Mobile only): ", + "Visibility": "", + "Data": [ + "44", + "ADB_Enable_07" + ], + "HelpText": "This feature determines whether Intel Automatic Display Brightness is to be enabled. Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) depending on the current ambient light environment.\nWhen enabled, the driver and VBIOS will control the backlight brightness of the LFP depending on the ambient environment if and only if the LFP is the only active display. When disabled, the driver will perform no action.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "EDP 4k/2k HOBL Feature: ", + "Visibility": "", + "Data": [ + "44", + "eDP_4k_2k_HOBL_feature_Enable_07" + ], + "HelpText": "This feature will allow users to disable/enable the edp 4k/2k HOBL(Hours Of Battery Life) feature by programming relevant registers specific for a platform.\r\n.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Default Display LACE Enabled status: ", + "Visibility": "", + "Data": [ + "44", + "LACE_Status_07" + ], + "HelpText": "This feature, when enabled, will set Default Display LACE Enabled status otherwise, the functionality will be disabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "DPST Aggressiveness Level: ", + "Visibility": "", + "Data": [ + "44", + "DPST_Aggressiveness_Profile_07" + ], + "HelpText": "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n1 (Maximum Quality with No DPST)\n2\n3\n4\n5\n6 (Maximum Battery)", + "WidgetValues": [ + { + "Key": "1 - Maximum Quality with No DPST", + "Value": "1" + }, + { + "Key": "2", + "Value": "2" + }, + { + "Key": "3", + "Value": "3" + }, + { + "Key": "4", + "Value": "4" + }, + { + "Key": "5", + "Value": "5" + }, + { + "Key": "6 - Maximum Battery", + "Value": "6" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "LACE Aggressiveness Level: ", + "Visibility": "", + "Data": [ + "44", + "LACE_Aggressiveness_Profile_07" + ], + "HelpText": "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\nMinimum 0\nModerate 1\nHigh 2", + "WidgetValues": [ + { + "Key": "Minimum", + "Value": "0" + }, + { + "Key": "Moderate", + "Value": "1" + }, + { + "Key": "High", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "ELP Aggressiveness Level: ", + "Visibility": "", + "Data": [ + "44", + "ELP_Aggressiveness_Profile_07" + ], + "HelpText": "This feature allows for the selection of ELP Aggressiveness level for this Panel Type.\nMinimum Power Savings\nMedium Power Savings \nMaximum Power Savings", + "WidgetValues": [ + { + "Key": "Minimum Power Savings", + "Value": "0" + }, + { + "Key": "Medium Power Savings", + "Value": "1" + }, + { + "Key": "Maximum Power Savings", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "OPST Aggressiveness Level: ", + "Visibility": "", + "Data": [ + "44", + "OPST_Aggressiveness_Profile_07" + ], + "HelpText": "This feature allows for the selection of OPST Aggressiveness level for this Panel Type.\nMinimum Power Savings\nMedium Power Savings \nMaximum Power Savings", + "WidgetValues": [ + { + "Key": "Minimum Power Savings", + "Value": "0" + }, + { + "Key": "Medium Power Savings", + "Value": "1" + }, + { + "Key": "Maximum Power Savings", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Default Display VRR Enabled status: ", + "Visibility": "", + "Data": [ + "44", + "VRR_Status_07" + ], + "HelpText": "VRR (Variable Refresh Rate) is a feature that can continuously and seamlessly vary Refresh Rate on the fly, on displays that support Variable Refresh rate Technologies.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-7-6", + "PageName": "Generic DTD Timings", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Pixel Clock in KHz: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_Pixel_CLK_07" + ], + "HelpText": "Pixel Clock (in KHz) Range from 0.001 to 4294967.295 MP/s.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Active: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_Active_07" + ], + "HelpText": "Horizontal Active Image Pixels Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Active: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_Active_07" + ], + "HelpText": "Vertical Active Image Lines Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Blank: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_Blank_07" + ], + "HelpText": "Horizontal Blank Pixels Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Blank: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_Blank_07" + ], + "HelpText": "Vertical Blank lines Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Front Porch: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_FrontPorch_07" + ], + "HelpText": "Horizontal Front Porch Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Front Porch: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_FrontPorch_07" + ], + "HelpText": "Vertical Front Porch Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Sync: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_Sync_07" + ], + "HelpText": "Horizontal Sync Width Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Sync: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_Sync_07" + ], + "HelpText": "Vertical Sync Width Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Image Size: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_Image_Size_07" + ], + "HelpText": "Horizontal Addressable Video Image Size in mm represented by 16bits. Image size multiplier 1.00 mm precision.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Image Size: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_Image_Size_07" + ], + "HelpText": "Vertical Addressable Video Image Size in mm represented by 16bits. Image size multiplier 1.00 mm precision.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryBin", + "WidgetName": "Common Flag: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_Common_Flag_07" + ], + "HelpText": "Common DTD Flags:\nBit 7 : Horizontal Sync Polarity\n1 : Positive\n0 : Negative\nBit 6 : Vertical Sync polarity\n1 : Positive\n0 : Negative\nBit 5 - 0: Reserved (Default value 0)", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-7-7", + "PageName": "LFP PnP ID Table", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Table", + "WidgetName": "", + "Visibility": "", + "Data": [ + "42", + "LFP_Panel_PnP_ID_07" + ], + "HelpText": "This feature allows the 10 bytes of EDID Vendor/Product ID starting at offset 08h to be used as a PnP ID.\n\nTable Definition:\n\tWord: ID Manufacturer Name\n\tWord: ID Product Code\n\tDWord: ID Serial Number\n\tByte: Week of Manufacture\n\tByte: Year of Manufacture", + "WidgetValues": [ + { + "ColumnName": "PnP ID", + "SizeinBytes": "1" + } + ] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-7-8", + "PageName": "Backlight Control Parameters", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Inverter Type: ", + "Visibility": "", + "Data": [ + "43", + "BLC_Inv_Type_07" + ], + "HelpText": "This feature allows for the selection of the Backlight Inverter type that is to be used to control the backlight brightness of the LFP.\nWhen PWM is selected, the driver and VBIOS will control the backlight brightness via the integrated PWM solution for the applicable chipsets.\nWhen None/External is selected, the system BIOS will control the backlight brightness via the external solution.", + "WidgetValues": [ + { + "Key": "None/External", + "Value": "0" + }, + { + "Key": "PWM", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Pwm Source Selection: ", + "Visibility": "", + "Data": [ + "43", + "Lfp_Pwm_Source_Selection_07" + ], + "HelpText": "If panel supports 'Intel HDR AUX Interface', it will always be chosen by default. If not, value in 'PWM Source Selection' will be used", + "WidgetValues": [ + { + "Key": "PWM From Display Engine", + "Value": "2" + }, + { + "Key": "PWM From LCD Panel", + "Value": "3" + }, + { + "Key": "Panel Driver Interface", + "Value": "4" + }, + { + "Key": "VESA eDP AUX Interface", + "Value": "5" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Pwm Controller Selection: ", + "Visibility": "", + "Data": [ + "43", + "Lfp_Pwm_Controller_Selection_07" + ], + "HelpText": "This field allows to select the PWM Controller to be used for the selected Local Flat Panel.This field allows to select the PWM Controller to be used for the selected Local Flat Panel.If Two LFPs are connected then PWM0 and PWM1 must be selected accordingly.", + "WidgetValues": [ + { + "Key": "PWM0", + "Value": "0" + }, + { + "Key": "PWM1", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Inverter Polarity: ", + "Visibility": "", + "Data": [ + "43", + "BLC_Inv_Polarity_07" + ], + "HelpText": "This feature allows the backlight inverter polarity to be specified.\nNormal means 0 value is minimum brightness.\nInverted means 0 value is maximum brightness.", + "WidgetValues": [ + { + "Key": "Normal", + "Value": "0" + }, + { + "Key": "Inverted", + "Value": "1" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Minimum Brightness: ", + "Visibility": "", + "Data": [ + "43", + "Post_Min_Brightness_07" + ], + "HelpText": "This feature allows defining the absolute minimum backlight brightness. The driver will never decrease the backlight less than this value. The value must be specified using normal polarity semantics. The value should range from 0 to 255 if the brightness precision bit is chosen to be 8, and it should range from 0 to 65535 if the precision bit is chosen to be 16.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "POST Backlight Intensity: ", + "Visibility": "", + "Data": [ + "43", + "Post_Brightness_07" + ], + "HelpText": "This feature is used to set default backlight brightness value of the panel at POST. The value should range from 0 to 255 if the bit precision is chosen to be 8 and it should range from 0 to 65535 if the brightness bit precision is chosent to be 16.", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Brightness Precision Bits: ", + "Visibility": "", + "Data": [ + "43", + "BrightnessPrecisionBits_07" + ], + "HelpText": "This field represents the range of brightness in terms of bit precision.\n 8 = Brightness range of 0 to 255.\n 16 = Brightness range of 0 to 65535", + "WidgetValues": [ + { + "Key": "8", + "Value": "8" + }, + { + "Key": "16", + "Value": "16" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "PWM Inverter Frequency (Hz): ", + "Visibility": "", + "Data": [ + "43", + "PWM_Frequency_07" + ], + "HelpText": "This feature allows for the definition of the frequency needed for PWM Inverter.\nNote: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Intel HDR DPCD Refresh Timeout (unit - 10 micro seconds): ", + "Visibility": "", + "Data": [ + "43", + "HdrDpcdRefreshTimeout_07" + ], + "HelpText": "This field allows to configure the refresh timeout of Intel HDR DPCDs for different TCON Vendors.\nNote:\n\tThe value is in units of 10 microseconds.\n\tThe range (entered as a decimal number), for the timeout is 0-65535", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-7-9", + "PageName": "Chromaticity Control", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Chromaticity Control Feature: ", + "Visibility": "", + "Data": [ + "46", + "Chromacity_Enable_07" + ], + "HelpText": "This bit enables Chromaticity feature.\nIf this bit is enabled, EDID values for chromaticity will be used, else feature is disabled.\nFeature will be supported for Panels that support EDID version 1.4 or higher.\nPlease refer to section 3.7 of EDID Specification 1.4.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Override the EDID values: ", + "Visibility": "", + "Data": [ + "46", + "Override_EDID_Data_07" + ], + "HelpText": "This option when enabled along with Chromaticity feature will override EDID values through following VBT data", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Red_Green_bits (Bits 1:0 at 19h): ", + "Visibility": "", + "Data": [ + "46", + "Red_Green_07" + ], + "HelpText": "Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Blue_White_bits (Bits 1:0 at 1Ah): ", + "Visibility": "", + "Data": [ + "46", + "Blue_White_07" + ], + "HelpText": "Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Red_x (Bits 9:2 at 1Bh): ", + "Visibility": "", + "Data": [ + "46", + "Red_x_07" + ], + "HelpText": "Bits 9:2 of red color x coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Red_y (Bits 9:2 at 1Ch): ", + "Visibility": "", + "Data": [ + "46", + "Red_y_07" + ], + "HelpText": "Bits 9:2 of red color y coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Green_x (Bits 9:2 at 1Dh): ", + "Visibility": "", + "Data": [ + "46", + "Green_x_07" + ], + "HelpText": "Bits 9:2 of Green color x coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Green_y (Bits 9:2 at 1Eh): ", + "Visibility": "", + "Data": [ + "46", + "Green_y_07" + ], + "HelpText": "Bits 9:2 of Green color y coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Blue_x (Bits 9:2 at 1Fh): ", + "Visibility": "", + "Data": [ + "46", + "Blue_x_07" + ], + "HelpText": "Bits 9:2 of Blue color x coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Blue_y (Bits 9:2 at 20h): ", + "Visibility": "", + "Data": [ + "46", + "Blue_y_07" + ], + "HelpText": "Bits 9:2 of Blue color y coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " White_x (Bits 9:2 at 21h): ", + "Visibility": "", + "Data": [ + "46", + "White_x_07" + ], + "HelpText": "Bits 9:2 of White color x coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " White_y (Bits 9:2 at 22h): ", + "Visibility": "", + "Data": [ + "46", + "White_y_07" + ], + "HelpText": "Bits 9:2 of White color y coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Override Luminance values ", + "Visibility": "", + "Data": [ + "46", + "Override_LUM_Data_07" + ], + "HelpText": "This option when enabled along with Chromaticity feature will override luminance values following VBT values", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Minimum Luminance: ", + "Visibility": "", + "Data": [ + "46", + "MinLuminance_07" + ], + "HelpText": "Minimum luminance value.\n2 byte value, encoded in IEEE 754 half-precision binary floating point format,", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Maximum full frame luminance: ", + "Visibility": "", + "Data": [ + "46", + "MaxFullLuminance_07" + ], + "HelpText": "Maximum Full frame luminance value.\n2 byte value, encoded in IEEE 754 half-precision binary floating point format,", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Maximum Luminance: ", + "Visibility": "", + "Data": [ + "46", + "MaxLuminance_07" + ], + "HelpText": "Maximum luminance value(Relatively smaller portion of screen).\n2 byte value, encoded in IEEE 754 half-precision binary floating point format.", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Override Gamma values: ", + "Visibility": "", + "Data": [ + "46", + "Override_Gamma_Data_07" + ], + "HelpText": "This option when enabled along with Chromaticity feature will override gamma values through following VBT data", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Panel gamma: ", + "Visibility": "", + "Data": [ + "46", + "Gamma_07" + ], + "HelpText": "Value shall define the gamma range, from 1.00 to 3.54, as follows:\nField Value = (Gamma (value in float) x 100) - 100\nField values range from 00h through FFh.\nFFh = No gamma information shall be provided", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-7-10", + "PageName": "VESA DSC Parameters", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "DSC Major Version: ", + "Visibility": "", + "Data": [ + "56", + "C7_Major_Dsc_Version" + ], + "HelpText": "VESA DSC Major revision field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "DSC Minor Version: ", + "Visibility": "", + "Data": [ + "56", + "C7_Minor_Dsc_Version" + ], + "HelpText": "VESA DSC Minor revision field.", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Block prediction supported: ", + "Visibility": "", + "Data": [ + "56", + "C7_Blk_Prediction_En" + ], + "HelpText": "Sink supports block prediction as per the VESA DSC Spec.", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "RC Buffer Block size as per VESA DSC Spec: ", + "Visibility": "", + "Data": [ + "56", + "C7_RC_Block_Size" + ], + "HelpText": "RC buffer block size for a single RC buffer as defined by the VESA DSC spec.", + "WidgetValues": [ + { + "Key": "1 KB", + "Value": "0" + }, + { + "Key": "4 KB", + "Value": "1" + }, + { + "Key": "16 KB", + "Value": "2" + }, + { + "Key": "64 KB", + "Value": "3" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Number of RC buffer blocks as per VESA DSC Spec: ", + "Visibility": "", + "Data": [ + "56", + "C7_Dsc_RC_Buf_Size" + ], + "HelpText": "This field defines the number of RC buffers as per VESA DSC spec.\nThe number of RC buffers used by the software shall be (Value + 1) where Value is in range 0 to 127.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryBin", + "WidgetName": "Slices per line supported by the sink device: ", + "Visibility": "", + "Data": [ + "56", + "C7_Dsc_Slices_Per_Line" + ], + "HelpText": "This field defines the slices per line supported by the sink device.\nThe field is defined in bitmap fashion and details of each bits are as defined below:\n\tBits 31-10\t\t Bit 9\tBit 8\tBit 7\tBit 6\tBit 5\tBit 4\t Bit 3\t Bit 2\t Bit 1\t Bit 0\n\tReserved\t\t 24\t 20\t 16\t 12\t 10\t 8\t 6\t 4\t 2\t 1\nBit = 0, not supported. Bit = 1, supported\nNote: Assumption is that sink shall support all lower slices per line than maximum selected field. i.e. If it supports say 8 slices per line, it will also support 4/2/1 slices per line", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Line buffer depth as per VESA DSC Spec: ", + "Visibility": "", + "Data": [ + "56", + "C7_Line_Buffer_Depth" + ], + "HelpText": "Line buffer depth in bits as per VESA DSC spec.", + "WidgetValues": [ + { + "Key": "8 bits", + "Value": "0" + }, + { + "Key": "9 bits", + "Value": "1" + }, + { + "Key": "10 bits", + "Value": "2" + }, + { + "Key": "11 bits", + "Value": "3" + }, + { + "Key": "12 bits", + "Value": "4" + }, + { + "Key": "13 bits", + "Value": "5" + }, + { + "Key": "14 bits", + "Value": "6" + }, + { + "Key": "15 bits", + "Value": "7" + }, + { + "Key": "16 bits", + "Value": "8" + } + ] + }, + { + "WidgetType": "EntryBin", + "WidgetName": "Input compression BPC supported by the sink device: ", + "Visibility": "", + "Data": [ + "56", + "C7_Dsc_Bpc" + ], + "HelpText": "This field defines the compression input bpc supported by the sink device.\nThe field is defined in bitmap fashion and details of each bits are as defined below:\n\tBits 7-4\t Bit 3\t Bit 2\t Bit 1\t Bit 0\n\tRsvd\t 12 bpc\t 10bpc\t 8bpc\t Rsvd\nBit = 0, not supported. Bit = 1, supported\nNote: Assumption is that sink shall support all lower bpc values than the maximum selected field. i.e. If it supports say 12bpc, it will also support 10 and 8bpc as well", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Maximum supported compression BPP: ", + "Visibility": "", + "Data": [ + "56", + "C7_Dsc_Max_Bpp" + ], + "HelpText": "As of today, we are supporting 6/8/10/12 BPP for compression output.\nSelect the most appropriate BPP as supported by the sink.", + "WidgetValues": [ + { + "Key": "6 Bits per pixel", + "Value": "0" + }, + { + "Key": "8 Bits per pixel", + "Value": "1" + }, + { + "Key": "10 Bits per pixel", + "Value": "2" + }, + { + "Key": "12 Bits per pixel", + "Value": "3" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Slice height supported by the sink device: ", + "Visibility": "", + "Data": [ + "56", + "C7_Dsc_Slice_Height" + ], + "HelpText": "Slice height supported by the sink device for DSC slice.\nNote: Slice height must divide the picture height uniformly.", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + } + ] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-8", + "PageName": "Panel #08", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "LabelHeading", + "WidgetName": "Common LFP Features", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryAsci", + "WidgetName": " LFP Panel Name: ", + "Visibility": "", + "Data": [ + "42", + "Panel_Name_08" + ], + "HelpText": "This feature defines the LFP panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Target X-Res: ", + "Visibility": "", + "Data": [ + "42", + "Panel_Width_08" + ], + "HelpText": "This value specifies the Target X-Resolution for this panel.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Target Y-Res: ", + "Visibility": "", + "Data": [ + "42", + "Panel_Height_08" + ], + "HelpText": "This value specifies the Target Y-Resolution for this panel.", + "WidgetValues": [] + }, + { + "WidgetType": "LabelHeading", + "WidgetName": " DPS Panel Type Features", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Seamless DRRS Minimum Refresh Rate (Hz): ", + "Visibility": "", + "Data": [ + "42", + "Seamless_DRRS_Min_RR_08" + ], + "HelpText": "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\nNote: Graphics driver will use this field only when EDID support is disabled in VBT configuration.", + "WidgetValues": [] + }, + { + "WidgetType": "LabelHeading", + "WidgetName": " BackLight Technology Type Features", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " BackLight Technology: ", + "Visibility": "", + "Data": [ + "40", + "Blt_Control_08" + ], + "HelpText": "This feature allows OEM to select the Backlight Technology.", + "WidgetValues": [ + { + "Key": "LED Backlight", + "Value": "2" + }, + { + "Key": "CCFL Backlight", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Panel Rotation: ", + "Visibility": "", + "Data": [ + "40", + "Panel_Rotation_08" + ], + "HelpText": "This feature specifies the Panel Rotation of LFP panel used.", + "WidgetValues": [ + { + "Key": "0 degree", + "Value": "0" + }, + { + "Key": "180 degree", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Panel Position: ", + "Visibility": "", + "Data": [ + "40", + "Panel_Position_08" + ], + "HelpText": "This feature specifies the Panel Position of LFP panel used.", + "WidgetValues": [ + { + "Key": "Inside Shell", + "Value": "0" + }, + { + "Key": "Outside Shell", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Dual LFP Port Sync: ", + "Visibility": "", + "Data": [ + "42", + "EnablePortSync_Bit_08" + ], + "HelpText": "This feature will allow users to disable/enable Dual LFP Port Sync and it is applicable for DDI-A, DDI-B in case of eDP and DSI-0, DSI-1 in case of MIPI. \r\n.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " GPU Dithering for Banding artifacts: ", + "Visibility": "", + "Data": [ + "42", + "EnableDithering_Bit_08" + ], + "HelpText": "This field can be used to enable dithering from the source side for reducing banding artifacts on the visual quality features like DPST.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "Button", + "WidgetName": "Power Features", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Generic DTD Timings", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "LFP PnP ID Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Backlight Control Parameters", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Chromaticity Control", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "VESA DSC Parameters", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "LabelHeading", + "WidgetName": "Integrated eDP Settings", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "eDP Fast Link Training Configuration Parameters", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "eDP Panel Power Sequencing Parameters", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Edp Max Port Link Rate (in 200 Khz): ", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [ + "27", + "eDP_Max_Port_Link_Rate_08" + ], + "HelpText": "This field specifies EDP Max Port Link Rate supported by the port in unit of 200KHz.\nDefault value would be \"0\", in which case Display Drivers should consider EDP Max Port Link Rate to be the Platform supported Max Link Rate.\nOnly when OEM's need to limit to particular Link Rate can enter the value as mentioned in below table.\n\nNote:\n1) OEM's need to enter the values mentioned from below table only.\n2) If value entered is not matching with any of the below values then Platform supported Max Link Rate should be considere as EDP Max Port Link Rate by the display drivers.\n3) In case of EDP Fast Link Training Params(FLT), if user enters FLT Link Rate value greater than the \"eDP Max Port Link Rate\" then we need to use \n Fast Link training Link Rate = MIN (FLT Link Rate , eDP Max Port Link Rate)\n---------------------------------------------------------\n|\tLink Rate(Gbps)\t|\t Value to enter in text field\t|\n|\t \t\t|\t in terms of 200KHZ \t|\n---------------------------------------------------------\n|\t 1.62 \t\t|\t 8100 \t|\n|\t 2.16 \t\t|\t 10800 \t|\n|\t 2.43 \t\t|\t 12150 \t|\n|\t 2.7 \t\t|\t 13500 \t|\n|\t 3.24 \t\t|\t 16200 \t|\n|\t 3.78 \t\t|\t 18900 \t|\n|\t 4.32 \t\t|\t 21600 \t|\n|\t 5.4 \t\t|\t 27000 \t|\n|\t 6.48 \t\t|\t 32400 \t|\n|\t 6.75 \t\t|\t 33750 \t|\n|\t 8.1 \t\t|\t 40500 \t|\n", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Panel Color Depth: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Panel_Color_Depth_08" + ], + "HelpText": "This feature specifies the color depth of eDP panel used.", + "WidgetValues": [ + { + "Key": "18-bit Color Depth", + "Value": "0" + }, + { + "Key": "24-bit Color Depth", + "Value": "1" + }, + { + "Key": "30-bit Color Depth", + "Value": "2" + }, + { + "Key": "36-bit Color Depth", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Select VSwing/Pre-Emphasis table : ", + "Visibility": "", + "Data": [ + "27", + "eDP_VswingPreEmph_8" + ], + "HelpText": "This feature selects the VSwing Pre-Emphasis setting table to be used. For Tigerlake, based on the selection respective table will be used.\nTables for Tigerlake:\nLow Power VSwing Pre-Emphasis Setting Table:\nFor HBR2:\n\t\t\t\t\t\t Pre-Emphasis (db)\n\t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\nVoltage \t\t Level-0/200mV \t\t 200mV, 0.0db \t\t 200mV, 1.9db \t\t 200mV, 3.5db \t\t 200mV, 4.9db\nSwing \t\t Level-1/250mV \t\t 250mV, 0.0db \t\t 250mV, 1.6db \t\t 250mV, 2.9db \t\t N/A\n(mV) \t\t Level-2/300mV \t\t 300mV, 0.0db \t\t 300mV, 1.3db \t\t N/A \t\t N/A\n\t\t Level-3/350mV \t\t 350mV, 0.0db \t\t N/A \t\t N/A \t\t N/A\n\n\nFor HBR3:\n\t\t\t\t\t\t Pre-Emphasis (db)\n\t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\nVoltage \t\t Level-0/350mV \t\t 350mV, 0.0db \t\t 350mV, 3.1db \t\t 350mV, 6.0db \t\t 350mV, 8.2db\nSwing \t\t Level-1/500mV \t\t 500mV, 0.0db \t\t 500mV, 2.9db \t\t 500mV, 5.1db \t\t N/A\n(mV) \t\t Level-2/650mV \t\t 650mV, 0.6db \t\t 600mV, 3.5db \t\t N/A \t\t N/A\n\t\t Level-3/900mV \t\t 900mV, 0.0db \t\t N/A \t\t N/A \t\t N/A\n\n\nDefault VSwing Pre-Emphasis Setting Table:\nFor HBR:\n\t\t\t\t\t\t Pre-Emphasis (db)\n\t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\nVoltage \t\t Level-0/350mV \t\t 350mV, 0.0db \t\t 350mV, 3.1db \t\t 350mV, 6.0db \t\t 350mV, 8.2db\nSwing \t\t Level-1/500mV \t\t 500mV, 0.0db \t\t 500mV, 2.9db \t\t 500mV, 5.1db \t\t N/A\n(mV) \t\t Level-2/650mV \t\t 650mV, 0.6db \t\t 600mV, 3.5db \t\t N/A \t\t N/A\n\t\t Level-3/900mV \t\t 900mV, 0.0db \t\t N/A \t\t N/A \t\t N/A\n\n\nFor HBR2:\n\t\t\t\t\t\t Pre-Emphasis (db)\n\t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\nVoltage \t\t Level-0/350mV \t\t 350mV, 0.0db \t\t 350mV, 3.1db \t\t 350mV, 6.0db \t\t 350mV, 8.2db\nSwing \t\t Level-1/500mV \t\t 500mV, 0.0db \t\t 500mV, 2.9db \t\t 500mV, 5.1db \t\t N/A\n(mV) \t\t Level-2/650mV \t\t 650mV, 0.6db \t\t 600mV, 3.5db \t\t N/A \t\t N/A\n\t\t Level-3/900mV \t\t 900mV, 0.0db \t\t N/A \t\t N/A \t\t N/A", + "WidgetValues": [ + { + "Key": "Default VSwing/Pre-Emphasis Table", + "Value": "1" + }, + { + "Key": "Low Power VSwing/Pre-Emphasis Table", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " eDP Spread Spectrum Clock: ", + "Visibility": "", + "Data": [ + "40", + "Enable_SSC08" + ], + "HelpText": "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Pixel Overlap Count: ", + "Visibility": "", + "Data": [ + "42", + "PixelOverlapCount_08" + ], + "HelpText": "Select the number of Pixels to be overlapped per half of Scanline while using Edp Multi-SST(MSO) feature.", + "WidgetValues": [ + { + "Key": "Zero Pixel Overlap", + "Value": "0" + }, + { + "Key": "One Pixel Overlap", + "Value": "1" + }, + { + "Key": "Two Pixel Overlap", + "Value": "2" + }, + { + "Key": "Three Pixel Overlap", + "Value": "3" + }, + { + "Key": "Four Pixel Overlap", + "Value": "4" + }, + { + "Key": "Five Pixel Overlap", + "Value": "5" + }, + { + "Key": "Six Pixel Overlap", + "Value": "6" + }, + { + "Key": "Seven Pixel Overlap", + "Value": "7" + }, + { + "Key": "Eight Pixel Overlap", + "Value": "8" + } + ] + }, + { + "WidgetType": "Button", + "WidgetName": "PSR Feature", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Apical Feature", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + } + ], + "NestedPages": [ + { + "Type": "Block", + "Block": { + "PageNum": "5-2-8-1", + "PageName": "eDP Panel Power Sequencing Parameters", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " T3 optimization: ", + "Visibility": "", + "Data": [ + "27", + "eDP_T3_Optimization_08" + ], + "HelpText": "This feature enables or disables T3 optimization.\nWhen enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\nWhen disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "LCDVCC to HPD high delay (T3): ", + "Visibility": "", + "Data": [ + "27", + "eDP_Vcc_To_Hpd_Delay_08" + ], + "HelpText": "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\nValid Range: 0 to 200msec", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Valid video data to Backlight Enable delay (T8): ", + "Visibility": "", + "Data": [ + "27", + "eDP_DataOn_To_BkltEnable_Delay_08" + ], + "HelpText": "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\nT8 is inclusive of T7.\nValid Range of T7: 0 to 50msec", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "PWM-On To Backlight Enable delay: ", + "Visibility": "", + "Data": [ + "27", + "eDP_PwmOn_To_Bklt_Enable_Delay_08" + ], + "HelpText": "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\nDelay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\nSo it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Backlight Disable to PWM-Off delay: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Bklt_Disable_To_PwmOff_Delay_08" + ], + "HelpText": "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\nDelay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\nSo it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Backlight Disable to End of Valid video data delay (T9): ", + "Visibility": "", + "Data": [ + "27", + "eDP_BkltDisable_To_DataOff_Delay_08" + ], + "HelpText": "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "End of Valid video data to Power-Off delay (T10): ", + "Visibility": "", + "Data": [ + "27", + "eDP_DataOff_To_PowerOff_Delay_08" + ], + "HelpText": "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\nValid Range: 0 to 500 msec", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Power-off time (T12): ", + "Visibility": "", + "Data": [ + "27", + "eDP_PowerCycle_Delay_08" + ], + "HelpText": "Using this field Power-off time can be specified in 100uS.", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-8-2", + "PageName": "eDP Fast Link Training Configuration Parameters", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Is FastLinkTraining Feature Supported: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Fast_Link_Training_Supported_08" + ], + "HelpText": "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled.", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Data Rate: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Fast_Link_Training_Data_Rate_08" + ], + "HelpText": "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. It will be used if the sink indicates that no aux handshake is required during link training.\n\nIn case of EDP Fast Link Training Params(FLT), if user enters FLT Link Rate value greater than the \"eDP Max Port Link Rate\" then driver would use \n Fast Link training Link Rate = MIN (FLT Link Rate , eDP Max Port Link Rate).", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Lane Count: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Link_LaneCount_08" + ], + "HelpText": "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. It will be used if the sink indicates that no aux handshake is required during link training.", + "WidgetValues": [ + { + "Key": "x1", + "Value": "0" + }, + { + "Key": "x2", + "Value": "1" + }, + { + "Key": "x4", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Pre-Emphasis: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Link_PreEmp_08" + ], + "HelpText": "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. It will be used if the sink indicates that no aux handshake is required during link training.", + "WidgetValues": [ + { + "Key": "Level-0", + "Value": "0" + }, + { + "Key": "Level-1", + "Value": "1" + }, + { + "Key": "Level-2", + "Value": "2" + }, + { + "Key": "Level-3", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Voltage Swing: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Link_Vswing_08" + ], + "HelpText": "This feature allows for the selection of the Voltage Swing value for the embedded DP link. It will be used if the sink indicates that no aux handshake is required during link training.", + "WidgetValues": [ + { + "Key": "Swing-0", + "Value": "0" + }, + { + "Key": "Swing-1", + "Value": "1" + }, + { + "Key": "Swing-2", + "Value": "2" + }, + { + "Key": "Swing-3", + "Value": "3" + } + ] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-8-3", + "PageName": "PSR Feature", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Full Link enable: ", + "Visibility": "", + "Data": [ + "9", + "PSR_FullLink_Enable_08" + ], + "HelpText": "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state.", + "WidgetValues": [ + { + "Key": "No", + "Value": "0" + }, + { + "Key": "Yes", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Require AUX to wake up: ", + "Visibility": "", + "Data": [ + "9", + "PSR_Require_AUX2Wakeup_08" + ], + "HelpText": "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used.", + "WidgetValues": [ + { + "Key": "No", + "Value": "0" + }, + { + "Key": "Yes", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Lines to wait before link standby: ", + "Visibility": "", + "Data": [ + "9", + "PSR_Lines2Wait_B4LinkS3_08" + ], + "HelpText": "This field determines Lines to wait before link standby\n0 lines to wait (Default)\n1 lines to wait\n4 lines to wait\n8 lines to wait\nOthers Reserved", + "WidgetValues": [ + { + "Key": "0 lines to wait", + "Value": "0" + }, + { + "Key": "1 lines to wait", + "Value": "1" + }, + { + "Key": "4 lines to wait", + "Value": "2" + }, + { + "Key": "8 lines to wait", + "Value": "3" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Idle frames to wait: ", + "Visibility": "", + "Data": [ + "9", + "PSR_IdleFrames2Wait_08" + ], + "HelpText": "Idle frames to wait for PSR enable.\nAllowed values 0-15. Default value is 0.", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Clock Recovery Time: ", + "Visibility": "", + "Data": [ + "9", + "PSR_TP1_WaitTime_08" + ], + "HelpText": "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)", + "WidgetValues": [ + { + "Key": "500 usec", + "Value": "0" + }, + { + "Key": "100 usec", + "Value": "1" + }, + { + "Key": "2.5 msec", + "Value": "2" + }, + { + "Key": "0 (Skip)", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Channel Equalization Time for PSR1 panel: ", + "Visibility": "", + "Data": [ + "9", + "PSR1_TP_2_3_4_WaitTime_08" + ], + "HelpText": "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) or TP4(Training Pattern4) time during PSR1 exit(wake up)", + "WidgetValues": [ + { + "Key": "500 usec", + "Value": "0" + }, + { + "Key": "100 usec", + "Value": "1" + }, + { + "Key": "2.5 msec", + "Value": "2" + }, + { + "Key": "0 (Skip)", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Channel Equalization Time for PSR2 panel: ", + "Visibility": "", + "Data": [ + "9", + "PSR2_TP_2_3_4_WaitTime_08" + ], + "HelpText": "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) or TP4(Training Pattern4) time during PSR2 exit(wake up)", + "WidgetValues": [ + { + "Key": "500 usec", + "Value": "0" + }, + { + "Key": "100 usec", + "Value": "1" + }, + { + "Key": "2.5 msec", + "Value": "2" + }, + { + "Key": "50 usec", + "Value": "3" + } + ] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-8-4", + "PageName": "Apical Feature", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Apical Assertive Display IP: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Apical_Display_Ip_Enable_08" + ], + "HelpText": "This field enables/disables the Apical Assertive Display IP for this panel.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Panel OUI (IEEE OUI): ", + "Visibility": "", + "Data": [ + "27", + "eDP_Panel_Oui_08" + ], + "HelpText": "This field specifies the Apical IP specific Panel OUI field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " DPCD Base Address: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Dpcd_Base_Address_08" + ], + "HelpText": "This field specifies the Apical IP specific DPCD base address field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " DPCD Irdidix Control 0: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Dpcd_Irdidix_Control0_08" + ], + "HelpText": "This field specifies the Apical IP specific DPCD Irdidix control 0 field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " DPCD Option Select: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Dpcd_Option_Select_08" + ], + "HelpText": "This field specifies the Apical IP specific DPCD option select field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " DPCD Backlight: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Dpcd_Backlight_08" + ], + "HelpText": "This field specifies the Apical IP specific backlight value.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Ambient Light: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Ambient_Light_08" + ], + "HelpText": "This field specifies the Apical IP specific Ambient light value.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Backlight scale: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Backlight_Scale_08" + ], + "HelpText": "This field specifies the Apical IP specific backlight scale field.", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-8-5", + "PageName": "Power Features", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Inte Display Power Saving Technology (DPST) (Mobile only): ", + "Visibility": "", + "Data": [ + "44", + "DPST_Enable_08" + ], + "HelpText": "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled.\nIntel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power.\nNote: This technology is only active when the system is running in battery mode and the LFP is the only active display device.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Intel Display Refresh Rate Switching (DRRS) (Mobile only): ", + "Visibility": "", + "Data": [ + "44", + "DRRS_Enable_08" + ], + "HelpText": "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Edge Luminance Profile (ELP) : ", + "Visibility": "", + "Data": [ + "44", + "ELP_Enable_08" + ], + "HelpText": "This feature determines whether the ELP feature is enabled or disabled.\nEdge Luminance Profile (ELP) is a panel technology which reduce luminance on the edge of screen to save panel power.\nNote:This technology cannot co-exist with DPST and OPST ((i.e.) OPST, DPST and ELP cannot exist together.They are all mutually exclusive to each other.)", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " OLED Power Saving Technology (OPST) : ", + "Visibility": "", + "Data": [ + "44", + "OPST_Enable_08" + ], + "HelpText": "This feature determines whether the OPST feature is enabled or disabled.\nOLED Power Saving Technology (OPST) is a panel technology which saves power by intelligent, adaptive dimming of midrange pixel values more aggressively than the extremes without compromising the viewability.\nNote: This technology cannot co-exist with ELP and DPST ((i.e.) OPST, DPST and ELP cannot exist together.They are all mutually exclusive to each other.)", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Dynamic Media Refresh Rate Switching Enable/Disable ", + "Visibility": "", + "Data": [ + "44", + "DMRRS_Enable_08" + ], + "HelpText": "This feature determines whether Dynamic media refresh rate switching is to be enabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Enable Display Lace Support: ", + "Visibility": "", + "Data": [ + "44", + "LACE_Enable_08" + ], + "HelpText": "This feature, when enabled, will set Display Lace Support otherwise, the functionality will be disabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Panel Self Refresh (PSR): ", + "Visibility": "", + "Data": [ + "44", + "PSR_Enable_08" + ], + "HelpText": "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Assertive Display Technology Enable/Disable: ", + "Visibility": "", + "Data": [ + "44", + "ADT_Enable_08" + ], + "HelpText": "This feature determines whether Assertive display technology is to be enabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Intel Automatic Display Brightness (ADB) (Mobile only): ", + "Visibility": "", + "Data": [ + "44", + "ADB_Enable_08" + ], + "HelpText": "This feature determines whether Intel Automatic Display Brightness is to be enabled. Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) depending on the current ambient light environment.\nWhen enabled, the driver and VBIOS will control the backlight brightness of the LFP depending on the ambient environment if and only if the LFP is the only active display. When disabled, the driver will perform no action.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "EDP 4k/2k HOBL Feature: ", + "Visibility": "", + "Data": [ + "44", + "eDP_4k_2k_HOBL_feature_Enable_08" + ], + "HelpText": "This feature will allow users to disable/enable the edp 4k/2k HOBL(Hours Of Battery Life) feature by programming relevant registers specific for a platform.\r\n.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Default Display LACE Enabled status: ", + "Visibility": "", + "Data": [ + "44", + "LACE_Status_08" + ], + "HelpText": "This feature, when enabled, will set Default Display LACE Enabled status otherwise, the functionality will be disabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "DPST Aggressiveness Level: ", + "Visibility": "", + "Data": [ + "44", + "DPST_Aggressiveness_Profile_08" + ], + "HelpText": "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n1 (Maximum Quality with No DPST)\n2\n3\n4\n5\n6 (Maximum Battery)", + "WidgetValues": [ + { + "Key": "1 - Maximum Quality with No DPST", + "Value": "1" + }, + { + "Key": "2", + "Value": "2" + }, + { + "Key": "3", + "Value": "3" + }, + { + "Key": "4", + "Value": "4" + }, + { + "Key": "5", + "Value": "5" + }, + { + "Key": "6 - Maximum Battery", + "Value": "6" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "LACE Aggressiveness Level: ", + "Visibility": "", + "Data": [ + "44", + "LACE_Aggressiveness_Profile_08" + ], + "HelpText": "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\nMinimum 0\nModerate 1\nHigh 2", + "WidgetValues": [ + { + "Key": "Minimum", + "Value": "0" + }, + { + "Key": "Moderate", + "Value": "1" + }, + { + "Key": "High", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "ELP Aggressiveness Level: ", + "Visibility": "", + "Data": [ + "44", + "ELP_Aggressiveness_Profile_08" + ], + "HelpText": "This feature allows for the selection of ELP Aggressiveness level for this Panel Type.\nMinimum Power Savings\nMedium Power Savings \nMaximum Power Savings", + "WidgetValues": [ + { + "Key": "Minimum Power Savings", + "Value": "0" + }, + { + "Key": "Medium Power Savings", + "Value": "1" + }, + { + "Key": "Maximum Power Savings", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "OPST Aggressiveness Level: ", + "Visibility": "", + "Data": [ + "44", + "OPST_Aggressiveness_Profile_08" + ], + "HelpText": "This feature allows for the selection of OPST Aggressiveness level for this Panel Type.\nMinimum Power Savings\nMedium Power Savings \nMaximum Power Savings", + "WidgetValues": [ + { + "Key": "Minimum Power Savings", + "Value": "0" + }, + { + "Key": "Medium Power Savings", + "Value": "1" + }, + { + "Key": "Maximum Power Savings", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Default Display VRR Enabled status: ", + "Visibility": "", + "Data": [ + "44", + "VRR_Status_08" + ], + "HelpText": "VRR (Variable Refresh Rate) is a feature that can continuously and seamlessly vary Refresh Rate on the fly, on displays that support Variable Refresh rate Technologies.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-8-6", + "PageName": "Generic DTD Timings", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Pixel Clock in KHz: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_Pixel_CLK_08" + ], + "HelpText": "Pixel Clock (in KHz) Range from 0.001 to 4294967.295 MP/s.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Active: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_Active_08" + ], + "HelpText": "Horizontal Active Image Pixels Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Active: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_Active_08" + ], + "HelpText": "Vertical Active Image Lines Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Blank: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_Blank_08" + ], + "HelpText": "Horizontal Blank Pixels Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Blank: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_Blank_08" + ], + "HelpText": "Vertical Blank lines Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Front Porch: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_FrontPorch_08" + ], + "HelpText": "Horizontal Front Porch Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Front Porch: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_FrontPorch_08" + ], + "HelpText": "Vertical Front Porch Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Sync: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_Sync_08" + ], + "HelpText": "Horizontal Sync Width Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Sync: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_Sync_08" + ], + "HelpText": "Vertical Sync Width Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Image Size: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_Image_Size_08" + ], + "HelpText": "Horizontal Addressable Video Image Size in mm represented by 16bits. Image size multiplier 1.00 mm precision.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Image Size: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_Image_Size_08" + ], + "HelpText": "Vertical Addressable Video Image Size in mm represented by 16bits. Image size multiplier 1.00 mm precision.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryBin", + "WidgetName": "Common Flag: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_Common_Flag_08" + ], + "HelpText": "Common DTD Flags:\nBit 7 : Horizontal Sync Polarity\n1 : Positive\n0 : Negative\nBit 6 : Vertical Sync polarity\n1 : Positive\n0 : Negative\nBit 5 - 0: Reserved (Default value 0)", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-8-7", + "PageName": "LFP PnP ID Table", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Table", + "WidgetName": "", + "Visibility": "", + "Data": [ + "42", + "LFP_Panel_PnP_ID_08" + ], + "HelpText": "This feature allows the 10 bytes of EDID Vendor/Product ID starting at offset 08h to be used as a PnP ID.\n\nTable Definition:\n\tWord: ID Manufacturer Name\n\tWord: ID Product Code\n\tDWord: ID Serial Number\n\tByte: Week of Manufacture\n\tByte: Year of Manufacture", + "WidgetValues": [ + { + "ColumnName": "PnP ID", + "SizeinBytes": "1" + } + ] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-8-8", + "PageName": "Backlight Control Parameters", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Inverter Type: ", + "Visibility": "", + "Data": [ + "43", + "BLC_Inv_Type_08" + ], + "HelpText": "This feature allows for the selection of the Backlight Inverter type that is to be used to control the backlight brightness of the LFP.\nWhen PWM is selected, the driver and VBIOS will control the backlight brightness via the integrated PWM solution for the applicable chipsets.\nWhen None/External is selected, the system BIOS will control the backlight brightness via the external solution.", + "WidgetValues": [ + { + "Key": "None/External", + "Value": "0" + }, + { + "Key": "PWM", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Pwm Source Selection: ", + "Visibility": "", + "Data": [ + "43", + "Lfp_Pwm_Source_Selection_08" + ], + "HelpText": "If panel supports 'Intel HDR AUX Interface', it will always be chosen by default. If not, value in 'PWM Source Selection' will be used", + "WidgetValues": [ + { + "Key": "PWM From Display Engine", + "Value": "2" + }, + { + "Key": "PWM From LCD Panel", + "Value": "3" + }, + { + "Key": "Panel Driver Interface", + "Value": "4" + }, + { + "Key": "VESA eDP AUX Interface", + "Value": "5" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Pwm Controller Selection: ", + "Visibility": "", + "Data": [ + "43", + "Lfp_Pwm_Controller_Selection_08" + ], + "HelpText": "This field allows to select the PWM Controller to be used for the selected Local Flat Panel.This field allows to select the PWM Controller to be used for the selected Local Flat Panel.If Two LFPs are connected then PWM0 and PWM1 must be selected accordingly.", + "WidgetValues": [ + { + "Key": "PWM0", + "Value": "0" + }, + { + "Key": "PWM1", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Inverter Polarity: ", + "Visibility": "", + "Data": [ + "43", + "BLC_Inv_Polarity_08" + ], + "HelpText": "This feature allows the backlight inverter polarity to be specified.\nNormal means 0 value is minimum brightness.\nInverted means 0 value is maximum brightness.", + "WidgetValues": [ + { + "Key": "Normal", + "Value": "0" + }, + { + "Key": "Inverted", + "Value": "1" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Minimum Brightness: ", + "Visibility": "", + "Data": [ + "43", + "Post_Min_Brightness_08" + ], + "HelpText": "This feature allows defining the absolute minimum backlight brightness. The driver will never decrease the backlight less than this value. The value must be specified using normal polarity semantics. The value should range from 0 to 255 if the brightness precision bit is chosen to be 8, and it should range from 0 to 65535 if the precision bit is chosen to be 16.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "POST Backlight Intensity: ", + "Visibility": "", + "Data": [ + "43", + "Post_Brightness_08" + ], + "HelpText": "This feature is used to set default backlight brightness value of the panel at POST. The value should range from 0 to 255 if the bit precision is chosen to be 8 and it should range from 0 to 65535 if the brightness bit precision is chosent to be 16.", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Brightness Precision Bits: ", + "Visibility": "", + "Data": [ + "43", + "BrightnessPrecisionBits_08" + ], + "HelpText": "This field represents the range of brightness in terms of bit precision.\n 8 = Brightness range of 0 to 255.\n 16 = Brightness range of 0 to 65535", + "WidgetValues": [ + { + "Key": "8", + "Value": "8" + }, + { + "Key": "16", + "Value": "16" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "PWM Inverter Frequency (Hz): ", + "Visibility": "", + "Data": [ + "43", + "PWM_Frequency_08" + ], + "HelpText": "This feature allows for the definition of the frequency needed for PWM Inverter.\nNote: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Intel HDR DPCD Refresh Timeout (unit - 10 micro seconds): ", + "Visibility": "", + "Data": [ + "43", + "HdrDpcdRefreshTimeout_08" + ], + "HelpText": "This field allows to configure the refresh timeout of Intel HDR DPCDs for different TCON Vendors.\nNote:\n\tThe value is in units of 10 microseconds.\n\tThe range (entered as a decimal number), for the timeout is 0-65535", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-8-9", + "PageName": "Chromaticity Control", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Chromaticity Control Feature: ", + "Visibility": "", + "Data": [ + "46", + "Chromacity_Enable_08" + ], + "HelpText": "This bit enables Chromaticity feature.\nIf this bit is enabled, EDID values for chromaticity will be used, else feature is disabled.\nFeature will be supported for Panels that support EDID version 1.4 or higher.\nPlease refer to section 3.7 of EDID Specification 1.4.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Override the EDID values: ", + "Visibility": "", + "Data": [ + "46", + "Override_EDID_Data_08" + ], + "HelpText": "This option when enabled along with Chromaticity feature will override EDID values through following VBT data", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Red_Green_bits (Bits 1:0 at 19h): ", + "Visibility": "", + "Data": [ + "46", + "Red_Green_08" + ], + "HelpText": "Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Blue_White_bits (Bits 1:0 at 1Ah): ", + "Visibility": "", + "Data": [ + "46", + "Blue_White_08" + ], + "HelpText": "Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Red_x (Bits 9:2 at 1Bh): ", + "Visibility": "", + "Data": [ + "46", + "Red_x_08" + ], + "HelpText": "Bits 9:2 of red color x coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Red_y (Bits 9:2 at 1Ch): ", + "Visibility": "", + "Data": [ + "46", + "Red_y_08" + ], + "HelpText": "Bits 9:2 of red color y coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Green_x (Bits 9:2 at 1Dh): ", + "Visibility": "", + "Data": [ + "46", + "Green_x_08" + ], + "HelpText": "Bits 9:2 of Green color x coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Green_y (Bits 9:2 at 1Eh): ", + "Visibility": "", + "Data": [ + "46", + "Green_y_08" + ], + "HelpText": "Bits 9:2 of Green color y coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Blue_x (Bits 9:2 at 1Fh): ", + "Visibility": "", + "Data": [ + "46", + "Blue_x_08" + ], + "HelpText": "Bits 9:2 of Blue color x coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Blue_y (Bits 9:2 at 20h): ", + "Visibility": "", + "Data": [ + "46", + "Blue_y_08" + ], + "HelpText": "Bits 9:2 of Blue color y coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " White_x (Bits 9:2 at 21h): ", + "Visibility": "", + "Data": [ + "46", + "White_x_08" + ], + "HelpText": "Bits 9:2 of White color x coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " White_y (Bits 9:2 at 22h): ", + "Visibility": "", + "Data": [ + "46", + "White_y_08" + ], + "HelpText": "Bits 9:2 of White color y coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Override Luminance values ", + "Visibility": "", + "Data": [ + "46", + "Override_LUM_Data_08" + ], + "HelpText": "This option when enabled along with Chromaticity feature will override luminance values following VBT values", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Minimum Luminance: ", + "Visibility": "", + "Data": [ + "46", + "MinLuminance_08" + ], + "HelpText": "Minimum luminance value.\n2 byte value, encoded in IEEE 754 half-precision binary floating point format,", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Maximum full frame luminance: ", + "Visibility": "", + "Data": [ + "46", + "MaxFullLuminance_08" + ], + "HelpText": "Maximum Full frame luminance value.\n2 byte value, encoded in IEEE 754 half-precision binary floating point format,", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Maximum Luminance: ", + "Visibility": "", + "Data": [ + "46", + "MaxLuminance_08" + ], + "HelpText": "Maximum luminance value(Relatively smaller portion of screen).\n2 byte value, encoded in IEEE 754 half-precision binary floating point format.", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Override Gamma values: ", + "Visibility": "", + "Data": [ + "46", + "Override_Gamma_Data_08" + ], + "HelpText": "This option when enabled along with Chromaticity feature will override gamma values through following VBT data", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Panel gamma: ", + "Visibility": "", + "Data": [ + "46", + "Gamma_08" + ], + "HelpText": "Value shall define the gamma range, from 1.00 to 3.54, as follows:\nField Value = (Gamma (value in float) x 100) - 100\nField values range from 00h through FFh.\nFFh = No gamma information shall be provided", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-8-10", + "PageName": "VESA DSC Parameters", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "DSC Major Version: ", + "Visibility": "", + "Data": [ + "56", + "C8_Major_Dsc_Version" + ], + "HelpText": "VESA DSC Major revision field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "DSC Minor Version: ", + "Visibility": "", + "Data": [ + "56", + "C8_Minor_Dsc_Version" + ], + "HelpText": "VESA DSC Minor revision field.", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Block prediction supported: ", + "Visibility": "", + "Data": [ + "56", + "C8_Blk_Prediction_En" + ], + "HelpText": "Sink supports block prediction as per the VESA DSC Spec.", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "RC Buffer Block size as per VESA DSC Spec: ", + "Visibility": "", + "Data": [ + "56", + "C8_RC_Block_Size" + ], + "HelpText": "RC buffer block size for a single RC buffer as defined by the VESA DSC spec.", + "WidgetValues": [ + { + "Key": "1 KB", + "Value": "0" + }, + { + "Key": "4 KB", + "Value": "1" + }, + { + "Key": "16 KB", + "Value": "2" + }, + { + "Key": "64 KB", + "Value": "3" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Number of RC buffer blocks as per VESA DSC Spec: ", + "Visibility": "", + "Data": [ + "56", + "C8_Dsc_RC_Buf_Size" + ], + "HelpText": "This field defines the number of RC buffers as per VESA DSC spec.\nThe number of RC buffers used by the software shall be (Value + 1) where Value is in range 0 to 127.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryBin", + "WidgetName": "Slices per line supported by the sink device: ", + "Visibility": "", + "Data": [ + "56", + "C8_Dsc_Slices_Per_Line" + ], + "HelpText": "This field defines the slices per line supported by the sink device.\nThe field is defined in bitmap fashion and details of each bits are as defined below:\n\tBits 31-10\t\t Bit 9\tBit 8\tBit 7\tBit 6\tBit 5\tBit 4\t Bit 3\t Bit 2\t Bit 1\t Bit 0\n\tReserved\t\t 24\t 20\t 16\t 12\t 10\t 8\t 6\t 4\t 2\t 1\nBit = 0, not supported. Bit = 1, supported\nNote: Assumption is that sink shall support all lower slices per line than maximum selected field. i.e. If it supports say 8 slices per line, it will also support 4/2/1 slices per line", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Line buffer depth as per VESA DSC Spec: ", + "Visibility": "", + "Data": [ + "56", + "C8_Line_Buffer_Depth" + ], + "HelpText": "Line buffer depth in bits as per VESA DSC spec.", + "WidgetValues": [ + { + "Key": "8 bits", + "Value": "0" + }, + { + "Key": "9 bits", + "Value": "1" + }, + { + "Key": "10 bits", + "Value": "2" + }, + { + "Key": "11 bits", + "Value": "3" + }, + { + "Key": "12 bits", + "Value": "4" + }, + { + "Key": "13 bits", + "Value": "5" + }, + { + "Key": "14 bits", + "Value": "6" + }, + { + "Key": "15 bits", + "Value": "7" + }, + { + "Key": "16 bits", + "Value": "8" + } + ] + }, + { + "WidgetType": "EntryBin", + "WidgetName": "Input compression BPC supported by the sink device: ", + "Visibility": "", + "Data": [ + "56", + "C8_Dsc_Bpc" + ], + "HelpText": "This field defines the compression input bpc supported by the sink device.\nThe field is defined in bitmap fashion and details of each bits are as defined below:\n\tBits 7-4\t Bit 3\t Bit 2\t Bit 1\t Bit 0\n\tRsvd\t 12 bpc\t 10bpc\t 8bpc\t Rsvd\nBit = 0, not supported. Bit = 1, supported\nNote: Assumption is that sink shall support all lower bpc values than the maximum selected field. i.e. If it supports say 12bpc, it will also support 10 and 8bpc as well", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Maximum supported compression BPP: ", + "Visibility": "", + "Data": [ + "56", + "C8_Dsc_Max_Bpp" + ], + "HelpText": "As of today, we are supporting 6/8/10/12 BPP for compression output.\nSelect the most appropriate BPP as supported by the sink.", + "WidgetValues": [ + { + "Key": "6 Bits per pixel", + "Value": "0" + }, + { + "Key": "8 Bits per pixel", + "Value": "1" + }, + { + "Key": "10 Bits per pixel", + "Value": "2" + }, + { + "Key": "12 Bits per pixel", + "Value": "3" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Slice height supported by the sink device: ", + "Visibility": "", + "Data": [ + "56", + "C8_Dsc_Slice_Height" + ], + "HelpText": "Slice height supported by the sink device for DSC slice.\nNote: Slice height must divide the picture height uniformly.", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + } + ] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-9", + "PageName": "Panel #09", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "LabelHeading", + "WidgetName": "Common LFP Features", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryAsci", + "WidgetName": " LFP Panel Name: ", + "Visibility": "", + "Data": [ + "42", + "Panel_Name_09" + ], + "HelpText": "This feature defines the LFP panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Target X-Res: ", + "Visibility": "", + "Data": [ + "42", + "Panel_Width_09" + ], + "HelpText": "This value specifies the Target X-Resolution for this panel.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Target Y-Res: ", + "Visibility": "", + "Data": [ + "42", + "Panel_Height_09" + ], + "HelpText": "This value specifies the Target Y-Resolution for this panel.", + "WidgetValues": [] + }, + { + "WidgetType": "LabelHeading", + "WidgetName": " DPS Panel Type Features", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Seamless DRRS Minimum Refresh Rate (Hz): ", + "Visibility": "", + "Data": [ + "42", + "Seamless_DRRS_Min_RR_09" + ], + "HelpText": "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\nNote: Graphics driver will use this field only when EDID support is disabled in VBT configuration.", + "WidgetValues": [] + }, + { + "WidgetType": "LabelHeading", + "WidgetName": " BackLight Technology Type Features", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " BackLight Technology: ", + "Visibility": "", + "Data": [ + "40", + "Blt_Control_09" + ], + "HelpText": "This feature allows OEM to select the Backlight Technology.", + "WidgetValues": [ + { + "Key": "LED Backlight", + "Value": "2" + }, + { + "Key": "CCFL Backlight", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Panel Rotation: ", + "Visibility": "", + "Data": [ + "40", + "Panel_Rotation_09" + ], + "HelpText": "This feature specifies the Panel Rotation of LFP panel used.", + "WidgetValues": [ + { + "Key": "0 degree", + "Value": "0" + }, + { + "Key": "180 degree", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Panel Position: ", + "Visibility": "", + "Data": [ + "40", + "Panel_Position_09" + ], + "HelpText": "This feature specifies the Panel Position of LFP panel used.", + "WidgetValues": [ + { + "Key": "Inside Shell", + "Value": "0" + }, + { + "Key": "Outside Shell", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Dual LFP Port Sync: ", + "Visibility": "", + "Data": [ + "42", + "EnablePortSync_Bit_09" + ], + "HelpText": "This feature will allow users to disable/enable Dual LFP Port Sync and it is applicable for DDI-A, DDI-B in case of eDP and DSI-0, DSI-1 in case of MIPI. \r\n.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " GPU Dithering for Banding artifacts: ", + "Visibility": "", + "Data": [ + "42", + "EnableDithering_Bit_09" + ], + "HelpText": "This field can be used to enable dithering from the source side for reducing banding artifacts on the visual quality features like DPST.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "Button", + "WidgetName": "Power Features", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Generic DTD Timings", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "LFP PnP ID Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Backlight Control Parameters", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Chromaticity Control", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "VESA DSC Parameters", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "LabelHeading", + "WidgetName": "Integrated eDP Settings", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "eDP Fast Link Training Configuration Parameters", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "eDP Panel Power Sequencing Parameters", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Edp Max Port Link Rate (in 200 Khz): ", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [ + "27", + "eDP_Max_Port_Link_Rate_09" + ], + "HelpText": "This field specifies EDP Max Port Link Rate supported by the port in unit of 200KHz.\nDefault value would be \"0\", in which case Display Drivers should consider EDP Max Port Link Rate to be the Platform supported Max Link Rate.\nOnly when OEM's need to limit to particular Link Rate can enter the value as mentioned in below table.\n\nNote:\n1) OEM's need to enter the values mentioned from below table only.\n2) If value entered is not matching with any of the below values then Platform supported Max Link Rate should be considere as EDP Max Port Link Rate by the display drivers.\n3) In case of EDP Fast Link Training Params(FLT), if user enters FLT Link Rate value greater than the \"eDP Max Port Link Rate\" then we need to use \n Fast Link training Link Rate = MIN (FLT Link Rate , eDP Max Port Link Rate)\n---------------------------------------------------------\n|\tLink Rate(Gbps)\t|\t Value to enter in text field\t|\n|\t \t\t|\t in terms of 200KHZ \t|\n---------------------------------------------------------\n|\t 1.62 \t\t|\t 8100 \t|\n|\t 2.16 \t\t|\t 10800 \t|\n|\t 2.43 \t\t|\t 12150 \t|\n|\t 2.7 \t\t|\t 13500 \t|\n|\t 3.24 \t\t|\t 16200 \t|\n|\t 3.78 \t\t|\t 18900 \t|\n|\t 4.32 \t\t|\t 21600 \t|\n|\t 5.4 \t\t|\t 27000 \t|\n|\t 6.48 \t\t|\t 32400 \t|\n|\t 6.75 \t\t|\t 33750 \t|\n|\t 8.1 \t\t|\t 40500 \t|\n", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Panel Color Depth: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Panel_Color_Depth_09" + ], + "HelpText": "This feature specifies the color depth of eDP panel used.", + "WidgetValues": [ + { + "Key": "18-bit Color Depth", + "Value": "0" + }, + { + "Key": "24-bit Color Depth", + "Value": "1" + }, + { + "Key": "30-bit Color Depth", + "Value": "2" + }, + { + "Key": "36-bit Color Depth", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Select VSwing/Pre-Emphasis table : ", + "Visibility": "", + "Data": [ + "27", + "eDP_VswingPreEmph_9" + ], + "HelpText": "This feature selects the VSwing Pre-Emphasis setting table to be used. For Tigerlake, based on the selection respective table will be used.\nTables for Tigerlake:\nLow Power VSwing Pre-Emphasis Setting Table:\nFor HBR2:\n\t\t\t\t\t\t Pre-Emphasis (db)\n\t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\nVoltage \t\t Level-0/200mV \t\t 200mV, 0.0db \t\t 200mV, 1.9db \t\t 200mV, 3.5db \t\t 200mV, 4.9db\nSwing \t\t Level-1/250mV \t\t 250mV, 0.0db \t\t 250mV, 1.6db \t\t 250mV, 2.9db \t\t N/A\n(mV) \t\t Level-2/300mV \t\t 300mV, 0.0db \t\t 300mV, 1.3db \t\t N/A \t\t N/A\n\t\t Level-3/350mV \t\t 350mV, 0.0db \t\t N/A \t\t N/A \t\t N/A\n\n\nFor HBR3:\n\t\t\t\t\t\t Pre-Emphasis (db)\n\t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\nVoltage \t\t Level-0/350mV \t\t 350mV, 0.0db \t\t 350mV, 3.1db \t\t 350mV, 6.0db \t\t 350mV, 8.2db\nSwing \t\t Level-1/500mV \t\t 500mV, 0.0db \t\t 500mV, 2.9db \t\t 500mV, 5.1db \t\t N/A\n(mV) \t\t Level-2/650mV \t\t 650mV, 0.6db \t\t 600mV, 3.5db \t\t N/A \t\t N/A\n\t\t Level-3/900mV \t\t 900mV, 0.0db \t\t N/A \t\t N/A \t\t N/A\n\n\nDefault VSwing Pre-Emphasis Setting Table:\nFor HBR:\n\t\t\t\t\t\t Pre-Emphasis (db)\n\t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\nVoltage \t\t Level-0/350mV \t\t 350mV, 0.0db \t\t 350mV, 3.1db \t\t 350mV, 6.0db \t\t 350mV, 8.2db\nSwing \t\t Level-1/500mV \t\t 500mV, 0.0db \t\t 500mV, 2.9db \t\t 500mV, 5.1db \t\t N/A\n(mV) \t\t Level-2/650mV \t\t 650mV, 0.6db \t\t 600mV, 3.5db \t\t N/A \t\t N/A\n\t\t Level-3/900mV \t\t 900mV, 0.0db \t\t N/A \t\t N/A \t\t N/A\n\n\nFor HBR2:\n\t\t\t\t\t\t Pre-Emphasis (db)\n\t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\nVoltage \t\t Level-0/350mV \t\t 350mV, 0.0db \t\t 350mV, 3.1db \t\t 350mV, 6.0db \t\t 350mV, 8.2db\nSwing \t\t Level-1/500mV \t\t 500mV, 0.0db \t\t 500mV, 2.9db \t\t 500mV, 5.1db \t\t N/A\n(mV) \t\t Level-2/650mV \t\t 650mV, 0.6db \t\t 600mV, 3.5db \t\t N/A \t\t N/A\n\t\t Level-3/900mV \t\t 900mV, 0.0db \t\t N/A \t\t N/A \t\t N/A", + "WidgetValues": [ + { + "Key": "Default VSwing/Pre-Emphasis Table", + "Value": "1" + }, + { + "Key": "Low Power VSwing/Pre-Emphasis Table", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " eDP Spread Spectrum Clock: ", + "Visibility": "", + "Data": [ + "40", + "Enable_SSC09" + ], + "HelpText": "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Pixel Overlap Count: ", + "Visibility": "", + "Data": [ + "42", + "PixelOverlapCount_09" + ], + "HelpText": "Select the number of Pixels to be overlapped per half of Scanline while using Edp Multi-SST(MSO) feature.", + "WidgetValues": [ + { + "Key": "Zero Pixel Overlap", + "Value": "0" + }, + { + "Key": "One Pixel Overlap", + "Value": "1" + }, + { + "Key": "Two Pixel Overlap", + "Value": "2" + }, + { + "Key": "Three Pixel Overlap", + "Value": "3" + }, + { + "Key": "Four Pixel Overlap", + "Value": "4" + }, + { + "Key": "Five Pixel Overlap", + "Value": "5" + }, + { + "Key": "Six Pixel Overlap", + "Value": "6" + }, + { + "Key": "Seven Pixel Overlap", + "Value": "7" + }, + { + "Key": "Eight Pixel Overlap", + "Value": "8" + } + ] + }, + { + "WidgetType": "Button", + "WidgetName": "PSR Feature", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Apical Feature", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + } + ], + "NestedPages": [ + { + "Type": "Block", + "Block": { + "PageNum": "5-2-9-1", + "PageName": "eDP Panel Power Sequencing Parameters", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " T3 optimization: ", + "Visibility": "", + "Data": [ + "27", + "eDP_T3_Optimization_09" + ], + "HelpText": "This feature enables or disables T3 optimization.\nWhen enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\nWhen disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "LCDVCC to HPD high delay (T3): ", + "Visibility": "", + "Data": [ + "27", + "eDP_Vcc_To_Hpd_Delay_09" + ], + "HelpText": "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\nValid Range: 0 to 200msec", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Valid video data to Backlight Enable delay (T8): ", + "Visibility": "", + "Data": [ + "27", + "eDP_DataOn_To_BkltEnable_Delay_09" + ], + "HelpText": "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\nT8 is inclusive of T7.\nValid Range of T7: 0 to 50msec", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "PWM-On To Backlight Enable delay: ", + "Visibility": "", + "Data": [ + "27", + "eDP_PwmOn_To_Bklt_Enable_Delay_09" + ], + "HelpText": "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\nDelay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\nSo it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Backlight Disable to PWM-Off delay: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Bklt_Disable_To_PwmOff_Delay_09" + ], + "HelpText": "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\nDelay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\nSo it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Backlight Disable to End of Valid video data delay (T9): ", + "Visibility": "", + "Data": [ + "27", + "eDP_BkltDisable_To_DataOff_Delay_09" + ], + "HelpText": "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "End of Valid video data to Power-Off delay (T10): ", + "Visibility": "", + "Data": [ + "27", + "eDP_DataOff_To_PowerOff_Delay_09" + ], + "HelpText": "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\nValid Range: 0 to 500 msec", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Power-off time (T12): ", + "Visibility": "", + "Data": [ + "27", + "eDP_PowerCycle_Delay_09" + ], + "HelpText": "Using this field Power-off time can be specified in 100uS.", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-9-2", + "PageName": "eDP Fast Link Training Configuration Parameters", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Is FastLinkTraining Feature Supported: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Fast_Link_Training_Supported_09" + ], + "HelpText": "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled.", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Data Rate: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Fast_Link_Training_Data_Rate_09" + ], + "HelpText": "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. It will be used if the sink indicates that no aux handshake is required during link training.\n\nIn case of EDP Fast Link Training Params(FLT), if user enters FLT Link Rate value greater than the \"eDP Max Port Link Rate\" then driver would use \n Fast Link training Link Rate = MIN (FLT Link Rate , eDP Max Port Link Rate).", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Lane Count: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Link_LaneCount_09" + ], + "HelpText": "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. It will be used if the sink indicates that no aux handshake is required during link training.", + "WidgetValues": [ + { + "Key": "x1", + "Value": "0" + }, + { + "Key": "x2", + "Value": "1" + }, + { + "Key": "x4", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Pre-Emphasis: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Link_PreEmp_09" + ], + "HelpText": "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. It will be used if the sink indicates that no aux handshake is required during link training.", + "WidgetValues": [ + { + "Key": "Level-0", + "Value": "0" + }, + { + "Key": "Level-1", + "Value": "1" + }, + { + "Key": "Level-2", + "Value": "2" + }, + { + "Key": "Level-3", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Voltage Swing: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Link_Vswing_09" + ], + "HelpText": "This feature allows for the selection of the Voltage Swing value for the embedded DP link. It will be used if the sink indicates that no aux handshake is required during link training.", + "WidgetValues": [ + { + "Key": "Swing-0", + "Value": "0" + }, + { + "Key": "Swing-1", + "Value": "1" + }, + { + "Key": "Swing-2", + "Value": "2" + }, + { + "Key": "Swing-3", + "Value": "3" + } + ] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-9-3", + "PageName": "PSR Feature", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Full Link enable: ", + "Visibility": "", + "Data": [ + "9", + "PSR_FullLink_Enable_09" + ], + "HelpText": "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state.", + "WidgetValues": [ + { + "Key": "No", + "Value": "0" + }, + { + "Key": "Yes", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Require AUX to wake up: ", + "Visibility": "", + "Data": [ + "9", + "PSR_Require_AUX2Wakeup_09" + ], + "HelpText": "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used.", + "WidgetValues": [ + { + "Key": "No", + "Value": "0" + }, + { + "Key": "Yes", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Lines to wait before link standby: ", + "Visibility": "", + "Data": [ + "9", + "PSR_Lines2Wait_B4LinkS3_09" + ], + "HelpText": "This field determines Lines to wait before link standby\n0 lines to wait (Default)\n1 lines to wait\n4 lines to wait\n8 lines to wait\nOthers Reserved", + "WidgetValues": [ + { + "Key": "0 lines to wait", + "Value": "0" + }, + { + "Key": "1 lines to wait", + "Value": "1" + }, + { + "Key": "4 lines to wait", + "Value": "2" + }, + { + "Key": "8 lines to wait", + "Value": "3" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Idle frames to wait: ", + "Visibility": "", + "Data": [ + "9", + "PSR_IdleFrames2Wait_09" + ], + "HelpText": "Idle frames to wait for PSR enable.\nAllowed values 0-15. Default value is 0.", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Clock Recovery Time: ", + "Visibility": "", + "Data": [ + "9", + "PSR_TP1_WaitTime_09" + ], + "HelpText": "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)", + "WidgetValues": [ + { + "Key": "500 usec", + "Value": "0" + }, + { + "Key": "100 usec", + "Value": "1" + }, + { + "Key": "2.5 msec", + "Value": "2" + }, + { + "Key": "0 (Skip)", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Channel Equalization Time for PSR1 panel: ", + "Visibility": "", + "Data": [ + "9", + "PSR1_TP_2_3_4_WaitTime_09" + ], + "HelpText": "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) or TP4(Training Pattern4) time during PSR1 exit(wake up)", + "WidgetValues": [ + { + "Key": "500 usec", + "Value": "0" + }, + { + "Key": "100 usec", + "Value": "1" + }, + { + "Key": "2.5 msec", + "Value": "2" + }, + { + "Key": "0 (Skip)", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Channel Equalization Time for PSR2 panel: ", + "Visibility": "", + "Data": [ + "9", + "PSR2_TP_2_3_4_WaitTime_09" + ], + "HelpText": "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) or TP4(Training Pattern4) time during PSR2 exit(wake up)", + "WidgetValues": [ + { + "Key": "500 usec", + "Value": "0" + }, + { + "Key": "100 usec", + "Value": "1" + }, + { + "Key": "2.5 msec", + "Value": "2" + }, + { + "Key": "50 usec", + "Value": "3" + } + ] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-9-4", + "PageName": "Apical Feature", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Apical Assertive Display IP: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Apical_Display_Ip_Enable_09" + ], + "HelpText": "This field enables/disables the Apical Assertive Display IP for this panel.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Panel OUI (IEEE OUI): ", + "Visibility": "", + "Data": [ + "27", + "eDP_Panel_Oui_09" + ], + "HelpText": "This field specifies the Apical IP specific Panel OUI field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " DPCD Base Address: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Dpcd_Base_Address_09" + ], + "HelpText": "This field specifies the Apical IP specific DPCD base address field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " DPCD Irdidix Control 0: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Dpcd_Irdidix_Control0_09" + ], + "HelpText": "This field specifies the Apical IP specific DPCD Irdidix control 0 field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " DPCD Option Select: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Dpcd_Option_Select_09" + ], + "HelpText": "This field specifies the Apical IP specific DPCD option select field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " DPCD Backlight: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Dpcd_Backlight_09" + ], + "HelpText": "This field specifies the Apical IP specific backlight value.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Ambient Light: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Ambient_Light_09" + ], + "HelpText": "This field specifies the Apical IP specific Ambient light value.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Backlight scale: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Backlight_Scale_09" + ], + "HelpText": "This field specifies the Apical IP specific backlight scale field.", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-9-5", + "PageName": "Power Features", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Intel Display Power Saving Technology (DPST) (Mobile only): ", + "Visibility": "", + "Data": [ + "44", + "DPST_Enable_09" + ], + "HelpText": "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled.\nIntel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power.\nNote: This technology is only active when the system is running in battery mode and the LFP is the only active display device.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Intel Display Refresh Rate Switching (DRRS) (Mobile only): ", + "Visibility": "", + "Data": [ + "44", + "DRRS_Enable_09" + ], + "HelpText": "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Edge Luminance Profile (ELP) : ", + "Visibility": "", + "Data": [ + "44", + "ELP_Enable_09" + ], + "HelpText": "This feature determines whether the ELP feature is enabled or disabled.\nEdge Luminance Profile (ELP) is a panel technology which reduce luminance on the edge of screen to save panel power.\nNote:This technology cannot co-exist with DPST and OPST ((i.e.) OPST, DPST and ELP cannot exist together.They are all mutually exclusive to each other.)", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " OLED Power Saving Technology (OPST) : ", + "Visibility": "", + "Data": [ + "44", + "OPST_Enable_09" + ], + "HelpText": "This feature determines whether the OPST feature is enabled or disabled.\nOLED Power Saving Technology (OPST) is a panel technology which saves power by intelligent, adaptive dimming of midrange pixel values more aggressively than the extremes without compromising the viewability.\nNote: This technology cannot co-exist with ELP and DPST ((i.e.) OPST, DPST and ELP cannot exist together.They are all mutually exclusive to each other.)", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Dynamic Media Refresh Rate Switching Enable/Disable ", + "Visibility": "", + "Data": [ + "44", + "DMRRS_Enable_09" + ], + "HelpText": "This feature determines whether Dynamic media refresh rate switching is to be enabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Enable Display Lace Support: ", + "Visibility": "", + "Data": [ + "44", + "LACE_Enable_09" + ], + "HelpText": "This feature, when enabled, will set Display Lace Support otherwise, the functionality will be disabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Panel Self Refresh (PSR): ", + "Visibility": "", + "Data": [ + "44", + "PSR_Enable_09" + ], + "HelpText": "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Assertive Display Technology Enable/Disable: ", + "Visibility": "", + "Data": [ + "44", + "ADT_Enable_09" + ], + "HelpText": "This feature determines whether Assertive display technology is to be enabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Intel Automatic Display Brightness (ADB) (Mobile only): ", + "Visibility": "", + "Data": [ + "44", + "ADB_Enable_09" + ], + "HelpText": "This feature determines whether Intel Automatic Display Brightness is to be enabled. Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) depending on the current ambient light environment.\nWhen enabled, the driver and VBIOS will control the backlight brightness of the LFP depending on the ambient environment if and only if the LFP is the only active display. When disabled, the driver will perform no action.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "EDP 4k/2k HOBL Feature: ", + "Visibility": "", + "Data": [ + "44", + "eDP_4k_2k_HOBL_feature_Enable_09" + ], + "HelpText": "This feature will allow users to disable/enable the edp 4k/2k HOBL(Hours Of Battery Life) feature by programming relevant registers specific for a platform.\r\n.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Default Display LACE Enabled status: ", + "Visibility": "", + "Data": [ + "44", + "LACE_Status_09" + ], + "HelpText": "This feature, when enabled, will set Default Display LACE Enabled status otherwise, the functionality will be disabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "DPST Aggressiveness Level: ", + "Visibility": "", + "Data": [ + "44", + "DPST_Aggressiveness_Profile_09" + ], + "HelpText": "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n1 (Maximum Quality with No DPST)\n2\n3\n4\n5\n6 (Maximum Battery)", + "WidgetValues": [ + { + "Key": "1 - Maximum Quality with No DPST", + "Value": "1" + }, + { + "Key": "2", + "Value": "2" + }, + { + "Key": "3", + "Value": "3" + }, + { + "Key": "4", + "Value": "4" + }, + { + "Key": "5", + "Value": "5" + }, + { + "Key": "6 - Maximum Battery", + "Value": "6" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "LACE Aggressiveness Level: ", + "Visibility": "", + "Data": [ + "44", + "LACE_Aggressiveness_Profile_09" + ], + "HelpText": "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\nMinimum 0\nModerate 1\nHigh 2", + "WidgetValues": [ + { + "Key": "Minimum", + "Value": "0" + }, + { + "Key": "Moderate", + "Value": "1" + }, + { + "Key": "High", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "ELP Aggressiveness Level: ", + "Visibility": "", + "Data": [ + "44", + "ELP_Aggressiveness_Profile_09" + ], + "HelpText": "This feature allows for the selection of ELP Aggressiveness level for this Panel Type.\nMinimum Power Savings\nMedium Power Savings \nMaximum Power Savings", + "WidgetValues": [ + { + "Key": "Minimum Power Savings", + "Value": "0" + }, + { + "Key": "Medium Power Savings", + "Value": "1" + }, + { + "Key": "Maximum Power Savings", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "OPST Aggressiveness Level: ", + "Visibility": "", + "Data": [ + "44", + "OPST_Aggressiveness_Profile_09" + ], + "HelpText": "This feature allows for the selection of OPST Aggressiveness level for this Panel Type.\nMinimum Power Savings\nMedium Power Savings \nMaximum Power Savings", + "WidgetValues": [ + { + "Key": "Minimum Power Savings", + "Value": "0" + }, + { + "Key": "Medium Power Savings", + "Value": "1" + }, + { + "Key": "Maximum Power Savings", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Default Display VRR Enabled status: ", + "Visibility": "", + "Data": [ + "44", + "VRR_Status_09" + ], + "HelpText": "VRR (Variable Refresh Rate) is a feature that can continuously and seamlessly vary Refresh Rate on the fly, on displays that support Variable Refresh rate Technologies.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-9-6", + "PageName": "Generic DTD Timings", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Pixel Clock in KHz: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_Pixel_CLK_09" + ], + "HelpText": "Pixel Clock (in KHz) Range from 0.001 to 4294967.295 MP/s.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Active: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_Active_09" + ], + "HelpText": "Horizontal Active Image Pixels Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Active: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_Active_09" + ], + "HelpText": "Vertical Active Image Lines Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Blank: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_Blank_09" + ], + "HelpText": "Horizontal Blank Pixels Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Blank: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_Blank_09" + ], + "HelpText": "Vertical Blank lines Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Front Porch: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_FrontPorch_09" + ], + "HelpText": "Horizontal Front Porch Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Front Porch: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_FrontPorch_09" + ], + "HelpText": "Vertical Front Porch Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Sync: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_Sync_09" + ], + "HelpText": "Horizontal Sync Width Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Sync: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_Sync_09" + ], + "HelpText": "Vertical Sync Width Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Image Size: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_Image_Size_09" + ], + "HelpText": "Horizontal Addressable Video Image Size in mm represented by 16bits. Image size multiplier 1.00 mm precision.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Image Size: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_Image_Size_09" + ], + "HelpText": "Vertical Addressable Video Image Size in mm represented by 16bits. Image size multiplier 1.00 mm precision.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryBin", + "WidgetName": "Common Flag: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_Common_Flag_09" + ], + "HelpText": "Common DTD Flags:\nBit 7 : Horizontal Sync Polarity\n1 : Positive\n0 : Negative\nBit 6 : Vertical Sync polarity\n1 : Positive\n0 : Negative\nBit 5 - 0: Reserved (Default value 0)", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-9-7", + "PageName": "LFP PnP ID Table", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Table", + "WidgetName": "", + "Visibility": "", + "Data": [ + "42", + "LFP_Panel_PnP_ID_09" + ], + "HelpText": "This feature allows the 10 bytes of EDID Vendor/Product ID starting at offset 08h to be used as a PnP ID.\n\nTable Definition:\n\tWord: ID Manufacturer Name\n\tWord: ID Product Code\n\tDWord: ID Serial Number\n\tByte: Week of Manufacture\n\tByte: Year of Manufacture", + "WidgetValues": [ + { + "ColumnName": "PnP ID", + "SizeinBytes": "1" + } + ] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-9-8", + "PageName": "Backlight Control Parameters", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Inverter Type: ", + "Visibility": "", + "Data": [ + "43", + "BLC_Inv_Type_09" + ], + "HelpText": "This feature allows for the selection of the Backlight Inverter type that is to be used to control the backlight brightness of the LFP.\nWhen PWM is selected, the driver and VBIOS will control the backlight brightness via the integrated PWM solution for the applicable chipsets.\nWhen None/External is selected, the system BIOS will control the backlight brightness via the external solution.", + "WidgetValues": [ + { + "Key": "None/External", + "Value": "0" + }, + { + "Key": "PWM", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Pwm Source Selection: ", + "Visibility": "", + "Data": [ + "43", + "Lfp_Pwm_Source_Selection_09" + ], + "HelpText": "If panel supports 'Intel HDR AUX Interface', it will always be chosen by default. If not, value in 'PWM Source Selection' will be used", + "WidgetValues": [ + { + "Key": "PWM From Display Engine", + "Value": "2" + }, + { + "Key": "PWM From LCD Panel", + "Value": "3" + }, + { + "Key": "Panel Driver Interface", + "Value": "4" + }, + { + "Key": "VESA eDP AUX Interface", + "Value": "5" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Pwm Controller Selection: ", + "Visibility": "", + "Data": [ + "43", + "Lfp_Pwm_Controller_Selection_09" + ], + "HelpText": "This field allows to select the PWM Controller to be used for the selected Local Flat Panel.This field allows to select the PWM Controller to be used for the selected Local Flat Panel.If Two LFPs are connected then PWM0 and PWM1 must be selected accordingly.", + "WidgetValues": [ + { + "Key": "PWM0", + "Value": "0" + }, + { + "Key": "PWM1", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Inverter Polarity: ", + "Visibility": "", + "Data": [ + "43", + "BLC_Inv_Polarity_09" + ], + "HelpText": "This feature allows the backlight inverter polarity to be specified.\nNormal means 0 value is minimum brightness.\nInverted means 0 value is maximum brightness.", + "WidgetValues": [ + { + "Key": "Normal", + "Value": "0" + }, + { + "Key": "Inverted", + "Value": "1" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Minimum Brightness: ", + "Visibility": "", + "Data": [ + "43", + "Post_Min_Brightness_09" + ], + "HelpText": "This feature allows defining the absolute minimum backlight brightness. The driver will never decrease the backlight less than this value. The value must be specified using normal polarity semantics. The value should range from 0 to 255 if the brightness precision bit is chosen to be 8, and it should range from 0 to 65535 if the precision bit is chosen to be 16.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "POST Backlight Intensity: ", + "Visibility": "", + "Data": [ + "43", + "Post_Brightness_09" + ], + "HelpText": "This feature is used to set default backlight brightness value of the panel at POST. The value should range from 0 to 255 if the bit precision is chosen to be 8 and it should range from 0 to 65535 if the brightness bit precision is chosent to be 16.", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Brightness Precision Bits: ", + "Visibility": "", + "Data": [ + "43", + "BrightnessPrecisionBits_09" + ], + "HelpText": "This field represents the range of brightness in terms of bit precision.\n 8 = Brightness range of 0 to 255.\n 16 = Brightness range of 0 to 65535", + "WidgetValues": [ + { + "Key": "8", + "Value": "8" + }, + { + "Key": "16", + "Value": "16" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "PWM Inverter Frequency (Hz): ", + "Visibility": "", + "Data": [ + "43", + "PWM_Frequency_09" + ], + "HelpText": "This feature allows for the definition of the frequency needed for PWM Inverter.\nNote: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Intel HDR DPCD Refresh Timeout (unit - 10 micro seconds): ", + "Visibility": "", + "Data": [ + "43", + "HdrDpcdRefreshTimeout_09" + ], + "HelpText": "This field allows to configure the refresh timeout of Intel HDR DPCDs for different TCON Vendors.\nNote:\n\tThe value is in units of 10 microseconds.\n\tThe range (entered as a decimal number), for the timeout is 0-65535", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-9-9", + "PageName": "Chromaticity Control", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Chromaticity Control Feature: ", + "Visibility": "", + "Data": [ + "46", + "Chromacity_Enable_09" + ], + "HelpText": "This bit enables Chromaticity feature.\nIf this bit is enabled, EDID values for chromaticity will be used, else feature is disabled.\nFeature will be supported for Panels that support EDID version 1.4 or higher.\nPlease refer to section 3.7 of EDID Specification 1.4.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Override the EDID values: ", + "Visibility": "", + "Data": [ + "46", + "Override_EDID_Data_09" + ], + "HelpText": "This option when enabled along with Chromaticity feature will override EDID values through following VBT data", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Red_Green_bits (Bits 1:0 at 19h): ", + "Visibility": "", + "Data": [ + "46", + "Red_Green_09" + ], + "HelpText": "Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Blue_White_bits (Bits 1:0 at 1Ah): ", + "Visibility": "", + "Data": [ + "46", + "Blue_White_09" + ], + "HelpText": "Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Red_x (Bits 9:2 at 1Bh): ", + "Visibility": "", + "Data": [ + "46", + "Red_x_09" + ], + "HelpText": "Bits 9:2 of red color x coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Red_y (Bits 9:2 at 1Ch): ", + "Visibility": "", + "Data": [ + "46", + "Red_y_09" + ], + "HelpText": "Bits 9:2 of red color y coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Green_x (Bits 9:2 at 1Dh): ", + "Visibility": "", + "Data": [ + "46", + "Green_x_09" + ], + "HelpText": "Bits 9:2 of Green color x coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Green_y (Bits 9:2 at 1Eh): ", + "Visibility": "", + "Data": [ + "46", + "Green_y_09" + ], + "HelpText": "Bits 9:2 of Green color y coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Blue_x (Bits 9:2 at 1Fh): ", + "Visibility": "", + "Data": [ + "46", + "Blue_x_09" + ], + "HelpText": "Bits 9:2 of Blue color x coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Blue_y (Bits 9:2 at 20h): ", + "Visibility": "", + "Data": [ + "46", + "Blue_y_09" + ], + "HelpText": "Bits 9:2 of Blue color y coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " White_x (Bits 9:2 at 21h): ", + "Visibility": "", + "Data": [ + "46", + "White_x_09" + ], + "HelpText": "Bits 9:2 of White color x coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " White_y (Bits 9:2 at 22h): ", + "Visibility": "", + "Data": [ + "46", + "White_y_09" + ], + "HelpText": "Bits 9:2 of White color y coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Override Luminance values ", + "Visibility": "", + "Data": [ + "46", + "Override_LUM_Data_09" + ], + "HelpText": "This option when enabled along with Chromaticity feature will override luminance values following VBT values", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Minimum Luminance: ", + "Visibility": "", + "Data": [ + "46", + "MinLuminance_09" + ], + "HelpText": "Minimum luminance value.\n2 byte value, encoded in IEEE 754 half-precision binary floating point format,", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Maximum full frame luminance: ", + "Visibility": "", + "Data": [ + "46", + "MaxFullLuminance_09" + ], + "HelpText": "Maximum Full frame luminance value.\n2 byte value, encoded in IEEE 754 half-precision binary floating point format,", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Maximum Luminance: ", + "Visibility": "", + "Data": [ + "46", + "MaxLuminance_09" + ], + "HelpText": "Maximum luminance value(Relatively smaller portion of screen).\n2 byte value, encoded in IEEE 754 half-precision binary floating point format.", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Override Gamma values: ", + "Visibility": "", + "Data": [ + "46", + "Override_Gamma_Data_09" + ], + "HelpText": "This option when enabled along with Chromaticity feature will override gamma values through following VBT data", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Panel gamma: ", + "Visibility": "", + "Data": [ + "46", + "Gamma_09" + ], + "HelpText": "Value shall define the gamma range, from 1.00 to 3.54, as follows:\nField Value = (Gamma (value in float) x 100) - 100\nField values range from 00h through FFh.\nFFh = No gamma information shall be provided", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-9-10", + "PageName": "VESA DSC Parameters", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "DSC Major Version: ", + "Visibility": "", + "Data": [ + "56", + "C9_Major_Dsc_Version" + ], + "HelpText": "VESA DSC Major revision field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "DSC Minor Version: ", + "Visibility": "", + "Data": [ + "56", + "C9_Minor_Dsc_Version" + ], + "HelpText": "VESA DSC Minor revision field.", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Block prediction supported: ", + "Visibility": "", + "Data": [ + "56", + "C9_Blk_Prediction_En" + ], + "HelpText": "Sink supports block prediction as per the VESA DSC Spec.", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "RC Buffer Block size as per VESA DSC Spec: ", + "Visibility": "", + "Data": [ + "56", + "C9_RC_Block_Size" + ], + "HelpText": "RC buffer block size for a single RC buffer as defined by the VESA DSC spec.", + "WidgetValues": [ + { + "Key": "1 KB", + "Value": "0" + }, + { + "Key": "4 KB", + "Value": "1" + }, + { + "Key": "16 KB", + "Value": "2" + }, + { + "Key": "64 KB", + "Value": "3" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Number of RC buffer blocks as per VESA DSC Spec: ", + "Visibility": "", + "Data": [ + "56", + "C9_Dsc_RC_Buf_Size" + ], + "HelpText": "This field defines the number of RC buffers as per VESA DSC spec.\nThe number of RC buffers used by the software shall be (Value + 1) where Value is in range 0 to 127.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryBin", + "WidgetName": "Slices per line supported by the sink device: ", + "Visibility": "", + "Data": [ + "56", + "C9_Dsc_Slices_Per_Line" + ], + "HelpText": "This field defines the slices per line supported by the sink device.\nThe field is defined in bitmap fashion and details of each bits are as defined below:\n\tBits 31-10\t\t Bit 9\tBit 8\tBit 7\tBit 6\tBit 5\tBit 4\t Bit 3\t Bit 2\t Bit 1\t Bit 0\n\tReserved\t\t 24\t 20\t 16\t 12\t 10\t 8\t 6\t 4\t 2\t 1\nBit = 0, not supported. Bit = 1, supported\nNote: Assumption is that sink shall support all lower slices per line than maximum selected field. i.e. If it supports say 8 slices per line, it will also support 4/2/1 slices per line", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Line buffer depth as per VESA DSC Spec: ", + "Visibility": "", + "Data": [ + "56", + "C9_Line_Buffer_Depth" + ], + "HelpText": "Line buffer depth in bits as per VESA DSC spec.", + "WidgetValues": [ + { + "Key": "8 bits", + "Value": "0" + }, + { + "Key": "9 bits", + "Value": "1" + }, + { + "Key": "10 bits", + "Value": "2" + }, + { + "Key": "11 bits", + "Value": "3" + }, + { + "Key": "12 bits", + "Value": "4" + }, + { + "Key": "13 bits", + "Value": "5" + }, + { + "Key": "14 bits", + "Value": "6" + }, + { + "Key": "15 bits", + "Value": "7" + }, + { + "Key": "16 bits", + "Value": "8" + } + ] + }, + { + "WidgetType": "EntryBin", + "WidgetName": "Input compression BPC supported by the sink device: ", + "Visibility": "", + "Data": [ + "56", + "C9_Dsc_Bpc" + ], + "HelpText": "This field defines the compression input bpc supported by the sink device.\nThe field is defined in bitmap fashion and details of each bits are as defined below:\n\tBits 7-4\t Bit 3\t Bit 2\t Bit 1\t Bit 0\n\tRsvd\t 12 bpc\t 10bpc\t 8bpc\t Rsvd\nBit = 0, not supported. Bit = 1, supported\nNote: Assumption is that sink shall support all lower bpc values than the maximum selected field. i.e. If it supports say 12bpc, it will also support 10 and 8bpc as well", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Maximum supported compression BPP: ", + "Visibility": "", + "Data": [ + "56", + "C9_Dsc_Max_Bpp" + ], + "HelpText": "As of today, we are supporting 6/8/10/12 BPP for compression output.\nSelect the most appropriate BPP as supported by the sink.", + "WidgetValues": [ + { + "Key": "6 Bits per pixel", + "Value": "0" + }, + { + "Key": "8 Bits per pixel", + "Value": "1" + }, + { + "Key": "10 Bits per pixel", + "Value": "2" + }, + { + "Key": "12 Bits per pixel", + "Value": "3" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Slice height supported by the sink device: ", + "Visibility": "", + "Data": [ + "56", + "C9_Dsc_Slice_Height" + ], + "HelpText": "Slice height supported by the sink device for DSC slice.\nNote: Slice height must divide the picture height uniformly.", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + } + ] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-10", + "PageName": "Panel #10", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "LabelHeading", + "WidgetName": "Common LFP Features", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryAsci", + "WidgetName": " LFP Panel Name: ", + "Visibility": "", + "Data": [ + "42", + "Panel_Name_10" + ], + "HelpText": "This feature defines the LFP panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Target X-Res: ", + "Visibility": "", + "Data": [ + "42", + "Panel_Width_10" + ], + "HelpText": "This value specifies the Target X-Resolution for this panel.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Target Y-Res: ", + "Visibility": "", + "Data": [ + "42", + "Panel_Height_10" + ], + "HelpText": "This value specifies the Target Y-Resolution for this panel.", + "WidgetValues": [] + }, + { + "WidgetType": "LabelHeading", + "WidgetName": " DPS Panel Type Features", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Seamless DRRS Minimum Refresh Rate (Hz): ", + "Visibility": "", + "Data": [ + "42", + "Seamless_DRRS_Min_RR_10" + ], + "HelpText": "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\nNote: Graphics driver will use this field only when EDID support is disabled in VBT configuration.", + "WidgetValues": [] + }, + { + "WidgetType": "LabelHeading", + "WidgetName": " BackLight Technology Type Features", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " BackLight Technology: ", + "Visibility": "", + "Data": [ + "40", + "Blt_Control_10" + ], + "HelpText": "This feature allows OEM to select the Backlight Technology.", + "WidgetValues": [ + { + "Key": "LED Backlight", + "Value": "2" + }, + { + "Key": "CCFL Backlight", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Panel Rotation: ", + "Visibility": "", + "Data": [ + "40", + "Panel_Rotation_10" + ], + "HelpText": "This feature specifies the Panel Rotation of LFP panel used.", + "WidgetValues": [ + { + "Key": "0 degree", + "Value": "0" + }, + { + "Key": "180 degree", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Panel Position: ", + "Visibility": "", + "Data": [ + "40", + "Panel_Position_10" + ], + "HelpText": "This feature specifies the Panel Position of LFP panel used.", + "WidgetValues": [ + { + "Key": "Inside Shell", + "Value": "0" + }, + { + "Key": "Outside Shell", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Dual LFP Port Sync: ", + "Visibility": "", + "Data": [ + "42", + "EnablePortSync_Bit_10" + ], + "HelpText": "This feature will allow users to disable/enable Dual LFP Port Sync and it is applicable for DDI-A, DDI-B in case of eDP and DSI-0, DSI-1 in case of MIPI. \r\n.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " GPU Dithering for Banding artifacts: ", + "Visibility": "", + "Data": [ + "42", + "EnableDithering_Bit_10" + ], + "HelpText": "This field can be used to enable dithering from the source side for reducing banding artifacts on the visual quality features like DPST.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "Button", + "WidgetName": "Power Features", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Generic DTD Timings", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "LFP PnP ID Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Backlight Control Parameters", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Chromaticity Control", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "VESA DSC Parameters", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "LabelHeading", + "WidgetName": "Integrated eDP Settings", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "eDP Fast Link Training Configuration Parameters", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "eDP Panel Power Sequencing Parameters", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Edp Max Port Link Rate (in 200 Khz): ", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [ + "27", + "eDP_Max_Port_Link_Rate_10" + ], + "HelpText": "This field specifies EDP Max Port Link Rate supported by the port in unit of 200KHz.\nDefault value would be \"0\", in which case Display Drivers should consider EDP Max Port Link Rate to be the Platform supported Max Link Rate.\nOnly when OEM's need to limit to particular Link Rate can enter the value as mentioned in below table.\n\nNote:\n1) OEM's need to enter the values mentioned from below table only.\n2) If value entered is not matching with any of the below values then Platform supported Max Link Rate should be considere as EDP Max Port Link Rate by the display drivers.\n3) In case of EDP Fast Link Training Params(FLT), if user enters FLT Link Rate value greater than the \"eDP Max Port Link Rate\" then we need to use \n Fast Link training Link Rate = MIN (FLT Link Rate , eDP Max Port Link Rate)\n---------------------------------------------------------\n|\tLink Rate(Gbps)\t|\t Value to enter in text field\t|\n|\t \t\t|\t in terms of 200KHZ \t|\n---------------------------------------------------------\n|\t 1.62 \t\t|\t 8100 \t|\n|\t 2.16 \t\t|\t 10800 \t|\n|\t 2.43 \t\t|\t 12150 \t|\n|\t 2.7 \t\t|\t 13500 \t|\n|\t 3.24 \t\t|\t 16200 \t|\n|\t 3.78 \t\t|\t 18900 \t|\n|\t 4.32 \t\t|\t 21600 \t|\n|\t 5.4 \t\t|\t 27000 \t|\n|\t 6.48 \t\t|\t 32400 \t|\n|\t 6.75 \t\t|\t 33750 \t|\n|\t 8.1 \t\t|\t 40500 \t|\n", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Panel Color Depth: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Panel_Color_Depth_10" + ], + "HelpText": "This feature specifies the color depth of eDP panel used.", + "WidgetValues": [ + { + "Key": "18-bit Color Depth", + "Value": "0" + }, + { + "Key": "24-bit Color Depth", + "Value": "1" + }, + { + "Key": "30-bit Color Depth", + "Value": "2" + }, + { + "Key": "36-bit Color Depth", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Select VSwing/Pre-Emphasis table : ", + "Visibility": "", + "Data": [ + "27", + "eDP_VswingPreEmph_10" + ], + "HelpText": "This feature selects the VSwing Pre-Emphasis setting table to be used. For Tigerlake, based on the selection respective table will be used.\nTables for Tigerlake:\nLow Power VSwing Pre-Emphasis Setting Table:\nFor HBR2:\n\t\t\t\t\t\t Pre-Emphasis (db)\n\t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\nVoltage \t\t Level-0/200mV \t\t 200mV, 0.0db \t\t 200mV, 1.9db \t\t 200mV, 3.5db \t\t 200mV, 4.9db\nSwing \t\t Level-1/250mV \t\t 250mV, 0.0db \t\t 250mV, 1.6db \t\t 250mV, 2.9db \t\t N/A\n(mV) \t\t Level-2/300mV \t\t 300mV, 0.0db \t\t 300mV, 1.3db \t\t N/A \t\t N/A\n\t\t Level-3/350mV \t\t 350mV, 0.0db \t\t N/A \t\t N/A \t\t N/A\n\n\nFor HBR3:\n\t\t\t\t\t\t Pre-Emphasis (db)\n\t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\nVoltage \t\t Level-0/350mV \t\t 350mV, 0.0db \t\t 350mV, 3.1db \t\t 350mV, 6.0db \t\t 350mV, 8.2db\nSwing \t\t Level-1/500mV \t\t 500mV, 0.0db \t\t 500mV, 2.9db \t\t 500mV, 5.1db \t\t N/A\n(mV) \t\t Level-2/650mV \t\t 650mV, 0.6db \t\t 600mV, 3.5db \t\t N/A \t\t N/A\n\t\t Level-3/900mV \t\t 900mV, 0.0db \t\t N/A \t\t N/A \t\t N/A\n\n\nDefault VSwing Pre-Emphasis Setting Table:\nFor HBR:\n\t\t\t\t\t\t Pre-Emphasis (db)\n\t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\nVoltage \t\t Level-0/350mV \t\t 350mV, 0.0db \t\t 350mV, 3.1db \t\t 350mV, 6.0db \t\t 350mV, 8.2db\nSwing \t\t Level-1/500mV \t\t 500mV, 0.0db \t\t 500mV, 2.9db \t\t 500mV, 5.1db \t\t N/A\n(mV) \t\t Level-2/650mV \t\t 650mV, 0.6db \t\t 600mV, 3.5db \t\t N/A \t\t N/A\n\t\t Level-3/900mV \t\t 900mV, 0.0db \t\t N/A \t\t N/A \t\t N/A\n\n\nFor HBR2:\n\t\t\t\t\t\t Pre-Emphasis (db)\n\t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\nVoltage \t\t Level-0/350mV \t\t 350mV, 0.0db \t\t 350mV, 3.1db \t\t 350mV, 6.0db \t\t 350mV, 8.2db\nSwing \t\t Level-1/500mV \t\t 500mV, 0.0db \t\t 500mV, 2.9db \t\t 500mV, 5.1db \t\t N/A\n(mV) \t\t Level-2/650mV \t\t 650mV, 0.6db \t\t 600mV, 3.5db \t\t N/A \t\t N/A\n\t\t Level-3/900mV \t\t 900mV, 0.0db \t\t N/A \t\t N/A \t\t N/A", + "WidgetValues": [ + { + "Key": "Default VSwing/Pre-Emphasis Table", + "Value": "1" + }, + { + "Key": "Low Power VSwing/Pre-Emphasis Table", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " eDP Spread Spectrum Clock: ", + "Visibility": "", + "Data": [ + "40", + "Enable_SSC10" + ], + "HelpText": "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Pixel Overlap Count: ", + "Visibility": "", + "Data": [ + "42", + "PixelOverlapCount_10" + ], + "HelpText": "Select the number of Pixels to be overlapped per half of Scanline while using Edp Multi-SST(MSO) feature.", + "WidgetValues": [ + { + "Key": "Zero Pixel Overlap", + "Value": "0" + }, + { + "Key": "One Pixel Overlap", + "Value": "1" + }, + { + "Key": "Two Pixel Overlap", + "Value": "2" + }, + { + "Key": "Three Pixel Overlap", + "Value": "3" + }, + { + "Key": "Four Pixel Overlap", + "Value": "4" + }, + { + "Key": "Five Pixel Overlap", + "Value": "5" + }, + { + "Key": "Six Pixel Overlap", + "Value": "6" + }, + { + "Key": "Seven Pixel Overlap", + "Value": "7" + }, + { + "Key": "Eight Pixel Overlap", + "Value": "8" + } + ] + }, + { + "WidgetType": "Button", + "WidgetName": "PSR Feature", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Apical Feature", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + } + ], + "NestedPages": [ + { + "Type": "Block", + "Block": { + "PageNum": "5-2-10-1", + "PageName": "eDP Panel Power Sequencing Parameters", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " T3 optimization: ", + "Visibility": "", + "Data": [ + "27", + "eDP_T3_Optimization_10" + ], + "HelpText": "This feature enables or disables T3 optimization.\nWhen enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\nWhen disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "LCDVCC to HPD high delay (T3): ", + "Visibility": "", + "Data": [ + "27", + "eDP_Vcc_To_Hpd_Delay_10" + ], + "HelpText": "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\nValid Range: 0 to 200msec", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Valid video data to Backlight Enable delay (T8): ", + "Visibility": "", + "Data": [ + "27", + "eDP_DataOn_To_BkltEnable_Delay_10" + ], + "HelpText": "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\nT8 is inclusive of T7.\nValid Range of T7: 0 to 50msec", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "PWM-On To Backlight Enable delay: ", + "Visibility": "", + "Data": [ + "27", + "eDP_PwmOn_To_Bklt_Enable_Delay_10" + ], + "HelpText": "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\nDelay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\nSo it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Backlight Disable to PWM-Off delay: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Bklt_Disable_To_PwmOff_Delay_10" + ], + "HelpText": "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\nDelay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\nSo it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Backlight Disable to End of Valid video data delay (T9): ", + "Visibility": "", + "Data": [ + "27", + "eDP_BkltDisable_To_DataOff_Delay_10" + ], + "HelpText": "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "End of Valid video data to Power-Off delay (T10): ", + "Visibility": "", + "Data": [ + "27", + "eDP_DataOff_To_PowerOff_Delay_10" + ], + "HelpText": "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\nValid Range: 0 to 500 msec", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Power-off time (T12): ", + "Visibility": "", + "Data": [ + "27", + "eDP_PowerCycle_Delay_10" + ], + "HelpText": "Using this field Power-off time can be specified in 100uS.", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-10-2", + "PageName": "eDP Fast Link Training Configuration Parameters", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Is FastLinkTraining Feature Supported: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Fast_Link_Training_Supported_10" + ], + "HelpText": "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled.", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Data Rate: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Fast_Link_Training_Data_Rate_10" + ], + "HelpText": "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. It will be used if the sink indicates that no aux handshake is required during link training.\n\nIn case of EDP Fast Link Training Params(FLT), if user enters FLT Link Rate value greater than the \"eDP Max Port Link Rate\" then driver would use \n Fast Link training Link Rate = MIN (FLT Link Rate , eDP Max Port Link Rate).", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Lane Count: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Link_LaneCount_10" + ], + "HelpText": "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. It will be used if the sink indicates that no aux handshake is required during link training.", + "WidgetValues": [ + { + "Key": "x1", + "Value": "0" + }, + { + "Key": "x2", + "Value": "1" + }, + { + "Key": "x4", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Pre-Emphasis: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Link_PreEmp_10" + ], + "HelpText": "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. It will be used if the sink indicates that no aux handshake is required during link training.", + "WidgetValues": [ + { + "Key": "Level-0", + "Value": "0" + }, + { + "Key": "Level-1", + "Value": "1" + }, + { + "Key": "Level-2", + "Value": "2" + }, + { + "Key": "Level-3", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Voltage Swing: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Link_Vswing_10" + ], + "HelpText": "This feature allows for the selection of the Voltage Swing value for the embedded DP link. It will be used if the sink indicates that no aux handshake is required during link training.", + "WidgetValues": [ + { + "Key": "Swing-0", + "Value": "0" + }, + { + "Key": "Swing-1", + "Value": "1" + }, + { + "Key": "Swing-2", + "Value": "2" + }, + { + "Key": "Swing-3", + "Value": "3" + } + ] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-10-3", + "PageName": "PSR Feature", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Full Link enable: ", + "Visibility": "", + "Data": [ + "9", + "PSR_FullLink_Enable_10" + ], + "HelpText": "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state.", + "WidgetValues": [ + { + "Key": "No", + "Value": "0" + }, + { + "Key": "Yes", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Require AUX to wake up: ", + "Visibility": "", + "Data": [ + "9", + "PSR_Require_AUX2Wakeup_10" + ], + "HelpText": "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used.", + "WidgetValues": [ + { + "Key": "No", + "Value": "0" + }, + { + "Key": "Yes", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Lines to wait before link standby: ", + "Visibility": "", + "Data": [ + "9", + "PSR_Lines2Wait_B4LinkS3_10" + ], + "HelpText": "This field determines Lines to wait before link standby\n0 lines to wait (Default)\n1 lines to wait\n4 lines to wait\n8 lines to wait\nOthers Reserved", + "WidgetValues": [ + { + "Key": "0 lines to wait", + "Value": "0" + }, + { + "Key": "1 lines to wait", + "Value": "1" + }, + { + "Key": "4 lines to wait", + "Value": "2" + }, + { + "Key": "8 lines to wait", + "Value": "3" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Idle frames to wait: ", + "Visibility": "", + "Data": [ + "9", + "PSR_IdleFrames2Wait_10" + ], + "HelpText": "Idle frames to wait for PSR enable.\nAllowed values 0-15. Default value is 0.", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Clock Recovery Time: ", + "Visibility": "", + "Data": [ + "9", + "PSR_TP1_WaitTime_10" + ], + "HelpText": "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)", + "WidgetValues": [ + { + "Key": "500 usec", + "Value": "0" + }, + { + "Key": "100 usec", + "Value": "1" + }, + { + "Key": "2.5 msec", + "Value": "2" + }, + { + "Key": "0 (Skip)", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Channel Equalization Time for PSR1 panel: ", + "Visibility": "", + "Data": [ + "9", + "PSR1_TP_2_3_4_WaitTime_10" + ], + "HelpText": "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) or TP4(Training Pattern4) time during PSR1 exit(wake up)", + "WidgetValues": [ + { + "Key": "500 usec", + "Value": "0" + }, + { + "Key": "100 usec", + "Value": "1" + }, + { + "Key": "2.5 msec", + "Value": "2" + }, + { + "Key": "0 (Skip)", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Channel Equalization Time for PSR2 panel: ", + "Visibility": "", + "Data": [ + "9", + "PSR2_TP_2_3_4_WaitTime_10" + ], + "HelpText": "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) or TP4(Training Pattern4) time during PSR2 exit(wake up)", + "WidgetValues": [ + { + "Key": "500 usec", + "Value": "0" + }, + { + "Key": "100 usec", + "Value": "1" + }, + { + "Key": "2.5 msec", + "Value": "2" + }, + { + "Key": "50 usec", + "Value": "3" + } + ] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-10-4", + "PageName": "Apical Feature", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Apical Assertive Display IP: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Apical_Display_Ip_Enable_10" + ], + "HelpText": "This field enables/disables the Apical Assertive Display IP for this panel.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Panel OUI (IEEE OUI): ", + "Visibility": "", + "Data": [ + "27", + "eDP_Panel_Oui_10" + ], + "HelpText": "This field specifies the Apical IP specific Panel OUI field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " DPCD Base Address: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Dpcd_Base_Address_10" + ], + "HelpText": "This field specifies the Apical IP specific DPCD base address field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " DPCD Irdidix Control 0: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Dpcd_Irdidix_Control0_10" + ], + "HelpText": "This field specifies the Apical IP specific DPCD Irdidix control 0 field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " DPCD Option Select: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Dpcd_Option_Select_10" + ], + "HelpText": "This field specifies the Apical IP specific DPCD option select field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " DPCD Backlight: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Dpcd_Backlight_10" + ], + "HelpText": "This field specifies the Apical IP specific backlight value.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Ambient Light: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Ambient_Light_10" + ], + "HelpText": "This field specifies the Apical IP specific Ambient light value.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Backlight scale: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Backlight_Scale_10" + ], + "HelpText": "This field specifies the Apical IP specific backlight scale field.", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-10-5", + "PageName": "Power Features", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Intel Display Power Saving Technology (DPST) (Mobile only): ", + "Visibility": "", + "Data": [ + "44", + "DPST_Enable_10" + ], + "HelpText": "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled.\nIntel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power.\nNote: This technology is only active when the system is running in battery mode and the LFP is the only active display device.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Intel Display Refresh Rate Switching (DRRS) (Mobile only): ", + "Visibility": "", + "Data": [ + "44", + "DRRS_Enable_10" + ], + "HelpText": "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Edge Luminance Profile (ELP) : ", + "Visibility": "", + "Data": [ + "44", + "ELP_Enable_10" + ], + "HelpText": "This feature determines whether the ELP feature is enabled or disabled.\nEdge Luminance Profile (ELP) is a panel technology which reduce luminance on the edge of screen to save panel power.\nNote:This technology cannot co-exist with DPST and OPST ((i.e.) OPST, DPST and ELP cannot exist together.They are all mutually exclusive to each other.)", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " OLED Power Saving Technology (OPST) : ", + "Visibility": "", + "Data": [ + "44", + "OPST_Enable_10" + ], + "HelpText": "This feature determines whether the OPST feature is enabled or disabled.\nOLED Power Saving Technology (OPST) is a panel technology which saves power by intelligent, adaptive dimming of midrange pixel values more aggressively than the extremes without compromising the viewability.\nNote: This technology cannot co-exist with ELP and DPST ((i.e.) OPST, DPST and ELP cannot exist together.They are all mutually exclusive to each other.)", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Dynamic Media Refresh Rate Switching Enable/Disable ", + "Visibility": "", + "Data": [ + "44", + "DMRRS_Enable_10" + ], + "HelpText": "This feature determines whether Dynamic media refresh rate switching is to be enabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Enable Display Lace Support: ", + "Visibility": "", + "Data": [ + "44", + "LACE_Enable_10" + ], + "HelpText": "This feature, when enabled, will set Display Lace Support otherwise, the functionality will be disabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Panel Self Refresh (PSR): ", + "Visibility": "", + "Data": [ + "44", + "PSR_Enable_10" + ], + "HelpText": "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Assertive Display Technology Enable/Disable: ", + "Visibility": "", + "Data": [ + "44", + "ADT_Enable_10" + ], + "HelpText": "This feature determines whether Assertive display technology is to be enabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Intel Automatic Display Brightness (ADB) (Mobile only): ", + "Visibility": "", + "Data": [ + "44", + "ADB_Enable_10" + ], + "HelpText": "This feature determines whether Intel Automatic Display Brightness is to be enabled. Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) depending on the current ambient light environment.\nWhen enabled, the driver and VBIOS will control the backlight brightness of the LFP depending on the ambient environment if and only if the LFP is the only active display. When disabled, the driver will perform no action.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "EDP 4k/2k HOBL Feature: ", + "Visibility": "", + "Data": [ + "44", + "eDP_4k_2k_HOBL_feature_Enable_10" + ], + "HelpText": "This feature will allow users to disable/enable the edp 4k/2k HOBL(Hours Of Battery Life) feature by programming relevant registers specific for a platform.\r\n.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Default Display LACE Enabled status: ", + "Visibility": "", + "Data": [ + "44", + "LACE_Status_10" + ], + "HelpText": "This feature, when enabled, will set Default Display LACE Enabled status otherwise, the functionality will be disabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "DPST Aggressiveness Level: ", + "Visibility": "", + "Data": [ + "44", + "DPST_Aggressiveness_Profile_10" + ], + "HelpText": "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n1 (Maximum Quality with No DPST)\n2\n3\n4\n5\n6 (Maximum Battery)", + "WidgetValues": [ + { + "Key": "1 - Maximum Quality with No DPST", + "Value": "1" + }, + { + "Key": "2", + "Value": "2" + }, + { + "Key": "3", + "Value": "3" + }, + { + "Key": "4", + "Value": "4" + }, + { + "Key": "5", + "Value": "5" + }, + { + "Key": "6 - Maximum Battery", + "Value": "6" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "LACE Aggressiveness Level: ", + "Visibility": "", + "Data": [ + "44", + "LACE_Aggressiveness_Profile_10" + ], + "HelpText": "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\nMinimum 0\nModerate 1\nHigh 2", + "WidgetValues": [ + { + "Key": "Minimum", + "Value": "0" + }, + { + "Key": "Moderate", + "Value": "1" + }, + { + "Key": "High", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "ELP Aggressiveness Level: ", + "Visibility": "", + "Data": [ + "44", + "ELP_Aggressiveness_Profile_10" + ], + "HelpText": "This feature allows for the selection of ELP Aggressiveness level for this Panel Type.\nMinimum Power Savings\nMedium Power Savings \nMaximum Power Savings", + "WidgetValues": [ + { + "Key": "Minimum Power Savings", + "Value": "0" + }, + { + "Key": "Medium Power Savings", + "Value": "1" + }, + { + "Key": "Maximum Power Savings", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "OPST Aggressiveness Level: ", + "Visibility": "", + "Data": [ + "44", + "OPST_Aggressiveness_Profile_10" + ], + "HelpText": "This feature allows for the selection of OPST Aggressiveness level for this Panel Type.\nMinimum Power Savings\nMedium Power Savings \nMaximum Power Savings", + "WidgetValues": [ + { + "Key": "Minimum Power Savings", + "Value": "0" + }, + { + "Key": "Medium Power Savings", + "Value": "1" + }, + { + "Key": "Maximum Power Savings", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Default Display VRR Enabled status: ", + "Visibility": "", + "Data": [ + "44", + "VRR_Status_10" + ], + "HelpText": "VRR (Variable Refresh Rate) is a feature that can continuously and seamlessly vary Refresh Rate on the fly, on displays that support Variable Refresh rate Technologies.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-10-6", + "PageName": "Generic DTD Timings", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Pixel Clock in KHz: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_Pixel_CLK_10" + ], + "HelpText": "Pixel Clock (in KHz) Range from 0.001 to 4294967.295 MP/s.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Active: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_Active_10" + ], + "HelpText": "Horizontal Active Image Pixels Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Active: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_Active_10" + ], + "HelpText": "Vertical Active Image Lines Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Blank: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_Blank_10" + ], + "HelpText": "Horizontal Blank Pixels Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Blank: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_Blank_10" + ], + "HelpText": "Vertical Blank lines Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Front Porch: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_FrontPorch_10" + ], + "HelpText": "Horizontal Front Porch Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Front Porch: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_FrontPorch_10" + ], + "HelpText": "Vertical Front Porch Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Sync: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_Sync_10" + ], + "HelpText": "Horizontal Sync Width Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Sync: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_Sync_10" + ], + "HelpText": "Vertical Sync Width Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Image Size: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_Image_Size_10" + ], + "HelpText": "Horizontal Addressable Video Image Size in mm represented by 16bits. Image size multiplier 1.00 mm precision.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Image Size: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_Image_Size_10" + ], + "HelpText": "Vertical Addressable Video Image Size in mm represented by 16bits. Image size multiplier 1.00 mm precision.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryBin", + "WidgetName": "Common Flag: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_Common_Flag_10" + ], + "HelpText": "Common DTD Flags:\nBit 7 : Horizontal Sync Polarity\n1 : Positive\n0 : Negative\nBit 6 : Vertical Sync polarity\n1 : Positive\n0 : Negative\nBit 5 - 0: Reserved (Default value 0)", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-10-7", + "PageName": "LFP PnP ID Table", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Table", + "WidgetName": "", + "Visibility": "", + "Data": [ + "42", + "LFP_Panel_PnP_ID_10" + ], + "HelpText": "This feature allows the 10 bytes of EDID Vendor/Product ID starting at offset 08h to be used as a PnP ID.\n\nTable Definition:\n\tWord: ID Manufacturer Name\n\tWord: ID Product Code\n\tDWord: ID Serial Number\n\tByte: Week of Manufacture\n\tByte: Year of Manufacture", + "WidgetValues": [ + { + "ColumnName": "PnP ID", + "SizeinBytes": "1" + } + ] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-10-8", + "PageName": "Backlight Control Parameters", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Inverter Type: ", + "Visibility": "", + "Data": [ + "43", + "BLC_Inv_Type_10" + ], + "HelpText": "This feature allows for the selection of the Backlight Inverter type that is to be used to control the backlight brightness of the LFP.\nWhen PWM is selected, the driver and VBIOS will control the backlight brightness via the integrated PWM solution for the applicable chipsets.\nWhen None/External is selected, the system BIOS will control the backlight brightness via the external solution.", + "WidgetValues": [ + { + "Key": "None/External", + "Value": "0" + }, + { + "Key": "PWM", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Pwm Source Selection: ", + "Visibility": "", + "Data": [ + "43", + "Lfp_Pwm_Source_Selection_10" + ], + "HelpText": "If panel supports 'Intel HDR AUX Interface', it will always be chosen by default. If not, value in 'PWM Source Selection' will be used", + "WidgetValues": [ + { + "Key": "PWM From Display Engine", + "Value": "2" + }, + { + "Key": "PWM From LCD Panel", + "Value": "3" + }, + { + "Key": "Panel Driver Interface", + "Value": "4" + }, + { + "Key": "VESA eDP AUX Interface", + "Value": "5" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Pwm Controller Selection: ", + "Visibility": "", + "Data": [ + "43", + "Lfp_Pwm_Controller_Selection_10" + ], + "HelpText": "This field allows to select the PWM Controller to be used for the selected Local Flat Panel.This field allows to select the PWM Controller to be used for the selected Local Flat Panel.If Two LFPs are connected then PWM0 and PWM1 must be selected accordingly.", + "WidgetValues": [ + { + "Key": "PWM0", + "Value": "0" + }, + { + "Key": "PWM1", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Inverter Polarity: ", + "Visibility": "", + "Data": [ + "43", + "BLC_Inv_Polarity_10" + ], + "HelpText": "This feature allows the backlight inverter polarity to be specified.\nNormal means 0 value is minimum brightness.\nInverted means 0 value is maximum brightness.", + "WidgetValues": [ + { + "Key": "Normal", + "Value": "0" + }, + { + "Key": "Inverted", + "Value": "1" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Minimum Brightness: ", + "Visibility": "", + "Data": [ + "43", + "Post_Min_Brightness_10" + ], + "HelpText": "This feature allows defining the absolute minimum backlight brightness. The driver will never decrease the backlight less than this value. The value must be specified using normal polarity semantics. The value should range from 0 to 255 if the brightness precision bit is chosen to be 8, and it should range from 0 to 65535 if the precision bit is chosen to be 16.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "POST Backlight Intensity: ", + "Visibility": "", + "Data": [ + "43", + "Post_Brightness_10" + ], + "HelpText": "This feature is used to set default backlight brightness value of the panel at POST. The value should range from 0 to 255 if the bit precision is chosen to be 8 and it should range from 0 to 65535 if the brightness bit precision is chosent to be 16.", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Brightness Precision Bits: ", + "Visibility": "", + "Data": [ + "43", + "BrightnessPrecisionBits_10" + ], + "HelpText": "This field represents the range of brightness in terms of bit precision.\n 8 = Brightness range of 0 to 255.\n 16 = Brightness range of 0 to 65535", + "WidgetValues": [ + { + "Key": "8", + "Value": "8" + }, + { + "Key": "16", + "Value": "16" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "PWM Inverter Frequency (Hz): ", + "Visibility": "", + "Data": [ + "43", + "PWM_Frequency_10" + ], + "HelpText": "This feature allows for the definition of the frequency needed for PWM Inverter.\nNote: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Intel HDR DPCD Refresh Timeout (unit - 10 micro seconds): ", + "Visibility": "", + "Data": [ + "43", + "HdrDpcdRefreshTimeout_10" + ], + "HelpText": "This field allows to configure the refresh timeout of Intel HDR DPCDs for different TCON Vendors.\nNote:\n\tThe value is in units of 10 microseconds.\n\tThe range (entered as a decimal number), for the timeout is 0-65535", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-10-9", + "PageName": "Chromaticity Control", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Chromaticity Control Feature: ", + "Visibility": "", + "Data": [ + "46", + "Chromacity_Enable_10" + ], + "HelpText": "This bit enables Chromaticity feature.\nIf this bit is enabled, EDID values for chromaticity will be used, else feature is disabled.\nFeature will be supported for Panels that support EDID version 1.4 or higher.\nPlease refer to section 3.7 of EDID Specification 1.4.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Override the EDID values: ", + "Visibility": "", + "Data": [ + "46", + "Override_EDID_Data_10" + ], + "HelpText": "This option when enabled along with Chromaticity feature will override EDID values through following VBT data", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Red_Green_bits (Bits 1:0 at 19h): ", + "Visibility": "", + "Data": [ + "46", + "Red_Green_10" + ], + "HelpText": "Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Blue_White_bits (Bits 1:0 at 1Ah): ", + "Visibility": "", + "Data": [ + "46", + "Blue_White_10" + ], + "HelpText": "Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Red_x (Bits 9:2 at 1Bh): ", + "Visibility": "", + "Data": [ + "46", + "Red_x_10" + ], + "HelpText": "Bits 9:2 of red color x coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Red_y (Bits 9:2 at 1Ch): ", + "Visibility": "", + "Data": [ + "46", + "Red_y_10" + ], + "HelpText": "Bits 9:2 of red color y coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Green_x (Bits 9:2 at 1Dh): ", + "Visibility": "", + "Data": [ + "46", + "Green_x_10" + ], + "HelpText": "Bits 9:2 of Green color x coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Green_y (Bits 9:2 at 1Eh): ", + "Visibility": "", + "Data": [ + "46", + "Green_y_10" + ], + "HelpText": "Bits 9:2 of Green color y coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Blue_x (Bits 9:2 at 1Fh): ", + "Visibility": "", + "Data": [ + "46", + "Blue_x_10" + ], + "HelpText": "Bits 9:2 of Blue color x coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Blue_y (Bits 9:2 at 20h): ", + "Visibility": "", + "Data": [ + "46", + "Blue_y_10" + ], + "HelpText": "Bits 9:2 of Blue color y coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " White_x (Bits 9:2 at 21h): ", + "Visibility": "", + "Data": [ + "46", + "White_x_10" + ], + "HelpText": "Bits 9:2 of White color x coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " White_y (Bits 9:2 at 22h): ", + "Visibility": "", + "Data": [ + "46", + "White_y_10" + ], + "HelpText": "Bits 9:2 of White color y coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Override Luminance values ", + "Visibility": "", + "Data": [ + "46", + "Override_LUM_Data_10" + ], + "HelpText": "This option when enabled along with Chromaticity feature will override luminance values following VBT values", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Minimum Luminance: ", + "Visibility": "", + "Data": [ + "46", + "MinLuminance_10" + ], + "HelpText": "Minimum luminance value.\n2 byte value, encoded in IEEE 754 half-precision binary floating point format,", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Maximum full frame luminance: ", + "Visibility": "", + "Data": [ + "46", + "MaxFullLuminance_10" + ], + "HelpText": "Maximum Full frame luminance value.\n2 byte value, encoded in IEEE 754 half-precision binary floating point format,", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Maximum Luminance: ", + "Visibility": "", + "Data": [ + "46", + "MaxLuminance_10" + ], + "HelpText": "Maximum luminance value(Relatively smaller portion of screen).\n2 byte value, encoded in IEEE 754 half-precision binary floating point format.", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Override Gamma values: ", + "Visibility": "", + "Data": [ + "46", + "Override_Gamma_Data_10" + ], + "HelpText": "This option when enabled along with Chromaticity feature will override gamma values through following VBT data", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Panel gamma: ", + "Visibility": "", + "Data": [ + "46", + "Gamma_10" + ], + "HelpText": "Value shall define the gamma range, from 1.00 to 3.54, as follows:\nField Value = (Gamma (value in float) x 100) - 100\nField values range from 00h through FFh.\nFFh = No gamma information shall be provided", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-10-10", + "PageName": "VESA DSC Parameters", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "DSC Major Version: ", + "Visibility": "", + "Data": [ + "56", + "C10_Major_Dsc_Version" + ], + "HelpText": "VESA DSC Major revision field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "DSC Minor Version: ", + "Visibility": "", + "Data": [ + "56", + "C10_Minor_Dsc_Version" + ], + "HelpText": "VESA DSC Minor revision field.", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Block prediction supported: ", + "Visibility": "", + "Data": [ + "56", + "C10_Blk_Prediction_En" + ], + "HelpText": "Sink supports block prediction as per the VESA DSC Spec.", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "RC Buffer Block size as per VESA DSC Spec: ", + "Visibility": "", + "Data": [ + "56", + "C10_RC_Block_Size" + ], + "HelpText": "RC buffer block size for a single RC buffer as defined by the VESA DSC spec.", + "WidgetValues": [ + { + "Key": "1 KB", + "Value": "0" + }, + { + "Key": "4 KB", + "Value": "1" + }, + { + "Key": "16 KB", + "Value": "2" + }, + { + "Key": "64 KB", + "Value": "3" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Number of RC buffer blocks as per VESA DSC Spec: ", + "Visibility": "", + "Data": [ + "56", + "C10_Dsc_RC_Buf_Size" + ], + "HelpText": "This field defines the number of RC buffers as per VESA DSC spec.\nThe number of RC buffers used by the software shall be (Value + 1) where Value is in range 0 to 127.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryBin", + "WidgetName": "Slices per line supported by the sink device: ", + "Visibility": "", + "Data": [ + "56", + "C10_Dsc_Slices_Per_Line" + ], + "HelpText": "This field defines the slices per line supported by the sink device.\nThe field is defined in bitmap fashion and details of each bits are as defined below:\n\tBits 31-10\t\t Bit 9\tBit 8\tBit 7\tBit 6\tBit 5\tBit 4\t Bit 3\t Bit 2\t Bit 1\t Bit 0\n\tReserved\t\t 24\t 20\t 16\t 12\t 10\t 8\t 6\t 4\t 2\t 1\nBit = 0, not supported. Bit = 1, supported\nNote: Assumption is that sink shall support all lower slices per line than maximum selected field. i.e. If it supports say 8 slices per line, it will also support 4/2/1 slices per line", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Line buffer depth as per VESA DSC Spec: ", + "Visibility": "", + "Data": [ + "56", + "C10_Line_Buffer_Depth" + ], + "HelpText": "Line buffer depth in bits as per VESA DSC spec.", + "WidgetValues": [ + { + "Key": "8 bits", + "Value": "0" + }, + { + "Key": "9 bits", + "Value": "1" + }, + { + "Key": "10 bits", + "Value": "2" + }, + { + "Key": "11 bits", + "Value": "3" + }, + { + "Key": "12 bits", + "Value": "4" + }, + { + "Key": "13 bits", + "Value": "5" + }, + { + "Key": "14 bits", + "Value": "6" + }, + { + "Key": "15 bits", + "Value": "7" + }, + { + "Key": "16 bits", + "Value": "8" + } + ] + }, + { + "WidgetType": "EntryBin", + "WidgetName": "Input compression BPC supported by the sink device: ", + "Visibility": "", + "Data": [ + "56", + "C10_Dsc_Bpc" + ], + "HelpText": "This field defines the compression input bpc supported by the sink device.\nThe field is defined in bitmap fashion and details of each bits are as defined below:\n\tBits 7-4\t Bit 3\t Bit 2\t Bit 1\t Bit 0\n\tRsvd\t 12 bpc\t 10bpc\t 8bpc\t Rsvd\nBit = 0, not supported. Bit = 1, supported\nNote: Assumption is that sink shall support all lower bpc values than the maximum selected field. i.e. If it supports say 12bpc, it will also support 10 and 8bpc as well", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Maximum supported compression BPP: ", + "Visibility": "", + "Data": [ + "56", + "C10_Dsc_Max_Bpp" + ], + "HelpText": "As of today, we are supporting 6/8/10/12 BPP for compression output.\nSelect the most appropriate BPP as supported by the sink.", + "WidgetValues": [ + { + "Key": "6 Bits per pixel", + "Value": "0" + }, + { + "Key": "8 Bits per pixel", + "Value": "1" + }, + { + "Key": "10 Bits per pixel", + "Value": "2" + }, + { + "Key": "12 Bits per pixel", + "Value": "3" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Slice height supported by the sink device: ", + "Visibility": "", + "Data": [ + "56", + "C10_Dsc_Slice_Height" + ], + "HelpText": "Slice height supported by the sink device for DSC slice.\nNote: Slice height must divide the picture height uniformly.", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + } + ] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-11", + "PageName": "Panel #11", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "LabelHeading", + "WidgetName": "Common LFP Features", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryAsci", + "WidgetName": " LFP Panel Name: ", + "Visibility": "", + "Data": [ + "42", + "Panel_Name_11" + ], + "HelpText": "This feature defines the LFP panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Target X-Res: ", + "Visibility": "", + "Data": [ + "42", + "Panel_Width_11" + ], + "HelpText": "This value specifies the Target X-Resolution for this panel.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Target Y-Res: ", + "Visibility": "", + "Data": [ + "42", + "Panel_Height_11" + ], + "HelpText": "This value specifies the Target Y-Resolution for this panel.", + "WidgetValues": [] + }, + { + "WidgetType": "LabelHeading", + "WidgetName": " DPS Panel Type Features", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Seamless DRRS Minimum Refresh Rate (Hz): ", + "Visibility": "", + "Data": [ + "42", + "Seamless_DRRS_Min_RR_11" + ], + "HelpText": "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\nNote: Graphics driver will use this field only when EDID support is disabled in VBT configuration.", + "WidgetValues": [] + }, + { + "WidgetType": "LabelHeading", + "WidgetName": " BackLight Technology Type Features", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " BackLight Technology: ", + "Visibility": "", + "Data": [ + "40", + "Blt_Control_11" + ], + "HelpText": "This feature allows OEM to select the Backlight Technology.", + "WidgetValues": [ + { + "Key": "LED Backlight", + "Value": "2" + }, + { + "Key": "CCFL Backlight", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Panel Rotation: ", + "Visibility": "", + "Data": [ + "40", + "Panel_Rotation_11" + ], + "HelpText": "This feature specifies the Panel Rotation of LFP panel used.", + "WidgetValues": [ + { + "Key": "0 degree", + "Value": "0" + }, + { + "Key": "180 degree", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Panel Position: ", + "Visibility": "", + "Data": [ + "40", + "Panel_Position_11" + ], + "HelpText": "This feature specifies the Panel Position of LFP panel used.", + "WidgetValues": [ + { + "Key": "Inside Shell", + "Value": "0" + }, + { + "Key": "Outside Shell", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Dual LFP Port Sync: ", + "Visibility": "", + "Data": [ + "42", + "EnablePortSync_Bit_11" + ], + "HelpText": "This feature will allow users to disable/enable Dual LFP Port Sync and it is applicable for DDI-A, DDI-B in case of eDP and DSI-0, DSI-1 in case of MIPI. \r\n.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " GPU Dithering for Banding artifacts: ", + "Visibility": "", + "Data": [ + "42", + "EnableDithering_Bit_11" + ], + "HelpText": "This field can be used to enable dithering from the source side for reducing banding artifacts on the visual quality features like DPST.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "Button", + "WidgetName": "Power Features", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Generic DTD Timings", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "LFP PnP ID Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Backlight Control Parameters", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Chromaticity Control", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "VESA DSC Parameters", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "LabelHeading", + "WidgetName": "Integrated eDP Settings", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "eDP Fast Link Training Configuration Parameters", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "eDP Panel Power Sequencing Parameters", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Edp Max Port Link Rate (in 200 Khz): ", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [ + "27", + "eDP_Max_Port_Link_Rate_11" + ], + "HelpText": "This field specifies EDP Max Port Link Rate supported by the port in unit of 200KHz.\nDefault value would be \"0\", in which case Display Drivers should consider EDP Max Port Link Rate to be the Platform supported Max Link Rate.\nOnly when OEM's need to limit to particular Link Rate can enter the value as mentioned in below table.\n\nNote:\n1) OEM's need to enter the values mentioned from below table only.\n2) If value entered is not matching with any of the below values then Platform supported Max Link Rate should be considere as EDP Max Port Link Rate by the display drivers.\n3) In case of EDP Fast Link Training Params(FLT), if user enters FLT Link Rate value greater than the \"eDP Max Port Link Rate\" then we need to use \n Fast Link training Link Rate = MIN (FLT Link Rate , eDP Max Port Link Rate)\n---------------------------------------------------------\n|\tLink Rate(Gbps)\t|\t Value to enter in text field\t|\n|\t \t\t|\t in terms of 200KHZ \t|\n---------------------------------------------------------\n|\t 1.62 \t\t|\t 8100 \t|\n|\t 2.16 \t\t|\t 10800 \t|\n|\t 2.43 \t\t|\t 12150 \t|\n|\t 2.7 \t\t|\t 13500 \t|\n|\t 3.24 \t\t|\t 16200 \t|\n|\t 3.78 \t\t|\t 18900 \t|\n|\t 4.32 \t\t|\t 21600 \t|\n|\t 5.4 \t\t|\t 27000 \t|\n|\t 6.48 \t\t|\t 32400 \t|\n|\t 6.75 \t\t|\t 33750 \t|\n|\t 8.1 \t\t|\t 40500 \t|\n", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Panel Color Depth: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Panel_Color_Depth_11" + ], + "HelpText": "This feature specifies the color depth of eDP panel used.", + "WidgetValues": [ + { + "Key": "18-bit Color Depth", + "Value": "0" + }, + { + "Key": "24-bit Color Depth", + "Value": "1" + }, + { + "Key": "30-bit Color Depth", + "Value": "2" + }, + { + "Key": "36-bit Color Depth", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Select VSwing/Pre-Emphasis table : ", + "Visibility": "", + "Data": [ + "27", + "eDP_VswingPreEmph_11" + ], + "HelpText": "This feature selects the VSwing Pre-Emphasis setting table to be used. For Tigerlake, based on the selection respective table will be used.\nTables for Tigerlake:\nLow Power VSwing Pre-Emphasis Setting Table:\nFor HBR2:\n\t\t\t\t\t\t Pre-Emphasis (db)\n\t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\nVoltage \t\t Level-0/200mV \t\t 200mV, 0.0db \t\t 200mV, 1.9db \t\t 200mV, 3.5db \t\t 200mV, 4.9db\nSwing \t\t Level-1/250mV \t\t 250mV, 0.0db \t\t 250mV, 1.6db \t\t 250mV, 2.9db \t\t N/A\n(mV) \t\t Level-2/300mV \t\t 300mV, 0.0db \t\t 300mV, 1.3db \t\t N/A \t\t N/A\n\t\t Level-3/350mV \t\t 350mV, 0.0db \t\t N/A \t\t N/A \t\t N/A\n\n\nFor HBR3:\n\t\t\t\t\t\t Pre-Emphasis (db)\n\t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\nVoltage \t\t Level-0/350mV \t\t 350mV, 0.0db \t\t 350mV, 3.1db \t\t 350mV, 6.0db \t\t 350mV, 8.2db\nSwing \t\t Level-1/500mV \t\t 500mV, 0.0db \t\t 500mV, 2.9db \t\t 500mV, 5.1db \t\t N/A\n(mV) \t\t Level-2/650mV \t\t 650mV, 0.6db \t\t 600mV, 3.5db \t\t N/A \t\t N/A\n\t\t Level-3/900mV \t\t 900mV, 0.0db \t\t N/A \t\t N/A \t\t N/A\n\n\nDefault VSwing Pre-Emphasis Setting Table:\nFor HBR:\n\t\t\t\t\t\t Pre-Emphasis (db)\n\t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\nVoltage \t\t Level-0/350mV \t\t 350mV, 0.0db \t\t 350mV, 3.1db \t\t 350mV, 6.0db \t\t 350mV, 8.2db\nSwing \t\t Level-1/500mV \t\t 500mV, 0.0db \t\t 500mV, 2.9db \t\t 500mV, 5.1db \t\t N/A\n(mV) \t\t Level-2/650mV \t\t 650mV, 0.6db \t\t 600mV, 3.5db \t\t N/A \t\t N/A\n\t\t Level-3/900mV \t\t 900mV, 0.0db \t\t N/A \t\t N/A \t\t N/A\n\n\nFor HBR2:\n\t\t\t\t\t\t Pre-Emphasis (db)\n\t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\nVoltage \t\t Level-0/350mV \t\t 350mV, 0.0db \t\t 350mV, 3.1db \t\t 350mV, 6.0db \t\t 350mV, 8.2db\nSwing \t\t Level-1/500mV \t\t 500mV, 0.0db \t\t 500mV, 2.9db \t\t 500mV, 5.1db \t\t N/A\n(mV) \t\t Level-2/650mV \t\t 650mV, 0.6db \t\t 600mV, 3.5db \t\t N/A \t\t N/A\n\t\t Level-3/900mV \t\t 900mV, 0.0db \t\t N/A \t\t N/A \t\t N/A", + "WidgetValues": [ + { + "Key": "Default VSwing/Pre-Emphasis Table", + "Value": "1" + }, + { + "Key": "Low Power VSwing/Pre-Emphasis Table", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " eDP Spread Spectrum Clock: ", + "Visibility": "", + "Data": [ + "40", + "Enable_SSC11" + ], + "HelpText": "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Pixel Overlap Count: ", + "Visibility": "", + "Data": [ + "42", + "PixelOverlapCount_11" + ], + "HelpText": "Select the number of Pixels to be overlapped per half of Scanline while using Edp Multi-SST(MSO) feature.", + "WidgetValues": [ + { + "Key": "Zero Pixel Overlap", + "Value": "0" + }, + { + "Key": "One Pixel Overlap", + "Value": "1" + }, + { + "Key": "Two Pixel Overlap", + "Value": "2" + }, + { + "Key": "Three Pixel Overlap", + "Value": "3" + }, + { + "Key": "Four Pixel Overlap", + "Value": "4" + }, + { + "Key": "Five Pixel Overlap", + "Value": "5" + }, + { + "Key": "Six Pixel Overlap", + "Value": "6" + }, + { + "Key": "Seven Pixel Overlap", + "Value": "7" + }, + { + "Key": "Eight Pixel Overlap", + "Value": "8" + } + ] + }, + { + "WidgetType": "Button", + "WidgetName": "PSR Feature", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Apical Feature", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + } + ], + "NestedPages": [ + { + "Type": "Block", + "Block": { + "PageNum": "5-2-11-1", + "PageName": "eDP Panel Power Sequencing Parameters", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " T3 optimization: ", + "Visibility": "", + "Data": [ + "27", + "eDP_T3_Optimization_11" + ], + "HelpText": "This feature enables or disables T3 optimization.\nWhen enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\nWhen disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "LCDVCC to HPD high delay (T3): ", + "Visibility": "", + "Data": [ + "27", + "eDP_Vcc_To_Hpd_Delay_11" + ], + "HelpText": "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\nValid Range: 0 to 200msec", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Valid video data to Backlight Enable delay (T8): ", + "Visibility": "", + "Data": [ + "27", + "eDP_DataOn_To_BkltEnable_Delay_11" + ], + "HelpText": "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\nT8 is inclusive of T7.\nValid Range of T7: 0 to 50msec", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "PWM-On To Backlight Enable delay: ", + "Visibility": "", + "Data": [ + "27", + "eDP_PwmOn_To_Bklt_Enable_Delay_11" + ], + "HelpText": "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\nDelay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\nSo it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Backlight Disable to PWM-Off delay: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Bklt_Disable_To_PwmOff_Delay_11" + ], + "HelpText": "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\nDelay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\nSo it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Backlight Disable to End of Valid video data delay (T9): ", + "Visibility": "", + "Data": [ + "27", + "eDP_BkltDisable_To_DataOff_Delay_11" + ], + "HelpText": "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "End of Valid video data to Power-Off delay (T10): ", + "Visibility": "", + "Data": [ + "27", + "eDP_DataOff_To_PowerOff_Delay_11" + ], + "HelpText": "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\nValid Range: 0 to 500 msec", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Power-off time (T12): ", + "Visibility": "", + "Data": [ + "27", + "eDP_PowerCycle_Delay_11" + ], + "HelpText": "Using this field Power-off time can be specified in 100uS.", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-11-2", + "PageName": "eDP Fast Link Training Configuration Parameters", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Is FastLinkTraining Feature Supported: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Fast_Link_Training_Supported_11" + ], + "HelpText": "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled.", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Data Rate: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Fast_Link_Training_Data_Rate_11" + ], + "HelpText": "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. It will be used if the sink indicates that no aux handshake is required during link training.\n\nIn case of EDP Fast Link Training Params(FLT), if user enters FLT Link Rate value greater than the \"eDP Max Port Link Rate\" then driver would use \n Fast Link training Link Rate = MIN (FLT Link Rate , eDP Max Port Link Rate).", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Lane Count: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Link_LaneCount_11" + ], + "HelpText": "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. It will be used if the sink indicates that no aux handshake is required during link training.", + "WidgetValues": [ + { + "Key": "x1", + "Value": "0" + }, + { + "Key": "x2", + "Value": "1" + }, + { + "Key": "x4", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Pre-Emphasis: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Link_PreEmp_11" + ], + "HelpText": "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. It will be used if the sink indicates that no aux handshake is required during link training.", + "WidgetValues": [ + { + "Key": "Level-0", + "Value": "0" + }, + { + "Key": "Level-1", + "Value": "1" + }, + { + "Key": "Level-2", + "Value": "2" + }, + { + "Key": "Level-3", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Voltage Swing: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Link_Vswing_11" + ], + "HelpText": "This feature allows for the selection of the Voltage Swing value for the embedded DP link. It will be used if the sink indicates that no aux handshake is required during link training.", + "WidgetValues": [ + { + "Key": "Swing-0", + "Value": "0" + }, + { + "Key": "Swing-1", + "Value": "1" + }, + { + "Key": "Swing-2", + "Value": "2" + }, + { + "Key": "Swing-3", + "Value": "3" + } + ] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-11-3", + "PageName": "PSR Feature", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Full Link enable: ", + "Visibility": "", + "Data": [ + "9", + "PSR_FullLink_Enable_11" + ], + "HelpText": "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state.", + "WidgetValues": [ + { + "Key": "No", + "Value": "0" + }, + { + "Key": "Yes", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Require AUX to wake up: ", + "Visibility": "", + "Data": [ + "9", + "PSR_Require_AUX2Wakeup_11" + ], + "HelpText": "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used.", + "WidgetValues": [ + { + "Key": "No", + "Value": "0" + }, + { + "Key": "Yes", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Lines to wait before link standby: ", + "Visibility": "", + "Data": [ + "9", + "PSR_Lines2Wait_B4LinkS3_11" + ], + "HelpText": "This field determines Lines to wait before link standby\n0 lines to wait (Default)\n1 lines to wait\n4 lines to wait\n8 lines to wait\nOthers Reserved", + "WidgetValues": [ + { + "Key": "0 lines to wait", + "Value": "0" + }, + { + "Key": "1 lines to wait", + "Value": "1" + }, + { + "Key": "4 lines to wait", + "Value": "2" + }, + { + "Key": "8 lines to wait", + "Value": "3" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Idle frames to wait: ", + "Visibility": "", + "Data": [ + "9", + "PSR_IdleFrames2Wait_11" + ], + "HelpText": "Idle frames to wait for PSR enable.\nAllowed values 0-15. Default value is 0.", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Clock Recovery Time: ", + "Visibility": "", + "Data": [ + "9", + "PSR_TP1_WaitTime_11" + ], + "HelpText": "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)", + "WidgetValues": [ + { + "Key": "500 usec", + "Value": "0" + }, + { + "Key": "100 usec", + "Value": "1" + }, + { + "Key": "2.5 msec", + "Value": "2" + }, + { + "Key": "0 (Skip)", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Channel Equalization Time for PSR1 panel: ", + "Visibility": "", + "Data": [ + "9", + "PSR1_TP_2_3_4_WaitTime_11" + ], + "HelpText": "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) or TP4(Training Pattern4) time during PSR1 exit(wake up)", + "WidgetValues": [ + { + "Key": "500 usec", + "Value": "0" + }, + { + "Key": "100 usec", + "Value": "1" + }, + { + "Key": "2.5 msec", + "Value": "2" + }, + { + "Key": "0 (Skip)", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Channel Equalization Time for PSR2 panel: ", + "Visibility": "", + "Data": [ + "9", + "PSR2_TP_2_3_4_WaitTime_11" + ], + "HelpText": "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) or TP4(Training Pattern4) time during PSR2 exit(wake up)", + "WidgetValues": [ + { + "Key": "500 usec", + "Value": "0" + }, + { + "Key": "100 usec", + "Value": "1" + }, + { + "Key": "2.5 msec", + "Value": "2" + }, + { + "Key": "50 usec", + "Value": "3" + } + ] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-11-4", + "PageName": "Apical Feature", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Apical Assertive Display IP: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Apical_Display_Ip_Enable_11" + ], + "HelpText": "This field enables/disables the Apical Assertive Display IP for this panel.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Panel OUI (IEEE OUI): ", + "Visibility": "", + "Data": [ + "27", + "eDP_Panel_Oui_11" + ], + "HelpText": "This field specifies the Apical IP specific Panel OUI field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " DPCD Base Address: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Dpcd_Base_Address_11" + ], + "HelpText": "This field specifies the Apical IP specific DPCD base address field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " DPCD Irdidix Control 0: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Dpcd_Irdidix_Control0_11" + ], + "HelpText": "This field specifies the Apical IP specific DPCD Irdidix control 0 field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " DPCD Option Select: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Dpcd_Option_Select_11" + ], + "HelpText": "This field specifies the Apical IP specific DPCD option select field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " DPCD Backlight: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Dpcd_Backlight_11" + ], + "HelpText": "This field specifies the Apical IP specific backlight value.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Ambient Light: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Ambient_Light_11" + ], + "HelpText": "This field specifies the Apical IP specific Ambient light value.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Backlight scale: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Backlight_Scale_11" + ], + "HelpText": "This field specifies the Apical IP specific backlight scale field.", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-11-5", + "PageName": "Power Features", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Intel Display Power Saving Technology (DPST) (Mobile only): ", + "Visibility": "", + "Data": [ + "44", + "DPST_Enable_11" + ], + "HelpText": "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled.\nIntel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power.\nNote: This technology is only active when the system is running in battery mode and the LFP is the only active display device.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Intel Display Refresh Rate Switching (DRRS) (Mobile only): ", + "Visibility": "", + "Data": [ + "44", + "DRRS_Enable_11" + ], + "HelpText": "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Edge Luminance Profile (ELP) : ", + "Visibility": "", + "Data": [ + "44", + "ELP_Enable_11" + ], + "HelpText": "This feature determines whether the ELP feature is enabled or disabled.\nEdge Luminance Profile (ELP) is a panel technology which reduce luminance on the edge of screen to save panel power.\nNote:This technology cannot co-exist with DPST and OPST ((i.e.) OPST, DPST and ELP cannot exist together.They are all mutually exclusive to each other.)", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " OLED Power Saving Technology (OPST) : ", + "Visibility": "", + "Data": [ + "44", + "OPST_Enable_11" + ], + "HelpText": "This feature determines whether the OPST feature is enabled or disabled.\nOLED Power Saving Technology (OPST) is a panel technology which saves power by intelligent, adaptive dimming of midrange pixel values more aggressively than the extremes without compromising the viewability.\nNote: This technology cannot co-exist with ELP and DPST ((i.e.) OPST, DPST and ELP cannot exist together.They are all mutually exclusive to each other.)", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Dynamic Media Refresh Rate Switching Enable/Disable ", + "Visibility": "", + "Data": [ + "44", + "DMRRS_Enable_11" + ], + "HelpText": "This feature determines whether Dynamic media refresh rate switching is to be enabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Enable Display Lace Support: ", + "Visibility": "", + "Data": [ + "44", + "LACE_Enable_11" + ], + "HelpText": "This feature, when enabled, will set Display Lace Support otherwise, the functionality will be disabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Panel Self Refresh (PSR): ", + "Visibility": "", + "Data": [ + "44", + "PSR_Enable_11" + ], + "HelpText": "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Assertive Display Technology Enable/Disable: ", + "Visibility": "", + "Data": [ + "44", + "ADT_Enable_11" + ], + "HelpText": "This feature determines whether Assertive display technology is to be enabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Intel Automatic Display Brightness (ADB) (Mobile only): ", + "Visibility": "", + "Data": [ + "44", + "ADB_Enable_11" + ], + "HelpText": "This feature determines whether Intel Automatic Display Brightness is to be enabled. Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) depending on the current ambient light environment.\nWhen enabled, the driver and VBIOS will control the backlight brightness of the LFP depending on the ambient environment if and only if the LFP is the only active display. When disabled, the driver will perform no action.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "EDP 4k/2k HOBL Feature: ", + "Visibility": "", + "Data": [ + "44", + "eDP_4k_2k_HOBL_feature_Enable_11" + ], + "HelpText": "This feature will allow users to disable/enable the edp 4k/2k HOBL(Hours Of Battery Life) feature by programming relevant registers specific for a platform.\r\n.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Default Display LACE Enabled status: ", + "Visibility": "", + "Data": [ + "44", + "LACE_Status_11" + ], + "HelpText": "This feature, when enabled, will set Default Display LACE Enabled status otherwise, the functionality will be disabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "DPST Aggressiveness Level: ", + "Visibility": "", + "Data": [ + "44", + "DPST_Aggressiveness_Profile_11" + ], + "HelpText": "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n1 (Maximum Quality with No DPST)\n2\n3\n4\n5\n6 (Maximum Battery)", + "WidgetValues": [ + { + "Key": "1 - Maximum Quality with No DPST", + "Value": "1" + }, + { + "Key": "2", + "Value": "2" + }, + { + "Key": "3", + "Value": "3" + }, + { + "Key": "4", + "Value": "4" + }, + { + "Key": "5", + "Value": "5" + }, + { + "Key": "6 - Maximum Battery", + "Value": "6" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "LACE Aggressiveness Level: ", + "Visibility": "", + "Data": [ + "44", + "LACE_Aggressiveness_Profile_11" + ], + "HelpText": "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\nMinimum 0\nModerate 1\nHigh 2", + "WidgetValues": [ + { + "Key": "Minimum", + "Value": "0" + }, + { + "Key": "Moderate", + "Value": "1" + }, + { + "Key": "High", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "ELP Aggressiveness Level: ", + "Visibility": "", + "Data": [ + "44", + "ELP_Aggressiveness_Profile_11" + ], + "HelpText": "This feature allows for the selection of ELP Aggressiveness level for this Panel Type.\nMinimum Power Savings\nMedium Power Savings \nMaximum Power Savings", + "WidgetValues": [ + { + "Key": "Minimum Power Savings", + "Value": "0" + }, + { + "Key": "Medium Power Savings", + "Value": "1" + }, + { + "Key": "Maximum Power Savings", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "OPST Aggressiveness Level: ", + "Visibility": "", + "Data": [ + "44", + "OPST_Aggressiveness_Profile_11" + ], + "HelpText": "This feature allows for the selection of OPST Aggressiveness level for this Panel Type.\nMinimum Power Savings\nMedium Power Savings \nMaximum Power Savings", + "WidgetValues": [ + { + "Key": "Minimum Power Savings", + "Value": "0" + }, + { + "Key": "Medium Power Savings", + "Value": "1" + }, + { + "Key": "Maximum Power Savings", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Default Display VRR Enabled status: ", + "Visibility": "", + "Data": [ + "44", + "VRR_Status_11" + ], + "HelpText": "VRR (Variable Refresh Rate) is a feature that can continuously and seamlessly vary Refresh Rate on the fly, on displays that support Variable Refresh rate Technologies.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-11-6", + "PageName": "Generic DTD Timings", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Pixel Clock in KHz: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_Pixel_CLK_11" + ], + "HelpText": "Pixel Clock (in KHz) Range from 0.001 to 4294967.295 MP/s.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Active: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_Active_11" + ], + "HelpText": "Horizontal Active Image Pixels Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Active: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_Active_11" + ], + "HelpText": "Vertical Active Image Lines Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Blank: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_Blank_11" + ], + "HelpText": "Horizontal Blank Pixels Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Blank: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_Blank_11" + ], + "HelpText": "Vertical Blank lines Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Front Porch: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_FrontPorch_11" + ], + "HelpText": "Horizontal Front Porch Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Front Porch: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_FrontPorch_11" + ], + "HelpText": "Vertical Front Porch Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Sync: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_Sync_11" + ], + "HelpText": "Horizontal Sync Width Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Sync: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_Sync_11" + ], + "HelpText": "Vertical Sync Width Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Image Size: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_Image_Size_11" + ], + "HelpText": "Horizontal Addressable Video Image Size in mm represented by 16bits. Image size multiplier 1.00 mm precision.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Image Size: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_Image_Size_11" + ], + "HelpText": "Vertical Addressable Video Image Size in mm represented by 16bits. Image size multiplier 1.00 mm precision.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryBin", + "WidgetName": "Common Flag: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_Common_Flag_11" + ], + "HelpText": "Common DTD Flags:\nBit 7 : Horizontal Sync Polarity\n1 : Positive\n0 : Negative\nBit 6 : Vertical Sync polarity\n1 : Positive\n0 : Negative\nBit 5 - 0: Reserved (Default value 0)", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-11-7", + "PageName": "LFP PnP ID Table", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Table", + "WidgetName": "", + "Visibility": "", + "Data": [ + "42", + "LFP_Panel_PnP_ID_11" + ], + "HelpText": "This feature allows the 10 bytes of EDID Vendor/Product ID starting at offset 08h to be used as a PnP ID.\n\nTable Definition:\n\tWord: ID Manufacturer Name\n\tWord: ID Product Code\n\tDWord: ID Serial Number\n\tByte: Week of Manufacture\n\tByte: Year of Manufacture", + "WidgetValues": [ + { + "ColumnName": "PnP ID", + "SizeinBytes": "1" + } + ] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-11-8", + "PageName": "Backlight Control Parameters", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Inverter Type: ", + "Visibility": "", + "Data": [ + "43", + "BLC_Inv_Type_11" + ], + "HelpText": "This feature allows for the selection of the Backlight Inverter type that is to be used to control the backlight brightness of the LFP.\nWhen PWM is selected, the driver and VBIOS will control the backlight brightness via the integrated PWM solution for the applicable chipsets.\nWhen None/External is selected, the system BIOS will control the backlight brightness via the external solution.", + "WidgetValues": [ + { + "Key": "None/External", + "Value": "0" + }, + { + "Key": "PWM", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Pwm Source Selection: ", + "Visibility": "", + "Data": [ + "43", + "Lfp_Pwm_Source_Selection_11" + ], + "HelpText": "If panel supports 'Intel HDR AUX Interface', it will always be chosen by default. If not, value in 'PWM Source Selection' will be used", + "WidgetValues": [ + { + "Key": "PWM From Display Engine", + "Value": "2" + }, + { + "Key": "PWM From LCD Panel", + "Value": "3" + }, + { + "Key": "Panel Driver Interface", + "Value": "4" + }, + { + "Key": "VESA eDP AUX Interface", + "Value": "5" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Pwm Controller Selection: ", + "Visibility": "", + "Data": [ + "43", + "Lfp_Pwm_Controller_Selection_11" + ], + "HelpText": "This field allows to select the PWM Controller to be used for the selected Local Flat Panel.This field allows to select the PWM Controller to be used for the selected Local Flat Panel.If Two LFPs are connected then PWM0 and PWM1 must be selected accordingly.", + "WidgetValues": [ + { + "Key": "PWM0", + "Value": "0" + }, + { + "Key": "PWM1", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Inverter Polarity: ", + "Visibility": "", + "Data": [ + "43", + "BLC_Inv_Polarity_11" + ], + "HelpText": "This feature allows the backlight inverter polarity to be specified.\nNormal means 0 value is minimum brightness.\nInverted means 0 value is maximum brightness.", + "WidgetValues": [ + { + "Key": "Normal", + "Value": "0" + }, + { + "Key": "Inverted", + "Value": "1" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Minimum Brightness: ", + "Visibility": "", + "Data": [ + "43", + "Post_Min_Brightness_11" + ], + "HelpText": "This feature allows defining the absolute minimum backlight brightness. The driver will never decrease the backlight less than this value. The value must be specified using normal polarity semantics. The value should range from 0 to 255 if the brightness precision bit is chosen to be 8, and it should range from 0 to 65535 if the precision bit is chosen to be 16.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "POST Backlight Intensity: ", + "Visibility": "", + "Data": [ + "43", + "Post_Brightness_11" + ], + "HelpText": "This feature is used to set default backlight brightness value of the panel at POST. The value should range from 0 to 255 if the bit precision is chosen to be 8 and it should range from 0 to 65535 if the brightness bit precision is chosent to be 16.", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Brightness Precision Bits: ", + "Visibility": "", + "Data": [ + "43", + "BrightnessPrecisionBits_11" + ], + "HelpText": "This field represents the range of brightness in terms of bit precision.\n 8 = Brightness range of 0 to 255.\n 16 = Brightness range of 0 to 65535", + "WidgetValues": [ + { + "Key": "8", + "Value": "8" + }, + { + "Key": "16", + "Value": "16" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "PWM Inverter Frequency (Hz): ", + "Visibility": "", + "Data": [ + "43", + "PWM_Frequency_11" + ], + "HelpText": "This feature allows for the definition of the frequency needed for PWM Inverter.\nNote: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Intel HDR DPCD Refresh Timeout (unit - 10 micro seconds): ", + "Visibility": "", + "Data": [ + "43", + "HdrDpcdRefreshTimeout_11" + ], + "HelpText": "This field allows to configure the refresh timeout of Intel HDR DPCDs for different TCON Vendors.\nNote:\n\tThe value is in units of 10 microseconds.\n\tThe range (entered as a decimal number), for the timeout is 0-65535", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-11-9", + "PageName": "Chromaticity Control", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Chromaticity Control Feature: ", + "Visibility": "", + "Data": [ + "46", + "Chromacity_Enable_11" + ], + "HelpText": "This bit enables Chromaticity feature.\nIf this bit is enabled, EDID values for chromaticity will be used, else feature is disabled.\nFeature will be supported for Panels that support EDID version 1.4 or higher.\nPlease refer to section 3.7 of EDID Specification 1.4.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Override the EDID values: ", + "Visibility": "", + "Data": [ + "46", + "Override_EDID_Data_11" + ], + "HelpText": "This option when enabled along with Chromaticity feature will override EDID values through following VBT data", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Red_Green_bits (Bits 1:0 at 19h): ", + "Visibility": "", + "Data": [ + "46", + "Red_Green_11" + ], + "HelpText": "Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Blue_White_bits (Bits 1:0 at 1Ah): ", + "Visibility": "", + "Data": [ + "46", + "Blue_White_11" + ], + "HelpText": "Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Red_x (Bits 9:2 at 1Bh): ", + "Visibility": "", + "Data": [ + "46", + "Red_x_11" + ], + "HelpText": "Bits 9:2 of red color x coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Red_y (Bits 9:2 at 1Ch): ", + "Visibility": "", + "Data": [ + "46", + "Red_y_11" + ], + "HelpText": "Bits 9:2 of red color y coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Green_x (Bits 9:2 at 1Dh): ", + "Visibility": "", + "Data": [ + "46", + "Green_x_11" + ], + "HelpText": "Bits 9:2 of Green color x coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Green_y (Bits 9:2 at 1Eh): ", + "Visibility": "", + "Data": [ + "46", + "Green_y_11" + ], + "HelpText": "Bits 9:2 of Green color y coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Blue_x (Bits 9:2 at 1Fh): ", + "Visibility": "", + "Data": [ + "46", + "Blue_x_11" + ], + "HelpText": "Bits 9:2 of Blue color x coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Blue_y (Bits 9:2 at 20h): ", + "Visibility": "", + "Data": [ + "46", + "Blue_y_11" + ], + "HelpText": "Bits 9:2 of Blue color y coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " White_x (Bits 9:2 at 21h): ", + "Visibility": "", + "Data": [ + "46", + "White_x_11" + ], + "HelpText": "Bits 9:2 of White color x coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " White_y (Bits 9:2 at 22h): ", + "Visibility": "", + "Data": [ + "46", + "White_y_11" + ], + "HelpText": "Bits 9:2 of White color y coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Override Luminance values ", + "Visibility": "", + "Data": [ + "46", + "Override_LUM_Data_11" + ], + "HelpText": "This option when enabled along with Chromaticity feature will override luminance values following VBT values", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Minimum Luminance: ", + "Visibility": "", + "Data": [ + "46", + "MinLuminance_11" + ], + "HelpText": "Minimum luminance value.\n2 byte value, encoded in IEEE 754 half-precision binary floating point format,", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Maximum full frame luminance: ", + "Visibility": "", + "Data": [ + "46", + "MaxFullLuminance_11" + ], + "HelpText": "Maximum Full frame luminance value.\n2 byte value, encoded in IEEE 754 half-precision binary floating point format,", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Maximum Luminance: ", + "Visibility": "", + "Data": [ + "46", + "MaxLuminance_11" + ], + "HelpText": "Maximum luminance value(Relatively smaller portion of screen).\n2 byte value, encoded in IEEE 754 half-precision binary floating point format.", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Override Gamma values: ", + "Visibility": "", + "Data": [ + "46", + "Override_Gamma_Data_11" + ], + "HelpText": "This option when enabled along with Chromaticity feature will override gamma values through following VBT data", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Panel gamma: ", + "Visibility": "", + "Data": [ + "46", + "Gamma_11" + ], + "HelpText": "Value shall define the gamma range, from 1.00 to 3.54, as follows:\nField Value = (Gamma (value in float) x 100) - 100\nField values range from 00h through FFh.\nFFh = No gamma information shall be provided", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-11-10", + "PageName": "VESA DSC Parameters", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "DSC Major Version: ", + "Visibility": "", + "Data": [ + "56", + "C11_Major_Dsc_Version" + ], + "HelpText": "VESA DSC Major revision field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "DSC Minor Version: ", + "Visibility": "", + "Data": [ + "56", + "C11_Minor_Dsc_Version" + ], + "HelpText": "VESA DSC Minor revision field.", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Block prediction supported: ", + "Visibility": "", + "Data": [ + "56", + "C11_Blk_Prediction_En" + ], + "HelpText": "Sink supports block prediction as per the VESA DSC Spec.", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "RC Buffer Block size as per VESA DSC Spec: ", + "Visibility": "", + "Data": [ + "56", + "C11_RC_Block_Size" + ], + "HelpText": "RC buffer block size for a single RC buffer as defined by the VESA DSC spec.", + "WidgetValues": [ + { + "Key": "1 KB", + "Value": "0" + }, + { + "Key": "4 KB", + "Value": "1" + }, + { + "Key": "16 KB", + "Value": "2" + }, + { + "Key": "64 KB", + "Value": "3" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Number of RC buffer blocks as per VESA DSC Spec: ", + "Visibility": "", + "Data": [ + "56", + "C11_Dsc_RC_Buf_Size" + ], + "HelpText": "This field defines the number of RC buffers as per VESA DSC spec.\nThe number of RC buffers used by the software shall be (Value + 1) where Value is in range 0 to 127.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryBin", + "WidgetName": "Slices per line supported by the sink device: ", + "Visibility": "", + "Data": [ + "56", + "C11_Dsc_Slices_Per_Line" + ], + "HelpText": "This field defines the slices per line supported by the sink device.\nThe field is defined in bitmap fashion and details of each bits are as defined below:\n\tBits 31-10\t\t Bit 9\tBit 8\tBit 7\tBit 6\tBit 5\tBit 4\t Bit 3\t Bit 2\t Bit 1\t Bit 0\n\tReserved\t\t 24\t 20\t 16\t 12\t 10\t 8\t 6\t 4\t 2\t 1\nBit = 0, not supported. Bit = 1, supported\nNote: Assumption is that sink shall support all lower slices per line than maximum selected field. i.e. If it supports say 8 slices per line, it will also support 4/2/1 slices per line", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Line buffer depth as per VESA DSC Spec: ", + "Visibility": "", + "Data": [ + "56", + "C11_Line_Buffer_Depth" + ], + "HelpText": "Line buffer depth in bits as per VESA DSC spec.", + "WidgetValues": [ + { + "Key": "8 bits", + "Value": "0" + }, + { + "Key": "9 bits", + "Value": "1" + }, + { + "Key": "10 bits", + "Value": "2" + }, + { + "Key": "11 bits", + "Value": "3" + }, + { + "Key": "12 bits", + "Value": "4" + }, + { + "Key": "13 bits", + "Value": "5" + }, + { + "Key": "14 bits", + "Value": "6" + }, + { + "Key": "15 bits", + "Value": "7" + }, + { + "Key": "16 bits", + "Value": "8" + } + ] + }, + { + "WidgetType": "EntryBin", + "WidgetName": "Input compression BPC supported by the sink device: ", + "Visibility": "", + "Data": [ + "56", + "C11_Dsc_Bpc" + ], + "HelpText": "This field defines the compression input bpc supported by the sink device.\nThe field is defined in bitmap fashion and details of each bits are as defined below:\n\tBits 7-4\t Bit 3\t Bit 2\t Bit 1\t Bit 0\n\tRsvd\t 12 bpc\t 10bpc\t 8bpc\t Rsvd\nBit = 0, not supported. Bit = 1, supported\nNote: Assumption is that sink shall support all lower bpc values than the maximum selected field. i.e. If it supports say 12bpc, it will also support 10 and 8bpc as well", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Maximum supported compression BPP: ", + "Visibility": "", + "Data": [ + "56", + "C11_Dsc_Max_Bpp" + ], + "HelpText": "As of today, we are supporting 6/8/10/12 BPP for compression output.\nSelect the most appropriate BPP as supported by the sink.", + "WidgetValues": [ + { + "Key": "6 Bits per pixel", + "Value": "0" + }, + { + "Key": "8 Bits per pixel", + "Value": "1" + }, + { + "Key": "10 Bits per pixel", + "Value": "2" + }, + { + "Key": "12 Bits per pixel", + "Value": "3" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Slice height supported by the sink device: ", + "Visibility": "", + "Data": [ + "56", + "C11_Dsc_Slice_Height" + ], + "HelpText": "Slice height supported by the sink device for DSC slice.\nNote: Slice height must divide the picture height uniformly.", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + } + ] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-12", + "PageName": "Panel #12", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "LabelHeading", + "WidgetName": "Common LFP Features", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryAsci", + "WidgetName": " LFP Panel Name: ", + "Visibility": "", + "Data": [ + "42", + "Panel_Name_12" + ], + "HelpText": "This feature defines the LFP panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Target X-Res: ", + "Visibility": "", + "Data": [ + "42", + "Panel_Width_12" + ], + "HelpText": "This value specifies the Target X-Resolution for this panel.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Target Y-Res: ", + "Visibility": "", + "Data": [ + "42", + "Panel_Height_12" + ], + "HelpText": "This value specifies the Target Y-Resolution for this panel.", + "WidgetValues": [] + }, + { + "WidgetType": "LabelHeading", + "WidgetName": " DPS Panel Type Features", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Seamless DRRS Minimum Refresh Rate (Hz): ", + "Visibility": "", + "Data": [ + "42", + "Seamless_DRRS_Min_RR_12" + ], + "HelpText": "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\nNote: Graphics driver will use this field only when EDID support is disabled in VBT configuration.", + "WidgetValues": [] + }, + { + "WidgetType": "LabelHeading", + "WidgetName": " BackLight Technology Type Features", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " BackLight Technology: ", + "Visibility": "", + "Data": [ + "40", + "Blt_Control_12" + ], + "HelpText": "This feature allows OEM to select the Backlight Technology.", + "WidgetValues": [ + { + "Key": "LED Backlight", + "Value": "2" + }, + { + "Key": "CCFL Backlight", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Panel Rotation: ", + "Visibility": "", + "Data": [ + "40", + "Panel_Rotation_12" + ], + "HelpText": "This feature specifies the Panel Rotation of LFP panel used.", + "WidgetValues": [ + { + "Key": "0 degree", + "Value": "0" + }, + { + "Key": "180 degree", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Panel Position: ", + "Visibility": "", + "Data": [ + "40", + "Panel_Position_12" + ], + "HelpText": "This feature specifies the Panel Position of LFP panel used.", + "WidgetValues": [ + { + "Key": "Inside Shell", + "Value": "0" + }, + { + "Key": "Outside Shell", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Dual LFP Port Sync: ", + "Visibility": "", + "Data": [ + "42", + "EnablePortSync_Bit_12" + ], + "HelpText": "This feature will allow users to disable/enable Dual LFP Port Sync and it is applicable for DDI-A, DDI-B in case of eDP and DSI-0, DSI-1 in case of MIPI. \r\n.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " GPU Dithering for Banding artifacts: ", + "Visibility": "", + "Data": [ + "42", + "EnableDithering_Bit_12" + ], + "HelpText": "This field can be used to enable dithering from the source side for reducing banding artifacts on the visual quality features like DPST.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "Button", + "WidgetName": "Power Features", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Generic DTD Timings", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "LFP PnP ID Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Backlight Control Parameters", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Chromaticity Control", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "VESA DSC Parameters", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "LabelHeading", + "WidgetName": "Integrated eDP Settings", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "eDP Fast Link Training Configuration Parameters", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "eDP Panel Power Sequencing Parameters", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Edp Max Port Link Rate (in 200 Khz): ", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [ + "27", + "eDP_Max_Port_Link_Rate_12" + ], + "HelpText": "This field specifies EDP Max Port Link Rate supported by the port in unit of 200KHz.\nDefault value would be \"0\", in which case Display Drivers should consider EDP Max Port Link Rate to be the Platform supported Max Link Rate.\nOnly when OEM's need to limit to particular Link Rate can enter the value as mentioned in below table.\n\nNote:\n1) OEM's need to enter the values mentioned from below table only.\n2) If value entered is not matching with any of the below values then Platform supported Max Link Rate should be considere as EDP Max Port Link Rate by the display drivers.\n3) In case of EDP Fast Link Training Params(FLT), if user enters FLT Link Rate value greater than the \"eDP Max Port Link Rate\" then we need to use \n Fast Link training Link Rate = MIN (FLT Link Rate , eDP Max Port Link Rate)\n---------------------------------------------------------\n|\tLink Rate(Gbps)\t|\t Value to enter in text field\t|\n|\t \t\t|\t in terms of 200KHZ \t|\n---------------------------------------------------------\n|\t 1.62 \t\t|\t 8100 \t|\n|\t 2.16 \t\t|\t 10800 \t|\n|\t 2.43 \t\t|\t 12150 \t|\n|\t 2.7 \t\t|\t 13500 \t|\n|\t 3.24 \t\t|\t 16200 \t|\n|\t 3.78 \t\t|\t 18900 \t|\n|\t 4.32 \t\t|\t 21600 \t|\n|\t 5.4 \t\t|\t 27000 \t|\n|\t 6.48 \t\t|\t 32400 \t|\n|\t 6.75 \t\t|\t 33750 \t|\n|\t 8.1 \t\t|\t 40500 \t|\n", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Panel Color Depth: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Panel_Color_Depth_12" + ], + "HelpText": "This feature specifies the color depth of eDP panel used.", + "WidgetValues": [ + { + "Key": "18-bit Color Depth", + "Value": "0" + }, + { + "Key": "24-bit Color Depth", + "Value": "1" + }, + { + "Key": "30-bit Color Depth", + "Value": "2" + }, + { + "Key": "36-bit Color Depth", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Select VSwing/Pre-Emphasis table : ", + "Visibility": "", + "Data": [ + "27", + "eDP_VswingPreEmph_12" + ], + "HelpText": "This feature selects the VSwing Pre-Emphasis setting table to be used. For Tigerlake, based on the selection respective table will be used.\nTables for Tigerlake:\nLow Power VSwing Pre-Emphasis Setting Table:\nFor HBR2:\n\t\t\t\t\t\t Pre-Emphasis (db)\n\t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\nVoltage \t\t Level-0/200mV \t\t 200mV, 0.0db \t\t 200mV, 1.9db \t\t 200mV, 3.5db \t\t 200mV, 4.9db\nSwing \t\t Level-1/250mV \t\t 250mV, 0.0db \t\t 250mV, 1.6db \t\t 250mV, 2.9db \t\t N/A\n(mV) \t\t Level-2/300mV \t\t 300mV, 0.0db \t\t 300mV, 1.3db \t\t N/A \t\t N/A\n\t\t Level-3/350mV \t\t 350mV, 0.0db \t\t N/A \t\t N/A \t\t N/A\n\n\nFor HBR3:\n\t\t\t\t\t\t Pre-Emphasis (db)\n\t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\nVoltage \t\t Level-0/350mV \t\t 350mV, 0.0db \t\t 350mV, 3.1db \t\t 350mV, 6.0db \t\t 350mV, 8.2db\nSwing \t\t Level-1/500mV \t\t 500mV, 0.0db \t\t 500mV, 2.9db \t\t 500mV, 5.1db \t\t N/A\n(mV) \t\t Level-2/650mV \t\t 650mV, 0.6db \t\t 600mV, 3.5db \t\t N/A \t\t N/A\n\t\t Level-3/900mV \t\t 900mV, 0.0db \t\t N/A \t\t N/A \t\t N/A\n\n\nDefault VSwing Pre-Emphasis Setting Table:\nFor HBR:\n\t\t\t\t\t\t Pre-Emphasis (db)\n\t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\nVoltage \t\t Level-0/350mV \t\t 350mV, 0.0db \t\t 350mV, 3.1db \t\t 350mV, 6.0db \t\t 350mV, 8.2db\nSwing \t\t Level-1/500mV \t\t 500mV, 0.0db \t\t 500mV, 2.9db \t\t 500mV, 5.1db \t\t N/A\n(mV) \t\t Level-2/650mV \t\t 650mV, 0.6db \t\t 600mV, 3.5db \t\t N/A \t\t N/A\n\t\t Level-3/900mV \t\t 900mV, 0.0db \t\t N/A \t\t N/A \t\t N/A\n\n\nFor HBR2:\n\t\t\t\t\t\t Pre-Emphasis (db)\n\t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\nVoltage \t\t Level-0/350mV \t\t 350mV, 0.0db \t\t 350mV, 3.1db \t\t 350mV, 6.0db \t\t 350mV, 8.2db\nSwing \t\t Level-1/500mV \t\t 500mV, 0.0db \t\t 500mV, 2.9db \t\t 500mV, 5.1db \t\t N/A\n(mV) \t\t Level-2/650mV \t\t 650mV, 0.6db \t\t 600mV, 3.5db \t\t N/A \t\t N/A\n\t\t Level-3/900mV \t\t 900mV, 0.0db \t\t N/A \t\t N/A \t\t N/A", + "WidgetValues": [ + { + "Key": "Default VSwing/Pre-Emphasis Table", + "Value": "1" + }, + { + "Key": "Low Power VSwing/Pre-Emphasis Table", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " eDP Spread Spectrum Clock: ", + "Visibility": "", + "Data": [ + "40", + "Enable_SSC12" + ], + "HelpText": "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Pixel Overlap Count: ", + "Visibility": "", + "Data": [ + "42", + "PixelOverlapCount_12" + ], + "HelpText": "Select the number of Pixels to be overlapped per half of Scanline while using Edp Multi-SST(MSO) feature.", + "WidgetValues": [ + { + "Key": "Zero Pixel Overlap", + "Value": "0" + }, + { + "Key": "One Pixel Overlap", + "Value": "1" + }, + { + "Key": "Two Pixel Overlap", + "Value": "2" + }, + { + "Key": "Three Pixel Overlap", + "Value": "3" + }, + { + "Key": "Four Pixel Overlap", + "Value": "4" + }, + { + "Key": "Five Pixel Overlap", + "Value": "5" + }, + { + "Key": "Six Pixel Overlap", + "Value": "6" + }, + { + "Key": "Seven Pixel Overlap", + "Value": "7" + }, + { + "Key": "Eight Pixel Overlap", + "Value": "8" + } + ] + }, + { + "WidgetType": "Button", + "WidgetName": "PSR Feature", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Apical Feature", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + } + ], + "NestedPages": [ + { + "Type": "Block", + "Block": { + "PageNum": "5-2-12-1", + "PageName": "eDP Panel Power Sequencing Parameters", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " T3 optimization: ", + "Visibility": "", + "Data": [ + "27", + "eDP_T3_Optimization_12" + ], + "HelpText": "This feature enables or disables T3 optimization.\nWhen enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\nWhen disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "LCDVCC to HPD high delay (T3): ", + "Visibility": "", + "Data": [ + "27", + "eDP_Vcc_To_Hpd_Delay_12" + ], + "HelpText": "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\nValid Range: 0 to 200msec", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Valid video data to Backlight Enable delay (T8): ", + "Visibility": "", + "Data": [ + "27", + "eDP_DataOn_To_BkltEnable_Delay_12" + ], + "HelpText": "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\nT8 is inclusive of T7.\nValid Range of T7: 0 to 50msec", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "PWM-On To Backlight Enable delay: ", + "Visibility": "", + "Data": [ + "27", + "eDP_PwmOn_To_Bklt_Enable_Delay_12" + ], + "HelpText": "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\nDelay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\nSo it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Backlight Disable to PWM-Off delay: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Bklt_Disable_To_PwmOff_Delay_12" + ], + "HelpText": "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\nDelay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\nSo it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Backlight Disable to End of Valid video data delay (T9): ", + "Visibility": "", + "Data": [ + "27", + "eDP_BkltDisable_To_DataOff_Delay_12" + ], + "HelpText": "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "End of Valid video data to Power-Off delay (T10): ", + "Visibility": "", + "Data": [ + "27", + "eDP_DataOff_To_PowerOff_Delay_12" + ], + "HelpText": "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\nValid Range: 0 to 500 msec", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Power-off time (T12): ", + "Visibility": "", + "Data": [ + "27", + "eDP_PowerCycle_Delay_12" + ], + "HelpText": "Using this field Power-off time can be specified in 100uS.", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-12-2", + "PageName": "eDP Fast Link Training Configuration Parameters", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Is FastLinkTraining Feature Supported: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Fast_Link_Training_Supported_12" + ], + "HelpText": "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled.", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Data Rate: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Fast_Link_Training_Data_Rate_12" + ], + "HelpText": "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. It will be used if the sink indicates that no aux handshake is required during link training.\n\nIn case of EDP Fast Link Training Params(FLT), if user enters FLT Link Rate value greater than the \"eDP Max Port Link Rate\" then driver would use \n Fast Link training Link Rate = MIN (FLT Link Rate , eDP Max Port Link Rate).", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Lane Count: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Link_LaneCount_12" + ], + "HelpText": "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. It will be used if the sink indicates that no aux handshake is required during link training.", + "WidgetValues": [ + { + "Key": "x1", + "Value": "0" + }, + { + "Key": "x2", + "Value": "1" + }, + { + "Key": "x4", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Pre-Emphasis: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Link_PreEmp_12" + ], + "HelpText": "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. It will be used if the sink indicates that no aux handshake is required during link training.", + "WidgetValues": [ + { + "Key": "Level-0", + "Value": "0" + }, + { + "Key": "Level-1", + "Value": "1" + }, + { + "Key": "Level-2", + "Value": "2" + }, + { + "Key": "Level-3", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Voltage Swing: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Link_Vswing_12" + ], + "HelpText": "This feature allows for the selection of the Voltage Swing value for the embedded DP link. It will be used if the sink indicates that no aux handshake is required during link training.", + "WidgetValues": [ + { + "Key": "Swing-0", + "Value": "0" + }, + { + "Key": "Swing-1", + "Value": "1" + }, + { + "Key": "Swing-2", + "Value": "2" + }, + { + "Key": "Swing-3", + "Value": "3" + } + ] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-12-3", + "PageName": "PSR Feature", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Full Link enable: ", + "Visibility": "", + "Data": [ + "9", + "PSR_FullLink_Enable_12" + ], + "HelpText": "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state.", + "WidgetValues": [ + { + "Key": "No", + "Value": "0" + }, + { + "Key": "Yes", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Require AUX to wake up: ", + "Visibility": "", + "Data": [ + "9", + "PSR_Require_AUX2Wakeup_12" + ], + "HelpText": "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used.", + "WidgetValues": [ + { + "Key": "No", + "Value": "0" + }, + { + "Key": "Yes", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Lines to wait before link standby: ", + "Visibility": "", + "Data": [ + "9", + "PSR_Lines2Wait_B4LinkS3_12" + ], + "HelpText": "This field determines Lines to wait before link standby\n0 lines to wait (Default)\n1 lines to wait\n4 lines to wait\n8 lines to wait\nOthers Reserved", + "WidgetValues": [ + { + "Key": "0 lines to wait", + "Value": "0" + }, + { + "Key": "1 lines to wait", + "Value": "1" + }, + { + "Key": "4 lines to wait", + "Value": "2" + }, + { + "Key": "8 lines to wait", + "Value": "3" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Idle frames to wait: ", + "Visibility": "", + "Data": [ + "9", + "PSR_IdleFrames2Wait_12" + ], + "HelpText": "Idle frames to wait for PSR enable.\nAllowed values 0-15. Default value is 0.", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Clock Recovery Time: ", + "Visibility": "", + "Data": [ + "9", + "PSR_TP1_WaitTime_12" + ], + "HelpText": "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)", + "WidgetValues": [ + { + "Key": "500 usec", + "Value": "0" + }, + { + "Key": "100 usec", + "Value": "1" + }, + { + "Key": "2.5 msec", + "Value": "2" + }, + { + "Key": "0 (Skip)", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Channel Equalization Time for PSR1 panel: ", + "Visibility": "", + "Data": [ + "9", + "PSR1_TP_2_3_4_WaitTime_12" + ], + "HelpText": "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) or TP4(Training Pattern4) time during PSR1 exit(wake up)", + "WidgetValues": [ + { + "Key": "500 usec", + "Value": "0" + }, + { + "Key": "100 usec", + "Value": "1" + }, + { + "Key": "2.5 msec", + "Value": "2" + }, + { + "Key": "0 (Skip)", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Channel Equalization Time for PSR2 panel: ", + "Visibility": "", + "Data": [ + "9", + "PSR2_TP_2_3_4_WaitTime_12" + ], + "HelpText": "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) or TP4(Training Pattern4) time during PSR2 exit(wake up)", + "WidgetValues": [ + { + "Key": "500 usec", + "Value": "0" + }, + { + "Key": "100 usec", + "Value": "1" + }, + { + "Key": "2.5 msec", + "Value": "2" + }, + { + "Key": "50 usec", + "Value": "3" + } + ] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-12-4", + "PageName": "Apical Feature", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Apical Assertive Display IP: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Apical_Display_Ip_Enable_12" + ], + "HelpText": "This field enables/disables the Apical Assertive Display IP for this panel.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Panel OUI (IEEE OUI): ", + "Visibility": "", + "Data": [ + "27", + "eDP_Panel_Oui_12" + ], + "HelpText": "This field specifies the Apical IP specific Panel OUI field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " DPCD Base Address: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Dpcd_Base_Address_12" + ], + "HelpText": "This field specifies the Apical IP specific DPCD base address field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " DPCD Irdidix Control 0: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Dpcd_Irdidix_Control0_12" + ], + "HelpText": "This field specifies the Apical IP specific DPCD Irdidix control 0 field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " DPCD Option Select: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Dpcd_Option_Select_12" + ], + "HelpText": "This field specifies the Apical IP specific DPCD option select field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " DPCD Backlight: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Dpcd_Backlight_12" + ], + "HelpText": "This field specifies the Apical IP specific backlight value.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Ambient Light: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Ambient_Light_12" + ], + "HelpText": "This field specifies the Apical IP specific Ambient light value.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Backlight scale: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Backlight_Scale_12" + ], + "HelpText": "This field specifies the Apical IP specific backlight scale field.", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-12-5", + "PageName": "Power Features", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Intel Display Power Saving Technology (DPST) (Mobile only): ", + "Visibility": "", + "Data": [ + "44", + "DPST_Enable_12" + ], + "HelpText": "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled.\nIntel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power.\nNote: This technology is only active when the system is running in battery mode and the LFP is the only active display device.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Intel Display Refresh Rate Switching (DRRS) (Mobile only): ", + "Visibility": "", + "Data": [ + "44", + "DRRS_Enable_12" + ], + "HelpText": "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Edge Luminance Profile (ELP) : ", + "Visibility": "", + "Data": [ + "44", + "ELP_Enable_12" + ], + "HelpText": "This feature determines whether the ELP feature is enabled or disabled.\nEdge Luminance Profile (ELP) is a panel technology which reduce luminance on the edge of screen to save panel power.\nNote:This technology cannot co-exist with DPST and OPST ((i.e.) OPST, DPST and ELP cannot exist together.They are all mutually exclusive to each other.)", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " OLED Power Saving Technology (OPST) : ", + "Visibility": "", + "Data": [ + "44", + "OPST_Enable_12" + ], + "HelpText": "This feature determines whether the OPST feature is enabled or disabled.\nOLED Power Saving Technology (OPST) is a panel technology which saves power by intelligent, adaptive dimming of midrange pixel values more aggressively than the extremes without compromising the viewability.\nNote: This technology cannot co-exist with ELP and DPST ((i.e.) OPST, DPST and ELP cannot exist together.They are all mutually exclusive to each other.)", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Dynamic Media Refresh Rate Switching Enable/Disable ", + "Visibility": "", + "Data": [ + "44", + "DMRRS_Enable_12" + ], + "HelpText": "This feature determines whether Dynamic media refresh rate switching is to be enabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Enable Display Lace Support: ", + "Visibility": "", + "Data": [ + "44", + "LACE_Enable_12" + ], + "HelpText": "This feature, when enabled, will set Display Lace Support otherwise, the functionality will be disabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Panel Self Refresh (PSR): ", + "Visibility": "", + "Data": [ + "44", + "PSR_Enable_12" + ], + "HelpText": "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Assertive Display Technology Enable/Disable: ", + "Visibility": "", + "Data": [ + "44", + "ADT_Enable_12" + ], + "HelpText": "This feature determines whether Assertive display technology is to be enabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Intel Automatic Display Brightness (ADB) (Mobile only): ", + "Visibility": "", + "Data": [ + "44", + "ADB_Enable_12" + ], + "HelpText": "This feature determines whether Intel Automatic Display Brightness is to be enabled. Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) depending on the current ambient light environment.\nWhen enabled, the driver and VBIOS will control the backlight brightness of the LFP depending on the ambient environment if and only if the LFP is the only active display. When disabled, the driver will perform no action.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "EDP 4k/2k HOBL Feature: ", + "Visibility": "", + "Data": [ + "44", + "eDP_4k_2k_HOBL_feature_Enable_12" + ], + "HelpText": "This feature will allow users to disable/enable the edp 4k/2k HOBL(Hours Of Battery Life) feature by programming relevant registers specific for a platform.\r\n.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Default Display LACE Enabled status: ", + "Visibility": "", + "Data": [ + "44", + "LACE_Status_12" + ], + "HelpText": "This feature, when enabled, will set Default Display LACE Enabled status otherwise, the functionality will be disabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "DPST Aggressiveness Level: ", + "Visibility": "", + "Data": [ + "44", + "DPST_Aggressiveness_Profile_12" + ], + "HelpText": "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n1 (Maximum Quality with No DPST)\n2\n3\n4\n5\n6 (Maximum Battery)", + "WidgetValues": [ + { + "Key": "1 - Maximum Quality with No DPST", + "Value": "1" + }, + { + "Key": "2", + "Value": "2" + }, + { + "Key": "3", + "Value": "3" + }, + { + "Key": "4", + "Value": "4" + }, + { + "Key": "5", + "Value": "5" + }, + { + "Key": "6 - Maximum Battery", + "Value": "6" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "LACE Aggressiveness Level: ", + "Visibility": "", + "Data": [ + "44", + "LACE_Aggressiveness_Profile_12" + ], + "HelpText": "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\nMinimum 0\nModerate 1\nHigh 2", + "WidgetValues": [ + { + "Key": "Minimum", + "Value": "0" + }, + { + "Key": "Moderate", + "Value": "1" + }, + { + "Key": "High", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "ELP Aggressiveness Level: ", + "Visibility": "", + "Data": [ + "44", + "ELP_Aggressiveness_Profile_12" + ], + "HelpText": "This feature allows for the selection of ELP Aggressiveness level for this Panel Type.\nMinimum Power Savings\nMedium Power Savings \nMaximum Power Savings", + "WidgetValues": [ + { + "Key": "Minimum Power Savings", + "Value": "0" + }, + { + "Key": "Medium Power Savings", + "Value": "1" + }, + { + "Key": "Maximum Power Savings", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "OPST Aggressiveness Level: ", + "Visibility": "", + "Data": [ + "44", + "OPST_Aggressiveness_Profile_12" + ], + "HelpText": "This feature allows for the selection of OPST Aggressiveness level for this Panel Type.\nMinimum Power Savings\nMedium Power Savings \nMaximum Power Savings", + "WidgetValues": [ + { + "Key": "Minimum Power Savings", + "Value": "0" + }, + { + "Key": "Medium Power Savings", + "Value": "1" + }, + { + "Key": "Maximum Power Savings", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Default Display VRR Enabled status: ", + "Visibility": "", + "Data": [ + "44", + "VRR_Status_12" + ], + "HelpText": "VRR (Variable Refresh Rate) is a feature that can continuously and seamlessly vary Refresh Rate on the fly, on displays that support Variable Refresh rate Technologies.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-12-6", + "PageName": "Generic DTD Timings", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Pixel Clock in KHz: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_Pixel_CLK_12" + ], + "HelpText": "Pixel Clock (in KHz) Range from 0.001 to 4294967.295 MP/s.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Active: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_Active_12" + ], + "HelpText": "Horizontal Active Image Pixels Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Active: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_Active_12" + ], + "HelpText": "Vertical Active Image Lines Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Blank: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_Blank_12" + ], + "HelpText": "Horizontal Blank Pixels Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Blank: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_Blank_12" + ], + "HelpText": "Vertical Blank lines Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Front Porch: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_FrontPorch_12" + ], + "HelpText": "Horizontal Front Porch Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Front Porch: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_FrontPorch_12" + ], + "HelpText": "Vertical Front Porch Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Sync: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_Sync_12" + ], + "HelpText": "Horizontal Sync Width Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Sync: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_Sync_12" + ], + "HelpText": "Vertical Sync Width Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Image Size: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_Image_Size_12" + ], + "HelpText": "Horizontal Addressable Video Image Size in mm represented by 16bits. Image size multiplier 1.00 mm precision.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Image Size: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_Image_Size_12" + ], + "HelpText": "Vertical Addressable Video Image Size in mm represented by 16bits. Image size multiplier 1.00 mm precision.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryBin", + "WidgetName": "Common Flag: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_Common_Flag_12" + ], + "HelpText": "Common DTD Flags:\nBit 7 : Horizontal Sync Polarity\n1 : Positive\n0 : Negative\nBit 6 : Vertical Sync polarity\n1 : Positive\n0 : Negative\nBit 5 - 0: Reserved (Default value 0)", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-12-7", + "PageName": "LFP PnP ID Table", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Table", + "WidgetName": "", + "Visibility": "", + "Data": [ + "42", + "LFP_Panel_PnP_ID_12" + ], + "HelpText": "This feature allows the 10 bytes of EDID Vendor/Product ID starting at offset 08h to be used as a PnP ID.\n\nTable Definition:\n\tWord: ID Manufacturer Name\n\tWord: ID Product Code\n\tDWord: ID Serial Number\n\tByte: Week of Manufacture\n\tByte: Year of Manufacture", + "WidgetValues": [ + { + "ColumnName": "PnP ID", + "SizeinBytes": "1" + } + ] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-12-8", + "PageName": "Backlight Control Parameters", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Inverter Type: ", + "Visibility": "", + "Data": [ + "43", + "BLC_Inv_Type_12" + ], + "HelpText": "This feature allows for the selection of the Backlight Inverter type that is to be used to control the backlight brightness of the LFP.\nWhen PWM is selected, the driver and VBIOS will control the backlight brightness via the integrated PWM solution for the applicable chipsets.\nWhen None/External is selected, the system BIOS will control the backlight brightness via the external solution.", + "WidgetValues": [ + { + "Key": "None/External", + "Value": "0" + }, + { + "Key": "PWM", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Pwm Source Selection: ", + "Visibility": "", + "Data": [ + "43", + "Lfp_Pwm_Source_Selection_12" + ], + "HelpText": "If panel supports 'Intel HDR AUX Interface', it will always be chosen by default. If not, value in 'PWM Source Selection' will be used", + "WidgetValues": [ + { + "Key": "PWM From Display Engine", + "Value": "2" + }, + { + "Key": "PWM From LCD Panel", + "Value": "3" + }, + { + "Key": "Panel Driver Interface", + "Value": "4" + }, + { + "Key": "VESA eDP AUX Interface", + "Value": "5" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Pwm Controller Selection: ", + "Visibility": "", + "Data": [ + "43", + "Lfp_Pwm_Controller_Selection_12" + ], + "HelpText": "This field allows to select the PWM Controller to be used for the selected Local Flat Panel.This field allows to select the PWM Controller to be used for the selected Local Flat Panel.If Two LFPs are connected then PWM0 and PWM1 must be selected accordingly.", + "WidgetValues": [ + { + "Key": "PWM0", + "Value": "0" + }, + { + "Key": "PWM1", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Inverter Polarity: ", + "Visibility": "", + "Data": [ + "43", + "BLC_Inv_Polarity_12" + ], + "HelpText": "This feature allows the backlight inverter polarity to be specified.\nNormal means 0 value is minimum brightness.\nInverted means 0 value is maximum brightness.", + "WidgetValues": [ + { + "Key": "Normal", + "Value": "0" + }, + { + "Key": "Inverted", + "Value": "1" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Minimum Brightness: ", + "Visibility": "", + "Data": [ + "43", + "Post_Min_Brightness_12" + ], + "HelpText": "This feature allows defining the absolute minimum backlight brightness. The driver will never decrease the backlight less than this value. The value must be specified using normal polarity semantics. The value should range from 0 to 255 if the brightness precision bit is chosen to be 8, and it should range from 0 to 65535 if the precision bit is chosen to be 16.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "POST Backlight Intensity: ", + "Visibility": "", + "Data": [ + "43", + "Post_Brightness_12" + ], + "HelpText": "This feature is used to set default backlight brightness value of the panel at POST. The value should range from 0 to 255 if the bit precision is chosen to be 8 and it should range from 0 to 65535 if the brightness bit precision is chosent to be 16.", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Brightness Precision Bits: ", + "Visibility": "", + "Data": [ + "43", + "BrightnessPrecisionBits_12" + ], + "HelpText": "This field represents the range of brightness in terms of bit precision.\n 8 = Brightness range of 0 to 255.\n 16 = Brightness range of 0 to 65535", + "WidgetValues": [ + { + "Key": "8", + "Value": "8" + }, + { + "Key": "16", + "Value": "16" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "PWM Inverter Frequency (Hz): ", + "Visibility": "", + "Data": [ + "43", + "PWM_Frequency_12" + ], + "HelpText": "This feature allows for the definition of the frequency needed for PWM Inverter.\nNote: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Intel HDR DPCD Refresh Timeout (unit - 10 micro seconds): ", + "Visibility": "", + "Data": [ + "43", + "HdrDpcdRefreshTimeout_12" + ], + "HelpText": "This field allows to configure the refresh timeout of Intel HDR DPCDs for different TCON Vendors.\nNote:\n\tThe value is in units of 10 microseconds.\n\tThe range (entered as a decimal number), for the timeout is 0-65535", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-12-9", + "PageName": "Chromaticity Control", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Chromaticity Control Feature: ", + "Visibility": "", + "Data": [ + "46", + "Chromacity_Enable_12" + ], + "HelpText": "This bit enables Chromaticity feature.\nIf this bit is enabled, EDID values for chromaticity will be used, else feature is disabled.\nFeature will be supported for Panels that support EDID version 1.4 or higher.\nPlease refer to section 3.7 of EDID Specification 1.4.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Override the EDID values: ", + "Visibility": "", + "Data": [ + "46", + "Override_EDID_Data_12" + ], + "HelpText": "This option when enabled along with Chromaticity feature will override EDID values through following VBT data", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Red_Green_bits (Bits 1:0 at 19h): ", + "Visibility": "", + "Data": [ + "46", + "Red_Green_12" + ], + "HelpText": "Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Blue_White_bits (Bits 1:0 at 1Ah): ", + "Visibility": "", + "Data": [ + "46", + "Blue_White_12" + ], + "HelpText": "Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Red_x (Bits 9:2 at 1Bh): ", + "Visibility": "", + "Data": [ + "46", + "Red_x_12" + ], + "HelpText": "Bits 9:2 of red color x coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Red_y (Bits 9:2 at 1Ch): ", + "Visibility": "", + "Data": [ + "46", + "Red_y_12" + ], + "HelpText": "Bits 9:2 of red color y coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Green_x (Bits 9:2 at 1Dh): ", + "Visibility": "", + "Data": [ + "46", + "Green_x_12" + ], + "HelpText": "Bits 9:2 of Green color x coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Green_y (Bits 9:2 at 1Eh): ", + "Visibility": "", + "Data": [ + "46", + "Green_y_12" + ], + "HelpText": "Bits 9:2 of Green color y coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Blue_x (Bits 9:2 at 1Fh): ", + "Visibility": "", + "Data": [ + "46", + "Blue_x_12" + ], + "HelpText": "Bits 9:2 of Blue color x coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Blue_y (Bits 9:2 at 20h): ", + "Visibility": "", + "Data": [ + "46", + "Blue_y_12" + ], + "HelpText": "Bits 9:2 of Blue color y coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " White_x (Bits 9:2 at 21h): ", + "Visibility": "", + "Data": [ + "46", + "White_x_12" + ], + "HelpText": "Bits 9:2 of White color x coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " White_y (Bits 9:2 at 22h): ", + "Visibility": "", + "Data": [ + "46", + "White_y_12" + ], + "HelpText": "Bits 9:2 of White color y coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Override Luminance values ", + "Visibility": "", + "Data": [ + "46", + "Override_LUM_Data_12" + ], + "HelpText": "This option when enabled along with Chromaticity feature will override luminance values following VBT values", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Minimum Luminance: ", + "Visibility": "", + "Data": [ + "46", + "MinLuminance_12" + ], + "HelpText": "Minimum luminance value.\n2 byte value, encoded in IEEE 754 half-precision binary floating point format,", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Maximum full frame luminance: ", + "Visibility": "", + "Data": [ + "46", + "MaxFullLuminance_12" + ], + "HelpText": "Maximum Full frame luminance value.\n2 byte value, encoded in IEEE 754 half-precision binary floating point format,", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Maximum Luminance: ", + "Visibility": "", + "Data": [ + "46", + "MaxLuminance_12" + ], + "HelpText": "Maximum luminance value(Relatively smaller portion of screen).\n2 byte value, encoded in IEEE 754 half-precision binary floating point format.", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Override Gamma values: ", + "Visibility": "", + "Data": [ + "46", + "Override_Gamma_Data_12" + ], + "HelpText": "This option when enabled along with Chromaticity feature will override gamma values through following VBT data", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Panel gamma: ", + "Visibility": "", + "Data": [ + "46", + "Gamma_12" + ], + "HelpText": "Value shall define the gamma range, from 1.00 to 3.54, as follows:\nField Value = (Gamma (value in float) x 100) - 100\nField values range from 00h through FFh.\nFFh = No gamma information shall be provided", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-12-10", + "PageName": "VESA DSC Parameters", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "DSC Major Version: ", + "Visibility": "", + "Data": [ + "56", + "C12_Major_Dsc_Version" + ], + "HelpText": "VESA DSC Major revision field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "DSC Minor Version: ", + "Visibility": "", + "Data": [ + "56", + "C12_Minor_Dsc_Version" + ], + "HelpText": "VESA DSC Minor revision field.", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Block prediction supported: ", + "Visibility": "", + "Data": [ + "56", + "C12_Blk_Prediction_En" + ], + "HelpText": "Sink supports block prediction as per the VESA DSC Spec.", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "RC Buffer Block size as per VESA DSC Spec: ", + "Visibility": "", + "Data": [ + "56", + "C12_RC_Block_Size" + ], + "HelpText": "RC buffer block size for a single RC buffer as defined by the VESA DSC spec.", + "WidgetValues": [ + { + "Key": "1 KB", + "Value": "0" + }, + { + "Key": "4 KB", + "Value": "1" + }, + { + "Key": "16 KB", + "Value": "2" + }, + { + "Key": "64 KB", + "Value": "3" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Number of RC buffer blocks as per VESA DSC Spec: ", + "Visibility": "", + "Data": [ + "56", + "C12_Dsc_RC_Buf_Size" + ], + "HelpText": "This field defines the number of RC buffers as per VESA DSC spec.\nThe number of RC buffers used by the software shall be (Value + 1) where Value is in range 0 to 127.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryBin", + "WidgetName": "Slices per line supported by the sink device: ", + "Visibility": "", + "Data": [ + "56", + "C12_Dsc_Slices_Per_Line" + ], + "HelpText": "This field defines the slices per line supported by the sink device.\nThe field is defined in bitmap fashion and details of each bits are as defined below:\n\tBits 31-10\t\t Bit 9\tBit 8\tBit 7\tBit 6\tBit 5\tBit 4\t Bit 3\t Bit 2\t Bit 1\t Bit 0\n\tReserved\t\t 24\t 20\t 16\t 12\t 10\t 8\t 6\t 4\t 2\t 1\nBit = 0, not supported. Bit = 1, supported\nNote: Assumption is that sink shall support all lower slices per line than maximum selected field. i.e. If it supports say 8 slices per line, it will also support 4/2/1 slices per line", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Line buffer depth as per VESA DSC Spec: ", + "Visibility": "", + "Data": [ + "56", + "C12_Line_Buffer_Depth" + ], + "HelpText": "Line buffer depth in bits as per VESA DSC spec.", + "WidgetValues": [ + { + "Key": "8 bits", + "Value": "0" + }, + { + "Key": "9 bits", + "Value": "1" + }, + { + "Key": "10 bits", + "Value": "2" + }, + { + "Key": "11 bits", + "Value": "3" + }, + { + "Key": "12 bits", + "Value": "4" + }, + { + "Key": "13 bits", + "Value": "5" + }, + { + "Key": "14 bits", + "Value": "6" + }, + { + "Key": "15 bits", + "Value": "7" + }, + { + "Key": "16 bits", + "Value": "8" + } + ] + }, + { + "WidgetType": "EntryBin", + "WidgetName": "Input compression BPC supported by the sink device: ", + "Visibility": "", + "Data": [ + "56", + "C12_Dsc_Bpc" + ], + "HelpText": "This field defines the compression input bpc supported by the sink device.\nThe field is defined in bitmap fashion and details of each bits are as defined below:\n\tBits 7-4\t Bit 3\t Bit 2\t Bit 1\t Bit 0\n\tRsvd\t 12 bpc\t 10bpc\t 8bpc\t Rsvd\nBit = 0, not supported. Bit = 1, supported\nNote: Assumption is that sink shall support all lower bpc values than the maximum selected field. i.e. If it supports say 12bpc, it will also support 10 and 8bpc as well", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Maximum supported compression BPP: ", + "Visibility": "", + "Data": [ + "56", + "C12_Dsc_Max_Bpp" + ], + "HelpText": "As of today, we are supporting 6/8/10/12 BPP for compression output.\nSelect the most appropriate BPP as supported by the sink.", + "WidgetValues": [ + { + "Key": "6 Bits per pixel", + "Value": "0" + }, + { + "Key": "8 Bits per pixel", + "Value": "1" + }, + { + "Key": "10 Bits per pixel", + "Value": "2" + }, + { + "Key": "12 Bits per pixel", + "Value": "3" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Slice height supported by the sink device: ", + "Visibility": "", + "Data": [ + "56", + "C12_Dsc_Slice_Height" + ], + "HelpText": "Slice height supported by the sink device for DSC slice.\nNote: Slice height must divide the picture height uniformly.", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + } + ] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-13", + "PageName": "Panel #13", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "LabelHeading", + "WidgetName": "Common LFP Features", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryAsci", + "WidgetName": " LFP Panel Name: ", + "Visibility": "", + "Data": [ + "42", + "Panel_Name_13" + ], + "HelpText": "This feature defines the LFP panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Target X-Res: ", + "Visibility": "", + "Data": [ + "42", + "Panel_Width_13" + ], + "HelpText": "This value specifies the Target X-Resolution for this panel.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Target Y-Res: ", + "Visibility": "", + "Data": [ + "42", + "Panel_Height_13" + ], + "HelpText": "This value specifies the Target Y-Resolution for this panel.", + "WidgetValues": [] + }, + { + "WidgetType": "LabelHeading", + "WidgetName": " DPS Panel Type Features", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Seamless DRRS Minimum Refresh Rate (Hz): ", + "Visibility": "", + "Data": [ + "42", + "Seamless_DRRS_Min_RR_13" + ], + "HelpText": "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\nNote: Graphics driver will use this field only when EDID support is disabled in VBT configuration.", + "WidgetValues": [] + }, + { + "WidgetType": "LabelHeading", + "WidgetName": " BackLight Technology Type Features", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " BackLight Technology: ", + "Visibility": "", + "Data": [ + "40", + "Blt_Control_13" + ], + "HelpText": "This feature allows OEM to select the Backlight Technology.", + "WidgetValues": [ + { + "Key": "LED Backlight", + "Value": "2" + }, + { + "Key": "CCFL Backlight", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Panel Rotation: ", + "Visibility": "", + "Data": [ + "40", + "Panel_Rotation_13" + ], + "HelpText": "This feature specifies the Panel Rotation of LFP panel used.", + "WidgetValues": [ + { + "Key": "0 degree", + "Value": "0" + }, + { + "Key": "180 degree", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Panel Position: ", + "Visibility": "", + "Data": [ + "40", + "Panel_Position_13" + ], + "HelpText": "This feature specifies the Panel Position of LFP panel used.", + "WidgetValues": [ + { + "Key": "Inside Shell", + "Value": "0" + }, + { + "Key": "Outside Shell", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Dual LFP Port Sync: ", + "Visibility": "", + "Data": [ + "42", + "EnablePortSync_Bit_13" + ], + "HelpText": "This feature will allow users to disable/enable Dual LFP Port Sync and it is applicable for DDI-A, DDI-B in case of eDP and DSI-0, DSI-1 in case of MIPI. \r\n.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " GPU Dithering for Banding artifacts: ", + "Visibility": "", + "Data": [ + "42", + "EnableDithering_Bit_13" + ], + "HelpText": "This field can be used to enable dithering from the source side for reducing banding artifacts on the visual quality features like DPST.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "Button", + "WidgetName": "Power Features", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Generic DTD Timings", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "LFP PnP ID Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Backlight Control Parameters", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Chromaticity Control", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "VESA DSC Parameters", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "LabelHeading", + "WidgetName": "Integrated eDP Settings", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "eDP Fast Link Training Configuration Parameters", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "eDP Panel Power Sequencing Parameters", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Edp Max Port Link Rate (in 200 Khz): ", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [ + "27", + "eDP_Max_Port_Link_Rate_13" + ], + "HelpText": "This field specifies EDP Max Port Link Rate supported by the port in unit of 200KHz.\nDefault value would be \"0\", in which case Display Drivers should consider EDP Max Port Link Rate to be the Platform supported Max Link Rate.\nOnly when OEM's need to limit to particular Link Rate can enter the value as mentioned in below table.\n\nNote:\n1) OEM's need to enter the values mentioned from below table only.\n2) If value entered is not matching with any of the below values then Platform supported Max Link Rate should be considere as EDP Max Port Link Rate by the display drivers.\n3) In case of EDP Fast Link Training Params(FLT), if user enters FLT Link Rate value greater than the \"eDP Max Port Link Rate\" then we need to use \n Fast Link training Link Rate = MIN (FLT Link Rate , eDP Max Port Link Rate)\n---------------------------------------------------------\n|\tLink Rate(Gbps)\t|\t Value to enter in text field\t|\n|\t \t\t|\t in terms of 200KHZ \t|\n---------------------------------------------------------\n|\t 1.62 \t\t|\t 8100 \t|\n|\t 2.16 \t\t|\t 10800 \t|\n|\t 2.43 \t\t|\t 12150 \t|\n|\t 2.7 \t\t|\t 13500 \t|\n|\t 3.24 \t\t|\t 16200 \t|\n|\t 3.78 \t\t|\t 18900 \t|\n|\t 4.32 \t\t|\t 21600 \t|\n|\t 5.4 \t\t|\t 27000 \t|\n|\t 6.48 \t\t|\t 32400 \t|\n|\t 6.75 \t\t|\t 33750 \t|\n|\t 8.1 \t\t|\t 40500 \t|\n", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Panel Color Depth: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Panel_Color_Depth_13" + ], + "HelpText": "This feature specifies the color depth of eDP panel used.", + "WidgetValues": [ + { + "Key": "18-bit Color Depth", + "Value": "0" + }, + { + "Key": "24-bit Color Depth", + "Value": "1" + }, + { + "Key": "30-bit Color Depth", + "Value": "2" + }, + { + "Key": "36-bit Color Depth", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Select VSwing/Pre-Emphasis table : ", + "Visibility": "", + "Data": [ + "27", + "eDP_VswingPreEmph_13" + ], + "HelpText": "This feature selects the VSwing Pre-Emphasis setting table to be used. For Tigerlake, based on the selection respective table will be used.\nTables for Tigerlake:\nLow Power VSwing Pre-Emphasis Setting Table:\nFor HBR2:\n\t\t\t\t\t\t Pre-Emphasis (db)\n\t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\nVoltage \t\t Level-0/200mV \t\t 200mV, 0.0db \t\t 200mV, 1.9db \t\t 200mV, 3.5db \t\t 200mV, 4.9db\nSwing \t\t Level-1/250mV \t\t 250mV, 0.0db \t\t 250mV, 1.6db \t\t 250mV, 2.9db \t\t N/A\n(mV) \t\t Level-2/300mV \t\t 300mV, 0.0db \t\t 300mV, 1.3db \t\t N/A \t\t N/A\n\t\t Level-3/350mV \t\t 350mV, 0.0db \t\t N/A \t\t N/A \t\t N/A\n\n\nFor HBR3:\n\t\t\t\t\t\t Pre-Emphasis (db)\n\t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\nVoltage \t\t Level-0/350mV \t\t 350mV, 0.0db \t\t 350mV, 3.1db \t\t 350mV, 6.0db \t\t 350mV, 8.2db\nSwing \t\t Level-1/500mV \t\t 500mV, 0.0db \t\t 500mV, 2.9db \t\t 500mV, 5.1db \t\t N/A\n(mV) \t\t Level-2/650mV \t\t 650mV, 0.6db \t\t 600mV, 3.5db \t\t N/A \t\t N/A\n\t\t Level-3/900mV \t\t 900mV, 0.0db \t\t N/A \t\t N/A \t\t N/A\n\n\nDefault VSwing Pre-Emphasis Setting Table:\nFor HBR:\n\t\t\t\t\t\t Pre-Emphasis (db)\n\t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\nVoltage \t\t Level-0/350mV \t\t 350mV, 0.0db \t\t 350mV, 3.1db \t\t 350mV, 6.0db \t\t 350mV, 8.2db\nSwing \t\t Level-1/500mV \t\t 500mV, 0.0db \t\t 500mV, 2.9db \t\t 500mV, 5.1db \t\t N/A\n(mV) \t\t Level-2/650mV \t\t 650mV, 0.6db \t\t 600mV, 3.5db \t\t N/A \t\t N/A\n\t\t Level-3/900mV \t\t 900mV, 0.0db \t\t N/A \t\t N/A \t\t N/A\n\n\nFor HBR2:\n\t\t\t\t\t\t Pre-Emphasis (db)\n\t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\nVoltage \t\t Level-0/350mV \t\t 350mV, 0.0db \t\t 350mV, 3.1db \t\t 350mV, 6.0db \t\t 350mV, 8.2db\nSwing \t\t Level-1/500mV \t\t 500mV, 0.0db \t\t 500mV, 2.9db \t\t 500mV, 5.1db \t\t N/A\n(mV) \t\t Level-2/650mV \t\t 650mV, 0.6db \t\t 600mV, 3.5db \t\t N/A \t\t N/A\n\t\t Level-3/900mV \t\t 900mV, 0.0db \t\t N/A \t\t N/A \t\t N/A", + "WidgetValues": [ + { + "Key": "Default VSwing/Pre-Emphasis Table", + "Value": "1" + }, + { + "Key": "Low Power VSwing/Pre-Emphasis Table", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " eDP Spread Spectrum Clock: ", + "Visibility": "", + "Data": [ + "40", + "Enable_SSC13" + ], + "HelpText": "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Pixel Overlap Count: ", + "Visibility": "", + "Data": [ + "42", + "PixelOverlapCount_13" + ], + "HelpText": "Select the number of Pixels to be overlapped per half of Scanline while using Edp Multi-SST(MSO) feature.", + "WidgetValues": [ + { + "Key": "Zero Pixel Overlap", + "Value": "0" + }, + { + "Key": "One Pixel Overlap", + "Value": "1" + }, + { + "Key": "Two Pixel Overlap", + "Value": "2" + }, + { + "Key": "Three Pixel Overlap", + "Value": "3" + }, + { + "Key": "Four Pixel Overlap", + "Value": "4" + }, + { + "Key": "Five Pixel Overlap", + "Value": "5" + }, + { + "Key": "Six Pixel Overlap", + "Value": "6" + }, + { + "Key": "Seven Pixel Overlap", + "Value": "7" + }, + { + "Key": "Eight Pixel Overlap", + "Value": "8" + } + ] + }, + { + "WidgetType": "Button", + "WidgetName": "PSR Feature", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Apical Feature", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + } + ], + "NestedPages": [ + { + "Type": "Block", + "Block": { + "PageNum": "5-2-13-1", + "PageName": "eDP Panel Power Sequencing Parameters", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " T3 optimization: ", + "Visibility": "", + "Data": [ + "27", + "eDP_T3_Optimization_13" + ], + "HelpText": "This feature enables or disables T3 optimization.\nWhen enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\nWhen disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "LCDVCC to HPD high delay (T3): ", + "Visibility": "", + "Data": [ + "27", + "eDP_Vcc_To_Hpd_Delay_13" + ], + "HelpText": "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\nValid Range: 0 to 200msec", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Valid video data to Backlight Enable delay (T8): ", + "Visibility": "", + "Data": [ + "27", + "eDP_DataOn_To_BkltEnable_Delay_13" + ], + "HelpText": "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\nT8 is inclusive of T7.\nValid Range of T7: 0 to 50msec", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "PWM-On To Backlight Enable delay: ", + "Visibility": "", + "Data": [ + "27", + "eDP_PwmOn_To_Bklt_Enable_Delay_13" + ], + "HelpText": "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\nDelay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\nSo it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Backlight Disable to PWM-Off delay: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Bklt_Disable_To_PwmOff_Delay_13" + ], + "HelpText": "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\nDelay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\nSo it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Backlight Disable to End of Valid video data delay (T9): ", + "Visibility": "", + "Data": [ + "27", + "eDP_BkltDisable_To_DataOff_Delay_13" + ], + "HelpText": "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "End of Valid video data to Power-Off delay (T10): ", + "Visibility": "", + "Data": [ + "27", + "eDP_DataOff_To_PowerOff_Delay_13" + ], + "HelpText": "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\nValid Range: 0 to 500 msec", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Power-off time (T12): ", + "Visibility": "", + "Data": [ + "27", + "eDP_PowerCycle_Delay_13" + ], + "HelpText": "Using this field Power-off time can be specified in 100uS.", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-13-2", + "PageName": "eDP Fast Link Training Configuration Parameters", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Is FastLinkTraining Feature Supported: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Fast_Link_Training_Supported_13" + ], + "HelpText": "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled.", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Data Rate: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Fast_Link_Training_Data_Rate_13" + ], + "HelpText": "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. It will be used if the sink indicates that no aux handshake is required during link training.\n\nIn case of EDP Fast Link Training Params(FLT), if user enters FLT Link Rate value greater than the \"eDP Max Port Link Rate\" then driver would use \n Fast Link training Link Rate = MIN (FLT Link Rate , eDP Max Port Link Rate).", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Lane Count: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Link_LaneCount_13" + ], + "HelpText": "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. It will be used if the sink indicates that no aux handshake is required during link training.", + "WidgetValues": [ + { + "Key": "x1", + "Value": "0" + }, + { + "Key": "x2", + "Value": "1" + }, + { + "Key": "x4", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Pre-Emphasis: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Link_PreEmp_13" + ], + "HelpText": "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. It will be used if the sink indicates that no aux handshake is required during link training.", + "WidgetValues": [ + { + "Key": "Level-0", + "Value": "0" + }, + { + "Key": "Level-1", + "Value": "1" + }, + { + "Key": "Level-2", + "Value": "2" + }, + { + "Key": "Level-3", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Voltage Swing: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Link_Vswing_13" + ], + "HelpText": "This feature allows for the selection of the Voltage Swing value for the embedded DP link. It will be used if the sink indicates that no aux handshake is required during link training.", + "WidgetValues": [ + { + "Key": "Swing-0", + "Value": "0" + }, + { + "Key": "Swing-1", + "Value": "1" + }, + { + "Key": "Swing-2", + "Value": "2" + }, + { + "Key": "Swing-3", + "Value": "3" + } + ] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-13-3", + "PageName": "PSR Feature", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Full Link enable: ", + "Visibility": "", + "Data": [ + "9", + "PSR_FullLink_Enable_13" + ], + "HelpText": "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state.", + "WidgetValues": [ + { + "Key": "No", + "Value": "0" + }, + { + "Key": "Yes", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Require AUX to wake up: ", + "Visibility": "", + "Data": [ + "9", + "PSR_Require_AUX2Wakeup_13" + ], + "HelpText": "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used.", + "WidgetValues": [ + { + "Key": "No", + "Value": "0" + }, + { + "Key": "Yes", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Lines to wait before link standby: ", + "Visibility": "", + "Data": [ + "9", + "PSR_Lines2Wait_B4LinkS3_13" + ], + "HelpText": "This field determines Lines to wait before link standby\n0 lines to wait (Default)\n1 lines to wait\n4 lines to wait\n8 lines to wait\nOthers Reserved", + "WidgetValues": [ + { + "Key": "0 lines to wait", + "Value": "0" + }, + { + "Key": "1 lines to wait", + "Value": "1" + }, + { + "Key": "4 lines to wait", + "Value": "2" + }, + { + "Key": "8 lines to wait", + "Value": "3" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Idle frames to wait: ", + "Visibility": "", + "Data": [ + "9", + "PSR_IdleFrames2Wait_13" + ], + "HelpText": "Idle frames to wait for PSR enable.\nAllowed values 0-15. Default value is 0.", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Clock Recovery Time: ", + "Visibility": "", + "Data": [ + "9", + "PSR_TP1_WaitTime_13" + ], + "HelpText": "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)", + "WidgetValues": [ + { + "Key": "500 usec", + "Value": "0" + }, + { + "Key": "100 usec", + "Value": "1" + }, + { + "Key": "2.5 msec", + "Value": "2" + }, + { + "Key": "0 (Skip)", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Channel Equalization Time for PSR1 panel: ", + "Visibility": "", + "Data": [ + "9", + "PSR1_TP_2_3_4_WaitTime_13" + ], + "HelpText": "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) or TP4(Training Pattern4) time during PSR1 exit(wake up)", + "WidgetValues": [ + { + "Key": "500 usec", + "Value": "0" + }, + { + "Key": "100 usec", + "Value": "1" + }, + { + "Key": "2.5 msec", + "Value": "2" + }, + { + "Key": "0 (Skip)", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Channel Equalization Time for PSR2 panel: ", + "Visibility": "", + "Data": [ + "9", + "PSR2_TP_2_3_4_WaitTime_13" + ], + "HelpText": "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) or TP4(Training Pattern4) time during PSR2 exit(wake up)", + "WidgetValues": [ + { + "Key": "500 usec", + "Value": "0" + }, + { + "Key": "100 usec", + "Value": "1" + }, + { + "Key": "2.5 msec", + "Value": "2" + }, + { + "Key": "50 usec", + "Value": "3" + } + ] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-13-4", + "PageName": "Apical Feature", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Apical Assertive Display IP: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Apical_Display_Ip_Enable_13" + ], + "HelpText": "This field enables/disables the Apical Assertive Display IP for this panel.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Panel OUI (IEEE OUI): ", + "Visibility": "", + "Data": [ + "27", + "eDP_Panel_Oui_13" + ], + "HelpText": "This field specifies the Apical IP specific Panel OUI field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " DPCD Base Address: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Dpcd_Base_Address_13" + ], + "HelpText": "This field specifies the Apical IP specific DPCD base address field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " DPCD Irdidix Control 0: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Dpcd_Irdidix_Control0_13" + ], + "HelpText": "This field specifies the Apical IP specific DPCD Irdidix control 0 field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " DPCD Option Select: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Dpcd_Option_Select_13" + ], + "HelpText": "This field specifies the Apical IP specific DPCD option select field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " DPCD Backlight: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Dpcd_Backlight_13" + ], + "HelpText": "This field specifies the Apical IP specific backlight value.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Ambient Light: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Ambient_Light_13" + ], + "HelpText": "This field specifies the Apical IP specific Ambient light value.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Backlight scale: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Backlight_Scale_13" + ], + "HelpText": "This field specifies the Apical IP specific backlight scale field.", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-13-5", + "PageName": "Power Features", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Intel Display Power Saving Technology (DPST) (Mobile only): ", + "Visibility": "", + "Data": [ + "44", + "DPST_Enable_13" + ], + "HelpText": "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled.\nIntel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power.\nNote: This technology is only active when the system is running in battery mode and the LFP is the only active display device.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Intel Display Refresh Rate Switching (DRRS) (Mobile only): ", + "Visibility": "", + "Data": [ + "44", + "DRRS_Enable_13" + ], + "HelpText": "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Edge Luminance Profile (ELP) : ", + "Visibility": "", + "Data": [ + "44", + "ELP_Enable_13" + ], + "HelpText": "This feature determines whether the ELP feature is enabled or disabled.\nEdge Luminance Profile (ELP) is a panel technology which reduce luminance on the edge of screen to save panel power.\nNote:This technology cannot co-exist with DPST and OPST ((i.e.) OPST, DPST and ELP cannot exist together.They are all mutually exclusive to each other.)", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " OLED Power Saving Technology (OPST) : ", + "Visibility": "", + "Data": [ + "44", + "OPST_Enable_13" + ], + "HelpText": "This feature determines whether the OPST feature is enabled or disabled.\nOLED Power Saving Technology (OPST) is a panel technology which saves power by intelligent, adaptive dimming of midrange pixel values more aggressively than the extremes without compromising the viewability.\nNote: This technology cannot co-exist with ELP and DPST ((i.e.) OPST, DPST and ELP cannot exist together.They are all mutually exclusive to each other.)", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Dynamic Media Refresh Rate Switching Enable/Disable ", + "Visibility": "", + "Data": [ + "44", + "DMRRS_Enable_13" + ], + "HelpText": "This feature determines whether Dynamic media refresh rate switching is to be enabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Enable Display Lace Support: ", + "Visibility": "", + "Data": [ + "44", + "LACE_Enable_13" + ], + "HelpText": "This feature, when enabled, will set Display Lace Support otherwise, the functionality will be disabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Panel Self Refresh (PSR): ", + "Visibility": "", + "Data": [ + "44", + "PSR_Enable_13" + ], + "HelpText": "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Assertive Display Technology Enable/Disable: ", + "Visibility": "", + "Data": [ + "44", + "ADT_Enable_13" + ], + "HelpText": "This feature determines whether Assertive display technology is to be enabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Intel Automatic Display Brightness (ADB) (Mobile only): ", + "Visibility": "", + "Data": [ + "44", + "ADB_Enable_13" + ], + "HelpText": "This feature determines whether Intel Automatic Display Brightness is to be enabled. Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) depending on the current ambient light environment.\nWhen enabled, the driver and VBIOS will control the backlight brightness of the LFP depending on the ambient environment if and only if the LFP is the only active display. When disabled, the driver will perform no action.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "EDP 4k/2k HOBL Feature: ", + "Visibility": "", + "Data": [ + "44", + "eDP_4k_2k_HOBL_feature_Enable_13" + ], + "HelpText": "This feature will allow users to disable/enable the edp 4k/2k HOBL(Hours Of Battery Life) feature by programming relevant registers specific for a platform.\r\n.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Default Display LACE Enabled status: ", + "Visibility": "", + "Data": [ + "44", + "LACE_Status_13" + ], + "HelpText": "This feature, when enabled, will set Default Display LACE Enabled status otherwise, the functionality will be disabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "DPST Aggressiveness Level: ", + "Visibility": "", + "Data": [ + "44", + "DPST_Aggressiveness_Profile_13" + ], + "HelpText": "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n1 (Maximum Quality with No DPST)\n2\n3\n4\n5\n6 (Maximum Battery)", + "WidgetValues": [ + { + "Key": "1 - Maximum Quality with No DPST", + "Value": "1" + }, + { + "Key": "2", + "Value": "2" + }, + { + "Key": "3", + "Value": "3" + }, + { + "Key": "4", + "Value": "4" + }, + { + "Key": "5", + "Value": "5" + }, + { + "Key": "6 - Maximum Battery", + "Value": "6" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "LACE Aggressiveness Level: ", + "Visibility": "", + "Data": [ + "44", + "LACE_Aggressiveness_Profile_13" + ], + "HelpText": "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\nMinimum 0\nModerate 1\nHigh 2", + "WidgetValues": [ + { + "Key": "Minimum", + "Value": "0" + }, + { + "Key": "Moderate", + "Value": "1" + }, + { + "Key": "High", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "ELP Aggressiveness Level: ", + "Visibility": "", + "Data": [ + "44", + "ELP_Aggressiveness_Profile_13" + ], + "HelpText": "This feature allows for the selection of ELP Aggressiveness level for this Panel Type.\nMinimum Power Savings\nMedium Power Savings \nMaximum Power Savings", + "WidgetValues": [ + { + "Key": "Minimum Power Savings", + "Value": "0" + }, + { + "Key": "Medium Power Savings", + "Value": "1" + }, + { + "Key": "Maximum Power Savings", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "OPST Aggressiveness Level: ", + "Visibility": "", + "Data": [ + "44", + "OPST_Aggressiveness_Profile_13" + ], + "HelpText": "This feature allows for the selection of OPST Aggressiveness level for this Panel Type.\nMinimum Power Savings\nMedium Power Savings \nMaximum Power Savings", + "WidgetValues": [ + { + "Key": "Minimum Power Savings", + "Value": "0" + }, + { + "Key": "Medium Power Savings", + "Value": "1" + }, + { + "Key": "Maximum Power Savings", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Default Display VRR Enabled status: ", + "Visibility": "", + "Data": [ + "44", + "VRR_Status_13" + ], + "HelpText": "VRR (Variable Refresh Rate) is a feature that can continuously and seamlessly vary Refresh Rate on the fly, on displays that support Variable Refresh rate Technologies.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-13-6", + "PageName": "Generic DTD Timings", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Pixel Clock in KHz: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_Pixel_CLK_13" + ], + "HelpText": "Pixel Clock (in KHz) Range from 0.001 to 4294967.295 MP/s.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Active: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_Active_13" + ], + "HelpText": "Horizontal Active Image Pixels Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Active: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_Active_13" + ], + "HelpText": "Vertical Active Image Lines Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Blank: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_Blank_13" + ], + "HelpText": "Horizontal Blank Pixels Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Blank: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_Blank_13" + ], + "HelpText": "Vertical Blank lines Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Front Porch: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_FrontPorch_13" + ], + "HelpText": "Horizontal Front Porch Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Front Porch: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_FrontPorch_13" + ], + "HelpText": "Vertical Front Porch Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Sync: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_Sync_13" + ], + "HelpText": "Horizontal Sync Width Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Sync: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_Sync_13" + ], + "HelpText": "Vertical Sync Width Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Image Size: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_Image_Size_13" + ], + "HelpText": "Horizontal Addressable Video Image Size in mm represented by 16bits. Image size multiplier 1.00 mm precision.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Image Size: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_Image_Size_13" + ], + "HelpText": "Vertical Addressable Video Image Size in mm represented by 16bits. Image size multiplier 1.00 mm precision.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryBin", + "WidgetName": "Common Flag: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_Common_Flag_13" + ], + "HelpText": "Common DTD Flags:\nBit 7 : Horizontal Sync Polarity\n1 : Positive\n0 : Negative\nBit 6 : Vertical Sync polarity\n1 : Positive\n0 : Negative\nBit 5 - 0: Reserved (Default value 0)", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-13-7", + "PageName": "LFP PnP ID Table", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Table", + "WidgetName": "", + "Visibility": "", + "Data": [ + "42", + "LFP_Panel_PnP_ID_13" + ], + "HelpText": "This feature allows the 10 bytes of EDID Vendor/Product ID starting at offset 08h to be used as a PnP ID.\n\nTable Definition:\n\tWord: ID Manufacturer Name\n\tWord: ID Product Code\n\tDWord: ID Serial Number\n\tByte: Week of Manufacture\n\tByte: Year of Manufacture", + "WidgetValues": [ + { + "ColumnName": "PnP ID", + "SizeinBytes": "1" + } + ] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-13-8", + "PageName": "Backlight Control Parameters", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Inverter Type: ", + "Visibility": "", + "Data": [ + "43", + "BLC_Inv_Type_13" + ], + "HelpText": "This feature allows for the selection of the Backlight Inverter type that is to be used to control the backlight brightness of the LFP.\nWhen PWM is selected, the driver and VBIOS will control the backlight brightness via the integrated PWM solution for the applicable chipsets.\nWhen None/External is selected, the system BIOS will control the backlight brightness via the external solution.", + "WidgetValues": [ + { + "Key": "None/External", + "Value": "0" + }, + { + "Key": "PWM", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Pwm Source Selection: ", + "Visibility": "", + "Data": [ + "43", + "Lfp_Pwm_Source_Selection_13" + ], + "HelpText": "If panel supports 'Intel HDR AUX Interface', it will always be chosen by default. If not, value in 'PWM Source Selection' will be used", + "WidgetValues": [ + { + "Key": "PWM From Display Engine", + "Value": "2" + }, + { + "Key": "PWM From LCD Panel", + "Value": "3" + }, + { + "Key": "Panel Driver Interface", + "Value": "4" + }, + { + "Key": "VESA eDP AUX Interface", + "Value": "5" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Pwm Controller Selection: ", + "Visibility": "", + "Data": [ + "43", + "Lfp_Pwm_Controller_Selection_13" + ], + "HelpText": "This field allows to select the PWM Controller to be used for the selected Local Flat Panel.This field allows to select the PWM Controller to be used for the selected Local Flat Panel.If Two LFPs are connected then PWM0 and PWM1 must be selected accordingly.", + "WidgetValues": [ + { + "Key": "PWM0", + "Value": "0" + }, + { + "Key": "PWM1", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Inverter Polarity: ", + "Visibility": "", + "Data": [ + "43", + "BLC_Inv_Polarity_13" + ], + "HelpText": "This feature allows the backlight inverter polarity to be specified.\nNormal means 0 value is minimum brightness.\nInverted means 0 value is maximum brightness.", + "WidgetValues": [ + { + "Key": "Normal", + "Value": "0" + }, + { + "Key": "Inverted", + "Value": "1" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Minimum Brightness: ", + "Visibility": "", + "Data": [ + "43", + "Post_Min_Brightness_13" + ], + "HelpText": "This feature allows defining the absolute minimum backlight brightness. The driver will never decrease the backlight less than this value. The value must be specified using normal polarity semantics. The value should range from 0 to 255 if the brightness precision bit is chosen to be 8, and it should range from 0 to 65535 if the precision bit is chosen to be 16.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "POST Backlight Intensity: ", + "Visibility": "", + "Data": [ + "43", + "Post_Brightness_13" + ], + "HelpText": "This feature is used to set default backlight brightness value of the panel at POST. The value should range from 0 to 255 if the bit precision is chosen to be 8 and it should range from 0 to 65535 if the brightness bit precision is chosent to be 16.", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Brightness Precision Bits: ", + "Visibility": "", + "Data": [ + "43", + "BrightnessPrecisionBits_13" + ], + "HelpText": "This field represents the range of brightness in terms of bit precision.\n 8 = Brightness range of 0 to 255.\n 16 = Brightness range of 0 to 65535", + "WidgetValues": [ + { + "Key": "8", + "Value": "8" + }, + { + "Key": "16", + "Value": "16" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "PWM Inverter Frequency (Hz): ", + "Visibility": "", + "Data": [ + "43", + "PWM_Frequency_13" + ], + "HelpText": "This feature allows for the definition of the frequency needed for PWM Inverter.\nNote: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Intel HDR DPCD Refresh Timeout (unit - 10 micro seconds): ", + "Visibility": "", + "Data": [ + "43", + "HdrDpcdRefreshTimeout_13" + ], + "HelpText": "This field allows to configure the refresh timeout of Intel HDR DPCDs for different TCON Vendors.\nNote:\n\tThe value is in units of 10 microseconds.\n\tThe range (entered as a decimal number), for the timeout is 0-65535", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-13-9", + "PageName": "Chromaticity Control", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Chromaticity Control Feature: ", + "Visibility": "", + "Data": [ + "46", + "Chromacity_Enable_13" + ], + "HelpText": "This bit enables Chromaticity feature.\nIf this bit is enabled, EDID values for chromaticity will be used, else feature is disabled.\nFeature will be supported for Panels that support EDID version 1.4 or higher.\nPlease refer to section 3.7 of EDID Specification 1.4.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Override the EDID values: ", + "Visibility": "", + "Data": [ + "46", + "Override_EDID_Data_13" + ], + "HelpText": "This option when enabled along with Chromaticity feature will override EDID values through following VBT data", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Red_Green_bits (Bits 1:0 at 19h): ", + "Visibility": "", + "Data": [ + "46", + "Red_Green_13" + ], + "HelpText": "Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Blue_White_bits (Bits 1:0 at 1Ah): ", + "Visibility": "", + "Data": [ + "46", + "Blue_White_13" + ], + "HelpText": "Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Red_x (Bits 9:2 at 1Bh): ", + "Visibility": "", + "Data": [ + "46", + "Red_x_13" + ], + "HelpText": "Bits 9:2 of red color x coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Red_y (Bits 9:2 at 1Ch): ", + "Visibility": "", + "Data": [ + "46", + "Red_y_13" + ], + "HelpText": "Bits 9:2 of red color y coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Green_x (Bits 9:2 at 1Dh): ", + "Visibility": "", + "Data": [ + "46", + "Green_x_13" + ], + "HelpText": "Bits 9:2 of Green color x coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Green_y (Bits 9:2 at 1Eh): ", + "Visibility": "", + "Data": [ + "46", + "Green_y_13" + ], + "HelpText": "Bits 9:2 of Green color y coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Blue_x (Bits 9:2 at 1Fh): ", + "Visibility": "", + "Data": [ + "46", + "Blue_x_13" + ], + "HelpText": "Bits 9:2 of Blue color x coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Blue_y (Bits 9:2 at 20h): ", + "Visibility": "", + "Data": [ + "46", + "Blue_y_13" + ], + "HelpText": "Bits 9:2 of Blue color y coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " White_x (Bits 9:2 at 21h): ", + "Visibility": "", + "Data": [ + "46", + "White_x_13" + ], + "HelpText": "Bits 9:2 of White color x coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " White_y (Bits 9:2 at 22h): ", + "Visibility": "", + "Data": [ + "46", + "White_y_13" + ], + "HelpText": "Bits 9:2 of White color y coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Override Luminance values ", + "Visibility": "", + "Data": [ + "46", + "Override_LUM_Data_13" + ], + "HelpText": "This option when enabled along with Chromaticity feature will override luminance values following VBT values", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Minimum Luminance: ", + "Visibility": "", + "Data": [ + "46", + "MinLuminance_13" + ], + "HelpText": "Minimum luminance value.\n2 byte value, encoded in IEEE 754 half-precision binary floating point format,", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Maximum full frame luminance: ", + "Visibility": "", + "Data": [ + "46", + "MaxFullLuminance_13" + ], + "HelpText": "Maximum Full frame luminance value.\n2 byte value, encoded in IEEE 754 half-precision binary floating point format,", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Maximum Luminance: ", + "Visibility": "", + "Data": [ + "46", + "MaxLuminance_13" + ], + "HelpText": "Maximum luminance value(Relatively smaller portion of screen).\n2 byte value, encoded in IEEE 754 half-precision binary floating point format.", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Override Gamma values: ", + "Visibility": "", + "Data": [ + "46", + "Override_Gamma_Data_13" + ], + "HelpText": "This option when enabled along with Chromaticity feature will override gamma values through following VBT data", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Panel gamma: ", + "Visibility": "", + "Data": [ + "46", + "Gamma_13" + ], + "HelpText": "Value shall define the gamma range, from 1.00 to 3.54, as follows:\nField Value = (Gamma (value in float) x 100) - 100\nField values range from 00h through FFh.\nFFh = No gamma information shall be provided", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-13-10", + "PageName": "VESA DSC Parameters", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "DSC Major Version: ", + "Visibility": "", + "Data": [ + "56", + "C13_Major_Dsc_Version" + ], + "HelpText": "VESA DSC Major revision field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "DSC Minor Version: ", + "Visibility": "", + "Data": [ + "56", + "C13_Minor_Dsc_Version" + ], + "HelpText": "VESA DSC Minor revision field.", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Block prediction supported: ", + "Visibility": "", + "Data": [ + "56", + "C13_Blk_Prediction_En" + ], + "HelpText": "Sink supports block prediction as per the VESA DSC Spec.", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "RC Buffer Block size as per VESA DSC Spec: ", + "Visibility": "", + "Data": [ + "56", + "C13_RC_Block_Size" + ], + "HelpText": "RC buffer block size for a single RC buffer as defined by the VESA DSC spec.", + "WidgetValues": [ + { + "Key": "1 KB", + "Value": "0" + }, + { + "Key": "4 KB", + "Value": "1" + }, + { + "Key": "16 KB", + "Value": "2" + }, + { + "Key": "64 KB", + "Value": "3" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Number of RC buffer blocks as per VESA DSC Spec: ", + "Visibility": "", + "Data": [ + "56", + "C13_Dsc_RC_Buf_Size" + ], + "HelpText": "This field defines the number of RC buffers as per VESA DSC spec.\nThe number of RC buffers used by the software shall be (Value + 1) where Value is in range 0 to 127.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryBin", + "WidgetName": "Slices per line supported by the sink device: ", + "Visibility": "", + "Data": [ + "56", + "C13_Dsc_Slices_Per_Line" + ], + "HelpText": "This field defines the slices per line supported by the sink device.\nThe field is defined in bitmap fashion and details of each bits are as defined below:\n\tBits 31-10\t\t Bit 9\tBit 8\tBit 7\tBit 6\tBit 5\tBit 4\t Bit 3\t Bit 2\t Bit 1\t Bit 0\n\tReserved\t\t 24\t 20\t 16\t 12\t 10\t 8\t 6\t 4\t 2\t 1\nBit = 0, not supported. Bit = 1, supported\nNote: Assumption is that sink shall support all lower slices per line than maximum selected field. i.e. If it supports say 8 slices per line, it will also support 4/2/1 slices per line", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Line buffer depth as per VESA DSC Spec: ", + "Visibility": "", + "Data": [ + "56", + "C13_Line_Buffer_Depth" + ], + "HelpText": "Line buffer depth in bits as per VESA DSC spec.", + "WidgetValues": [ + { + "Key": "8 bits", + "Value": "0" + }, + { + "Key": "9 bits", + "Value": "1" + }, + { + "Key": "10 bits", + "Value": "2" + }, + { + "Key": "11 bits", + "Value": "3" + }, + { + "Key": "12 bits", + "Value": "4" + }, + { + "Key": "13 bits", + "Value": "5" + }, + { + "Key": "14 bits", + "Value": "6" + }, + { + "Key": "15 bits", + "Value": "7" + }, + { + "Key": "16 bits", + "Value": "8" + } + ] + }, + { + "WidgetType": "EntryBin", + "WidgetName": "Input compression BPC supported by the sink device: ", + "Visibility": "", + "Data": [ + "56", + "C13_Dsc_Bpc" + ], + "HelpText": "This field defines the compression input bpc supported by the sink device.\nThe field is defined in bitmap fashion and details of each bits are as defined below:\n\tBits 7-4\t Bit 3\t Bit 2\t Bit 1\t Bit 0\n\tRsvd\t 12 bpc\t 10bpc\t 8bpc\t Rsvd\nBit = 0, not supported. Bit = 1, supported\nNote: Assumption is that sink shall support all lower bpc values than the maximum selected field. i.e. If it supports say 12bpc, it will also support 10 and 8bpc as well", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Maximum supported compression BPP: ", + "Visibility": "", + "Data": [ + "56", + "C13_Dsc_Max_Bpp" + ], + "HelpText": "As of today, we are supporting 6/8/10/12 BPP for compression output.\nSelect the most appropriate BPP as supported by the sink.", + "WidgetValues": [ + { + "Key": "6 Bits per pixel", + "Value": "0" + }, + { + "Key": "8 Bits per pixel", + "Value": "1" + }, + { + "Key": "10 Bits per pixel", + "Value": "2" + }, + { + "Key": "12 Bits per pixel", + "Value": "3" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Slice height supported by the sink device: ", + "Visibility": "", + "Data": [ + "56", + "C13_Dsc_Slice_Height" + ], + "HelpText": "Slice height supported by the sink device for DSC slice.\nNote: Slice height must divide the picture height uniformly.", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + } + ] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-14", + "PageName": "Panel #14", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "LabelHeading", + "WidgetName": "Common LFP Features", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryAsci", + "WidgetName": " LFP Panel Name: ", + "Visibility": "", + "Data": [ + "42", + "Panel_Name_14" + ], + "HelpText": "This feature defines the LFP panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Target X-Res: ", + "Visibility": "", + "Data": [ + "42", + "Panel_Width_14" + ], + "HelpText": "This value specifies the Target X-Resolution for this panel.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Target Y-Res: ", + "Visibility": "", + "Data": [ + "42", + "Panel_Height_14" + ], + "HelpText": "This value specifies the Target Y-Resolution for this panel.", + "WidgetValues": [] + }, + { + "WidgetType": "LabelHeading", + "WidgetName": " DPS Panel Type Features", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Seamless DRRS Minimum Refresh Rate (Hz): ", + "Visibility": "", + "Data": [ + "42", + "Seamless_DRRS_Min_RR_14" + ], + "HelpText": "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\nNote: Graphics driver will use this field only when EDID support is disabled in VBT configuration.", + "WidgetValues": [] + }, + { + "WidgetType": "LabelHeading", + "WidgetName": " BackLight Technology Type Features", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " BackLight Technology: ", + "Visibility": "", + "Data": [ + "40", + "Blt_Control_14" + ], + "HelpText": "This feature allows OEM to select the Backlight Technology.", + "WidgetValues": [ + { + "Key": "LED Backlight", + "Value": "2" + }, + { + "Key": "CCFL Backlight", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Panel Rotation: ", + "Visibility": "", + "Data": [ + "40", + "Panel_Rotation_14" + ], + "HelpText": "This feature specifies the Panel Rotation of LFP panel used.", + "WidgetValues": [ + { + "Key": "0 degree", + "Value": "0" + }, + { + "Key": "180 degree", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Panel Position: ", + "Visibility": "", + "Data": [ + "40", + "Panel_Position_14" + ], + "HelpText": "This feature specifies the Panel Position of LFP panel used.", + "WidgetValues": [ + { + "Key": "Inside Shell", + "Value": "0" + }, + { + "Key": "Outside Shell", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Dual LFP Port Sync: ", + "Visibility": "", + "Data": [ + "42", + "EnablePortSync_Bit_14" + ], + "HelpText": "This feature will allow users to disable/enable Dual LFP Port Sync and it is applicable for DDI-A, DDI-B in case of eDP and DSI-0, DSI-1 in case of MIPI. \r\n.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " GPU Dithering for Banding artifacts: ", + "Visibility": "", + "Data": [ + "42", + "EnableDithering_Bit_14" + ], + "HelpText": "This field can be used to enable dithering from the source side for reducing banding artifacts on the visual quality features like DPST.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "Button", + "WidgetName": "Power Features", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Generic DTD Timings", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "LFP PnP ID Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Backlight Control Parameters", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Chromaticity Control", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "VESA DSC Parameters", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "LabelHeading", + "WidgetName": "Integrated eDP Settings", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "eDP Fast Link Training Configuration Parameters", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "eDP Panel Power Sequencing Parameters", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Edp Max Port Link Rate (in 200 Khz): ", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [ + "27", + "eDP_Max_Port_Link_Rate_14" + ], + "HelpText": "This field specifies EDP Max Port Link Rate supported by the port in unit of 200KHz.\nDefault value would be \"0\", in which case Display Drivers should consider EDP Max Port Link Rate to be the Platform supported Max Link Rate.\nOnly when OEM's need to limit to particular Link Rate can enter the value as mentioned in below table.\n\nNote:\n1) OEM's need to enter the values mentioned from below table only.\n2) If value entered is not matching with any of the below values then Platform supported Max Link Rate should be considere as EDP Max Port Link Rate by the display drivers.\n3) In case of EDP Fast Link Training Params(FLT), if user enters FLT Link Rate value greater than the \"eDP Max Port Link Rate\" then we need to use \n Fast Link training Link Rate = MIN (FLT Link Rate , eDP Max Port Link Rate)\n---------------------------------------------------------\n|\tLink Rate(Gbps)\t|\t Value to enter in text field\t|\n|\t \t\t|\t in terms of 200KHZ \t|\n---------------------------------------------------------\n|\t 1.62 \t\t|\t 8100 \t|\n|\t 2.16 \t\t|\t 10800 \t|\n|\t 2.43 \t\t|\t 12150 \t|\n|\t 2.7 \t\t|\t 13500 \t|\n|\t 3.24 \t\t|\t 16200 \t|\n|\t 3.78 \t\t|\t 18900 \t|\n|\t 4.32 \t\t|\t 21600 \t|\n|\t 5.4 \t\t|\t 27000 \t|\n|\t 6.48 \t\t|\t 32400 \t|\n|\t 6.75 \t\t|\t 33750 \t|\n|\t 8.1 \t\t|\t 40500 \t|\n", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Panel Color Depth: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Panel_Color_Depth_14" + ], + "HelpText": "This feature specifies the color depth of eDP panel used.", + "WidgetValues": [ + { + "Key": "18-bit Color Depth", + "Value": "0" + }, + { + "Key": "24-bit Color Depth", + "Value": "1" + }, + { + "Key": "30-bit Color Depth", + "Value": "2" + }, + { + "Key": "36-bit Color Depth", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Select VSwing/Pre-Emphasis table : ", + "Visibility": "", + "Data": [ + "27", + "eDP_VswingPreEmph_14" + ], + "HelpText": "This feature selects the VSwing Pre-Emphasis setting table to be used. For Tigerlake, based on the selection respective table will be used.\nTables for Tigerlake:\nLow Power VSwing Pre-Emphasis Setting Table:\nFor HBR2:\n\t\t\t\t\t\t Pre-Emphasis (db)\n\t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\nVoltage \t\t Level-0/200mV \t\t 200mV, 0.0db \t\t 200mV, 1.9db \t\t 200mV, 3.5db \t\t 200mV, 4.9db\nSwing \t\t Level-1/250mV \t\t 250mV, 0.0db \t\t 250mV, 1.6db \t\t 250mV, 2.9db \t\t N/A\n(mV) \t\t Level-2/300mV \t\t 300mV, 0.0db \t\t 300mV, 1.3db \t\t N/A \t\t N/A\n\t\t Level-3/350mV \t\t 350mV, 0.0db \t\t N/A \t\t N/A \t\t N/A\n\n\nFor HBR3:\n\t\t\t\t\t\t Pre-Emphasis (db)\n\t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\nVoltage \t\t Level-0/350mV \t\t 350mV, 0.0db \t\t 350mV, 3.1db \t\t 350mV, 6.0db \t\t 350mV, 8.2db\nSwing \t\t Level-1/500mV \t\t 500mV, 0.0db \t\t 500mV, 2.9db \t\t 500mV, 5.1db \t\t N/A\n(mV) \t\t Level-2/650mV \t\t 650mV, 0.6db \t\t 600mV, 3.5db \t\t N/A \t\t N/A\n\t\t Level-3/900mV \t\t 900mV, 0.0db \t\t N/A \t\t N/A \t\t N/A\n\n\nDefault VSwing Pre-Emphasis Setting Table:\nFor HBR:\n\t\t\t\t\t\t Pre-Emphasis (db)\n\t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\nVoltage \t\t Level-0/350mV \t\t 350mV, 0.0db \t\t 350mV, 3.1db \t\t 350mV, 6.0db \t\t 350mV, 8.2db\nSwing \t\t Level-1/500mV \t\t 500mV, 0.0db \t\t 500mV, 2.9db \t\t 500mV, 5.1db \t\t N/A\n(mV) \t\t Level-2/650mV \t\t 650mV, 0.6db \t\t 600mV, 3.5db \t\t N/A \t\t N/A\n\t\t Level-3/900mV \t\t 900mV, 0.0db \t\t N/A \t\t N/A \t\t N/A\n\n\nFor HBR2:\n\t\t\t\t\t\t Pre-Emphasis (db)\n\t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\nVoltage \t\t Level-0/350mV \t\t 350mV, 0.0db \t\t 350mV, 3.1db \t\t 350mV, 6.0db \t\t 350mV, 8.2db\nSwing \t\t Level-1/500mV \t\t 500mV, 0.0db \t\t 500mV, 2.9db \t\t 500mV, 5.1db \t\t N/A\n(mV) \t\t Level-2/650mV \t\t 650mV, 0.6db \t\t 600mV, 3.5db \t\t N/A \t\t N/A\n\t\t Level-3/900mV \t\t 900mV, 0.0db \t\t N/A \t\t N/A \t\t N/A", + "WidgetValues": [ + { + "Key": "Default VSwing/Pre-Emphasis Table", + "Value": "1" + }, + { + "Key": "Low Power VSwing/Pre-Emphasis Table", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " eDP Spread Spectrum Clock: ", + "Visibility": "", + "Data": [ + "40", + "Enable_SSC14" + ], + "HelpText": "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Pixel Overlap Count: ", + "Visibility": "", + "Data": [ + "42", + "PixelOverlapCount_14" + ], + "HelpText": "Select the number of Pixels to be overlapped per half of Scanline while using Edp Multi-SST(MSO) feature.", + "WidgetValues": [ + { + "Key": "Zero Pixel Overlap", + "Value": "0" + }, + { + "Key": "One Pixel Overlap", + "Value": "1" + }, + { + "Key": "Two Pixel Overlap", + "Value": "2" + }, + { + "Key": "Three Pixel Overlap", + "Value": "3" + }, + { + "Key": "Four Pixel Overlap", + "Value": "4" + }, + { + "Key": "Five Pixel Overlap", + "Value": "5" + }, + { + "Key": "Six Pixel Overlap", + "Value": "6" + }, + { + "Key": "Seven Pixel Overlap", + "Value": "7" + }, + { + "Key": "Eight Pixel Overlap", + "Value": "8" + } + ] + }, + { + "WidgetType": "Button", + "WidgetName": "PSR Feature", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Apical Feature", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + } + ], + "NestedPages": [ + { + "Type": "Block", + "Block": { + "PageNum": "5-2-14-1", + "PageName": "eDP Panel Power Sequencing Parameters", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " T3 optimization: ", + "Visibility": "", + "Data": [ + "27", + "eDP_T3_Optimization_14" + ], + "HelpText": "This feature enables or disables T3 optimization.\nWhen enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\nWhen disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "LCDVCC to HPD high delay (T3): ", + "Visibility": "", + "Data": [ + "27", + "eDP_Vcc_To_Hpd_Delay_14" + ], + "HelpText": "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\nValid Range: 0 to 200msec", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Valid video data to Backlight Enable delay (T8): ", + "Visibility": "", + "Data": [ + "27", + "eDP_DataOn_To_BkltEnable_Delay_14" + ], + "HelpText": "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\nT8 is inclusive of T7.\nValid Range of T7: 0 to 50msec", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "PWM-On To Backlight Enable delay: ", + "Visibility": "", + "Data": [ + "27", + "eDP_PwmOn_To_Bklt_Enable_Delay_14" + ], + "HelpText": "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\nDelay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\nSo it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Backlight Disable to PWM-Off delay: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Bklt_Disable_To_PwmOff_Delay_14" + ], + "HelpText": "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\nDelay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\nSo it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Backlight Disable to End of Valid video data delay (T9): ", + "Visibility": "", + "Data": [ + "27", + "eDP_BkltDisable_To_DataOff_Delay_14" + ], + "HelpText": "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "End of Valid video data to Power-Off delay (T10): ", + "Visibility": "", + "Data": [ + "27", + "eDP_DataOff_To_PowerOff_Delay_14" + ], + "HelpText": "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\nValid Range: 0 to 500 msec", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Power-off time (T12): ", + "Visibility": "", + "Data": [ + "27", + "eDP_PowerCycle_Delay_14" + ], + "HelpText": "Using this field Power-off time can be specified in 100uS.", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-14-2", + "PageName": "eDP Fast Link Training Configuration Parameters", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Is FastLinkTraining Feature Supported: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Fast_Link_Training_Supported_14" + ], + "HelpText": "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled.", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Data Rate: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Fast_Link_Training_Data_Rate_14" + ], + "HelpText": "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. It will be used if the sink indicates that no aux handshake is required during link training.\n\nIn case of EDP Fast Link Training Params(FLT), if user enters FLT Link Rate value greater than the \"eDP Max Port Link Rate\" then driver would use \n Fast Link training Link Rate = MIN (FLT Link Rate , eDP Max Port Link Rate).", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Lane Count: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Link_LaneCount_14" + ], + "HelpText": "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. It will be used if the sink indicates that no aux handshake is required during link training.", + "WidgetValues": [ + { + "Key": "x1", + "Value": "0" + }, + { + "Key": "x2", + "Value": "1" + }, + { + "Key": "x4", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Pre-Emphasis: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Link_PreEmp_14" + ], + "HelpText": "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. It will be used if the sink indicates that no aux handshake is required during link training.", + "WidgetValues": [ + { + "Key": "Level-0", + "Value": "0" + }, + { + "Key": "Level-1", + "Value": "1" + }, + { + "Key": "Level-2", + "Value": "2" + }, + { + "Key": "Level-3", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Voltage Swing: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Link_Vswing_14" + ], + "HelpText": "This feature allows for the selection of the Voltage Swing value for the embedded DP link. It will be used if the sink indicates that no aux handshake is required during link training.", + "WidgetValues": [ + { + "Key": "Swing-0", + "Value": "0" + }, + { + "Key": "Swing-1", + "Value": "1" + }, + { + "Key": "Swing-2", + "Value": "2" + }, + { + "Key": "Swing-3", + "Value": "3" + } + ] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-14-3", + "PageName": "PSR Feature", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Full Link enable: ", + "Visibility": "", + "Data": [ + "9", + "PSR_FullLink_Enable_14" + ], + "HelpText": "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state.", + "WidgetValues": [ + { + "Key": "No", + "Value": "0" + }, + { + "Key": "Yes", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Require AUX to wake up: ", + "Visibility": "", + "Data": [ + "9", + "PSR_Require_AUX2Wakeup_14" + ], + "HelpText": "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used.", + "WidgetValues": [ + { + "Key": "No", + "Value": "0" + }, + { + "Key": "Yes", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Lines to wait before link standby: ", + "Visibility": "", + "Data": [ + "9", + "PSR_Lines2Wait_B4LinkS3_14" + ], + "HelpText": "This field determines Lines to wait before link standby\n0 lines to wait (Default)\n1 lines to wait\n4 lines to wait\n8 lines to wait\nOthers Reserved", + "WidgetValues": [ + { + "Key": "0 lines to wait", + "Value": "0" + }, + { + "Key": "1 lines to wait", + "Value": "1" + }, + { + "Key": "4 lines to wait", + "Value": "2" + }, + { + "Key": "8 lines to wait", + "Value": "3" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Idle frames to wait: ", + "Visibility": "", + "Data": [ + "9", + "PSR_IdleFrames2Wait_14" + ], + "HelpText": "Idle frames to wait for PSR enable.\nAllowed values 0-15. Default value is 0.", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Clock Recovery Time: ", + "Visibility": "", + "Data": [ + "9", + "PSR_TP1_WaitTime_14" + ], + "HelpText": "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)", + "WidgetValues": [ + { + "Key": "500 usec", + "Value": "0" + }, + { + "Key": "100 usec", + "Value": "1" + }, + { + "Key": "2.5 msec", + "Value": "2" + }, + { + "Key": "0 (Skip)", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Channel Equalization Time for PSR1 panel: ", + "Visibility": "", + "Data": [ + "9", + "PSR1_TP_2_3_4_WaitTime_14" + ], + "HelpText": "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) or TP4(Training Pattern4) time during PSR1 exit(wake up)", + "WidgetValues": [ + { + "Key": "500 usec", + "Value": "0" + }, + { + "Key": "100 usec", + "Value": "1" + }, + { + "Key": "2.5 msec", + "Value": "2" + }, + { + "Key": "0 (Skip)", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Channel Equalization Time for PSR2 panel: ", + "Visibility": "", + "Data": [ + "9", + "PSR2_TP_2_3_4_WaitTime_14" + ], + "HelpText": "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) or TP4(Training Pattern4) time during PSR2 exit(wake up)", + "WidgetValues": [ + { + "Key": "500 usec", + "Value": "0" + }, + { + "Key": "100 usec", + "Value": "1" + }, + { + "Key": "2.5 msec", + "Value": "2" + }, + { + "Key": "50 usec", + "Value": "3" + } + ] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-14-4", + "PageName": "Apical Feature", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Apical Assertive Display IP: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Apical_Display_Ip_Enable_14" + ], + "HelpText": "This field enables/disables the Apical Assertive Display IP for this panel.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Panel OUI (IEEE OUI): ", + "Visibility": "", + "Data": [ + "27", + "eDP_Panel_Oui_14" + ], + "HelpText": "This field specifies the Apical IP specific Panel OUI field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " DPCD Base Address: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Dpcd_Base_Address_14" + ], + "HelpText": "This field specifies the Apical IP specific DPCD base address field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " DPCD Irdidix Control 0: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Dpcd_Irdidix_Control0_14" + ], + "HelpText": "This field specifies the Apical IP specific DPCD Irdidix control 0 field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " DPCD Option Select: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Dpcd_Option_Select_14" + ], + "HelpText": "This field specifies the Apical IP specific DPCD option select field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " DPCD Backlight: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Dpcd_Backlight_14" + ], + "HelpText": "This field specifies the Apical IP specific backlight value.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Ambient Light: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Ambient_Light_14" + ], + "HelpText": "This field specifies the Apical IP specific Ambient light value.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Backlight scale: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Backlight_Scale_14" + ], + "HelpText": "This field specifies the Apical IP specific backlight scale field.", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-14-5", + "PageName": "Power Features", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Intel Display Power Saving Technology (DPST) (Mobile only): ", + "Visibility": "", + "Data": [ + "44", + "DPST_Enable_14" + ], + "HelpText": "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled.\nIntel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power.\nNote: This technology is only active when the system is running in battery mode and the LFP is the only active display device.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Intel Display Refresh Rate Switching (DRRS) (Mobile only): ", + "Visibility": "", + "Data": [ + "44", + "DRRS_Enable_14" + ], + "HelpText": "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Edge Luminance Profile (ELP) : ", + "Visibility": "", + "Data": [ + "44", + "ELP_Enable_14" + ], + "HelpText": "This feature determines whether the ELP feature is enabled or disabled.\nEdge Luminance Profile (ELP) is a panel technology which reduce luminance on the edge of screen to save panel power.\nNote:This technology cannot co-exist with DPST and OPST ((i.e.) OPST, DPST and ELP cannot exist together.They are all mutually exclusive to each other.)", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " OLED Power Saving Technology (OPST) : ", + "Visibility": "", + "Data": [ + "44", + "OPST_Enable_14" + ], + "HelpText": "This feature determines whether the OPST feature is enabled or disabled.\nOLED Power Saving Technology (OPST) is a panel technology which saves power by intelligent, adaptive dimming of midrange pixel values more aggressively than the extremes without compromising the viewability.\nNote: This technology cannot co-exist with ELP and DPST ((i.e.) OPST, DPST and ELP cannot exist together.They are all mutually exclusive to each other.)", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Dynamic Media Refresh Rate Switching Enable/Disable ", + "Visibility": "", + "Data": [ + "44", + "DMRRS_Enable_14" + ], + "HelpText": "This feature determines whether Dynamic media refresh rate switching is to be enabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Enable Display Lace Support: ", + "Visibility": "", + "Data": [ + "44", + "LACE_Enable_14" + ], + "HelpText": "This feature, when enabled, will set Display Lace Support otherwise, the functionality will be disabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Panel Self Refresh (PSR): ", + "Visibility": "", + "Data": [ + "44", + "PSR_Enable_14" + ], + "HelpText": "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Assertive Display Technology Enable/Disable: ", + "Visibility": "", + "Data": [ + "44", + "ADT_Enable_14" + ], + "HelpText": "This feature determines whether Assertive display technology is to be enabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Intel Automatic Display Brightness (ADB) (Mobile only): ", + "Visibility": "", + "Data": [ + "44", + "ADB_Enable_14" + ], + "HelpText": "This feature determines whether Intel Automatic Display Brightness is to be enabled. Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) depending on the current ambient light environment.\nWhen enabled, the driver and VBIOS will control the backlight brightness of the LFP depending on the ambient environment if and only if the LFP is the only active display. When disabled, the driver will perform no action.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "EDP 4k/2k HOBL Feature: ", + "Visibility": "", + "Data": [ + "44", + "eDP_4k_2k_HOBL_feature_Enable_14" + ], + "HelpText": "This feature will allow users to disable/enable the edp 4k/2k HOBL(Hours Of Battery Life) feature by programming relevant registers specific for a platform.\r\n.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Default Display LACE Enabled status: ", + "Visibility": "", + "Data": [ + "44", + "LACE_Status_14" + ], + "HelpText": "This feature, when enabled, will set Default Display LACE Enabled status otherwise, the functionality will be disabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "DPST Aggressiveness Level: ", + "Visibility": "", + "Data": [ + "44", + "DPST_Aggressiveness_Profile_14" + ], + "HelpText": "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n1 (Maximum Quality with No DPST)\n2\n3\n4\n5\n6 (Maximum Battery)", + "WidgetValues": [ + { + "Key": "1 - Maximum Quality with No DPST", + "Value": "1" + }, + { + "Key": "2", + "Value": "2" + }, + { + "Key": "3", + "Value": "3" + }, + { + "Key": "4", + "Value": "4" + }, + { + "Key": "5", + "Value": "5" + }, + { + "Key": "6 - Maximum Battery", + "Value": "6" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "LACE Aggressiveness Level: ", + "Visibility": "", + "Data": [ + "44", + "LACE_Aggressiveness_Profile_14" + ], + "HelpText": "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\nMinimum 0\nModerate 1\nHigh 2", + "WidgetValues": [ + { + "Key": "Minimum", + "Value": "0" + }, + { + "Key": "Moderate", + "Value": "1" + }, + { + "Key": "High", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "ELP Aggressiveness Level: ", + "Visibility": "", + "Data": [ + "44", + "ELP_Aggressiveness_Profile_14" + ], + "HelpText": "This feature allows for the selection of ELP Aggressiveness level for this Panel Type.\nMinimum Power Savings\nMedium Power Savings \nMaximum Power Savings", + "WidgetValues": [ + { + "Key": "Minimum Power Savings", + "Value": "0" + }, + { + "Key": "Medium Power Savings", + "Value": "1" + }, + { + "Key": "Maximum Power Savings", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "OPST Aggressiveness Level: ", + "Visibility": "", + "Data": [ + "44", + "OPST_Aggressiveness_Profile_14" + ], + "HelpText": "This feature allows for the selection of OPST Aggressiveness level for this Panel Type.\nMinimum Power Savings\nMedium Power Savings \nMaximum Power Savings", + "WidgetValues": [ + { + "Key": "Minimum Power Savings", + "Value": "0" + }, + { + "Key": "Medium Power Savings", + "Value": "1" + }, + { + "Key": "Maximum Power Savings", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Default Display VRR Enabled status: ", + "Visibility": "", + "Data": [ + "44", + "VRR_Status_14" + ], + "HelpText": "VRR (Variable Refresh Rate) is a feature that can continuously and seamlessly vary Refresh Rate on the fly, on displays that support Variable Refresh rate Technologies.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-14-6", + "PageName": "Generic DTD Timings", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Pixel Clock in KHz: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_Pixel_CLK_14" + ], + "HelpText": "Pixel Clock (in KHz) Range from 0.001 to 4294967.295 MP/s.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Active: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_Active_14" + ], + "HelpText": "Horizontal Active Image Pixels Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Active: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_Active_14" + ], + "HelpText": "Vertical Active Image Lines Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Blank: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_Blank_14" + ], + "HelpText": "Horizontal Blank Pixels Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Blank: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_Blank_14" + ], + "HelpText": "Vertical Blank lines Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Front Porch: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_FrontPorch_14" + ], + "HelpText": "Horizontal Front Porch Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Front Porch: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_FrontPorch_14" + ], + "HelpText": "Vertical Front Porch Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Sync: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_Sync_14" + ], + "HelpText": "Horizontal Sync Width Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Sync: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_Sync_14" + ], + "HelpText": "Vertical Sync Width Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Image Size: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_Image_Size_14" + ], + "HelpText": "Horizontal Addressable Video Image Size in mm represented by 16bits. Image size multiplier 1.00 mm precision.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Image Size: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_Image_Size_14" + ], + "HelpText": "Vertical Addressable Video Image Size in mm represented by 16bits. Image size multiplier 1.00 mm precision.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryBin", + "WidgetName": "Common Flag: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_Common_Flag_14" + ], + "HelpText": "Common DTD Flags:\nBit 7 : Horizontal Sync Polarity\n1 : Positive\n0 : Negative\nBit 6 : Vertical Sync polarity\n1 : Positive\n0 : Negative\nBit 5 - 0: Reserved (Default value 0)", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-14-7", + "PageName": "LFP PnP ID Table", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Table", + "WidgetName": "", + "Visibility": "", + "Data": [ + "42", + "LFP_Panel_PnP_ID_14" + ], + "HelpText": "This feature allows the 10 bytes of EDID Vendor/Product ID starting at offset 08h to be used as a PnP ID.\n\nTable Definition:\n\tWord: ID Manufacturer Name\n\tWord: ID Product Code\n\tDWord: ID Serial Number\n\tByte: Week of Manufacture\n\tByte: Year of Manufacture", + "WidgetValues": [ + { + "ColumnName": "PnP ID", + "SizeinBytes": "1" + } + ] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-14-8", + "PageName": "Backlight Control Parameters", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Inverter Type: ", + "Visibility": "", + "Data": [ + "43", + "BLC_Inv_Type_14" + ], + "HelpText": "This feature allows for the selection of the Backlight Inverter type that is to be used to control the backlight brightness of the LFP.\nWhen PWM is selected, the driver and VBIOS will control the backlight brightness via the integrated PWM solution for the applicable chipsets.\nWhen None/External is selected, the system BIOS will control the backlight brightness via the external solution.", + "WidgetValues": [ + { + "Key": "None/External", + "Value": "0" + }, + { + "Key": "PWM", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Pwm Source Selection: ", + "Visibility": "", + "Data": [ + "43", + "Lfp_Pwm_Source_Selection_14" + ], + "HelpText": "If panel supports 'Intel HDR AUX Interface', it will always be chosen by default. If not, value in 'PWM Source Selection' will be used", + "WidgetValues": [ + { + "Key": "PWM From Display Engine", + "Value": "2" + }, + { + "Key": "PWM From LCD Panel", + "Value": "3" + }, + { + "Key": "Panel Driver Interface", + "Value": "4" + }, + { + "Key": "VESA eDP AUX Interface", + "Value": "5" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Pwm Controller Selection: ", + "Visibility": "", + "Data": [ + "43", + "Lfp_Pwm_Controller_Selection_14" + ], + "HelpText": "This field allows to select the PWM Controller to be used for the selected Local Flat Panel.This field allows to select the PWM Controller to be used for the selected Local Flat Panel.If Two LFPs are connected then PWM0 and PWM1 must be selected accordingly.", + "WidgetValues": [ + { + "Key": "PWM0", + "Value": "0" + }, + { + "Key": "PWM1", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Inverter Polarity: ", + "Visibility": "", + "Data": [ + "43", + "BLC_Inv_Polarity_14" + ], + "HelpText": "This feature allows the backlight inverter polarity to be specified.\nNormal means 0 value is minimum brightness.\nInverted means 0 value is maximum brightness.", + "WidgetValues": [ + { + "Key": "Normal", + "Value": "0" + }, + { + "Key": "Inverted", + "Value": "1" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Minimum Brightness: ", + "Visibility": "", + "Data": [ + "43", + "Post_Min_Brightness_14" + ], + "HelpText": "This feature allows defining the absolute minimum backlight brightness. The driver will never decrease the backlight less than this value. The value must be specified using normal polarity semantics. The value should range from 0 to 255 if the brightness precision bit is chosen to be 8, and it should range from 0 to 65535 if the precision bit is chosen to be 16.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "POST Backlight Intensity: ", + "Visibility": "", + "Data": [ + "43", + "Post_Brightness_14" + ], + "HelpText": "This feature is used to set default backlight brightness value of the panel at POST. The value should range from 0 to 255 if the bit precision is chosen to be 8 and it should range from 0 to 65535 if the brightness bit precision is chosent to be 16.", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Brightness Precision Bits: ", + "Visibility": "", + "Data": [ + "43", + "BrightnessPrecisionBits_14" + ], + "HelpText": "This field represents the range of brightness in terms of bit precision.\n 8 = Brightness range of 0 to 255.\n 16 = Brightness range of 0 to 65535", + "WidgetValues": [ + { + "Key": "8", + "Value": "8" + }, + { + "Key": "16", + "Value": "16" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "PWM Inverter Frequency (Hz): ", + "Visibility": "", + "Data": [ + "43", + "PWM_Frequency_14" + ], + "HelpText": "This feature allows for the definition of the frequency needed for PWM Inverter.\nNote: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Intel HDR DPCD Refresh Timeout (unit - 10 micro seconds): ", + "Visibility": "", + "Data": [ + "43", + "HdrDpcdRefreshTimeout_14" + ], + "HelpText": "This field allows to configure the refresh timeout of Intel HDR DPCDs for different TCON Vendors.\nNote:\n\tThe value is in units of 10 microseconds.\n\tThe range (entered as a decimal number), for the timeout is 0-65535", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-14-9", + "PageName": "Chromaticity Control", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Chromaticity Control Feature: ", + "Visibility": "", + "Data": [ + "46", + "Chromacity_Enable_14" + ], + "HelpText": "This bit enables Chromaticity feature.\nIf this bit is enabled, EDID values for chromaticity will be used, else feature is disabled.\nFeature will be supported for Panels that support EDID version 1.4 or higher.\nPlease refer to section 3.7 of EDID Specification 1.4.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Override the EDID values: ", + "Visibility": "", + "Data": [ + "46", + "Override_EDID_Data_14" + ], + "HelpText": "This option when enabled along with Chromaticity feature will override EDID values through following VBT data", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Red_Green_bits (Bits 1:0 at 19h): ", + "Visibility": "", + "Data": [ + "46", + "Red_Green_14" + ], + "HelpText": "Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Blue_White_bits (Bits 1:0 at 1Ah): ", + "Visibility": "", + "Data": [ + "46", + "Blue_White_14" + ], + "HelpText": "Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Red_x (Bits 9:2 at 1Bh): ", + "Visibility": "", + "Data": [ + "46", + "Red_x_14" + ], + "HelpText": "Bits 9:2 of red color x coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Red_y (Bits 9:2 at 1Ch): ", + "Visibility": "", + "Data": [ + "46", + "Red_y_14" + ], + "HelpText": "Bits 9:2 of red color y coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Green_x (Bits 9:2 at 1Dh): ", + "Visibility": "", + "Data": [ + "46", + "Green_x_14" + ], + "HelpText": "Bits 9:2 of Green color x coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Green_y (Bits 9:2 at 1Eh): ", + "Visibility": "", + "Data": [ + "46", + "Green_y_14" + ], + "HelpText": "Bits 9:2 of Green color y coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Blue_x (Bits 9:2 at 1Fh): ", + "Visibility": "", + "Data": [ + "46", + "Blue_x_14" + ], + "HelpText": "Bits 9:2 of Blue color x coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Blue_y (Bits 9:2 at 20h): ", + "Visibility": "", + "Data": [ + "46", + "Blue_y_14" + ], + "HelpText": "Bits 9:2 of Blue color y coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " White_x (Bits 9:2 at 21h): ", + "Visibility": "", + "Data": [ + "46", + "White_x_14" + ], + "HelpText": "Bits 9:2 of White color x coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " White_y (Bits 9:2 at 22h): ", + "Visibility": "", + "Data": [ + "46", + "White_y_14" + ], + "HelpText": "Bits 9:2 of White color y coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Override Luminance values ", + "Visibility": "", + "Data": [ + "46", + "Override_LUM_Data_14" + ], + "HelpText": "This option when enabled along with Chromaticity feature will override luminance values following VBT values", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Minimum Luminance: ", + "Visibility": "", + "Data": [ + "46", + "MinLuminance_14" + ], + "HelpText": "Minimum luminance value.\n2 byte value, encoded in IEEE 754 half-precision binary floating point format,", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Maximum full frame luminance: ", + "Visibility": "", + "Data": [ + "46", + "MaxFullLuminance_14" + ], + "HelpText": "Maximum Full frame luminance value.\n2 byte value, encoded in IEEE 754 half-precision binary floating point format,", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Maximum Luminance: ", + "Visibility": "", + "Data": [ + "46", + "MaxLuminance_14" + ], + "HelpText": "Maximum luminance value(Relatively smaller portion of screen).\n2 byte value, encoded in IEEE 754 half-precision binary floating point format.", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Override Gamma values: ", + "Visibility": "", + "Data": [ + "46", + "Override_Gamma_Data_14" + ], + "HelpText": "This option when enabled along with Chromaticity feature will override gamma values through following VBT data", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Panel gamma: ", + "Visibility": "", + "Data": [ + "46", + "Gamma_14" + ], + "HelpText": "Value shall define the gamma range, from 1.00 to 3.54, as follows:\nField Value = (Gamma (value in float) x 100) - 100\nField values range from 00h through FFh.\nFFh = No gamma information shall be provided", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-14-10", + "PageName": "VESA DSC Parameters", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "DSC Major Version: ", + "Visibility": "", + "Data": [ + "56", + "C14_Major_Dsc_Version" + ], + "HelpText": "VESA DSC Major revision field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "DSC Minor Version: ", + "Visibility": "", + "Data": [ + "56", + "C14_Minor_Dsc_Version" + ], + "HelpText": "VESA DSC Minor revision field.", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Block prediction supported: ", + "Visibility": "", + "Data": [ + "56", + "C14_Blk_Prediction_En" + ], + "HelpText": "Sink supports block prediction as per the VESA DSC Spec.", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "RC Buffer Block size as per VESA DSC Spec: ", + "Visibility": "", + "Data": [ + "56", + "C14_RC_Block_Size" + ], + "HelpText": "RC buffer block size for a single RC buffer as defined by the VESA DSC spec.", + "WidgetValues": [ + { + "Key": "1 KB", + "Value": "0" + }, + { + "Key": "4 KB", + "Value": "1" + }, + { + "Key": "16 KB", + "Value": "2" + }, + { + "Key": "64 KB", + "Value": "3" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Number of RC buffer blocks as per VESA DSC Spec: ", + "Visibility": "", + "Data": [ + "56", + "C14_Dsc_RC_Buf_Size" + ], + "HelpText": "This field defines the number of RC buffers as per VESA DSC spec.\nThe number of RC buffers used by the software shall be (Value + 1) where Value is in range 0 to 127.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryBin", + "WidgetName": "Slices per line supported by the sink device: ", + "Visibility": "", + "Data": [ + "56", + "C14_Dsc_Slices_Per_Line" + ], + "HelpText": "This field defines the slices per line supported by the sink device.\nThe field is defined in bitmap fashion and details of each bits are as defined below:\n\tBits 31-10\t\t Bit 9\tBit 8\tBit 7\tBit 6\tBit 5\tBit 4\t Bit 3\t Bit 2\t Bit 1\t Bit 0\n\tReserved\t\t 24\t 20\t 16\t 12\t 10\t 8\t 6\t 4\t 2\t 1\nBit = 0, not supported. Bit = 1, supported\nNote: Assumption is that sink shall support all lower slices per line than maximum selected field. i.e. If it supports say 8 slices per line, it will also support 4/2/1 slices per line", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Line buffer depth as per VESA DSC Spec: ", + "Visibility": "", + "Data": [ + "56", + "C14_Line_Buffer_Depth" + ], + "HelpText": "Line buffer depth in bits as per VESA DSC spec.", + "WidgetValues": [ + { + "Key": "8 bits", + "Value": "0" + }, + { + "Key": "9 bits", + "Value": "1" + }, + { + "Key": "10 bits", + "Value": "2" + }, + { + "Key": "11 bits", + "Value": "3" + }, + { + "Key": "12 bits", + "Value": "4" + }, + { + "Key": "13 bits", + "Value": "5" + }, + { + "Key": "14 bits", + "Value": "6" + }, + { + "Key": "15 bits", + "Value": "7" + }, + { + "Key": "16 bits", + "Value": "8" + } + ] + }, + { + "WidgetType": "EntryBin", + "WidgetName": "Input compression BPC supported by the sink device: ", + "Visibility": "", + "Data": [ + "56", + "C14_Dsc_Bpc" + ], + "HelpText": "This field defines the compression input bpc supported by the sink device.\nThe field is defined in bitmap fashion and details of each bits are as defined below:\n\tBits 7-4\t Bit 3\t Bit 2\t Bit 1\t Bit 0\n\tRsvd\t 12 bpc\t 10bpc\t 8bpc\t Rsvd\nBit = 0, not supported. Bit = 1, supported\nNote: Assumption is that sink shall support all lower bpc values than the maximum selected field. i.e. If it supports say 12bpc, it will also support 10 and 8bpc as well", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Maximum supported compression BPP: ", + "Visibility": "", + "Data": [ + "56", + "C14_Dsc_Max_Bpp" + ], + "HelpText": "As of today, we are supporting 6/8/10/12 BPP for compression output.\nSelect the most appropriate BPP as supported by the sink.", + "WidgetValues": [ + { + "Key": "6 Bits per pixel", + "Value": "0" + }, + { + "Key": "8 Bits per pixel", + "Value": "1" + }, + { + "Key": "10 Bits per pixel", + "Value": "2" + }, + { + "Key": "12 Bits per pixel", + "Value": "3" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Slice height supported by the sink device: ", + "Visibility": "", + "Data": [ + "56", + "C14_Dsc_Slice_Height" + ], + "HelpText": "Slice height supported by the sink device for DSC slice.\nNote: Slice height must divide the picture height uniformly.", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + } + ] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-15", + "PageName": "Panel #15", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "LabelHeading", + "WidgetName": "Common LFP Features", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryAsci", + "WidgetName": " LFP Panel Name: ", + "Visibility": "", + "Data": [ + "42", + "Panel_Name_15" + ], + "HelpText": "This feature defines the LFP panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Target X-Res: ", + "Visibility": "", + "Data": [ + "42", + "Panel_Width_15" + ], + "HelpText": "This value specifies the Target X-Resolution for this panel.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Target Y-Res: ", + "Visibility": "", + "Data": [ + "42", + "Panel_Height_15" + ], + "HelpText": "This value specifies the Target Y-Resolution for this panel.", + "WidgetValues": [] + }, + { + "WidgetType": "LabelHeading", + "WidgetName": " DPS Panel Type Features", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Seamless DRRS Minimum Refresh Rate (Hz): ", + "Visibility": "", + "Data": [ + "42", + "Seamless_DRRS_Min_RR_15" + ], + "HelpText": "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\nNote: Graphics driver will use this field only when EDID support is disabled in VBT configuration.", + "WidgetValues": [] + }, + { + "WidgetType": "LabelHeading", + "WidgetName": " BackLight Technology Type Features", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " BackLight Technology: ", + "Visibility": "", + "Data": [ + "40", + "Blt_Control_15" + ], + "HelpText": "This feature allows OEM to select the Backlight Technology.", + "WidgetValues": [ + { + "Key": "LED Backlight", + "Value": "2" + }, + { + "Key": "CCFL Backlight", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Panel Rotation: ", + "Visibility": "", + "Data": [ + "40", + "Panel_Rotation_15" + ], + "HelpText": "This feature specifies the Panel Rotation of LFP panel used.", + "WidgetValues": [ + { + "Key": "0 degree", + "Value": "0" + }, + { + "Key": "180 degree", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Panel Position: ", + "Visibility": "", + "Data": [ + "40", + "Panel_Position_15" + ], + "HelpText": "This feature specifies the Panel Position of LFP panel used.", + "WidgetValues": [ + { + "Key": "Inside Shell", + "Value": "0" + }, + { + "Key": "Outside Shell", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Dual LFP Port Sync: ", + "Visibility": "", + "Data": [ + "42", + "EnablePortSync_Bit_15" + ], + "HelpText": "This feature will allow users to disable/enable Dual LFP Port Sync and it is applicable for DDI-A, DDI-B in case of eDP and DSI-0, DSI-1 in case of MIPI. \r\n.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " GPU Dithering for Banding artifacts: ", + "Visibility": "", + "Data": [ + "42", + "EnableDithering_Bit_15" + ], + "HelpText": "This field can be used to enable dithering from the source side for reducing banding artifacts on the visual quality features like DPST.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "Button", + "WidgetName": "Power Features", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Generic DTD Timings", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "LFP PnP ID Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Backlight Control Parameters", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Chromaticity Control", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "VESA DSC Parameters", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "LabelHeading", + "WidgetName": "Integrated eDP Settings", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "eDP Fast Link Training Configuration Parameters", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "eDP Panel Power Sequencing Parameters", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Edp Max Port Link Rate (in 200 Khz): ", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [ + "27", + "eDP_Max_Port_Link_Rate_15" + ], + "HelpText": "This field specifies EDP Max Port Link Rate supported by the port in unit of 200KHz.\nDefault value would be \"0\", in which case Display Drivers should consider EDP Max Port Link Rate to be the Platform supported Max Link Rate.\nOnly when OEM's need to limit to particular Link Rate can enter the value as mentioned in below table.\n\nNote:\n1) OEM's need to enter the values mentioned from below table only.\n2) If value entered is not matching with any of the below values then Platform supported Max Link Rate should be considere as EDP Max Port Link Rate by the display drivers.\n3) In case of EDP Fast Link Training Params(FLT), if user enters FLT Link Rate value greater than the \"eDP Max Port Link Rate\" then we need to use \n Fast Link training Link Rate = MIN (FLT Link Rate , eDP Max Port Link Rate)\n---------------------------------------------------------\n|\tLink Rate(Gbps)\t|\t Value to enter in text field\t|\n|\t \t\t|\t in terms of 200KHZ \t|\n---------------------------------------------------------\n|\t 1.62 \t\t|\t 8100 \t|\n|\t 2.16 \t\t|\t 10800 \t|\n|\t 2.43 \t\t|\t 12150 \t|\n|\t 2.7 \t\t|\t 13500 \t|\n|\t 3.24 \t\t|\t 16200 \t|\n|\t 3.78 \t\t|\t 18900 \t|\n|\t 4.32 \t\t|\t 21600 \t|\n|\t 5.4 \t\t|\t 27000 \t|\n|\t 6.48 \t\t|\t 32400 \t|\n|\t 6.75 \t\t|\t 33750 \t|\n|\t 8.1 \t\t|\t 40500 \t|\n", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Panel Color Depth: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Panel_Color_Depth_15" + ], + "HelpText": "This feature specifies the color depth of eDP panel used.", + "WidgetValues": [ + { + "Key": "18-bit Color Depth", + "Value": "0" + }, + { + "Key": "24-bit Color Depth", + "Value": "1" + }, + { + "Key": "30-bit Color Depth", + "Value": "2" + }, + { + "Key": "36-bit Color Depth", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Select VSwing/Pre-Emphasis table : ", + "Visibility": "", + "Data": [ + "27", + "eDP_VswingPreEmph_15" + ], + "HelpText": "This feature selects the VSwing Pre-Emphasis setting table to be used. For Tigerlake, based on the selection respective table will be used.\nTables for Tigerlake:\nLow Power VSwing Pre-Emphasis Setting Table:\nFor HBR2:\n\t\t\t\t\t\t Pre-Emphasis (db)\n\t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\nVoltage \t\t Level-0/200mV \t\t 200mV, 0.0db \t\t 200mV, 1.9db \t\t 200mV, 3.5db \t\t 200mV, 4.9db\nSwing \t\t Level-1/250mV \t\t 250mV, 0.0db \t\t 250mV, 1.6db \t\t 250mV, 2.9db \t\t N/A\n(mV) \t\t Level-2/300mV \t\t 300mV, 0.0db \t\t 300mV, 1.3db \t\t N/A \t\t N/A\n\t\t Level-3/350mV \t\t 350mV, 0.0db \t\t N/A \t\t N/A \t\t N/A\n\n\nFor HBR3:\n\t\t\t\t\t\t Pre-Emphasis (db)\n\t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\nVoltage \t\t Level-0/350mV \t\t 350mV, 0.0db \t\t 350mV, 3.1db \t\t 350mV, 6.0db \t\t 350mV, 8.2db\nSwing \t\t Level-1/500mV \t\t 500mV, 0.0db \t\t 500mV, 2.9db \t\t 500mV, 5.1db \t\t N/A\n(mV) \t\t Level-2/650mV \t\t 650mV, 0.6db \t\t 600mV, 3.5db \t\t N/A \t\t N/A\n\t\t Level-3/900mV \t\t 900mV, 0.0db \t\t N/A \t\t N/A \t\t N/A\n\n\nDefault VSwing Pre-Emphasis Setting Table:\nFor HBR:\n\t\t\t\t\t\t Pre-Emphasis (db)\n\t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\nVoltage \t\t Level-0/350mV \t\t 350mV, 0.0db \t\t 350mV, 3.1db \t\t 350mV, 6.0db \t\t 350mV, 8.2db\nSwing \t\t Level-1/500mV \t\t 500mV, 0.0db \t\t 500mV, 2.9db \t\t 500mV, 5.1db \t\t N/A\n(mV) \t\t Level-2/650mV \t\t 650mV, 0.6db \t\t 600mV, 3.5db \t\t N/A \t\t N/A\n\t\t Level-3/900mV \t\t 900mV, 0.0db \t\t N/A \t\t N/A \t\t N/A\n\n\nFor HBR2:\n\t\t\t\t\t\t Pre-Emphasis (db)\n\t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\nVoltage \t\t Level-0/350mV \t\t 350mV, 0.0db \t\t 350mV, 3.1db \t\t 350mV, 6.0db \t\t 350mV, 8.2db\nSwing \t\t Level-1/500mV \t\t 500mV, 0.0db \t\t 500mV, 2.9db \t\t 500mV, 5.1db \t\t N/A\n(mV) \t\t Level-2/650mV \t\t 650mV, 0.6db \t\t 600mV, 3.5db \t\t N/A \t\t N/A\n\t\t Level-3/900mV \t\t 900mV, 0.0db \t\t N/A \t\t N/A \t\t N/A", + "WidgetValues": [ + { + "Key": "Default VSwing/Pre-Emphasis Table", + "Value": "1" + }, + { + "Key": "Low Power VSwing/Pre-Emphasis Table", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " eDP Spread Spectrum Clock: ", + "Visibility": "", + "Data": [ + "40", + "Enable_SSC15" + ], + "HelpText": "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Pixel Overlap Count: ", + "Visibility": "", + "Data": [ + "42", + "PixelOverlapCount_15" + ], + "HelpText": "Select the number of Pixels to be overlapped per half of Scanline while using Edp Multi-SST(MSO) feature.", + "WidgetValues": [ + { + "Key": "Zero Pixel Overlap", + "Value": "0" + }, + { + "Key": "One Pixel Overlap", + "Value": "1" + }, + { + "Key": "Two Pixel Overlap", + "Value": "2" + }, + { + "Key": "Three Pixel Overlap", + "Value": "3" + }, + { + "Key": "Four Pixel Overlap", + "Value": "4" + }, + { + "Key": "Five Pixel Overlap", + "Value": "5" + }, + { + "Key": "Six Pixel Overlap", + "Value": "6" + }, + { + "Key": "Seven Pixel Overlap", + "Value": "7" + }, + { + "Key": "Eight Pixel Overlap", + "Value": "8" + } + ] + }, + { + "WidgetType": "Button", + "WidgetName": "PSR Feature", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Apical Feature", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + } + ], + "NestedPages": [ + { + "Type": "Block", + "Block": { + "PageNum": "5-2-15-1", + "PageName": "eDP Panel Power Sequencing Parameters", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " T3 optimization: ", + "Visibility": "", + "Data": [ + "27", + "eDP_T3_Optimization_15" + ], + "HelpText": "This feature enables or disables T3 optimization.\nWhen enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\nWhen disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "LCDVCC to HPD high delay (T3): ", + "Visibility": "", + "Data": [ + "27", + "eDP_Vcc_To_Hpd_Delay_15" + ], + "HelpText": "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\nValid Range: 0 to 200msec", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Valid video data to Backlight Enable delay (T8): ", + "Visibility": "", + "Data": [ + "27", + "eDP_DataOn_To_BkltEnable_Delay_15" + ], + "HelpText": "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\nT8 is inclusive of T7.\nValid Range of T7: 0 to 50msec", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "PWM-On To Backlight Enable delay: ", + "Visibility": "", + "Data": [ + "27", + "eDP_PwmOn_To_Bklt_Enable_Delay_15" + ], + "HelpText": "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\nDelay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\nSo it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Backlight Disable to PWM-Off delay: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Bklt_Disable_To_PwmOff_Delay_15" + ], + "HelpText": "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\nDelay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\nSo it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Backlight Disable to End of Valid video data delay (T9): ", + "Visibility": "", + "Data": [ + "27", + "eDP_BkltDisable_To_DataOff_Delay_15" + ], + "HelpText": "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "End of Valid video data to Power-Off delay (T10): ", + "Visibility": "", + "Data": [ + "27", + "eDP_DataOff_To_PowerOff_Delay_15" + ], + "HelpText": "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\nValid Range: 0 to 500 msec", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Power-off time (T12): ", + "Visibility": "", + "Data": [ + "27", + "eDP_PowerCycle_Delay_15" + ], + "HelpText": "Using this field Power-off time can be specified in 100uS.", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-15-2", + "PageName": "eDP Fast Link Training Configuration Parameters", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Is FastLinkTraining Feature Supported: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Fast_Link_Training_Supported_15" + ], + "HelpText": "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled.", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Data Rate: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Fast_Link_Training_Data_Rate_15" + ], + "HelpText": "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. It will be used if the sink indicates that no aux handshake is required during link training.\n\nIn case of EDP Fast Link Training Params(FLT), if user enters FLT Link Rate value greater than the \"eDP Max Port Link Rate\" then driver would use \n Fast Link training Link Rate = MIN (FLT Link Rate , eDP Max Port Link Rate).", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Lane Count: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Link_LaneCount_15" + ], + "HelpText": "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. It will be used if the sink indicates that no aux handshake is required during link training.", + "WidgetValues": [ + { + "Key": "x1", + "Value": "0" + }, + { + "Key": "x2", + "Value": "1" + }, + { + "Key": "x4", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Pre-Emphasis: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Link_PreEmp_15" + ], + "HelpText": "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. It will be used if the sink indicates that no aux handshake is required during link training.", + "WidgetValues": [ + { + "Key": "Level-0", + "Value": "0" + }, + { + "Key": "Level-1", + "Value": "1" + }, + { + "Key": "Level-2", + "Value": "2" + }, + { + "Key": "Level-3", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Voltage Swing: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Link_Vswing_15" + ], + "HelpText": "This feature allows for the selection of the Voltage Swing value for the embedded DP link. It will be used if the sink indicates that no aux handshake is required during link training.", + "WidgetValues": [ + { + "Key": "Swing-0", + "Value": "0" + }, + { + "Key": "Swing-1", + "Value": "1" + }, + { + "Key": "Swing-2", + "Value": "2" + }, + { + "Key": "Swing-3", + "Value": "3" + } + ] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-15-3", + "PageName": "PSR Feature", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Full Link enable: ", + "Visibility": "", + "Data": [ + "9", + "PSR_FullLink_Enable_15" + ], + "HelpText": "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state.", + "WidgetValues": [ + { + "Key": "No", + "Value": "0" + }, + { + "Key": "Yes", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Require AUX to wake up: ", + "Visibility": "", + "Data": [ + "9", + "PSR_Require_AUX2Wakeup_15" + ], + "HelpText": "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used.", + "WidgetValues": [ + { + "Key": "No", + "Value": "0" + }, + { + "Key": "Yes", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Lines to wait before link standby: ", + "Visibility": "", + "Data": [ + "9", + "PSR_Lines2Wait_B4LinkS3_15" + ], + "HelpText": "This field determines Lines to wait before link standby\n0 lines to wait (Default)\n1 lines to wait\n4 lines to wait\n8 lines to wait\nOthers Reserved", + "WidgetValues": [ + { + "Key": "0 lines to wait", + "Value": "0" + }, + { + "Key": "1 lines to wait", + "Value": "1" + }, + { + "Key": "4 lines to wait", + "Value": "2" + }, + { + "Key": "8 lines to wait", + "Value": "3" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Idle frames to wait: ", + "Visibility": "", + "Data": [ + "9", + "PSR_IdleFrames2Wait_15" + ], + "HelpText": "Idle frames to wait for PSR enable.\nAllowed values 0-15. Default value is 0.", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Clock Recovery Time: ", + "Visibility": "", + "Data": [ + "9", + "PSR_TP1_WaitTime_15" + ], + "HelpText": "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)", + "WidgetValues": [ + { + "Key": "500 usec", + "Value": "0" + }, + { + "Key": "100 usec", + "Value": "1" + }, + { + "Key": "2.5 msec", + "Value": "2" + }, + { + "Key": "0 (Skip)", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Channel Equalization Time for PSR1 panel: ", + "Visibility": "", + "Data": [ + "9", + "PSR1_TP_2_3_4_WaitTime_15" + ], + "HelpText": "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) or TP4(Training Pattern4) time during PSR1 exit(wake up)", + "WidgetValues": [ + { + "Key": "500 usec", + "Value": "0" + }, + { + "Key": "100 usec", + "Value": "1" + }, + { + "Key": "2.5 msec", + "Value": "2" + }, + { + "Key": "0 (Skip)", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Channel Equalization Time for PSR2 panel: ", + "Visibility": "", + "Data": [ + "9", + "PSR2_TP_2_3_4_WaitTime_15" + ], + "HelpText": "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) or TP4(Training Pattern4) time during PSR2 exit(wake up)", + "WidgetValues": [ + { + "Key": "500 usec", + "Value": "0" + }, + { + "Key": "100 usec", + "Value": "1" + }, + { + "Key": "2.5 msec", + "Value": "2" + }, + { + "Key": "50 usec", + "Value": "3" + } + ] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-15-4", + "PageName": "Apical Feature", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Apical Assertive Display IP: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Apical_Display_Ip_Enable_15" + ], + "HelpText": "This field enables/disables the Apical Assertive Display IP for this panel.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Panel OUI (IEEE OUI): ", + "Visibility": "", + "Data": [ + "27", + "eDP_Panel_Oui_15" + ], + "HelpText": "This field specifies the Apical IP specific Panel OUI field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " DPCD Base Address: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Dpcd_Base_Address_15" + ], + "HelpText": "This field specifies the Apical IP specific DPCD base address field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " DPCD Irdidix Control 0: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Dpcd_Irdidix_Control0_15" + ], + "HelpText": "This field specifies the Apical IP specific DPCD Irdidix control 0 field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " DPCD Option Select: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Dpcd_Option_Select_15" + ], + "HelpText": "This field specifies the Apical IP specific DPCD option select field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " DPCD Backlight: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Dpcd_Backlight_15" + ], + "HelpText": "This field specifies the Apical IP specific backlight value.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Ambient Light: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Ambient_Light_15" + ], + "HelpText": "This field specifies the Apical IP specific Ambient light value.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Backlight scale: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Backlight_Scale_15" + ], + "HelpText": "This field specifies the Apical IP specific backlight scale field.", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-15-5", + "PageName": "Power Features", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Intel Display Power Saving Technology (DPST) (Mobile only): ", + "Visibility": "", + "Data": [ + "44", + "DPST_Enable_15" + ], + "HelpText": "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled.\nIntel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power.\nNote: This technology is only active when the system is running in battery mode and the LFP is the only active display device.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Intel Display Refresh Rate Switching (DRRS) (Mobile only): ", + "Visibility": "", + "Data": [ + "44", + "DRRS_Enable_15" + ], + "HelpText": "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Edge Luminance Profile (ELP) : ", + "Visibility": "", + "Data": [ + "44", + "ELP_Enable_15" + ], + "HelpText": "This feature determines whether the ELP feature is enabled or disabled.\nEdge Luminance Profile (ELP) is a panel technology which reduce luminance on the edge of screen to save panel power.\nNote:This technology cannot co-exist with DPST and OPST ((i.e.) OPST, DPST and ELP cannot exist together.They are all mutually exclusive to each other.)", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " OLED Power Saving Technology (OPST) : ", + "Visibility": "", + "Data": [ + "44", + "OPST_Enable_15" + ], + "HelpText": "This feature determines whether the OPST feature is enabled or disabled.\nOLED Power Saving Technology (OPST) is a panel technology which saves power by intelligent, adaptive dimming of midrange pixel values more aggressively than the extremes without compromising the viewability.\nNote: This technology cannot co-exist with ELP and DPST ((i.e.) OPST, DPST and ELP cannot exist together.They are all mutually exclusive to each other.)", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Dynamic Media Refresh Rate Switching Enable/Disable ", + "Visibility": "", + "Data": [ + "44", + "DMRRS_Enable_15" + ], + "HelpText": "This feature determines whether Dynamic media refresh rate switching is to be enabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Enable Display Lace Support: ", + "Visibility": "", + "Data": [ + "44", + "LACE_Enable_15" + ], + "HelpText": "This feature, when enabled, will set Display Lace Support otherwise, the functionality will be disabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Panel Self Refresh (PSR): ", + "Visibility": "", + "Data": [ + "44", + "PSR_Enable_15" + ], + "HelpText": "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Assertive Display Technology Enable/Disable: ", + "Visibility": "", + "Data": [ + "44", + "ADT_Enable_15" + ], + "HelpText": "This feature determines whether Assertive display technology is to be enabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Intel Automatic Display Brightness (ADB) (Mobile only): ", + "Visibility": "", + "Data": [ + "44", + "ADB_Enable_15" + ], + "HelpText": "This feature determines whether Intel Automatic Display Brightness is to be enabled. Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) depending on the current ambient light environment.\nWhen enabled, the driver and VBIOS will control the backlight brightness of the LFP depending on the ambient environment if and only if the LFP is the only active display. When disabled, the driver will perform no action.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "EDP 4k/2k HOBL Feature: ", + "Visibility": "", + "Data": [ + "44", + "eDP_4k_2k_HOBL_feature_Enable_15" + ], + "HelpText": "This feature will allow users to disable/enable the edp 4k/2k HOBL(Hours Of Battery Life) feature by programming relevant registers specific for a platform.\r\n.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Default Display LACE Enabled status: ", + "Visibility": "", + "Data": [ + "44", + "LACE_Status_15" + ], + "HelpText": "This feature, when enabled, will set Default Display LACE Enabled status otherwise, the functionality will be disabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "DPST Aggressiveness Level: ", + "Visibility": "", + "Data": [ + "44", + "DPST_Aggressiveness_Profile_15" + ], + "HelpText": "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n1 (Maximum Quality with No DPST)\n2\n3\n4\n5\n6 (Maximum Battery)", + "WidgetValues": [ + { + "Key": "1 - Maximum Quality with No DPST", + "Value": "1" + }, + { + "Key": "2", + "Value": "2" + }, + { + "Key": "3", + "Value": "3" + }, + { + "Key": "4", + "Value": "4" + }, + { + "Key": "5", + "Value": "5" + }, + { + "Key": "6 - Maximum Battery", + "Value": "6" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "LACE Aggressiveness Level: ", + "Visibility": "", + "Data": [ + "44", + "LACE_Aggressiveness_Profile_15" + ], + "HelpText": "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\nMinimum 0\nModerate 1\nHigh 2", + "WidgetValues": [ + { + "Key": "Minimum", + "Value": "0" + }, + { + "Key": "Moderate", + "Value": "1" + }, + { + "Key": "High", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "ELP Aggressiveness Level: ", + "Visibility": "", + "Data": [ + "44", + "ELP_Aggressiveness_Profile_15" + ], + "HelpText": "This feature allows for the selection of ELP Aggressiveness level for this Panel Type.\nMinimum Power Savings\nMedium Power Savings \nMaximum Power Savings", + "WidgetValues": [ + { + "Key": "Minimum Power Savings", + "Value": "0" + }, + { + "Key": "Medium Power Savings", + "Value": "1" + }, + { + "Key": "Maximum Power Savings", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "OPST Aggressiveness Level: ", + "Visibility": "", + "Data": [ + "44", + "OPST_Aggressiveness_Profile_15" + ], + "HelpText": "This feature allows for the selection of OPST Aggressiveness level for this Panel Type.\nMinimum Power Savings\nMedium Power Savings \nMaximum Power Savings", + "WidgetValues": [ + { + "Key": "Minimum Power Savings", + "Value": "0" + }, + { + "Key": "Medium Power Savings", + "Value": "1" + }, + { + "Key": "Maximum Power Savings", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Default Display VRR Enabled status: ", + "Visibility": "", + "Data": [ + "44", + "VRR_Status_15" + ], + "HelpText": "VRR (Variable Refresh Rate) is a feature that can continuously and seamlessly vary Refresh Rate on the fly, on displays that support Variable Refresh rate Technologies.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-15-6", + "PageName": "Generic DTD Timings", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Pixel Clock in KHz: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_Pixel_CLK_15" + ], + "HelpText": "Pixel Clock (in KHz) Range from 0.001 to 4294967.295 MP/s.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Active: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_Active_15" + ], + "HelpText": "Horizontal Active Image Pixels Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Active: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_Active_15" + ], + "HelpText": "Vertical Active Image Lines Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Blank: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_Blank_15" + ], + "HelpText": "Horizontal Blank Pixels Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Blank: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_Blank_15" + ], + "HelpText": "Vertical Blank lines Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Front Porch: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_FrontPorch_15" + ], + "HelpText": "Horizontal Front Porch Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Front Porch: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_FrontPorch_15" + ], + "HelpText": "Vertical Front Porch Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Sync: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_Sync_15" + ], + "HelpText": "Horizontal Sync Width Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Sync: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_Sync_15" + ], + "HelpText": "Vertical Sync Width Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Image Size: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_Image_Size_15" + ], + "HelpText": "Horizontal Addressable Video Image Size in mm represented by 16bits. Image size multiplier 1.00 mm precision.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Image Size: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_Image_Size_15" + ], + "HelpText": "Vertical Addressable Video Image Size in mm represented by 16bits. Image size multiplier 1.00 mm precision.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryBin", + "WidgetName": "Common Flag: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_Common_Flag_15" + ], + "HelpText": "Common DTD Flags:\nBit 7 : Horizontal Sync Polarity\n1 : Positive\n0 : Negative\nBit 6 : Vertical Sync polarity\n1 : Positive\n0 : Negative\nBit 5 - 0: Reserved (Default value 0)", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-15-7", + "PageName": "LFP PnP ID Table", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Table", + "WidgetName": "", + "Visibility": "", + "Data": [ + "42", + "LFP_Panel_PnP_ID_15" + ], + "HelpText": "This feature allows the 10 bytes of EDID Vendor/Product ID starting at offset 08h to be used as a PnP ID.\n\nTable Definition:\n\tWord: ID Manufacturer Name\n\tWord: ID Product Code\n\tDWord: ID Serial Number\n\tByte: Week of Manufacture\n\tByte: Year of Manufacture", + "WidgetValues": [ + { + "ColumnName": "PnP ID", + "SizeinBytes": "1" + } + ] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-15-8", + "PageName": "Backlight Control Parameters", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Inverter Type: ", + "Visibility": "", + "Data": [ + "43", + "BLC_Inv_Type_15" + ], + "HelpText": "This feature allows for the selection of the Backlight Inverter type that is to be used to control the backlight brightness of the LFP.\nWhen PWM is selected, the driver and VBIOS will control the backlight brightness via the integrated PWM solution for the applicable chipsets.\nWhen None/External is selected, the system BIOS will control the backlight brightness via the external solution.", + "WidgetValues": [ + { + "Key": "None/External", + "Value": "0" + }, + { + "Key": "PWM", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Pwm Source Selection: ", + "Visibility": "", + "Data": [ + "43", + "Lfp_Pwm_Source_Selection_15" + ], + "HelpText": "If panel supports 'Intel HDR AUX Interface', it will always be chosen by default. If not, value in 'PWM Source Selection' will be used", + "WidgetValues": [ + { + "Key": "PWM From Display Engine", + "Value": "2" + }, + { + "Key": "PWM From LCD Panel", + "Value": "3" + }, + { + "Key": "Panel Driver Interface", + "Value": "4" + }, + { + "Key": "VESA eDP AUX Interface", + "Value": "5" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Pwm Controller Selection: ", + "Visibility": "", + "Data": [ + "43", + "Lfp_Pwm_Controller_Selection_15" + ], + "HelpText": "This field allows to select the PWM Controller to be used for the selected Local Flat Panel.This field allows to select the PWM Controller to be used for the selected Local Flat Panel.If Two LFPs are connected then PWM0 and PWM1 must be selected accordingly.", + "WidgetValues": [ + { + "Key": "PWM0", + "Value": "0" + }, + { + "Key": "PWM1", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Inverter Polarity: ", + "Visibility": "", + "Data": [ + "43", + "BLC_Inv_Polarity_15" + ], + "HelpText": "This feature allows the backlight inverter polarity to be specified.\nNormal means 0 value is minimum brightness.\nInverted means 0 value is maximum brightness.", + "WidgetValues": [ + { + "Key": "Normal", + "Value": "0" + }, + { + "Key": "Inverted", + "Value": "1" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Minimum Brightness: ", + "Visibility": "", + "Data": [ + "43", + "Post_Min_Brightness_15" + ], + "HelpText": "This feature allows defining the absolute minimum backlight brightness. The driver will never decrease the backlight less than this value. The value must be specified using normal polarity semantics. The value should range from 0 to 255 if the brightness precision bit is chosen to be 8, and it should range from 0 to 65535 if the precision bit is chosen to be 16.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "POST Backlight Intensity: ", + "Visibility": "", + "Data": [ + "43", + "Post_Brightness_15" + ], + "HelpText": "This feature is used to set default backlight brightness value of the panel at POST. The value should range from 0 to 255 if the bit precision is chosen to be 8 and it should range from 0 to 65535 if the brightness bit precision is chosent to be 16.", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Brightness Precision Bits: ", + "Visibility": "", + "Data": [ + "43", + "BrightnessPrecisionBits_15" + ], + "HelpText": "This field represents the range of brightness in terms of bit precision.\n 8 = Brightness range of 0 to 255.\n 16 = Brightness range of 0 to 65535", + "WidgetValues": [ + { + "Key": "8", + "Value": "8" + }, + { + "Key": "16", + "Value": "16" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "PWM Inverter Frequency (Hz): ", + "Visibility": "", + "Data": [ + "43", + "PWM_Frequency_15" + ], + "HelpText": "This feature allows for the definition of the frequency needed for PWM Inverter.\nNote: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Intel HDR DPCD Refresh Timeout (unit - 10 micro seconds): ", + "Visibility": "", + "Data": [ + "43", + "HdrDpcdRefreshTimeout_15" + ], + "HelpText": "This field allows to configure the refresh timeout of Intel HDR DPCDs for different TCON Vendors.\nNote:\n\tThe value is in units of 10 microseconds.\n\tThe range (entered as a decimal number), for the timeout is 0-65535", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-15-9", + "PageName": "Chromaticity Control", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Chromaticity Control Feature: ", + "Visibility": "", + "Data": [ + "46", + "Chromacity_Enable_15" + ], + "HelpText": "This bit enables Chromaticity feature.\nIf this bit is enabled, EDID values for chromaticity will be used, else feature is disabled.\nFeature will be supported for Panels that support EDID version 1.4 or higher.\nPlease refer to section 3.7 of EDID Specification 1.4.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Override the EDID values: ", + "Visibility": "", + "Data": [ + "46", + "Override_EDID_Data_15" + ], + "HelpText": "This option when enabled along with Chromaticity feature will override EDID values through following VBT data", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Red_Green_bits (Bits 1:0 at 19h): ", + "Visibility": "", + "Data": [ + "46", + "Red_Green_15" + ], + "HelpText": "Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Blue_White_bits (Bits 1:0 at 1Ah): ", + "Visibility": "", + "Data": [ + "46", + "Blue_White_15" + ], + "HelpText": "Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Red_x (Bits 9:2 at 1Bh): ", + "Visibility": "", + "Data": [ + "46", + "Red_x_15" + ], + "HelpText": "Bits 9:2 of red color x coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Red_y (Bits 9:2 at 1Ch): ", + "Visibility": "", + "Data": [ + "46", + "Red_y_15" + ], + "HelpText": "Bits 9:2 of red color y coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Green_x (Bits 9:2 at 1Dh): ", + "Visibility": "", + "Data": [ + "46", + "Green_x_15" + ], + "HelpText": "Bits 9:2 of Green color x coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Green_y (Bits 9:2 at 1Eh): ", + "Visibility": "", + "Data": [ + "46", + "Green_y_15" + ], + "HelpText": "Bits 9:2 of Green color y coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Blue_x (Bits 9:2 at 1Fh): ", + "Visibility": "", + "Data": [ + "46", + "Blue_x_15" + ], + "HelpText": "Bits 9:2 of Blue color x coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Blue_y (Bits 9:2 at 20h): ", + "Visibility": "", + "Data": [ + "46", + "Blue_y_15" + ], + "HelpText": "Bits 9:2 of Blue color y coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " White_x (Bits 9:2 at 21h): ", + "Visibility": "", + "Data": [ + "46", + "White_x_15" + ], + "HelpText": "Bits 9:2 of White color x coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " White_y (Bits 9:2 at 22h): ", + "Visibility": "", + "Data": [ + "46", + "White_y_15" + ], + "HelpText": "Bits 9:2 of White color y coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Override Luminance values ", + "Visibility": "", + "Data": [ + "46", + "Override_LUM_Data_15" + ], + "HelpText": "This option when enabled along with Chromaticity feature will override luminance values following VBT values", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Minimum Luminance: ", + "Visibility": "", + "Data": [ + "46", + "MinLuminance_15" + ], + "HelpText": "Minimum luminance value.\n2 byte value, encoded in IEEE 754 half-precision binary floating point format,", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Maximum full frame luminance: ", + "Visibility": "", + "Data": [ + "46", + "MaxFullLuminance_15" + ], + "HelpText": "Maximum Full frame luminance value.\n2 byte value, encoded in IEEE 754 half-precision binary floating point format,", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Maximum Luminance: ", + "Visibility": "", + "Data": [ + "46", + "MaxLuminance_15" + ], + "HelpText": "Maximum luminance value(Relatively smaller portion of screen).\n2 byte value, encoded in IEEE 754 half-precision binary floating point format.", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Override Gamma values: ", + "Visibility": "", + "Data": [ + "46", + "Override_Gamma_Data_15" + ], + "HelpText": "This option when enabled along with Chromaticity feature will override gamma values through following VBT data", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Panel gamma: ", + "Visibility": "", + "Data": [ + "46", + "Gamma_15" + ], + "HelpText": "Value shall define the gamma range, from 1.00 to 3.54, as follows:\nField Value = (Gamma (value in float) x 100) - 100\nField values range from 00h through FFh.\nFFh = No gamma information shall be provided", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-15-10", + "PageName": "VESA DSC Parameters", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "DSC Major Version: ", + "Visibility": "", + "Data": [ + "56", + "C15_Major_Dsc_Version" + ], + "HelpText": "VESA DSC Major revision field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "DSC Minor Version: ", + "Visibility": "", + "Data": [ + "56", + "C15_Minor_Dsc_Version" + ], + "HelpText": "VESA DSC Minor revision field.", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Block prediction supported: ", + "Visibility": "", + "Data": [ + "56", + "C15_Blk_Prediction_En" + ], + "HelpText": "Sink supports block prediction as per the VESA DSC Spec.", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "RC Buffer Block size as per VESA DSC Spec: ", + "Visibility": "", + "Data": [ + "56", + "C15_RC_Block_Size" + ], + "HelpText": "RC buffer block size for a single RC buffer as defined by the VESA DSC spec.", + "WidgetValues": [ + { + "Key": "1 KB", + "Value": "0" + }, + { + "Key": "4 KB", + "Value": "1" + }, + { + "Key": "16 KB", + "Value": "2" + }, + { + "Key": "64 KB", + "Value": "3" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Number of RC buffer blocks as per VESA DSC Spec: ", + "Visibility": "", + "Data": [ + "56", + "C15_Dsc_RC_Buf_Size" + ], + "HelpText": "This field defines the number of RC buffers as per VESA DSC spec.\nThe number of RC buffers used by the software shall be (Value + 1) where Value is in range 0 to 127.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryBin", + "WidgetName": "Slices per line supported by the sink device: ", + "Visibility": "", + "Data": [ + "56", + "C15_Dsc_Slices_Per_Line" + ], + "HelpText": "This field defines the slices per line supported by the sink device.\nThe field is defined in bitmap fashion and details of each bits are as defined below:\n\tBits 31-10\t\t Bit 9\tBit 8\tBit 7\tBit 6\tBit 5\tBit 4\t Bit 3\t Bit 2\t Bit 1\t Bit 0\n\tReserved\t\t 24\t 20\t 16\t 12\t 10\t 8\t 6\t 4\t 2\t 1\nBit = 0, not supported. Bit = 1, supported\nNote: Assumption is that sink shall support all lower slices per line than maximum selected field. i.e. If it supports say 8 slices per line, it will also support 4/2/1 slices per line", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Line buffer depth as per VESA DSC Spec: ", + "Visibility": "", + "Data": [ + "56", + "C15_Line_Buffer_Depth" + ], + "HelpText": "Line buffer depth in bits as per VESA DSC spec.", + "WidgetValues": [ + { + "Key": "8 bits", + "Value": "0" + }, + { + "Key": "9 bits", + "Value": "1" + }, + { + "Key": "10 bits", + "Value": "2" + }, + { + "Key": "11 bits", + "Value": "3" + }, + { + "Key": "12 bits", + "Value": "4" + }, + { + "Key": "13 bits", + "Value": "5" + }, + { + "Key": "14 bits", + "Value": "6" + }, + { + "Key": "15 bits", + "Value": "7" + }, + { + "Key": "16 bits", + "Value": "8" + } + ] + }, + { + "WidgetType": "EntryBin", + "WidgetName": "Input compression BPC supported by the sink device: ", + "Visibility": "", + "Data": [ + "56", + "C15_Dsc_Bpc" + ], + "HelpText": "This field defines the compression input bpc supported by the sink device.\nThe field is defined in bitmap fashion and details of each bits are as defined below:\n\tBits 7-4\t Bit 3\t Bit 2\t Bit 1\t Bit 0\n\tRsvd\t 12 bpc\t 10bpc\t 8bpc\t Rsvd\nBit = 0, not supported. Bit = 1, supported\nNote: Assumption is that sink shall support all lower bpc values than the maximum selected field. i.e. If it supports say 12bpc, it will also support 10 and 8bpc as well", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Maximum supported compression BPP: ", + "Visibility": "", + "Data": [ + "56", + "C15_Dsc_Max_Bpp" + ], + "HelpText": "As of today, we are supporting 6/8/10/12 BPP for compression output.\nSelect the most appropriate BPP as supported by the sink.", + "WidgetValues": [ + { + "Key": "6 Bits per pixel", + "Value": "0" + }, + { + "Key": "8 Bits per pixel", + "Value": "1" + }, + { + "Key": "10 Bits per pixel", + "Value": "2" + }, + { + "Key": "12 Bits per pixel", + "Value": "3" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Slice height supported by the sink device: ", + "Visibility": "", + "Data": [ + "56", + "C15_Dsc_Slice_Height" + ], + "HelpText": "Slice height supported by the sink device for DSC slice.\nNote: Slice height must divide the picture height uniformly.", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + } + ] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-16", + "PageName": "Panel #16", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "LabelHeading", + "WidgetName": "Common LFP Features", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryAsci", + "WidgetName": " LFP Panel Name: ", + "Visibility": "", + "Data": [ + "42", + "Panel_Name_16" + ], + "HelpText": "This feature defines the LFP panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Target X-Res: ", + "Visibility": "", + "Data": [ + "42", + "Panel_Width_16" + ], + "HelpText": "This value specifies the Target X-Resolution for this panel.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Target Y-Res: ", + "Visibility": "", + "Data": [ + "42", + "Panel_Height_16" + ], + "HelpText": "This value specifies the Target Y-Resolution for this panel.", + "WidgetValues": [] + }, + { + "WidgetType": "LabelHeading", + "WidgetName": " DPS Panel Type Features", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Seamless DRRS Minimum Refresh Rate (Hz): ", + "Visibility": "", + "Data": [ + "42", + "Seamless_DRRS_Min_RR_16" + ], + "HelpText": "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\nNote: Graphics driver will use this field only when EDID support is disabled in VBT configuration.", + "WidgetValues": [] + }, + { + "WidgetType": "LabelHeading", + "WidgetName": " BackLight Technology Type Features", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " BackLight Technology: ", + "Visibility": "", + "Data": [ + "40", + "Blt_Control_16" + ], + "HelpText": "This feature allows OEM to select the Backlight Technology.", + "WidgetValues": [ + { + "Key": "LED Backlight", + "Value": "2" + }, + { + "Key": "CCFL Backlight", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Panel Rotation: ", + "Visibility": "", + "Data": [ + "40", + "Panel_Rotation_16" + ], + "HelpText": "This feature specifies the Panel Rotation of LFP panel used.", + "WidgetValues": [ + { + "Key": "0 degree", + "Value": "0" + }, + { + "Key": "180 degree", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Panel Position: ", + "Visibility": "", + "Data": [ + "40", + "Panel_Position_16" + ], + "HelpText": "This feature specifies the Panel Position of LFP panel used.", + "WidgetValues": [ + { + "Key": "Inside Shell", + "Value": "0" + }, + { + "Key": "Outside Shell", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Dual LFP Port Sync: ", + "Visibility": "", + "Data": [ + "42", + "EnablePortSync_Bit_16" + ], + "HelpText": "This feature will allow users to disable/enable Dual LFP Port Sync and it is applicable for DDI-A, DDI-B in case of eDP and DSI-0, DSI-1 in case of MIPI. \r\n.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " GPU Dithering for Banding artifacts: ", + "Visibility": "", + "Data": [ + "42", + "EnableDithering_Bit_16" + ], + "HelpText": "This field can be used to enable dithering from the source side for reducing banding artifacts on the visual quality features like DPST.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "Button", + "WidgetName": "Power Features", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Generic DTD Timings", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "LFP PnP ID Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Backlight Control Parameters", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Chromaticity Control", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "VESA DSC Parameters", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "LabelHeading", + "WidgetName": "Integrated eDP Settings", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "eDP Fast Link Training Configuration Parameters", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "eDP Panel Power Sequencing Parameters", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Edp Max Port Link Rate (in 200 Khz): ", + "Visibility": "Block:2, Field:LFP_Device_Class, Value:6150 or Block:2, Field:LFP2_Device_Class, Value:6150", + "Data": [ + "27", + "eDP_Max_Port_Link_Rate_16" + ], + "HelpText": "This field specifies EDP Max Port Link Rate supported by the port in unit of 200KHz.\nDefault value would be \"0\", in which case Display Drivers should consider EDP Max Port Link Rate to be the Platform supported Max Link Rate.\nOnly when OEM's need to limit to particular Link Rate can enter the value as mentioned in below table.\n\nNote:\n1) OEM's need to enter the values mentioned from below table only.\n2) If value entered is not matching with any of the below values then Platform supported Max Link Rate should be considere as EDP Max Port Link Rate by the display drivers.\n3) In case of EDP Fast Link Training Params(FLT), if user enters FLT Link Rate value greater than the \"eDP Max Port Link Rate\" then we need to use \n Fast Link training Link Rate = MIN (FLT Link Rate , eDP Max Port Link Rate)\n---------------------------------------------------------\n|\tLink Rate(Gbps)\t|\t Value to enter in text field\t|\n|\t \t\t|\t in terms of 200KHZ \t|\n---------------------------------------------------------\n|\t 1.62 \t\t|\t 8100 \t|\n|\t 2.16 \t\t|\t 10800 \t|\n|\t 2.43 \t\t|\t 12150 \t|\n|\t 2.7 \t\t|\t 13500 \t|\n|\t 3.24 \t\t|\t 16200 \t|\n|\t 3.78 \t\t|\t 18900 \t|\n|\t 4.32 \t\t|\t 21600 \t|\n|\t 5.4 \t\t|\t 27000 \t|\n|\t 6.48 \t\t|\t 32400 \t|\n|\t 6.75 \t\t|\t 33750 \t|\n|\t 8.1 \t\t|\t 40500 \t|\n", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Panel Color Depth: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Panel_Color_Depth_16" + ], + "HelpText": "This feature specifies the color depth of eDP panel used.", + "WidgetValues": [ + { + "Key": "18-bit Color Depth", + "Value": "0" + }, + { + "Key": "24-bit Color Depth", + "Value": "1" + }, + { + "Key": "30-bit Color Depth", + "Value": "2" + }, + { + "Key": "36-bit Color Depth", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Select VSwing/Pre-Emphasis table : ", + "Visibility": "", + "Data": [ + "27", + "eDP_VswingPreEmph_16" + ], + "HelpText": "This feature selects the VSwing Pre-Emphasis setting table to be used. For Tigerlake, based on the selection respective table will be used.\nTables for Tigerlake:\nLow Power VSwing Pre-Emphasis Setting Table:\nFor HBR2:\n\t\t\t\t\t\t Pre-Emphasis (db)\n\t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\nVoltage \t\t Level-0/200mV \t\t 200mV, 0.0db \t\t 200mV, 1.9db \t\t 200mV, 3.5db \t\t 200mV, 4.9db\nSwing \t\t Level-1/250mV \t\t 250mV, 0.0db \t\t 250mV, 1.6db \t\t 250mV, 2.9db \t\t N/A\n(mV) \t\t Level-2/300mV \t\t 300mV, 0.0db \t\t 300mV, 1.3db \t\t N/A \t\t N/A\n\t\t Level-3/350mV \t\t 350mV, 0.0db \t\t N/A \t\t N/A \t\t N/A\n\n\nFor HBR3:\n\t\t\t\t\t\t Pre-Emphasis (db)\n\t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\nVoltage \t\t Level-0/350mV \t\t 350mV, 0.0db \t\t 350mV, 3.1db \t\t 350mV, 6.0db \t\t 350mV, 8.2db\nSwing \t\t Level-1/500mV \t\t 500mV, 0.0db \t\t 500mV, 2.9db \t\t 500mV, 5.1db \t\t N/A\n(mV) \t\t Level-2/650mV \t\t 650mV, 0.6db \t\t 600mV, 3.5db \t\t N/A \t\t N/A\n\t\t Level-3/900mV \t\t 900mV, 0.0db \t\t N/A \t\t N/A \t\t N/A\n\n\nDefault VSwing Pre-Emphasis Setting Table:\nFor HBR:\n\t\t\t\t\t\t Pre-Emphasis (db)\n\t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\nVoltage \t\t Level-0/350mV \t\t 350mV, 0.0db \t\t 350mV, 3.1db \t\t 350mV, 6.0db \t\t 350mV, 8.2db\nSwing \t\t Level-1/500mV \t\t 500mV, 0.0db \t\t 500mV, 2.9db \t\t 500mV, 5.1db \t\t N/A\n(mV) \t\t Level-2/650mV \t\t 650mV, 0.6db \t\t 600mV, 3.5db \t\t N/A \t\t N/A\n\t\t Level-3/900mV \t\t 900mV, 0.0db \t\t N/A \t\t N/A \t\t N/A\n\n\nFor HBR2:\n\t\t\t\t\t\t Pre-Emphasis (db)\n\t\t DP Applet \t\t Level-0/0dB \t\t Level-1/1.5dB \t\t Level-2/4dB \t\t Level-3/6dB\nVoltage \t\t Level-0/350mV \t\t 350mV, 0.0db \t\t 350mV, 3.1db \t\t 350mV, 6.0db \t\t 350mV, 8.2db\nSwing \t\t Level-1/500mV \t\t 500mV, 0.0db \t\t 500mV, 2.9db \t\t 500mV, 5.1db \t\t N/A\n(mV) \t\t Level-2/650mV \t\t 650mV, 0.6db \t\t 600mV, 3.5db \t\t N/A \t\t N/A\n\t\t Level-3/900mV \t\t 900mV, 0.0db \t\t N/A \t\t N/A \t\t N/A", + "WidgetValues": [ + { + "Key": "Default VSwing/Pre-Emphasis Table", + "Value": "1" + }, + { + "Key": "Low Power VSwing/Pre-Emphasis Table", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " eDP Spread Spectrum Clock: ", + "Visibility": "", + "Data": [ + "40", + "Enable_SSC16" + ], + "HelpText": "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Pixel Overlap Count: ", + "Visibility": "", + "Data": [ + "42", + "PixelOverlapCount_16" + ], + "HelpText": "Select the number of Pixels to be overlapped per half of Scanline while using Edp Multi-SST(MSO) feature.", + "WidgetValues": [ + { + "Key": "Zero Pixel Overlap", + "Value": "0" + }, + { + "Key": "One Pixel Overlap", + "Value": "1" + }, + { + "Key": "Two Pixel Overlap", + "Value": "2" + }, + { + "Key": "Three Pixel Overlap", + "Value": "3" + }, + { + "Key": "Four Pixel Overlap", + "Value": "4" + }, + { + "Key": "Five Pixel Overlap", + "Value": "5" + }, + { + "Key": "Six Pixel Overlap", + "Value": "6" + }, + { + "Key": "Seven Pixel Overlap", + "Value": "7" + }, + { + "Key": "Eight Pixel Overlap", + "Value": "8" + } + ] + }, + { + "WidgetType": "Button", + "WidgetName": "PSR Feature", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Apical Feature", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + } + ], + "NestedPages": [ + { + "Type": "Block", + "Block": { + "PageNum": "5-2-16-1", + "PageName": "eDP Panel Power Sequencing Parameters", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " T3 optimization: ", + "Visibility": "", + "Data": [ + "27", + "eDP_T3_Optimization_16" + ], + "HelpText": "This feature enables or disables T3 optimization.\nWhen enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\nWhen disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "LCDVCC to HPD high delay (T3): ", + "Visibility": "", + "Data": [ + "27", + "eDP_Vcc_To_Hpd_Delay_16" + ], + "HelpText": "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\nValid Range: 0 to 200msec", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Valid video data to Backlight Enable delay (T8): ", + "Visibility": "", + "Data": [ + "27", + "eDP_DataOn_To_BkltEnable_Delay_16" + ], + "HelpText": "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\nT8 is inclusive of T7.\nValid Range of T7: 0 to 50msec", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "PWM-On To Backlight Enable delay: ", + "Visibility": "", + "Data": [ + "27", + "eDP_PwmOn_To_Bklt_Enable_Delay_16" + ], + "HelpText": "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\nDelay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\nSo it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Backlight Disable to PWM-Off delay: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Bklt_Disable_To_PwmOff_Delay_16" + ], + "HelpText": "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\nDelay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\nSo it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Backlight Disable to End of Valid video data delay (T9): ", + "Visibility": "", + "Data": [ + "27", + "eDP_BkltDisable_To_DataOff_Delay_16" + ], + "HelpText": "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "End of Valid video data to Power-Off delay (T10): ", + "Visibility": "", + "Data": [ + "27", + "eDP_DataOff_To_PowerOff_Delay_16" + ], + "HelpText": "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\nValid Range: 0 to 500 msec", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Power-off time (T12): ", + "Visibility": "", + "Data": [ + "27", + "eDP_PowerCycle_Delay_16" + ], + "HelpText": "Using this field Power-off time can be specified in 100uS.", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-16-2", + "PageName": "eDP Fast Link Training Configuration Parameters", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Is FastLinkTraining Feature Supported: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Fast_Link_Training_Supported_16" + ], + "HelpText": "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled.", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Data Rate: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Fast_Link_Training_Data_Rate_16" + ], + "HelpText": "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. It will be used if the sink indicates that no aux handshake is required during link training.\n\nIn case of EDP Fast Link Training Params(FLT), if user enters FLT Link Rate value greater than the \"eDP Max Port Link Rate\" then driver would use \n Fast Link training Link Rate = MIN (FLT Link Rate , eDP Max Port Link Rate).", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Lane Count: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Link_LaneCount_16" + ], + "HelpText": "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. It will be used if the sink indicates that no aux handshake is required during link training.", + "WidgetValues": [ + { + "Key": "x1", + "Value": "0" + }, + { + "Key": "x2", + "Value": "1" + }, + { + "Key": "x4", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Pre-Emphasis: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Link_PreEmp_16" + ], + "HelpText": "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. It will be used if the sink indicates that no aux handshake is required during link training.", + "WidgetValues": [ + { + "Key": "Level-0", + "Value": "0" + }, + { + "Key": "Level-1", + "Value": "1" + }, + { + "Key": "Level-2", + "Value": "2" + }, + { + "Key": "Level-3", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Voltage Swing: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Link_Vswing_16" + ], + "HelpText": "This feature allows for the selection of the Voltage Swing value for the embedded DP link. It will be used if the sink indicates that no aux handshake is required during link training.", + "WidgetValues": [ + { + "Key": "Swing-0", + "Value": "0" + }, + { + "Key": "Swing-1", + "Value": "1" + }, + { + "Key": "Swing-2", + "Value": "2" + }, + { + "Key": "Swing-3", + "Value": "3" + } + ] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-16-3", + "PageName": "PSR Feature", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Full Link enable: ", + "Visibility": "", + "Data": [ + "9", + "PSR_FullLink_Enable_16" + ], + "HelpText": "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state.", + "WidgetValues": [ + { + "Key": "No", + "Value": "0" + }, + { + "Key": "Yes", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Require AUX to wake up: ", + "Visibility": "", + "Data": [ + "9", + "PSR_Require_AUX2Wakeup_16" + ], + "HelpText": "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used.", + "WidgetValues": [ + { + "Key": "No", + "Value": "0" + }, + { + "Key": "Yes", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Lines to wait before link standby: ", + "Visibility": "", + "Data": [ + "9", + "PSR_Lines2Wait_B4LinkS3_16" + ], + "HelpText": "This field determines Lines to wait before link standby\n0 lines to wait (Default)\n1 lines to wait\n4 lines to wait\n8 lines to wait\nOthers Reserved", + "WidgetValues": [ + { + "Key": "0 lines to wait", + "Value": "0" + }, + { + "Key": "1 lines to wait", + "Value": "1" + }, + { + "Key": "4 lines to wait", + "Value": "2" + }, + { + "Key": "8 lines to wait", + "Value": "3" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Idle frames to wait: ", + "Visibility": "", + "Data": [ + "9", + "PSR_IdleFrames2Wait_16" + ], + "HelpText": "Idle frames to wait for PSR enable.\nAllowed values 0-15. Default value is 0.", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Clock Recovery Time: ", + "Visibility": "", + "Data": [ + "9", + "PSR_TP1_WaitTime_16" + ], + "HelpText": "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)", + "WidgetValues": [ + { + "Key": "500 usec", + "Value": "0" + }, + { + "Key": "100 usec", + "Value": "1" + }, + { + "Key": "2.5 msec", + "Value": "2" + }, + { + "Key": "0 (Skip)", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Channel Equalization Time for PSR1 panel: ", + "Visibility": "", + "Data": [ + "9", + "PSR1_TP_2_3_4_WaitTime_16" + ], + "HelpText": "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) or TP4(Training Pattern4) time during PSR1 exit(wake up)", + "WidgetValues": [ + { + "Key": "500 usec", + "Value": "0" + }, + { + "Key": "100 usec", + "Value": "1" + }, + { + "Key": "2.5 msec", + "Value": "2" + }, + { + "Key": "0 (Skip)", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Channel Equalization Time for PSR2 panel: ", + "Visibility": "", + "Data": [ + "9", + "PSR2_TP_2_3_4_WaitTime_16" + ], + "HelpText": "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) or TP4(Training Pattern4) time during PSR2 exit(wake up)", + "WidgetValues": [ + { + "Key": "500 usec", + "Value": "0" + }, + { + "Key": "100 usec", + "Value": "1" + }, + { + "Key": "2.5 msec", + "Value": "2" + }, + { + "Key": "50 usec", + "Value": "3" + } + ] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-16-4", + "PageName": "Apical Feature", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Apical Assertive Display IP: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Apical_Display_Ip_Enable_16" + ], + "HelpText": "This field enables/disables the Apical Assertive Display IP for this panel.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Panel OUI (IEEE OUI): ", + "Visibility": "", + "Data": [ + "27", + "eDP_Panel_Oui_16" + ], + "HelpText": "This field specifies the Apical IP specific Panel OUI field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " DPCD Base Address: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Dpcd_Base_Address_16" + ], + "HelpText": "This field specifies the Apical IP specific DPCD base address field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " DPCD Irdidix Control 0: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Dpcd_Irdidix_Control0_16" + ], + "HelpText": "This field specifies the Apical IP specific DPCD Irdidix control 0 field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " DPCD Option Select: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Dpcd_Option_Select_16" + ], + "HelpText": "This field specifies the Apical IP specific DPCD option select field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " DPCD Backlight: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Dpcd_Backlight_16" + ], + "HelpText": "This field specifies the Apical IP specific backlight value.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Ambient Light: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Ambient_Light_16" + ], + "HelpText": "This field specifies the Apical IP specific Ambient light value.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Backlight scale: ", + "Visibility": "", + "Data": [ + "27", + "eDP_Backlight_Scale_16" + ], + "HelpText": "This field specifies the Apical IP specific backlight scale field.", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-16-5", + "PageName": "Power Features", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Intel Display Power Saving Technology (DPST) (Mobile only): ", + "Visibility": "", + "Data": [ + "44", + "DPST_Enable_16" + ], + "HelpText": "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled.\nIntel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power.\nNote: This technology is only active when the system is running in battery mode and the LFP is the only active display device.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Intel Display Refresh Rate Switching (DRRS) (Mobile only): ", + "Visibility": "", + "Data": [ + "44", + "DRRS_Enable_16" + ], + "HelpText": "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Edge Luminance Profile (ELP) : ", + "Visibility": "", + "Data": [ + "44", + "ELP_Enable_16" + ], + "HelpText": "This feature determines whether the ELP feature is enabled or disabled.\nEdge Luminance Profile (ELP) is a panel technology which reduce luminance on the edge of screen to save panel power.\nNote:This technology cannot co-exist with DPST and OPST ((i.e.) OPST, DPST and ELP cannot exist together.They are all mutually exclusive to each other.)", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " OLED Power Saving Technology (OPST) : ", + "Visibility": "", + "Data": [ + "44", + "OPST_Enable_16" + ], + "HelpText": "This feature determines whether the OPST feature is enabled or disabled.\nOLED Power Saving Technology (OPST) is a panel technology which saves power by intelligent, adaptive dimming of midrange pixel values more aggressively than the extremes without compromising the viewability.\nNote: This technology cannot co-exist with ELP and DPST ((i.e.) OPST, DPST and ELP cannot exist together.They are all mutually exclusive to each other.)", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Dynamic Media Refresh Rate Switching Enable/Disable ", + "Visibility": "", + "Data": [ + "44", + "DMRRS_Enable_16" + ], + "HelpText": "This feature determines whether Dynamic media refresh rate switching is to be enabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Enable Display Lace Support: ", + "Visibility": "", + "Data": [ + "44", + "LACE_Enable_16" + ], + "HelpText": "This feature, when enabled, will set Display Lace Support otherwise, the functionality will be disabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Panel Self Refresh (PSR): ", + "Visibility": "", + "Data": [ + "44", + "PSR_Enable_16" + ], + "HelpText": "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Assertive Display Technology Enable/Disable: ", + "Visibility": "", + "Data": [ + "44", + "ADT_Enable_16" + ], + "HelpText": "This feature determines whether Assertive display technology is to be enabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Intel Automatic Display Brightness (ADB) (Mobile only): ", + "Visibility": "", + "Data": [ + "44", + "ADB_Enable_16" + ], + "HelpText": "This feature determines whether Intel Automatic Display Brightness is to be enabled. Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) depending on the current ambient light environment.\nWhen enabled, the driver and VBIOS will control the backlight brightness of the LFP depending on the ambient environment if and only if the LFP is the only active display. When disabled, the driver will perform no action.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "EDP 4k/2k HOBL Feature: ", + "Visibility": "", + "Data": [ + "44", + "eDP_4k_2k_HOBL_feature_Enable_16" + ], + "HelpText": "This feature will allow users to disable/enable the edp 4k/2k HOBL(Hours Of Battery Life) feature by programming relevant registers specific for a platform.\r\n.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Default Display LACE Enabled status: ", + "Visibility": "", + "Data": [ + "44", + "LACE_Status_16" + ], + "HelpText": "This feature, when enabled, will set Default Display LACE Enabled status otherwise, the functionality will be disabled.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "DPST Aggressiveness Level: ", + "Visibility": "", + "Data": [ + "44", + "DPST_Aggressiveness_Profile_16" + ], + "HelpText": "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n1 (Maximum Quality with No DPST)\n2\n3\n4\n5\n6 (Maximum Battery)", + "WidgetValues": [ + { + "Key": "1 - Maximum Quality with No DPST", + "Value": "1" + }, + { + "Key": "2", + "Value": "2" + }, + { + "Key": "3", + "Value": "3" + }, + { + "Key": "4", + "Value": "4" + }, + { + "Key": "5", + "Value": "5" + }, + { + "Key": "6 - Maximum Battery", + "Value": "6" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "LACE Aggressiveness Level: ", + "Visibility": "", + "Data": [ + "44", + "LACE_Aggressiveness_Profile_16" + ], + "HelpText": "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\nMinimum 0\nModerate 1\nHigh 2", + "WidgetValues": [ + { + "Key": "Minimum", + "Value": "0" + }, + { + "Key": "Moderate", + "Value": "1" + }, + { + "Key": "High", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "ELP Aggressiveness Level: ", + "Visibility": "", + "Data": [ + "44", + "ELP_Aggressiveness_Profile_16" + ], + "HelpText": "This feature allows for the selection of ELP Aggressiveness level for this Panel Type.\nMinimum Power Savings\nMedium Power Savings \nMaximum Power Savings", + "WidgetValues": [ + { + "Key": "Minimum Power Savings", + "Value": "0" + }, + { + "Key": "Medium Power Savings", + "Value": "1" + }, + { + "Key": "Maximum Power Savings", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "OPST Aggressiveness Level: ", + "Visibility": "", + "Data": [ + "44", + "OPST_Aggressiveness_Profile_16" + ], + "HelpText": "This feature allows for the selection of OPST Aggressiveness level for this Panel Type.\nMinimum Power Savings\nMedium Power Savings \nMaximum Power Savings", + "WidgetValues": [ + { + "Key": "Minimum Power Savings", + "Value": "0" + }, + { + "Key": "Medium Power Savings", + "Value": "1" + }, + { + "Key": "Maximum Power Savings", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Default Display VRR Enabled status: ", + "Visibility": "", + "Data": [ + "44", + "VRR_Status_16" + ], + "HelpText": "VRR (Variable Refresh Rate) is a feature that can continuously and seamlessly vary Refresh Rate on the fly, on displays that support Variable Refresh rate Technologies.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-16-6", + "PageName": "Generic DTD Timings", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Pixel Clock in KHz: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_Pixel_CLK_16" + ], + "HelpText": "Pixel Clock (in KHz) Range from 0.001 to 4294967.295 MP/s.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Active: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_Active_16" + ], + "HelpText": "Horizontal Active Image Pixels Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Active: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_Active_16" + ], + "HelpText": "Vertical Active Image Lines Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Blank: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_Blank_16" + ], + "HelpText": "Horizontal Blank Pixels Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Blank: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_Blank_16" + ], + "HelpText": "Vertical Blank lines Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Front Porch: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_FrontPorch_16" + ], + "HelpText": "Horizontal Front Porch Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Front Porch: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_FrontPorch_16" + ], + "HelpText": "Vertical Front Porch Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Sync: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_Sync_16" + ], + "HelpText": "Horizontal Sync Width Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Sync: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_Sync_16" + ], + "HelpText": "Vertical Sync Width Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Image Size: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_H_Image_Size_16" + ], + "HelpText": "Horizontal Addressable Video Image Size in mm represented by 16bits. Image size multiplier 1.00 mm precision.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Image Size: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_V_Image_Size_16" + ], + "HelpText": "Vertical Addressable Video Image Size in mm represented by 16bits. Image size multiplier 1.00 mm precision.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryBin", + "WidgetName": "Common Flag: ", + "Visibility": "", + "Data": [ + "58", + "LFP_DTD_Common_Flag_16" + ], + "HelpText": "Common DTD Flags:\nBit 7 : Horizontal Sync Polarity\n1 : Positive\n0 : Negative\nBit 6 : Vertical Sync polarity\n1 : Positive\n0 : Negative\nBit 5 - 0: Reserved (Default value 0)", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-16-7", + "PageName": "LFP PnP ID Table", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Table", + "WidgetName": "", + "Visibility": "", + "Data": [ + "42", + "LFP_Panel_PnP_ID_16" + ], + "HelpText": "This feature allows the 10 bytes of EDID Vendor/Product ID starting at offset 08h to be used as a PnP ID.\n\nTable Definition:\n\tWord: ID Manufacturer Name\n\tWord: ID Product Code\n\tDWord: ID Serial Number\n\tByte: Week of Manufacture\n\tByte: Year of Manufacture", + "WidgetValues": [ + { + "ColumnName": "PnP ID", + "SizeinBytes": "1" + } + ] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-16-8", + "PageName": "Backlight Control Parameters", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Inverter Type: ", + "Visibility": "", + "Data": [ + "43", + "BLC_Inv_Type_16" + ], + "HelpText": "This feature allows for the selection of the Backlight Inverter type that is to be used to control the backlight brightness of the LFP.\nWhen PWM is selected, the driver and VBIOS will control the backlight brightness via the integrated PWM solution for the applicable chipsets.\nWhen None/External is selected, the system BIOS will control the backlight brightness via the external solution.", + "WidgetValues": [ + { + "Key": "None/External", + "Value": "0" + }, + { + "Key": "PWM", + "Value": "2" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Pwm Source Selection: ", + "Visibility": "", + "Data": [ + "43", + "Lfp_Pwm_Source_Selection_16" + ], + "HelpText": "If panel supports 'Intel HDR AUX Interface', it will always be chosen by default. If not, value in 'PWM Source Selection' will be used", + "WidgetValues": [ + { + "Key": "PWM From Display Engine", + "Value": "2" + }, + { + "Key": "PWM From LCD Panel", + "Value": "3" + }, + { + "Key": "Panel Driver Interface", + "Value": "4" + }, + { + "Key": "VESA eDP AUX Interface", + "Value": "5" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Pwm Controller Selection: ", + "Visibility": "", + "Data": [ + "43", + "Lfp_Pwm_Controller_Selection_16" + ], + "HelpText": "This field allows to select the PWM Controller to be used for the selected Local Flat Panel.This field allows to select the PWM Controller to be used for the selected Local Flat Panel.If Two LFPs are connected then PWM0 and PWM1 must be selected accordingly.", + "WidgetValues": [ + { + "Key": "PWM0", + "Value": "0" + }, + { + "Key": "PWM1", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Inverter Polarity: ", + "Visibility": "", + "Data": [ + "43", + "BLC_Inv_Polarity_16" + ], + "HelpText": "This feature allows the backlight inverter polarity to be specified.\nNormal means 0 value is minimum brightness.\nInverted means 0 value is maximum brightness.", + "WidgetValues": [ + { + "Key": "Normal", + "Value": "0" + }, + { + "Key": "Inverted", + "Value": "1" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Minimum Brightness: ", + "Visibility": "", + "Data": [ + "43", + "Post_Min_Brightness_16" + ], + "HelpText": "This feature allows defining the absolute minimum backlight brightness. The driver will never decrease the backlight less than this value. The value must be specified using normal polarity semantics. The value should range from 0 to 255 if the brightness precision bit is chosen to be 8, and it should range from 0 to 65535 if the precision bit is chosen to be 16.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "POST Backlight Intensity: ", + "Visibility": "", + "Data": [ + "43", + "Post_Brightness_16" + ], + "HelpText": "This feature is used to set default backlight brightness value of the panel at POST. The value should range from 0 to 255 if the bit precision is chosen to be 8 and it should range from 0 to 65535 if the brightness bit precision is chosent to be 16.", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Brightness Precision Bits: ", + "Visibility": "", + "Data": [ + "43", + "BrightnessPrecisionBits_16" + ], + "HelpText": "This field represents the range of brightness in terms of bit precision.\n 8 = Brightness range of 0 to 255.\n 16 = Brightness range of 0 to 65535", + "WidgetValues": [ + { + "Key": "8", + "Value": "8" + }, + { + "Key": "16", + "Value": "16" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "PWM Inverter Frequency (Hz): ", + "Visibility": "", + "Data": [ + "43", + "PWM_Frequency_16" + ], + "HelpText": "This feature allows for the definition of the frequency needed for PWM Inverter.\nNote: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Intel HDR DPCD Refresh Timeout (unit - 10 micro seconds): ", + "Visibility": "", + "Data": [ + "43", + "HdrDpcdRefreshTimeout_16" + ], + "HelpText": "This field allows to configure the refresh timeout of Intel HDR DPCDs for different TCON Vendors.\nNote:\n\tThe value is in units of 10 microseconds.\n\tThe range (entered as a decimal number), for the timeout is 0-65535", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-16-9", + "PageName": "Chromaticity Control", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Chromaticity Control Feature: ", + "Visibility": "", + "Data": [ + "46", + "Chromacity_Enable_16" + ], + "HelpText": "This bit enables Chromaticity feature.\nIf this bit is enabled, EDID values for chromaticity will be used, else feature is disabled.\nFeature will be supported for Panels that support EDID version 1.4 or higher.\nPlease refer to section 3.7 of EDID Specification 1.4.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Override the EDID values: ", + "Visibility": "", + "Data": [ + "46", + "Override_EDID_Data_16" + ], + "HelpText": "This option when enabled along with Chromaticity feature will override EDID values through following VBT data", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Red_Green_bits (Bits 1:0 at 19h): ", + "Visibility": "", + "Data": [ + "46", + "Red_Green_16" + ], + "HelpText": "Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Blue_White_bits (Bits 1:0 at 1Ah): ", + "Visibility": "", + "Data": [ + "46", + "Blue_White_16" + ], + "HelpText": "Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Red_x (Bits 9:2 at 1Bh): ", + "Visibility": "", + "Data": [ + "46", + "Red_x_16" + ], + "HelpText": "Bits 9:2 of red color x coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Red_y (Bits 9:2 at 1Ch): ", + "Visibility": "", + "Data": [ + "46", + "Red_y_16" + ], + "HelpText": "Bits 9:2 of red color y coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Green_x (Bits 9:2 at 1Dh): ", + "Visibility": "", + "Data": [ + "46", + "Green_x_16" + ], + "HelpText": "Bits 9:2 of Green color x coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Green_y (Bits 9:2 at 1Eh): ", + "Visibility": "", + "Data": [ + "46", + "Green_y_16" + ], + "HelpText": "Bits 9:2 of Green color y coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Blue_x (Bits 9:2 at 1Fh): ", + "Visibility": "", + "Data": [ + "46", + "Blue_x_16" + ], + "HelpText": "Bits 9:2 of Blue color x coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Blue_y (Bits 9:2 at 20h): ", + "Visibility": "", + "Data": [ + "46", + "Blue_y_16" + ], + "HelpText": "Bits 9:2 of Blue color y coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " White_x (Bits 9:2 at 21h): ", + "Visibility": "", + "Data": [ + "46", + "White_x_16" + ], + "HelpText": "Bits 9:2 of White color x coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " White_y (Bits 9:2 at 22h): ", + "Visibility": "", + "Data": [ + "46", + "White_y_16" + ], + "HelpText": "Bits 9:2 of White color y coordinate", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Override Luminance values ", + "Visibility": "", + "Data": [ + "46", + "Override_LUM_Data_16" + ], + "HelpText": "This option when enabled along with Chromaticity feature will override luminance values following VBT values", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Minimum Luminance: ", + "Visibility": "", + "Data": [ + "46", + "MinLuminance_16" + ], + "HelpText": "Minimum luminance value.\n2 byte value, encoded in IEEE 754 half-precision binary floating point format,", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Maximum full frame luminance: ", + "Visibility": "", + "Data": [ + "46", + "MaxFullLuminance_16" + ], + "HelpText": "Maximum Full frame luminance value.\n2 byte value, encoded in IEEE 754 half-precision binary floating point format,", + "WidgetValues": [] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Maximum Luminance: ", + "Visibility": "", + "Data": [ + "46", + "MaxLuminance_16" + ], + "HelpText": "Maximum luminance value(Relatively smaller portion of screen).\n2 byte value, encoded in IEEE 754 half-precision binary floating point format.", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Override Gamma values: ", + "Visibility": "", + "Data": [ + "46", + "Override_Gamma_Data_16" + ], + "HelpText": "This option when enabled along with Chromaticity feature will override gamma values through following VBT data", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "EntryHex", + "WidgetName": " Panel gamma: ", + "Visibility": "", + "Data": [ + "46", + "Gamma_16" + ], + "HelpText": "Value shall define the gamma range, from 1.00 to 3.54, as follows:\nField Value = (Gamma (value in float) x 100) - 100\nField values range from 00h through FFh.\nFFh = No gamma information shall be provided", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-2-16-10", + "PageName": "VESA DSC Parameters", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "DSC Major Version: ", + "Visibility": "", + "Data": [ + "56", + "C16_Major_Dsc_Version" + ], + "HelpText": "VESA DSC Major revision field.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "DSC Minor Version: ", + "Visibility": "", + "Data": [ + "56", + "C16_Minor_Dsc_Version" + ], + "HelpText": "VESA DSC Minor revision field.", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Block prediction supported: ", + "Visibility": "", + "Data": [ + "56", + "C16_Blk_Prediction_En" + ], + "HelpText": "Sink supports block prediction as per the VESA DSC Spec.", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "RC Buffer Block size as per VESA DSC Spec: ", + "Visibility": "", + "Data": [ + "56", + "C16_RC_Block_Size" + ], + "HelpText": "RC buffer block size for a single RC buffer as defined by the VESA DSC spec.", + "WidgetValues": [ + { + "Key": "1 KB", + "Value": "0" + }, + { + "Key": "4 KB", + "Value": "1" + }, + { + "Key": "16 KB", + "Value": "2" + }, + { + "Key": "64 KB", + "Value": "3" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Number of RC buffer blocks as per VESA DSC Spec: ", + "Visibility": "", + "Data": [ + "56", + "C16_Dsc_RC_Buf_Size" + ], + "HelpText": "This field defines the number of RC buffers as per VESA DSC spec.\nThe number of RC buffers used by the software shall be (Value + 1) where Value is in range 0 to 127.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryBin", + "WidgetName": "Slices per line supported by the sink device: ", + "Visibility": "", + "Data": [ + "56", + "C16_Dsc_Slices_Per_Line" + ], + "HelpText": "This field defines the slices per line supported by the sink device.\nThe field is defined in bitmap fashion and details of each bits are as defined below:\n\tBits 31-10\t\t Bit 9\tBit 8\tBit 7\tBit 6\tBit 5\tBit 4\t Bit 3\t Bit 2\t Bit 1\t Bit 0\n\tReserved\t\t 24\t 20\t 16\t 12\t 10\t 8\t 6\t 4\t 2\t 1\nBit = 0, not supported. Bit = 1, supported\nNote: Assumption is that sink shall support all lower slices per line than maximum selected field. i.e. If it supports say 8 slices per line, it will also support 4/2/1 slices per line", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Line buffer depth as per VESA DSC Spec: ", + "Visibility": "", + "Data": [ + "56", + "C16_Line_Buffer_Depth" + ], + "HelpText": "Line buffer depth in bits as per VESA DSC spec.", + "WidgetValues": [ + { + "Key": "8 bits", + "Value": "0" + }, + { + "Key": "9 bits", + "Value": "1" + }, + { + "Key": "10 bits", + "Value": "2" + }, + { + "Key": "11 bits", + "Value": "3" + }, + { + "Key": "12 bits", + "Value": "4" + }, + { + "Key": "13 bits", + "Value": "5" + }, + { + "Key": "14 bits", + "Value": "6" + }, + { + "Key": "15 bits", + "Value": "7" + }, + { + "Key": "16 bits", + "Value": "8" + } + ] + }, + { + "WidgetType": "EntryBin", + "WidgetName": "Input compression BPC supported by the sink device: ", + "Visibility": "", + "Data": [ + "56", + "C16_Dsc_Bpc" + ], + "HelpText": "This field defines the compression input bpc supported by the sink device.\nThe field is defined in bitmap fashion and details of each bits are as defined below:\n\tBits 7-4\t Bit 3\t Bit 2\t Bit 1\t Bit 0\n\tRsvd\t 12 bpc\t 10bpc\t 8bpc\t Rsvd\nBit = 0, not supported. Bit = 1, supported\nNote: Assumption is that sink shall support all lower bpc values than the maximum selected field. i.e. If it supports say 12bpc, it will also support 10 and 8bpc as well", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Maximum supported compression BPP: ", + "Visibility": "", + "Data": [ + "56", + "C16_Dsc_Max_Bpp" + ], + "HelpText": "As of today, we are supporting 6/8/10/12 BPP for compression output.\nSelect the most appropriate BPP as supported by the sink.", + "WidgetValues": [ + { + "Key": "6 Bits per pixel", + "Value": "0" + }, + { + "Key": "8 Bits per pixel", + "Value": "1" + }, + { + "Key": "10 Bits per pixel", + "Value": "2" + }, + { + "Key": "12 Bits per pixel", + "Value": "3" + } + ] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Slice height supported by the sink device: ", + "Visibility": "", + "Data": [ + "56", + "C16_Dsc_Slice_Height" + ], + "HelpText": "Slice height supported by the sink device for DSC slice.\nNote: Slice height must divide the picture height uniformly.", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + } + ] + } + } + ] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-3", + "PageName": "Integrated DisplayPort/HDMI Configuration", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Label", + "WidgetName": "Configurations for DisplayPort/HDMI Solution (External Connectors): ", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Label", + "WidgetName": "DisplayPort SSC configuration: ", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " DisplayPort (External Connectors) Spread Spectrum Clock: ", + "Visibility": "", + "Data": [ + "1", + "DP_SSC_Enb" + ], + "HelpText": "This feature allow OEMs to enable/disable SSC for external DisplayPort. This feature is valid only the attached DisplayPort panel support SSC.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " DisplayPort Spread Spectrum Clock Enable/Disable for Dongles: ", + "Visibility": "", + "Data": [ + "1", + "DP_SSC_Dongle_Enb" + ], + "HelpText": "This feature is to enable or disable DisplayPort Dongle Spread Spectrum Clock when dongle are used and the attached DisplayPort panel should support SSC", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "Label", + "WidgetName": "DisplayPort Device Configuration: ", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Device 1(EFP1) Configuration", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Device 2(EFP2) Configuration", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Device 3(EFP3) Configuration", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Device 4(EFP4) Configuration", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Device 5(EFP5) Configuration", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Device 6(EFP6) Configuration", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Device 7(EFP7) Configuration", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + } + ], + "NestedPages": [ + { + "Type": "Block", + "Block": { + "PageNum": "5-3-1", + "PageName": "Device 1(EFP1) Configuration", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Select Device Type: ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP1_Type" + ], + "HelpText": "This feature specifies the Device Type for this add-in device.\n\nNote:\nDevice Type \"Integrated Display Only Internal to Chassis\" specifies if the display location is internal to the system chasis or not. \nThis Device Class Type should be configured for Port-A and Port-B only.\nIf configured as internal, OEM's must ensure that we also configure this as internal in the FIT tool for CSME FW.\nThe options should be selected as Internal only if the port is used in AIO designs and part of the system chasis. It should be set as External for physically external ports.", + "WidgetValues": [ + { + "Key": "No Device", + "Value": "0" + }, + { + "Key": "Integrated DisplayPort Only", + "Value": "26822" + }, + { + "Key": "Integrated DisplayPort with HDMI/DVI Compatible", + "Value": "24790" + }, + { + "Key": "Integrated DisplayPort with DVI Compatible", + "Value": "26838" + }, + { + "Key": "Integrated Display Only Internal to Chassis", + "Value": "18502" + }, + { + "Key": "Integrated HDMI/DVI", + "Value": "24786" + }, + { + "Key": "Integrated DVI Only", + "Value": "26834" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Select Output Port: ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP1_Port" + ], + "HelpText": "This feature specifies which DVO port the device is configured.", + "WidgetValues": [ + { + "Key": "HDMI-A", + "Value": "0" + }, + { + "Key": "HDMI-B", + "Value": "1" + }, + { + "Key": "HDMI-TC1", + "Value": "14" + }, + { + "Key": "HDMI-TC2", + "Value": "16" + }, + { + "Key": "HDMI-TC3", + "Value": "18" + }, + { + "Key": "HDMI-TC4", + "Value": "20" + }, + { + "Key": "DisplayPort-A", + "Value": "10" + }, + { + "Key": "DisplayPort-B", + "Value": "7" + }, + { + "Key": "DisplayPort TC1", + "Value": "13" + }, + { + "Key": "DisplayPort TC2", + "Value": "15" + }, + { + "Key": "DisplayPort TC3", + "Value": "17" + }, + { + "Key": "DisplayPort TC4", + "Value": "19" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Select DDC Bus GPIO Pin Pair: ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP1_DDC_Pin" + ], + "HelpText": "This feature specifies the GPIO pin pair used as DDC bus by this device. If this device doesn't support DDC bus, this field will be ignored. \t Pin Pair Value \t\t ADLP PCH mapping\n \t Pin-Pair #1\t\t DDI-A DDC\n \t Pin-Pair #2\t\t DDI-B DDC \n \t Pin-Pair #3\t\t DDI-TC1 DDC \n \t Pin-Pair #4\t\t DDI-TC2 DDC \n \t Pin-Pair #5\t\t DDI-TC3 DDC \n \t Pin-Pair #6\t\t DDI-TC4 DDC \n", + "WidgetValues": [ + { + "Key": "N/A", + "Value": "0" + }, + { + "Key": "Pin-Pair #1", + "Value": "1" + }, + { + "Key": "Pin-Pair #2", + "Value": "2" + }, + { + "Key": "Pin-Pair #3", + "Value": "3" + }, + { + "Key": "Pin-Pair #4", + "Value": "4" + }, + { + "Key": "Pin-Pair #5", + "Value": "5" + }, + { + "Key": "Pin-Pair #6", + "Value": "6" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Select AUX Channel: ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP1_AUX_Channel" + ], + "HelpText": "This feature specifies the AUX Channel for int-DisplayPort. This field is valid only if integrated DP is selected for Device Type.", + "WidgetValues": [ + { + "Key": "N/A", + "Value": "0" + }, + { + "Key": "DisplayPort-A AUX Channel", + "Value": "64" + }, + { + "Key": "DisplayPort-B AUX Channel", + "Value": "16" + }, + { + "Key": "DisplayPort TC1 AUX Channel", + "Value": "96" + }, + { + "Key": "DisplayPort TC2 AUX Channel", + "Value": "112" + }, + { + "Key": "DisplayPort TC3 AUX Channel", + "Value": "128" + }, + { + "Key": "DisplayPort TC4 AUX Channel", + "Value": "144" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Select HDMI level shifter configuration: ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP1_HDMI_LS_Type" + ], + "HelpText": "This feature specifies the Level shifter configuration for HDMI. This field is valid only if HDMI is selected for Device Type.\n\n-------------------------------------------------------------------------------------------------------------\n|\t\t\t|\tCOMBO-PHY\t|\tDKL-PHY\t\t|\n-------------------------------------------------------------------------------------------------------------\n|\tLevel 1\t\t|\t450mV 0.0dB\t|\t400mV 0dB\t\n|\tLevel 2\t\t|\t450mV 3.2dB\t|\t500mV 0dB\t|\n|\tLevel 3\t\t|\t450mV 5.5dB\t|\t650mV 0dB\t|\n|\tLevel 4\t\t|\t650mV 0.0dB\t|\t800mV 0dB\t|\n|\tLevel 5\t\t|\t650mV 2.3dB\t|\t1000mV 0dB\t|\n|\tLevel 6\t\t|\t850mV 0.0dB\t|\tFULL -1.5dB\t|\n|\tLevel 7\t\t|\t600mV 3.0dB\t|\tFULL -1.8dB\t|\n|\tLevel 8\t\t|\t450mV 0.0dB\t|\tFULL -2dB\t|\n|\tLevel 9\t\t|\t450mV 0.0dB\t|\tFULL -2.5dB\t|\n|\tLevel 10\t\t|\t450mV 0.0dB\t|\tFULL -3dB\t|\n", + "WidgetValues": [ + { + "Key": "Level 1", + "Value": "0" + }, + { + "Key": "Level 2", + "Value": "1" + }, + { + "Key": "Level 3", + "Value": "2" + }, + { + "Key": "Level 4", + "Value": "3" + }, + { + "Key": "Level 5", + "Value": "4" + }, + { + "Key": "Level 6", + "Value": "5" + }, + { + "Key": "Level 7", + "Value": "6" + }, + { + "Key": "Level 8", + "Value": "7" + }, + { + "Key": "Level 9", + "Value": "8" + }, + { + "Key": "Level 10", + "Value": "9" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Select HDMI maximum data rate: ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP1_HDMI_Maximum_Data_Rate" + ], + "HelpText": "This feature limits the maximum data rate per lane for HDMI. This field is valid only if HDMI is selected for Device Type. \n\nNote: OEM’s need to configure the maximum data rate as per mother board support.", + "WidgetValues": [ + { + "Key": "6.00 Gbps", + "Value": "0" + }, + { + "Key": "2.97 Gbps", + "Value": "1" + }, + { + "Key": "1.65 Gbps", + "Value": "2" + }, + { + "Key": "5.94 Gbps", + "Value": "3" + }, + { + "Key": "3.40 Gbps", + "Value": "4" + }, + { + "Key": "3.00 Gbps", + "Value": "5" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Select DP max Link Rate: ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP1_DP_Port_Max_LinkRate" + ], + "HelpText": "This feature limits the maximum link rate for DP Port. This field is valid only if DP is selected for Device Type. \n\nHBR3 is the max Link rate supported by ADL-P/M/N. UHBR link rates are supported only by RPL-P. So, choosing a Link rate greater than HBR3 for ADL-P/M/N will automatically force a fallback to HBR3 in GOP and gfx-driver. \n\nNote: OEM’s need to configure the maximum Link rate as per mother board support.", + "WidgetValues": [ + { + "Key": "Default Max Link Rate supported by Plaftform", + "Value": "0" + }, + { + "Key": "LBR (1.62 Gbps)", + "Value": "1" + }, + { + "Key": "HBR (2.7 Gbps)", + "Value": "2" + }, + { + "Key": "HBR2 (5.4 Gbps)", + "Value": "3" + }, + { + "Key": "HBR3 (8.1 Gbps)", + "Value": "4" + }, + { + "Key": "UHBR10 (10 Gbps)", + "Value": "5" + }, + { + "Key": "UHBR13_5 (13.5 Gbps)", + "Value": "6" + }, + { + "Key": "UHBR20 (20 Gbps)", + "Value": "7" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Select DP Port Max Lane Count Supported: ", + "Visibility": "", + "Data": [ + "2", + "EFP1_EDP_DP_Port_Max_LaneCount" + ], + "HelpText": "This feature allows for the selection of the Port Max Lane Count (Port Width) for the EDP/DP link.", + "WidgetValues": [ + { + "Key": "x1", + "Value": "0" + }, + { + "Key": "x2", + "Value": "1" + }, + { + "Key": "x4", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "EDIDless Panel: ", + "Visibility": "", + "Data": [ + "2", + "EFP1_EDIDless_en" + ], + "HelpText": "If the Attached panel is EDIDless select Yes and the supplied DTD takes priority.", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "Button", + "WidgetName": "EDID-less EFP Panel Generic DTD Timings", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "LTTPR(Link-Training Tunable PHY Repeaters) Mode: ", + "Visibility": "", + "Data": [ + "2", + "EFP1_LTTPRNonTransparentMode" + ], + "HelpText": "This option is used to enable or disable the LTTPR Non transparent Mode.", + "WidgetValues": [ + { + "Key": "Non-Transparent Mode", + "Value": "1" + }, + { + "Key": "Transparent Mode", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Max FrlRate Field Status", + "Visibility": "", + "Data": [ + "2", + "EFP1_IsMaxFrlRateFieldValid" + ], + "HelpText": "Indicates if we need to consider the MaxFrlRate field for HDMI2.1\nDisable - Don't consider the MaximumFrlRate for limiting the FrlRates on HDMI2.1 displays\nEnable - MaximumFrlRate given in bits 0 to 3 are used to override Max FRL Rate supported by platform/panel", + "WidgetValues": [ + { + "Key": "Disabled", + "Value": "0" + }, + { + "Key": "Enabled", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Maximum FrlRate ", + "Visibility": "", + "Data": [ + "2", + "EFP1_MaximumFrlRate" + ], + "HelpText": "0000 = FrlRates not supported (HDMI 2.1 is limited to support only TMDS modes)\n0001 = 3 GT/s\n0010 = 6 GT/s\n0011 = 8 GT/s\n0100 = 10 GT/s\n0101 = 12 GT/s", + "WidgetValues": [ + { + "Key": "FrlRates not supported", + "Value": "0" + }, + { + "Key": "3 GT/s", + "Value": "1" + }, + { + "Key": "6 GT/s", + "Value": "2" + }, + { + "Key": "8 GT/s", + "Value": "3" + }, + { + "Key": "10 GT/s", + "Value": "4" + }, + { + "Key": "12 GT/s", + "Value": "5" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "DP to HDMI Pcon: ", + "Visibility": "", + "Data": [ + "2", + "LSPcon1_Options" + ], + "HelpText": "This option is used to enable or disable the OnBoard LSPCON chip.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "DDI Lane Reversal: ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP1_Lane_Reversal" + ], + "HelpText": "This feature, when enabled, will set lane reversal bit for selected Port", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "DP Alt mode over Type C: ", + "Visibility": "", + "Data": [ + "2", + "EFP1_DP_Alt_Mode_OverTypeC_Enabled" + ], + "HelpText": "This option Enables/Disables DP alternate mode over type C ports.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "DP Tunneling over Thunderbolt: ", + "Visibility": "", + "Data": [ + "2", + "EFP1_Thunderbolt_Feature_Enabled" + ], + "HelpText": "This option Enables/Disables DP tunneling over Thunderbolt for selected Port.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Dockable Port: ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP1_Port_Dockable" + ], + "HelpText": "This feature will describe if this Port is Dockable or Not.", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "Label", + "WidgetName": "Select DisplayPort Redriver ", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Vswing PreEmphasis Table Override: ", + "Visibility": "", + "Data": [ + "2", + "INT_EFP1_Vswing_Override_Enable" + ], + "HelpText": "This feature, when enabled, will allow Graphics driver to use the Vswing and Pre-emphasis values from VBT. OEM's must not enable or disable this on their own and work with the Intel CE team to change any settings in this page. When this field is enabled, corresponding table must be populated in the VBT for PHY Vswing parameters too.", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + } + ], + "NestedPages": [ + { + "Type": "Block", + "Block": { + "PageNum": "5-3-1-1", + "PageName": "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Non-dock topology: (OnBoard) ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP1_OnBoard_Redriver_Present" + ], + "HelpText": "This feature will describe if Non-Dock Topology/OnBoard Redriver DP Link is present or Not.", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Pre-Emphasis Level: ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP1_OnBoard_Pre_emphasis" + ], + "HelpText": "This feature allows for the selection of Pre-emphasis level for the OnBoard redriver DP link.\nLevel 0 (0 dB)\nLevel 1 (3.5 dB)\nLevel 2 (6.0 dB)\nLevel 3 (9.5 dB)", + "WidgetValues": [ + { + "Key": "Level-0", + "Value": "0" + }, + { + "Key": "Level-1", + "Value": "1" + }, + { + "Key": "Level-2", + "Value": "2" + }, + { + "Key": "Level-3", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Voltage Swing Level: ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP1_OnBoard_Voltage_swing" + ], + "HelpText": "This feature allows for the selection of voltage swing level for the OnBoard redriver DP link.\nSwing-0 (0.4 V)\nSwing-1 (0.6 V)\nSwing-2 (0.8 V)\nSwing-3 (1.2 V)", + "WidgetValues": [ + { + "Key": "Swing-0", + "Value": "0" + }, + { + "Key": "Swing-1", + "Value": "1" + }, + { + "Key": "Swing-2", + "Value": "2" + }, + { + "Key": "Swing-3", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Dock Topology: (Mobile only) ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP1_Dock_Redriver_Present" + ], + "HelpText": "This feature will describe if Dock Topology/Dock Redriver DP Link is present or not.", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Pre-Emphasis Level: ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP1_Dock_Pre_emphasis" + ], + "HelpText": "This feature allows for the selection of Pre-emphasis level for the Dock redriver DP link.\nLevel 0 (0 dB)\nLevel 1 (3.5 dB)\nLevel 2 (6.0 dB)\nLevel 3 (9.5 dB)", + "WidgetValues": [ + { + "Key": "Level-0", + "Value": "0" + }, + { + "Key": "Level-1", + "Value": "1" + }, + { + "Key": "Level-2", + "Value": "2" + }, + { + "Key": "Level-3", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Voltage Swing Level: ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP1_Dock_Voltage_swing" + ], + "HelpText": "This feature allows for the selection of voltage swing level for the Dock redriver DP link.\nSwing-0 (0.4 V)\nSwing-1 (0.6 V)\nSwing-2 (0.8 V)\nSwing-3 (1.2 V)", + "WidgetValues": [ + { + "Key": "Swing-0", + "Value": "0" + }, + { + "Key": "Swing-1", + "Value": "1" + }, + { + "Key": "Swing-2", + "Value": "2" + }, + { + "Key": "Swing-3", + "Value": "3" + } + ] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-3-1-2", + "PageName": "EDID-less EFP Panel Generic DTD Timings", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Pixel Clock in KHz: ", + "Visibility": "", + "Data": [ + "58", + "EFP_DTD_Pixel_CLK_01" + ], + "HelpText": "Pixel Clock (in KHz) Range from 0.001 to 4294967.295 MP/s.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Active: ", + "Visibility": "", + "Data": [ + "58", + "EFP_DTD_H_Active_01" + ], + "HelpText": "Horizontal Active Image Pixels Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Active: ", + "Visibility": "", + "Data": [ + "58", + "EFP_DTD_V_Active_01" + ], + "HelpText": "Vertical Active Image Lines Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Blank: ", + "Visibility": "", + "Data": [ + "58", + "EFP_DTD_H_Blank_01" + ], + "HelpText": "Horizontal Blank Pixels Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Blank: ", + "Visibility": "", + "Data": [ + "58", + "EFP_DTD_V_Blank_01" + ], + "HelpText": "Vertical Blank lines Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Front Porch: ", + "Visibility": "", + "Data": [ + "58", + "EFP_DTD_H_FrontPorch_01" + ], + "HelpText": "Horizontal Front Porch Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Front Porch: ", + "Visibility": "", + "Data": [ + "58", + "EFP_DTD_V_FrontPorch_01" + ], + "HelpText": "Vertical Front Porch Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Sync: ", + "Visibility": "", + "Data": [ + "58", + "EFP_DTD_H_Sync_01" + ], + "HelpText": "Horizontal Sync Width Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Sync: ", + "Visibility": "", + "Data": [ + "58", + "EFP_DTD_V_Sync_01" + ], + "HelpText": "Vertical Sync Width Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Image Size: ", + "Visibility": "", + "Data": [ + "58", + "EFP_DTD_H_Image_Size_01" + ], + "HelpText": "Horizontal Addressable Video Image Size in mm represented by 16bits. Image size multiplier 1.00 mm precision.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Image Size: ", + "Visibility": "", + "Data": [ + "58", + "EFP_DTD_V_Image_Size_01" + ], + "HelpText": "Vertical Addressable Video Image Size in mm represented by 16bits. Image size multiplier 1.00 mm precision.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryBin", + "WidgetName": "Common Flag: ", + "Visibility": "", + "Data": [ + "58", + "EFP_DTD_Common_Flag_01" + ], + "HelpText": "Common DTD Flags:\nBit 7 : Horizontal Sync Polarity\n1 : Positive\n0 : Negative\nBit 6 : Vertical Sync polarity\n1 : Positive\n0 : Negative\nBit 5 - 0: Reserved (Default value 0)", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + } + ] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-3-2", + "PageName": "Device 2(EFP2) Configuration", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Select Device Type: ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP2_Type" + ], + "HelpText": "This feature specifies the Device Type for this add-in device.\n\nNote:\nDevice Type \"Integrated Display Only Internal to Chassis\" specifies if the display location is internal to the system chasis or not. \nThis Device Class Type should be configured for Port-A and Port-B only.\nIf configured as internal, OEM's must ensure that we also configure this as internal in the FIT tool for CSME FW.\nThe options should be selected as Internal only if the port is used in AIO designs and part of the system chasis. It should be set as External for physically external ports.", + "WidgetValues": [ + { + "Key": "No Device", + "Value": "0" + }, + { + "Key": "Integrated DisplayPort Only", + "Value": "26822" + }, + { + "Key": "Integrated DisplayPort with HDMI/DVI Compatible", + "Value": "24790" + }, + { + "Key": "Integrated DisplayPort with DVI Compatible", + "Value": "26838" + }, + { + "Key": "Integrated Display Only Internal to Chassis", + "Value": "18502" + }, + { + "Key": "Integrated HDMI/DVI", + "Value": "24786" + }, + { + "Key": "Integrated DVI Only", + "Value": "26834" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Select Output Port: ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP2_Port" + ], + "HelpText": "This feature specifies which DVO port the device is configured.", + "WidgetValues": [ + { + "Key": "HDMI-A", + "Value": "0" + }, + { + "Key": "HDMI-B", + "Value": "1" + }, + { + "Key": "HDMI-TC1", + "Value": "14" + }, + { + "Key": "HDMI-TC2", + "Value": "16" + }, + { + "Key": "HDMI-TC3", + "Value": "18" + }, + { + "Key": "HDMI-TC4", + "Value": "20" + }, + { + "Key": "DisplayPort-A", + "Value": "10" + }, + { + "Key": "DisplayPort-B", + "Value": "7" + }, + { + "Key": "DisplayPort-TC1", + "Value": "13" + }, + { + "Key": "DisplayPort-TC2", + "Value": "15" + }, + { + "Key": "DisplayPort-TC3", + "Value": "17" + }, + { + "Key": "DisplayPort-TC4", + "Value": "19" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Select DDC Bus GPIO Pin Pair: ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP2_DDC_Pin" + ], + "HelpText": "This feature specifies the GPIO pin pair used as DDC bus by this device. If this device doesn't support DDC bus, this field will be ignored. \t Pin Pair Value \t\t ADLP PCH mapping\n \t Pin-Pair #1\t\t DDI-A DDC\n \t Pin-Pair #2\t\t DDI-B DDC \n \t Pin-Pair #3\t\t DDI-TC1 DDC \n \t Pin-Pair #4\t\t DDI-TC2 DDC \n \t Pin-Pair #5\t\t DDI-TC3 DDC \n \t Pin-Pair #6\t\t DDI-TC4 DDC \n", + "WidgetValues": [ + { + "Key": "N/A", + "Value": "0" + }, + { + "Key": "Pin-Pair #1", + "Value": "1" + }, + { + "Key": "Pin-Pair #2", + "Value": "2" + }, + { + "Key": "Pin-Pair #3", + "Value": "3" + }, + { + "Key": "Pin-Pair #4", + "Value": "4" + }, + { + "Key": "Pin-Pair #5", + "Value": "5" + }, + { + "Key": "Pin-Pair #6", + "Value": "6" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Select AUX Channel: ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP2_AUX_Channel" + ], + "HelpText": "This feature specifies the AUX Channel for int-DisplayPort. This field is valid only if integrated DP is selected for Device Type.", + "WidgetValues": [ + { + "Key": "N/A", + "Value": "0" + }, + { + "Key": "DisplayPort-A AUX Channel", + "Value": "64" + }, + { + "Key": "DisplayPort-B AUX Channel", + "Value": "16" + }, + { + "Key": "DisplayPort TC1 AUX Channel", + "Value": "96" + }, + { + "Key": "DisplayPort TC2 AUX Channel", + "Value": "112" + }, + { + "Key": "DisplayPort TC3 AUX Channel", + "Value": "128" + }, + { + "Key": "DisplayPort TC4 AUX Channel", + "Value": "144" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Select HDMI level shifter configuration: ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP2_HDMI_LS_Type" + ], + "HelpText": "This feature specifies the Level shifter configuration for HDMI. This field is valid only if HDMI is selected for Device Type.\n\n-------------------------------------------------------------------------------------------------------------\n|\t\t\t|\tCOMBO-PHY\t|\tDKL-PHY\t\t|\n-------------------------------------------------------------------------------------------------------------\n|\tLevel 1\t\t|\t450mV 0.0dB\t|\t400mV 0dB\t\n|\tLevel 2\t\t|\t450mV 3.2dB\t|\t500mV 0dB\t|\n|\tLevel 3\t\t|\t450mV 5.5dB\t|\t650mV 0dB\t|\n|\tLevel 4\t\t|\t650mV 0.0dB\t|\t800mV 0dB\t|\n|\tLevel 5\t\t|\t650mV 2.3dB\t|\t1000mV 0dB\t|\n|\tLevel 6\t\t|\t850mV 0.0dB\t|\tFULL -1.5dB\t|\n|\tLevel 7\t\t|\t600mV 3.0dB\t|\tFULL -1.8dB\t|\n|\tLevel 8\t\t|\t450mV 0.0dB\t|\tFULL -2dB\t|\n|\tLevel 9\t\t|\t450mV 0.0dB\t|\tFULL -2.5dB\t|\n|\tLevel 10\t\t|\t450mV 0.0dB\t|\tFULL -3dB\t|\n", + "WidgetValues": [ + { + "Key": "Level 1", + "Value": "0" + }, + { + "Key": "Level 2", + "Value": "1" + }, + { + "Key": "Level 3", + "Value": "2" + }, + { + "Key": "Level 4", + "Value": "3" + }, + { + "Key": "Level 5", + "Value": "4" + }, + { + "Key": "Level 6", + "Value": "5" + }, + { + "Key": "Level 7", + "Value": "6" + }, + { + "Key": "Level 8", + "Value": "7" + }, + { + "Key": "Level 9", + "Value": "8" + }, + { + "Key": "Level 10", + "Value": "9" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Select HDMI maximum data rate: ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP2_HDMI_Maximum_Data_Rate" + ], + "HelpText": "This feature limits the maximum data rate per lane for HDMI. This field is valid only if HDMI is selected for Device Type. \n\nNote: OEM’s need to configure the maximum data rate as per mother board support.", + "WidgetValues": [ + { + "Key": "6.00 Gbps", + "Value": "0" + }, + { + "Key": "2.97 Gbps", + "Value": "1" + }, + { + "Key": "1.65 Gbps", + "Value": "2" + }, + { + "Key": "5.94 Gbps", + "Value": "3" + }, + { + "Key": "3.40 Gbps", + "Value": "4" + }, + { + "Key": "3.00 Gbps", + "Value": "5" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Select DP max Link Rate: ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP2_DP_Port_Max_LinkRate" + ], + "HelpText": "This feature limits the maximum link rate for DP Port. This field is valid only if DP is selected for Device Type. \n\nHBR3 is the max Link rate supported by ADL-P/M/N. UHBR link rates are supported only by RPL-P. So, choosing a Link rate greater than HBR3 for ADL-P/M/N will automatically force a fallback to HBR3 in GOP and gfx-driver. \n\nNote: OEM’s need to configure the maximum Link rate as per mother board support.", + "WidgetValues": [ + { + "Key": "Default Max Link Rate supported by Plaftform", + "Value": "0" + }, + { + "Key": "LBR (1.62 Gbps)", + "Value": "1" + }, + { + "Key": "HBR (2.7 Gbps)", + "Value": "2" + }, + { + "Key": "HBR2 (5.4 Gbps)", + "Value": "3" + }, + { + "Key": "HBR3 (8.1 Gbps)", + "Value": "4" + }, + { + "Key": "UHBR10 (10 Gbps)", + "Value": "5" + }, + { + "Key": "UHBR13_5 (13.5 Gbps)", + "Value": "6" + }, + { + "Key": "UHBR20 (20 Gbps)", + "Value": "7" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Select DP Port Max Lane Count Supported: ", + "Visibility": "", + "Data": [ + "2", + "EFP2_EDP_DP_Port_Max_LaneCount" + ], + "HelpText": "This feature allows for the selection of the Port Max Lane Count (Port Width) for the EDP/DP link.", + "WidgetValues": [ + { + "Key": "x1", + "Value": "0" + }, + { + "Key": "x2", + "Value": "1" + }, + { + "Key": "x4", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "EDIDless Panel: ", + "Visibility": "", + "Data": [ + "2", + "EFP2_EDIDless_en" + ], + "HelpText": "If the Attached panel is EDIDless select Yes and the supplied DTD takes priority.", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "Button", + "WidgetName": "EDID-less EFP Panel Generic DTD Timings", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "LTTPR(Link-Training Tunable PHY Repeaters) Mode: ", + "Visibility": "", + "Data": [ + "2", + "EFP2_LTTPRNonTransparentMode" + ], + "HelpText": "This option is used to enable or disable the LTTPR Non transparent Mode.", + "WidgetValues": [ + { + "Key": "Non-Transparent Mode", + "Value": "1" + }, + { + "Key": "Transparent Mode", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Max FrlRate Field Status", + "Visibility": "", + "Data": [ + "2", + "EFP2_IsMaxFrlRateFieldValid" + ], + "HelpText": "Indicates if we need to consider the MaxFrlRate field for HDMI2.1\nDisable - Don't consider the MaximumFrlRate for limiting the FrlRates on HDMI2.1 displays\nEnable - MaximumFrlRate given in bits 0 to 3 are used to override Max FRL Rate supported by platform/panel", + "WidgetValues": [ + { + "Key": "Disabled", + "Value": "0" + }, + { + "Key": "Enabled", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Maximum FrlRate ", + "Visibility": "", + "Data": [ + "2", + "EFP2_MaximumFrlRate" + ], + "HelpText": "0000 = FrlRates not supported (HDMI 2.1 is limited to support only TMDS modes)\n0001 = 3 GT/s\n0010 = 6 GT/s\n0011 = 8 GT/s\n0100 = 10 GT/s\n0101 = 12 GT/s", + "WidgetValues": [ + { + "Key": "FrlRates not supported", + "Value": "0" + }, + { + "Key": "3 GT/s", + "Value": "1" + }, + { + "Key": "6 GT/s", + "Value": "2" + }, + { + "Key": "8 GT/s", + "Value": "3" + }, + { + "Key": "10 GT/s", + "Value": "4" + }, + { + "Key": "12 GT/s", + "Value": "5" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "DP to HDMI Pcon: ", + "Visibility": "", + "Data": [ + "2", + "LSPcon2_Options" + ], + "HelpText": "This option is used to enable or disable the OnBoard LSPCON chip.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "DDI Lane Reversal: ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP2_Lane_Reversal" + ], + "HelpText": "This feature, when enabled, will set lane reversal bit for selected Port", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "DP Alt mode over Type C: ", + "Visibility": "", + "Data": [ + "2", + "EFP2_DP_Alt_Mode_OverTypeC_Enabled" + ], + "HelpText": "This option Enables/Disables DP alternate mode over type C ports.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "DP Tunneling over Thunderbolt: ", + "Visibility": "", + "Data": [ + "2", + "EFP2_Thunderbolt_Feature_Enabled" + ], + "HelpText": "This option Enables/Disables DP tunneling over Thunderbolt for selected Port.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Dockable Port: ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP2_Port_Dockable" + ], + "HelpText": "This feature will describe if this Port is Dockable or Not.", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "Label", + "WidgetName": "Select DisplayPort Redriver ", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Vswing PreEmphasis Table Override: ", + "Visibility": "", + "Data": [ + "2", + "INT_EFP2_Vswing_Override_Enable" + ], + "HelpText": "This feature, when enabled, will allow Graphics driver to use the Vswing and Pre-emphasis values from VBT. OEM's must not enable or disable this on their own and work with the Intel CE team to change any settings in this page. When this field is enabled, corresponding table must be populated in the VBT for PHY Vswing parameters too.", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + } + ], + "NestedPages": [ + { + "Type": "Block", + "Block": { + "PageNum": "5-3-2-1", + "PageName": "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Non-dock topology: (OnBoard) ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP2_OnBoard_Redriver_Present" + ], + "HelpText": "This feature will describe if Non-Dock Topology/OnBoard Redriver DP Link is present or Not.", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Pre-Emphasis Level: ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP2_OnBoard_Pre_emphasis" + ], + "HelpText": "This feature allows for the selection of Pre-emphasis level for the OnBoard redriver DP link.\nLevel 0 (0 dB)\nLevel 1 (3.5 dB)\nLevel 2 (6.0 dB)\nLevel 3 (9.5 dB)", + "WidgetValues": [ + { + "Key": "Level-0", + "Value": "0" + }, + { + "Key": "Level-1", + "Value": "1" + }, + { + "Key": "Level-2", + "Value": "2" + }, + { + "Key": "Level-3", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Voltage Swing Level: ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP2_OnBoard_Voltage_swing" + ], + "HelpText": "This feature allows for the selection of voltage swing level for the OnBoard redriver DP link.\nSwing-0 (0.4 V)\nSwing-1 (0.6 V)\nSwing-2 (0.8 V)\nSwing-3 (1.2 V)", + "WidgetValues": [ + { + "Key": "Swing-0", + "Value": "0" + }, + { + "Key": "Swing-1", + "Value": "1" + }, + { + "Key": "Swing-2", + "Value": "2" + }, + { + "Key": "Swing-3", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Dock Topology: (Mobile only) ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP2_Dock_Redriver_Present" + ], + "HelpText": "This feature will describe if Dock Topology/Dock Redriver DP Link is present or not.", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Pre-Emphasis Level: ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP2_Dock_Pre_emphasis" + ], + "HelpText": "This feature allows for the selection of Pre-emphasis level for the Dock redriver DP link.\nLevel 0 (0 dB)\nLevel 1 (3.5 dB)\nLevel 2 (6.0 dB)\nLevel 3 (9.5 dB)", + "WidgetValues": [ + { + "Key": "Level-0", + "Value": "0" + }, + { + "Key": "Level-1", + "Value": "1" + }, + { + "Key": "Level-2", + "Value": "2" + }, + { + "Key": "Level-3", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Voltage Swing Level: ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP2_Dock_Voltage_swing" + ], + "HelpText": "This feature allows for the selection of voltage swing level for the Dock redriver DP link.\nSwing-0 (0.4 V)\nSwing-1 (0.6 V)\nSwing-2 (0.8 V)\nSwing-3 (1.2 V)", + "WidgetValues": [ + { + "Key": "Swing-0", + "Value": "0" + }, + { + "Key": "Swing-1", + "Value": "1" + }, + { + "Key": "Swing-2", + "Value": "2" + }, + { + "Key": "Swing-3", + "Value": "3" + } + ] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-3-2-2", + "PageName": "EDID-less EFP Panel Generic DTD Timings", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Pixel Clock in KHz: ", + "Visibility": "", + "Data": [ + "58", + "EFP_DTD_Pixel_CLK_02" + ], + "HelpText": "Pixel Clock (in KHz) Range from 0.001 to 4294967.295 MP/s.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Active: ", + "Visibility": "", + "Data": [ + "58", + "EFP_DTD_H_Active_02" + ], + "HelpText": "Horizontal Active Image Pixels Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Active: ", + "Visibility": "", + "Data": [ + "58", + "EFP_DTD_V_Active_02" + ], + "HelpText": "Vertical Active Image Lines Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Blank: ", + "Visibility": "", + "Data": [ + "58", + "EFP_DTD_H_Blank_02" + ], + "HelpText": "Horizontal Blank Pixels Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Blank: ", + "Visibility": "", + "Data": [ + "58", + "EFP_DTD_V_Blank_02" + ], + "HelpText": "Vertical Blank lines Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Front Porch: ", + "Visibility": "", + "Data": [ + "58", + "EFP_DTD_H_FrontPorch_02" + ], + "HelpText": "Horizontal Front Porch Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Front Porch: ", + "Visibility": "", + "Data": [ + "58", + "EFP_DTD_V_FrontPorch_02" + ], + "HelpText": "Vertical Front Porch Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Sync: ", + "Visibility": "", + "Data": [ + "58", + "EFP_DTD_H_Sync_02" + ], + "HelpText": "Horizontal Sync Width Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Sync: ", + "Visibility": "", + "Data": [ + "58", + "EFP_DTD_V_Sync_02" + ], + "HelpText": "Vertical Sync Width Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Image Size: ", + "Visibility": "", + "Data": [ + "58", + "EFP_DTD_H_Image_Size_02" + ], + "HelpText": "Horizontal Addressable Video Image Size in mm represented by 16bits. Image size multiplier 1.00 mm precision.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Image Size: ", + "Visibility": "", + "Data": [ + "58", + "EFP_DTD_V_Image_Size_02" + ], + "HelpText": "Vertical Addressable Video Image Size in mm represented by 16bits. Image size multiplier 1.00 mm precision.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryBin", + "WidgetName": "Common Flag: ", + "Visibility": "", + "Data": [ + "58", + "EFP_DTD_Common_Flag_02" + ], + "HelpText": "Common DTD Flags:\nBit 7 : Horizontal Sync Polarity\n1 : Positive\n0 : Negative\nBit 6 : Vertical Sync polarity\n1 : Positive\n0 : Negative\nBit 5 - 0: Reserved (Default value 0)", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + } + ] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-3-3", + "PageName": "Device 3(EFP3) Configuration", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Select Device Type: ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP3_Type" + ], + "HelpText": "This feature specifies the Device Type for this add-in device.\n\nNote:\nDevice Type \"Integrated Display Only Internal to Chassis\" specifies if the display location is internal to the system chasis or not. \nThis Device Class Type should be configured for Port-A and Port-B only.\nIf configured as internal, OEM's must ensure that we also configure this as internal in the FIT tool for CSME FW.\nThe options should be selected as Internal only if the port is used in AIO designs and part of the system chasis. It should be set as External for physically external ports.", + "WidgetValues": [ + { + "Key": "No Device", + "Value": "0" + }, + { + "Key": "Integrated DisplayPort Only", + "Value": "26822" + }, + { + "Key": "Integrated DisplayPort with HDMI/DVI Compatible", + "Value": "24790" + }, + { + "Key": "Integrated DisplayPort with DVI Compatible", + "Value": "26838" + }, + { + "Key": "Integrated Display Only Internal to Chassis", + "Value": "18502" + }, + { + "Key": "Integrated HDMI/DVI", + "Value": "24786" + }, + { + "Key": "Integrated DVI Only", + "Value": "26834" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Select Output Port: ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP3_Port" + ], + "HelpText": "This feature specifies which DVO port the device is configured.", + "WidgetValues": [ + { + "Key": "HDMI-A", + "Value": "0" + }, + { + "Key": "HDMI-B", + "Value": "1" + }, + { + "Key": "HDMI-TC1", + "Value": "14" + }, + { + "Key": "HDMI-TC2", + "Value": "16" + }, + { + "Key": "HDMI-TC3", + "Value": "18" + }, + { + "Key": "HDMI-TC4", + "Value": "20" + }, + { + "Key": "DisplayPort-A", + "Value": "10" + }, + { + "Key": "DisplayPort-B", + "Value": "7" + }, + { + "Key": "DisplayPort-TC1", + "Value": "13" + }, + { + "Key": "DisplayPort-TC2", + "Value": "15" + }, + { + "Key": "DisplayPort-TC3", + "Value": "17" + }, + { + "Key": "DisplayPort-TC4", + "Value": "19" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Select DDC Bus GPIO Pin Pair: ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP3_DDC_Pin" + ], + "HelpText": "This feature specifies the GPIO pin pair used as DDC bus by this device. If this device doesn't support DDC bus, this field will be ignored. \t Pin Pair Value \t\t ADLP PCH mapping\n \t Pin-Pair #1\t\t DDI-A DDC\n \t Pin-Pair #2\t\t DDI-B DDC \n \t Pin-Pair #3\t\t DDI-TC1 DDC \n \t Pin-Pair #4\t\t DDI-TC2 DDC \n \t Pin-Pair #5\t\t DDI-TC3 DDC \n \t Pin-Pair #6\t\t DDI-TC4 DDC \n", + "WidgetValues": [ + { + "Key": "N/A", + "Value": "0" + }, + { + "Key": "Pin-Pair #1", + "Value": "1" + }, + { + "Key": "Pin-Pair #2", + "Value": "2" + }, + { + "Key": "Pin-Pair #3", + "Value": "3" + }, + { + "Key": "Pin-Pair #4", + "Value": "4" + }, + { + "Key": "Pin-Pair #5", + "Value": "5" + }, + { + "Key": "Pin-Pair #6", + "Value": "6" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Select AUX Channel: ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP3_AUX_Channel" + ], + "HelpText": "This feature specifies the AUX Channel for int-DisplayPort. This field is valid only if integrated DP is selected for Device Type.", + "WidgetValues": [ + { + "Key": "N/A", + "Value": "0" + }, + { + "Key": "DisplayPort-A AUX Channel", + "Value": "64" + }, + { + "Key": "DisplayPort-B AUX Channel", + "Value": "16" + }, + { + "Key": "DisplayPort TC1 AUX Channel", + "Value": "96" + }, + { + "Key": "DisplayPort TC2 AUX Channel", + "Value": "112" + }, + { + "Key": "DisplayPort TC3 AUX Channel", + "Value": "128" + }, + { + "Key": "DisplayPort TC4 AUX Channel", + "Value": "144" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Select HDMI level shifter configuration: ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP3_HDMI_LS_Type" + ], + "HelpText": "This feature specifies the Level shifter configuration for HDMI. This field is valid only if HDMI is selected for Device Type.\n\n-------------------------------------------------------------------------------------------------------------\n|\t\t\t|\tCOMBO-PHY\t|\tDKL-PHY\t\t|\n-------------------------------------------------------------------------------------------------------------\n|\tLevel 1\t\t|\t450mV 0.0dB\t|\t400mV 0dB\t\n|\tLevel 2\t\t|\t450mV 3.2dB\t|\t500mV 0dB\t|\n|\tLevel 3\t\t|\t450mV 5.5dB\t|\t650mV 0dB\t|\n|\tLevel 4\t\t|\t650mV 0.0dB\t|\t800mV 0dB\t|\n|\tLevel 5\t\t|\t650mV 2.3dB\t|\t1000mV 0dB\t|\n|\tLevel 6\t\t|\t850mV 0.0dB\t|\tFULL -1.5dB\t|\n|\tLevel 7\t\t|\t600mV 3.0dB\t|\tFULL -1.8dB\t|\n|\tLevel 8\t\t|\t450mV 0.0dB\t|\tFULL -2dB\t|\n|\tLevel 9\t\t|\t450mV 0.0dB\t|\tFULL -2.5dB\t|\n|\tLevel 10\t\t|\t450mV 0.0dB\t|\tFULL -3dB\t|\n", + "WidgetValues": [ + { + "Key": "Level 1", + "Value": "0" + }, + { + "Key": "Level 2", + "Value": "1" + }, + { + "Key": "Level 3", + "Value": "2" + }, + { + "Key": "Level 4", + "Value": "3" + }, + { + "Key": "Level 5", + "Value": "4" + }, + { + "Key": "Level 6", + "Value": "5" + }, + { + "Key": "Level 7", + "Value": "6" + }, + { + "Key": "Level 8", + "Value": "7" + }, + { + "Key": "Level 9", + "Value": "8" + }, + { + "Key": "Level 10", + "Value": "9" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Select HDMI maximum data rate: ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP3_HDMI_Maximum_Data_Rate" + ], + "HelpText": "This feature limits the maximum data rate per lane for HDMI. This field is valid only if HDMI is selected for Device Type. \n\nNote: OEM’s need to configure the maximum data rate as per mother board support.", + "WidgetValues": [ + { + "Key": "6.00 Gbps", + "Value": "0" + }, + { + "Key": "2.97 Gbps", + "Value": "1" + }, + { + "Key": "1.65 Gbps", + "Value": "2" + }, + { + "Key": "5.94 Gbps", + "Value": "3" + }, + { + "Key": "3.40 Gbps", + "Value": "4" + }, + { + "Key": "3.00 Gbps", + "Value": "5" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Select DP max Link Rate: ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP3_DP_Port_Max_LinkRate" + ], + "HelpText": "This feature limits the maximum link rate for DP Port. This field is valid only if DP is selected for Device Type. \n\nHBR3 is the max Link rate supported by ADL-P/M/N. UHBR link rates are supported only by RPL-P. So, choosing a Link rate greater than HBR3 for ADL-P/M/N will automatically force a fallback to HBR3 in GOP and gfx-driver. \n\nNote: OEM’s need to configure the maximum Link rate as per mother board support.", + "WidgetValues": [ + { + "Key": "Default Max Link Rate supported by Plaftform", + "Value": "0" + }, + { + "Key": "LBR (1.62 Gbps)", + "Value": "1" + }, + { + "Key": "HBR (2.7 Gbps)", + "Value": "2" + }, + { + "Key": "HBR2 (5.4 Gbps)", + "Value": "3" + }, + { + "Key": "HBR3 (8.1 Gbps)", + "Value": "4" + }, + { + "Key": "UHBR10 (10 Gbps)", + "Value": "5" + }, + { + "Key": "UHBR13_5 (13.5 Gbps)", + "Value": "6" + }, + { + "Key": "UHBR20 (20 Gbps)", + "Value": "7" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Select DP Port Max Lane Count Supported: ", + "Visibility": "", + "Data": [ + "2", + "EFP3_EDP_DP_Port_Max_LaneCount" + ], + "HelpText": "This feature allows for the selection of the Port Max Lane Count (Port Width) for the EDP/DP link.", + "WidgetValues": [ + { + "Key": "x1", + "Value": "0" + }, + { + "Key": "x2", + "Value": "1" + }, + { + "Key": "x4", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "EDIDless Panel: ", + "Visibility": "", + "Data": [ + "2", + "EFP3_EDIDless_en" + ], + "HelpText": "If the Attached panel is EDIDless select Yes and the supplied DTD takes priority.", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "Button", + "WidgetName": "EDID-less EFP Panel Generic DTD Timings", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "LTTPR(Link-Training Tunable PHY Repeaters) Mode: ", + "Visibility": "", + "Data": [ + "2", + "EFP3_LTTPRNonTransparentMode" + ], + "HelpText": "This option is used to enable or disable the LTTPR Non transparent Mode.", + "WidgetValues": [ + { + "Key": "Non-Transparent Mode", + "Value": "1" + }, + { + "Key": "Transparent Mode", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Max FrlRate Field Status", + "Visibility": "", + "Data": [ + "2", + "EFP3_IsMaxFrlRateFieldValid" + ], + "HelpText": "Indicates if we need to consider the MaxFrlRate field for HDMI2.1\nDisable - Don't consider the MaximumFrlRate for limiting the FrlRates on HDMI2.1 displays\nEnable - MaximumFrlRate given in bits 0 to 3 are used to override Max FRL Rate supported by platform/panel", + "WidgetValues": [ + { + "Key": "Disabled", + "Value": "0" + }, + { + "Key": "Enabled", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Maximum FrlRate ", + "Visibility": "", + "Data": [ + "2", + "EFP3_MaximumFrlRate" + ], + "HelpText": "0000 = FrlRates not supported (HDMI 2.1 is limited to support only TMDS modes)\n0001 = 3 GT/s\n0010 = 6 GT/s\n0011 = 8 GT/s\n0100 = 10 GT/s\n0101 = 12 GT/s", + "WidgetValues": [ + { + "Key": "FrlRates not supported", + "Value": "0" + }, + { + "Key": "3 GT/s", + "Value": "1" + }, + { + "Key": "6 GT/s", + "Value": "2" + }, + { + "Key": "8 GT/s", + "Value": "3" + }, + { + "Key": "10 GT/s", + "Value": "4" + }, + { + "Key": "12 GT/s", + "Value": "5" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "DP to HDMI Pcon: ", + "Visibility": "", + "Data": [ + "2", + "LSPcon3_Options" + ], + "HelpText": "This option is used to enable or disable the OnBoard LSPCON chip.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "DDI Lane Reversal: ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP3_Lane_Reversal" + ], + "HelpText": "This feature, when enabled, will set lane reversal bit for selected Port", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "DP Alt mode over Type C: ", + "Visibility": "", + "Data": [ + "2", + "EFP3_DP_Alt_Mode_OverTypeC_Enabled" + ], + "HelpText": "This option Enables/Disables DP alternate mode over type C ports.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "DP Tunneling over Thunderbolt: ", + "Visibility": "", + "Data": [ + "2", + "EFP3_Thunderbolt_Feature_Enabled" + ], + "HelpText": "This option Enables/Disables DP tunneling over Thunderbolt for selected Port.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Dockable Port: ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP3_Port_Dockable" + ], + "HelpText": "This feature will describe if this Port is Dockable or Not.", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "Label", + "WidgetName": "Select DisplayPort Redriver ", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Vswing PreEmphasis Table Override: ", + "Visibility": "", + "Data": [ + "2", + "INT_EFP3_Vswing_Override_Enable" + ], + "HelpText": "This feature, when enabled, will allow Graphics driver to use the Vswing and Pre-emphasis values from VBT. OEM's must not enable or disable this on their own and work with the Intel CE team to change any settings in this page. When this field is enabled, corresponding table must be populated in the VBT for PHY Vswing parameters too.", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + } + ], + "NestedPages": [ + { + "Type": "Block", + "Block": { + "PageNum": "5-3-3-1", + "PageName": "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Non-dock topology: (OnBoard) ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP3_OnBoard_Redriver_Present" + ], + "HelpText": "This feature will describe if Non-Dock Topology/OnBoard Redriver DP Link is present or Not.", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Pre-Emphasis Level: ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP3_OnBoard_Pre_emphasis" + ], + "HelpText": "This feature allows for the selection of Pre-emphasis level for the OnBoard redriver DP link.\nLevel 0 (0 dB)\nLevel 1 (3.5 dB)\nLevel 2 (6.0 dB)\nLevel 3 (9.5 dB)", + "WidgetValues": [ + { + "Key": "Level-0", + "Value": "0" + }, + { + "Key": "Level-1", + "Value": "1" + }, + { + "Key": "Level-2", + "Value": "2" + }, + { + "Key": "Level-3", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Voltage Swing Level: ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP3_OnBoard_Voltage_swing" + ], + "HelpText": "This feature allows for the selection of voltage swing level for the OnBoard redriver DP link.\nSwing-0 (0.4 V)\nSwing-1 (0.6 V)\nSwing-2 (0.8 V)\nSwing-3 (1.2 V)", + "WidgetValues": [ + { + "Key": "Swing-0", + "Value": "0" + }, + { + "Key": "Swing-1", + "Value": "1" + }, + { + "Key": "Swing-2", + "Value": "2" + }, + { + "Key": "Swing-3", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Dock Topology: (Mobile only) ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP3_Dock_Redriver_Present" + ], + "HelpText": "This feature will describe if Dock Topology/Dock Redriver DP Link is present or not.", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Pre-Emphasis Level: ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP3_Dock_Pre_emphasis" + ], + "HelpText": "This feature allows for the selection of Pre-emphasis level for the Dock redriver DP link.\nLevel 0 (0 dB)\nLevel 1 (3.5 dB)\nLevel 2 (6.0 dB)\nLevel 3 (9.5 dB)", + "WidgetValues": [ + { + "Key": "Level-0", + "Value": "0" + }, + { + "Key": "Level-1", + "Value": "1" + }, + { + "Key": "Level-2", + "Value": "2" + }, + { + "Key": "Level-3", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Voltage Swing Level: ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP3_Dock_Voltage_swing" + ], + "HelpText": "This feature allows for the selection of voltage swing level for the Dock redriver DP link.\nSwing-0 (0.4 V)\nSwing-1 (0.6 V)\nSwing-2 (0.8 V)\nSwing-3 (1.2 V)", + "WidgetValues": [ + { + "Key": "Swing-0", + "Value": "0" + }, + { + "Key": "Swing-1", + "Value": "1" + }, + { + "Key": "Swing-2", + "Value": "2" + }, + { + "Key": "Swing-3", + "Value": "3" + } + ] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-3-3-2", + "PageName": "EDID-less EFP Panel Generic DTD Timings", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Pixel Clock in KHz: ", + "Visibility": "", + "Data": [ + "58", + "EFP_DTD_Pixel_CLK_03" + ], + "HelpText": "Pixel Clock (in KHz) Range from 0.001 to 4294967.295 MP/s.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Active: ", + "Visibility": "", + "Data": [ + "58", + "EFP_DTD_H_Active_03" + ], + "HelpText": "Horizontal Active Image Pixels Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Active: ", + "Visibility": "", + "Data": [ + "58", + "EFP_DTD_V_Active_03" + ], + "HelpText": "Vertical Active Image Lines Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Blank: ", + "Visibility": "", + "Data": [ + "58", + "EFP_DTD_H_Blank_03" + ], + "HelpText": "Horizontal Blank Pixels Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Blank: ", + "Visibility": "", + "Data": [ + "58", + "EFP_DTD_V_Blank_03" + ], + "HelpText": "Vertical Blank lines Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Front Porch: ", + "Visibility": "", + "Data": [ + "58", + "EFP_DTD_H_FrontPorch_03" + ], + "HelpText": "Horizontal Front Porch Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Front Porch: ", + "Visibility": "", + "Data": [ + "58", + "EFP_DTD_V_FrontPorch_03" + ], + "HelpText": "Vertical Front Porch Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Sync: ", + "Visibility": "", + "Data": [ + "58", + "EFP_DTD_H_Sync_03" + ], + "HelpText": "Horizontal Sync Width Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Sync: ", + "Visibility": "", + "Data": [ + "58", + "EFP_DTD_V_Sync_03" + ], + "HelpText": "Vertical Sync Width Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Image Size: ", + "Visibility": "", + "Data": [ + "58", + "EFP_DTD_H_Image_Size_03" + ], + "HelpText": "Horizontal Addressable Video Image Size in mm represented by 16bits. Image size multiplier 1.00 mm precision.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Image Size: ", + "Visibility": "", + "Data": [ + "58", + "EFP_DTD_V_Image_Size_03" + ], + "HelpText": "Vertical Addressable Video Image Size in mm represented by 16bits. Image size multiplier 1.00 mm precision.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryBin", + "WidgetName": "Common Flag: ", + "Visibility": "", + "Data": [ + "58", + "EFP_DTD_Common_Flag_03" + ], + "HelpText": "Common DTD Flags:\nBit 7 : Horizontal Sync Polarity\n1 : Positive\n0 : Negative\nBit 6 : Vertical Sync polarity\n1 : Positive\n0 : Negative\nBit 5 - 0: Reserved (Default value 0)", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + } + ] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-3-4", + "PageName": "Device 4(EFP4) Configuration", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Select Device Type: ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP4_Type" + ], + "HelpText": "This feature specifies the Device Type for this add-in device.\n\nNote:\nDevice Type \"Integrated Display Only Internal to Chassis\" specifies if the display location is internal to the system chasis or not. \nThis Device Class Type should be configured for Port-A and Port-B only.\nIf configured as internal, OEM's must ensure that we also configure this as internal in the FIT tool for CSME FW.\nThe options should be selected as Internal only if the port is used in AIO designs and part of the system chasis. It should be set as External for physically external ports.", + "WidgetValues": [ + { + "Key": "No Device", + "Value": "0" + }, + { + "Key": "Integrated DisplayPort Only", + "Value": "26822" + }, + { + "Key": "Integrated DisplayPort with HDMI/DVI Compatible", + "Value": "24790" + }, + { + "Key": "Integrated DisplayPort with DVI Compatible", + "Value": "26838" + }, + { + "Key": "Integrated Display Only Internal to Chassis", + "Value": "18502" + }, + { + "Key": "Integrated HDMI/DVI", + "Value": "24786" + }, + { + "Key": "Integrated DVI Only", + "Value": "26834" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Select Output Port: ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP4_Port" + ], + "HelpText": "This feature specifies which DVO port the device is configured.", + "WidgetValues": [ + { + "Key": "HDMI-A", + "Value": "0" + }, + { + "Key": "HDMI-B", + "Value": "1" + }, + { + "Key": "HDMI-TC1", + "Value": "14" + }, + { + "Key": "HDMI-TC2", + "Value": "16" + }, + { + "Key": "HDMI-TC3", + "Value": "18" + }, + { + "Key": "HDMI-TC4", + "Value": "20" + }, + { + "Key": "DisplayPort-A", + "Value": "10" + }, + { + "Key": "DisplayPort-B", + "Value": "7" + }, + { + "Key": "DisplayPort-TC1", + "Value": "13" + }, + { + "Key": "DisplayPort-TC2", + "Value": "15" + }, + { + "Key": "DisplayPort-TC3", + "Value": "17" + }, + { + "Key": "DisplayPort-TC4", + "Value": "19" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Select DDC Bus GPIO Pin Pair: ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP4_DDC_Pin" + ], + "HelpText": "This feature specifies the GPIO pin pair used as DDC bus by this device. If this device doesn't support DDC bus, this field will be ignored. \t Pin Pair Value \t\t ADLP PCH mapping\n \t Pin-Pair #1\t\t DDI-A DDC\n \t Pin-Pair #2\t\t DDI-B DDC \n \t Pin-Pair #3\t\t DDI-TC1 DDC \n \t Pin-Pair #4\t\t DDI-TC2 DDC \n \t Pin-Pair #5\t\t DDI-TC3 DDC \n \t Pin-Pair #6\t\t DDI-TC4 DDC \n", + "WidgetValues": [ + { + "Key": "N/A", + "Value": "0" + }, + { + "Key": "Pin-Pair #1", + "Value": "1" + }, + { + "Key": "Pin-Pair #2", + "Value": "2" + }, + { + "Key": "Pin-Pair #3", + "Value": "3" + }, + { + "Key": "Pin-Pair #4", + "Value": "4" + }, + { + "Key": "Pin-Pair #5", + "Value": "5" + }, + { + "Key": "Pin-Pair #6", + "Value": "6" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Select AUX Channel: ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP4_AUX_Channel" + ], + "HelpText": "This feature specifies the AUX Channel for int-DisplayPort. This field is valid only if integrated DP is selected for Device Type.", + "WidgetValues": [ + { + "Key": "N/A", + "Value": "0" + }, + { + "Key": "DisplayPort-A AUX Channel", + "Value": "64" + }, + { + "Key": "DisplayPort-B AUX Channel", + "Value": "16" + }, + { + "Key": "DisplayPort TC1 AUX Channel", + "Value": "96" + }, + { + "Key": "DisplayPort TC2 AUX Channel", + "Value": "112" + }, + { + "Key": "DisplayPort TC3 AUX Channel", + "Value": "128" + }, + { + "Key": "DisplayPort TC4 AUX Channel", + "Value": "144" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Select HDMI level shifter configuration: ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP4_HDMI_LS_Type" + ], + "HelpText": "This feature specifies the Level shifter configuration for HDMI. This field is valid only if HDMI is selected for Device Type.\n\n-------------------------------------------------------------------------------------------------------------\n|\t\t\t|\tCOMBO-PHY\t|\tDKL-PHY\t\t|\n-------------------------------------------------------------------------------------------------------------\n|\tLevel 1\t\t|\t450mV 0.0dB\t|\t400mV 0dB\t\n|\tLevel 2\t\t|\t450mV 3.2dB\t|\t500mV 0dB\t|\n|\tLevel 3\t\t|\t450mV 5.5dB\t|\t650mV 0dB\t|\n|\tLevel 4\t\t|\t650mV 0.0dB\t|\t800mV 0dB\t|\n|\tLevel 5\t\t|\t650mV 2.3dB\t|\t1000mV 0dB\t|\n|\tLevel 6\t\t|\t850mV 0.0dB\t|\tFULL -1.5dB\t|\n|\tLevel 7\t\t|\t600mV 3.0dB\t|\tFULL -1.8dB\t|\n|\tLevel 8\t\t|\t450mV 0.0dB\t|\tFULL -2dB\t|\n|\tLevel 9\t\t|\t450mV 0.0dB\t|\tFULL -2.5dB\t|\n|\tLevel 10\t\t|\t450mV 0.0dB\t|\tFULL -3dB\t|\n", + "WidgetValues": [ + { + "Key": "Level 1", + "Value": "0" + }, + { + "Key": "Level 2", + "Value": "1" + }, + { + "Key": "Level 3", + "Value": "2" + }, + { + "Key": "Level 4", + "Value": "3" + }, + { + "Key": "Level 5", + "Value": "4" + }, + { + "Key": "Level 6", + "Value": "5" + }, + { + "Key": "Level 7", + "Value": "6" + }, + { + "Key": "Level 8", + "Value": "7" + }, + { + "Key": "Level 9", + "Value": "8" + }, + { + "Key": "Level 10", + "Value": "9" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Select HDMI maximum data rate: ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP4_HDMI_Maximum_Data_Rate" + ], + "HelpText": "This feature limits the maximum data rate per lane for HDMI. This field is valid only if HDMI is selected for Device Type. \n\nNote: OEM’s need to configure the maximum data rate as per mother board support.", + "WidgetValues": [ + { + "Key": "6.00 Gbps", + "Value": "0" + }, + { + "Key": "2.97 Gbps", + "Value": "1" + }, + { + "Key": "1.65 Gbps", + "Value": "2" + }, + { + "Key": "5.94 Gbps", + "Value": "3" + }, + { + "Key": "3.40 Gbps", + "Value": "4" + }, + { + "Key": "3.00 Gbps", + "Value": "5" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Select DP max Link Rate: ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP4_DP_Port_Max_LinkRate" + ], + "HelpText": "This feature limits the maximum link rate for DP Port. This field is valid only if DP is selected for Device Type. \n\nHBR3 is the max Link rate supported by ADL-P/M/N. UHBR link rates are supported only by RPL-P. So, choosing a Link rate greater than HBR3 for ADL-P/M/N will automatically force a fallback to HBR3 in GOP and gfx-driver. \n\nNote: OEM’s need to configure the maximum Link rate as per mother board support.", + "WidgetValues": [ + { + "Key": "Default Max Link Rate supported by Plaftform", + "Value": "0" + }, + { + "Key": "LBR (1.62 Gbps)", + "Value": "1" + }, + { + "Key": "HBR (2.7 Gbps)", + "Value": "2" + }, + { + "Key": "HBR2 (5.4 Gbps)", + "Value": "3" + }, + { + "Key": "HBR3 (8.1 Gbps)", + "Value": "4" + }, + { + "Key": "UHBR10 (10 Gbps)", + "Value": "5" + }, + { + "Key": "UHBR13_5 (13.5 Gbps)", + "Value": "6" + }, + { + "Key": "UHBR20 (20 Gbps)", + "Value": "7" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Select DP Port Max Lane Count Supported: ", + "Visibility": "", + "Data": [ + "2", + "EFP4_EDP_DP_Port_Max_LaneCount" + ], + "HelpText": "This feature allows for the selection of the Port Max Lane Count (Port Width) for the EDP/DP link.", + "WidgetValues": [ + { + "Key": "x1", + "Value": "0" + }, + { + "Key": "x2", + "Value": "1" + }, + { + "Key": "x4", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "EDIDless Panel: ", + "Visibility": "", + "Data": [ + "2", + "EFP4_EDIDless_en" + ], + "HelpText": "If the Attached panel is EDIDless select Yes and the supplied DTD takes priority.", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "Button", + "WidgetName": "EDID-less EFP Panel Generic DTD Timings", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "LTTPR(Link-Training Tunable PHY Repeaters) Mode: ", + "Visibility": "", + "Data": [ + "2", + "EFP4_LTTPRNonTransparentMode" + ], + "HelpText": "This option is used to enable or disable the LTTPR Non transparent Mode.", + "WidgetValues": [ + { + "Key": "Non-Transparent Mode", + "Value": "1" + }, + { + "Key": "Transparent Mode", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Max FrlRate Field Status", + "Visibility": "", + "Data": [ + "2", + "EFP4_IsMaxFrlRateFieldValid" + ], + "HelpText": "Indicates if we need to consider the MaxFrlRate field for HDMI2.1\nDisable - Don't consider the MaximumFrlRate for limiting the FrlRates on HDMI2.1 displays\nEnable - MaximumFrlRate given in bits 0 to 3 are used to override Max FRL Rate supported by platform/panel", + "WidgetValues": [ + { + "Key": "Disabled", + "Value": "0" + }, + { + "Key": "Enabled", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Maximum FrlRate ", + "Visibility": "", + "Data": [ + "2", + "EFP4_MaximumFrlRate" + ], + "HelpText": "0000 = FrlRates not supported (HDMI 2.1 is limited to support only TMDS modes)\n0001 = 3 GT/s\n0010 = 6 GT/s\n0011 = 8 GT/s\n0100 = 10 GT/s\n0101 = 12 GT/s", + "WidgetValues": [ + { + "Key": "FrlRates not supported", + "Value": "0" + }, + { + "Key": "3 GT/s", + "Value": "1" + }, + { + "Key": "6 GT/s", + "Value": "2" + }, + { + "Key": "8 GT/s", + "Value": "3" + }, + { + "Key": "10 GT/s", + "Value": "4" + }, + { + "Key": "12 GT/s", + "Value": "5" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "DP to HDMI Pcon: ", + "Visibility": "", + "Data": [ + "2", + "LSPcon4_Options" + ], + "HelpText": "This option is used to enable or disable the OnBoard LSPCON chip.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "DDI Lane Reversal: ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP4_Lane_Reversal" + ], + "HelpText": "This feature, when enabled, will set lane reversal bit for selected Port", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "DP Alt mode over Type C: ", + "Visibility": "", + "Data": [ + "2", + "EFP4_DP_Alt_Mode_OverTypeC_Enabled" + ], + "HelpText": "This option Enables/Disables DP alternate mode over type C ports.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "DP Tunneling over Thunderbolt: ", + "Visibility": "", + "Data": [ + "2", + "EFP4_Thunderbolt_Feature_Enabled" + ], + "HelpText": "This option Enables/Disables DP tunneling over Thunderbolt for selected Port.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Dockable Port: ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP4_Port_Dockable" + ], + "HelpText": "This feature will describe if this Port is Dockable or Not.", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "Label", + "WidgetName": "Select DisplayPort Redriver ", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Vswing PreEmphasis Table Override: ", + "Visibility": "", + "Data": [ + "2", + "INT_EFP4_Vswing_Override_Enable" + ], + "HelpText": "This feature, when enabled, will allow Graphics driver to use the Vswing and Pre-emphasis values from VBT. OEM's must not enable or disable this on their own and work with the Intel CE team to change any settings in this page. When this field is enabled, corresponding table must be populated in the VBT for PHY Vswing parameters too.", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + } + ], + "NestedPages": [ + { + "Type": "Block", + "Block": { + "PageNum": "5-3-4-1", + "PageName": "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Non-dock topology: (OnBoard) ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP4_OnBoard_Redriver_Present" + ], + "HelpText": "This feature will describe if Non-Dock Topology/OnBoard Redriver DP Link is present or Not.", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Pre-Emphasis Level: ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP4_OnBoard_Pre_emphasis" + ], + "HelpText": "This feature allows for the selection of Pre-emphasis level for the OnBoard redriver DP link.\nLevel 0 (0 dB)\nLevel 1 (3.5 dB)\nLevel 2 (6.0 dB)\nLevel 3 (9.5 dB)", + "WidgetValues": [ + { + "Key": "Level-0", + "Value": "0" + }, + { + "Key": "Level-1", + "Value": "1" + }, + { + "Key": "Level-2", + "Value": "2" + }, + { + "Key": "Level-3", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Voltage Swing Level: ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP4_OnBoard_Voltage_swing" + ], + "HelpText": "This feature allows for the selection of voltage swing level for the OnBoard redriver DP link.\nSwing-0 (0.4 V)\nSwing-1 (0.6 V)\nSwing-2 (0.8 V)\nSwing-3 (1.2 V)", + "WidgetValues": [ + { + "Key": "Swing-0", + "Value": "0" + }, + { + "Key": "Swing-1", + "Value": "1" + }, + { + "Key": "Swing-2", + "Value": "2" + }, + { + "Key": "Swing-3", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Dock Topology: (Mobile only) ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP4_Dock_Redriver_Present" + ], + "HelpText": "This feature will describe if Dock Topology/Dock Redriver DP Link is present or not.", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Pre-Emphasis Level: ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP4_Dock_Pre_emphasis" + ], + "HelpText": "This feature allows for the selection of Pre-emphasis level for the Dock redriver DP link.\nLevel 0 (0 dB)\nLevel 1 (3.5 dB)\nLevel 2 (6.0 dB)\nLevel 3 (9.5 dB)", + "WidgetValues": [ + { + "Key": "Level-0", + "Value": "0" + }, + { + "Key": "Level-1", + "Value": "1" + }, + { + "Key": "Level-2", + "Value": "2" + }, + { + "Key": "Level-3", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Voltage Swing Level: ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP4_Dock_Voltage_swing" + ], + "HelpText": "This feature allows for the selection of voltage swing level for the Dock redriver DP link.\nSwing-0 (0.4 V)\nSwing-1 (0.6 V)\nSwing-2 (0.8 V)\nSwing-3 (1.2 V)", + "WidgetValues": [ + { + "Key": "Swing-0", + "Value": "0" + }, + { + "Key": "Swing-1", + "Value": "1" + }, + { + "Key": "Swing-2", + "Value": "2" + }, + { + "Key": "Swing-3", + "Value": "3" + } + ] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-3-4-2", + "PageName": "EDID-less EFP Panel Generic DTD Timings", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Pixel Clock in KHz: ", + "Visibility": "", + "Data": [ + "58", + "EFP_DTD_Pixel_CLK_04" + ], + "HelpText": "Pixel Clock (in KHz) Range from 0.001 to 4294967.295 MP/s.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Active: ", + "Visibility": "", + "Data": [ + "58", + "EFP_DTD_H_Active_04" + ], + "HelpText": "Horizontal Active Image Pixels Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Active: ", + "Visibility": "", + "Data": [ + "58", + "EFP_DTD_V_Active_04" + ], + "HelpText": "Vertical Active Image Lines Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Blank: ", + "Visibility": "", + "Data": [ + "58", + "EFP_DTD_H_Blank_04" + ], + "HelpText": "Horizontal Blank Pixels Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Blank: ", + "Visibility": "", + "Data": [ + "58", + "EFP_DTD_V_Blank_04" + ], + "HelpText": "Vertical Blank lines Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Front Porch: ", + "Visibility": "", + "Data": [ + "58", + "EFP_DTD_H_FrontPorch_04" + ], + "HelpText": "Horizontal Front Porch Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Front Porch: ", + "Visibility": "", + "Data": [ + "58", + "EFP_DTD_V_FrontPorch_04" + ], + "HelpText": "Vertical Front Porch Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Sync: ", + "Visibility": "", + "Data": [ + "58", + "EFP_DTD_H_Sync_04" + ], + "HelpText": "Horizontal Sync Width Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Sync: ", + "Visibility": "", + "Data": [ + "58", + "EFP_DTD_V_Sync_04" + ], + "HelpText": "Vertical Sync Width Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Image Size: ", + "Visibility": "", + "Data": [ + "58", + "EFP_DTD_H_Image_Size_04" + ], + "HelpText": "Horizontal Addressable Video Image Size in mm represented by 16bits. Image size multiplier 1.00 mm precision.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Image Size: ", + "Visibility": "", + "Data": [ + "58", + "EFP_DTD_V_Image_Size_04" + ], + "HelpText": "Vertical Addressable Video Image Size in mm represented by 16bits. Image size multiplier 1.00 mm precision.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryBin", + "WidgetName": "Common Flag: ", + "Visibility": "", + "Data": [ + "58", + "EFP_DTD_Common_Flag_04" + ], + "HelpText": "Common DTD Flags:\nBit 7 : Horizontal Sync Polarity\n1 : Positive\n0 : Negative\nBit 6 : Vertical Sync polarity\n1 : Positive\n0 : Negative\nBit 5 - 0: Reserved (Default value 0)", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + } + ] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-3-5", + "PageName": "Device 5(EFP5) Configuration", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Select Device Type: ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP5_Type" + ], + "HelpText": "This feature specifies the Device Type for this add-in device.\n\nNote:\nDevice Type \"Integrated Display Only Internal to Chassis\" specifies if the display location is internal to the system chasis or not. \nThis Device Class Type should be configured for Port-A and Port-B only.\nIf configured as internal, OEM's must ensure that we also configure this as internal in the FIT tool for CSME FW.\nThe options should be selected as Internal only if the port is used in AIO designs and part of the system chasis. It should be set as External for physically external ports.", + "WidgetValues": [ + { + "Key": "No Device", + "Value": "0" + }, + { + "Key": "Integrated DisplayPort Only", + "Value": "26822" + }, + { + "Key": "Integrated DisplayPort with HDMI/DVI Compatible", + "Value": "24790" + }, + { + "Key": "Integrated DisplayPort with DVI Compatible", + "Value": "26838" + }, + { + "Key": "Integrated Display Only Internal to Chassis", + "Value": "18502" + }, + { + "Key": "Integrated HDMI/DVI", + "Value": "24786" + }, + { + "Key": "Integrated DVI Only", + "Value": "26834" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Select Output Port: ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP5_Port" + ], + "HelpText": "This feature specifies which DVO port the device is configured.", + "WidgetValues": [ + { + "Key": "HDMI-A", + "Value": "0" + }, + { + "Key": "HDMI-B", + "Value": "1" + }, + { + "Key": "HDMI-TC1", + "Value": "14" + }, + { + "Key": "HDMI-TC2", + "Value": "16" + }, + { + "Key": "HDMI-TC3", + "Value": "18" + }, + { + "Key": "HDMI-TC4", + "Value": "20" + }, + { + "Key": "DisplayPort-A", + "Value": "10" + }, + { + "Key": "DisplayPort-B", + "Value": "7" + }, + { + "Key": "DisplayPort-TC1", + "Value": "13" + }, + { + "Key": "DisplayPort-TC2", + "Value": "15" + }, + { + "Key": "DisplayPort-TC3", + "Value": "17" + }, + { + "Key": "DisplayPort-TC4", + "Value": "19" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Select DDC Bus GPIO Pin Pair: ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP5_DDC_Pin" + ], + "HelpText": "This feature specifies the GPIO pin pair used as DDC bus by this device. If this device doesn't support DDC bus, this field will be ignored. \t Pin Pair Value \t\t ADLP PCH mapping\n \t Pin-Pair #1\t\t DDI-A DDC\n \t Pin-Pair #2\t\t DDI-B DDC \n \t Pin-Pair #3\t\t DDI-TC1 DDC \n \t Pin-Pair #4\t\t DDI-TC2 DDC \n \t Pin-Pair #5\t\t DDI-TC3 DDC \n \t Pin-Pair #6\t\t DDI-TC4 DDC \n", + "WidgetValues": [ + { + "Key": "N/A", + "Value": "0" + }, + { + "Key": "Pin-Pair #1", + "Value": "1" + }, + { + "Key": "Pin-Pair #2", + "Value": "2" + }, + { + "Key": "Pin-Pair #3", + "Value": "3" + }, + { + "Key": "Pin-Pair #4", + "Value": "4" + }, + { + "Key": "Pin-Pair #5", + "Value": "5" + }, + { + "Key": "Pin-Pair #6", + "Value": "6" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Select AUX Channel: ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP5_AUX_Channel" + ], + "HelpText": "This feature specifies the AUX Channel for int-DisplayPort. This field is valid only if integrated DP is selected for Device Type.", + "WidgetValues": [ + { + "Key": "N/A", + "Value": "0" + }, + { + "Key": "DisplayPort-A AUX Channel", + "Value": "64" + }, + { + "Key": "DisplayPort-B AUX Channel", + "Value": "16" + }, + { + "Key": "DisplayPort TC1 AUX Channel", + "Value": "96" + }, + { + "Key": "DisplayPort TC2 AUX Channel", + "Value": "112" + }, + { + "Key": "DisplayPort TC3 AUX Channel", + "Value": "128" + }, + { + "Key": "DisplayPort TC4 AUX Channel", + "Value": "144" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Select HDMI level shifter configuration: ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP5_HDMI_LS_Type" + ], + "HelpText": "This feature specifies the Level shifter configuration for HDMI. This field is valid only if HDMI is selected for Device Type.\n\n-------------------------------------------------------------------------------------------------------------\n|\t\t\t|\tCOMBO-PHY\t|\tDKL-PHY\t\t|\n-------------------------------------------------------------------------------------------------------------\n|\tLevel 1\t\t|\t450mV 0.0dB\t|\t400mV 0dB\t\n|\tLevel 2\t\t|\t450mV 3.2dB\t|\t500mV 0dB\t|\n|\tLevel 3\t\t|\t450mV 5.5dB\t|\t650mV 0dB\t|\n|\tLevel 4\t\t|\t650mV 0.0dB\t|\t800mV 0dB\t|\n|\tLevel 5\t\t|\t650mV 2.3dB\t|\t1000mV 0dB\t|\n|\tLevel 6\t\t|\t850mV 0.0dB\t|\tFULL -1.5dB\t|\n|\tLevel 7\t\t|\t600mV 3.0dB\t|\tFULL -1.8dB\t|\n|\tLevel 8\t\t|\t450mV 0.0dB\t|\tFULL -2dB\t|\n|\tLevel 9\t\t|\t450mV 0.0dB\t|\tFULL -2.5dB\t|\n|\tLevel 10\t\t|\t450mV 0.0dB\t|\tFULL -3dB\t|\n", + "WidgetValues": [ + { + "Key": "Level 1", + "Value": "0" + }, + { + "Key": "Level 2", + "Value": "1" + }, + { + "Key": "Level 3", + "Value": "2" + }, + { + "Key": "Level 4", + "Value": "3" + }, + { + "Key": "Level 5", + "Value": "4" + }, + { + "Key": "Level 6", + "Value": "5" + }, + { + "Key": "Level 7", + "Value": "6" + }, + { + "Key": "Level 8", + "Value": "7" + }, + { + "Key": "Level 9", + "Value": "8" + }, + { + "Key": "Level 10", + "Value": "9" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Select HDMI maximum data rate: ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP5_HDMI_Maximum_Data_Rate" + ], + "HelpText": "This feature limits the maximum data rate per lane for HDMI. This field is valid only if HDMI is selected for Device Type. \n\nNote: OEM’s need to configure the maximum data rate as per mother board support.", + "WidgetValues": [ + { + "Key": "6.00 Gbps", + "Value": "0" + }, + { + "Key": "2.97 Gbps", + "Value": "1" + }, + { + "Key": "1.65 Gbps", + "Value": "2" + }, + { + "Key": "5.94 Gbps", + "Value": "3" + }, + { + "Key": "3.40 Gbps", + "Value": "4" + }, + { + "Key": "3.00 Gbps", + "Value": "5" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Select DP max Link Rate: ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP5_DP_Port_Max_LinkRate" + ], + "HelpText": "This feature limits the maximum link rate for DP Port. This field is valid only if DP is selected for Device Type. \n\nHBR3 is the max Link rate supported by ADL-P/M/N. UHBR link rates are supported only by RPL-P. So, choosing a Link rate greater than HBR3 for ADL-P/M/N will automatically force a fallback to HBR3 in GOP and gfx-driver. \n\nNote: OEM’s need to configure the maximum Link rate as per mother board support.", + "WidgetValues": [ + { + "Key": "Default Max Link Rate supported by Plaftform", + "Value": "0" + }, + { + "Key": "LBR (1.62 Gbps)", + "Value": "1" + }, + { + "Key": "HBR (2.7 Gbps)", + "Value": "2" + }, + { + "Key": "HBR2 (5.4 Gbps)", + "Value": "3" + }, + { + "Key": "HBR3 (8.1 Gbps)", + "Value": "4" + }, + { + "Key": "UHBR10 (10 Gbps)", + "Value": "5" + }, + { + "Key": "UHBR13_5 (13.5 Gbps)", + "Value": "6" + }, + { + "Key": "UHBR20 (20 Gbps)", + "Value": "7" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Select DP Port Max Lane Count Supported: ", + "Visibility": "", + "Data": [ + "2", + "EFP5_EDP_DP_Port_Max_LaneCount" + ], + "HelpText": "This feature allows for the selection of the Port Max Lane Count (Port Width) for the EDP/DP link.", + "WidgetValues": [ + { + "Key": "x1", + "Value": "0" + }, + { + "Key": "x2", + "Value": "1" + }, + { + "Key": "x4", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "EDIDless Panel: ", + "Visibility": "", + "Data": [ + "2", + "EFP5_EDIDless_en" + ], + "HelpText": "If the Attached panel is EDIDless select Yes and the supplied DTD takes priority.", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "Button", + "WidgetName": "EDID-less EFP Panel Generic DTD Timings", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "LTTPR(Link-Training Tunable PHY Repeaters) Mode: ", + "Visibility": "", + "Data": [ + "2", + "EFP5_LTTPRNonTransparentMode" + ], + "HelpText": "This option is used to enable or disable the LTTPR Non transparent Mode.", + "WidgetValues": [ + { + "Key": "Non-Transparent Mode", + "Value": "1" + }, + { + "Key": "Transparent Mode", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Max FrlRate Field Status", + "Visibility": "", + "Data": [ + "2", + "EFP5_IsMaxFrlRateFieldValid" + ], + "HelpText": "Indicates if we need to consider the MaxFrlRate field for HDMI2.1\nDisable - Don't consider the MaximumFrlRate for limiting the FrlRates on HDMI2.1 displays\nEnable - MaximumFrlRate given in bits 0 to 3 are used to override Max FRL Rate supported by platform/panel", + "WidgetValues": [ + { + "Key": "Disabled", + "Value": "0" + }, + { + "Key": "Enabled", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Maximum FrlRate ", + "Visibility": "", + "Data": [ + "2", + "EFP5_MaximumFrlRate" + ], + "HelpText": "0000 = FrlRates not supported (HDMI 2.1 is limited to support only TMDS modes)\n0001 = 3 GT/s\n0010 = 6 GT/s\n0011 = 8 GT/s\n0100 = 10 GT/s\n0101 = 12 GT/s", + "WidgetValues": [ + { + "Key": "FrlRates not supported", + "Value": "0" + }, + { + "Key": "3 GT/s", + "Value": "1" + }, + { + "Key": "6 GT/s", + "Value": "2" + }, + { + "Key": "8 GT/s", + "Value": "3" + }, + { + "Key": "10 GT/s", + "Value": "4" + }, + { + "Key": "12 GT/s", + "Value": "5" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "DP to HDMI Pcon: ", + "Visibility": "", + "Data": [ + "2", + "LSPcon5_Options" + ], + "HelpText": "This option is used to enable or disable the OnBoard LSPCON chip.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "DDI Lane Reversal: ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP5_Lane_Reversal" + ], + "HelpText": "This feature, when enabled, will set lane reversal bit for selected Port", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "DP Alt mode over Type C: ", + "Visibility": "", + "Data": [ + "2", + "EFP5_DP_Alt_Mode_OverTypeC_Enabled" + ], + "HelpText": "This option Enables/Disables DP alternate mode over type C ports.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "DP Tunneling over Thunderbolt: ", + "Visibility": "", + "Data": [ + "2", + "EFP5_Thunderbolt_Feature_Enabled" + ], + "HelpText": "This option Enables/Disables DP tunneling over Thunderbolt for selected Port.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Dockable Port: ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP5_Port_Dockable" + ], + "HelpText": "This feature will describe if this Port is Dockable or Not.", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "Label", + "WidgetName": "Select DisplayPort Redriver ", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Vswing PreEmphasis Table Override: ", + "Visibility": "", + "Data": [ + "2", + "INT_EFP5_Vswing_Override_Enable" + ], + "HelpText": "This feature, when enabled, will allow Graphics driver to use the Vswing and Pre-emphasis values from VBT. OEM's must not enable or disable this on their own and work with the Intel CE team to change any settings in this page. When this field is enabled, corresponding table must be populated in the VBT for PHY Vswing parameters too.", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + } + ], + "NestedPages": [ + { + "Type": "Block", + "Block": { + "PageNum": "5-3-5-1", + "PageName": "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Non-dock topology: (OnBoard) ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP5_OnBoard_Redriver_Present" + ], + "HelpText": "This feature will describe if Non-Dock Topology/OnBoard Redriver DP Link is present or Not.", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Pre-Emphasis Level: ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP5_OnBoard_Pre_emphasis" + ], + "HelpText": "This feature allows for the selection of Pre-emphasis level for the OnBoard redriver DP link.\nLevel 0 (0 dB)\nLevel 1 (3.5 dB)\nLevel 2 (6.0 dB)\nLevel 3 (9.5 dB)", + "WidgetValues": [ + { + "Key": "Level-0", + "Value": "0" + }, + { + "Key": "Level-1", + "Value": "1" + }, + { + "Key": "Level-2", + "Value": "2" + }, + { + "Key": "Level-3", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Voltage Swing Level: ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP5_OnBoard_Voltage_swing" + ], + "HelpText": "This feature allows for the selection of voltage swing level for the OnBoard redriver DP link.\nSwing-0 (0.4 V)\nSwing-1 (0.6 V)\nSwing-2 (0.8 V)\nSwing-3 (1.2 V)", + "WidgetValues": [ + { + "Key": "Swing-0", + "Value": "0" + }, + { + "Key": "Swing-1", + "Value": "1" + }, + { + "Key": "Swing-2", + "Value": "2" + }, + { + "Key": "Swing-3", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Dock Topology: (Mobile only) ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP5_Dock_Redriver_Present" + ], + "HelpText": "This feature will describe if Dock Topology/Dock Redriver DP Link is present or not.", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Pre-Emphasis Level: ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP5_Dock_Pre_emphasis" + ], + "HelpText": "This feature allows for the selection of Pre-emphasis level for the Dock redriver DP link.\nLevel 0 (0 dB)\nLevel 1 (3.5 dB)\nLevel 2 (6.0 dB)\nLevel 3 (9.5 dB)", + "WidgetValues": [ + { + "Key": "Level-0", + "Value": "0" + }, + { + "Key": "Level-1", + "Value": "1" + }, + { + "Key": "Level-2", + "Value": "2" + }, + { + "Key": "Level-3", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Voltage Swing Level: ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP5_Dock_Voltage_swing" + ], + "HelpText": "This feature allows for the selection of voltage swing level for the Dock redriver DP link.\nSwing-0 (0.4 V)\nSwing-1 (0.6 V)\nSwing-2 (0.8 V)\nSwing-3 (1.2 V)", + "WidgetValues": [ + { + "Key": "Swing-0", + "Value": "0" + }, + { + "Key": "Swing-1", + "Value": "1" + }, + { + "Key": "Swing-2", + "Value": "2" + }, + { + "Key": "Swing-3", + "Value": "3" + } + ] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-3-5-2", + "PageName": "EDID-less EFP Panel Generic DTD Timings", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Pixel Clock in KHz: ", + "Visibility": "", + "Data": [ + "58", + "EFP_DTD_Pixel_CLK_05" + ], + "HelpText": "Pixel Clock (in KHz) Range from 0.001 to 4294967.295 MP/s.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Active: ", + "Visibility": "", + "Data": [ + "58", + "EFP_DTD_H_Active_05" + ], + "HelpText": "Horizontal Active Image Pixels Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Active: ", + "Visibility": "", + "Data": [ + "58", + "EFP_DTD_V_Active_05" + ], + "HelpText": "Vertical Active Image Lines Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Blank: ", + "Visibility": "", + "Data": [ + "58", + "EFP_DTD_H_Blank_05" + ], + "HelpText": "Horizontal Blank Pixels Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Blank: ", + "Visibility": "", + "Data": [ + "58", + "EFP_DTD_V_Blank_05" + ], + "HelpText": "Vertical Blank lines Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Front Porch: ", + "Visibility": "", + "Data": [ + "58", + "EFP_DTD_H_FrontPorch_05" + ], + "HelpText": "Horizontal Front Porch Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Front Porch: ", + "Visibility": "", + "Data": [ + "58", + "EFP_DTD_V_FrontPorch_05" + ], + "HelpText": "Vertical Front Porch Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Sync: ", + "Visibility": "", + "Data": [ + "58", + "EFP_DTD_H_Sync_05" + ], + "HelpText": "Horizontal Sync Width Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Sync: ", + "Visibility": "", + "Data": [ + "58", + "EFP_DTD_V_Sync_05" + ], + "HelpText": "Vertical Sync Width Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Image Size: ", + "Visibility": "", + "Data": [ + "58", + "EFP_DTD_H_Image_Size_05" + ], + "HelpText": "Horizontal Addressable Video Image Size in mm represented by 16bits. Image size multiplier 1.00 mm precision.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Image Size: ", + "Visibility": "", + "Data": [ + "58", + "EFP_DTD_V_Image_Size_05" + ], + "HelpText": "Vertical Addressable Video Image Size in mm represented by 16bits. Image size multiplier 1.00 mm precision.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryBin", + "WidgetName": "Common Flag: ", + "Visibility": "", + "Data": [ + "58", + "EFP_DTD_Common_Flag_05" + ], + "HelpText": "Common DTD Flags:\nBit 7 : Horizontal Sync Polarity\n1 : Positive\n0 : Negative\nBit 6 : Vertical Sync polarity\n1 : Positive\n0 : Negative\nBit 5 - 0: Reserved (Default value 0)", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + } + ] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-3-6", + "PageName": "Device 6(EFP6) Configuration", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Select Device Type: ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP6_Type" + ], + "HelpText": "This feature specifies the Device Type for this add-in device.\n\nNote:\nDevice Type \"Integrated Display Only Internal to Chassis\" specifies if the display location is internal to the system chasis or not. \nThis Device Class Type should be configured for Port-A and Port-B only.\nIf configured as internal, OEM's must ensure that we also configure this as internal in the FIT tool for CSME FW.\nThe options should be selected as Internal only if the port is used in AIO designs and part of the system chasis. It should be set as External for physically external ports.", + "WidgetValues": [ + { + "Key": "No Device", + "Value": "0" + }, + { + "Key": "Integrated DisplayPort Only", + "Value": "26822" + }, + { + "Key": "Integrated DisplayPort with HDMI/DVI Compatible", + "Value": "24790" + }, + { + "Key": "Integrated DisplayPort with DVI Compatible", + "Value": "26838" + }, + { + "Key": "Integrated Display Only Internal to Chassis", + "Value": "18502" + }, + { + "Key": "Integrated HDMI/DVI", + "Value": "24786" + }, + { + "Key": "Integrated DVI Only", + "Value": "26834" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Select Output Port: ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP6_Port" + ], + "HelpText": "This feature specifies which DVO port the device is configured.", + "WidgetValues": [ + { + "Key": "HDMI-A", + "Value": "0" + }, + { + "Key": "HDMI-B", + "Value": "1" + }, + { + "Key": "HDMI-TC1", + "Value": "14" + }, + { + "Key": "HDMI-TC2", + "Value": "16" + }, + { + "Key": "HDMI-TC3", + "Value": "18" + }, + { + "Key": "HDMI-TC4", + "Value": "20" + }, + { + "Key": "DisplayPort-A", + "Value": "10" + }, + { + "Key": "DisplayPort-B", + "Value": "7" + }, + { + "Key": "DisplayPort-TC1", + "Value": "13" + }, + { + "Key": "DisplayPort-TC2", + "Value": "15" + }, + { + "Key": "DisplayPort-TC3", + "Value": "17" + }, + { + "Key": "DisplayPort-TC4", + "Value": "19" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Select DDC Bus GPIO Pin Pair: ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP6_DDC_Pin" + ], + "HelpText": "This feature specifies the GPIO pin pair used as DDC bus by this device. If this device doesn't support DDC bus, this field will be ignored. \t Pin Pair Value \t\t ADLP PCH mapping\n \t Pin-Pair #1\t\t DDI-A DDC\n \t Pin-Pair #2\t\t DDI-B DDC \n \t Pin-Pair #3\t\t DDI-TC1 DDC \n \t Pin-Pair #4\t\t DDI-TC2 DDC \n \t Pin-Pair #5\t\t DDI-TC3 DDC \n \t Pin-Pair #6\t\t DDI-TC4 DDC \n", + "WidgetValues": [ + { + "Key": "N/A", + "Value": "0" + }, + { + "Key": "Pin-Pair #1", + "Value": "1" + }, + { + "Key": "Pin-Pair #2", + "Value": "2" + }, + { + "Key": "Pin-Pair #3", + "Value": "3" + }, + { + "Key": "Pin-Pair #4", + "Value": "4" + }, + { + "Key": "Pin-Pair #5", + "Value": "5" + }, + { + "Key": "Pin-Pair #6", + "Value": "6" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Select AUX Channel: ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP6_AUX_Channel" + ], + "HelpText": "This feature specifies the AUX Channel for int-DisplayPort. This field is valid only if integrated DP is selected for Device Type.", + "WidgetValues": [ + { + "Key": "N/A", + "Value": "0" + }, + { + "Key": "DisplayPort-A AUX Channel", + "Value": "64" + }, + { + "Key": "DisplayPort-B AUX Channel", + "Value": "16" + }, + { + "Key": "DisplayPort TC1 AUX Channel", + "Value": "96" + }, + { + "Key": "DisplayPort TC2 AUX Channel", + "Value": "112" + }, + { + "Key": "DisplayPort TC3 AUX Channel", + "Value": "128" + }, + { + "Key": "DisplayPort TC4 AUX Channel", + "Value": "144" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Select HDMI level shifter configuration: ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP6_HDMI_LS_Type" + ], + "HelpText": "This feature specifies the Level shifter configuration for HDMI. This field is valid only if HDMI is selected for Device Type.\n\n-------------------------------------------------------------------------------------------------------------\n|\t\t\t|\tCOMBO-PHY\t|\tDKL-PHY\t\t|\n-------------------------------------------------------------------------------------------------------------\n|\tLevel 1\t\t|\t450mV 0.0dB\t|\t400mV 0dB\t\n|\tLevel 2\t\t|\t450mV 3.2dB\t|\t500mV 0dB\t|\n|\tLevel 3\t\t|\t450mV 5.5dB\t|\t650mV 0dB\t|\n|\tLevel 4\t\t|\t650mV 0.0dB\t|\t800mV 0dB\t|\n|\tLevel 5\t\t|\t650mV 2.3dB\t|\t1000mV 0dB\t|\n|\tLevel 6\t\t|\t850mV 0.0dB\t|\tFULL -1.5dB\t|\n|\tLevel 7\t\t|\t600mV 3.0dB\t|\tFULL -1.8dB\t|\n|\tLevel 8\t\t|\t450mV 0.0dB\t|\tFULL -2dB\t|\n|\tLevel 9\t\t|\t450mV 0.0dB\t|\tFULL -2.5dB\t|\n|\tLevel 10\t\t|\t450mV 0.0dB\t|\tFULL -3dB\t|\n", + "WidgetValues": [ + { + "Key": "Level 1", + "Value": "0" + }, + { + "Key": "Level 2", + "Value": "1" + }, + { + "Key": "Level 3", + "Value": "2" + }, + { + "Key": "Level 4", + "Value": "3" + }, + { + "Key": "Level 5", + "Value": "4" + }, + { + "Key": "Level 6", + "Value": "5" + }, + { + "Key": "Level 7", + "Value": "6" + }, + { + "Key": "Level 8", + "Value": "7" + }, + { + "Key": "Level 9", + "Value": "8" + }, + { + "Key": "Level 10", + "Value": "9" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Select HDMI maximum data rate: ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP6_HDMI_Maximum_Data_Rate" + ], + "HelpText": "This feature limits the maximum data rate per lane for HDMI. This field is valid only if HDMI is selected for Device Type. \n\nNote: OEM’s need to configure the maximum data rate as per mother board support.", + "WidgetValues": [ + { + "Key": "6.00 Gbps", + "Value": "0" + }, + { + "Key": "2.97 Gbps", + "Value": "1" + }, + { + "Key": "1.65 Gbps", + "Value": "2" + }, + { + "Key": "5.94 Gbps", + "Value": "3" + }, + { + "Key": "3.40 Gbps", + "Value": "4" + }, + { + "Key": "3.00 Gbps", + "Value": "5" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Select DP max Link Rate: ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP6_DP_Port_Max_LinkRate" + ], + "HelpText": "This feature limits the maximum link rate for DP Port. This field is valid only if DP is selected for Device Type. \n\nHBR3 is the max Link rate supported by ADL-P/M/N. UHBR link rates are supported only by RPL-P. So, choosing a Link rate greater than HBR3 for ADL-P/M/N will automatically force a fallback to HBR3 in GOP and gfx-driver. \n\nNote: OEM’s need to configure the maximum Link rate as per mother board support.", + "WidgetValues": [ + { + "Key": "Default Max Link Rate supported by Plaftform", + "Value": "0" + }, + { + "Key": "LBR (1.62 Gbps)", + "Value": "1" + }, + { + "Key": "HBR (2.7 Gbps)", + "Value": "2" + }, + { + "Key": "HBR2 (5.4 Gbps)", + "Value": "3" + }, + { + "Key": "HBR3 (8.1 Gbps)", + "Value": "4" + }, + { + "Key": "UHBR10 (10 Gbps)", + "Value": "5" + }, + { + "Key": "UHBR13_5 (13.5 Gbps)", + "Value": "6" + }, + { + "Key": "UHBR20 (20 Gbps)", + "Value": "7" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Select DP Port Max Lane Count Supported: ", + "Visibility": "", + "Data": [ + "2", + "EFP6_EDP_DP_Port_Max_LaneCount" + ], + "HelpText": "This feature allows for the selection of the Port Max Lane Count (Port Width) for the EDP/DP link.", + "WidgetValues": [ + { + "Key": "x1", + "Value": "0" + }, + { + "Key": "x2", + "Value": "1" + }, + { + "Key": "x4", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "EDIDless Panel: ", + "Visibility": "", + "Data": [ + "2", + "EFP6_EDIDless_en" + ], + "HelpText": "If the Attached panel is EDIDless select Yes and the supplied DTD takes priority.", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "Button", + "WidgetName": "EDID-less EFP Panel Generic DTD Timings", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "LTTPR(Link-Training Tunable PHY Repeaters) Mode: ", + "Visibility": "", + "Data": [ + "2", + "EFP6_LTTPRNonTransparentMode" + ], + "HelpText": "This option is used to enable or disable the LTTPR Non transparent Mode.", + "WidgetValues": [ + { + "Key": "Non-Transparent Mode", + "Value": "1" + }, + { + "Key": "Transparent Mode", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Max FrlRate Field Status", + "Visibility": "", + "Data": [ + "2", + "EFP6_IsMaxFrlRateFieldValid" + ], + "HelpText": "Indicates if we need to consider the MaxFrlRate field for HDMI2.1\nDisable - Don't consider the MaximumFrlRate for limiting the FrlRates on HDMI2.1 displays\nEnable - MaximumFrlRate given in bits 0 to 3 are used to override Max FRL Rate supported by platform/panel", + "WidgetValues": [ + { + "Key": "Disabled", + "Value": "0" + }, + { + "Key": "Enabled", + "Value": "1" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Maximum FrlRate ", + "Visibility": "", + "Data": [ + "2", + "EFP6_MaximumFrlRate" + ], + "HelpText": "0000 = FrlRates not supported (HDMI 2.1 is limited to support only TMDS modes)\n0001 = 3 GT/s\n0010 = 6 GT/s\n0011 = 8 GT/s\n0100 = 10 GT/s\n0101 = 12 GT/s", + "WidgetValues": [ + { + "Key": "FrlRates not supported", + "Value": "0" + }, + { + "Key": "3 GT/s", + "Value": "1" + }, + { + "Key": "6 GT/s", + "Value": "2" + }, + { + "Key": "8 GT/s", + "Value": "3" + }, + { + "Key": "10 GT/s", + "Value": "4" + }, + { + "Key": "12 GT/s", + "Value": "5" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "DP to HDMI Pcon: ", + "Visibility": "", + "Data": [ + "2", + "LSPcon6_Options" + ], + "HelpText": "This option is used to enable or disable the OnBoard LSPCON chip.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "DDI Lane Reversal: ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP6_Lane_Reversal" + ], + "HelpText": "This feature, when enabled, will set lane reversal bit for selected Port", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "DP Alt mode over Type C: ", + "Visibility": "", + "Data": [ + "2", + "EFP6_DP_Alt_Mode_OverTypeC_Enabled" + ], + "HelpText": "This option Enables/Disables DP alternate mode over type C ports.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "DP Tunneling over Thunderbolt: ", + "Visibility": "", + "Data": [ + "2", + "EFP6_Thunderbolt_Feature_Enabled" + ], + "HelpText": "This option Enables/Disables DP tunneling over Thunderbolt for selected Port.", + "WidgetValues": [ + { + "Key": "Enabled", + "Value": "1" + }, + { + "Key": "Disabled", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Dockable Port: ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP6_Port_Dockable" + ], + "HelpText": "This feature will describe if this Port is Dockable or Not.", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "Label", + "WidgetName": "Select DisplayPort Redriver ", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Vswing PreEmphasis Table Override: ", + "Visibility": "", + "Data": [ + "2", + "INT_EFP6_Vswing_Override_Enable" + ], + "HelpText": "This feature, when enabled, will allow Graphics driver to use the Vswing and Pre-emphasis values from VBT. OEM's must not enable or disable this on their own and work with the Intel CE team to change any settings in this page. When this field is enabled, corresponding table must be populated in the VBT for PHY Vswing parameters too.", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + } + ], + "NestedPages": [ + { + "Type": "Block", + "Block": { + "PageNum": "5-3-6-1", + "PageName": "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Non-dock topology: (OnBoard) ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP6_OnBoard_Redriver_Present" + ], + "HelpText": "This feature will describe if Non-Dock Topology/OnBoard Redriver DP Link is present or Not.", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Pre-Emphasis Level: ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP6_OnBoard_Pre_emphasis" + ], + "HelpText": "This feature allows for the selection of Pre-emphasis level for the OnBoard redriver DP link.\nLevel 0 (0 dB)\nLevel 1 (3.5 dB)\nLevel 2 (6.0 dB)\nLevel 3 (9.5 dB)", + "WidgetValues": [ + { + "Key": "Level-0", + "Value": "0" + }, + { + "Key": "Level-1", + "Value": "1" + }, + { + "Key": "Level-2", + "Value": "2" + }, + { + "Key": "Level-3", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Voltage Swing Level: ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP6_OnBoard_Voltage_swing" + ], + "HelpText": "This feature allows for the selection of voltage swing level for the OnBoard redriver DP link.\nSwing-0 (0.4 V)\nSwing-1 (0.6 V)\nSwing-2 (0.8 V)\nSwing-3 (1.2 V)", + "WidgetValues": [ + { + "Key": "Swing-0", + "Value": "0" + }, + { + "Key": "Swing-1", + "Value": "1" + }, + { + "Key": "Swing-2", + "Value": "2" + }, + { + "Key": "Swing-3", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": "Dock Topology: (Mobile only) ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP6_Dock_Redriver_Present" + ], + "HelpText": "This feature will describe if Dock Topology/Dock Redriver DP Link is present or not.", + "WidgetValues": [ + { + "Key": "Yes", + "Value": "1" + }, + { + "Key": "No", + "Value": "0" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Pre-Emphasis Level: ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP6_Dock_Pre_emphasis" + ], + "HelpText": "This feature allows for the selection of Pre-emphasis level for the Dock redriver DP link.\nLevel 0 (0 dB)\nLevel 1 (3.5 dB)\nLevel 2 (6.0 dB)\nLevel 3 (9.5 dB)", + "WidgetValues": [ + { + "Key": "Level-0", + "Value": "0" + }, + { + "Key": "Level-1", + "Value": "1" + }, + { + "Key": "Level-2", + "Value": "2" + }, + { + "Key": "Level-3", + "Value": "3" + } + ] + }, + { + "WidgetType": "ComboBox", + "WidgetName": " Voltage Swing Level: ", + "Visibility": "", + "Data": [ + "2", + "Int_EFP6_Dock_Voltage_swing" + ], + "HelpText": "This feature allows for the selection of voltage swing level for the Dock redriver DP link.\nSwing-0 (0.4 V)\nSwing-1 (0.6 V)\nSwing-2 (0.8 V)\nSwing-3 (1.2 V)", + "WidgetValues": [ + { + "Key": "Swing-0", + "Value": "0" + }, + { + "Key": "Swing-1", + "Value": "1" + }, + { + "Key": "Swing-2", + "Value": "2" + }, + { + "Key": "Swing-3", + "Value": "3" + } + ] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "5-3-6-2", + "PageName": "EDID-less EFP Panel Generic DTD Timings", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Pixel Clock in KHz: ", + "Visibility": "", + "Data": [ + "58", + "EFP_DTD_Pixel_CLK_06" + ], + "HelpText": "Pixel Clock (in KHz) Range from 0.001 to 4294967.295 MP/s.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Active: ", + "Visibility": "", + "Data": [ + "58", + "EFP_DTD_H_Active_06" + ], + "HelpText": "Horizontal Active Image Pixels Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Active: ", + "Visibility": "", + "Data": [ + "58", + "EFP_DTD_V_Active_06" + ], + "HelpText": "Vertical Active Image Lines Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Blank: ", + "Visibility": "", + "Data": [ + "58", + "EFP_DTD_H_Blank_06" + ], + "HelpText": "Horizontal Blank Pixels Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Blank: ", + "Visibility": "", + "Data": [ + "58", + "EFP_DTD_V_Blank_06" + ], + "HelpText": "Vertical Blank lines Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Front Porch: ", + "Visibility": "", + "Data": [ + "58", + "EFP_DTD_H_FrontPorch_06" + ], + "HelpText": "Horizontal Front Porch Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Front Porch: ", + "Visibility": "", + "Data": [ + "58", + "EFP_DTD_V_FrontPorch_06" + ], + "HelpText": "Vertical Front Porch Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Sync: ", + "Visibility": "", + "Data": [ + "58", + "EFP_DTD_H_Sync_06" + ], + "HelpText": "Horizontal Sync Width Number of Pixels ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Sync: ", + "Visibility": "", + "Data": [ + "58", + "EFP_DTD_V_Sync_06" + ], + "HelpText": "Vertical Sync Width Number of lines ranges from 1 to 65,536.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Horizontal Image Size: ", + "Visibility": "", + "Data": [ + "58", + "EFP_DTD_H_Image_Size_06" + ], + "HelpText": "Horizontal Addressable Video Image Size in mm represented by 16bits. Image size multiplier 1.00 mm precision.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": "Vertical Image Size: ", + "Visibility": "", + "Data": [ + "58", + "EFP_DTD_V_Image_Size_06" + ], + "HelpText": "Vertical Addressable Video Image Size in mm represented by 16bits. Image size multiplier 1.00 mm precision.", + "WidgetValues": [] + }, + { + "WidgetType": "EntryBin", + "WidgetName": "Common Flag: ", + "Visibility": "", + "Data": [ + "58", + "EFP_DTD_Common_Flag_06" + ], + "HelpText": "Common DTD Flags:\nBit 7 : Horizontal Sync Polarity\n1 : Positive\n0 : Negative\nBit 6 : Vertical Sync polarity\n1 : Positive\n0 : Negative\nBit 5 - 0: Reserved (Default value 0)", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + } + ] + } + } + ] + } + } + ] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "7", + "PageName": "OEM Customizable Modes", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "OEM Mode 1 Configuration", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": "OEM Mode 2 Configuration", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "Button", + "WidgetName": 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0\n\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\tGOP\tDriver\tVBIOS", + "WidgetValues": [] + }, + { + "WidgetType": "EntryBin", + "WidgetName": "Display Flags: ", + "Visibility": "", + "Data": [ + "20", + "OEM_Display2_Flags1" + ], + "HelpText": "Support flags: (0 = Disabled, 1 = Enabled)\n\n\tBit 9\tBit 8\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\n\tEFP 8\tEFP 7\tLFP 2\tEFP 2\tEFP 3\tEFP 4\tLFP 1\tEFP 1\tEFP 5\tEFP 6", + "WidgetValues": [] + }, + { + "WidgetType": "LabelHeading", + "WidgetName": "Mode Characteristics: ", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " X Resolution: ", + "Visibility": "", + "Data": [ + "20", + "OEM_Mode_X1" + ], + "HelpText": "X Resolution in pixels (decimal).", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Y Resolution: ", + "Visibility": "", + "Data": [ + "20", + "OEM_Mode_Y1" + ], + "HelpText": "Y Resolution in pixels (decimal).", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Refresh Rate: ", + "Visibility": "", + "Data": [ + "20", + "OEM_Mode_RRate1" + ], + "HelpText": "Refresh rate for OEM customizable mode (decimal).", + "WidgetValues": [] + } + ], + "NestedPages": [] + } + }, + { + "Type": "Block", + "Block": { + "PageNum": "7-2", + "PageName": "OEM Mode 2 Configuration", + "Visibility": "", + "PageHelpText": "", + "PageID": [ + { + "WidgetType": "Button", + "WidgetName": "Close Table", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryBin", + "WidgetName": "Support Flags: ", + "Visibility": "", + "Data": [ + "20", + "OEM_Mode_Flags2" + ], + "HelpText": "Support flags: (0 = Disabled, 1 = Enabled)\n\n\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\n\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\tGOP\tDriver\tVBIOS", + "WidgetValues": [] + }, + { + "WidgetType": "EntryBin", + "WidgetName": "Display Flags: ", + "Visibility": "", + "Data": [ + "20", + "OEM_Display2_Flags2" + ], + "HelpText": "Support flags: (0 = Disabled, 1 = Enabled)\n\n\tBit 9\tBit 8\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\n\tEFP 8\tEFP 7\tLFP 2\tEFP 2\tEFP 3\tEFP 4\tLFP 1\tEFP 1\tEFP 5\tEFP 6", + "WidgetValues": [] + }, + { + "WidgetType": "LabelHeading", + "WidgetName": "Mode Characteristics: ", + "Visibility": "", + "Data": [], + "HelpText": "", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " X Resolution: ", + "Visibility": "", + "Data": [ + "20", + "OEM_Mode_X2" + ], + "HelpText": "X Resolution in pixels (decimal).", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Y Resolution: ", + "Visibility": "", + "Data": [ + "20", + "OEM_Mode_Y2" + ], + "HelpText": "Y Resolution in pixels (decimal).", + "WidgetValues": [] + }, + { + "WidgetType": "EntryInt", + "WidgetName": " Refresh Rate: ", + "Visibility": "", + "Data": [ + "20", + "OEM_Mode_RRate2" + ], + "HelpText": "Refresh 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