From 12899ef3875414e6f105b04bf5c961322d932d99 Mon Sep 17 00:00:00 2001 From: Nate DeSimone Date: Mon, 14 Dec 2020 15:59:24 -0800 Subject: [PATCH] Convert Braswell BSF file to CR/LF format Signed-off-by: Nate DeSimone --- BraswellFspBinPkg/Vbt/vbt.bsf | 22906 ++++++++++++++++---------------- 1 file changed, 11453 insertions(+), 11453 deletions(-) diff --git a/BraswellFspBinPkg/Vbt/vbt.bsf b/BraswellFspBinPkg/Vbt/vbt.bsf index 2561219..8c32a51 100644 --- a/BraswellFspBinPkg/Vbt/vbt.bsf +++ b/BraswellFspBinPkg/Vbt/vbt.bsf @@ -1,11453 +1,11453 @@ -; TITLE BMP.bsf - BMP Scrip File for Video BIOS -;============================================================================== -; Advance Graphics ROM BIOS -;------------------------------------------------------------------------------ -; Copyright (c) Intel Corporation (2000 - 2011). -; -; INTEL MAKES NO WARRANTY OF ANY KIND REGARDING THE CODE. THIS CODE IS -; LICENSED ON AN "AS IS" BASIS AND INTEL WILL NOT PROVIDE ANY SUPPORT, -; ASSISTANCE, INSTALLATION, TRAINING OR OTHER SERVICES. -; INTEL DOES NOT PROVIDE ANY UPDATES, ENHANCEMENTS OR EXTENSIONS. -; INTEL SPECIFICALLY DISCLAIMS ANY WARRANTY OF MERCHANTABILITY, -; NONINFRINGEMENT, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY OTHER -; WARRANTY. -; -; Intel disclaims all liability, including liability for infringement of -; any proprietary rights, relating to use of the code. No license, express -; or implied, by estoppel or otherwise, to any intellectual property rights -; is granted herein. -; -; File Description: -; This file is the script file use by the BMP utility which will allow -; OEM's to edit data and select features on a binary file. -; -;------------------------------------------------------------------------------ - - -;============================================================================== -; Header - Start of BMP Structure Definition -;------------------------------------------------------------------------------ - -StructDef - -Find "BIOS_DATA_BLOCK " - - ; The following block will determine the reference - ; pointer for all table pointer variables. - -Find_Ptr_Ref "BIOS_DATA_BLOCK" ; Reference to beginning of VB VBT data - -$BDB_Ver 2 bytes ; BIOS Data Block version number (decimal, e.g.201 = 02.01) -$BDB_Header_Size 2 bytes ; BIOS Data Block Header size -$BDB_Size 2 bytes ; BIOS Data Block size - -;============================================================================== -; Block 254 - Signon Strings and Other General Data -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size - -$Bmp_BIOS_Size 2 bytes -$BIOS_Type 1 byte ; BIOS Type: - ; = 0, DESKTOP - ; = 1, MOBILE - -$RelStage 1 byte ; Release status - -$Chipset 1 byte ; = 17 - SandyBridge-Desktop - ; = 18 - Sandybridge-Mobile - ; = 19 - Ivybridge-Desktop - ; = 20 - Ivybridge-Mobile - ; = 21 - Haswell-Desktop - ; = 22 - Haswell-Mobile - - ; = 24 - VaalleyView - -$Integrated_LVDS 1 bit ; Integrated LVDS Support: - ; 1 = Yes - ; 0 = None - -$Integrated_TV 1 bit ; Integrated TV Support: - ; 1 = Yes - ; 0 = None - -$Integrated_EFP 1 bit ; Integrated EFP Support: - ; 1 = Yes - ; 0 = None - -$eDP 1 bit ; eDP: - ; 1 = Yes - ; 0 = None - -SKIP 4 bits -SKIP 4 bytes ; Skip build number string - - ; Signon and copyright strings - -$Signon 155 bytes ; Signon string -$Copyright 61 bytes ; Copyright string - - ; General Byte Definitions - -$bmp_BIOS_CS 2 bytes ; BIOS code segment -$bmp_VBIOS_Post_Mode 1 byte ; Mode number to set during V BIOS POST -$bmp_BW_Percent 1 byte ; Set percentage of total memory BW -SKIP 1 byte ; Popup Memory Size -$bmp_Resize_PCI_BIOS 1 byte ; BIOS size granularity in 0.5 KB -SKIP 1 byte ; Is the CRT already switched to DDC2 - -$Allow_Boot_DVI 1 bit ; Allow boot DVI even not attach -$Allow_Aspect_Ratio 1 bit ; VBIOS aspect ratio for DOS -SKIP 6 bits - -ALIGN - -;============================================================================== -; Block 1 - General Bit Definitions -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size - - ; - ; bmp_Bits_1 - ; - -$Enable_Panel_Fitting 2 bits ; Enable / Disable panel fitting -$Flexaim_Support 1 bit ; Enable / Disable Flex-aim support -$Msg_Enable 1 bit ; Disable signon and copyright -$Cls_After_Signon 3 bits ; Clear screen after display message and pause -$bmp_DVO_A_Color_Flip 1 bit ; Flat color flip -ALIGN - - ; - ; bmp_Bits_2 - ; -$Download_Ext_VBT 1 bit ; Download external VBT flag -$Enable_SSC 1 bit ; Enable/Disable SSC -$SSC_Freq 1 bit ; SSC Frequency -$Enable_LFPOn_Override 1 bit ; Enable/Disable LFP ON Override -$Disable_SSC_DDT 1 bit ; Disable SSC in Dual Display Twin -$Override_VGA_720p 1 bit ; Enable/Disable Override 720p for VGA modes -$Display_Clock_Mode 1 bit ; Enables DCI mode or legacy BTM mode -$Hotplug_Support_Enb 1 bit ; Hot Plug support in DOS - -ALIGN - ; - ; bmp_Bits_3 - ; -SKIP 2 bits -$180_Deg_Rotation_Enable 1 bit ; 180 Degree Rotation Enable bit -SKIP 5 bits -ALIGN - -$bmp_Legacy_Monitor_Detect 1 bit ; Use legacy monitor detect algorithm -SKIP 7 bits -ALIGN - - ; - ; Int_Displays_Support - ; -$Int_CRT_Support 1 bit ; Integrated CRT support -$Int_TV_Support 1 bit ; Integrated TV support -$Int_EFP_Support 1 bit ; Integrated EFP support -$DP_SSC_Enb 1 bit ; DP SSC Enable bit -$DP_SSC_Freq 1 bit ; DP SSC Frequency bit -$DP_SSC_Dongle_Enb 1 bit ; DP SSC dongle Enable/Disable -SKIP 2 bits - -ALIGN - - -;============================================================================== -; Block 253 - PRD Boot Algorithm Table -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size - -SKIP 1 byte -$ChildDevice1Primary 1 byte -$ChildDevice1Secondary 1 byte -SKIP 1 byte -$ChildDevice2Primary 1 byte -$ChildDevice2Secondary 1 byte -SKIP 1 byte -$ChildDevice3Primary 1 byte -$ChildDevice3Secondary 1 byte -SKIP 1 byte -$ChildDevice4Primary 1 byte -$ChildDevice4Secondary 1 byte -SKIP 1 byte -$ChildDevice5Primary 1 byte -$ChildDevice5Secondary 1 byte -SKIP 1 byte -$ChildDevice6Primary 1 byte -$ChildDevice6Secondary 1 byte -SKIP 1 byte -$ChildDevice7Primary 1 byte -$ChildDevice7Secondary 1 byte -SKIP 1 byte -$ChildDevice8Primary 1 byte -$ChildDevice8Secondary 1 byte -SKIP 1 byte -$ChildDevice9Primary 1 byte -$ChildDevice9Secondary 1 byte -SKIP 1 byte -$ChildDevice10Primary 1 byte -$ChildDevice10Secondary 1 byte -SKIP 1 byte -$ChildDevice11Primary 1 byte -$ChildDevice11Secondary 1 byte -SKIP 1 byte -$ChildDevice12Primary 1 byte -$ChildDevice12Secondary 1 byte -SKIP 1 byte -$ChildDevice13Primary 1 byte -$ChildDevice13Secondary 1 byte -SKIP 1 byte -$ChildDevice14Primary 1 byte -$ChildDevice14Secondary 1 byte -SKIP 1 byte -$ChildDevice15Primary 1 byte -$ChildDevice15Secondary 1 byte -SKIP 1 byte -$ChildDevice16Primary 1 byte -$ChildDevice16Secondary 1 byte - -SKIP 2 bytes ; No of entries - -;============================================================================== -; Block 2 - General Data Definitions -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size - -$CRT_DDC_GMBUS_Pin 1 byte ; CRT DDC GMBUS pin pair - -$DPMS_ACPI_Bit 1 bit ; Apply ACPI DPMS CRT Power States -$Skip_Boot_CRT_Detect 1 bit ; Disable/Enable skip boot CRT detect -$DPMS_AIM_Bit 1 bit ; Apply DPMS to AIM devices -SKIP 5 bits -ALIGN - - -$Boot_Display 2 bytes ; Boot display type -$size_ChildStruc 1 byte - - -$Int_LFP1_DID 2 bytes ; Skip Device Handle -$Int_LFP1_Type 2 bytes ; Device type -SKIP 7 bytes ; Skip -SKIP 1 byte ; Skip -$Int_LFP1_Priority 1 byte ; primary/secondary panel select -ALIGN -SKIP 3 bytes ; Skip -$Int_LFP1_Port 1 byte ; eDP port select -SKIP 2 bytes ; Skip remaining Data structure -$Int_LFP1_DDC_Pin 1 byte ; LFP DDC GMBUS pin pair -SKIP 5 bytes -$Int_LFP1_AUX_Channel 1 byte ; DP AUX channel -SKIP 7 bytes -SKIP 4 bytes - - - - -$Int_EFP1_DID 2 bytes ; Skip Device Handle -$Int_EFP1_Type 2 bytes ; Device type -SKIP 1 byte ; Skip I2C Speed -$EFP1_OnBoard_PreEmph_Level 3 bits ; EFP1 On Board Dp Redriver PreEmphasis Level -$EFP1_OnBoard_VSwing_Level 3 bits ; EFP1 On Board Dp Redriver VSwing Level -$EFP1_OnBoard_Redriver_Present 1 bit ; Is OnBoard Redriver Present for EFP1 -SKIP 1 bit ; Reserved -$EFP1_OnDock_PreEmph_Level 3 bits ; EFP1 On Dock Dp Redriver PreEmphasis Level -$EFP1_OnDock_VSwing_Level 3 bits ; EFP1 On Dock Dp Redriver VSwing Level -$EFP1_OnDock_Redriver_Present 1 bit ; Is On Dock Redriver Present for EFP1 -SKIP 1 bit ; Reserved -$Int_EFP1_HDMI_LS_Type 5 bits ; HDMI Level shifter configuration -SKIP 3 bits ; Reserved -ALIGN -SKIP 2 bytes ; Skip EDIDless DTD offset -$EFP1_EDIDless_en 1 bit ; EDIDless enable bit -SKIP 7 bits ; Skip remaining bits -SKIP 3 bytes ; Skip Reserved_1 -SKIP 2 bytes ; skip Addin module table offset -$Int_EFP1_Port 1 byte ; EFP1 port -SKIP 2 bytes ; Skip -$Int_EFP1_DDC_Pin 1 byte ; EFP1 DDC Pin -SKIP 3 bytes -$Int_EFP1_Docked_Port 1 bit ; HDMI/DP Docked Port -SKIP 1 bit ; Skip Enabling Lane Reversal Bit -SKIP 6 bits ; Reserved -$Int_EFP1_HDMI_Compat 1 bit ; HDMI combatibility -$Int_EFP1_Conn_Info 3 bits ; Connector information -SKIP 4 bits -$Int_EFP1_AUX_Channel 1 byte ; DP AUX channel -$Int_EFP1_Dongle_Detect 1 byte ; Dongle Detect -SKIP 6 bytes ; Skip -$EFP1_USB_C_DongleFeature_Enabled 1 bit ;USB C dongle feature enabled -SKIP 7 bits -$EFP1_GPIO_Index 1 byte ;GPIO resource ID used by drivers -$EFP1_GPIO_Number 2 bytes ;GPIO number - - -$Int_EFP2_DID 2 bytes ; Skip Device Handle -$Int_EFP2_Type 2 bytes ; Device type -SKIP 1 byte ; Skip I2C Speed -$EFP2_OnBoard_PreEmph_Level 3 bits ; EFP2 On Board Dp Redriver PreEmphasis Level -$EFP2_OnBoard_VSwing_Level 3 bits ; EFP2 On Board Dp Redriver VSwing Level -$EFP2_OnBoard_Redriver_Present 1 bit ; Is OnBoard Redriver Present for EFP2 -SKIP 1 bit ; Reserved -$EFP2_OnDock_PreEmph_Level 3 bits ; EFP2 On Dock Dp Redriver PreEmphasis Level -$EFP2_OnDock_VSwing_Level 3 bits ; EFP2 On Dock Dp Redriver VSwing Level -$EFP2_OnDock_Redriver_Present 1 bit ; Is On Dock Redriver Present for EFP2 -SKIP 1 bit ; Reserved -$Int_EFP2_HDMI_LS_Type 5 bits ; HDMI Level shifter configuration -SKIP 3 bits ; Reserved -ALIGN -SKIP 2 bytes ; Skip EDIDless DTD offset -$EFP2_EDIDless_en 1 bit ; EDIDless enable bit -SKIP 7 bits ; Skip remaining bits -SKIP 3 bytes ; Skip Reserved_1 -SKIP 2 bytes ; skip Addin module table offset -$Int_EFP2_Port 1 byte ; EFP1 port -SKIP 2 bytes ; Skip -$Int_EFP2_DDC_Pin 1 byte ; EFP1 DDC Pin -SKIP 3 bytes -$Int_EFP2_Docked_Port 1 bit ; HDMI/DP Docked Port -SKIP 1 bit ; Skip Enabling Lane Reversal Bit -SKIP 6 bits ; Reserved -$Int_EFP2_HDMI_Compat 1 bit ; HDMI combatibility -$Int_EFP2_Conn_Info 3 bits ; Connector information -SKIP 4 bits -$Int_EFP2_AUX_Channel 1 byte ; DP AUX channel -$Int_EFP2_Dongle_Detect 1 byte ; Dongle Detect -SKIP 6 bytes ; Skip -$EFP2_USB_C_DongleFeature_Enabled 1 bit ;USB C dongle feature enabled -SKIP 7 bits -$EFP2_GPIO_Index 1 byte ;GPIO resource ID used by drivers -$EFP2_GPIO_Number 2 bytes ;GPIO number - - -$Int_EFP3_DID 2 bytes ; Skip Device Handle -$Int_EFP3_Type 2 bytes ; Device type -SKIP 1 byte ; Skip I2C Speed -$EFP3_OnBoard_PreEmph_Level 3 bits ; EFP3 On Board Dp Redriver PreEmphasis Level -$EFP3_OnBoard_VSwing_Level 3 bits ; EFP3 On Board Dp Redriver VSwing Level -$EFP3_OnBoard_Redriver_Present 1 bit ; Is OnBoard Redriver Present for EFP2 -SKIP 1 bit ; Reserved -$EFP3_OnDock_PreEmph_Level 3 bits ; EFP3 On Dock Dp Redriver PreEmphasis Level -$EFP3_OnDock_VSwing_Level 3 bits ; EFP3 On Dock Dp Redriver VSwing Level -$EFP3_OnDock_Redriver_Present 1 bit ; Is On Dock Redriver Present for EFP3 -SKIP 1 bit ; Reserved -$Int_EFP3_HDMI_LS_Type 5 bits ; HDMI Level shifter configuration -SKIP 3 bits ; Reserved -ALIGN -SKIP 2 bytes ; Skip EDIDless DTD offset -$EFP3_EDIDless_en 1 bit ; EDIDless enable bit -SKIP 7 bits ; Skip remaining bits -SKIP 3 bytes ; Skip Reserved_1 -SKIP 2 bytes ; skip Addin module table offset -$Int_EFP3_Port 1 byte ; EFP3 port -SKIP 2 bytes ; Skip -$Int_EFP3_DDC_Pin 1 byte ; EFP3 DDC Pin -SKIP 3 bytes -$Int_EFP3_Docked_Port 1 bit ; HDMI/DP Docked Port -SKIP 1 bit ; Skip Enabling Lane Reversal Bit -SKIP 6 bits ; Reserved -$Int_EFP3_HDMI_Compat 1 bit ; HDMI combatibility -$Int_EFP3_Conn_Info 3 bits ; Connector information -SKIP 4 bits -$Int_EFP3_AUX_Channel 1 byte ; DP AUX channel -$Int_EFP3_Dongle_Detect 1 byte ; Dongle Detect -SKIP 6 bytes ; Skip -$EFP3_USB_C_DongleFeature_Enabled 1 bit ;USB C dongle feature enabled -SKIP 7 bits -$EFP3_GPIO_Index 1 byte ;GPIO resource ID used by drivers -$EFP3_GPIO_Number 2 bytes ;GPIO number - - - - - -;============================================================================== -; Block 3 - Original Display Toggle List -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size - -$bmp_Display_Detect 1 byte ; Display must be attached or not - -;============================================================================== -; Block 4 - Mode Support Bit Definitions -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size - -SKIP 28 bytes ; Mode List - -;============================================================================== -; Block 252 - Hook Defintions -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size - -$H31_POST_End_Hook 1 byte ; POST end hook int vector -$H33_After_Mode_Set 1 byte ; After mode set hook -$H35_Bootup_Display 1 byte ; Bootup display hook -$H38_Before_Mode_Set 1 byte ; Before mode set hook -$H45_VESA_DDC_Hook 1 byte ; VESA DDC hook interrupt vector -$H46_VESA_PM_Hook 1 byte ; VESA PM hook interrupt vector -$H47_Notify_Display_Sw 1 byte ; Notify display switch hook -$H48_After_VESA_PM 1 byte ; After VESA PM hook -$H14_Update_Display 1 byte ; Update Expansion/Display State Hook -$H14_Get_Misc_Status 1 byte ; Get Miscellaneous Status Hook -$H36_Boot_TV_Format 1 byte ; Boot TV to NTSC/PAL -$H34_Set_LFP_Fitting 1 byte ; Set panel fitting flags -$H40_Set_Panel_Type 1 byte ; Set panel fitting flags -$H49_Get_BL_Inv_Pol 1 byte ; Get inverter type and polarity for backlight -$H51_LFP_Panel_Type 1 byte ; Get active LFP configuration from CMOS setup -$H74_SR_Enable 1 byte ; Hook to enable/ disable Self Refresh as part of WA. - - ; BMP - Pointer tables - -$Dev_Boot_Table_Ptr 2 bytes ; Start at BMP Boot table -$Dev_Boot_Table_Size 2 bytes -$Dev_Boot_Table, $Dev_Boot_Table_Ptr, $Dev_Boot_Table_Size, Offset 0 byte - -$Dev_Removed_Table_Ptr 2 bytes ; Start at BMP Remove configurations table -$Dev_Removed_Table_Size 2 bytes -$Dev_Removed_Table, $Dev_Removed_Table_Ptr, $Dev_Removed_Table_Size, Offset 0 byte - -$MMIO_Boot_Table_Ptr 2 bytes ; Start at BMP Boot table -$MMIO_Boot_Table_Size 2 bytes -$MMIO_Boot_Table, $MMIO_Boot_Table_Ptr, $MMIO_Boot_Table_Size, Offset 0 byte - -$SWF_IO_Table_Ptr 2 bytes -$SWF_IO_Table_Size 2 bytes -$SWF_IO_Table, $SWF_IO_Table_Ptr, $SWF_IO_Table_Size, Offset 3 bytes - -$SWF_MMIO_Table_Ptr 2 bytes -$SWF_MMIO_Table_Size 2 bytes -$SWF_MMIO_Table, $SWF_MMIO_Table_Ptr, $SWF_MMIO_Table_Size, Offset 3 bytes - - -$Mode_Rem_Table_Ptr 2 bytes ; Start at BMP Boot table -$Mode_Rem_Table_Size 2 bytes -$Mode_Rem_Table, $Mode_Rem_Table_Ptr, $Mode_Rem_Table_Size, Offset 0 byte - -SKIP 80 bytes - -;============================================================================== -; Block 6 - Extended MMIO Register tables -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size - -SKIP 117 bytes ; Skip data - -;============================================================================== -; Block 7 - IO Software flag register table for initializaton -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size - -SKIP 7 bytes ; Skip data - -;============================================================================== -; Block 8 - MMIO Software flag register table for initializaton -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size - -SKIP 61 bytes ; Skip data - -;============================================================================== - -;============================================================================== -; Block 9 - PSR Feature Table -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size - -SKIP 96 bytes ; PSR Table data - -;============================================================================== - - -;============================================================================== -; Block 10 - Modes Removal Table. -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size - -SKIP 203 bytes ; Skip data - - -;============================================================================== -; Block 12 - Driver default boot display -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size -$Driver_Boot_Device 1 bit -$Block_Disp_Switch 1 bit -$Allow_FDOS_Disp_Switch 1 bit ; Allow FS DOS display switching -$Hot_Plug_DVO 1 bit -$Dual_View_Zoom 1 bit -$Drv_Int15_hook 1 bit -$DVD_Sprite_Clone 1 bit -$Use_110h_for_LFP 1 bit -ALIGN - -$Driver_Boot_Mode_X 2 bytes ; X resolution -$Driver_Boot_Mode_Y 2 bytes ; Y resolution -$Driver_Boot_Mode_BPP 1 byte ; Pixel depth -$Driver_Boot_Mode_RR 1 byte ; Refresh rate -; bmp_Ext_Driver_Bits - -$Enable_LFP_Primary 1 bit -$GTF_Mode_Pruning 1 bit -SKIP 1 bit ; DISABLE_DFGT -SKIP 1 bit ; DISABLE_DFGT -$NT4_Dual_Dsp_Clone_Spt 1 bit ; Dual display clone support for NT4 -$Default_Power_Scheme 1 bit -$Sprite_Display_Assign 1 bit ; Sprite Display Assignment for when Overlay is Active in Clone Mode -$CUI_Maintain_Aspect 1 bit ; Display "Maintain Aspect Ratio" via CUI -$Preserve_Aspect_Ratio 1 bit ; Preserve Aspect Ratio -$SDVO_Device_Power_Down 1 bit ; SDVO device power down -$Hot_Plug_CRT 1 bit ; CRT hot plug -$LVDS_Config 2 bits ; LVDS configuration -$Hot_Plug_TV 1 bit ; Hot plug TV enable/disable -$INT_HDMI_Config 2 bits ; Integrated HDMI Configuration -ALIGN - - ; bmp_Driver_Flags_1 - -$CUIHotK_Static_Display 1 bit -SKIP 7 bits -$Legacy_Monitor_Max_X 2 bytes -$Legacy_Monitor_Max_Y 2 bytes -$Legacy_Monitor_Max_RR 1 bytes -ALIGN - -; bmp_Ext2_Driver_Bits - -$Enable_Int_Src_Term 1 bit ; Enable Internal Source Termination for HDMI -SKIP 7 bits -ALIGN - -$VBT_Customization_Version 1 byte ; Customization VBT version number -ALIGN - - ; bmp_Driver_Feature_Flags - -SKIP 5 bits -$PM_DRRS_Enable 1 bit ; Intel ® Display Refresh Rate Switching (DRRS) Enable/Disable Flag. -SKIP 3 bits -$Panel_Self_Refresh 1 bit ; Panel Self refresh feature (PSR) -SKIP 2 bits -$DMRRS 1 bit ; Dynamic Media Refresh Rate Enable/Disable -SKIP 3 bits - -;============================================================================== -; Block 13 - Driver Persistence Algorithm -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size - -$Driver_Persist_Hotkey 1 bit -$Driver_Persist_Lid_Switch 1 bit -$Driver_Persist_PM 1 bit -$PersistHotkeyRestoreCloneMDS 1 bit -$PersistHotkeyRestoreRefreshrate 1 bit -$PersistHotkeyRestorePipe 1 bit -$PersistHotkeyRestoreMode 1 bit -$PersistEDIDRestoreMode 1 bit -$PersistHotPlugRestoreMode 1 bit -$Driver_Persist_Docking 1 bit -SKIP 6 bits -ALIGN -$PersistMaxConfig 1 byte - -;============================================================================== -; Block 16 - VBIOS/Driver Toggle list, capabilities tables -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size -SKIP 132 bytes ; Skip Toggle lists -ALIGN - - -;============================================================================== -; Block 17 - Test Feature -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size - -$SV_Dis_Arbiter 1 bit ; Disable VGA fast arbiter -$SV_Setmode_No_DVO 1 bit ; Do Setmode without reprogramming DVO -$SV_Special_GMBus 1 bit ; Special GMBus support -$SV_Wait_Timeout_Hang 1 bit -SKIP 4 bits -ALIGN -SKIP 7 bytes ; Skip reserved space - - -;============================================================================== -; Block 18 - Driver Rotation Configuration -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size -$Rotation_Support_Enable 1 bit ; Driver Rotation Feature Support bit -SKIP 7 bits -$Rot_Flags 1 byte -SKIP 10 bytes - - -;============================================================================== -; Block 19 - Removed Display Configurations -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size -SKIP 2 bytes ; Table Row/Size Data -SKIP 30 bytes ; Skip Removed displays table - - -;============================================================================== -; Block 20 - OEM Customizable Modes -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip ID -SKIP 2 bytes ; Table Row/Size Data - -$OEM_Mode_Flags1 1 byte -$OEM_Display_Flags1 1 byte -$OEM_Mode_X1 2 bytes -$OEM_Mode_Y1 2 bytes -$OEM_Mode_Color1 1 byte -$OEM_Mode_RRate1 1 byte -$OEM_Mode_DTD1 18 bytes - -$OEM_Mode_Flags2 1 byte -$OEM_Display_Flags2 1 byte -$OEM_Mode_X2 2 bytes -$OEM_Mode_Y2 2 bytes -$OEM_Mode_Color2 1 byte -$OEM_Mode_RRate2 1 byte -$OEM_Mode_DTD2 18 bytes - -$OEM_Mode_Flags3 1 byte -$OEM_Display_Flags3 1 byte -$OEM_Mode_X3 2 bytes -$OEM_Mode_Y3 2 bytes -$OEM_Mode_Color3 1 byte -$OEM_Mode_RRate3 1 byte -$OEM_Mode_DTD3 18 bytes - -$OEM_Mode_Flags4 1 byte -$OEM_Display_Flags4 1 byte -$OEM_Mode_X4 2 bytes -$OEM_Mode_Y4 2 bytes -$OEM_Mode_Color4 1 byte -$OEM_Mode_RRate4 1 byte -$OEM_Mode_DTD4 18 bytes - -$OEM_Mode_Flags5 1 byte -$OEM_Display_Flags5 1 byte -$OEM_Mode_X5 2 bytes -$OEM_Mode_Y5 2 bytes -$OEM_Mode_Color5 1 byte -$OEM_Mode_RRate5 1 byte -$OEM_Mode_DTD5 18 bytes - -$OEM_Mode_Flags6 1 byte -$OEM_Display_Flags6 1 byte -$OEM_Mode_X6 2 bytes -$OEM_Mode_Y6 2 bytes -$OEM_Mode_Color6 1 byte -$OEM_Mode_RRate6 1 byte -$OEM_Mode_DTD6 18 bytes - -;============================================================================== -; Block 26 - TV Options -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip ID and size -$Under_Over_Scan_Via_YPrPb 2 bits ; Underscan/overscan for HDTV via YPrPb -SKIP 10 bits -$Under_Over_Scan_Via_DVI 2 bits ; Underscan/overscan for HDTV via DVI -$Add_Overscan_Mode 1 bit ; Add modes to avoid overscan issue -$D_Connector 1 bit ; D-Connector Support -ALIGN - -;============================================================================== -; Block #27 - eDP Power Sequencing -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size - - ; Panel#1 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_01 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_01 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_01 2 bytes -$eDP_DataOff_To_PowerOff_Delay_01 2 bytes -$eDP_PowerCycle_Delay_01 2 bytes - - ; Panel#2 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_02 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_02 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_02 2 bytes -$eDP_DataOff_To_PowerOff_Delay_02 2 bytes -$eDP_PowerCycle_Delay_02 2 bytes - - ; Panel#3 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_03 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_03 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_03 2 bytes -$eDP_DataOff_To_PowerOff_Delay_03 2 bytes -$eDP_PowerCycle_Delay_03 2 bytes - - ; Panel#4 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_04 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_04 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_04 2 bytes -$eDP_DataOff_To_PowerOff_Delay_04 2 bytes -$eDP_PowerCycle_Delay_04 2 bytes - - ; Panel#5 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_05 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_05 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_05 2 bytes -$eDP_DataOff_To_PowerOff_Delay_05 2 bytes -$eDP_PowerCycle_Delay_05 2 bytes - - ; Panel#6 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_06 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_06 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_06 2 bytes -$eDP_DataOff_To_PowerOff_Delay_06 2 bytes -$eDP_PowerCycle_Delay_06 2 bytes - - ; Panel#7 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_07 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_07 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_07 2 bytes -$eDP_DataOff_To_PowerOff_Delay_07 2 bytes -$eDP_PowerCycle_Delay_07 2 bytes - - ; Panel#8 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_08 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_08 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_08 2 bytes -$eDP_DataOff_To_PowerOff_Delay_08 2 bytes -$eDP_PowerCycle_Delay_08 2 bytes - - ; Panel#9 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_09 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_09 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_09 2 bytes -$eDP_DataOff_To_PowerOff_Delay_09 2 bytes -$eDP_PowerCycle_Delay_09 2 bytes - - ; Panel#10 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_10 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_10 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_10 2 bytes -$eDP_DataOff_To_PowerOff_Delay_10 2 bytes -$eDP_PowerCycle_Delay_10 2 bytes - - ; Panel#11 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_11 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_11 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_11 2 bytes -$eDP_DataOff_To_PowerOff_Delay_11 2 bytes -$eDP_PowerCycle_Delay_11 2 bytes - - ; Panel#12 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_12 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_12 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_12 2 bytes -$eDP_DataOff_To_PowerOff_Delay_12 2 bytes -$eDP_PowerCycle_Delay_12 2 bytes - - ; Panel#13 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_13 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_13 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_13 2 bytes -$eDP_DataOff_To_PowerOff_Delay_13 2 bytes -$eDP_PowerCycle_Delay_13 2 bytes - - ; Panel#14 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_14 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_14 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_14 2 bytes -$eDP_DataOff_To_PowerOff_Delay_14 2 bytes -$eDP_PowerCycle_Delay_14 2 bytes - - ; Panel#15 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_15 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_15 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_15 2 bytes -$eDP_DataOff_To_PowerOff_Delay_15 2 bytes -$eDP_PowerCycle_Delay_15 2 bytes - - ; Panel#16 Power Sequencing -$eDP_Vcc_To_Hpd_Delay_16 2 bytes -$eDP_DataOn_To_BkltEnable_Delay_16 2 bytes -$eDP_BkltDisable_To_DataOff_Delay_16 2 bytes -$eDP_DataOff_To_PowerOff_Delay_16 2 bytes -$eDP_PowerCycle_Delay_16 2 bytes - -$eDP_Panel_Color_Depth_01 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_02 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_03 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_04 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_05 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_06 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_07 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_08 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_09 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_10 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_11 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_12 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_13 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_14 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_15 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp -$eDP_Panel_Color_Depth_16 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp - -$eDP_Link_DataRate_01 4 bits ; Panel #1 Link Data Rate -$eDP_Link_LaneCount_01 4 bits ; Panel #1 Link Lane Count -$eDP_Link_PreEmp_01 4 bits ; Panel #1 Link Pre-emphasis -$eDP_Link_Vswing_01 4 bits ; Panel #1 Link Voltage Swing - -$eDP_Link_DataRate_02 4 bits ; Panel #2 Link Data Rate -$eDP_Link_LaneCount_02 4 bits ; Panel #2 Link Lane Count -$eDP_Link_PreEmp_02 4 bits ; Panel #2 Link Pre-emphasis -$eDP_Link_Vswing_02 4 bits ; Panel #2 Link Voltage Swing - -$eDP_Link_DataRate_03 4 bits ; Panel #3 Link Data Rate -$eDP_Link_LaneCount_03 4 bits ; Panel #3 Link Lane Count -$eDP_Link_PreEmp_03 4 bits ; Panel #3 Link Pre-emphasis -$eDP_Link_Vswing_03 4 bits ; Panel #3 Link Voltage Swing - -$eDP_Link_DataRate_04 4 bits ; Panel #4 Link Data Rate -$eDP_Link_LaneCount_04 4 bits ; Panel #4 Link Lane Count -$eDP_Link_PreEmp_04 4 bits ; Panel #4 Link Pre-emphasis -$eDP_Link_Vswing_04 4 bits ; Panel #4 Link Voltage Swing - -$eDP_Link_DataRate_05 4 bits ; Panel #5 Link Data Rate -$eDP_Link_LaneCount_05 4 bits ; Panel #5 Link Lane Count -$eDP_Link_PreEmp_05 4 bits ; Panel #5 Link Pre-emphasis -$eDP_Link_Vswing_05 4 bits ; Panel #5 Link Voltage Swing - -$eDP_Link_DataRate_06 4 bits ; Panel #6 Link Data Rate -$eDP_Link_LaneCount_06 4 bits ; Panel #6 Link Lane Count -$eDP_Link_PreEmp_06 4 bits ; Panel #6 Link Pre-emphasis -$eDP_Link_Vswing_06 4 bits ; Panel #6 Link Voltage Swing - -$eDP_Link_DataRate_07 4 bits ; Panel #7 Link Data Rate -$eDP_Link_LaneCount_07 4 bits ; Panel #7 Link Lane Count -$eDP_Link_PreEmp_07 4 bits ; Panel #7 Link Pre-emphasis -$eDP_Link_Vswing_07 4 bits ; Panel #7 Link Voltage Swing - -$eDP_Link_DataRate_08 4 bits ; Panel #8 Link Data Rate -$eDP_Link_LaneCount_08 4 bits ; Panel #8 Link Lane Count -$eDP_Link_PreEmp_08 4 bits ; Panel #8 Link Pre-emphasis -$eDP_Link_Vswing_08 4 bits ; Panel #8 Link Voltage Swing - -$eDP_Link_DataRate_09 4 bits ; Panel #9 Link Data Rate -$eDP_Link_LaneCount_09 4 bits ; Panel #9 Link Lane Count -$eDP_Link_PreEmp_09 4 bits ; Panel #9 Link Pre-emphasis -$eDP_Link_Vswing_09 4 bits ; Panel #9 Link Voltage Swing - -$eDP_Link_DataRate_10 4 bits ; Panel #10 Link Data Rate -$eDP_Link_LaneCount_10 4 bits ; Panel #10 Link Lane Count -$eDP_Link_PreEmp_10 4 bits ; Panel #10 Link Pre-emphasis -$eDP_Link_Vswing_10 4 bits ; Panel #10 Link Voltage Swing - -$eDP_Link_DataRate_11 4 bits ; Panel #11 Link Data Rate -$eDP_Link_LaneCount_11 4 bits ; Panel #11 Link Lane Count -$eDP_Link_PreEmp_11 4 bits ; Panel #11 Link Pre-emphasis -$eDP_Link_Vswing_11 4 bits ; Panel #11 Link Voltage Swing - -$eDP_Link_DataRate_12 4 bits ; Panel #12 Link Data Rate -$eDP_Link_LaneCount_12 4 bits ; Panel #12 Link Lane Count -$eDP_Link_PreEmp_12 4 bits ; Panel #12 Link Pre-emphasis -$eDP_Link_Vswing_12 4 bits ; Panel #12 Link Voltage Swing - -$eDP_Link_DataRate_13 4 bits ; Panel #13 Link Data Rate -$eDP_Link_LaneCount_13 4 bits ; Panel #13 Link Lane Count -$eDP_Link_PreEmp_13 4 bits ; Panel #13 Link Pre-emphasis -$eDP_Link_Vswing_13 4 bits ; Panel #13 Link Voltage Swing - -$eDP_Link_DataRate_14 4 bits ; Panel #14 Link Data Rate -$eDP_Link_LaneCount_14 4 bits ; Panel #14 Link Lane Count -$eDP_Link_PreEmp_14 4 bits ; Panel #14 Link Pre-emphasis -$eDP_Link_Vswing_14 4 bits ; Panel #14 Link Voltage Swing - -$eDP_Link_DataRate_15 4 bits ; Panel #15 Link Data Rate -$eDP_Link_LaneCount_15 4 bits ; Panel #15 Link Lane Count -$eDP_Link_PreEmp_15 4 bits ; Panel #15 Link Pre-emphasis -$eDP_Link_Vswing_15 4 bits ; Panel #15 Link Voltage Swing - -$eDP_Link_DataRate_16 4 bits ; Panel #16 Link Data Rate -$eDP_Link_LaneCount_16 4 bits ; Panel #16 Link Lane Count -$eDP_Link_PreEmp_16 4 bits ; Panel #16 Link Pre-emphasis -$eDP_Link_Vswing_16 4 bits ; Panel #16 Link Voltage Swing - -$eDP_sDRRS_MSA_Delay_01 2 bits ; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4 -$eDP_sDRRS_MSA_Delay_02 2 bits ; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4 -$eDP_sDRRS_MSA_Delay_03 2 bits ; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4 -$eDP_sDRRS_MSA_Delay_04 2 bits ; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4 -$eDP_sDRRS_MSA_Delay_05 2 bits ; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4 -$eDP_sDRRS_MSA_Delay_06 2 bits ; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4 -$eDP_sDRRS_MSA_Delay_07 2 bits ; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4 -$eDP_sDRRS_MSA_Delay_08 2 bits ; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4 -$eDP_sDRRS_MSA_Delay_09 2 bits ; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4 -$eDP_sDRRS_MSA_Delay_10 2 bits ; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4 -$eDP_sDRRS_MSA_Delay_11 2 bits ; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4 -$eDP_sDRRS_MSA_Delay_12 2 bits ; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4 -$eDP_sDRRS_MSA_Delay_13 2 bits ; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4 -$eDP_sDRRS_MSA_Delay_14 2 bits ; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4 -$eDP_sDRRS_MSA_Delay_15 2 bits ; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4 -$eDP_sDRRS_MSA_Delay_16 2 bits ; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4 - -SKIP 2 bytes ; S3D Feature -$eDP_T3_Optimization_01 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #01 -$eDP_T3_Optimization_02 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #02 -$eDP_T3_Optimization_03 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #03 -$eDP_T3_Optimization_04 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #04 -$eDP_T3_Optimization_05 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #05 -$eDP_T3_Optimization_06 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #06 -$eDP_T3_Optimization_07 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #07 -$eDP_T3_Optimization_08 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #08 -$eDP_T3_Optimization_09 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #09 -$eDP_T3_Optimization_10 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #10 -$eDP_T3_Optimization_11 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #11 -$eDP_T3_Optimization_12 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #12 -$eDP_T3_Optimization_13 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #13 -$eDP_T3_Optimization_14 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #14 -$eDP_T3_Optimization_15 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #15 -$eDP_T3_Optimization_16 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #16 - -$eDP_VSwingPreEmph_1 4 bits; eDp selects VSwing Preemph table for panel #1 -$eDP_VSwingPreEmph_2 4 bits; eDp selects VSwing Preemph table for panel #2 -$eDP_VSwingPreEmph_3 4 bits; eDp selects VSwing Preemph table for panel #3 -$eDP_VSwingPreEmph_4 4 bits; eDp selects VSwing Preemph table for panel #4 -$eDP_VSwingPreEmph_5 4 bits; eDp selects VSwing Preemph table for panel #5 -$eDP_VSwingPreEmph_6 4 bits; eDp selects VSwing Preemph table for panel #6 -$eDP_VSwingPreEmph_7 4 bits; eDp selects VSwing Preemph table for panel #7 -$eDP_VSwingPreEmph_8 4 bits; eDp selects VSwing Preemph table for panel #8 -$eDP_VSwingPreEmph_9 4 bits; eDp selects VSwing Preemph table for panel #9 -$eDP_VSwingPreEmph_10 4 bits; eDp selects VSwing Preemph table for panel #10 -$eDP_VSwingPreEmph_11 4 bits; eDp selects VSwing Preemph table for panel #11 -$eDP_VSwingPreEmph_12 4 bits; eDp selects VSwing Preemph table for panel #12 -$eDP_VSwingPreEmph_13 4 bits; eDp selects VSwing Preemph table for panel #13 -$eDP_VSwingPreEmph_14 4 bits; eDp selects VSwing Preemph table for panel #14 -$eDP_VSwingPreEmph_15 4 bits; eDp selects VSwing Preemph table for panel #15 -$eDP_VSwingPreEmph_16 4 bits; eDp selects VSwing Preemph table for panel #16 - -$Fast_Link_Training_Supported_01 1 bit ; eDP Selects Fast Link Training if supported for Panel #1 -$Fast_Link_Training_Supported_02 1 bit ; eDP Selects Fast Link Training if supported for Panel #2 -$Fast_Link_Training_Supported_03 1 bit ; eDP Selects Fast Link Training if supported for Panel #3 -$Fast_Link_Training_Supported_04 1 bit ; eDP Selects Fast Link Training if supported for Panel #4 -$Fast_Link_Training_Supported_05 1 bit ; eDP Selects Fast Link Training if supported for Panel #5 -$Fast_Link_Training_Supported_06 1 bit ; eDP Selects Fast Link Training if supported for Panel #6 -$Fast_Link_Training_Supported_07 1 bit ; eDP Selects Fast Link Training if supported for Panel #7 -$Fast_Link_Training_Supported_08 1 bit ; eDP Selects Fast Link Training if supported for Panel #8 -$Fast_Link_Training_Supported_09 1 bit ; eDP Selects Fast Link Training if supported for Panel #9 -$Fast_Link_Training_Supported_10 1 bit ; eDP Selects Fast Link Training if supported for Panel #10 -$Fast_Link_Training_Supported_11 1 bit ; eDP Selects Fast Link Training if supported for Panel #11 -$Fast_Link_Training_Supported_12 1 bit ; eDP Selects Fast Link Training if supported for Panel #12 -$Fast_Link_Training_Supported_13 1 bit ; eDP Selects Fast Link Training if supported for Panel #13 -$Fast_Link_Training_Supported_14 1 bit ; eDP Selects Fast Link Training if supported for Panel #14 -$Fast_Link_Training_Supported_15 1 bit ; eDP Selects Fast Link Training if supported for Panel #15 -$Fast_Link_Training_Supported_16 1 bit ; eDP Selects Fast Link Training if supported for Panel #16 - -SKIP 2 bytes ;Skip Enable Power State at DPCD 600h - -$eDP_PwmOn_To_Bklt_Enable_Delay_01 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#1 -$eDP_Bklt_Disable_To_PwmOff_Delay_01 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#1 - -$eDP_PwmOn_To_Bklt_Enable_Delay_02 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#2 -$eDP_Bklt_Disable_To_PwmOff_Delay_02 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#2 - -$eDP_PwmOn_To_Bklt_Enable_Delay_03 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#3 -$eDP_Bklt_Disable_To_PwmOff_Delay_03 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#3 - -$eDP_PwmOn_To_Bklt_Enable_Delay_04 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#4 -$eDP_Bklt_Disable_To_PwmOff_Delay_04 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#4 - -$eDP_PwmOn_To_Bklt_Enable_Delay_05 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#5 -$eDP_Bklt_Disable_To_PwmOff_Delay_05 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#5 - -$eDP_PwmOn_To_Bklt_Enable_Delay_06 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#6 -$eDP_Bklt_Disable_To_PwmOff_Delay_06 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#6 - -$eDP_PwmOn_To_Bklt_Enable_Delay_07 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#7 -$eDP_Bklt_Disable_To_PwmOff_Delay_07 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#7 - -$eDP_PwmOn_To_Bklt_Enable_Delay_08 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#8 -$eDP_Bklt_Disable_To_PwmOff_Delay_08 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#8 - -$eDP_PwmOn_To_Bklt_Enable_Delay_09 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#9 -$eDP_Bklt_Disable_To_PwmOff_Delay_09 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#9 - -$eDP_PwmOn_To_Bklt_Enable_Delay_10 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#10 -$eDP_Bklt_Disable_To_PwmOff_Delay_10 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#10 - -$eDP_PwmOn_To_Bklt_Enable_Delay_11 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#11 -$eDP_Bklt_Disable_To_PwmOff_Delay_11 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#11 - -$eDP_PwmOn_To_Bklt_Enable_Delay_12 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#12 -$eDP_Bklt_Disable_To_PwmOff_Delay_12 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#12 - -$eDP_PwmOn_To_Bklt_Enable_Delay_13 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#13 -$eDP_Bklt_Disable_To_PwmOff_Delay_13 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#13 - -$eDP_PwmOn_To_Bklt_Enable_Delay_14 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#14 -$eDP_Bklt_Disable_To_PwmOff_Delay_14 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#14 - -$eDP_PwmOn_To_Bklt_Enable_Delay_15 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#15 -$eDP_Bklt_Disable_To_PwmOff_Delay_15 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#15 - -$eDP_PwmOn_To_Bklt_Enable_Delay_16 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#16 -$eDP_Bklt_Disable_To_PwmOff_Delay_16 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#16 - -;============================================================================== -; Block 28 - EDID-less EFP support - Panel data -;------------------------------------------------------------------------------ -SKIP 3 bytes ; Skip block ID and size -$EFP1_DTD 18 bytes ; DTD for Device 1 DP/HDMI/DVI panel -$EFP2_DTD 18 bytes ; DTD for Device 2 DP/HDMI/DVI panel -$EFP3_DTD 18 bytes ; DTD for Device 3 DP/HDMI/DVI panel -$EFP4_DTD 18 bytes ; DTD for Device 4 DP/HDMI/DVI panel - -;============================================================================== -; Block 31 - VBIOS/Driver Toggle list for HSW/BDW/CHV -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size -SKIP 3 bytes ; Skip number of entries and entry size -$Toggle_List1 32 bytes ; Toggle list 1 -SKIP 3 bytes ; Skip number of entries and entry size -$Toggle_List2 16 bytes ; Toggle list 2 -SKIP 3 bytes ; Skip number of entries and entry size -$Toggle_List3 16 bytes ; Toggle list 3 -SKIP 3 bytes ; Skip number of entries and entry size -$Toggle_List4 16 bytes ; Toggle list 4 -ALIGN - -;============================================================================== -; Block 40 - Start of LVDS BMP Structure Definition -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size - -$bmp_Panel_type 1 byte ; Flat panel type -SKIP 1 byte ; Obsoleted -SKIP 6 bits -$bmp_Panel_EDID 1 bit ; LVDS panel EDID enable/disable bit -SKIP 1 bit -SKIP 1 byte - - ; INT_LVDS_Panel_Channel_Bits - -$Int_LVDS_Panel_1_Channel_Type 2 bits ; Bits [2:3] = Panel #1 - ; = 00, Automatic (algorithm) - ; = 01, Single Channel - ; = 10, Dual Channel - ; = 11, Reserved -$Int_LVDS_Panel_2_Channel_Type 2 bits ; Bits [2:3] = Panel #2 - ; = 00, Automatic (algorithm) - ; = 01, Single Channel - ; = 10, Dual Channel - ; = 11, Reserved -$Int_LVDS_Panel_3_Channel_Type 2 bits ; Bits [2:3] = Panel #3 - ; = 00, Automatic (algorithm) - ; = 01, Single Channel - ; = 10, Dual Channel - ; = 11, Reserved -$Int_LVDS_Panel_4_Channel_Type 2 bits ; Bits [2:3] = Panel #4 - ; = 00, Automatic (algorithm) - ; = 01, Single Channel - ; = 10, Dual Channel - ; = 11, Reserved -$Int_LVDS_Panel_5_Channel_Type 2 bits ; Bits [2:3] = Panel #5 - ; = 00, Automatic (algorithm) - ; = 01, Single Channel - ; = 10, Dual Channel - ; = 11, Reserved -$Int_LVDS_Panel_6_Channel_Type 2 bits ; Bits [2:3] = Panel #6 - ; = 00, Automatic (algorithm) - ; = 01, Single Channel - ; = 10, Dual Channel - ; = 11, Reserved -$Int_LVDS_Panel_7_Channel_Type 2 bits ; Bits [2:3] = Panel #7 - ; = 00, Automatic (algorithm) - ; = 01, Single Channel - ; = 10, Dual Channel - ; = 11, Reserved -$Int_LVDS_Panel_8_Channel_Type 2 bits ; Bits [2:3] = Panel #8 - ; = 00, Automatic (algorithm) - ; = 01, Single Channel - ; = 10, Dual Channel - ; = 11, Reserved -$Int_LVDS_Panel_9_Channel_Type 2 bits ; Bits [2:3] = Panel #9 - ; = 00, Automatic (algorithm) - ; = 01, Single Channel - ; = 10, Dual Channel - ; = 11, Reserved -$Int_LVDS_Panel_10_Channel_Type 2 bits ; Bits [2:3] = Panel #10 - ; = 00, Automatic (algorithm) - ; = 01, Single Channel - ; = 10, Dual Channel - ; = 11, Reserved -$Int_LVDS_Panel_11_Channel_Type 2 bits ; Bits [2:3] = Panel #11 - ; = 00, Automatic (algorithm) - ; = 01, Single Channel - ; = 10, Dual Channel - ; = 11, Reserved -$Int_LVDS_Panel_12_Channel_Type 2 bits ; Bits [2:3] = Panel #12 - ; = 00, Automatic (algorithm) - ; = 01, Single Channel - ; = 10, Dual Channel - ; = 11, Reserved -$Int_LVDS_Panel_13_Channel_Type 2 bits ; Bits [2:3] = Panel #13 - ; = 00, Automatic (algorithm) - ; = 01, Single Channel - ; = 10, Dual Channel - ; = 11, Reserved -$Int_LVDS_Panel_14_Channel_Type 2 bits ; Bits [2:3] = Panel #14 - ; = 00, Automatic (algorithm) - ; = 01, Single Channel - ; = 10, Dual Channel - ; = 11, Reserved -$Int_LVDS_Panel_15_Channel_Type 2 bits ; Bits [2:3] = Panel #15 - ; = 00, Automatic (algorithm) - ; = 01, Single Channel - ; = 10, Dual Channel - ; = 11, Reserved -$Int_LVDS_Panel_16_Channel_Type 2 bits ; Bits [2:3] = Panel #16 - ; = 00, Automatic (algorithm) - ; = 01, Single Channel - ; = 10, Dual Channel - ; = 11, Reserved - - ; LVDS Spread Spectrum Clock - ; Enabel/Disable SSC -$Enable_SSC01 1 bit ; Panel #01, 0=No, 1=Yes -$Enable_SSC02 1 bit ; Panel #02, 0=No, 1=Yes -$Enable_SSC03 1 bit ; Panel #03, 0=No, 1=Yes -$Enable_SSC04 1 bit ; Panel #04, 0=No, 1=Yes -$Enable_SSC05 1 bit ; Panel #05, 0=No, 1=Yes -$Enable_SSC06 1 bit ; Panel #06, 0=No, 1=Yes -$Enable_SSC07 1 bit ; Panel #07, 0=No, 1=Yes -$Enable_SSC08 1 bit ; Panel #08, 0=No, 1=Yes -$Enable_SSC09 1 bit ; Panel #09, 0=No, 1=Yes -$Enable_SSC10 1 bit ; Panel #10, 0=No, 1=Yes -$Enable_SSC11 1 bit ; Panel #11, 0=No, 1=Yes -$Enable_SSC12 1 bit ; Panel #12, 0=No, 1=Yes -$Enable_SSC13 1 bit ; Panel #13, 0=No, 1=Yes -$Enable_SSC14 1 bit ; Panel #14, 0=No, 1=Yes -$Enable_SSC15 1 bit ; Panel #15, 0=No, 1=Yes -$Enable_SSC16 1 bit ; Panel #16, 0=No, 1=Yes - - ; LVDS Spread Spectrum Clock Frequency - ; SSC Frequency -$SSC_Freq01 1 bit ; Panel #01, 0=48MHz, 1=66MHz -$SSC_Freq02 1 bit ; Panel #02, 0=48MHz, 1=66MHz -$SSC_Freq03 1 bit ; Panel #03, 0=48MHz, 1=66MHz -$SSC_Freq04 1 bit ; Panel #04, 0=48MHz, 1=66MHz -$SSC_Freq05 1 bit ; Panel #05, 0=48MHz, 1=66MHz -$SSC_Freq06 1 bit ; Panel #06, 0=48MHz, 1=66MHz -$SSC_Freq07 1 bit ; Panel #07, 0=48MHz, 1=66MHz -$SSC_Freq08 1 bit ; Panel #08, 0=48MHz, 1=66MHz -$SSC_Freq09 1 bit ; Panel #09, 0=48MHz, 1=66MHz -$SSC_Freq10 1 bit ; Panel #10, 0=48MHz, 1=66MHz -$SSC_Freq11 1 bit ; Panel #11, 0=48MHz, 1=66MHz -$SSC_Freq12 1 bit ; Panel #12, 0=48MHz, 1=66MHz -$SSC_Freq13 1 bit ; Panel #13, 0=48MHz, 1=66MHz -$SSC_Freq14 1 bit ; Panel #14, 0=48MHz, 1=66MHz -$SSC_Freq15 1 bit ; Panel #15, 0=48MHz, 1=66MHz -$SSC_Freq16 1 bit ; Panel #16, 0=48MHz, 1=66MHz - - ; Disable SSC in Dual Display Twin -$Disable_SSC_DDT01 1 bit ; panel #01, 0=Disable, 1=Enable -$Disable_SSC_DDT02 1 bit ; panel #02, 0=Disable, 1=Enable -$Disable_SSC_DDT03 1 bit ; panel #03, 0=Disable, 1=Enable -$Disable_SSC_DDT04 1 bit ; panel #04, 0=Disable, 1=Enable -$Disable_SSC_DDT05 1 bit ; panel #05, 0=Disable, 1=Enable -$Disable_SSC_DDT06 1 bit ; panel #06, 0=Disable, 1=Enable -$Disable_SSC_DDT07 1 bit ; panel #07, 0=Disable, 1=Enable -$Disable_SSC_DDT08 1 bit ; panel #08, 0=Disable, 1=Enable -$Disable_SSC_DDT09 1 bit ; panel #09, 0=Disable, 1=Enable -$Disable_SSC_DDT10 1 bit ; panel #10, 0=Disable, 1=Enable -$Disable_SSC_DDT11 1 bit ; panel #11, 0=Disable, 1=Enable -$Disable_SSC_DDT12 1 bit ; panel #12, 0=Disable, 1=Enable -$Disable_SSC_DDT13 1 bit ; panel #13, 0=Disable, 1=Enable -$Disable_SSC_DDT14 1 bit ; panel #14, 0=Disable, 1=Enable -$Disable_SSC_DDT15 1 bit ; panel #15, 0=Disable, 1=Enable -$Disable_SSC_DDT16 1 bit ; panel #16, 0=Disable, 1=Enable - -$INT_Panel_Color_Depth01 1 bit ; Panel #01, 0 = 18bpps, 1 = 24bpps -$INT_Panel_Color_Depth02 1 bit ; Panel #02, 0 = 18bpps, 1 = 24bpps -$INT_Panel_Color_Depth03 1 bit ; Panel #03, 0 = 18bpps, 1 = 24bpps -$INT_Panel_Color_Depth04 1 bit ; Panel #04, 0 = 18bpps, 1 = 24bpps -$INT_Panel_Color_Depth05 1 bit ; Panel #05, 0 = 18bpps, 1 = 24bpps -$INT_Panel_Color_Depth06 1 bit ; Panel #06, 0 = 18bpps, 1 = 24bpps -$INT_Panel_Color_Depth07 1 bit ; Panel #07, 0 = 18bpps, 1 = 24bpps -$INT_Panel_Color_Depth08 1 bit ; Panel #08, 0 = 18bpps, 1 = 24bpps -$INT_Panel_Color_Depth09 1 bit ; Panel #09, 0 = 18bpps, 1 = 24bpps -$INT_Panel_Color_Depth10 1 bit ; Panel #10, 0 = 18bpps, 1 = 24bpps -$INT_Panel_Color_Depth11 1 bit ; Panel #11, 0 = 18bpps, 1 = 24bpps -$INT_Panel_Color_Depth12 1 bit ; Panel #12, 0 = 18bpps, 1 = 24bpps -$INT_Panel_Color_Depth13 1 bit ; Panel #13, 0 = 18bpps, 1 = 24bpps -$INT_Panel_Color_Depth14 1 bit ; Panel #14, 0 = 18bpps, 1 = 24bpps -$INT_Panel_Color_Depth15 1 bit ; Panel #15, 0 = 18bpps, 1 = 24bpps -$INT_Panel_Color_Depth16 1 bit ; Panel #16, 0 = 18bpps, 1 = 24bpps - -$DPS_Panel_Type_01 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_02 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_03 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_04 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_05 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_06 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_07 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_08 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_09 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_10 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_11 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_12 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_13 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_14 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_15 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless -$DPS_Panel_Type_16 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless - -$Blt_Control_01 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_02 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_03 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_04 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_05 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_06 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_07 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_08 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_09 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_10 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_11 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_12 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_13 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_14 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_15 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight -$Blt_Control_16 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight - - -;============================================================================== -; Block 41 - Flat Panel Data Tables Pointers -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; SKIP block ID and size -SKIP 1 byte ; Skip entries number byte - -$LVDS_Tbl_Ptr_01 2 bytes -$LVDS_Tbl_Size_01 1 byte -$LVDS_Tbl_01, $LVDS_Tbl_Ptr_01, $LVDS_Tbl_Size_01, Offset 4 bytes -$DVO_Tbl_Ptr_01 2 bytes -$DVO_Tbl_Size_01 1 byte -$DVO_Tbl_01, $DVO_Tbl_Ptr_01, $DVO_Tbl_Size_01, Offset 0 byte -$LVDS_PnP_ID_Ptr_01 2 bytes -$LVDS_PnP_ID_Size_01 1 byte -$LVDS_PnP_ID_01, $LVDS_PnP_ID_Ptr_01, $LVDS_PnP_ID_Size_01, Offset 0 byte - -$LVDS_Tbl_Ptr_02 2 bytes -$LVDS_Tbl_Size_02 1 byte -$LVDS_Tbl_02, $LVDS_Tbl_Ptr_02, $LVDS_Tbl_Size_02, Offset 4 bytes -$DVO_Tbl_Ptr_02 2 bytes -$DVO_Tbl_Size_02 1 byte -$DVO_Tbl_02, $DVO_Tbl_Ptr_02, $DVO_Tbl_Size_02, Offset 0 byte -$LVDS_PnP_ID_Ptr_02 2 bytes -$LVDS_PnP_ID_Size_02 1 byte -$LVDS_PnP_ID_02, $LVDS_PnP_ID_Ptr_02, $LVDS_PnP_ID_Size_02, Offset 0 byte - -$LVDS_Tbl_Ptr_03 2 bytes -$LVDS_Tbl_Size_03 1 byte -$LVDS_Tbl_03, $LVDS_Tbl_Ptr_03, $LVDS_Tbl_Size_03, Offset 4 bytes -$DVO_Tbl_Ptr_03 2 bytes -$DVO_Tbl_Size_03 1 byte -$DVO_Tbl_03, $DVO_Tbl_Ptr_03, $DVO_Tbl_Size_03, Offset 0 byte -$LVDS_PnP_ID_Ptr_03 2 bytes -$LVDS_PnP_ID_Size_03 1 byte -$LVDS_PnP_ID_03, $LVDS_PnP_ID_Ptr_03, $LVDS_PnP_ID_Size_03, Offset 0 byte - -$LVDS_Tbl_Ptr_04 2 bytes -$LVDS_Tbl_Size_04 1 byte -$LVDS_Tbl_04, $LVDS_Tbl_Ptr_04, $LVDS_Tbl_Size_04, Offset 4 bytes -$DVO_Tbl_Ptr_04 2 bytes -$DVO_Tbl_Size_04 1 byte -$DVO_Tbl_04, $DVO_Tbl_Ptr_04, $DVO_Tbl_Size_04, Offset 0 byte -$LVDS_PnP_ID_Ptr_04 2 bytes -$LVDS_PnP_ID_Size_04 1 byte -$LVDS_PnP_ID_04, $LVDS_PnP_ID_Ptr_04, $LVDS_PnP_ID_Size_04, Offset 0 byte - -$LVDS_Tbl_Ptr_05 2 bytes -$LVDS_Tbl_Size_05 1 byte -$LVDS_Tbl_05, $LVDS_Tbl_Ptr_05, $LVDS_Tbl_Size_05, Offset 4 bytes -$DVO_Tbl_Ptr_05 2 bytes -$DVO_Tbl_Size_05 1 byte -$DVO_Tbl_05, $DVO_Tbl_Ptr_05, $DVO_Tbl_Size_05, Offset 0 byte -$LVDS_PnP_ID_Ptr_05 2 bytes -$LVDS_PnP_ID_Size_05 1 byte -$LVDS_PnP_ID_05, $LVDS_PnP_ID_Ptr_05, $LVDS_PnP_ID_Size_05, Offset 0 byte - -$LVDS_Tbl_Ptr_06 2 bytes -$LVDS_Tbl_Size_06 1 byte -$LVDS_Tbl_06, $LVDS_Tbl_Ptr_06, $LVDS_Tbl_Size_06, Offset 4 bytes -$DVO_Tbl_Ptr_06 2 bytes -$DVO_Tbl_Size_06 1 byte -$DVO_Tbl_06, $DVO_Tbl_Ptr_06, $DVO_Tbl_Size_06, Offset 0 byte -$LVDS_PnP_ID_Ptr_06 2 bytes -$LVDS_PnP_ID_Size_06 1 byte -$LVDS_PnP_ID_06, $LVDS_PnP_ID_Ptr_06, $LVDS_PnP_ID_Size_06, Offset 0 byte - -$LVDS_Tbl_Ptr_07 2 bytes -$LVDS_Tbl_Size_07 1 byte -$LVDS_Tbl_07, $LVDS_Tbl_Ptr_07, $LVDS_Tbl_Size_07, Offset 4 bytes -$DVO_Tbl_Ptr_07 2 bytes -$DVO_Tbl_Size_07 1 byte -$DVO_Tbl_07, $DVO_Tbl_Ptr_07, $DVO_Tbl_Size_07, Offset 0 byte -$LVDS_PnP_ID_Ptr_07 2 bytes -$LVDS_PnP_ID_Size_07 1 byte -$LVDS_PnP_ID_07, $LVDS_PnP_ID_Ptr_07, $LVDS_PnP_ID_Size_07, Offset 0 byte - -$LVDS_Tbl_Ptr_08 2 bytes -$LVDS_Tbl_Size_08 1 byte -$LVDS_Tbl_08, $LVDS_Tbl_Ptr_08, $LVDS_Tbl_Size_08, Offset 4 bytes -$DVO_Tbl_Ptr_08 2 bytes -$DVO_Tbl_Size_08 1 byte -$DVO_Tbl_08, $DVO_Tbl_Ptr_08, $DVO_Tbl_Size_08, Offset 0 byte -$LVDS_PnP_ID_Ptr_08 2 bytes -$LVDS_PnP_ID_Size_08 1 byte -$LVDS_PnP_ID_08, $LVDS_PnP_ID_Ptr_08, $LVDS_PnP_ID_Size_08, Offset 0 byte - -$LVDS_Tbl_Ptr_09 2 bytes -$LVDS_Tbl_Size_09 1 byte -$LVDS_Tbl_09, $LVDS_Tbl_Ptr_09, $LVDS_Tbl_Size_09, Offset 4 bytes -$DVO_Tbl_Ptr_09 2 bytes -$DVO_Tbl_Size_09 1 byte -$DVO_Tbl_09, $DVO_Tbl_Ptr_09, $DVO_Tbl_Size_09, Offset 0 byte -$LVDS_PnP_ID_Ptr_09 2 bytes -$LVDS_PnP_ID_Size_09 1 byte -$LVDS_PnP_ID_09, $LVDS_PnP_ID_Ptr_09, $LVDS_PnP_ID_Size_09, Offset 0 byte - -$LVDS_Tbl_Ptr_10 2 bytes -$LVDS_Tbl_Size_10 1 byte -$LVDS_Tbl_10, $LVDS_Tbl_Ptr_10, $LVDS_Tbl_Size_10, Offset 4 bytes -$DVO_Tbl_Ptr_10 2 bytes -$DVO_Tbl_Size_10 1 byte -$DVO_Tbl_10, $DVO_Tbl_Ptr_10, $DVO_Tbl_Size_10, Offset 0 byte -$LVDS_PnP_ID_Ptr_10 2 bytes -$LVDS_PnP_ID_Size_10 1 byte -$LVDS_PnP_ID_10, $LVDS_PnP_ID_Ptr_10, $LVDS_PnP_ID_Size_10, Offset 0 byte - -$LVDS_Tbl_Ptr_11 2 bytes -$LVDS_Tbl_Size_11 1 byte -$LVDS_Tbl_11, $LVDS_Tbl_Ptr_11, $LVDS_Tbl_Size_11, Offset 4 bytes -$DVO_Tbl_Ptr_11 2 bytes -$DVO_Tbl_Size_11 1 byte -$DVO_Tbl_11, $DVO_Tbl_Ptr_11, $DVO_Tbl_Size_11, Offset 0 byte -$LVDS_PnP_ID_Ptr_11 2 bytes -$LVDS_PnP_ID_Size_11 1 byte -$LVDS_PnP_ID_11, $LVDS_PnP_ID_Ptr_11, $LVDS_PnP_ID_Size_11, Offset 0 byte - -$LVDS_Tbl_Ptr_12 2 bytes -$LVDS_Tbl_Size_12 1 byte -$LVDS_Tbl_12, $LVDS_Tbl_Ptr_12, $LVDS_Tbl_Size_12, Offset 4 bytes -$DVO_Tbl_Ptr_12 2 bytes -$DVO_Tbl_Size_12 1 byte -$DVO_Tbl_12, $DVO_Tbl_Ptr_12, $DVO_Tbl_Size_12, Offset 0 byte -$LVDS_PnP_ID_Ptr_12 2 bytes -$LVDS_PnP_ID_Size_12 1 byte -$LVDS_PnP_ID_12, $LVDS_PnP_ID_Ptr_12, $LVDS_PnP_ID_Size_12, Offset 0 byte - -$LVDS_Tbl_Ptr_13 2 bytes -$LVDS_Tbl_Size_13 1 byte -$LVDS_Tbl_13, $LVDS_Tbl_Ptr_13, $LVDS_Tbl_Size_13, Offset 4 bytes -$DVO_Tbl_Ptr_13 2 bytes -$DVO_Tbl_Size_13 1 byte -$DVO_Tbl_13, $DVO_Tbl_Ptr_13, $DVO_Tbl_Size_13, Offset 0 byte -$LVDS_PnP_ID_Ptr_13 2 bytes -$LVDS_PnP_ID_Size_13 1 byte -$LVDS_PnP_ID_13, $LVDS_PnP_ID_Ptr_13, $LVDS_PnP_ID_Size_13, Offset 0 byte - -$LVDS_Tbl_Ptr_14 2 bytes -$LVDS_Tbl_Size_14 1 byte -$LVDS_Tbl_14, $LVDS_Tbl_Ptr_14, $LVDS_Tbl_Size_14, Offset 4 bytes -$DVO_Tbl_Ptr_14 2 bytes -$DVO_Tbl_Size_14 1 byte -$DVO_Tbl_14, $DVO_Tbl_Ptr_14, $DVO_Tbl_Size_14, Offset 0 byte -$LVDS_PnP_ID_Ptr_14 2 bytes -$LVDS_PnP_ID_Size_14 1 byte -$LVDS_PnP_ID_14, $LVDS_PnP_ID_Ptr_14, $LVDS_PnP_ID_Size_14, Offset 0 byte - -$LVDS_Tbl_Ptr_15 2 bytes -$LVDS_Tbl_Size_15 1 byte -$LVDS_Tbl_15, $LVDS_Tbl_Ptr_15, $LVDS_Tbl_Size_15, Offset 4 bytes -$DVO_Tbl_Ptr_15 2 bytes -$DVO_Tbl_Size_15 1 byte -$DVO_Tbl_15, $DVO_Tbl_Ptr_15, $DVO_Tbl_Size_15, Offset 0 byte -$LVDS_PnP_ID_Ptr_15 2 bytes -$LVDS_PnP_ID_Size_15 1 byte -$LVDS_PnP_ID_15, $LVDS_PnP_ID_Ptr_15, $LVDS_PnP_ID_Size_15, Offset 0 byte - -$LVDS_Tbl_Ptr_16 2 bytes -$LVDS_Tbl_Size_16 1 byte -$LVDS_Tbl_16, $LVDS_Tbl_Ptr_16, $LVDS_Tbl_Size_16, Offset 4 bytes -$DVO_Tbl_Ptr_16 2 bytes -$DVO_Tbl_Size_16 1 byte -$DVO_Tbl_16, $DVO_Tbl_Ptr_16, $DVO_Tbl_Size_16, Offset 0 byte -$LVDS_PnP_ID_Ptr_16 2 bytes -$LVDS_PnP_ID_Size_16 1 byte -$LVDS_PnP_ID_16, $LVDS_PnP_ID_Ptr_16, $LVDS_PnP_ID_Size_16, Offset 0 byte - -SKIP 2 bytes ;LfpPanelNameTable Offset -SKIP 1 byte ;LfpPanelName Length - - - -;============================================================================== -; Block 42 - Flat Panel Data Tables -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size - - ; Flat Panel #1 - -$Panel_Width_01 2 bytes ; Panel Width -$Panel_Height_01 2 bytes ; Panel Height - -SKIP 4 bytes ;address-0x61180 or 0x0E1180 (for ILM) - Port control -SKIP 3 bytes ; bits[23:0] -SKIP 1 bit ; bit[24] -$Enable_Dither01 1 bit ; Panel #01, 0=No, 1=Yes -SKIP 6 bits ; bits[31:26] -ALIGN - -SKIP 4 bytes ; address-0x61208 or 0x0C7208 (for ILM) - Panel power on sequencing -$Power_On_Backlight_Enable_Delay_01 13 bits ; Power on Backlight Enable delay -SKIP 3 bits ; bits[15:13] -$PowerUpDelay_01 13 bits ; Power up delay -SKIP 3 bits ; bits[31:29] -ALIGN - -SKIP 4 bytes ; address-0x6120C or 0x0C720C (for ILM) -Panel Power off sequencing -$Power_Backlight_Off_Power_Down_Delay_01 13 bits ;Backlight off power down delay -SKIP 3 bits ; bits[15:13] -$PowerDownDelay_01 13 bits ; Power down delay -SKIP 3 bits ; bits[31:29] -ALIGN - -SKIP 4 bytes ;address-0x61210h or 0x0C7210 (for ILM) -Panel power cycle delay and reference divider -$PowerCycleDelay_01 5 bits ; Power Cycle delay -SKIP 3 bits ; bits[5:7] -ALIGN -SKIP 3 bytes - -SKIP 2 bytes ; 2 bytes at the end - -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - - ; Flat Panel #2 - -$Panel_Width_02 2 bytes ; Panel Width -$Panel_Height_02 2 bytes ; Panel Height - -SKIP 4 bytes ;address-0x61180 or 0x0E1180 (for ILM) - Port control -SKIP 3 bytes ; bits[23:0] -SKIP 1 bit ; bit[24] -$Enable_Dither02 1 bit ; Panel #02, 0=No, 1=Yes -SKIP 6 bits ; bits[31:26] -ALIGN - -SKIP 4 bytes ;address-0x61208 or 0x0C7208 (for ILM) - Panel power on sequencing -$Power_On_Backlight_Enable_Delay_02 13 bits ; Power on backlight enable delay -SKIP 3 bits ; bits[15:13] -$PowerUpDelay_02 13 bits ; Power up delay -SKIP 3 bits ; bits[31:29] -ALIGN - -SKIP 4 bytes ;address-0x6120C or 0x0C720C (for ILM)-Panel Power off sequencing -$Power_Backlight_Off_Power_Down_Delay_02 13 bits ; Backlight off power down delay -SKIP 3 bits ; bits[15:13] -$PowerDownDelay_02 13 bits ; Power down delay -SKIP 3 bits ; bits[31:29] -ALIGN - -SKIP 4 bytes ;address-0x61210h or 0x0C7210 (for ILM)-Panel power cycle delay and reference divider -$PowerCycleDelay_02 5 bits ; Power Cycle delay -SKIP 3 bits ; bits[5:7] -SKIP 3 bytes - -SKIP 2 bytes ; 2 bytes at the end -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - - ; Flat Panel #3 - -$Panel_Width_03 2 bytes ; Panel Width -$Panel_Height_03 2 bytes ; Panel Height -SKIP 4 bytes ;address-0x61180 or 0x0E1180 (for ILM) - Port control -SKIP 3 bytes ; bits[23:0] -SKIP 1 bit ; bit[24] -$Enable_Dither03 1 bit ; Panel #03, 0=No, 1=Yes -SKIP 6 bits ; bits[31:26] -ALIGN - -SKIP 4 bytes ;address-0x61208 or 0x0C7208 (for ILM) - Panel power on sequencing -$Power_On_Backlight_Enable_Delay_03 13 bits ; Power on backlight enable delay -SKIP 3 bits ; bits[15:13] -$PowerUpDelay_03 13 bits ; Power up delay -SKIP 3 bits ; bits[31:29] -ALIGN - -SKIP 4 bytes ;address-0x6120C or 0x0C720C (for ILM)-Panel Power off sequencing -$Power_Backlight_Off_Power_Down_Delay_03 13 bits ; Backlight off power down delay -SKIP 3 bits ; bits[15:13] -$PowerDownDelay_03 13 bits ; Power down delay -SKIP 3 bits ; bits[31:29] -ALIGN - -SKIP 4 bytes ;aaddress-0x61210h or 0x0C7210 (for ILM)-Panel power cycle delay and reference divider -$PowerCycleDelay_03 5 bits ; Power Cycle delay -SKIP 3 bits ; bits[5:7] -SKIP 3 bytes - -SKIP 2 bytes ; 2 bytes at the end -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - - ; Flat Panel #4 - -$Panel_Width_04 2 bytes ; Panel Width -$Panel_Height_04 2 bytes ; Panel Height -SKIP 4 bytes ;address-0x61180 or 0x0E1180 (for ILM) - Port control -SKIP 3 bytes ; bits[23:0] -SKIP 1 bit ; bit[24] -$Enable_Dither04 1 bit ; Panel #04, 0=No, 1=Yes -SKIP 6 bits ; bits[31:26] -ALIGN - -SKIP 4 bytes ;address-0x61208 or 0x0C7208 (for ILM) - Panel power on sequencing -$Power_On_Backlight_Enable_Delay_04 13 bits ; Power on backlight enable delay -SKIP 3 bits ; bits[15:13] -$PowerUpDelay_04 13 bits ; Power up delay -SKIP 3 bits ; bits[31:29] -ALIGN - -SKIP 4 bytes ;address-0x6120C or 0x0C720C (for ILM)-Panel Power off sequencing -$Power_Backlight_Off_Power_Down_Delay_04 13 bits ; Backlight off power down delay -SKIP 3 bits ; bits[15:13] -$PowerDownDelay_04 13 bits ; Power down delay -SKIP 3 bits ; bits[31:29] -ALIGN - -SKIP 4 bytes ;address-0x61210h or 0x0C7210 (for ILM)-Panel power cycle delay and reference divider -$PowerCycleDelay_04 5 bits ; Power Cycle delay -SKIP 3 bits ; bits[5:7] -SKIP 3 bytes - -SKIP 2 bytes ; 2 bytes at the end -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - - ; Flat Panel #5 - -$Panel_Width_05 2 bytes ; Panel Width -$Panel_Height_05 2 bytes ; Panel Height -SKIP 4 bytes ;address-0x61180 or 0x0E1180 (for ILM) - Port control -SKIP 3 bytes ; bits[23:0] -SKIP 1 bit ; bit[24] -$Enable_Dither05 1 bit ; Panel #05, 0=No, 1=Yes -SKIP 6 bits ; bits[31:26] -ALIGN - -SKIP 4 bytes ;address-0x61208 or 0x0C7208 (for ILM) - Panel power on sequencing -$Power_On_Backlight_Enable_Delay_05 13 bits ; Power on backlight enable delay -SKIP 3 bits ; bits[15:13] -$PowerUpDelay_05 13 bits ; Power up delay -SKIP 3 bits ; bits[31:29] -ALIGN - -SKIP 4 bytes ;address-0x6120C or 0x0C720C (for ILM)-Panel Power off sequencing -$Power_Backlight_Off_Power_Down_Delay_05 13 bits ; Backlight off power down delay -SKIP 3 bits ; bits[15:13] -$PowerDownDelay_05 13 bits ; Power down delay -SKIP 3 bits ; bits[31:29] -ALIGN - -SKIP 4 bytes ;address-0x61210h or 0x0C7210 (for ILM)-Panel power cycle delay and reference divider -$PowerCycleDelay_05 5 bits ; Power Cycle delay -SKIP 3 bits ; bits[5:7] -SKIP 3 bytes - -SKIP 2 bytes ; 2 bytes at the end -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - - ; Flat Panel #6 - -$Panel_Width_06 2 bytes ; Panel Width -$Panel_Height_06 2 bytes ; Panel Height -SKIP 4 bytes ;address-0x61180 or 0x0E1180 (for ILM) - Port control -SKIP 3 bytes ; bits[23:0] -SKIP 1 bit ; bit[24] -$Enable_Dither06 1 bit ; Panel #06, 0=No, 1=Yes -SKIP 6 bits ; bits[31:26] -ALIGN - -SKIP 4 bytes ;address-0x61208 or 0x0C7208 (for ILM) - Panel power on sequencing -$Power_On_Backlight_Enable_Delay_06 13 bits ; Power on backlight enable delay -SKIP 3 bits ; bits[15:13] -$PowerUpDelay_06 13 bits ; Power up delay -SKIP 3 bits ; bits[31:29] -ALIGN - -SKIP 4 bytes ;address-0x6120C or 0x0C720C (for ILM)-Panel Power off sequencing -$Power_Backlight_Off_Power_Down_Delay_06 13 bits ; Backlight off power down delay -SKIP 3 bits ; bits[15:13] -$PowerDownDelay_06 13 bits ; Power down delay -SKIP 3 bits ; bits[31:29] -ALIGN - -SKIP 4 bytes ;address-0x61210h or 0x0C7210 (for ILM)-Panel power cycle delay and reference divider -$PowerCycleDelay_06 5 bits ; Power Cycle delay -SKIP 3 bits ; bits[5:7] -SKIP 3 bytes - -SKIP 2 bytes ; 2 bytes at the end -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - - ; Flat Panel #7 - -$Panel_Width_07 2 bytes ; Panel Width -$Panel_Height_07 2 bytes ; Panel Height -SKIP 4 bytes ;address-0x61180 or 0x0E1180 (for ILM) - Port control -SKIP 3 bytes ; bits[23:0] -SKIP 1 bit ; bit[24] -$Enable_Dither07 1 bit ; Panel #07, 0=No, 1=Yes -SKIP 6 bits ; bits[31:26] -ALIGN - -SKIP 4 bytes ;address-0x61208 or 0x0C7208 (for ILM) - Panel power on sequencing -$Power_On_Backlight_Enable_Delay_07 13 bits ; Power on Backlight enable delay delay -SKIP 3 bits ; bits[15:13] -$PowerUpDelay_07 13 bits ; Power up delay -SKIP 3 bits ; bits[31:29] -ALIGN - -SKIP 4 bytes ;address-0x6120C or 0x0C720C (for ILM)-Panel Power off sequencing -$Power_Backlight_Off_Power_Down_Delay_07 13 bits ; Backlight off delay power down delay -SKIP 3 bits ; bits[15:13] -$PowerDownDelay_07 13 bits ; Power down delay -SKIP 3 bits ; bits[31:29] -ALIGN - -SKIP 4 bytes ;address-0x61210h or 0x0C7210 (for ILM)-Panel power cycle delay and reference divider -$PowerCycleDelay_07 5 bits ; Power Cycle delay -SKIP 3 bits ; bits[5:7] -SKIP 3 bytes - -SKIP 2 bytes ; 2 bytes at the end -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - - ; Flat Panel #8 - -$Panel_Width_08 2 bytes ; Panel Width -$Panel_Height_08 2 bytes ; Panel Height -SKIP 4 bytes ;address-0x61180 or 0x0E1180 (for ILM) - Port control -SKIP 3 bytes ; bits[23:0] -SKIP 1 bit ; bit[24] -$Enable_Dither08 1 bit ; Panel #08, 0=No, 1=Yes -SKIP 6 bits ; bits[31:26] -ALIGN - -SKIP 4 bytes ;address-0x61208 or 0x0C7208 (for ILM) - Panel power on sequencing -$Power_On_Backlight_Enable_Delay_08 13 bits ; Power on backlight enable delay -SKIP 3 bits ; bits[15:13] -$PowerUpDelay_08 13 bits ; Power up delay -SKIP 3 bits ; bits[31:29] -ALIGN - -SKIP 4 bytes ;address-0x6120C or 0x0C720C (for ILM)-Panel Power off sequencing -$Power_Backlight_Off_Power_Down_Delay_08 13 bits ; Backlight off power down delay -SKIP 3 bits ; bits[15:13] -$PowerDownDelay_08 13 bits ; Power down delay -SKIP 3 bits ; bits[31:29] -ALIGN - -SKIP 4 bytes ;address-0x61210h or 0x0C7210 (for ILM)-Panel power cycle delay and reference divider -$PowerCycleDelay_08 5 bits ; Power Cycle delay -SKIP 3 bits ; bits[5:7] -SKIP 3 bytes - -SKIP 2 bytes ; 2 bytes at the end -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - - ; Flat Panel #9 - -$Panel_Width_09 2 bytes ; Panel Width -$Panel_Height_09 2 bytes ; Panel Height -SKIP 4 bytes ;address-0x61180 or 0x0E1180 (for ILM) - Port control -SKIP 3 bytes ; bits[23:0] -SKIP 1 bit ; bit[24] -$Enable_Dither09 1 bit ; Panel #09, 0=No, 1=Yes -SKIP 6 bits ; bits[31:26] -ALIGN - -SKIP 4 bytes ;address-0x61208 or 0x0C7208 (for ILM) - Panel power on sequencing -$Power_On_Backlight_Enable_Delay_09 13 bits ; Power on backlight enable delay -SKIP 3 bits ; bits[15:13] -$PowerUpDelay_09 13 bits ; Power up delay -SKIP 3 bits ; bits[31:29] -ALIGN - -SKIP 4 bytes ;address-0x6120C or 0x0C720C (for ILM)-Panel Power off sequencing -$Power_Backlight_Off_Power_Down_Delay_09 13 bits ;Backlight off power down delay -SKIP 3 bits ; bits[15:13] -$PowerDownDelay_09 13 bits ; Power down delay -SKIP 3 bits ; bits[31:29] -ALIGN - -SKIP 4 bytes ;address-0x61210h or 0x0C7210 (for ILM)-Panel power cycle delay and reference divider -$PowerCycleDelay_09 5 bits ; Power Cycle delay -SKIP 3 bits ; bits[5:7] -SKIP 3 bytes - -SKIP 2 bytes ; 2 bytes at the end -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - - ; Flat Panel #10 - -$Panel_Width_10 2 bytes ; Panel Width -$Panel_Height_10 2 bytes ; Panel Height -SKIP 4 bytes ;address-0x61180 or 0x0E1180 (for ILM) - Port control -SKIP 3 bytes ; bits[23:0] -SKIP 1 bit ; bit[24] -$Enable_Dither10 1 bit ; Panel #10, 0=No, 1=Yes -SKIP 6 bits ; bits[31:26] -ALIGN - -SKIP 4 bytes ;address-0x61208 or 0x0C7208 (for ILM) - Panel power on sequencing -$Power_On_Backlight_Enable_Delay_10 13 bits ; Power on backlight enable delay -SKIP 3 bits ; bits[15:13] -$PowerUpDelay_10 13 bits ; Power up delay -SKIP 3 bits ; bits[31:29] -ALIGN - -SKIP 4 bytes ;address-0x6120C or 0x0C720C (for ILM)-Panel Power off sequencing -$Power_Backlight_Off_Power_Down_Delay_10 13 bits ;Backlight off power down delay -SKIP 3 bits ; bits[15:13] -$PowerDownDelay_10 13 bits ; Power down delay -SKIP 3 bits ; bits[31:29] -ALIGN - -SKIP 4 bytes ;address-0x61210h or 0x0C7210 (for ILM)-Panel power cycle delay and reference divider -$PowerCycleDelay_10 5 bits ; Power Cycle delay -SKIP 3 bits ; bits[5:7] -SKIP 3 bytes - -SKIP 2 bytes ; 2 bytes at the end -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - - ; Flat Panel #11 - -$Panel_Width_11 2 bytes ; Panel Width -$Panel_Height_11 2 bytes ; Panel Height -SKIP 4 bytes ;address-0x61180 or 0x0E1180 (for ILM) - Port control -SKIP 3 bytes ; bits[23:0] -SKIP 1 bit ; bit[24] -$Enable_Dither11 1 bit ; Panel #11, 0=No, 1=Yes -SKIP 6 bits ; bits[31:26] -ALIGN - -SKIP 4 bytes ;address-0x61208 or 0x0C7208 (for ILM) - Panel power on sequencing -$Power_On_Backlight_Enable_Delay_11 13 bits ; Power on backlight enable delay -SKIP 3 bits ; bits[15:13] -$PowerUpDelay_11 13 bits ; Power up delay -SKIP 3 bits ; bits[31:29] -ALIGN - -SKIP 4 bytes ;address-0x6120C or 0x0C720C (for ILM)-Panel Power off sequencing -$Power_Backlight_Off_Power_Down_Delay_11 13 bits ; Backlight off power down delay -SKIP 3 bits ; bits[15:13] -$PowerDownDelay_11 13 bits ; Power down delay -SKIP 3 bits ; bits[31:29] -ALIGN - -SKIP 4 bytes ;address-0x61210h or 0x0C7210 (for ILM)-Panel power cycle delay and reference divider -$PowerCycleDelay_11 5 bits ; Power Cycle delay -SKIP 3 bits ; bits[5:7] -SKIP 3 bytes - -SKIP 2 bytes ; 2 bytes at the end -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - - ; Flat Panel #12 - -$Panel_Width_12 2 bytes ; Panel Width -$Panel_Height_12 2 bytes ; Panel Height -SKIP 4 bytes ;address-0x61180 or 0x0E1180 (for ILM) - Port control -SKIP 3 bytes ; bits[23:0] -SKIP 1 bit ; bit[24] -$Enable_Dither12 1 bit ; Panel #12, 0=No, 1=Yes -SKIP 6 bits ; bits[31:26] -ALIGN - -SKIP 4 bytes ;address-0x61208 or 0x0C7208 (for ILM) - Panel power on sequencing -$Power_On_Backlight_Enable_Delay_12 13 bits ; Powen on backlight enable delay -SKIP 3 bits ; bits[15:13] -$PowerUpDelay_12 13 bits ; Power up delay -SKIP 3 bits ; bits[31:29] -ALIGN - -SKIP 4 bytes ;address-0x6120C or 0x0C720C (for ILM)-Panel Power off sequencing -$Power_Backlight_Off_Power_Down_Delay_12 13 bits ; Backlight off power down delay -SKIP 3 bits ; bits[15:13] -$PowerDownDelay_12 13 bits ; Power down delay -SKIP 3 bits ; bits[31:29] -ALIGN - -SKIP 4 bytes ;address-0x61210h or 0x0C7210 (for ILM)-Panel power cycle delay and reference divider -$PowerCycleDelay_12 5 bits ; Power Cycle delay -SKIP 3 bits ; bits[5:7] -SKIP 3 bytes - -SKIP 2 bytes ; 2 bytes at the end -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - - ; Flat Panel #13 - -$Panel_Width_13 2 bytes ; Panel Width -$Panel_Height_13 2 bytes ; Panel Height -SKIP 4 bytes ;address-0x61180 or 0x0E1180 (for ILM) - Port control -SKIP 3 bytes ; bits[23:0] -SKIP 1 bit ; bit[24] -$Enable_Dither13 1 bit ; Panel #13, 0=No, 1=Yes -SKIP 6 bits ; bits[31:26] -ALIGN - -SKIP 4 bytes ;address-0x61208 or 0x0C7208 (for ILM) - Panel power on sequencing -$Power_On_Backlight_Enable_Delay_13 13 bits ; Power on backlight enable delay -SKIP 3 bits ; bits[15:13] -$PowerUpDelay_13 13 bits ; Power up delay -SKIP 3 bits ; bits[31:29] -ALIGN - -SKIP 4 bytes ;address-0x6120C or 0x0C720C (for ILM)-Panel Power off sequencing -$Power_Backlight_Off_Power_Down_Delay_13 13 bits ;Backlight off power down delay -SKIP 3 bits ; bits[15:13] -$PowerDownDelay_13 13 bits ; Power down delay -SKIP 3 bits ; bits[31:29] -ALIGN - -SKIP 4 bytes ;address-0x61210h or 0x0C7210 (for ILM)-Panel power cycle delay and reference divider -$PowerCycleDelay_13 5 bits ; Power Cycle delay -SKIP 3 bits ; bits[5:7] -SKIP 3 bytes - -SKIP 2 bytes ; 2 bytes at the end -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - - ; Flat Panel #14 - -$Panel_Width_14 2 bytes ; Panel Width -$Panel_Height_14 2 bytes ; Panel Height -SKIP 4 bytes ;address-0x61180 or 0x0E1180 (for ILM) - Port control -SKIP 3 bytes ; bits[23:0] -SKIP 1 bit ; bit[24] -$Enable_Dither14 1 bit ; Panel #14, 0=No, 1=Yes -SKIP 6 bits ; bits[31:26] -ALIGN - -SKIP 4 bytes ;address-0x61208 or 0x0C7208 (for ILM) - Panel power on sequencing -$Power_On_Backlight_Enable_Delay_14 13 bits ; Power on baklight enable delay -SKIP 3 bits ; bits[15:13] -$PowerUpDelay_14 13 bits ; Power up delay -SKIP 3 bits ; bits[31:29] -ALIGN - -SKIP 4 bytes ;address-0x6120C or 0x0C720C (for ILM)-Panel Power off sequencing -$Power_Backlight_Off_Power_Down_Delay_14 13 bits ;Backlight off power down delay -SKIP 3 bits ; bits[15:13] -$PowerDownDelay_14 13 bits ; Power down delay -SKIP 3 bits ; bits[31:29] -ALIGN - -SKIP 4 bytes ;address-0x61210h or 0x0C7210 (for ILM)-Panel power cycle delay and reference divider -$PowerCycleDelay_14 5 bits ; Power Cycle delay -SKIP 3 bits ; bits[5:7] -SKIP 3 bytes - -SKIP 2 bytes ; 2 bytes at the end -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - - ; Flat Panel #15 - -$Panel_Width_15 2 bytes ; Panel Width -$Panel_Height_15 2 bytes ; Panel Height -SKIP 4 bytes ;address-0x61180 or 0x0E1180 (for ILM) - Port control -SKIP 3 bytes ; bits[23:0] -SKIP 1 bit ; bit[24] -$Enable_Dither15 1 bit ; Panel #15, 0=No, 1=Yes -SKIP 6 bits ; bits[31:26] -ALIGN - -SKIP 4 bytes ;address-0x61208 or 0x0C7208 (for ILM) - Panel power on sequencing -$Power_On_Backlight_Enable_Delay_15 13 bits ; Power on backlight enable delay -SKIP 3 bits ; bits[15:13] -$PowerUpDelay_15 13 bits ; Power up delay -SKIP 3 bits ; bits[31:29] -ALIGN - -SKIP 4 bytes ;address-0x6120C or 0x0C720C (for ILM)-Panel Power off sequencing -$Power_Backlight_Off_Power_Down_Delay_15 13 bits ; Backlight off power down delay -SKIP 3 bits ; bits[15:13] -$PowerDownDelay_15 13 bits ; Power down delay -SKIP 3 bits ; bits[31:29] -ALIGN - -SKIP 4 bytes ;address-0x61210h or 0x0C7210 (for ILM)-Panel power cycle delay and reference divider -$PowerCycleDelay_15 5 bits ; Power Cycle delay -SKIP 3 bits ; bits[5:7] -SKIP 3 bytes - -SKIP 2 bytes ; 2 bytes at the end -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - - ; Flat Panel #16 - -$Panel_Width_16 2 bytes ; Panel Width -$Panel_Height_16 2 bytes ; Panel Height -SKIP 4 bytes ;address-0x61180 or 0x0E1180 (for ILM) - Port control -SKIP 3 bytes ; bits[23:0] -SKIP 1 bit ; bit[24] -$Enable_Dither16 1 bit ; Panel #16, 0=No, 1=Yes -SKIP 6 bits ; bits[31:26] -ALIGN - -SKIP 4 bytes ;address-0x61208 or 0x0C7208 (for ILM) - Panel power on sequencing -$Power_On_Backlight_Enable_Delay_16 13 bits ; Power on backlight enable delay -SKIP 3 bits ; bits[15:13] -$PowerUpDelay_16 13 bits ; Power up delay -SKIP 3 bits ; bits[31:29] -ALIGN - -SKIP 4 bytes ;address-0x6120C or 0x0C720C (for ILM)-Panel Power off sequencing -$Power_Backlight_Off_Power_Down_Delay_16 13 bits ; backlight off power down delay -SKIP 3 bits ; bits[15:13] -$PowerDownDelay_16 13 bits ; Power down delay -SKIP 3 bits ; bits[31:29] -ALIGN - -SKIP 4 bytes ;address-0x61210h or 0x0C7210 (for ILM)-Panel power cycle delay and reference divider -$PowerCycleDelay_16 5 bits ; Power cycle delay -SKIP 3 bits ; bits[5:7] -SKIP 3 bytes - -SKIP 2 bytes ; 2 bytes at the end -SKIP 18 bytes ; DTD -SKIP 10 bytes ; PnP ID - -$Panel_Name_01 13 bytes ; LFP Panel Name -$Panel_Name_02 13 bytes ; LFP Panel Name -$Panel_Name_03 13 bytes ; LFP Panel Name -$Panel_Name_04 13 bytes ; LFP Panel Name -$Panel_Name_05 13 bytes ; LFP Panel Name -$Panel_Name_06 13 bytes ; LFP Panel Name -$Panel_Name_07 13 bytes ; LFP Panel Name -$Panel_Name_08 13 bytes ; LFP Panel Name -$Panel_Name_09 13 bytes ; LFP Panel Name -$Panel_Name_10 13 bytes ; LFP Panel Name -$Panel_Name_11 13 bytes ; LFP Panel Name -$Panel_Name_12 13 bytes ; LFP Panel Name -$Panel_Name_13 13 bytes ; LFP Panel Name -$Panel_Name_14 13 bytes ; LFP Panel Name -$Panel_Name_15 13 bytes ; LFP Panel Name -$Panel_Name_16 13 bytes ; LFP Panel Name - -$Enable_Scaling_01 1 bit ; Scaling Enable bit for Panel#1 -$Enable_Scaling_02 1 bit ; Scaling Enable bit for Panel#2 -$Enable_Scaling_03 1 bit ; Scaling Enable bit for Panel#3 -$Enable_Scaling_04 1 bit ; Scaling Enable bit for Panel#4 -$Enable_Scaling_05 1 bit ; Scaling Enable bit for Panel#5 -$Enable_Scaling_06 1 bit ; Scaling Enable bit for Panel#6 -$Enable_Scaling_07 1 bit ; Scaling Enable bit for Panel#7 -$Enable_Scaling_08 1 bit ; Scaling Enable bit for Panel#8 -$Enable_Scaling_09 1 bit ; Scaling Enable bit for Panel#9 -$Enable_Scaling_10 1 bit ; Scaling Enable bit for Panel#10 -$Enable_Scaling_11 1 bit ; Scaling Enable bit for Panel#11 -$Enable_Scaling_12 1 bit ; Scaling Enable bit for Panel#12 -$Enable_Scaling_13 1 bit ; Scaling Enable bit for Panel#13 -$Enable_Scaling_14 1 bit ; Scaling Enable bit for Panel#14 -$Enable_Scaling_15 1 bit ; Scaling Enable bit for Panel#15 -$Enable_Scaling_16 1 bit ; Scaling Enable bit for Panel#16 - -$Seamless_DRRS_Min_RR_01 1 byte ; Seamless DRRS Min Refresh Rate for Panel#1 -$Seamless_DRRS_Min_RR_02 1 byte ; Seamless DRRS Min Refresh Rate for Panel#2 -$Seamless_DRRS_Min_RR_03 1 byte ; Seamless DRRS Min Refresh Rate for Panel#3 -$Seamless_DRRS_Min_RR_04 1 byte ; Seamless DRRS Min Refresh Rate for Panel#4 -$Seamless_DRRS_Min_RR_05 1 byte ; Seamless DRRS Min Refresh Rate for Panel#5 -$Seamless_DRRS_Min_RR_06 1 byte ; Seamless DRRS Min Refresh Rate for Panel#6 -$Seamless_DRRS_Min_RR_07 1 byte ; Seamless DRRS Min Refresh Rate for Panel#7 -$Seamless_DRRS_Min_RR_08 1 byte ; Seamless DRRS Min Refresh Rate for Panel#8 -$Seamless_DRRS_Min_RR_09 1 byte ; Seamless DRRS Min Refresh Rate for Panel#9 -$Seamless_DRRS_Min_RR_10 1 byte ; Seamless DRRS Min Refresh Rate for Panel#10 -$Seamless_DRRS_Min_RR_11 1 byte ; Seamless DRRS Min Refresh Rate for Panel#11 -$Seamless_DRRS_Min_RR_12 1 byte ; Seamless DRRS Min Refresh Rate for Panel#12 -$Seamless_DRRS_Min_RR_13 1 byte ; Seamless DRRS Min Refresh Rate for Panel#13 -$Seamless_DRRS_Min_RR_14 1 byte ; Seamless DRRS Min Refresh Rate for Panel#14 -$Seamless_DRRS_Min_RR_15 1 byte ; Seamless DRRS Min Refresh Rate for Panel#15 -$Seamless_DRRS_Min_RR_16 1 byte ; Seamless DRRS Min Refresh Rate for Panel#16 - - -;============================================================================== -; Block 43 - BLC (Backlight Control) Support -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size -SKIP 1 byte ; Skip row size - - ; Flat Panel #1 -$BLC_Inv_Type_1 2 bits ; BLC inverter type -$BLC_Inv_Polarity_1 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_1 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_1 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_1 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_1 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_1 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_1 1 byte ; I2C inverter command code - - - ; Flat Panel #2 -$BLC_Inv_Type_2 2 bits ; BLC inverter type -$BLC_Inv_Polarity_2 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_2 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_2 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_2 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_2 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_2 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_2 1 byte ; I2C inverter command code - - ; Flat Panel #3 -$BLC_Inv_Type_3 2 bits ; BLC inverter type -$BLC_Inv_Polarity_3 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_3 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_3 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_3 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_3 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_3 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_3 1 byte ; I2C inverter command code - - - ; Flat Panel #4 -$BLC_Inv_Type_4 2 bits ; BLC inverter type -$BLC_Inv_Polarity_4 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_4 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_4 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_4 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_4 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_4 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_4 1 byte ; I2C inverter command code - - ; Flat Panel #5 -$BLC_Inv_Type_5 2 bits ; BLC inverter type -$BLC_Inv_Polarity_5 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_5 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_5 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_5 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_5 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_5 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_5 1 byte ; I2C inverter command code - - - ; Flat Panel #6 -$BLC_Inv_Type_6 2 bits ; BLC inverter type -$BLC_Inv_Polarity_6 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_6 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_6 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_6 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_6 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_6 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_6 1 byte ; I2C inverter command code - - ; Flat Panel #7 -$BLC_Inv_Type_7 2 bits ; BLC inverter type -$BLC_Inv_Polarity_7 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_7 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_7 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_7 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_7 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_7 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_7 1 byte ; I2C inverter command code - - - ; Flat Panel #8 -$BLC_Inv_Type_8 2 bits ; BLC inverter type -$BLC_Inv_Polarity_8 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_8 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_8 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_8 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_8 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_8 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_8 1 byte ; I2C inverter command code - - - ; Flat Panel #9 -$BLC_Inv_Type_9 2 bits ; BLC inverter type -$BLC_Inv_Polarity_9 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_9 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_9 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_9 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_9 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_9 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_9 1 byte ; I2C inverter command code - - ; Flat Panel #10 -$BLC_Inv_Type_10 2 bits ; BLC inverter type -$BLC_Inv_Polarity_10 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_10 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_10 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_10 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_10 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_10 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_10 1 byte ; I2C inverter command code - - - ; Flat Panel #11 -$BLC_Inv_Type_11 2 bits ; BLC inverter type -$BLC_Inv_Polarity_11 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_11 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_11 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_11 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_11 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_11 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_11 1 byte ; I2C inverter command code - - - ; Flat Panel #12 -$BLC_Inv_Type_12 2 bits ; BLC inverter type -$BLC_Inv_Polarity_12 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_12 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_12 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_12 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_12 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_12 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_12 1 byte ; I2C inverter command code - - ; Flat Panel #13 -$BLC_Inv_Type_13 2 bits ; BLC inverter type -$BLC_Inv_Polarity_13 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_13 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_13 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_13 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_13 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_13 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_13 1 byte ; I2C inverter command code - - - ; Flat Panel #14 -$BLC_Inv_Type_14 2 bits ; BLC inverter type -$BLC_Inv_Polarity_14 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_14 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_14 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_14 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_14 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_14 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_14 1 byte ; I2C inverter command code - - - ; Flat Panel #15 -$BLC_Inv_Type_15 2 bits ; BLC inverter type -$BLC_Inv_Polarity_15 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_15 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_15 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_15 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_15 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_15 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_15 1 byte ; I2C inverter command code - - - ; Flat Panel #16 -$BLC_Inv_Type_16 2 bits ; BLC inverter type -$BLC_Inv_Polarity_16 1 bit ; BLC inverter polarity -$BLC_GPIO_Pins_16 3 bits ; BLC inverter GPIO Pins -$BLC_GMBus_Speed_16 2 bits ; BLC inverter GMBus speed -$PWM_Frequency_16 2 bytes ; PWM inverter frequency -$BLC_Min_Brightness_16 1 byte ; Minimum Brightness, 0 - 255 -$BLC_I2C_Addr_16 1 byte ; I2C inverter Slave address -$BLC_Brightness_Cmd_16 1 byte ; I2C inverter command code - -$POST_BL_Brightness_01 1 byte ; Intial brightness value at POST for Flat Panel #1 - $POST_BL_Brightness_02 1 byte ; Intial brightness value at POST for Flat Panel #2 - $POST_BL_Brightness_03 1 byte ; Intial brightness value at POST for Flat Panel #3 - $POST_BL_Brightness_04 1 byte ; Intial brightness value at POST for Flat Panel #4 - $POST_BL_Brightness_05 1 byte ; Intial brightness value at POST for Flat Panel #5 - $POST_BL_Brightness_06 1 byte ; Intial brightness value at POST for Flat Panel #6 - $POST_BL_Brightness_07 1 byte ; Intial brightness value at POST for Flat Panel #7 - $POST_BL_Brightness_08 1 byte ; Intial brightness value at POST for Flat Panel #8 - $POST_BL_Brightness_09 1 byte ; Intial brightness value at POST for Flat Panel #9 - $POST_BL_Brightness_10 1 byte ; Intial brightness value at POST for Flat Panel #10 - $POST_BL_Brightness_11 1 byte ; Intial brightness value at POST for Flat Panel #11 - $POST_BL_Brightness_12 1 byte ; Intial brightness value at POST for Flat Panel #12 - $POST_BL_Brightness_13 1 byte ; Intial brightness value at POST for Flat Panel #13 - $POST_BL_Brightness_14 1 byte ; Intial brightness value at POST for Flat Panel #14 - $POST_BL_Brightness_15 1 byte ; Intial brightness value at POST for Flat Panel #15 - $POST_BL_Brightness_16 1 byte ; Intial brightness value at POST for Flat Panel #16 - - $Lfp_Pwm_Source_Selection_01 4 bits ; Pwm Source Selection for Panel #1 - $Lfp_Pwm_Controller_Selection_01 4 bits ; Pwm Controller Selection for Panel #1 - - $Lfp_Pwm_Source_Selection_02 4 bits ; Pwm Source Selection for Panel #2 - $Lfp_Pwm_Controller_Selection_02 4 bits ; Pwm Controller Selection for Panel #2 - - $Lfp_Pwm_Source_Selection_03 4 bits ; Pwm Source Selection for Panel #3 - $Lfp_Pwm_Controller_Selection_03 4 bits ; Pwm Controller Selection for Panel #3 - - $Lfp_Pwm_Source_Selection_04 4 bits ; Pwm Source Selection for Panel #4 - $Lfp_Pwm_Controller_Selection_04 4 bits ; Pwm Controller Selection for Panel #4 - - $Lfp_Pwm_Source_Selection_05 4 bits ; Pwm Source Selection for Panel #5 - $Lfp_Pwm_Controller_Selection_05 4 bits ; Pwm Controller Selection for Panel #5 - - $Lfp_Pwm_Source_Selection_06 4 bits ; Pwm Source Selection for Panel #6 - $Lfp_Pwm_Controller_Selection_06 4 bits ; Pwm Controller Selection for Panel #6 - - $Lfp_Pwm_Source_Selection_07 4 bits ; Pwm Source Selection for Panel #7 - $Lfp_Pwm_Controller_Selection_07 4 bits ; Pwm Controller Selection for Panel #7 - - $Lfp_Pwm_Source_Selection_08 4 bits ; Pwm Source Selection for Panel #8 - $Lfp_Pwm_Controller_Selection_08 4 bits ; Pwm Controller Selection for Panel #8 - - $Lfp_Pwm_Source_Selection_09 4 bits ; Pwm Source Selection for Panel #9 - $Lfp_Pwm_Controller_Selection_09 4 bits ; Pwm Controller Selection for Panel #9 - - $Lfp_Pwm_Source_Selection_10 4 bits ; Pwm Source Selection for Panel #10 - $Lfp_Pwm_Controller_Selection_10 4 bits ; Pwm Controller Selection for Panel #10 - - $Lfp_Pwm_Source_Selection_11 4 bits ; Pwm Source Selection for Panel #11 - $Lfp_Pwm_Controller_Selection_11 4 bits ; Pwm Controller Selection for Panel #11 - - $Lfp_Pwm_Source_Selection_12 4 bits ; Pwm Source Selection for Panel #12 - $Lfp_Pwm_Controller_Selection_12 4 bits ; Pwm Controller Selection for Panel #12 - - $Lfp_Pwm_Source_Selection_13 4 bits ; Pwm Source Selection for Panel #13 - $Lfp_Pwm_Controller_Selection_13 4 bits ; Pwm Controller Selection for Panel #13 - - $Lfp_Pwm_Source_Selection_14 4 bits ; Pwm Source Selection for Panel #14 - $Lfp_Pwm_Controller_Selection_14 4 bits ; Pwm Controller Selection for Panel #14 - - $Lfp_Pwm_Source_Selection_15 4 bits ; Pwm Source Selection for Panel #15 - $Lfp_Pwm_Controller_Selection_15 4 bits ; Pwm Controller Selection for Panel #15 - - $Lfp_Pwm_Source_Selection_16 4 bits ; Pwm Source Selection for Panel #16 - $Lfp_Pwm_Controller_Selection_16 4 bits ; Pwm Controller Selection for Panel #16 - -;============================================================================== -; Block 44 - BIA (Backlight Image Adaption) Support -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size - -$BIA_Enable 1 bit ; DPST support enable bit -$BIA_Aggress_Level 3 bits ; Power Conservation Preference level -SKIP 3 bits ; Reserved -$ALS_Enable 1 bit ; ALS enable bit -$ALS_Response_Data 20 bytes ; ALS Response Data - - ;============================================================================== - ; Block 46 - Chromaticity Support - ;------------------------------------------------------------------------------ - - SKIP 3 bytes ; Skip block ID and size - - - $Chromacity_Enable_1 1 bit ; enable or disable the chromacity bit - $Override_EDID_Data_1 1 bit ; Override the chromaticity bit - SKIP 6 bits ; Reserved bits - $Red_Green_1 1 byte ; Red/green chormaticity coordinates at 19h - $Blue_White_1 1 byte ; Blue/white chromatiity coordinates at 1Ah - $Red_x_1 1 byte ; Red x coordinate at 1Bh - $Red_y_1 1 byte ; Red y coordinate at 1Ch - $Green_x_1 1 byte ; Green x coordinate at 1Dh - $Green_y_1 1 byte ; Green y ccoordinate at 1Eh - $Blue_x_1 1 byte ; Blue x coordinate at 1Fh - $Blue_y_1 1 byte ; Blue y coordinate at 20h - $White_x_1 1 byte ; White x coordiante at 21h - $White_y_1 1 byte ; White y coordinate at 22h - - $Chromacity_Enable_2 1 bit ; enable or disable the chromacity bit - $Override_EDID_Data_2 1 bit ; Override the chromaticity bit - SKIP 6 bits ; Reserved bits - $Red_Green_2 1 byte ; Red/green chormaticity coordinates at 19h - $Blue_White_2 1 byte ; Blue/white chromatiity coordinates at 1Ah - $Red_x_2 1 byte ; Red x coordinate at 1Bh - $Red_y_2 1 byte ; Red y coordinate at 1Ch - $Green_x_2 1 byte ; Green x coordinate at 1Dh - $Green_y_2 1 byte ; Green y ccoordinate at 1Eh - $Blue_x_2 1 byte ; Blue x coordinate at 1Fh - $Blue_y_2 1 byte ; Blue y coordinate at 20h - $White_x_2 1 byte ; White x coordiante at 21h - $White_y_2 1 byte ; White y coordinate at 22h - - $Chromacity_Enable_3 1 bit ; enable or disable the chromacity bit - $Override_EDID_Data_3 1 bit ; Override the chromaticity bit - SKIP 6 bits ; Reserved bits - $Red_Green_3 1 byte ; Red/green chormaticity coordinates at 19h - $Blue_White_3 1 byte ; Blue/white chromatiity coordinates at 1Ah - $Red_x_3 1 byte ; Red x coordinate at 1Bh - $Red_y_3 1 byte ; Red y coordinate at 1Ch - $Green_x_3 1 byte ; Green x coordinate at 1Dh - $Green_y_3 1 byte ; Green y ccoordinate at 1Eh - $Blue_x_3 1 byte ; Blue x coordinate at 1Fh - $Blue_y_3 1 byte ; Blue y coordinate at 20h - $White_x_3 1 byte ; White x coordiante at 21h - $White_y_3 1 byte ; White y coordinate at 22h - - $Chromacity_Enable_4 1 bit ; enable or disable the chromacity bit - $Override_EDID_Data_4 1 bit ; Override the chromaticity bit - SKIP 6 bits ; Reserved bits - $Red_Green_4 1 byte ; Red/green chormaticity coordinates at 19h - $Blue_White_4 1 byte ; Blue/white chromatiity coordinates at 1Ah - $Red_x_4 1 byte ; Red x coordinate at 1Bh - $Red_y_4 1 byte ; Red y coordinate at 1Ch - $Green_x_4 1 byte ; Green x coordinate at 1Dh - $Green_y_4 1 byte ; Green y ccoordinate at 1Eh - $Blue_x_4 1 byte ; Blue x coordinate at 1Fh - $Blue_y_4 1 byte ; Blue y coordinate at 20h - $White_x_4 1 byte ; White x coordiante at 21h - $White_y_4 1 byte ; White y coordinate at 22h - - $Chromacity_Enable_5 1 bit ; enable or disable the chromacity bit - $Override_EDID_Data_5 1 bit ; Override the chromaticity bit - SKIP 6 bits ; Reserved bits - $Red_Green_5 1 byte ; Red/green chormaticity coordinates at 19h - $Blue_White_5 1 byte ; Blue/white chromatiity coordinates at 1Ah - $Red_x_5 1 byte ; Red x coordinate at 1Bh - $Red_y_5 1 byte ; Red y coordinate at 1Ch - $Green_x_5 1 byte ; Green x coordinate at 1Dh - $Green_y_5 1 byte ; Green y ccoordinate at 1Eh - $Blue_x_5 1 byte ; Blue x coordinate at 1Fh - $Blue_y_5 1 byte ; Blue y coordinate at 20h - $White_x_5 1 byte ; White x coordiante at 21h - $White_y_5 1 byte ; White y coordinate at 22h - - $Chromacity_Enable_6 1 bit ; enable or disable the chromacity bit - $Override_EDID_Data_6 1 bit ; Override the chromaticity bit - SKIP 6 bits ; Reserved bits - $Red_Green_6 1 byte ; Red/green chormaticity coordinates at 19h - $Blue_White_6 1 byte ; Blue/white chromatiity coordinates at 1Ah - $Red_x_6 1 byte ; Red x coordinate at 1Bh - $Red_y_6 1 byte ; Red y coordinate at 1Ch - $Green_x_6 1 byte ; Green x coordinate at 1Dh - $Green_y_6 1 byte ; Green y ccoordinate at 1Eh - $Blue_x_6 1 byte ; Blue x coordinate at 1Fh - $Blue_y_6 1 byte ; Blue y coordinate at 20h - $White_x_6 1 byte ; White x coordiante at 21h - $White_y_6 1 byte ; White y coordinate at 22h - - $Chromacity_Enable_7 1 bit ; enable or disable the chromacity bit - $Override_EDID_Data_7 1 bit ; Override the chromaticity bit - SKIP 6 bits ; Reserved bits - $Red_Green_7 1 byte ; Red/green chormaticity coordinates at 19h - $Blue_White_7 1 byte ; Blue/white chromatiity coordinates at 1Ah - $Red_x_7 1 byte ; Red x coordinate at 1Bh - $Red_y_7 1 byte ; Red y coordinate at 1Ch - $Green_x_7 1 byte ; Green x coordinate at 1Dh - $Green_y_7 1 byte ; Green y ccoordinate at 1Eh - $Blue_x_7 1 byte ; Blue x coordinate at 1Fh - $Blue_y_7 1 byte ; Blue y coordinate at 20h - $White_x_7 1 byte ; White x coordiante at 21h - $White_y_7 1 byte ; White y coordinate at 22h - - $Chromacity_Enable_8 1 bit ; enable or disable the chromacity bit - $Override_EDID_Data_8 1 bit ; Override the chromaticity bit - SKIP 6 bits ; Reserved bits - $Red_Green_8 1 byte ; Red/green chormaticity coordinates at 19h - $Blue_White_8 1 byte ; Blue/white chromatiity coordinates at 1Ah - $Red_x_8 1 byte ; Red x coordinate at 1Bh - $Red_y_8 1 byte ; Red y coordinate at 1Ch - $Green_x_8 1 byte ; Green x coordinate at 1Dh - $Green_y_8 1 byte ; Green y ccoordinate at 1Eh - $Blue_x_8 1 byte ; Blue x coordinate at 1Fh - $Blue_y_8 1 byte ; Blue y coordinate at 20h - $White_x_8 1 byte ; White x coordiante at 21h - $White_y_8 1 byte ; White y coordinate at 22h - - $Chromacity_Enable_9 1 bit ; enable or disable the chromacity bit - $Override_EDID_Data_9 1 bit ; Override the chromaticity bit - SKIP 6 bits ; Reserved bits - $Red_Green_9 1 byte ; Red/green chormaticity coordinates at 19h - $Blue_White_9 1 byte ; Blue/white chromatiity coordinates at 1Ah - $Red_x_9 1 byte ; Red x coordinate at 1Bh - $Red_y_9 1 byte ; Red y coordinate at 1Ch - $Green_x_9 1 byte ; Green x coordinate at 1Dh - $Green_y_9 1 byte ; Green y ccoordinate at 1Eh - $Blue_x_9 1 byte ; Blue x coordinate at 1Fh - $Blue_y_9 1 byte ; Blue y coordinate at 20h - $White_x_9 1 byte ; White x coordiante at 21h - $White_y_9 1 byte ; White y coordinate at 22h - - $Chromacity_Enable_10 1 bit ; enable or disable the chromacity bit - $Override_EDID_Data_10 1 bit ; Override the chromaticity bit - SKIP 6 bits ; Reserved bits - $Red_Green_10 1 byte ; Red/green chormaticity coordinates at 19h - $Blue_White_10 1 byte ; Blue/white chromatiity coordinates at 1Ah - $Red_x_10 1 byte ; Red x coordinate at 1Bh - $Red_y_10 1 byte ; Red y coordinate at 1Ch - $Green_x_10 1 byte ; Green x coordinate at 1Dh - $Green_y_10 1 byte ; Green y ccoordinate at 1Eh - $Blue_x_10 1 byte ; Blue x coordinate at 1Fh - $Blue_y_10 1 byte ; Blue y coordinate at 20h - $White_x_10 1 byte ; White x coordiante at 21h - $White_y_10 1 byte ; White y coordinate at 22h - - $Chromacity_Enable_11 1 bit ; enable or disable the chromacity bit - $Override_EDID_Data_11 1 bit ; Override the chromaticity bit - SKIP 6 bits ; Reserved bits - $Red_Green_11 1 byte ; Red/green chormaticity coordinates at 19h - $Blue_White_11 1 byte ; Blue/white chromatiity coordinates at 1Ah - $Red_x_11 1 byte ; Red x coordinate at 1Bh - $Red_y_11 1 byte ; Red y coordinate at 1Ch - $Green_x_11 1 byte ; Green x coordinate at 1Dh - $Green_y_11 1 byte ; Green y ccoordinate at 1Eh - $Blue_x_11 1 byte ; Blue x coordinate at 1Fh - $Blue_y_11 1 byte ; Blue y coordinate at 20h - $White_x_11 1 byte ; White x coordiante at 21h - $White_y_11 1 byte ; White y coordinate at 22h - - $Chromacity_Enable_12 1 bit ; enable or disable the chromacity bit - $Override_EDID_Data_12 1 bit ; Override the chromaticity bit - SKIP 6 bits ; Reserved bits - $Red_Green_12 1 byte ; Red/green chormaticity coordinates at 19h - $Blue_White_12 1 byte ; Blue/white chromatiity coordinates at 1Ah - $Red_x_12 1 byte ; Red x coordinate at 1Bh - $Red_y_12 1 byte ; Red y coordinate at 1Ch - $Green_x_12 1 byte ; Green x coordinate at 1Dh - $Green_y_12 1 byte ; Green y ccoordinate at 1Eh - $Blue_x_12 1 byte ; Blue x coordinate at 1Fh - $Blue_y_12 1 byte ; Blue y coordinate at 20h - $White_x_12 1 byte ; White x coordiante at 21h - $White_y_12 1 byte ; White y coordinate at 22h - - $Chromacity_Enable_13 1 bit ; enable or disable the chromacity bit - $Override_EDID_Data_13 1 bit ; Override the chromaticity bit - SKIP 6 bits ; Reserved bits - $Red_Green_13 1 byte ; Red/green chormaticity coordinates at 19h - $Blue_White_13 1 byte ; Blue/white chromatiity coordinates at 1Ah - $Red_x_13 1 byte ; Red x coordinate at 1Bh - $Red_y_13 1 byte ; Red y coordinate at 1Ch - $Green_x_13 1 byte ; Green x coordinate at 1Dh - $Green_y_13 1 byte ; Green y ccoordinate at 1Eh - $Blue_x_13 1 byte ; Blue x coordinate at 1Fh - $Blue_y_13 1 byte ; Blue y coordinate at 20h - $White_x_13 1 byte ; White x coordiante at 21h - $White_y_13 1 byte ; White y coordinate at 22h - - $Chromacity_Enable_14 1 bit ; enable or disable the chromacity bit - $Override_EDID_Data_14 1 bit ; Override the chromaticity bit - SKIP 6 bits ; Reserved bits - $Red_Green_14 1 byte ; Red/green chormaticity coordinates at 19h - $Blue_White_14 1 byte ; Blue/white chromatiity coordinates at 1Ah - $Red_x_14 1 byte ; Red x coordinate at 1Bh - $Red_y_14 1 byte ; Red y coordinate at 1Ch - $Green_x_14 1 byte ; Green x coordinate at 1Dh - $Green_y_14 1 byte ; Green y ccoordinate at 1Eh - $Blue_x_14 1 byte ; Blue x coordinate at 1Fh - $Blue_y_14 1 byte ; Blue y coordinate at 20h - $White_x_14 1 byte ; White x coordiante at 21h - $White_y_14 1 byte ; White y coordinate at 22h - - $Chromacity_Enable_15 1 bit ; enable or disable the chromacity bit - $Override_EDID_Data_15 1 bit ; Override the chromaticity bit - SKIP 6 bits ; Reserved bits - $Red_Green_15 1 byte ; Red/green chormaticity coordinates at 19h - $Blue_White_15 1 byte ; Blue/white chromatiity coordinates at 1Ah - $Red_x_15 1 byte ; Red x coordinate at 1Bh - $Red_y_15 1 byte ; Red y coordinate at 1Ch - $Green_x_15 1 byte ; Green x coordinate at 1Dh - $Green_y_15 1 byte ; Green y ccoordinate at 1Eh - $Blue_x_15 1 byte ; Blue x coordinate at 1Fh - $Blue_y_15 1 byte ; Blue y coordinate at 20h - $White_x_15 1 byte ; White x coordiante at 21h - $White_y_15 1 byte ; White y coordinate at 22h - - - $Chromacity_Enable_16 1 bit ; enable or disable the chromacity bit - $Override_EDID_Data_16 1 bit ; Override the chromaticity bit - SKIP 6 bits ; Reserved bits - $Red_Green_16 1 byte ; Red/green chormaticity coordinates at 19h - $Blue_White_16 1 byte ; Blue/white chromatiity coordinates at 1Ah - $Red_x_16 1 byte ; Red x coordinate at 1Bh - $Red_y_16 1 byte ; Red y coordinate at 1Ch - $Green_x_16 1 byte ; Green x coordinate at 1Dh - $Green_y_16 1 byte ; Green y ccoordinate at 1Eh - $Blue_x_16 1 byte ; Blue x coordinate at 1Fh - $Blue_y_16 1 byte ; Blue y coordinate at 20h - $White_x_16 1 byte ; White x coordiante at 21h - $White_y_16 1 byte ; White y coordinate at 22h - -;============================================================================== -; Block 51 - Fixed Mode -;------------------------------------------------------------------------------ - -SKIP 3 bytes ; Skip block ID and size -$Feature_Enable 1 byte ; enable or disable the feature -$X_res 4 bytes ; X resolution -$Y_res 4 bytes ; Y resolution - -;============================================================================== -; Block 52 - MIPI DSI Configuration Block -;----------------------------------------------------------------------------- - -$MIPI_DSI_CONF_BLOCKID 1 byte -$MIPI_DSI_CONF_BLOCKSIZE 2 bytes - - ;MIPI DSI CONF Panel#1 -$PanelIdentifier_1 2 bytes ;PanelIdentifier - -$Dithering_1 1 bit ;GeneralMIPIParams -SKIP 1 bit -$Panel_Type_1 1 bit -$MIPI_DSI_Panel_Architecture_Type_1 2 bits -$Video_Command_Mode_1 1 bit -$Packet_Sequence_Video_Mode_1 2 bits -$CABC_Support_1 1 bit -$PmicSocSelection_1 1 bit -$Colour_Format_Video_Mode_1 4 bits -$Panel_Rotation_1 2 bits -$Bta_Disable_1 1 bit -SKIP 15 bits - -$Dual_Link_1 2 bits ;PortDesc -$Number_Of_Lanes_1 2 bits -$Pixel_Overlap_Count_1 3 bits -$RGBFlip_1 1 bit -SKIP 8 bits - -SKIP 16 bits ;DsiControllerParams -SKIP 8 bits ;Reserved0 -$RequiredBurstModeRate_1 32 bits ;RequiredBurstModeRate - -$DsiDDRClock_1 4 bytes ;DsiDDRClock - -SKIP 32 bits ;BridgeRefClock - -$EscapeClk_1 2 bits ;EscapeClk -SKIP 6 bits - -$DPhyParamFlag_1 1 bit ;DphyFlags -$EoTpSupport_1 1 bit ;EoTpSupport -$ClockStop_1 1 bit -SKIP 13 bits - -$HsTxTimeOut_1 4 bytes ;HsTxTimeOut -$LpRxTimeOut_1 4 bytes ;LpRxTimeOut -$TurnAroundTimeOut_1 4 bytes ;TurnAroundTimeOut -$DeviceResetTimer_1 4 bytes ;DeviceResetTimer -$MasterInitTimer_1 4 bytes ;MasterInitTimer -$DbiBwTimer_1 32 bits ;DbiBwTimer - -$LpByteClkRegValue_1 32 bits ;LpByteClkRegValue -$DphyParamRegValue_1 32 bits ;DphyParamRegValue -$ClkLaneSwitchingTimeCount_1 32 bits ;ClkLaneSwitchingTimeCount -$HighLowSwitchCount_1 32 bits ;HighLowSwitchCount - -SKIP 32 bits ;Reserved1 -SKIP 32 bits ;Reserved2 -SKIP 32 bits ;Reserved3 -SKIP 32 bits ;Reserved4 -SKIP 32 bits ;Reserved5 -SKIP 32 bits ;Reserved6 - -SKIP 8 bits ;TClkMiss -SKIP 8 bits ;TClkPost -SKIP 8 bits ;Reserved7 -SKIP 8 bits ;TClkPre -$TClkPrepare_1 1 byte ;TClkPrepare -SKIP 8 bits ;TClkSettle -SKIP 8 bits ;TClkTermEn -$TClkTrail_1 1 byte ;TClkTrail -$TClkPrepareTClkZero_1 2 bytes ;TClkPrepareTClkZero -SKIP 8 bits ;Reserved8 -SKIP 8 bits ;TDTermEn -SKIP 8 bits ;TEot -SKIP 8 bits ;THsExit -$THsPrepare_1 1 byte ;THsPrepare -$THsPrepareTHsZero_1 2 bytes ;THsPrepareTHsZero -SKIP 8 bits ;Reserved9 -SKIP 8 bits ;THsSettle -SKIP 8 bits ;THsSkip -$THsTrail_1 8 bits ;THsTrail -SKIP 8 bits ;TInit -SKIP 8 bits ;TLpx -SKIP 8 bits ;Reserved10 -SKIP 16 bits ;Reserved11 - -$PanelEnable_1 1 bit ;PanelEnable -SKIP 7 bits -$BkltEnable_1 1 bit ;BkltEnable -SKIP 7 bits -$PWMEnable_1 1 bit ;PWMEnable -SKIP 7 bits -$RstRN_1 1 bit ;RstRN -SKIP 7 bits -$PwrDownR_1 1 bit ;PwrDownR -SKIP 7 bits -$StbyRN_1 1 bit ;StbyRN -SKIP 7 bits - - ;MIPI DSI CONF Panel#2 -$PanelIdentifier_2 2 bytes ;PanelIdentifier - -$Dithering_2 1 bit ;GeneralMIPIParams -SKIP 1 bit -$Panel_Type_2 1 bit -$MIPI_DSI_Panel_Architecture_Type_2 2 bits -$Video_Command_Mode_2 1 bit -$Packet_Sequence_Video_Mode_2 2 bits -$CABC_Support_2 1 bit -$PmicSocSelection_2 1 bit -$Colour_Format_Video_Mode_2 4 bits -$Panel_Rotation_2 2 bits -$Bta_Disable_2 1 bit -SKIP 15 bits - -$Dual_Link_2 2 bits ;PortDesc -$Number_Of_Lanes_2 2 bits -$Pixel_Overlap_Count_2 3 bits -$RGBFlip_2 1 bit -SKIP 8 bits - -SKIP 16 bits ;DsiControllerParams -SKIP 8 bits ;Reserved0 -$RequiredBurstModeRate_2 32 bits ;RequiredBurstModeRate - -$DsiDDRClock_2 4 bytes ;DsiDDRClock - -SKIP 32 bits ;BridgeRefClock - -$EscapeClk_2 2 bits ;EscapeClk -SKIP 6 bits - -$DPhyParamFlag_2 1 bit ;DphyFlags -$EoTpSupport_2 1 bit ;EoTpSupport -$ClockStop_2 1 bit -SKIP 13 bits - -$HsTxTimeOut_2 4 bytes ;HsTxTimeOut -$LpRxTimeOut_2 4 bytes ;LpRxTimeOut -$TurnAroundTimeOut_2 4 bytes ;TurnAroundTimeOut -$DeviceResetTimer_2 4 bytes ;DeviceResetTimer -$MasterInitTimer_2 4 bytes ;MasterInitTimer -$DbiBwTimer_2 32 bits ;DbiBwTimer - -$LpByteClkRegValue_2 32 bits ;LpByteClkRegValue -$DphyParamRegValue_2 32 bits ;DphyParamRegValue -$ClkLaneSwitchingTimeCount_2 32 bits ;ClkLaneSwitchingTimeCount -$HighLowSwitchCount_2 32 bits ;HighLowSwitchCount - -SKIP 32 bits ;Reserved1 -SKIP 32 bits ;Reserved2 -SKIP 32 bits ;Reserved3 -SKIP 32 bits ;Reserved4 -SKIP 32 bits ;Reserved5 -SKIP 32 bits ;Reserved6 - -SKIP 8 bits ;TClkMiss -SKIP 8 bits ;TClkPost -SKIP 8 bits ;Reserved7 -SKIP 8 bits ;TClkPre -$TClkPrepare_2 1 byte ;TClkPrepare -SKIP 8 bits ;TClkSettle -SKIP 8 bits ;TClkTermEn -$TClkTrail_2 1 byte ;TClkTrail -$TClkPrepareTClkZero_2 2 bytes ;TClkPrepareTClkZero -SKIP 8 bits ;Reserved8 -SKIP 8 bits ;TDTermEn -SKIP 8 bits ;TEot -SKIP 8 bits ;THsExit -$THsPrepare_2 1 byte ;THsPrepare -$THsPrepareTHsZero_2 2 bytes ;THsPrepareTHsZero -SKIP 8 bits ;Reserved9 -SKIP 8 bits ;THsSettle -SKIP 8 bits ;THsSkip -$THsTrail_2 8 bits ;THsTrail -SKIP 8 bits ;TInit -SKIP 8 bits ;TLpx -SKIP 8 bits ;Reserved10 -SKIP 16 bits ;Reserved11 - -$PanelEnable_2 1 bit ;PanelEnable -SKIP 7 bits -$BkltEnable_2 1 bit ;BkltEnable -SKIP 7 bits -$PWMEnable_2 1 bit ;PWMEnable -SKIP 7 bits -$RstRN_2 1 bit ;RstRN -SKIP 7 bits -$PwrDownR_2 1 bit ;PwrDownR -SKIP 7 bits -$StbyRN_2 1 bit ;StbyRN -SKIP 7 bits - - ;MIPI DSI CONF Panel#3 -$PanelIdentifier_3 2 bytes ;PanelIdentifier - -$Dithering_3 1 bit ;GeneralMIPIParams -SKIP 1 bit -$Panel_Type_3 1 bit -$MIPI_DSI_Panel_Architecture_Type_3 2 bits -$Video_Command_Mode_3 1 bit -$Packet_Sequence_Video_Mode_3 2 bits -$CABC_Support_3 1 bit -$PmicSocSelection_3 1 bit -$Colour_Format_Video_Mode_3 4 bits -$Panel_Rotation_3 2 bits -$Bta_Disable_3 1 bit -SKIP 15 bits - -$Dual_Link_3 2 bits ;PortDesc -$Number_Of_Lanes_3 2 bits -$Pixel_Overlap_Count_3 3 bits -$RGBFlip_3 1 bit -SKIP 8 bits - -SKIP 16 bits ;DsiControllerParams -SKIP 8 bits ;Reserved0 -$RequiredBurstModeRate_3 32 bits ;RequiredBurstModeRate - -$DsiDDRClock_3 4 bytes ;DsiDDRClock - -SKIP 32 bits ;BridgeRefClock - -$EscapeClk_3 2 bits ;EscapeClk -SKIP 6 bits - -$DPhyParamFlag_3 1 bit ;DphyFlags -$EoTpSupport_3 1 bit ;EoTpSupport -$ClockStop_3 1 bit -SKIP 13 bits - -$HsTxTimeOut_3 4 bytes ;HsTxTimeOut -$LpRxTimeOut_3 4 bytes ;LpRxTimeOut -$TurnAroundTimeOut_3 4 bytes ;TurnAroundTimeOut -$DeviceResetTimer_3 4 bytes ;DeviceResetTimer -$MasterInitTimer_3 4 bytes ;MasterInitTimer -$DbiBwTimer_3 32 bits ;DbiBwTimer - -$LpByteClkRegValue_3 32 bits ;LpByteClkRegValue -$DphyParamRegValue_3 32 bits ;DphyParamRegValue -$ClkLaneSwitchingTimeCount_3 32 bits ;ClkLaneSwitchingTimeCount -$HighLowSwitchCount_3 32 bits ;HighLowSwitchCount - -SKIP 32 bits ;Reserved1 -SKIP 32 bits ;Reserved2 -SKIP 32 bits ;Reserved3 -SKIP 32 bits ;Reserved4 -SKIP 32 bits ;Reserved5 -SKIP 32 bits ;Reserved6 - -SKIP 8 bits ;TClkMiss -SKIP 8 bits ;TClkPost -SKIP 8 bits ;Reserved7 -SKIP 8 bits ;TClkPre -$TClkPrepare_3 1 byte ;TClkPrepare -SKIP 8 bits ;TClkSettle -SKIP 8 bits ;TClkTermEn -$TClkTrail_3 1 byte ;TClkTrail -$TClkPrepareTClkZero_3 2 bytes ;TClkPrepareTClkZero -SKIP 8 bits ;Reserved8 -SKIP 8 bits ;TDTermEn -SKIP 8 bits ;TEot -SKIP 8 bits ;THsExit -$THsPrepare_3 1 byte ;THsPrepare -$THsPrepareTHsZero_3 2 bytes ;THsPrepareTHsZero -SKIP 8 bits ;Reserved9 -SKIP 8 bits ;THsSettle -SKIP 8 bits ;THsSkip -$THsTrail_3 8 bits ;THsTrail -SKIP 8 bits ;TInit -SKIP 8 bits ;TLpx -SKIP 8 bits ;Reserved10 -SKIP 16 bits ;Reserved11 - -$PanelEnable_3 1 bit ;PanelEnable -SKIP 7 bits -$BkltEnable_3 1 bit ;BkltEnable -SKIP 7 bits -$PWMEnable_3 1 bit ;PWMEnable -SKIP 7 bits -$RstRN_3 1 bit ;RstRN -SKIP 7 bits -$PwrDownR_3 1 bit ;PwrDownR -SKIP 7 bits -$StbyRN_3 1 bit ;StbyRN -SKIP 7 bits - - ;MIPI DSI CONF Panel#4 -$PanelIdentifier_4 2 bytes ;PanelIdentifier - -$Dithering_4 1 bit ;GeneralMIPIParams -SKIP 1 bit -$Panel_Type_4 1 bit -$MIPI_DSI_Panel_Architecture_Type_4 2 bits -$Video_Command_Mode_4 1 bit -$Packet_Sequence_Video_Mode_4 2 bits -$CABC_Support_4 1 bit -$PmicSocSelection_4 1 bit -$Colour_Format_Video_Mode_4 4 bits -$Panel_Rotation_4 2 bits -$Bta_Disable_4 1 bit -SKIP 15 bits - -$Dual_Link_4 2 bits ;PortDesc -$Number_Of_Lanes_4 2 bits -$Pixel_Overlap_Count_4 3 bits -$RGBFlip_4 1 bit -SKIP 8 bits - -SKIP 16 bits ;DsiControllerParams -SKIP 8 bits ;Reserved0 -$RequiredBurstModeRate_4 32 bits ;RequiredBurstModeRate - -$DsiDDRClock_4 4 bytes ;DsiDDRClock - -SKIP 32 bits ;BridgeRefClock - -$EscapeClk_4 2 bits ;EscapeClk -SKIP 6 bits - -$DPhyParamFlag_4 1 bit ;DphyFlags -$EoTpSupport_4 1 bit ;EoTpSupport -$ClockStop_4 1 bit -SKIP 13 bits - -$HsTxTimeOut_4 4 bytes ;HsTxTimeOut -$LpRxTimeOut_4 4 bytes ;LpRxTimeOut -$TurnAroundTimeOut_4 4 bytes ;TurnAroundTimeOut -$DeviceResetTimer_4 4 bytes ;DeviceResetTimer -$MasterInitTimer_4 4 bytes ;MasterInitTimer -$DbiBwTimer_4 32 bits ;DbiBwTimer - -$LpByteClkRegValue_4 32 bits ;LpByteClkRegValue -$DphyParamRegValue_4 32 bits ;DphyParamRegValue -$ClkLaneSwitchingTimeCount_4 32 bits ;ClkLaneSwitchingTimeCount -$HighLowSwitchCount_4 32 bits ;HighLowSwitchCount - -SKIP 32 bits ;Reserved1 -SKIP 32 bits ;Reserved2 -SKIP 32 bits ;Reserved3 -SKIP 32 bits ;Reserved4 -SKIP 32 bits ;Reserved5 -SKIP 32 bits ;Reserved6 - -SKIP 8 bits ;TClkMiss -SKIP 8 bits ;TClkPost -SKIP 8 bits ;Reserved7 -SKIP 8 bits ;TClkPre -$TClkPrepare_4 1 byte ;TClkPrepare -SKIP 8 bits ;TClkSettle -SKIP 8 bits ;TClkTermEn -$TClkTrail_4 1 byte ;TClkTrail -$TClkPrepareTClkZero_4 2 bytes ;TClkPrepareTClkZero -SKIP 8 bits ;Reserved8 -SKIP 8 bits ;TDTermEn -SKIP 8 bits ;TEot -SKIP 8 bits ;THsExit -$THsPrepare_4 1 byte ;THsPrepare -$THsPrepareTHsZero_4 2 bytes ;THsPrepareTHsZero -SKIP 8 bits ;Reserved9 -SKIP 8 bits ;THsSettle -SKIP 8 bits ;THsSkip -$THsTrail_4 8 bits ;THsTrail -SKIP 8 bits ;TInit -SKIP 8 bits ;TLpx -SKIP 8 bits ;Reserved10 -SKIP 16 bits ;Reserved11 - -$PanelEnable_4 1 bit ;PanelEnable -SKIP 7 bits -$BkltEnable_4 1 bit ;BkltEnable -SKIP 7 bits -$PWMEnable_4 1 bit ;PWMEnable -SKIP 7 bits -$RstRN_4 1 bit ;RstRN -SKIP 7 bits -$PwrDownR_4 1 bit ;PwrDownR -SKIP 7 bits -$StbyRN_4 1 bit ;StbyRN -SKIP 7 bits - - ;MIPI DSI CONF Panel#5 -$PanelIdentifier_5 2 bytes ;PanelIdentifier - -$Dithering_5 1 bit ;GeneralMIPIParams -SKIP 1 bit -$Panel_Type_5 1 bit -$MIPI_DSI_Panel_Architecture_Type_5 2 bits -$Video_Command_Mode_5 1 bit -$Packet_Sequence_Video_Mode_5 2 bits -$CABC_Support_5 1 bit -$PmicSocSelection_5 1 bit -$Colour_Format_Video_Mode_5 4 bits -$Panel_Rotation_5 2 bits -$Bta_Disable_5 1 bit -SKIP 15 bits - -$Dual_Link_5 2 bits ;PortDesc -$Number_Of_Lanes_5 2 bits -$Pixel_Overlap_Count_5 3 bits -$RGBFlip_5 1 bit -SKIP 8 bits - -SKIP 16 bits ;DsiControllerParams -SKIP 8 bits ;Reserved0 -$RequiredBurstModeRate_5 32 bits ;RequiredBurstModeRate - -$DsiDDRClock_5 4 bytes ;DsiDDRClock - -SKIP 32 bits ;BridgeRefClock - -$EscapeClk_5 2 bits ;EscapeClk -SKIP 6 bits - -$DPhyParamFlag_5 1 bit ;DphyFlags -$EoTpSupport_5 1 bit ;EoTpSupport -$ClockStop_5 1 bit -SKIP 13 bits - -$HsTxTimeOut_5 4 bytes ;HsTxTimeOut -$LpRxTimeOut_5 4 bytes ;LpRxTimeOut -$TurnAroundTimeOut_5 4 bytes ;TurnAroundTimeOut -$DeviceResetTimer_5 4 bytes ;DeviceResetTimer -$MasterInitTimer_5 4 bytes ;MasterInitTimer -$DbiBwTimer_5 32 bits ;DbiBwTimer - -$LpByteClkRegValue_5 32 bits ;LpByteClkRegValue -$DphyParamRegValue_5 32 bits ;DphyParamRegValue -$ClkLaneSwitchingTimeCount_5 32 bits ;ClkLaneSwitchingTimeCount -$HighLowSwitchCount_5 32 bits ;HighLowSwitchCount - -SKIP 32 bits ;Reserved1 -SKIP 32 bits ;Reserved2 -SKIP 32 bits ;Reserved3 -SKIP 32 bits ;Reserved4 -SKIP 32 bits ;Reserved5 -SKIP 32 bits ;Reserved6 - -SKIP 8 bits ;TClkMiss -SKIP 8 bits ;TClkPost -SKIP 8 bits ;Reserved7 -SKIP 8 bits ;TClkPre -$TClkPrepare_5 1 byte ;TClkPrepare -SKIP 8 bits ;TClkSettle -SKIP 8 bits ;TClkTermEn -$TClkTrail_5 1 byte ;TClkTrail -$TClkPrepareTClkZero_5 2 bytes ;TClkPrepareTClkZero -SKIP 8 bits ;Reserved8 -SKIP 8 bits ;TDTermEn -SKIP 8 bits ;TEot -SKIP 8 bits ;THsExit -$THsPrepare_5 1 byte ;THsPrepare -$THsPrepareTHsZero_5 2 bytes ;THsPrepareTHsZero -SKIP 8 bits ;Reserved9 -SKIP 8 bits ;THsSettle -SKIP 8 bits ;THsSkip -$THsTrail_5 8 bits ;THsTrail -SKIP 8 bits ;TInit -SKIP 8 bits ;TLpx -SKIP 8 bits ;Reserved10 -SKIP 16 bits ;Reserved11 - -$PanelEnable_5 1 bit ;PanelEnable -SKIP 7 bits -$BkltEnable_5 1 bit ;BkltEnable -SKIP 7 bits -$PWMEnable_5 1 bit ;PWMEnable -SKIP 7 bits -$RstRN_5 1 bit ;RstRN -SKIP 7 bits -$PwrDownR_5 1 bit ;PwrDownR -SKIP 7 bits -$StbyRN_5 1 bit ;StbyRN -SKIP 7 bits - - ;MIPI DSI CONF Panel#6 -$PanelIdentifier_6 2 bytes ;PanelIdentifier - -$Dithering_6 1 bit ;GeneralMIPIParams -SKIP 1 bit -$Panel_Type_6 1 bit -$MIPI_DSI_Panel_Architecture_Type_6 2 bits -$Video_Command_Mode_6 1 bit -$Packet_Sequence_Video_Mode_6 2 bits -$CABC_Support_6 1 bit -$PmicSocSelection_6 1 bit -$Colour_Format_Video_Mode_6 4 bits -$Panel_Rotation_6 2 bits -$Bta_Disable_6 1 bit -SKIP 15 bits - -$Dual_Link_6 2 bits ;PortDesc -$Number_Of_Lanes_6 2 bits -$Pixel_Overlap_Count_6 3 bits -$RGBFlip_6 1 bit -SKIP 8 bits - -SKIP 16 bits ;DsiControllerParams -SKIP 8 bits ;Reserved0 -$RequiredBurstModeRate_6 32 bits ;RequiredBurstModeRate - -$DsiDDRClock_6 4 bytes ;DsiDDRClock - -SKIP 32 bits ;BridgeRefClock - -$EscapeClk_6 2 bits ;EscapeClk -SKIP 6 bits - -$DPhyParamFlag_6 1 bit ;DphyFlags -$EoTpSupport_6 1 bit ;EoTpSupport -$ClockStop_6 1 bit -SKIP 13 bits - -$HsTxTimeOut_6 4 bytes ;HsTxTimeOut -$LpRxTimeOut_6 4 bytes ;LpRxTimeOut -$TurnAroundTimeOut_6 4 bytes ;TurnAroundTimeOut -$DeviceResetTimer_6 4 bytes ;DeviceResetTimer -$MasterInitTimer_6 4 bytes ;MasterInitTimer -$DbiBwTimer_6 32 bits ;DbiBwTimer - -$LpByteClkRegValue_6 32 bits ;LpByteClkRegValue -$DphyParamRegValue_6 32 bits ;DphyParamRegValue -$ClkLaneSwitchingTimeCount_6 32 bits ;ClkLaneSwitchingTimeCount -$HighLowSwitchCount_6 32 bits ;HighLowSwitchCount - -SKIP 32 bits ;Reserved1 -SKIP 32 bits ;Reserved2 -SKIP 32 bits ;Reserved3 -SKIP 32 bits ;Reserved4 -SKIP 32 bits ;Reserved5 -SKIP 32 bits ;Reserved6 - -SKIP 8 bits ;TClkMiss -SKIP 8 bits ;TClkPost -SKIP 8 bits ;Reserved7 -SKIP 8 bits ;TClkPre -$TClkPrepare_6 1 byte ;TClkPrepare -SKIP 8 bits ;TClkSettle -SKIP 8 bits ;TClkTermEn -$TClkTrail_6 1 byte ;TClkTrail -$TClkPrepareTClkZero_6 2 bytes ;TClkPrepareTClkZero -SKIP 8 bits ;Reserved8 -SKIP 8 bits ;TDTermEn -SKIP 8 bits ;TEot -SKIP 8 bits ;THsExit -$THsPrepare_6 1 byte ;THsPrepare -$THsPrepareTHsZero_6 2 bytes ;THsPrepareTHsZero -SKIP 8 bits ;Reserved9 -SKIP 8 bits ;THsSettle -SKIP 8 bits ;THsSkip -$THsTrail_6 8 bits ;THsTrail -SKIP 8 bits ;TInit -SKIP 8 bits ;TLpx -SKIP 8 bits ;Reserved10 -SKIP 16 bits ;Reserved11 - -$PanelEnable_6 1 bit ;PanelEnable -SKIP 7 bits -$BkltEnable_6 1 bit ;BkltEnable -SKIP 7 bits -$PWMEnable_6 1 bit ;PWMEnable -SKIP 7 bits -$RstRN_6 1 bit ;RstRN -SKIP 7 bits -$PwrDownR_6 1 bit ;PwrDownR -SKIP 7 bits -$StbyRN_6 1 bit ;StbyRN -SKIP 7 bits - - ; MIPI DSI PPS for Panel#1 -$PowerUpDelay_1 16 bits -$DataTurnOnToPanelBacklightEnableDelay_1 16 bits -$BacklightOffToDataTurnOffDelay_1 16 bits -$PowerDownDelay_1 16 bits -$PowerCycleDelay_1 16 bits - - ; MIPI DSI PPS for Panel#2 -$PowerUpDelay_2 16 bits -$DataTurnOnToPanelBacklightEnableDelay_2 16 bits -$BacklightOffToDataTurnOffDelay_2 16 bits -$PowerDownDelay_2 16 bits -$PowerCycleDelay_2 16 bits - - ; MIPI DSI PPS for Panel#3 -$PowerUpDelay_3 16 bits -$DataTurnOnToPanelBacklightEnableDelay_3 16 bits -$BacklightOffToDataTurnOffDelay_3 16 bits -$PowerDownDelay_3 16 bits -$PowerCycleDelay_3 16 bits - - ; MIPI DSI PPS for Panel#4 -$PowerUpDelay_4 16 bits -$DataTurnOnToPanelBacklightEnableDelay_4 16 bits -$BacklightOffToDataTurnOffDelay_4 16 bits -$PowerDownDelay_4 16 bits -$PowerCycleDelay_4 16 bits - - ; MIPI DSI PPS for Panel#5 -$PowerUpDelay_5 16 bits -$DataTurnOnToPanelBacklightEnableDelay_5 16 bits -$BacklightOffToDataTurnOffDelay_5 16 bits -$PowerDownDelay_5 16 bits -$PowerCycleDelay_5 16 bits - - ; MIPI DSI PPS for Panel#6 -$PowerUpDelay_6 16 bits -$DataTurnOnToPanelBacklightEnableDelay_6 16 bits -$BacklightOffToDataTurnOffDelay_6 16 bits -$PowerDownDelay_6 16 bits -$PowerCycleDelay_6 16 bits - -$Mipi_PwmOn_To_Bklt_Enable_Delay_01 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#1 -$Mipi_Bklt_Disable_To_PwmOff_Delay_01 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#1 - -$Mipi_PwmOn_To_Bklt_Enable_Delay_02 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#2 -$Mipi_Bklt_Disable_To_PwmOff_Delay_02 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#2 - -$Mipi_PwmOn_To_Bklt_Enable_Delay_03 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#3 -$Mipi_Bklt_Disable_To_PwmOff_Delay_03 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#3 - -$Mipi_PwmOn_To_Bklt_Enable_Delay_04 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#4 -$Mipi_Bklt_Disable_To_PwmOff_Delay_04 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#4 - -$Mipi_PwmOn_To_Bklt_Enable_Delay_05 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#5 -$Mipi_Bklt_Disable_To_PwmOff_Delay_05 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#5 - -$Mipi_PwmOn_To_Bklt_Enable_Delay_06 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#6 -$Mipi_Bklt_Disable_To_PwmOff_Delay_06 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#6 - -$Mipi_PmicI2cBusNo_1 1 byte -$Mipi_PmicI2cBusNo_2 1 byte -$Mipi_PmicI2cBusNo_3 1 byte -$Mipi_PmicI2cBusNo_4 1 byte -$Mipi_PmicI2cBusNo_5 1 byte -$Mipi_PmicI2cBusNo_6 1 byte - -EndStruct - - -;============================================================================== -; List Definitions -;------------------------------------------------------------------------------ - -List &Disabled_Enabled_List - Selection 0, "Disabled" - Selection 1, "Enabled" -EndList - -List &Pwr_Pref_List - Selection 0x01, "1 - Maximum Quality with No DPST" - Selection 0x02, "2" - Selection 0x03, "3" - Selection 0x04, "4" - Selection 0x05, "5" - Selection 0x06, "6 - Maximum Battery" -EndList - -List &Cls_After_Signon_List - Selection 0x00, "No CLS" - Selection 0x01, "0.5 Second Delay + CLS" - Selection 0x02, "1.0 Second Delay + CLS" - Selection 0x03, "1.5 Second Delay + CLS" - Selection 0x04, "2.0 Second Delay + CLS" - Selection 0x05, "2.5 Second Delay + CLS" - Selection 0x06, "3.0 Second Delay + CLS" - Selection 0x07, "3.5 Second Delay + CLS" -EndList - -List &Int_CRT_Device_Type_List - Selection 0x0000, "No Device" - Selection 0x0001, "CRT" - ;Selection 0x0011, "DVI with CRT" -EndList - -List &Int_EFP_Device_Type_List - Selection 0x0000, "No Device" - Selection 0x68C6, "DisplayPort" - Selection 0x60D2, "HDMI/DVI" - Selection 0x68D2, "Integrated DVI Only" - Selection 0x60D6, "DisplayPort with HDMI/DVI Compatible" - Selection 0x68D6, "DisplayPort with DVI Compatible" - ; Selection 0x68D3, "DVI with CRT" -EndList - -List &CRT_Device_Id_List - Selection 01h, "CRT" -EndList - -List &EFP1_Device_Id_List - Selection 04h, "EFP 1" - Selection 40h, "EFP 2" - Selection 08h, "LFP" - ;Selection 80h, "LFP 2" -EndList - -List &EFP2_Device_Id_List - Selection 04h, "EFP 1" - Selection 40h, "EFP 2" - Selection 08h, "LFP" - ;Selection 80h, "LFP 2" -EndList - -List &LVDS_Device_Id_List - Selection 08h, "LFP" -EndList - -List &DOS_Boot_Mode_List - Selection 0x03, "03h" - Selection 0x12, "12h" - Selection 0x13, "13h" - Selection 0x30, "30h" - Selection 0x32, "32h" - Selection 0x34, "34h" - Selection 0x40, "40h" - Selection 0x41, "41h" - Selection 0x42, "42h" - Selection 0x43, "43h" - Selection 0x44, "44h" - Selection 0x45, "45h" - Selection 0x50, "50h" - Selection 0x52, "52h" - Selection 0x54, "54h" -EndList - -List &LFP_Port_List - Selection 0x07, "eDP Port B" - Selection 0x08, "eDP Port C" - ; Selection 0x15, "MIPI Port A" - ;Selection 0x17, "MIPI Port C" - -EndList - -List &LVDS_eDP_Port_List - Selection 0x04, "LVDS" - Selection 0x07, "Port B" - Selection 0x08, "Port C" -EndList - - - -List &Int_EFP_Port_List - Selection 0x00, "N/A" - Selection 0x01, "Port B" - Selection 0x02, "Port C" - Selection 0x03, "Port D" - -EndList - -List &Int_eDP_AUX_Channel_List - Selection 0x00, "N/A" - Selection 0x10, "eDP-B AUX Channel" - Selection 0x20, "eDP-C AUX Channel" -EndList - -List &Int_DP_AUX_Channel_List - Selection 0x00, "N/A" - Selection 0x10, "DisplayPort-B AUX Channel" - Selection 0x20, "DisplayPort-C AUX Channel" - Selection 0x30, "DisplayPort-D AUX Channel" -EndList - -List &GPIO_Pin_List - Selection 0x00, "N/A" - Selection 0x05, "Integrated HDMI-B DDC GPIO Pins" - Selection 0x04, "Integrated HDMI-C DDC GPIO Pins" - Selection 0x03, "Integrated HDMI-D DDC GPIO Pins" ; as mentioned in CHV Bspec - Selection 0x01, "I2C GPIO pins" -; Selection 0x02, "Analog CRT DDC GPIO pins" -EndList - - -List &GMBus_Speed_List - Selection 0x01, "50 KHz" - Selection 0x00, "100 KHz" - Selection 0x02, "400 KHz" - Selection 0x03, "1 MHz" -EndList - - -List &Inv_Type_List - Selection 0x00, "None/External" - Selection 0x01, "I2C" - Selection 0x02, "PWM" -EndList - -List &Inv_Polarity_List - Selection 0x00, "Normal" - Selection 0x01, "Inverted" -EndList - -List &IntXXh_List - Selection 0x00, "Disabled" - Selection 0x01, "Use Interrupt 15h" -EndList - -List &LVDS_Channel_List - Selection 0x00, "Single Channel" - Selection 0x01, "Dual Channel" -EndList - -List &INT_LVDS_Channel_List - Selection 0x00, "Automatic Selection" - Selection 0x01, "Single Channel" - Selection 0x02, "Dual Channel" -EndList - -List &LVDS_Config_List - Selection 0x00, "No Device" - Selection 0x1020, "LVDS" -EndList - -List &eDP_Config_List - Selection 0x00, "No Device" - Selection 0x1806, "eDP" - ; Selection 0x1400, "MIPI" -EndList - -List &eDP_LVDS_Config_List - Selection 0x00, "No Device" - Selection 0x1020, "LVDS" - Selection 0x1806, "eDP" -EndList - - -List &No_Yes_List - Selection 0, "No" - Selection 1, "Yes" -EndList - -List &Off_On_List - Selection 0, "Off" - Selection 1, "On" -EndList - -List &OS_Driver_List - Selection 0, "OS Default Algorithm" - Selection 1, "Driver Algorithm" -EndList - -List &OS_DriverP_List - Selection 0, "OS Default Algorithm" - Selection 1, "Driver Persistence Algorithm" -EndList - -List &Panel_Color_Depth_List - Selection 0x00, "18-bit Color Depth" - Selection 0x01, "24-bit Color Depth" -EndList - -List &eDP_Panel_Color_Depth_List - Selection 0x00, "18-bit Color Depth" - Selection 0x01, "24-bit Color Depth" - Selection 0x02, "30-bit Color Depth" -EndList - -List &eDP_Link_DataRate_List - Selection 0x00, "1.62 Gbps" - Selection 0x01, "2.70 Gbps" -EndList - -List &eDP_Link_LaneCount_List - Selection 0x00, "x1" - Selection 0x01, "x2" - Selection 0x03, "x4" -EndList - -List &eDP_Link_PreEmp_List - Selection 0x00, "Level 0" - Selection 0x01, "Level 1" - Selection 0x02, "Level 2" - Selection 0x03, "Level 3" -EndList - -List &eDP_Link_VSwing_List - Selection 0x00, "Level 0" - Selection 0x01, "Level 1" - Selection 0x02, "Level 2" - Selection 0x03, "Level 3" -EndList - - -List &Panel_Connector_List - Selection 0x00, "SPGW" - Selection 0x01, "OpenLDI" -EndList - -List &Panel_List - Selection 0x00, "PANEL #01" - Selection 0x01, "PANEL #02" - Selection 0x02, "PANEL #03" - Selection 0x03, "PANEL #04" - Selection 0x04, "PANEL #05" - Selection 0x05, "PANEL #06" - Selection 0x06, "PANEL #07" - Selection 0x07, "PANEL #08" - Selection 0x08, "PANEL #09" - Selection 0x09, "PANEL #10" - Selection 0x0A, "PANEL #11" - Selection 0x0B, "PANEL #12" - Selection 0x0C, "PANEL #13" - Selection 0x0D, "PANEL #14" - Selection 0x0E, "PANEL #15" - Selection 0x0F, "PANEL #16" -EndList - - -List &Panel_Stretch_List - Selection 0x00, "Disable Panel Fitting" - Selection 0x01, "Enabled for Text Modes Only" - Selection 0x02, "Enabled for Graphics Modes Only" - Selection 0x03, "Enabled for Both Text and Graphics Modes" -EndList - -List &PCI_BIOS_Disabled_Enabled_List - Selection 0x00, "Disabled" - Selection 0x01, "Resize to 0.5K boundary" - Selection 0x20, "Resize to 16K boundary" -EndList - -List &RelStage - Selection 1, "Production" - Selection 254, "Evaluation" -EndList - -List &Power_Scheme_List - Selection 0, "CUI" - Selection 1, "3rd Party Application" -EndList - -List &Render_Freq_List - Selection 0, "High Frequency" - Selection 1, "Low Frequency" -EndList - -List &SSC_List - Selection 0, "96 MHz" - Selection 1, "100 MHz" -EndList - -List &SDVO_Panel_List - Selection 0x00, "PANEL #01" - Selection 0x01, "PANEL #02" - Selection 0x02, "PANEL #03" - Selection 0x03, "PANEL #04" -EndList - -List &Yes_No_List - Selection 0, "Yes" - Selection 1, "No" -EndList - -List &Sprite_Display_List - Selection 0, "Secondary Display" - Selection 1, "Primary Display" -EndList - -List &Under_Over_List - Selection 0x0, "Enable Underscan and Overscan modes" - Selection 0x1, "Enable only overscan modes" - Selection 0x2, "Enable only underscan modes" -EndList - -List &Inter_Exter_List - Selection 0, "External Termination" - Selection 1, "Internal Termination" -EndList - -List &DPS_Panel_Type_List - Selection 0x00, "Static DRRS" - Selection 0x02, "Seamless" -EndList - -List &MSA_TimingDelay_List - Selection 0x00, "Line 1" - Selection 0x01, "Line 2" - Selection 0x02, "Line 3" - Selection 0x03, "Line 4" -EndList - -List &Blt_Control_Type_List - ;Selection 0x00, "Default" - Selection 0x01, "CCFL Backlight" - Selection 0x02, "LED Backlight" -EndList - - -List &Mode_Preferred_List - Selection 0x00, "Mode Timing" - Selection 0x01, "Preferred Timing" -EndList - -List &DisplayList - Selection 0x08, "LFP" - ;Selection 0x80, "LFP 2" - ;Selection 0x01, "CRT" - Selection 0x04, "EFP 1" - Selection 0x40, "EFP 2" - Selection 0x20, "EFP 3" - Selection 0x00, "None" -EndList - -List &Dither_Select_Bit - Selection 0, "Dithering in Panel controller" - Selection 1, "Dithering in Display Controller" -EndList - -List &MIPI_Bridge_Ref_Clock_List - Selection 0, "19.2" - Selection 1, "26" -EndList - -List &Panel_Identifier_List - Selection 0x0, "Use Sequence Block" - Selection 0x1, "MIPI DSI Panel-1" - Selection 0x2, "MIPI DSI Panel-2" - Selection 0x3, "MIPI DSI Panel-3" - Selection 0x4, "MIPI DSI Panel-4" - Selection 0x5, "MIPI DSI Panel-5" - Selection 0x6, "MIPI DSI Panel-6" - Selection 0x7, "MIPI DSI Panel-7" - Selection 0x8, "MIPI DSI Panel-8" - ;Selection 0x9, "MIPI DSI Panel-9" - ;Selection 0xA, "MIPI DSI Panel-10" - ;Selection 0xB, "MIPI DSI Panel-11" - ;Selection 0xC, "MIPI DSI Panel-12" - ;Selection 0xD, "MIPI DSI Panel-13" - ;Selection 0xE, "MIPI DSI Panel-14" - ;Selection 0xF, "MIPI DSI Panel-15" - ;Selection 0x10, "MIPI DSI Panel-16" -EndList - -List &Panel_Type_List - Selection 0, "Native MIPI DSI" - Selection 1, "MIPI DSI to LVDS Bridge" -EndList - -List &MIPI_DSI_Panel_Architecture_Type_List - Selection 0x0, "Type 1" - Selection 0x1, "Type 2" - Selection 0x2, "Type 3" - Selection 0x3, "Type 4" -EndList - -List &Video_Command_Mode_List - Selection 0, "Video Mode" - Selection 1, "Command Mode" -EndList - -List &Packet_Sequence_Video_Mode_List - ;Selection 0x0, "Reserved" - Selection 0x1, "Non-burst with sync pulse" - Selection 0x2, "Non-burst with sync events" - Selection 0x3, "Burst Mode" -EndList - -List &Colour_Format_Video_Mode_List - Selection 0x1, "RGB565" - Selection 0x2, "RGB666" - Selection 0x3, "RGB 666(Loosely Packed Format)" - Selection 0x4, "RGB888" -EndList - -List &Panel_Rotation_List - Selection 0x0, "0 degree" - Selection 0x1, "90 degree" - Selection 0x2, "180 degree" - Selection 0x3, "270 degree" -EndList - -List &Enable_Disable_List - Selection 0, "Enable" - Selection 1, "Disable" -EndList - -List &EscapeClk_List - Selection 0x0, "20 MHz" - Selection 0x1, "10 MHz" - Selection 0x2, "5 MHz" - ;Selection 0x3, "Undefined" -EndList - -List &DPhyParamFlag_List - Selection 0, "Dphy Param is not valid" - Selection 1, "Dphy Param is valid" -EndList - -List &MIPI_DSI_Panel_Color_Depth_List - Selection 0x0, "18Bpp" - Selection 0x1, "24Bpp" -EndList - -List &Lane_Count_List - Selection 0x0, "1" - Selection 0x1, "2" - Selection 0x2, "3" - Selection 0x3, "4" -EndList - -List &Dual_Link_List - Selection 0x0, "Dual Link Not Supported" - Selection 0x1, "Dual Link Front Back Mode" - Selection 0x2, "Dual Link Pixel Alternative Mode" - ;Selection 0x3, "Reserved" -EndList - -List &Hdmi_LS_List_CHV - Selection 0x00, "1.2V 3dB" - Selection 0x01, "1.0V 0dB" -EndList - -List &Edp_Pwm_Source_List - Selection 0x1, "LPSS PWM" - Selection 0x2, "DISPLAY PWM" -EndList - -List &eDP_VSwing_Preemph_table_List - Selection 0x00, "Low Power VSwing/Pre-Emphasis Table" - Selection 0x01, "Default VSwing/Pre-Emphasis Table" -EndList - -;============================================================================== -; Page Definitions -;------------------------------------------------------------------------------ - -BeginInfoBlock - PPVer "2.01" - Image EOF Thru EOF At EOF -EndInfoBlock - - -;============================================================================== -; Page - VBT version -;------------------------------------------------------------------------------ - -Page "VBT version" - - Title "PLATFORM : CherryView" - Title "VBT version: 195" - -EndPage ; VBT version - - - -;============================================================================== -; Page - UEFI GOP Driver Configuration -;------------------------------------------------------------------------------ - -Page "UEFI GOP Driver Configuration" - - ;Combo $Hotplug_Support_Enb, " Hot Plug Support:", &Disabled_Enabled_List, - ;Help "This feature is to enable/disable Hot Plug Suppport for CRT/DP/HDMI displays " - - Title "Child Device Configuration" - Link "Child Device List", "Child Device List" - - Title "Fixed Mode" - Link "Fixed Mode Feature", "Fixed Mode Feature" - - ;============================================================================== - ; Page - Boot Display Algorithm - ;------------------------------------------------------------------------------ - - Page "Child Device List" - - Title "Select the child devices that the GOP driver should enumerate if detected." - Title "Note: The child devices are listed here in decreasing order of priority. In case the system BIOS does not specify " - "the child device to start, then GOP driver selects the highest priority child device" - - Link "Close Window", ".." - - Title "Child Device 1" - Combo $ChildDevice1Primary, "Primary display:" , &DisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice1Secondary, " Secondary display: " , &DisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 2" - Combo $ChildDevice2Primary, "Primary display:" , &DisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice2Secondary, " Secondary display: " , &DisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 3" - Combo $ChildDevice3Primary, "Primary display:" , &DisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice3Secondary, " Secondary display: " , &DisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 4" - Combo $ChildDevice4Primary, "Primary display:" , &DisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice4Secondary, " Secondary display: " , &DisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 5" - Combo $ChildDevice5Primary, "Primary display:" , &DisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice5Secondary, " Secondary display: " , &DisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 6" - Combo $ChildDevice6Primary, "Primary display:" , &DisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice6Secondary, " Secondary display: " , &DisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 7" - Combo $ChildDevice7Primary, "Primary display:" , &DisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice7Secondary, " Secondary display: " , &DisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 8" - Combo $ChildDevice8Primary, "Primary display:" , &DisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice8Secondary, " Secondary display: " , &DisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 9" - Combo $ChildDevice9Primary, "Primary display:" , &DisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice9Secondary, " Secondary display: " , &DisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 10" - Combo $ChildDevice10Primary, "Primary display:" , &DisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice10Secondary, " Secondary display: " , &DisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 11" - Combo $ChildDevice11Primary, "Primary display:" , &DisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice11Secondary, " Secondary display: " , &DisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 12" - Combo $ChildDevice12Primary, "Primary display:" , &DisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice12Secondary, " Secondary display: " , &DisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 13" - Combo $ChildDevice13Primary, "Primary display:" , &DisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice13Secondary, " Secondary display: " , &DisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 14" - Combo $ChildDevice14Primary, "Primary display:" , &DisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice14Secondary, " Secondary display: " , &DisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 15" - Combo $ChildDevice15Primary, "Primary display:" , &DisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice15Secondary, " Secondary display: " , &DisplayList, - Help "Secondary Display\r\n" - - Title " " - Title "Child Device 16" - Combo $ChildDevice16Primary, "Primary display:" , &DisplayList, - Help "Primary Display\r\n" - Combo $ChildDevice16Secondary, " Secondary display: " , &DisplayList, - Help "Secondary Display\r\n" - EndPage ;"Child Device List" - -;============================================================================ -; Page - Fixed Mode Configuration -;---------------------------------------------------------------------------- - - Page "Fixed Mode Feature" - Link "Close Table", ".." - Combo $Feature_Enable, "Enable Feature:", &No_Yes_List, - Help "Fixed Mode Feature allows user to fix a mode during POST such that only that particular mode will be always set.\r\n" - "This field specifies if user wants to enable/disable the feature.\r\n" - "When enabled user is expected to provide a valid input." - - EditNum $X_res, "Horizontal Pixels:", DEC, - Help "This value specifies the horizontal pixels of the mode. It should be always less than or equal to the native horizontal resolution.\r\n" - - EditNum $Y_res, "Vertical Pixels:", DEC, - Help "This value specifies the vertical pixels of the mode. It should be always less than or equal to the native vertical resolution.\r\n" - - EndPage -EndPage ; "UEFI GOP Driver Configuration" - - - -;============================================================================ -; Page - Windows Graphics Driver Configuration -;---------------------------------------------------------------------------- - -Page "Windows Graphics Driver Configuration" - - Link "General Features" , "General Features" - Link "Display Features" , "Display Features" - Link "Power Conservation" , "Power Conservation" - - Page "General Features" - Link "Close Table" , ".." - - EditNum $VBT_Customization_Version, " VBT Customization Version:", DEC, - Help "This feature allows the OEM to have a customized VBT version " - "number. The permissible values for VBT Customization version " - "is from 0 to 255.\r\n" - - Combo $Driver_Boot_Device, " First Boot Display Device:", &OS_Driver_List, - Help "This feature allows the OEM to select which algorithm to " - "follow on the first boot after the driver has been " - "installed.\r\n" - "\r\n" - "OS Default - If this is selected, the operating system's " - "algorithm will be used.\r\n" - "\r\n" - "Driver Default - If this is selected, the boot device will " - "follow the driver algorithm. The expected behavior can be " - "found in the Driver PRD chapter: 'First Boot Default " - "Display Resolutions'." - - ;Combo $Allow_FDOS_Disp_Switch, " Allow Full Screen DOS Display Switching:", &No_Yes_List, - ;Help "This feature allows display switching when the system is in " - ; "full screen DOS. When set to yes, display switching will be " - ; "allowed while system is in full screen DOS. When set to no, " - ; "display switching will be blocked when system is in full " - ;"screen DOS." - - ;Combo $Hot_Plug_DVO, " DVO/SDVO Hot Plug:", &Disabled_Enabled_List, - ;Help "This feature allows the OEM to disable the DVO/SDVO Hot Plug " - ; "capability." - - - Combo $Use_110h_for_LFP, " Use _DOD 00000110h ID for Primary LFP:", &No_Yes_List, - Help "This feature when set to yes will use the legacy value " - "00000110h as the ID for primary LFP in the ACPI _DOD, _DGS " - "method. The ID is passed to the system BIOS through INT10h function 5F64h " - "The ID 00000110h is the backwards compatible ACPI ID " - "for LFP, which may be necessary in where Microsoft* WindowsXP " - "TabletPC*'s Graphical User Interface is required for Backlight " - "Control(hardcoded by some Windows OSes). In all other cases, " - "the default new ID is strongly preferred." - - - ;Combo $DVD_Sprite_Clone, " Disable Sprite (DVD) in Clone Mode:", &Yes_No_List, - ;Help "This feature when selected 'No', will allow the sprite to be " - ; "active during DVD playback when the platform is in a Dual " - ; "Display Clone configuration. Otherwise, when selected 'Yes', " - ; "the overlay sprite will be disabled during DVD playback when the " - ; "platform is in a Dual Display Clone configuration." - - Combo $GTF_Mode_Pruning, " Selective Mode Pruning:", &Disabled_Enabled_List, - Help "This feature when enabled will instruct driver software not " - "to enumerate or set specific display modes determined as " - "unsupported according to the EDID capabilities of the " - "display. If the display indicates support for all GTF/DMTS " - "timings in the display's EDID, then all modes supported by " - "the graphics host will be enumerated. If the display does " - "NOT indicate support for GTF/DMTS timings in the display's " - "EDID, then some modes/timings that may have been enumerated " - "by the display driver shall not be set." - "\r\n" - "\r\n" - "Note: This option applies for all display types. And in the " - "absence of other platform configuration information (e.g. " - "OEM Customizable Mode) requiring inclusion of that display " - "mode/timings." - - ;Combo $Sprite_Display_Assign, " Sprite Display Assignment for When Overlay is Active in Clone Mode:", &Sprite_Display_List, - ;Help "This feature when set to Primary Display, the driver will " - ; "assign the Sprite (2ndary overlay) to the primary display " - ; "defined in the current Dual Display Clone configuration, " - ; "otherwise when this feature is set to Secondary Display, the " - ;"driver will assign the Sprite (2ndary overlay) to the " - ;"secondary display defined in the current Dual Display Clone " - ;"configuration. Note: This bit will have no affect if an " - ;"application is using the VMR API. " - - - - Combo $CUIHotK_Static_Display, " Display must be attached for CUI/Hot Key:", &Yes_No_List, - Help "This feature allows a selectable option to determine whether " - "the display device must be attached for CUI Hot Key.\r\n" - "\r\n" - "With the 'No' option the display devices do not have to be " - "attached when enabling the displays via CUI Devices Pages, " - "CUI Hot Key. Note: This feature may cause the user to have " - "a blank display device due to switching to a display that is " - "not attached.\r\n" - "\r\n" - "With the 'Yes' option the display device must be attached or " - "the display switch attempt will be blocked." - EndPage - - Page "Display Features" - Link "Close Table" , ".." - - Combo $CUI_Maintain_Aspect, " Enable 'Maintain Aspect Ratio':", &No_Yes_List, - Help "This feature allows the OEM to enable or disable the 'Maintain " - "Aspect Ratio' feature. When the option is set to Yes, the " - "feature will be enabled and CUI will show for end user " - "selection 'Maintain Aspect Ratio'. When the option is set to " - "No, the complete 'Maintain Aspect Ratio' feature will be disabled." - - Combo $Preserve_Aspect_Ratio, " Preserve Aspect Ratio:", &Disabled_Enabled_List, - Help "This feature allows the OEM to configure the default option " - "for aspect ratio settings. When enabled, the CUI will reflect " - "preserve the aspect ratio as active setting. Otherwise, when " - "disabled, the CUI will use the setting 'Panel Fitting Initial " - "States' as default aspect ratio setting. This option will " - "only be available for initial boot value. Any subsequent " - "change in CUI will have higher priority." - - Title " " - TitleB "Legacy Monitor Mode Limit" - - EditNum $Legacy_Monitor_Max_X, " Maximum X Resolution (Pixels):", DEC, - Help "This feature allows the limiting of selectable display modes " - "when a legacy monitor is detected. The maximum resolution is " - "specified by a maximum number of horizontal active pixels." - "\r\n" - "Note: A legacy monitor is defined as a monitor with no DDC " - "available." - - EditNum $Legacy_Monitor_Max_Y, " Maximum Y Resolution (Pixels):", DEC, - Help "This feature allows the limiting of selectable display modes " - "when a legacy monitor is detected. The maximum resolution is " - "specified by a maximum number of vertical active pixels." - "\r\n" - "Note: A legacy monitor is defined as a monitor with no DDC " - "available." - - EditNum $Legacy_Monitor_Max_RR, " Maximum Refresh Rate (Hz):", DEC, - Help "This feature allows the limiting of selectable display modes " - "when a legacy monitor is detected. The maximum refresh rate " - "is specified in Hz." - "\r\n" - "Note: A legacy monitor is defined as a monitor with no DDC " - "available." - - - Title " " - TitleB "Rotation Support Configuration" - - - Combo $Rotation_Support_Enable, "Support Rotation Feature:", &No_Yes_List, - Help "This feature when set to yes, can cause the graphics driver to " - "support rotation feature, otherwise rotation feature support " - "will be disabled." - "\r\n" - "Note: Setting this field to Yes is a necessary condition for driver to " - "support rotation feature, but it is not sufficient." - - - Title " " - TitleB "Graphics Mode to Boot on Windows" - - - EditNum $Driver_Boot_Mode_X, " X Resolution (Pixels):", DEC, - Help "This feature allows the OEM to select which resolution the " - "system will use on the first reboot after the driver has " - "been installed.\r\n" - "\r\n" - "X Resolution (Pixels)\r\n" - "\r\n" - "Note: This feature is only used when the Boot Display " - "Algorithm is set to Driver Default." - - EditNum $Driver_Boot_Mode_Y, " Y Resolution (Pixels):", DEC, - Help "This feature allows the OEM to select which resolution the " - "system will use on the first reboot after the driver has " - "been installed.\r\n" - "\r\n" - "Y Resolution (Pixels)\r\n" - "\r\n" - "Note: This feature is only used when the Boot Display " - "Algorithm is set to Driver Default." - - EditNum $Driver_Boot_Mode_BPP, " Color Depth (Bits/Pixel):", DEC, - Help "This feature allows the OEM to select which resolution the " - "system will use on the first reboot after the driver has " - "been installed.\r\n" - "\r\n" - "Color Depth (BPP)\r\n" - "\r\n" - "Note: This feature is only used when the Boot Display " - "Algorithm is set to Driver Default." - - EditNum $Driver_Boot_Mode_RR, " Refresh Rate (Hz):", DEC, - Help "This feature allows the OEM to select which resolution the " - "system will use on the first reboot after the driver has " - "been installed.\r\n" - "\r\n" - "Refresh Rate (Hz)\r\n" - "\r\n" - "Note: This feature is only used when the Boot Display " - "Algorithm is set to Driver Default." -Title " " -TitleB "TV features" - - Combo $Under_Over_Scan_Via_YPrPb, " Enable underscanned modes for HDTV via Component (YPrPb):", &Under_Over_List, - Help "For 720p format when enable underscan and overscan modes " - "option is selected, expose 1184x666 and 1280x720 through CUI" - "\r\n" - "For 1080i format when enable underscan and overscan modes " - "option is selected, expose 1776x1080 and 1920x1080 through CUI" - - Combo $Under_Over_Scan_Via_DVI, " Enable underscanned modes for HDTV via HDMI:", &Under_Over_List, - Help "When 720p is found in the EDID structure of the active HDMI " - "display and enable underscan modes is selected, 1184x666 will " - "be available and be centered in 720p timings when enabled. " - "\r\n" - "When 1080i or 1080p is found in the EDID structure of the " - "active DVI display and enable underscan modes is selected, " - "1776x1000 will be centered in appropriate 1080 timings. " - - Title "\r\n" - Title " Add 1776x1000 when 1080i is selected and add 1184x666 when 720p is selected for HDTV via HDMI:" - Combo $Add_Overscan_Mode, " ", &Disabled_Enabled_List, - Help "For 1080i format, 1776x1000 will be made available in CUI " - "along with native resolution 1920x1080. For 720p format, " - "1184x666 will be made available in CUI along with native " - "resolution 1280x720. These resolutions are exposed to get the " - "HDMI image under scanned with task bar visible." - EndPage ; Display features - - - - - Page "Power Conservation" - Link "Close Table" , ".." - - ;Combo $SDVO_Device_Power_Down, " SDVO device power down:", &Disabled_Enabled_List, - ;Help "This feature powers down the SDVO device when the system is " - "running in battery mode (DC) and the corresponding display " - "not connected." - - Combo $BIA_Enable, " Intel® Display Power Saving Technology Support for the LFP:", &Disabled_Enabled_List, - Help "This feature determines whether the Intel® Display Power " - "Savings Technology (DPST) is enabled or disabled. Intel® DPST " - "is a display power savings technology that changes the " - "intensity of colors in order to conserve backlight power." - "\r\n\r\nNote: This technology is only active when the system " - "is running in battery mode and the LFP is the only active " - "display device." - - Combo $BIA_Aggress_Level, " Power Conservation Preference Level for the LFP:", &Pwr_Pref_List, - Help "This feature defines the Intel® Display Power Saving Technology " - "aggressiveness level if and only if the feature Intel® Display Power Saving " - "Technology is enabled." - "\r\n\r\nThe following are the definitions for each level:" - "\r\n1 - Maximum Quality - shall use no DPST " - "\r\n2 - Provides the user the maximum " - "brightness for their embedded Local Flat Panel (LFP)while DPST is in use" - "\r\n3 - This level defines maximum amount of brightness with " - "minimal power savings" - "\r\n4 - This level defines an intermediate value for brightness amount" - "\r\n5 - This level defines an intermediate value for the brightness amount" - "\r\n6 - Maximum Battery - Provided the user with the minimum amount of " - "brightness capable for their LFP with the maximum power savings" - - Combo $Panel_Self_Refresh, " Panel Self Refresh (PSR):", &Disabled_Enabled_List, - Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled. " - - Combo $PM_DRRS_Enable, " Intel ® Display Refresh Rate Switching (DRRS):", &Disabled_Enabled_List, - Help "This feature determines whether Intel ® Display Refresh Rate Switching (DRRS) is to be " - "enabled or not. " - - Combo $ALS_Enable, " Intel ® Automatic Display Brightness Support for the LFP:", &Disabled_Enabled_List, - Help "This feature determines whether Intel ® Automatic Display Brightness is to be " - "enabled. Intel ® Automatic Display Brightness adjusts the brightness of the " - "embedded Local Flat Panel (LFP) depending on the current " - "ambient light environment. When enabled, the driver and VBIOS" - " will control the backlight brightness of the LFP depending " - "on the ambient environment if and only if the LFP is the only " - "active display. When disabled, the driver and VBIOS will " - "perform no action." - - Combo $DMRRS, " Dynamic Media Refresh Rate Switching (DMRRS):", &Disabled_Enabled_List, - Help "This feature determines whether Dynamic Media Refresh Rate Switching feature is to be enabled. " - - Link "Ambient Light Response Data" , "Ambient Light Response Data" - - Page "Ambient Light Response Data" - Link "Close Table" , ".." - - Table $ALS_Response_Data " Ambient Light Response Data", - Column "Backlight Adjust", 2 bytes, EHEX - Column "Lux", 2 bytes, EHEX, - Help "This feature defines values used to calibrate the " - "Intel® Automatic Display Brightness policy's " - "response to account for specific hardware implementation " - "details such as sensor placement and optics. Up to five " - "points can be specified, where each point indicates a given " - "ambient light illuminance to display luminance mapping " - "specified as (<%BacklightAdjust>, ). Points should be " - "listed in monotonically increasing order by ambient light " - "illuminance (lux). A minimum of two points are required " - "(min and max)." - EndPage - - EndPage - EndPage -;============================================================================== -; Page - Display Configuration -;------------------------------------------------------------------------------ - -Page "Display Configuration" - - Link "LFP" , "LFP" - Link "EFP 1" , "EFP 1" - Link "EFP 2" , "EFP 2" - Link "EFP 3" , "EFP 3" - - TitleB "DisplayPort SSC configuration: " - Combo $DP_SSC_Enb, " DisplayPort (External Connectors) Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature allow OEMs to enable/disable SSC for external DisplayPort. " - "This feature is valid only the attached DisplayPort panel support SSC. " - "\r\n" - - Combo $DP_SSC_Dongle_Enb, " DisplayPort Spread Spectrum Clock Enable/Disable for Dongles:", &Disabled_Enabled_List, - Help "This feature is to enable or disable DisplayPort Dongle Spread Spectrum Clock when dongle are used " - "and the attached DisplayPort panel should support SSC\r\n" - - - Page "LFP" - Link "Close Table", ".." - - Combo $Int_LFP1_Type , "Active Local Flat Panel Configuration", &eDP_Config_List, - Help "This option select Device type." - - ; #IF ($Int_LFP1_Type == 0x1806) - Combo $Int_LFP1_Port, "Select Output Port:", &LFP_Port_List, - Help "This feature specifies which DVO port to use for the selected LFP Device." - ;#ENDIF - - Combo $Int_LFP1_AUX_Channel, "Select AUX Channel:", &Int_eDP_AUX_Channel_List, - Help "This feature specifies the AUX Channel for int-Embedded DisplayPort. " - "This field is valid only if integrated eDP is selected for Device Type." - - ;Combo $Int_LFP1_Priority, "Primary LFP panel: ", &Yes_No_List, - ;Help "This feature will select if the panel is primary or not. " - ;"The VLV platform has only one panel fitter. So, stretched mode will be only applicable " - ;"to primary panel . In secondary panel only native mode or " - ;"centering modes will be supported." - - Combo $bmp_Panel_type, "Select Panel Type:", &Panel_List, - Help "This feature selects the Local Flat Panel (LFP) the VBIOS " - "and driver is to enable.\r\n" - "\r\n" - "Note, a valid return from the system BIOS hook 5F40h will " - "replace this default value.\r\n" - "\r\n" - "Default LFP parameter values:\r\n" - "\tPANEL #01: 640x480 LVDS\r\n" - "\tPANEL #02: 800x600 LVDS\r\n" - "\tPANEL #03: 1024x768 LVDS\r\n" - "\tPANEL #04: 1280x1024 LVDS\r\n " - "\tPANEL #05: 1400x1050 Reduced Blanking LVDS\r\n" - "\tPANEL #06: 1400x1050 Non-Reduced Blanking LVDS\r\n" - "\tPANEL #07: 1600x1200 LVDS\r\n" - "\tPANEL #08: 1280x768 LVDS\r\n" - "\tPANEL #09: 1680x1050 LVDS\r\n" - "\tPANEL #10: 1920x1200 LVDS\r\n" - "\tPANEL #11: Reserved\r\n" - "\tPANEL #12: Reserved\r\n " - "\tPANEL #13: Reserved\r\n" - "\tPANEL #14: 1280x800 LVDS\r\n" - "\tPANEL #15: 1280x600 LVDS\r\n" - "\tPANEL #16: Reserved" - - Combo $bmp_Panel_EDID, "Local Flat Panel (LFP) EDID Support: ", &Disabled_Enabled_List, - Help "This feature, when enabled, will activate support for a LFP " - "with an EDID. The video BIOS and drivers will load the EDID " - "and use its data to set appropriate timing on current panel. " - "If disabled, there will be no attempt to read an EDID and other methods " - "will be used to set panel timing." - "\r\n\r\nNote: The backlight data may need to be updated." - "\r\n The option on page General" - " Features must be correct for platform." - - Combo $180_Deg_Rotation_Enable, "Enable 180 Degree Rotation:", &No_Yes_List, - Help "This feature when set to yes, will enable 180 Degree rotation " - "otherwise, the rotation functionality will be disabled." - - - EndPage - - - ;Page "CRT" - ; Link "Close Window" , ".." - - ; Combo $Int_CRT_Support, "CRT Device:", &Int_CRT_Device_Type_List, - ; Help "This option select CRT Device." - - ;Combo $CRT_DDC_GMBUS_Pin, "Select DDC Bus GPIO Pin Pair:", &GPIO_Pin_List, - ;Help "This feature specifies the GPIO pin pair " - ; "used as DDC bus by this device. If this device " - ; "doesn't support DDC bus, this field will be ignored." - - ;EndPage - - Page "EFP 1" - Link "Close Window" , ".." - - Combo $Int_EFP1_Type, "Device Type", &Int_EFP_Device_Type_List, - Help "This option specifies the Device Type." - - Combo $Int_EFP1_Port, "Select Output Port:", &Int_EFP_Port_List, - Help "This feature specifies which DVO port to use for the selected EFP Device." - - Combo $Int_EFP1_AUX_Channel, "Select AUX Channel:", &Int_DP_AUX_Channel_List, - Help "This feature specifies the AUX Channel for int-DisplayPort. " - "This field is valid only if integrated DP is selected for Device Type." - - Combo $Int_EFP1_DDC_Pin, "Select DDC Bus GPIO Pin Pair:", &GPIO_Pin_List, - Help "This feature specifies the GPIO pin pair " - "used as DDC bus by this device. If this device " - "doesn't support DDC bus, this field will be ignored." - - Combo $Int_EFP1_HDMI_LS_Type, "Select HDMI level shifter configuration:", &Hdmi_LS_List_CHV, - Help "This feature specifies the Level shifter configuration for HDMI. " - "This field is valid only if HDMI is selected for Device Type." - - ;Combo $Int_EFP1_Dongle_Detect, "Select Dongle Detect:", &Disabled_Enabled_List, - ;Help "This option Enables/Disables detection of type of dongle connected to DP port.\r\n" - ; "This option is used only by the GFX driver." - - Combo $Int_EFP1_Docked_Port, "Dockable: ", &No_Yes_List, - Help "This field describes if the Display Port is routed through Dock or not." - - Link "USB-Type-C Dongle Feature Configuration" , "USB-Type-C Dongle Feature Configuration" - Link "DisplayPort Redriver Configuration" , "DisplayPort Redriver Configuration" - - Page "USB-Type-C Dongle Feature Configuration" - - Combo $EFP1_USB_C_DongleFeature_Enabled, "USB-Type-C Dongle Feature Enabled:", &Disabled_Enabled_List, - Help "This option Enables/Disables USB-Type-C Dongle Feature for USB Type C port for DP panels.\r\n" - EditNum $EFP1_GPIO_Index, "GPIO Index:", DEC, - Help "Enter the GPIO index/GPIO resource ID which is being used by Gfx driver" - EditNum $EFP1_GPIO_Number, "GPIO Number:", DEC, - Help "Enter the GPIO number which will be read to identify whether it is 2xDP or 4xDP DP over USB cable attached." - "If 2xDP cable is attached, microcontroller will set the this gpio pin to high." - "If 4xDP cable is attached, microcontroller will set the this pin to low." - EndPage - - Page "DisplayPort Redriver Configuration" - - Combo $EFP1_OnBoard_Redriver_Present, "Non-dock topology:", &No_Yes_List, - Help "This feature will describe if Non-dock topology/OnBoard Redriver DP Link is present or not." - - Combo $EFP1_OnBoard_PreEmph_Level, " Pre-Emphasis Level:", &eDP_Link_PreEmp_List, - Help "This feature allows for the selection of " - "Pre-emphasis level for the OnBoard redriver DP link.\n" - "\r\n\n\t\t\tDefault Swing Setting Table\n" - "\t---------------------------------------------------------------------------------------------------\n" - "\t \t | \t\t PreEmphasis Levels\t\t |\n" - "\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\n " - "\t---------------------------------------------------------------------------------------------------\n" - "\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\n" - "\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\n" - "\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\n" - "\t| Level 3(1200mV) | 1200mV | N/A | N/A | N/A |\n" - "\t---------------------------------------------------------------------------------------------------\n" - "\tColumn - Non-Transition VDiff \r\n" - "\tRow - Transition VDiff \r\n" - - - Combo $EFP1_OnBoard_VSwing_Level, " Voltage Swing Level:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of " - "Voltage Swing level for the OnBoard redriver DP link.\n" - "\r\n\n\t\t\tDefault Swing Setting Table\n" - "\t---------------------------------------------------------------------------------------------------\n" - "\t \t | \t\t PreEmphasis Levels\t\t |\n" - "\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\n " - "\t---------------------------------------------------------------------------------------------------\n" - "\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\n" - "\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\n" - "\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\n" - "\t| Level 3(1200mV) | 1200mV | N/A | N/A | N/A |\n" - "\t---------------------------------------------------------------------------------------------------\n" - "\tColumn - Non-Transition VDiff \r\n" - "\tRow - Transition VDiff \r\n" - - - Title " " - - Combo $EFP1_OnDock_Redriver_Present, "Dock Topology: (Mobile only)", &No_Yes_List, - Help "This feature will describe if Dock Topology/Dock Redriver DP Link is present or not.\r\n\r\n" - "Note: For Dock Topology to work SBIOS should implement a GOP Policy Protocol to provide the" - " docking status of the platform to GOP.\n" - - Combo $EFP1_OnDock_PreEmph_Level, " Pre-Emphasis Level:", &eDP_Link_PreEmp_List, - Help "This feature allows for the selection of " - "Pre-emphasis level for the Dock redriver DP link." - "\r\n\n\t\t\tDefault Swing Setting Table\n" - "\t---------------------------------------------------------------------------------------------------\n" - "\t \t | \t\t PreEmphasis Levels\t\t |\n" - "\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\n " - "\t---------------------------------------------------------------------------------------------------\n" - "\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\n" - "\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\n" - "\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\n" - "\t| Level 3(1200mV) | 1200mV | N/A | N/A | N/A |\n" - "\t---------------------------------------------------------------------------------------------------\n" - "\tColumn - Non-Transition VDiff \r\n" - "\tRow - Transition VDiff \r\n" - - Combo $EFP1_OnDock_VSwing_Level, " Voltage Swing Level:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of " - "Voltage Swing level for the Dock redriver DP link." - "\r\n\n\t\t\tDefault Swing Setting Table\n" - "\t---------------------------------------------------------------------------------------------------\n" - "\t \t | \t\t PreEmphasis Levels\t\t |\n" - "\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\n " - "\t---------------------------------------------------------------------------------------------------\n" - "\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\n" - "\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\n" - "\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\n" - "\t| Level 3(1200mV) | 1200mV | N/A | N/A | N/A |\n" - "\t---------------------------------------------------------------------------------------------------\n" - "\tColumn - Non-Transition VDiff \r\n" - "\tRow - Transition VDiff \r\n" - - EndPage ; "DisplayPort Redriver Configuration" - - EndPage - - - Page "EFP 2" - Link "Close Window" , ".." - - Combo $Int_EFP2_Type, "Device Type:", &Int_EFP_Device_Type_List, - Help "This option specifies the Device Type." - - Combo $Int_EFP2_Port, "Select Output Port:", &Int_EFP_Port_List, - Help "This feature specifies which DVO port to use for the selected EFP Device." - - Combo $Int_EFP2_AUX_Channel, "Select AUX Channel:", &Int_DP_AUX_Channel_List, - Help "This feature specifies the AUX Channel for int-DisplayPort. " - "This field is valid only if integrated DP is selected for Device Type." - - Combo $Int_EFP2_DDC_Pin, "Select DDC Bus GPIO Pin Pair:", &GPIO_Pin_List, - Help "This feature specifies the GPIO pin pair " - "used as DDC bus by this device. If this device " - "doesn't support DDC bus, this field will be ignored." - - Combo $Int_EFP2_HDMI_LS_Type, "Select HDMI level shifter configuration:", &Hdmi_LS_List_CHV, - Help "This feature specifies the Level shifter configuration for HDMI. " - "This field is valid only if HDMI is selected for Device Type." - - - ;Combo $Int_EFP2_Dongle_Detect, "Select Dongle Detect:", &Disabled_Enabled_List, - ;Help "This option Enables/Disables detection of type of dongle connected to DP port.\r\n" - ; "This option is used only by the GFX driver." - - Combo $Int_EFP2_Docked_Port, "Dockable: ", &No_Yes_List, - Help "This field describes if the Display Port is routed through Dock or not." - - Link "USB-Type-C Dongle Feature Configuration" , "USB-Type-C Dongle Feature Configuration" - Link "DisplayPort Redriver Configuration" , "DisplayPort Redriver Configuration" - - Page "USB-Type-C Dongle Feature Configuration" - Combo $EFP2_USB_C_DongleFeature_Enabled, "USB-Type-C Dongle Feature Enabled:", &Disabled_Enabled_List, - Help "This option Enables/Disables USB-Type-C Dongle Feature for USB Type C port for DP panels.\r\n" - EditNum $EFP2_GPIO_Index, "GPIO Index:", DEC, - Help "Enter the GPIO index/GPIO resource ID which is being used by Gfx driver" - EditNum $EFP2_GPIO_Number, "GPIO Number:", DEC, - Help "Enter the GPIO number which will be read to identify whether it is 2xDP or 4xDP DP over USB cable attached." - "If 2xDP cable is attached, microcontroller will set the this gpio pin to high." - "If 4xDP cable is attached, microcontroller will set the this pin to low." - EndPage - - Page "DisplayPort Redriver Configuration" - - Combo $EFP2_OnBoard_Redriver_Present, "Non-dock topology:", &No_Yes_List, - Help "This feature will describe if Non-dock topology/OnBoard Redriver DP Link is present or not." - - Combo $EFP2_OnBoard_PreEmph_Level, " Pre-Emphasis Level:", &eDP_Link_PreEmp_List, - Help "This feature allows for the selection of " - "Pre-emphasis level for the OnBoard redriver DP link.\n" - "\r\n\n\t\t\tDefault Swing Setting Table\n" - "\t---------------------------------------------------------------------------------------------------\n" - "\t \t | \t\t PreEmphasis Levels\t\t |\n" - "\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\n " - "\t---------------------------------------------------------------------------------------------------\n" - "\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\n" - "\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\n" - "\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\n" - "\t| Level 3(1200mV) | 1200mV | N/A | N/A | N/A |\n" - "\t---------------------------------------------------------------------------------------------------\n" - "\tColumn - Non-Transition VDiff \r\n" - "\tRow - Transition VDiff \r\n" - - - Combo $EFP2_OnBoard_VSwing_Level, " Voltage Swing Level:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of " - "Voltage Swing level for the OnBoard redriver DP link.\n" - "\r\n\n\t\t\tDefault Swing Setting Table\n" - "\t---------------------------------------------------------------------------------------------------\n" - "\t \t | \t\t PreEmphasis Levels\t\t |\n" - "\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\n " - "\t---------------------------------------------------------------------------------------------------\n" - "\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\n" - "\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\n" - "\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\n" - "\t| Level 3(1200mV) | 1200mV | N/A | N/A | N/A |\n" - "\t---------------------------------------------------------------------------------------------------\n" - "\tColumn - Non-Transition VDiff \r\n" - "\tRow - Transition VDiff \r\n" - - - Title " " - - Combo $EFP2_OnDock_Redriver_Present, "Dock Topology: (Mobile only)", &No_Yes_List, - Help "This feature will describe if Dock Topology/Dock Redriver DP Link is present or not.\r\n\r\n" - "Note: For Dock Topology to work SBIOS should implement a GOP Policy Protocol to provide the" - " docking status of the platform to GOP.\n" - - Combo $EFP2_OnDock_PreEmph_Level, " Pre-Emphasis Level:", &eDP_Link_PreEmp_List, - Help "This feature allows for the selection of " - "Pre-emphasis level for the Dock redriver DP link." - "\r\n\n\t\t\tDefault Swing Setting Table\n" - "\t---------------------------------------------------------------------------------------------------\n" - "\t \t | \t\t PreEmphasis Levels\t\t |\n" - "\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\n " - "\t---------------------------------------------------------------------------------------------------\n" - "\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\n" - "\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\n" - "\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\n" - "\t| Level 3(1200mV) | 1200mV | N/A | N/A | N/A |\n" - "\t---------------------------------------------------------------------------------------------------\n" - "\tColumn - Non-Transition VDiff \r\n" - "\tRow - Transition VDiff \r\n" - - Combo $EFP2_OnDock_VSwing_Level, " Voltage Swing Level:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of " - "Voltage Swing level for the Dock redriver DP link." - "\r\n\n\t\t\tDefault Swing Setting Table\n" - "\t---------------------------------------------------------------------------------------------------\n" - "\t \t | \t\t PreEmphasis Levels\t\t |\n" - "\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\n " - "\t---------------------------------------------------------------------------------------------------\n" - "\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\n" - "\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\n" - "\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\n" - "\t| Level 3(1200mV) | 1200mV | N/A | N/A | N/A |\n" - "\t---------------------------------------------------------------------------------------------------\n" - "\tColumn - Non-Transition VDiff \r\n" - "\tRow - Transition VDiff \r\n" - - EndPage ; "DisplayPort Redriver Configuration" - - - EndPage - - Page "EFP 3" - Link "Close Window" , ".." - - Combo $Int_EFP3_Type, "Device Type:", &Int_EFP_Device_Type_List, - Help "This option specifies the Device Type." - - Combo $Int_EFP3_Port, "Select Output Port:", &Int_EFP_Port_List, - Help "This feature specifies which DVO port to use for the selected EFP Device." - - Combo $Int_EFP3_AUX_Channel, "Select AUX Channel:", &Int_DP_AUX_Channel_List, - Help "This feature specifies the AUX Channel for int-DisplayPort. " - "This field is valid only if integrated DP is selected for Device Type." - - Combo $Int_EFP3_DDC_Pin, "Select DDC Bus GPIO Pin Pair:", &GPIO_Pin_List, - Help "This feature specifies the GPIO pin pair " - "used as DDC bus by this device. If this device " - "doesn't support DDC bus, this field will be ignored." - - Combo $Int_EFP3_HDMI_LS_Type, "Select HDMI level shifter configuration:", &Hdmi_LS_List_CHV, - Help "This feature specifies the Level shifter configuration for HDMI. " - "This field is valid only if HDMI is selected for Device Type." - - ;Combo $Int_EFP3_Dongle_Detect, "Select Dongle Detect:", &Disabled_Enabled_List, - ;Help "This option Enables/Disables detection of type of dongle connected to DP port.\r\n" - Combo $Int_EFP3_Docked_Port, "Dockable: ", &No_Yes_List, - Help "This field describes if the Display Port is routed through Dock or not." - - Link "USB-Type-C Dongle Feature Configuration" , "USB-Type-C Dongle Feature Configuration" - Link "DisplayPort Redriver Configuration" , "DisplayPort Redriver Configuration" - - Page "USB-Type-C Dongle Feature Configuration" - Combo $EFP3_USB_C_DongleFeature_Enabled, "USB-Type-C Dongle Feature Enabled:", &Disabled_Enabled_List, - Help "This option Enables/Disables USB-Type-C Dongle Feature for USB Type C port for DP panels.\r\n" - EditNum $EFP3_GPIO_Index, "GPIO Index:", DEC, - Help "Enter the GPIO index/GPIO resource ID which is being used by Gfx driver" - EditNum $EFP3_GPIO_Number, "GPIO Number:", DEC, - Help "Enter the GPIO number which will be read to identify whether it is 2xDP or 4xDP DP over USB cable attached." - "If 2xDP cable is attached, microcontroller will set the this gpio pin to high." - "If 4xDP cable is attached, microcontroller will set the this pin to low." - EndPage - - Page "DisplayPort Redriver Configuration" - - Combo $EFP3_OnBoard_Redriver_Present, "Non-dock topology:", &No_Yes_List, - Help "This feature will describe if Non-dock topology/OnBoard Redriver DP Link is present or not." - - Combo $EFP3_OnBoard_PreEmph_Level, " Pre-Emphasis Level:", &eDP_Link_PreEmp_List, - Help "This feature allows for the selection of " - "Pre-emphasis level for the OnBoard redriver DP link.\n" - "\r\n\n\t\t\tDefault Swing Setting Table\n" - "\t---------------------------------------------------------------------------------------------------\n" - "\t \t | \t\t PreEmphasis Levels\t\t |\n" - "\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\n " - "\t---------------------------------------------------------------------------------------------------\n" - "\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\n" - "\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\n" - "\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\n" - "\t| Level 3(1200mV) | 1200mV | N/A | N/A | N/A |\n" - "\t---------------------------------------------------------------------------------------------------\n" - "\tColumn - Non-Transition VDiff \r\n" - "\tRow - Transition VDiff \r\n" - - - Combo $EFP3_OnBoard_VSwing_Level, " Voltage Swing Level:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of " - "Voltage Swing level for the OnBoard redriver DP link.\n" - "\r\n\n\t\t\tDefault Swing Setting Table\n" - "\t---------------------------------------------------------------------------------------------------\n" - "\t \t | \t\t PreEmphasis Levels\t\t |\n" - "\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\n " - "\t---------------------------------------------------------------------------------------------------\n" - "\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\n" - "\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\n" - "\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\n" - "\t| Level 3(1200mV) | 1200mV | N/A | N/A | N/A |\n" - "\t---------------------------------------------------------------------------------------------------\n" - "\tColumn - Non-Transition VDiff \r\n" - "\tRow - Transition VDiff \r\n" - - - Title " " - - Combo $EFP3_OnDock_Redriver_Present, "Dock Topology: (Mobile only)", &No_Yes_List, - Help "This feature will describe if Dock Topology/Dock Redriver DP Link is present or not.\r\n\r\n" - "Note: For Dock Topology to work SBIOS should implement a GOP Policy Protocol to provide the" - " docking status of the platform to GOP.\n" - - Combo $EFP3_OnDock_PreEmph_Level, " Pre-Emphasis Level:", &eDP_Link_PreEmp_List, - Help "This feature allows for the selection of " - "Pre-emphasis level for the Dock redriver DP link." - "\r\n\n\t\t\tDefault Swing Setting Table\n" - "\t---------------------------------------------------------------------------------------------------\n" - "\t \t | \t\t PreEmphasis Levels\t\t |\n" - "\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\n " - "\t---------------------------------------------------------------------------------------------------\n" - "\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\n" - "\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\n" - "\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\n" - "\t| Level 3(1200mV) | 1200mV | N/A | N/A | N/A |\n" - "\t---------------------------------------------------------------------------------------------------\n" - "\tColumn - Non-Transition VDiff \r\n" - "\tRow - Transition VDiff \r\n" - - Combo $EFP3_OnDock_VSwing_Level, " Voltage Swing Level:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of " - "Voltage Swing level for the Dock redriver DP link." - "\r\n\n\t\t\tDefault Swing Setting Table\n" - "\t---------------------------------------------------------------------------------------------------\n" - "\t \t | \t\t PreEmphasis Levels\t\t |\n" - "\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\n " - "\t---------------------------------------------------------------------------------------------------\n" - "\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\n" - "\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\n" - "\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\n" - "\t| Level 3(1200mV) | 1200mV | N/A | N/A | N/A |\n" - "\t---------------------------------------------------------------------------------------------------\n" - "\tColumn - Non-Transition VDiff \r\n" - "\tRow - Transition VDiff \r\n" - - EndPage ; "DisplayPort Redriver Configuration" - ; "This option is used only by the GFX driver." - - EndPage - - -EndPage - - - - -;============================================================================ -; Page - LFP Panel configuration -;---------------------------------------------------------------------------- -Page "LFP Panel configuration" - Link "Panel #1 ", "Panel #1 " - Link "Panel #2 ", "Panel #2 " - Link "Panel #3 ", "Panel #3 " - Link "Panel #4 ", "Panel #4 " - Link "Panel #5 ", "Panel #5 " - Link "Panel #6 ", "Panel #6 " - Link "Panel #7 ", "Panel #7 " - Link "Panel #8 ", "Panel #8 " - Link "Panel #9 ", "Panel #9 " - Link "Panel #10 ", "Panel #10 " - Link "Panel #11 ", "Panel #11 " - Link "Panel #12 ", "Panel #12 " - Link "Panel #13 ", "Panel #13 " - Link "Panel #14 ", "Panel #14 " - Link "Panel #15 ", "Panel #15 " - Link "Panel #16 ", "Panel #16 " - -;============================================================================== -; Page - Panel #1 (640x480) Flat Panel parameters -;------------------------------------------------------------------------------ - -Page "Panel #1 " - - TitleB "Common LFP Features" - - EditText $Panel_Name_01, "\tLFP Panel Name:", - Help "This feature defines the LVDS panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated. " - - Combo $Enable_Scaling_01, "\tScale to Target Resolution:", &No_Yes_List, - Help "Selecting this feature will make the graphics driver to enable Scaling feature by taking the Horizontal and Vertical resolution\r\n" - "from Target X-Res and Target Y-Res fields.\r\n" - - EditNum $Panel_Width_01, "\tTarget X-Res:", DEC, - Help "This value specifies the Target X-Resolution for this panel." - - EditNum $Panel_Height_01, "\tTarget Y-Res:", DEC, - Help "This value specifies the Target Y-Resolutoin for this panel." - "lines) for this panel." - - - Combo $DPS_Panel_Type_01, "\tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n " - "Intel SDRRS Technology is a feature of the Intel graphics driver\r\n" - "which reduces display power\r\n" - "SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n" - "rate will not adversely impact the user experience\r\n" - "Seamless:- Allows power savings when on battery mode and when a lower refresh\r\n" - "rate will not adversely impact the user experience.Implements seamless refresh\r\n" - "rate switching, which eliminates the screen blink that occurred\r\n" - "during the refresh rate transitions\r\n" - - EditNum $Seamless_DRRS_Min_RR_01, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, - Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n\n" - "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" - - Combo $Blt_Control_01, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology.\r\n " - - Title " " - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "DTD Timings Table" , "DTD Timings" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - - - - #if ($Int_LFP1_Type == 0x1806) - TitleB "Integrated eDP Features" - - Combo $Enable_SSC01, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " - Combo $eDP_Panel_Color_Depth_01, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used. " - - Combo $eDP_VSwingPreEmph_1, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For CherryTrail, based on the selection respective table will be used.\r\n" - "Tables for CherryTrail:-\r\n" - "------------------------------------------------------------------------------------------------------\n" - "|Low Power VSwing Pre-Emphasis Setting Table |\n" - "-----------------------------------------------------------------------------------------------------|\n" - "| | Pre-Emphasis (db) |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" - "| Voltage |------------------------------------------------------------------------- ---------------|\n" - "| Swing | Level 0/200 | 200mV,0db | 200mV,3.5db | 200mV,6db | 200mV,9db |\n" - "| (mV) |------------------------------------------------------------------------------------------|\n" - "| | Level 1/250 | 250mV,0db | 250mV,3.5db | 250mV,6db | NA |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | Level 2/300 | 300mV,0db | 300mV,3.5d | NA | NA |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | Level 3/350 | 350 mv, 0db | NA | NA | NA |\n" - "-----------------------------------------------------------------------------------------------------\n\n" - - "-----------------------------------------------------------------------------------------------------\n" - "|Default VSwing Pre-Emphasis Setting Table |\n" - "---------------------------------------------------------------------------------------------------|\n" - "| | Pre-Emphasis (db) |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" - "| Voltage |----------------------------------------------------------------------------------------|\n" - "| Swing | Level 0/400 | 400mV,0db | 400mV,3.5db | 400mV,6db | 400mV,9db |\n" - "| (mV) |----------------------------------------------------------------------------------------|\n" - "| | Level 1/600 | 600mV,0db | 600mV,3.5db | 600mV,6db | NA |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | Level 2/800 | 800mV,0db | 800mV,3.5db | NA | NA |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | Level 3/1200| 1200mV, 0db | NA | NA | NA |\n" - "-----------------------------------------------------------------------------------------------------\n\n" - - - Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Power Sequencing" - Link "eDP Fast Link Training Configuration" , "eDP Fast Link Training Configuration" - - Page "eDP Panel Power Sequencing" - Link "Close Table", ".." - - Combo $eDP_T3_Optimization_01, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/Graphics driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_01, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_01, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_01, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_01, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_01, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_01, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_01, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - - EndPage - - Page "eDP Fast Link Training Configuration" - - Link "Close Table" , ".." - Combo $Fast_Link_Training_Supported_01, " Is FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature if set to Yes will enable " - "Fast Link Training for eDp, if Panel also supports it." - - Combo $eDP_Link_DataRate_01, " Data Rate:", &eDP_Link_DataRate_List, - Help "This feature allows for the selection of the " - "Data Rate for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_01, " Lane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the " - "Lane Count (Port Width) for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_01, " Pre-Emphasis:", &eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the " - "Pre-emphasis value for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - - "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - "Column - Non-Transition VDiff \r\n" - "Row - Transition VDiff \r\n" - - Combo $eDP_Link_Vswing_01, " Voltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the " - "Voltage Swing value for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - - "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - "Column - Non-Transition VDiff \r\n" - "Row - Transition VDiff \r\n" - EndPage - #endif - Page "DTD Timings" - - Link "Close Table" , ".." - - Table $DVO_Tbl_01 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD " - "timings parameters related to the LFP. The " - "table is the 18-byte DTD structure defined in the " - "VESA EDID version 1.x.\r\n" - "\r\n" - "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" - "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tDB ?\t; Vertical Active in lines, LSB\r\n" - "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Horizontal Image Size, LSB\r\n" - "\tDB ?\t; Vertical Image Size, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tDB 0\t; Horizontal Border in pixels\r\n" - "\tDB 0\t; Vertical Border in lines\r\n" - "\tDB ?\t; Flags:\r\n" - "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t; Bit 6-5: 00 = Reserved\r\n" - "\t \t; Bit 4-3: 11 = Digital Separate\r\n" - "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 0: 0 = Reserved" - - EndPage - - Page "LFP PnP ID" - - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_01 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor / " - "Product ID starting at offset 08h to be used as a " - "PnP ID.\r\n" - "\r\n" - " Table Definition:\r\n" - " Word: ID Manufacturer Name\r\n" - " Word: ID Product Code\r\n" - " DWord: ID Serial Number\r\n" - " Byte: Week of Manufacture\r\n" - " Byte: Year of Manufacture" - - EndPage - - Page "Backlight Control Parameters" - - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_1, " Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the " - "Backlight Inverter type that is to be used to " - "control the backlight brightness of the LFP. When " - "PWM is selected, the driver and VBIOS will control " - "the backlight brightness via the integrated PWM " - "solution for the applicable chipsets. When I2C is " - "selected, the driver and VBIOS will control the " - "backlight brightness via the I2C solution for the " - "applicable chipsets. When None/External is " - "selected, the system BIOS will control the backlight " - "brightness via the external solution." - - Combo $Lfp_Pwm_Source_Selection_01, " Pwm Source Selection:", &Edp_Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - "\r\n" - - Combo $BLC_Inv_Polarity_1, " Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity " - "to be specified.\r\n" - "\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_1, " Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum " - "backlight brightness setting. The graphics driver " - "will never decrease the backlight less than this " - "value. The value must be specified using normal " - "polarity semantics." - - EditNum $POST_BL_Brightness_01, " POST Backlight Intensity:", DEC, - Help "This feature is used to set default brightness value at POST." - "This is configurable field of 0-255. Value of 0 indicates 0 brightness, 255 indicates maximum brightness. " - - EditNum $PWM_Frequency_1, " PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the " - "frequency needed for PWM Inverter.\r\n" - "\r\n" - "Note: The frequency range, entered as a decimal " - "number, for the integrated PWM is 200Hz - 40KHz." - - EndPage - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_1, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - Combo $Override_EDID_Data_1, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - EditNum $Red_Green_1, " Red_Green_bits (Bits 1&0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - EditNum $Blue_White_1, " Blue_White_bits (Bits 1&0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - EditNum $Red_x_1, " Red_x (Bits 9->2 at 1Bh)" , EHEX, - Help " Bits 9->2 of red color x coordinate" - EditNum $Red_y_1, " Red_y (Bits 9->2 at 1Ch)" , EHEX, - Help " Bits 9->2 of red color y coordinate" - EditNum $Green_x_1, " Green_x (Bits 9->2 at 1Dh)" , EHEX, - Help " Bits 9->2 of Green color x coordinate" - EditNum $Green_y_1, " Green_y (Bits 9->2 at 1Eh)" , EHEX, - Help " Bits 9->2 of Green color y coordinate" - EditNum $Blue_x_1, " Blue_x (Bits 9->2 at 1Fh)" , EHEX, - Help " Bits 9->2 of Blue color x coordinate" - EditNum $Blue_y_1, " Blue_y (Bits 9->2 at 20h)" , EHEX, - Help " Bits 9->2 of Blue color y coordinate" - EditNum $White_x_1, " White_x (Bits 9->2 at 21h)" , EHEX, - Help " Bits 9->2 of White color x coordinate" - EditNum $White_y_1, " White_y (Bits 9->2 at 22h)" , EHEX, - Help " Bits 9->2 of White color y coordinate" - - EndPage ; Chromaticity Control - - - - -EndPage - -;============================================================================== -; Page - Panel #2 (800x600) Flat Panel parameters -;------------------------------------------------------------------------------ - -Page "Panel #2 " - - TitleB "Common LFP Features" - - EditText $Panel_Name_02, "\tLFP Panel Name:", - Help "This feature defines the LVDS panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated. " - - Combo $Enable_Scaling_02, "\tScale to Target Resolution:", &No_Yes_List, - Help "Selecting this feature will make the graphics driver to enable Scaling feature by taking the Horizontal and Vertical resolution\r\n" - "from Target X-Res and Target Y-Res fields.\r\n" - - EditNum $Panel_Width_02, "\tTarget X-Res:", DEC, - Help "This value specifies the Target X-Resolution for this panel." - - EditNum $Panel_Height_02, "\tTarget Y-Res:", DEC, - Help "This value specifies the Target Y-Resolutoin for this panel." - - - Combo $DPS_Panel_Type_02, " \tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n " - "Intel SDRRS Technology is a feature of the Intel graphics driver\r\n" - "which reduces display power\r\n" - "SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n" - "rate will not adversely impact the user experience\r\n" - "Seamless:- Allows power savings when on battery mode and when a lower refresh\r\n" - "rate will not adversely impact the user experience.Implements seamless refresh\r\n" - "rate switching, which eliminates the screen blink that occurred\r\n" - "during the refresh rate transitions\r\n" - - EditNum $Seamless_DRRS_Min_RR_02, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, - Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n\n" - "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" - - Combo $Blt_Control_02, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology.\r\n " - - Title " " - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "DTD Timings Table" , "DTD Timings" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - - - - #if ($Int_LFP1_Type == 0x1806) - TitleB "Integrated eDP Features" - - - Combo $Enable_SSC02, " \teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " - Combo $eDP_Panel_Color_Depth_02, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used. " - - Combo $eDP_VSwingPreEmph_2, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For CherryTrail, based on the selection respective table will be used.\r\n" - "Tables for CherryTrail:-\r\n" - "------------------------------------------------------------------------------------------------------\n" - "|Low Power VSwing Pre-Emphasis Setting Table |\n" - "-----------------------------------------------------------------------------------------------------|\n" - "| | Pre-Emphasis (db) |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" - "| Voltage |------------------------------------------------------------------------- ---------------|\n" - "| Swing | Level 0/200 | 200mV,0db | 200mV,3.5db | 200mV,6db | 200mV,9db |\n" - "| (mV) |------------------------------------------------------------------------------------------|\n" - "| | Level 1/250 | 250mV,0db | 250mV,3.5db | 250mV,6db | NA |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | Level 2/300 | 300mV,0db | 300mV,3.5d | NA | NA |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | Level 3/350 | 350 mv, 0db | NA | NA | NA |\n" - "-----------------------------------------------------------------------------------------------------\n\n" - - "-----------------------------------------------------------------------------------------------------\n" - "|Default VSwing Pre-Emphasis Setting Table |\n" - "---------------------------------------------------------------------------------------------------|\n" - "| | Pre-Emphasis (db) |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" - "| Voltage |----------------------------------------------------------------------------------------|\n" - "| Swing | Level 0/400 | 400mV,0db | 400mV,3.5db | 400mV,6db | 400mV,9db |\n" - "| (mV) |----------------------------------------------------------------------------------------|\n" - "| | Level 1/600 | 600mV,0db | 600mV,3.5db | 600mV,6db | NA |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | Level 2/800 | 800mV,0db | 800mV,3.5db | NA | NA |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | Level 3/1200| 1200mV, 0db | NA | NA | NA |\n" - "-----------------------------------------------------------------------------------------------------\n\n" - - - Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Power Sequencing" - Link "eDP Fast Link Training Configuration" , "eDP Fast Link Training Configuration" - - Page "eDP Panel Power Sequencing" - Link "Close Table", ".." - - Combo $eDP_T3_Optimization_02, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/Graphics driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_02, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_02, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_02, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_02, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_02, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_02, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_02, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - - EndPage - - Page "eDP Fast Link Training Configuration" - - Link "Close Table" , ".." - Combo $Fast_Link_Training_Supported_02, " Is FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature if set to Yes will enable " - "Fast Link Training for eDp, if Panel also supports it." - - Combo $eDP_Link_DataRate_02, " Data Rate:", &eDP_Link_DataRate_List, - Help "This feature allows for the selection of the " - "Data Rate for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_02, " Lane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the " - "Lane Count (Port Width) for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_02, " Pre-Emphasis:", &eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the " - "Pre-emphasis value for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - - "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - "Column - Non-Transition VDiff \r\n" - "Row - Transition VDiff \r\n" - - Combo $eDP_Link_Vswing_02, " Voltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the " - "Voltage Swing value for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - - "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - "Column - Non-Transition VDiff \r\n" - "Row - Transition VDiff \r\n" - EndPage - #endif - - Page "DTD Timings" - - Link "Close Table" , ".." - - Table $DVO_Tbl_02 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD " - "timings parameters related to the LFP. The " - "table is the 18-byte DTD structure defined in the " - "VESA EDID version 1.x.\r\n" - "\r\n" - "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" - "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tDB ?\t; Vertical Active in lines, LSB\r\n" - "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Horizontal Image Size, LSB\r\n" - "\tDB ?\t; Vertical Image Size, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tDB 0\t; Horizontal Border in pixels\r\n" - "\tDB 0\t; Vertical Border in lines\r\n" - "\tDB ?\t; Flags:\r\n" - "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t; Bit 6-5: 00 = Reserved\r\n" - "\t \t; Bit 4-3: 11 = Digital Separate\r\n" - "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 0: 0 = Reserved" - - EndPage - - Page "LFP PnP ID" - - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_02 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor / " - "Product ID starting at offset 08h to be used as a " - "PnP ID.\r\n" - "\r\n" - " Table Definition:\r\n" - " Word: ID Manufacturer Name\r\n" - " Word: ID Product Code\r\n" - " DWord: ID Serial Number\r\n" - " Byte: Week of Manufacture\r\n" - " Byte: Year of Manufacture" - - EndPage - - Page "Backlight Control Parameters" - - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_2, " Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the " - "Backlight Inverter type that is to be used to " - "control the backlight brightness of the LFP. When " - "PWM is selected, the driver and VBIOS will control " - "the backlight brightness via the integrated PWM " - "solution for the applicable chipsets. When I2C is " - "selected, the driver and VBIOS will control the " - "backlight brightness via the I2C solution for the " - "applicable chipsets. When None/External is " - "selected, the system BIOS will control the backlight " - "brightness via the external solution." - - Combo $Lfp_Pwm_Source_Selection_02, " Pwm Source Selection:", &Edp_Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - "\r\n" - - Combo $BLC_Inv_Polarity_2, " Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity " - "to be specified.\r\n" - "\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_2, " Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum " - "backlight brightness setting. The graphics driver " - "will never decrease the backlight less than this " - "value. The value must be specified using normal " - "polarity semantics." - - EditNum $POST_BL_Brightness_02, " POST Backlight Intensity:", DEC, - Help "This feature is used to set default brightness value at POST." - "This is configurable field of 0-255. Value of 0 indicates 0 brightness, 255 indicates maximum brightness. " - - EditNum $PWM_Frequency_2, " PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the " - "frequency needed for PWM Inverter.\r\n" - "\r\n" - "Note: The frequency range, entered as a decimal " - "number, for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_2, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - Combo $Override_EDID_Data_2, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - EditNum $Red_Green_2, " Red_Green_bits (Bits 1&0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - EditNum $Blue_White_2, " Blue_White_bits (Bits 1&0 at 20h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - EditNum $Red_x_2, " Red_x (Bits 9->2 at 1Bh)" , EHEX, - Help " Bits 9->2 of red color x coordinate" - EditNum $Red_y_2, " Red_y (Bits 9->2 at 1Ch)" , EHEX, - Help " Bits 9->2 of red color y coordinate" - EditNum $Green_x_2, " Green_x (Bits 9->2 at 1Dh)" , EHEX, - Help " Bits 9->2 of Green color x coordinate" - EditNum $Green_y_2, " Green_y (Bits 9->2 at 1Eh)" , EHEX, - Help " Bits 9->2 of Green color y coordinate" - EditNum $Blue_x_2, " Blue_x (Bits 9->2 at 1Fh)" , EHEX, - Help " Bits 9->2 of Blue color x coordinate" - EditNum $Blue_y_2, " Blue_y (Bits 9->2 at 20h)" , EHEX, - Help " Bits 9->2 of Blue color y coordinate" - EditNum $White_x_2, " White_x (Bits 9->2 at 21h)" , EHEX, - Help " Bits 9->2 of White color x coordinate" - EditNum $White_y_2, " White_y (Bits 9->2 at 22h)" , EHEX, - Help " Bits 9->2 of White color y coordinate" - - EndPage ; Chromaticity Control - - -EndPage - - -;============================================================================== -; Page - Panel #3 (1024x768 LVDS) Flat Panel parameters -;------------------------------------------------------------------------------ - -Page "Panel #3 " - - TitleB "Common LFP Features" - - EditText $Panel_Name_03, "\tLFP Panel Name:", - Help "This feature defines the LVDS panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated. " - - Combo $Enable_Scaling_03, "\tScale to Target Resolution:", &No_Yes_List, - Help "Selecting this feature will make the graphics driver to enable Scaling feature by taking the Horizontal and Vertical resolution\r\n" - "from Target X-Res and Target Y-Res fields.\r\n" - - EditNum $Panel_Width_03, "\tTarget X-Res:", DEC, - Help "This value specifies the Target X-Resolution for this panel." - - EditNum $Panel_Height_03, "\tTarget Y-Res:", DEC, - Help "This value specifies the Target Y-Resolutoin for this panel." - - - Combo $DPS_Panel_Type_03, " \tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n " - "Intel SDRRS Technology is a feature of the Intel graphics driver\r\n" - "which reduces display power\r\n" - "SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n" - "rate will not adversely impact the user experience\r\n" - "Seamless:- Allows power savings when on battery mode and when a lower refresh\r\n" - "rate will not adversely impact the user experience.Implements seamless refresh\r\n" - "rate switching, which eliminates the screen blink that occurred\r\n" - "during the refresh rate transitions\r\n" - - EditNum $Seamless_DRRS_Min_RR_03, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, - Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n\n" - "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" - - Combo $Blt_Control_03, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology.\r\n " - - Title " " - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "DTD Timings Table" , "DTD Timings" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - - - - #if ($Int_LFP1_Type == 0x1806) - TitleB "Integrated eDP Features" - - - Combo $Enable_SSC03, " \teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " - - - Combo $eDP_Panel_Color_Depth_03, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used. " - - Combo $eDP_VSwingPreEmph_3, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For CherryTrail, based on the selection respective table will be used.\r\n" - "Tables for CherryTrail:-\r\n" - "------------------------------------------------------------------------------------------------------\n" - "|Low Power VSwing Pre-Emphasis Setting Table |\n" - "-----------------------------------------------------------------------------------------------------|\n" - "| | Pre-Emphasis (db) |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" - "| Voltage |------------------------------------------------------------------------- ---------------|\n" - "| Swing | Level 0/200 | 200mV,0db | 200mV,3.5db | 200mV,6db | 200mV,9db |\n" - "| (mV) |------------------------------------------------------------------------------------------|\n" - "| | Level 1/250 | 250mV,0db | 250mV,3.5db | 250mV,6db | NA |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | Level 2/300 | 300mV,0db | 300mV,3.5d | NA | NA |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | Level 3/350 | 350 mv, 0db | NA | NA | NA |\n" - "-----------------------------------------------------------------------------------------------------\n\n" - - "-----------------------------------------------------------------------------------------------------\n" - "|Default VSwing Pre-Emphasis Setting Table |\n" - "---------------------------------------------------------------------------------------------------|\n" - "| | Pre-Emphasis (db) |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" - "| Voltage |----------------------------------------------------------------------------------------|\n" - "| Swing | Level 0/400 | 400mV,0db | 400mV,3.5db | 400mV,6db | 400mV,9db |\n" - "| (mV) |----------------------------------------------------------------------------------------|\n" - "| | Level 1/600 | 600mV,0db | 600mV,3.5db | 600mV,6db | NA |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | Level 2/800 | 800mV,0db | 800mV,3.5db | NA | NA |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | Level 3/1200| 1200mV, 0db | NA | NA | NA |\n" - "-----------------------------------------------------------------------------------------------------\n\n" - - - Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Power Sequencing" - Link "eDP Fast Link Training Configuration" , "eDP Fast Link Training Configuration" - - Page "eDP Panel Power Sequencing" - Link "Close Table", ".." - - Combo $eDP_T3_Optimization_03, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/Graphics driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_03, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_03, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_03, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_03, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_03, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_03, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_03, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - - EndPage - - Page "eDP Fast Link Training Configuration" - - Link "Close Table" , ".." - Combo $Fast_Link_Training_Supported_03, " Is FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature if set to Yes will enable " - "Fast Link Training for eDp, if Panel also supports it." - - Combo $eDP_Link_DataRate_03, " Data Rate:", &eDP_Link_DataRate_List, - Help "This feature allows for the selection of the " - "Data Rate for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_03, " Lane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the " - "Lane Count (Port Width) for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_03, " Pre-Emphasis:", &eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the " - "Pre-emphasis value for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - - "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - "Column - Non-Transition VDiff \r\n" - "Row - Transition VDiff \r\n" - - Combo $eDP_Link_Vswing_03, " Voltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the " - "Voltage Swing value for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - - "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - "Column - Non-Transition VDiff \r\n" - "Row - Transition VDiff \r\n" - EndPage - #endif - - Page "DTD Timings" - - Link "Close Table" , ".." - - Table $DVO_Tbl_03 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD " - "timings parameters related to the LFP. The " - "table is the 18-byte DTD structure defined in the " - "VESA EDID version 1.x.\r\n" - "\r\n" - "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" - "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tDB ?\t; Vertical Active in lines, LSB\r\n" - "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Horizontal Image Size, LSB\r\n" - "\tDB ?\t; Vertical Image Size, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tDB 0\t; Horizontal Border in pixels\r\n" - "\tDB 0\t; Vertical Border in lines\r\n" - "\tDB ?\t; Flags:\r\n" - "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t; Bit 6-5: 00 = Reserved\r\n" - "\t \t; Bit 4-3: 11 = Digital Separate\r\n" - "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 0: 0 = Reserved" - - EndPage - - Page "LFP PnP ID" - - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_03 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor / " - "Product ID starting at offset 08h to be used as a " - "PnP ID.\r\n" - "\r\n" - " Table Definition:\r\n" - " Word: ID Manufacturer Name\r\n" - " Word: ID Product Code\r\n" - " DWord: ID Serial Number\r\n" - " Byte: Week of Manufacture\r\n" - " Byte: Year of Manufacture" - - EndPage - - Page "Backlight Control Parameters" - - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_3, " Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the " - "Backlight Inverter type that is to be used to " - "control the backlight brightness of the LFP. When " - "PWM is selected, the driver and VBIOS will control " - "the backlight brightness via the integrated PWM " - "solution for the applicable chipsets. When I2C is " - "selected, the driver and VBIOS will control the " - "backlight brightness via the I2C solution for the " - "applicable chipsets. When None/External is " - "selected, the system BIOS will control the backlight " - "brightness via the external solution." - - Combo $Lfp_Pwm_Source_Selection_03, " Pwm Source Selection:", &Edp_Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - "\r\n" - - Combo $BLC_Inv_Polarity_3, " Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity " - "to be specified.\r\n" - "\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_3, " Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum " - "backlight brightness setting. The graphics driver " - "will never decrease the backlight less than this " - "value. The value must be specified using normal " - "polarity semantics." - -EditNum $POST_BL_Brightness_03, " POST Backlight Intensity:", DEC, - Help "This feature is used to set default brightness value at POST." - "This is configurable field of 0-255. Value of 0 indicates 0 brightness, 255 indicates maximum brightness. " - - EditNum $PWM_Frequency_3, " PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the " - "frequency needed for PWM Inverter.\r\n" - "\r\n" - "Note: The frequency range, entered as a decimal " - "number, for the integrated PWM is 200Hz - 40KHz." - EndPage - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_3, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - Combo $Override_EDID_Data_3, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - EditNum $Red_Green_3, " Red_Green_bits (Bits 1&0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - EditNum $Blue_White_3, " Blue_White_bits (Bits 1&0 at 20h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - EditNum $Red_x_3, " Red_x (Bits 9->2 at 1Bh)" , EHEX, - Help " Bits 9->2 of red color x coordinate" - EditNum $Red_y_3, " Red_y (Bits 9->2 at 1Ch)" , EHEX, - Help " Bits 9->2 of red color y coordinate" - EditNum $Green_x_3, " Green_x (Bits 9->2 at 1Dh)" , EHEX, - Help " Bits 9->2 of Green color x coordinate" - EditNum $Green_y_3, " Green_y (Bits 9->2 at 1Eh)" , EHEX, - Help " Bits 9->2 of Green color y coordinate" - EditNum $Blue_x_3, " Blue_x (Bits 9->2 at 1Fh)" , EHEX, - Help " Bits 9->2 of Blue color x coordinate" - EditNum $Blue_y_3, " Blue_y (Bits 9->2 at 20h)" , EHEX, - Help " Bits 9->2 of Blue color y coordinate" - EditNum $White_x_3, " White_x (Bits 9->2 at 21h)" , EHEX, - Help " Bits 9->2 of White color x coordinate" - EditNum $White_y_3, " White_y (Bits 9->2 at 22h)" , EHEX, - Help " Bits 9->2 of White color y coordinate" - - EndPage ; Chromaticity Control - - - -EndPage - - -;============================================================================== -; Page - Panel #4 (1280x1024 LVDS) Flat Panel parameters -;------------------------------------------------------------------------------ - -Page "Panel #4 " - - TitleB "Common LFP Features" - - EditText $Panel_Name_04, "\tLFP Panel Name:", - Help "This feature defines the LVDS panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated. " - - Combo $Enable_Scaling_04, "\tScale to Target Resolution:", &No_Yes_List, - Help "Selecting this feature will make the graphics driver to enable Scaling feature by taking the Horizontal and Vertical resolution\r\n" - "from Target X-Res and Target Y-Res fields.\r\n" - - EditNum $Panel_Width_04, "\tTarget X-Res:", DEC, - Help "This value specifies the Target X-Resolution for this panel." - - EditNum $Panel_Height_04, "\tTarget Y-Res:", DEC, - Help "This value specifies the Target Y-Resolutoin for this panel." - - - Combo $DPS_Panel_Type_04, " \tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n " - "Intel SDRRS Technology is a feature of the Intel graphics driver\r\n" - "which reduces display power\r\n" - "SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n" - "rate will not adversely impact the user experience\r\n" - "Seamless:- Allows power savings when on battery mode and when a lower refresh\r\n" - "rate will not adversely impact the user experience.Implements seamless refresh\r\n" - "rate switching, which eliminates the screen blink that occurred\r\n" - "during the refresh rate transitions\r\n" - - EditNum $Seamless_DRRS_Min_RR_04, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, - Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n\n" - "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" - - Combo $Blt_Control_04, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology.\r\n " - - Title " " - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "DTD Timings Table" , "DTD Timings" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - - - - #if ($Int_LFP1_Type == 0x1806) - TitleB "Integrated eDP Features" - - - Combo $Enable_SSC04, " \teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " - - Combo $eDP_Panel_Color_Depth_04, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used. " - - Combo $eDP_VSwingPreEmph_4, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For CherryTrail, based on the selection respective table will be used.\r\n" - "Tables for CherryTrail:-\r\n" - "------------------------------------------------------------------------------------------------------\n" - "|Low Power VSwing Pre-Emphasis Setting Table |\n" - "-----------------------------------------------------------------------------------------------------|\n" - "| | Pre-Emphasis (db) |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" - "| Voltage |------------------------------------------------------------------------- ---------------|\n" - "| Swing | Level 0/200 | 200mV,0db | 200mV,3.5db | 200mV,6db | 200mV,9db |\n" - "| (mV) |------------------------------------------------------------------------------------------|\n" - "| | Level 1/250 | 250mV,0db | 250mV,3.5db | 250mV,6db | NA |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | Level 2/300 | 300mV,0db | 300mV,3.5d | NA | NA |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | Level 3/350 | 350 mv, 0db | NA | NA | NA |\n" - "-----------------------------------------------------------------------------------------------------\n\n" - - "-----------------------------------------------------------------------------------------------------\n" - "|Default VSwing Pre-Emphasis Setting Table |\n" - "---------------------------------------------------------------------------------------------------|\n" - "| | Pre-Emphasis (db) |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" - "| Voltage |----------------------------------------------------------------------------------------|\n" - "| Swing | Level 0/400 | 400mV,0db | 400mV,3.5db | 400mV,6db | 400mV,9db |\n" - "| (mV) |----------------------------------------------------------------------------------------|\n" - "| | Level 1/600 | 600mV,0db | 600mV,3.5db | 600mV,6db | NA |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | Level 2/800 | 800mV,0db | 800mV,3.5db | NA | NA |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | Level 3/1200| 1200mV, 0db | NA | NA | NA |\n" - "-----------------------------------------------------------------------------------------------------\n\n" - - - Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Power Sequencing" - Link "eDP Fast Link Training Configuration" , "eDP Fast Link Training Configuration" - - Page "eDP Panel Power Sequencing" - Link "Close Table", ".." - Combo $eDP_T3_Optimization_04, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/Graphics driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_04, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_04, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_04, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_04, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_04, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_04, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_04, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - - EndPage - - Page "eDP Fast Link Training Configuration" - - Link "Close Table" , ".." - Combo $Fast_Link_Training_Supported_04, " Is FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature if set to Yes will enable " - "Fast Link Training for eDp, if Panel also supports it." - - Combo $eDP_Link_DataRate_04, " Data Rate:", &eDP_Link_DataRate_List, - Help "This feature allows for the selection of the " - "Data Rate for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_04, " Lane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the " - "Lane Count (Port Width) for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_04, " Pre-Emphasis:", &eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the " - "Pre-emphasis value for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - - "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - "Column - Non-Transition VDiff \r\n" - "Row - Transition VDiff \r\n" - - Combo $eDP_Link_Vswing_04, " Voltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the " - "Voltage Swing value for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - - "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - "Column - Non-Transition VDiff \r\n" - "Row - Transition VDiff \r\n" - EndPage - #endif - - Page "DTD Timings" - - Link "Close Table" , ".." - - Table $DVO_Tbl_04 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD " - "timings parameters related to the LFP. The " - "table is the 18-byte DTD structure defined in the " - "VESA EDID version 1.x.\r\n" - "\r\n" - "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" - "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tDB ?\t; Vertical Active in lines, LSB\r\n" - "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Horizontal Image Size, LSB\r\n" - "\tDB ?\t; Vertical Image Size, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tDB 0\t; Horizontal Border in pixels\r\n" - "\tDB 0\t; Vertical Border in lines\r\n" - "\tDB ?\t; Flags:\r\n" - "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t; Bit 6-5: 00 = Reserved\r\n" - "\t \t; Bit 4-3: 11 = Digital Separate\r\n" - "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 0: 0 = Reserved" - - EndPage - - Page "LFP PnP ID" - - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_04 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor / " - "Product ID starting at offset 08h to be used as a " - "PnP ID.\r\n" - "\r\n" - " Table Definition:\r\n" - " Word: ID Manufacturer Name\r\n" - " Word: ID Product Code\r\n" - " DWord: ID Serial Number\r\n" - " Byte: Week of Manufacture\r\n" - " Byte: Year of Manufacture" - - EndPage - - Page "Backlight Control Parameters" - - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_4, " Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the " - "Backlight Inverter type that is to be used to " - "control the backlight brightness of the LFP. When " - "PWM is selected, the driver and VBIOS will control " - "the backlight brightness via the integrated PWM " - "solution for the applicable chipsets. When I2C is " - "selected, the driver and VBIOS will control the " - "backlight brightness via the I2C solution for the " - "applicable chipsets. When None/External is " - "selected, the system BIOS will control the backlight " - "brightness via the external solution." - - Combo $Lfp_Pwm_Source_Selection_04, " Pwm Source Selection:", &Edp_Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - "\r\n" - - Combo $BLC_Inv_Polarity_4, " Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity " - "to be specified.\r\n" - "\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_4, " Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum " - "backlight brightness setting. The graphics driver " - "will never decrease the backlight less than this " - "value. The value must be specified using normal " - "polarity semantics." - -EditNum $POST_BL_Brightness_04, " POST Backlight Intensity:", DEC, - Help "This feature is used to set default brightness value at POST." - "This is configurable field of 0-255. Value of 0 indicates 0 brightness, 255 indicates maximum brightness. " - - EditNum $PWM_Frequency_4, " PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the " - "frequency needed for PWM Inverter.\r\n" - "\r\n" - "Note: The frequency range, entered as a decimal " - "number, for the integrated PWM is 200Hz - 40KHz." - EndPage - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_4, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - Combo $Override_EDID_Data_4, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - EditNum $Red_Green_4, " Red_Green_bits (Bits 1&0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - EditNum $Blue_White_4, " Blue_White_bits (Bits 1&0 at 20h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - EditNum $Red_x_4, " Red_x (Bits 9->2 at 1Bh)" , EHEX, - Help " Bits 9->2 of red color x coordinate" - EditNum $Red_y_4, " Red_y (Bits 9->2 at 1Ch)" , EHEX, - Help " Bits 9->2 of red color y coordinate" - EditNum $Green_x_4, " Green_x (Bits 9->2 at 1Dh)" , EHEX, - Help " Bits 9->2 of Green color x coordinate" - EditNum $Green_y_4, " Green_y (Bits 9->2 at 1Eh)" , EHEX, - Help " Bits 9->2 of Green color y coordinate" - EditNum $Blue_x_4, " Blue_x (Bits 9->2 at 1Fh)" , EHEX, - Help " Bits 9->2 of Blue color x coordinate" - EditNum $Blue_y_4, " Blue_y (Bits 9->2 at 20h)" , EHEX, - Help " Bits 9->2 of Blue color y coordinate" - EditNum $White_x_4, " White_x (Bits 9->2 at 21h)" , EHEX, - Help " Bits 9->2 of White color x coordinate" - EditNum $White_y_4, " White_y (Bits 9->2 at 22h)" , EHEX, - Help " Bits 9->2 of White color y coordinate" - - EndPage ; Chromaticity Control - - - -EndPage - - -;============================================================================== -; Page - Panel #5 (1400x1050 LVDS - Reduced Blank) Flat Panel parameters -;------------------------------------------------------------------------------ - -Page "Panel #5 " - - TitleB "Common LFP Features" - - EditText $Panel_Name_05, "\tLFP Panel Name:", - Help "This feature defines the LVDS panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated. " - - Combo $Enable_Scaling_05, "\tScale to Target Resolution:", &No_Yes_List, - Help "Selecting this feature will make the graphics driver to enable Scaling feature by taking the Horizontal and Vertical resolution\r\n" - "from Target X-Res and Target Y-Res fields.\r\n" - - EditNum $Panel_Width_05, "\tTarget X-Res:", DEC, - Help "This value specifies the Target X-Resolution for this panel." - - EditNum $Panel_Height_05, "\tTarget Y-Res:", DEC, - Help "This value specifies the Target Y-Resolutoin for this panel." - - - Combo $DPS_Panel_Type_05, " \tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n " - "Intel SDRRS Technology is a feature of the Intel graphics driver\r\n" - "which reduces display power\r\n" - "SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n" - "rate will not adversely impact the user experience\r\n" - "Seamless:- Allows power savings when on battery mode and when a lower refresh\r\n" - "rate will not adversely impact the user experience.Implements seamless refresh\r\n" - "rate switching, which eliminates the screen blink that occurred\r\n" - "during the refresh rate transitions\r\n" - - EditNum $Seamless_DRRS_Min_RR_05, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, - Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n\n" - "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" - - Combo $Blt_Control_05, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology.\r\n " - - Title " " - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "DTD Timings Table" , "DTD Timings" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - - - #if ($Int_LFP1_Type == 0x1806) - TitleB "Integrated eDP Features" - Combo $Enable_SSC05, " \teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " - - - - Combo $eDP_Panel_Color_Depth_05, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used. " - - Combo $eDP_VSwingPreEmph_5, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For CherryTrail, based on the selection respective table will be used.\r\n" - "Tables for CherryTrail:-\r\n" - "------------------------------------------------------------------------------------------------------\n" - "|Low Power VSwing Pre-Emphasis Setting Table |\n" - "-----------------------------------------------------------------------------------------------------|\n" - "| | Pre-Emphasis (db) |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" - "| Voltage |------------------------------------------------------------------------- ---------------|\n" - "| Swing | Level 0/200 | 200mV,0db | 200mV,3.5db | 200mV,6db | 200mV,9db |\n" - "| (mV) |------------------------------------------------------------------------------------------|\n" - "| | Level 1/250 | 250mV,0db | 250mV,3.5db | 250mV,6db | NA |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | Level 2/300 | 300mV,0db | 300mV,3.5d | NA | NA |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | Level 3/350 | 350 mv, 0db | NA | NA | NA |\n" - "-----------------------------------------------------------------------------------------------------\n\n" - - "-----------------------------------------------------------------------------------------------------\n" - "|Default VSwing Pre-Emphasis Setting Table |\n" - "---------------------------------------------------------------------------------------------------|\n" - "| | Pre-Emphasis (db) |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" - "| Voltage |----------------------------------------------------------------------------------------|\n" - "| Swing | Level 0/400 | 400mV,0db | 400mV,3.5db | 400mV,6db | 400mV,9db |\n" - "| (mV) |----------------------------------------------------------------------------------------|\n" - "| | Level 1/600 | 600mV,0db | 600mV,3.5db | 600mV,6db | NA |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | Level 2/800 | 800mV,0db | 800mV,3.5db | NA | NA |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | Level 3/1200| 1200mV, 0db | NA | NA | NA |\n" - "-----------------------------------------------------------------------------------------------------\n\n" - - - Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Power Sequencing" - Link "eDP Fast Link Training Configuration" , "eDP Fast Link Training Configuration" - - - Page "eDP Panel Power Sequencing" - Link "Close Table", ".." - Combo $eDP_T3_Optimization_05, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/Graphics driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_05, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_05, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_05, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_05, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_05, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_05, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_05, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - - EndPage - - Page "eDP Fast Link Training Configuration" - - Link "Close Table" , ".." - Combo $Fast_Link_Training_Supported_05, " Is FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature if set to Yes will enable " - "Fast Link Training for eDp, if Panel also supports it." - - Combo $eDP_Link_DataRate_05, " Data Rate:", &eDP_Link_DataRate_List, - Help "This feature allows for the selection of the " - "Data Rate for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_05, " Lane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the " - "Lane Count (Port Width) for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_05, " Pre-Emphasis:", &eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the " - "Pre-emphasis value for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - - "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - "Column - Non-Transition VDiff \r\n" - "Row - Transition VDiff \r\n" - - Combo $eDP_Link_Vswing_05, " Voltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the " - "Voltage Swing value for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - - "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - "Column - Non-Transition VDiff \r\n" - "Row - Transition VDiff \r\n" - EndPage - #endif - - Page "DTD Timings" - - Link "Close Table" , ".." - - Table $DVO_Tbl_05 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD " - "timings parameters related to the LFP. The " - "table is the 18-byte DTD structure defined in the " - "VESA EDID version 1.x.\r\n" - "\r\n" - "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" - "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tDB ?\t; Vertical Active in lines, LSB\r\n" - "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Horizontal Image Size, LSB\r\n" - "\tDB ?\t; Vertical Image Size, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tDB 0\t; Horizontal Border in pixels\r\n" - "\tDB 0\t; Vertical Border in lines\r\n" - "\tDB ?\t; Flags:\r\n" - "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t; Bit 6-5: 00 = Reserved\r\n" - "\t \t; Bit 4-3: 11 = Digital Separate\r\n" - "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 0: 0 = Reserved" - - EndPage - - Page "LFP PnP ID" - - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_05 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor / " - "Product ID starting at offset 08h to be used as a " - "PnP ID.\r\n" - "\r\n" - " Table Definition:\r\n" - " Word: ID Manufacturer Name\r\n" - " Word: ID Product Code\r\n" - " DWord: ID Serial Number\r\n" - " Byte: Week of Manufacture\r\n" - " Byte: Year of Manufacture" - - EndPage - - Page "Backlight Control Parameters" - - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_5, " Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the " - "Backlight Inverter type that is to be used to " - "control the backlight brightness of the LFP. When " - "PWM is selected, the driver and VBIOS will control " - "the backlight brightness via the integrated PWM " - "solution for the applicable chipsets. When I2C is " - "selected, the driver and VBIOS will control the " - "backlight brightness via the I2C solution for the " - "applicable chipsets. When None/External is " - "selected, the system BIOS will control the backlight " - "brightness via the external solution." - - Combo $Lfp_Pwm_Source_Selection_05, " Pwm Source Selection:", &Edp_Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - "\r\n" - - Combo $BLC_Inv_Polarity_5, " Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity " - "to be specified.\r\n" - "\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_5, " Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum " - "backlight brightness setting. The graphics driver " - "will never decrease the backlight less than this " - "value. The value must be specified using normal " - "polarity semantics." - -EditNum $POST_BL_Brightness_05, " POST Backlight Intensity:", DEC, - Help "This feature is used to set default brightness value at POST." - "This is configurable field of 0-255. Value of 0 indicates 0 brightness, 255 indicates maximum brightness. " - - EditNum $PWM_Frequency_5, " PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the " - "frequency needed for PWM Inverter.\r\n" - "\r\n" - "Note: The frequency range, entered as a decimal " - "number, for the integrated PWM is 200Hz - 40KHz." - EndPage - - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_5, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - Combo $Override_EDID_Data_5, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - EditNum $Red_Green_5, " Red_Green_bits (Bits 1&0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - EditNum $Blue_White_5, " Blue_White_bits (Bits 1&0 at 20h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - EditNum $Red_x_5, " Red_x (Bits 9->2 at 1Bh)" , EHEX, - Help " Bits 9->2 of red color x coordinate" - EditNum $Red_y_5, " Red_y (Bits 9->2 at 1Ch)" , EHEX, - Help " Bits 9->2 of red color y coordinate" - EditNum $Green_x_5, " Green_x (Bits 9->2 at 1Dh)" , EHEX, - Help " Bits 9->2 of Green color x coordinate" - EditNum $Green_y_5, " Green_y (Bits 9->2 at 1Eh)" , EHEX, - Help " Bits 9->2 of Green color y coordinate" - EditNum $Blue_x_5, " Blue_x (Bits 9->2 at 1Fh)" , EHEX, - Help " Bits 9->2 of Blue color x coordinate" - EditNum $Blue_y_5, " Blue_y (Bits 9->2 at 20h)" , EHEX, - Help " Bits 9->2 of Blue color y coordinate" - EditNum $White_x_5, " White_x (Bits 9->2 at 21h)" , EHEX, - Help " Bits 9->2 of White color x coordinate" - EditNum $White_y_5, " White_y (Bits 9->2 at 22h)" , EHEX, - Help " Bits 9->2 of White color y coordinate" - - EndPage ; Chromaticity Control - -EndPage - - -;============================================================================== -; Page - Panel #6 (1400x1050) Flat Panel parameters -;------------------------------------------------------------------------------ - -Page "Panel #6 " - - TitleB "Common LFP Features" - - EditText $Panel_Name_06, "\tLFP Panel Name:", - Help "This feature defines the LVDS panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated. " - - Combo $Enable_Scaling_06, "\tScale to Target Resolution:", &No_Yes_List, - Help "Selecting this feature will make the graphics driver to enable Scaling feature by taking the Horizontal and Vertical resolution\r\n" - "from Target X-Res and Target Y-Res fields.\r\n" - - EditNum $Panel_Width_06, "\tTarget X-Res:", DEC, - Help "This value specifies the Target X-Resolution for this panel." - - EditNum $Panel_Height_06, "\tTarget Y-Res:", DEC, - Help "This value specifies the Target Y-Resolutoin for this panel." - - - - - Combo $DPS_Panel_Type_06, " \tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n " - "Intel SDRRS Technology is a feature of the Intel graphics driver\r\n" - "which reduces display power\r\n" - "SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n" - "rate will not adversely impact the user experience\r\n" - "Seamless:- Allows power savings when on battery mode and when a lower refresh\r\n" - "rate will not adversely impact the user experience.Implements seamless refresh\r\n" - "rate switching, which eliminates the screen blink that occurred\r\n" - "during the refresh rate transitions\r\n" - - EditNum $Seamless_DRRS_Min_RR_06, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, - Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n\n" - "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" - - Combo $Blt_Control_06, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology.\r\n " - - Title " " - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "DTD Timings Table" , "DTD Timings" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - - - #if ($Int_LFP1_Type == 0x1806) - TitleB "Integrated eDP Features" - - Combo $Enable_SSC06, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " - - - Combo $eDP_Panel_Color_Depth_06, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used. " - - Combo $eDP_VSwingPreEmph_6, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For CherryTrail, based on the selection respective table will be used.\r\n" - "Tables for CherryTrail:-\r\n" - "------------------------------------------------------------------------------------------------------\n" - "|Low Power VSwing Pre-Emphasis Setting Table |\n" - "-----------------------------------------------------------------------------------------------------|\n" - "| | Pre-Emphasis (db) |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" - "| Voltage |------------------------------------------------------------------------- ---------------|\n" - "| Swing | Level 0/200 | 200mV,0db | 200mV,3.5db | 200mV,6db | 200mV,9db |\n" - "| (mV) |------------------------------------------------------------------------------------------|\n" - "| | Level 1/250 | 250mV,0db | 250mV,3.5db | 250mV,6db | NA |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | Level 2/300 | 300mV,0db | 300mV,3.5d | NA | NA |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | Level 3/350 | 350 mv, 0db | NA | NA | NA |\n" - "-----------------------------------------------------------------------------------------------------\n\n" - - "-----------------------------------------------------------------------------------------------------\n" - "|Default VSwing Pre-Emphasis Setting Table |\n" - "---------------------------------------------------------------------------------------------------|\n" - "| | Pre-Emphasis (db) |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" - "| Voltage |----------------------------------------------------------------------------------------|\n" - "| Swing | Level 0/400 | 400mV,0db | 400mV,3.5db | 400mV,6db | 400mV,9db |\n" - "| (mV) |----------------------------------------------------------------------------------------|\n" - "| | Level 1/600 | 600mV,0db | 600mV,3.5db | 600mV,6db | NA |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | Level 2/800 | 800mV,0db | 800mV,3.5db | NA | NA |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | Level 3/1200| 1200mV, 0db | NA | NA | NA |\n" - "-----------------------------------------------------------------------------------------------------\n\n" - - - Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Power Sequencing" - Link "eDP Fast Link Training Configuration" , "eDP Fast Link Training Configuration" - - Page "eDP Panel Power Sequencing" - Link "Close Table", ".." - - Combo $eDP_T3_Optimization_06, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/Graphics driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_06, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_06, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_06, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_06, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_06, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_06, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_06, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - - EndPage - - Page "eDP Fast Link Training Configuration" - - Link "Close Table" , ".." - Combo $Fast_Link_Training_Supported_06, " Is FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature if set to Yes will enable " - "Fast Link Training for eDp, if Panel also supports it." - - Combo $eDP_Link_DataRate_06, " Data Rate:", &eDP_Link_DataRate_List, - Help "This feature allows for the selection of the " - "Data Rate for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_06, " Lane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the " - "Lane Count (Port Width) for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_06, " Pre-Emphasis:", &eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the " - "Pre-emphasis value for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - - "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - "Column - Non-Transition VDiff \r\n" - "Row - Transition VDiff \r\n" - - Combo $eDP_Link_Vswing_06, " Voltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the " - "Voltage Swing value for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - - "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - "Column - Non-Transition VDiff \r\n" - "Row - Transition VDiff \r\n" - EndPage - #endif - - Page "DTD Timings" - - Link "Close Table" , ".." - - Table $DVO_Tbl_06 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD " - "timings parameters related to the LFP. The " - "table is the 18-byte DTD structure defined in the " - "VESA EDID version 1.x.\r\n" - "\r\n" - "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" - "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tDB ?\t; Vertical Active in lines, LSB\r\n" - "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Horizontal Image Size, LSB\r\n" - "\tDB ?\t; Vertical Image Size, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tDB 0\t; Horizontal Border in pixels\r\n" - "\tDB 0\t; Vertical Border in lines\r\n" - "\tDB ?\t; Flags:\r\n" - "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t; Bit 6-5: 00 = Reserved\r\n" - "\t \t; Bit 4-3: 11 = Digital Separate\r\n" - "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 0: 0 = Reserved" - - EndPage - - Page "LFP PnP ID" - - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_06 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor / " - "Product ID starting at offset 08h to be used as a " - "PnP ID.\r\n" - "\r\n" - " Table Definition:\r\n" - " Word: ID Manufacturer Name\r\n" - " Word: ID Product Code\r\n" - " DWord: ID Serial Number\r\n" - " Byte: Week of Manufacture\r\n" - " Byte: Year of Manufacture" - - EndPage - - Page "Backlight Control Parameters" - - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_6, " Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the " - "Backlight Inverter type that is to be used to " - "control the backlight brightness of the LFP. When " - "PWM is selected, the driver and VBIOS will control " - "the backlight brightness via the integrated PWM " - "solution for the applicable chipsets. When I2C is " - "selected, the driver and VBIOS will control the " - "backlight brightness via the I2C solution for the " - "applicable chipsets. When None/External is " - "selected, the system BIOS will control the backlight " - "brightness via the external solution." - - Combo $Lfp_Pwm_Source_Selection_06, " Pwm Source Selection:", &Edp_Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - "\r\n" - - Combo $BLC_Inv_Polarity_6, " Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity " - "to be specified.\r\n" - "\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_6, " Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum " - "backlight brightness setting. The graphics driver " - "will never decrease the backlight less than this " - "value. The value must be specified using normal " - "polarity semantics." - -EditNum $POST_BL_Brightness_06, " POST Backlight Intensity:", DEC, - Help "This feature is used to set default brightness value at POST." - "This is configurable field of 0-255. Value of 0 indicates 0 brightness, 255 indicates maximum brightness. " - - EditNum $PWM_Frequency_6, " PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the " - "frequency needed for PWM Inverter.\r\n" - "\r\n" - "Note: The frequency range, entered as a decimal " - "number, for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_6, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - Combo $Override_EDID_Data_6, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - EditNum $Red_Green_6, " Red_Green_bits (Bits 1&0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - EditNum $Blue_White_6, " Blue_White_bits (Bits 1&0 at 20h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - EditNum $Red_x_6, " Red_x (Bits 9->2 at 1Bh)" , EHEX, - Help " Bits 9->2 of red color x coordinate" - EditNum $Red_y_6, " Red_y (Bits 9->2 at 1Ch)" , EHEX, - Help " Bits 9->2 of red color y coordinate" - EditNum $Green_x_6, " Green_x (Bits 9->2 at 1Dh)" , EHEX, - Help " Bits 9->2 of Green color x coordinate" - EditNum $Green_y_6, " Green_y (Bits 9->2 at 1Eh)" , EHEX, - Help " Bits 9->2 of Green color y coordinate" - EditNum $Blue_x_6, " Blue_x (Bits 9->2 at 1Fh)" , EHEX, - Help " Bits 9->2 of Blue color x coordinate" - EditNum $Blue_y_6, " Blue_y (Bits 9->2 at 20h)" , EHEX, - Help " Bits 9->2 of Blue color y coordinate" - EditNum $White_x_6, " White_x (Bits 9->2 at 21h)" , EHEX, - Help " Bits 9->2 of White color x coordinate" - EditNum $White_y_6, " White_y (Bits 9->2 at 22h)" , EHEX, - Help " Bits 9->2 of White color y coordinate" - - EndPage ; Chromaticity Control - - - - -EndPage - -; -; Panel#7 to Panel#16 are not shown in BMP UI for MIPI panels -; -#if ($Int_LFP1_Type != 0x1400) -;============================================================================== -; Page - Panel #7 (1600x1200) Flat Panel parameters -;------------------------------------------------------------------------------ - -Page "Panel #7 " - - TitleB "Common LFP Features" - - EditText $Panel_Name_07, "\tLFP Panel Name:", - Help "This feature defines the LVDS panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated. " - - Combo $Enable_Scaling_07, "\tScale to Target Resolution:", &No_Yes_List, - Help "Selecting this feature will make the graphics driver to enable Scaling feature by taking the Horizontal and Vertical resolution\r\n" - "from Target X-Res and Target Y-Res fields.\r\n" - - EditNum $Panel_Width_07, "\tTarget X-Res:", DEC, - Help "This value specifies the Target X-Resolution for this panel." - - EditNum $Panel_Height_07, "\tTarget Y-Res:", DEC, - Help "This value specifies the Target Y-Resolutoin for this panel." - - - - - Combo $DPS_Panel_Type_07, " \tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n " - "Intel SDRRS Technology is a feature of the Intel graphics driver\r\n" - "which reduces display power\r\n" - "SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n" - "rate will not adversely impact the user experience\r\n" - "Seamless:- Allows power savings when on battery mode and when a lower refresh\r\n" - "rate will not adversely impact the user experience.Implements seamless refresh\r\n" - "rate switching, which eliminates the screen blink that occurred\r\n" - "during the refresh rate transitions\r\n" - - EditNum $Seamless_DRRS_Min_RR_07, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, - Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n\n" - "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" - - Combo $Blt_Control_07, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology.\r\n " - - Title " " - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "DTD Timings Table" , "DTD Timings" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - - #if ($Int_LFP1_Type == 0x1806) - TitleB "Integrated eDP Features" - - - Combo $Enable_SSC07, " \teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " - - Combo $eDP_Panel_Color_Depth_07, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used. " - - Combo $eDP_VSwingPreEmph_7, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For CherryTrail, based on the selection respective table will be used.\r\n" - "Tables for CherryTrail:-\r\n" - "------------------------------------------------------------------------------------------------------\n" - "|Low Power VSwing Pre-Emphasis Setting Table |\n" - "-----------------------------------------------------------------------------------------------------|\n" - "| | Pre-Emphasis (db) |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" - "| Voltage |------------------------------------------------------------------------- ---------------|\n" - "| Swing | Level 0/200 | 200mV,0db | 200mV,3.5db | 200mV,6db | 200mV,9db |\n" - "| (mV) |------------------------------------------------------------------------------------------|\n" - "| | Level 1/250 | 250mV,0db | 250mV,3.5db | 250mV,6db | NA |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | Level 2/300 | 300mV,0db | 300mV,3.5d | NA | NA |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | Level 3/350 | 350 mv, 0db | NA | NA | NA |\n" - "-----------------------------------------------------------------------------------------------------\n\n" - - "-----------------------------------------------------------------------------------------------------\n" - "|Default VSwing Pre-Emphasis Setting Table |\n" - "---------------------------------------------------------------------------------------------------|\n" - "| | Pre-Emphasis (db) |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" - "| Voltage |----------------------------------------------------------------------------------------|\n" - "| Swing | Level 0/400 | 400mV,0db | 400mV,3.5db | 400mV,6db | 400mV,9db |\n" - "| (mV) |----------------------------------------------------------------------------------------|\n" - "| | Level 1/600 | 600mV,0db | 600mV,3.5db | 600mV,6db | NA |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | Level 2/800 | 800mV,0db | 800mV,3.5db | NA | NA |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | Level 3/1200| 1200mV, 0db | NA | NA | NA |\n" - "-----------------------------------------------------------------------------------------------------\n\n" - - - Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Power Sequencing" - Link "eDP Fast Link Training Configuration" , "eDP Fast Link Training Configuration" - - Page "eDP Panel Power Sequencing" - Link "Close Table", ".." - - Combo $eDP_T3_Optimization_07, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/Graphics driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_07, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_07, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_07, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_07, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_07, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_07, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_07, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - - EndPage - - Page "eDP Fast Link Training Configuration" - - Link "Close Table" , ".." - Combo $Fast_Link_Training_Supported_07, " Is FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature if set to Yes will enable " - "Fast Link Training for eDp, if Panel also supports it." - - Combo $eDP_Link_DataRate_07, " Data Rate:", &eDP_Link_DataRate_List, - Help "This feature allows for the selection of the " - "Data Rate for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_07, " Lane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the " - "Lane Count (Port Width) for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_07, " Pre-Emphasis:", &eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the " - "Pre-emphasis value for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - - "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - "Column - Non-Transition VDiff \r\n" - "Row - Transition VDiff \r\n" - - Combo $eDP_Link_Vswing_07, " Voltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the " - "Voltage Swing value for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - - "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - "Column - Non-Transition VDiff \r\n" - "Row - Transition VDiff \r\n" - EndPage - #endif - - Page "DTD Timings" - - Link "Close Table" , ".." - - Table $DVO_Tbl_07 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD " - "timings parameters related to the LFP. The " - "table is the 18-byte DTD structure defined in the " - "VESA EDID version 1.x.\r\n" - "\r\n" - "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" - "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tDB ?\t; Vertical Active in lines, LSB\r\n" - "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Horizontal Image Size, LSB\r\n" - "\tDB ?\t; Vertical Image Size, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tDB 0\t; Horizontal Border in pixels\r\n" - "\tDB 0\t; Vertical Border in lines\r\n" - "\tDB ?\t; Flags:\r\n" - "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t; Bit 6-5: 00 = Reserved\r\n" - "\t \t; Bit 4-3: 11 = Digital Separate\r\n" - "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 0: 0 = Reserved" - - EndPage - - Page "LFP PnP ID" - - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_07 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor / " - "Product ID starting at offset 08h to be used as a " - "PnP ID.\r\n" - "\r\n" - " Table Definition:\r\n" - " Word: ID Manufacturer Name\r\n" - " Word: ID Product Code\r\n" - " DWord: ID Serial Number\r\n" - " Byte: Week of Manufacture\r\n" - " Byte: Year of Manufacture" - - EndPage - - Page "Backlight Control Parameters" - - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_7, " Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the " - "Backlight Inverter type that is to be used to " - "control the backlight brightness of the LFP. When " - "PWM is selected, the driver and VBIOS will control " - "the backlight brightness via the integrated PWM " - "solution for the applicable chipsets. When I2C is " - "selected, the driver and VBIOS will control the " - "backlight brightness via the I2C solution for the " - "applicable chipsets. When None/External is " - "selected, the system BIOS will control the backlight " - "brightness via the external solution." - - Combo $Lfp_Pwm_Source_Selection_07, " Pwm Source Selection:", &Edp_Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - "\r\n" - - Combo $BLC_Inv_Polarity_7, " Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity " - "to be specified.\r\n" - "\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_7, " Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum " - "backlight brightness setting. The graphics driver " - "will never decrease the backlight less than this " - "value. The value must be specified using normal " - "polarity semantics." - -EditNum $POST_BL_Brightness_07, " POST Backlight Intensity:", DEC, - Help "This feature is used to set default brightness value at POST." - "This is configurable field of 0-255. Value of 0 indicates 0 brightness, 255 indicates maximum brightness. " - - EditNum $PWM_Frequency_7, " PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the " - "frequency needed for PWM Inverter.\r\n" - "\r\n" - "Note: The frequency range, entered as a decimal " - "number, for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_7, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - Combo $Override_EDID_Data_7, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - EditNum $Red_Green_7, " Red_Green_bits (Bits 1&0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - EditNum $Blue_White_7, " Blue_White_bits (Bits 1&0 at 20h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - EditNum $Red_x_7, " Red_x (Bits 9->2 at 1Bh)" , EHEX, - Help " Bits 9->2 of red color x coordinate" - EditNum $Red_y_7, " Red_y (Bits 9->2 at 1Ch)" , EHEX, - Help " Bits 9->2 of red color y coordinate" - EditNum $Green_x_7, " Green_x (Bits 9->2 at 1Dh)" , EHEX, - Help " Bits 9->2 of Green color x coordinate" - EditNum $Green_y_7, " Green_y (Bits 9->2 at 1Eh)" , EHEX, - Help " Bits 9->2 of Green color y coordinate" - EditNum $Blue_x_7, " Blue_x (Bits 9->2 at 1Fh)" , EHEX, - Help " Bits 9->2 of Blue color x coordinate" - EditNum $Blue_y_7, " Blue_y (Bits 9->2 at 20h)" , EHEX, - Help " Bits 9->2 of Blue color y coordinate" - EditNum $White_x_7, " White_x (Bits 9->2 at 21h)" , EHEX, - Help " Bits 9->2 of White color x coordinate" - EditNum $White_y_7, " White_y (Bits 9->2 at 22h)" , EHEX, - Help " Bits 9->2 of White color y coordinate" - - EndPage ; Chromaticity Control -EndPage - - - -;============================================================================== -; Page - Panel #8 (1280x768) Flat Panel parameters -;------------------------------------------------------------------------------ - -Page "Panel #8 " - - TitleB "Common LFP Features" - - EditText $Panel_Name_08, "\tLFP Panel Name:", - Help "This feature defines the LVDS panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated. " - - Combo $Enable_Scaling_08, "\tScale to Target Resolution:", &No_Yes_List, - Help "Selecting this feature will make the graphics driver to enable Scaling feature by taking the Horizontal and Vertical resolution\r\n" - "from Target X-Res and Target Y-Res fields.\r\n" - - EditNum $Panel_Width_08, "\tTarget X-Res:", DEC, - Help "This value specifies the Target X-Resolution for this panel." - - EditNum $Panel_Height_08, "\tTarget Y-Res:", DEC, - Help "This value specifies the Target Y-Resolutoin for this panel." - - - - - Combo $DPS_Panel_Type_08, " \tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n " - "Intel SDRRS Technology is a feature of the Intel graphics driver\r\n" - "which reduces display power\r\n" - "SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n" - "rate will not adversely impact the user experience\r\n" - "Seamless:- Allows power savings when on battery mode and when a lower refresh\r\n" - "rate will not adversely impact the user experience.Implements seamless refresh\r\n" - "rate switching, which eliminates the screen blink that occurred\r\n" - "during the refresh rate transitions\r\n" - - EditNum $Seamless_DRRS_Min_RR_08, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, - Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n\n" - "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" - - Combo $Blt_Control_08, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology.\r\n " - - Title " " - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "DTD Timings Table" , "DTD Timings" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - - #if ($Int_LFP1_Type == 0x1806) - TitleB "Integrated eDP Features" - - Combo $Enable_SSC08, " \teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " - - - Combo $eDP_Panel_Color_Depth_08, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used. " - - Combo $eDP_VSwingPreEmph_8, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For CherryTrail, based on the selection respective table will be used.\r\n" - "Tables for CherryTrail:-\r\n" - "------------------------------------------------------------------------------------------------------\n" - "|Low Power VSwing Pre-Emphasis Setting Table |\n" - "-----------------------------------------------------------------------------------------------------|\n" - "| | Pre-Emphasis (db) |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" - "| Voltage |------------------------------------------------------------------------- ---------------|\n" - "| Swing | Level 0/200 | 200mV,0db | 200mV,3.5db | 200mV,6db | 200mV,9db |\n" - "| (mV) |------------------------------------------------------------------------------------------|\n" - "| | Level 1/250 | 250mV,0db | 250mV,3.5db | 250mV,6db | NA |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | Level 2/300 | 300mV,0db | 300mV,3.5d | NA | NA |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | Level 3/350 | 350 mv, 0db | NA | NA | NA |\n" - "-----------------------------------------------------------------------------------------------------\n\n" - - "-----------------------------------------------------------------------------------------------------\n" - "|Default VSwing Pre-Emphasis Setting Table |\n" - "---------------------------------------------------------------------------------------------------|\n" - "| | Pre-Emphasis (db) |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" - "| Voltage |----------------------------------------------------------------------------------------|\n" - "| Swing | Level 0/400 | 400mV,0db | 400mV,3.5db | 400mV,6db | 400mV,9db |\n" - "| (mV) |----------------------------------------------------------------------------------------|\n" - "| | Level 1/600 | 600mV,0db | 600mV,3.5db | 600mV,6db | NA |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | Level 2/800 | 800mV,0db | 800mV,3.5db | NA | NA |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | Level 3/1200| 1200mV, 0db | NA | NA | NA |\n" - "-----------------------------------------------------------------------------------------------------\n\n" - - - Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Power Sequencing" - Link "eDP Fast Link Training Configuration" , "eDP Fast Link Training Configuration" - - Page "eDP Panel Power Sequencing" - Link "Close Table", ".." - - Combo $eDP_T3_Optimization_08, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/Graphics driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_08, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_08, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_08, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_08, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_08, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_08, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_08, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - - EndPage - - Page "eDP Fast Link Training Configuration" - - Link "Close Table" , ".." - Combo $Fast_Link_Training_Supported_08, " Is FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature if set to Yes will enable " - "Fast Link Training for eDp, if Panel also supports it." - - Combo $eDP_Link_DataRate_08, " Data Rate:", &eDP_Link_DataRate_List, - Help "This feature allows for the selection of the " - "Data Rate for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_08, " Lane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the " - "Lane Count (Port Width) for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_08, " Pre-Emphasis:", &eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the " - "Pre-emphasis value for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - - "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - "Column - Non-Transition VDiff \r\n" - "Row - Transition VDiff \r\n" - - Combo $eDP_Link_Vswing_08, " Voltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the " - "Voltage Swing value for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - - "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - "Column - Non-Transition VDiff \r\n" - "Row - Transition VDiff \r\n" - EndPage - #endif - - Page "DTD Timings" - - Link "Close Table" , ".." - - Table $DVO_Tbl_08 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD " - "timings parameters related to the LFP. The " - "table is the 18-byte DTD structure defined in the " - "VESA EDID version 1.x.\r\n" - "\r\n" - "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" - "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tDB ?\t; Vertical Active in lines, LSB\r\n" - "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Horizontal Image Size, LSB\r\n" - "\tDB ?\t; Vertical Image Size, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tDB 0\t; Horizontal Border in pixels\r\n" - "\tDB 0\t; Vertical Border in lines\r\n" - "\tDB ?\t; Flags:\r\n" - "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t; Bit 6-5: 00 = Reserved\r\n" - "\t \t; Bit 4-3: 11 = Digital Separate\r\n" - "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 0: 0 = Reserved" - - EndPage - - Page "LFP PnP ID" - - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_08 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor / " - "Product ID starting at offset 08h to be used as a " - "PnP ID.\r\n" - "\r\n" - " Table Definition:\r\n" - " Word: ID Manufacturer Name\r\n" - " Word: ID Product Code\r\n" - " DWord: ID Serial Number\r\n" - " Byte: Week of Manufacture\r\n" - " Byte: Year of Manufacture" - - EndPage - - Page "Backlight Control Parameters" - - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_8, " Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the " - "Backlight Inverter type that is to be used to " - "control the backlight brightness of the LFP. When " - "PWM is selected, the driver and VBIOS will control " - "the backlight brightness via the integrated PWM " - "solution for the applicable chipsets. When I2C is " - "selected, the driver and VBIOS will control the " - "backlight brightness via the I2C solution for the " - "applicable chipsets. When None/External is " - "selected, the system BIOS will control the backlight " - "brightness via the external solution." - - Combo $Lfp_Pwm_Source_Selection_08, " Pwm Source Selection:", &Edp_Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - "\r\n" - - Combo $BLC_Inv_Polarity_8, " Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity " - "to be specified.\r\n" - "\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_8, " Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum " - "backlight brightness setting. The graphics driver " - "will never decrease the backlight less than this " - "value. The value must be specified using normal " - "polarity semantics." - - EditNum $POST_BL_Brightness_08, " POST Backlight Intensity:", DEC, - Help "This feature is used to set default brightness value at POST." - "This is configurable field of 0-255. Value of 0 indicates 0 brightness, 255 indicates maximum brightness. " - - EditNum $PWM_Frequency_8, " PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the " - "frequency needed for PWM Inverter.\r\n" - "\r\n" - "Note: The frequency range, entered as a decimal " - "number, for the integrated PWM is 200Hz - 40KHz." - EndPage - - - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_8, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - Combo $Override_EDID_Data_8, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - EditNum $Red_Green_8, " Red_Green_bits (Bits 1&0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - EditNum $Blue_White_8, " Blue_White_bits (Bits 1&0 at 20h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - EditNum $Red_x_8, " Red_x (Bits 9->2 at 1Bh)" , EHEX, - Help " Bits 9->2 of red color x coordinate" - EditNum $Red_y_8, " Red_y (Bits 9->2 at 1Ch)" , EHEX, - Help " Bits 9->2 of red color y coordinate" - EditNum $Green_x_8, " Green_x (Bits 9->2 at 1Dh)" , EHEX, - Help " Bits 9->2 of Green color x coordinate" - EditNum $Green_y_8, " Green_y (Bits 9->2 at 1Eh)" , EHEX, - Help " Bits 9->2 of Green color y coordinate" - EditNum $Blue_x_8, " Blue_x (Bits 9->2 at 1Fh)" , EHEX, - Help " Bits 9->2 of Blue color x coordinate" - EditNum $Blue_y_8, " Blue_y (Bits 9->2 at 20h)" , EHEX, - Help " Bits 9->2 of Blue color y coordinate" - EditNum $White_x_8, " White_x (Bits 9->2 at 21h)" , EHEX, - Help " Bits 9->2 of White color x coordinate" - EditNum $White_y_8, " White_y (Bits 9->2 at 22h)" , EHEX, - Help " Bits 9->2 of White color y coordinate" - - EndPage ; Chromaticity Control -EndPage - -;============================================================================== -; Page - Panel #9 (1680x1050) Flat Panel parameters -;------------------------------------------------------------------------------ - -Page "Panel #9 " - - TitleB "Common LFP Features" - - EditText $Panel_Name_09, "\tLFP Panel Name:", - Help "This feature defines the LVDS panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated. " - - Combo $Enable_Scaling_09, "\tScale to Target Resolution:", &No_Yes_List, - Help "Selecting this feature will make the graphics driver to enable Scaling feature by taking the Horizontal and Vertical resolution\r\n" - "from Target X-Res and Target Y-Res fields.\r\n" - - EditNum $Panel_Width_09, "\tTarget X-Res:", DEC, - Help "This value specifies the Target X-Resolution for this panel." - - EditNum $Panel_Height_09, "\tTarget Y-Res:", DEC, - Help "This value specifies the Target Y-Resolutoin for this panel." - - - - - Combo $DPS_Panel_Type_09, " \tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n " - "Intel SDRRS Technology is a feature of the Intel graphics driver\r\n" - "which reduces display power\r\n" - "SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n" - "rate will not adversely impact the user experience\r\n" - "Seamless:- Allows power savings when on battery mode and when a lower refresh\r\n" - "rate will not adversely impact the user experience.Implements seamless refresh\r\n" - "rate switching, which eliminates the screen blink that occurred\r\n" - "during the refresh rate transitions\r\n" - - EditNum $Seamless_DRRS_Min_RR_09, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, - Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n\n" - "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" - - Combo $Blt_Control_09, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology.\r\n " - - Title " " - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "DTD Timings Table" , "DTD Timings" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - - #if ($Int_LFP1_Type == 0x1806) - TitleB "Integrated eDP Features" - - Combo $Enable_SSC09, " \teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " - - Combo $eDP_Panel_Color_Depth_09, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used. " - - Combo $eDP_VSwingPreEmph_9, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For CherryTrail, based on the selection respective table will be used.\r\n" - "Tables for CherryTrail:-\r\n" - "------------------------------------------------------------------------------------------------------\n" - "|Low Power VSwing Pre-Emphasis Setting Table |\n" - "-----------------------------------------------------------------------------------------------------|\n" - "| | Pre-Emphasis (db) |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" - "| Voltage |------------------------------------------------------------------------- ---------------|\n" - "| Swing | Level 0/200 | 200mV,0db | 200mV,3.5db | 200mV,6db | 200mV,9db |\n" - "| (mV) |------------------------------------------------------------------------------------------|\n" - "| | Level 1/250 | 250mV,0db | 250mV,3.5db | 250mV,6db | NA |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | Level 2/300 | 300mV,0db | 300mV,3.5d | NA | NA |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | Level 3/350 | 350 mv, 0db | NA | NA | NA |\n" - "-----------------------------------------------------------------------------------------------------\n\n" - - "-----------------------------------------------------------------------------------------------------\n" - "|Default VSwing Pre-Emphasis Setting Table |\n" - "---------------------------------------------------------------------------------------------------|\n" - "| | Pre-Emphasis (db) |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" - "| Voltage |----------------------------------------------------------------------------------------|\n" - "| Swing | Level 0/400 | 400mV,0db | 400mV,3.5db | 400mV,6db | 400mV,9db |\n" - "| (mV) |----------------------------------------------------------------------------------------|\n" - "| | Level 1/600 | 600mV,0db | 600mV,3.5db | 600mV,6db | NA |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | Level 2/800 | 800mV,0db | 800mV,3.5db | NA | NA |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | Level 3/1200| 1200mV, 0db | NA | NA | NA |\n" - "-----------------------------------------------------------------------------------------------------\n\n" - - - Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Power Sequencing" - Link "eDP Fast Link Training Configuration" , "eDP Fast Link Training Configuration" - - Page "eDP Panel Power Sequencing" - Link "Close Table", ".." - - Combo $eDP_T3_Optimization_09, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/Graphics driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_09, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_09, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_09, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_09, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_09, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_09, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_09, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - - EndPage - - Page "eDP Fast Link Training Configuration" - - Link "Close Table" , ".." - Combo $Fast_Link_Training_Supported_09, " Is FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature if set to Yes will enable " - "Fast Link Training for eDp, if Panel also supports it." - - Combo $eDP_Link_DataRate_09, " Data Rate:", &eDP_Link_DataRate_List, - Help "This feature allows for the selection of the " - "Data Rate for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_09, " Lane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the " - "Lane Count (Port Width) for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_09, " Pre-Emphasis:", &eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the " - "Pre-emphasis value for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(400mV) | Supported | Supported | Supported | Support | \r\n" - "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - - "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - "Column - Non-Transition VDiff \r\n" - "Row - Transition VDiff \r\n" - - Combo $eDP_Link_Vswing_09, " Voltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the " - "Voltage Swing value for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - - "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - "Column - Non-Transition VDiff \r\n" - "Row - Transition VDiff \r\n" - EndPage - #endif - - Page "DTD Timings" - - Link "Close Table" , ".." - - Table $DVO_Tbl_09 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD " - "timings parameters related to the LFP. The " - "table is the 18-byte DTD structure defined in the " - "VESA EDID version 1.x.\r\n" - "\r\n" - "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" - "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tDB ?\t; Vertical Active in lines, LSB\r\n" - "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Horizontal Image Size, LSB\r\n" - "\tDB ?\t; Vertical Image Size, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tDB 0\t; Horizontal Border in pixels\r\n" - "\tDB 0\t; Vertical Border in lines\r\n" - "\tDB ?\t; Flags:\r\n" - "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t; Bit 6-5: 00 = Reserved\r\n" - "\t \t; Bit 4-3: 11 = Digital Separate\r\n" - "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 0: 0 = Reserved" - - EndPage - - Page "LFP PnP ID" - - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_09 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor / " - "Product ID starting at offset 08h to be used as a " - "PnP ID.\r\n" - "\r\n" - " Table Definition:\r\n" - " Word: ID Manufacturer Name\r\n" - " Word: ID Product Code\r\n" - " DWord: ID Serial Number\r\n" - " Byte: Week of Manufacture\r\n" - " Byte: Year of Manufacture" - - EndPage - - Page "Backlight Control Parameters" - - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_9, " Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the " - "Backlight Inverter type that is to be used to " - "control the backlight brightness of the LFP. When " - "PWM is selected, the driver and VBIOS will control " - "the backlight brightness via the integrated PWM " - "solution for the applicable chipsets. When I2C is " - "selected, the driver and VBIOS will control the " - "backlight brightness via the I2C solution for the " - "applicable chipsets. When None/External is " - "selected, the system BIOS will control the backlight " - "brightness via the external solution." - - Combo $Lfp_Pwm_Source_Selection_09, " Pwm Source Selection:", &Edp_Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - "\r\n" - - Combo $BLC_Inv_Polarity_9, " Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity " - "to be specified.\r\n" - "\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_9, " Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum " - "backlight brightness setting. The graphics driver " - "will never decrease the backlight less than this " - "value. The value must be specified using normal " - "polarity semantics." - -EditNum $POST_BL_Brightness_09, " POST Backlight Intensity:", DEC, - Help "This feature is used to set default brightness value at POST." - "This is configurable field of 0-255. Value of 0 indicates 0 brightness, 255 indicates maximum brightness. " - - EditNum $PWM_Frequency_9, " PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the " - "frequency needed for PWM Inverter.\r\n" - "\r\n" - "Note: The frequency range, entered as a decimal " - "number, for the integrated PWM is 200Hz - 40KHz." - EndPage - - - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_9, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - Combo $Override_EDID_Data_9, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - EditNum $Red_Green_9, " Red_Green_bits (Bits 1&0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - EditNum $Blue_White_9, " Blue_White_bits (Bits 1&0 at 20h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - EditNum $Red_x_9, " Red_x (Bits 9->2 at 1Bh)" , EHEX, - Help " Bits 9->2 of red color x coordinate" - EditNum $Red_y_9, " Red_y (Bits 9->2 at 1Ch)" , EHEX, - Help " Bits 9->2 of red color y coordinate" - EditNum $Green_x_9, " Green_x (Bits 9->2 at 1Dh)" , EHEX, - Help " Bits 9->2 of Green color x coordinate" - EditNum $Green_y_9, " Green_y (Bits 9->2 at 1Eh)" , EHEX, - Help " Bits 9->2 of Green color y coordinate" - EditNum $Blue_x_9, " Blue_x (Bits 9->2 at 1Fh)" , EHEX, - Help " Bits 9->2 of Blue color x coordinate" - EditNum $Blue_y_9, " Blue_y (Bits 9->2 at 20h)" , EHEX, - Help " Bits 9->2 of Blue color y coordinate" - EditNum $White_x_9, " White_x (Bits 9->2 at 21h)" , EHEX, - Help " Bits 9->2 of White color x coordinate" - EditNum $White_y_9, " White_y (Bits 9->2 at 22h)" , EHEX, - Help " Bits 9->2 of White color y coordinate" - - EndPage ; Chromaticity Control - -EndPage -;============================================================================== -; Page - Panel #10 (1920x1200) Flat Panel parameters -;------------------------------------------------------------------------------ - -Page "Panel #10 " - - TitleB "Common LFP Features" - - EditText $Panel_Name_10, "\tLFP Panel Name:", - Help "This feature defines the LVDS panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated. " - - Combo $Enable_Scaling_10, "\tScale to Target Resolution:", &No_Yes_List, - Help "Selecting this feature will make the graphics driver to enable Scaling feature by taking the Horizontal and Vertical resolution\r\n" - "from Target X-Res and Target Y-Res fields.\r\n" - - EditNum $Panel_Width_10, "\tTarget X-Res:", DEC, - Help "This value specifies the Target X-Resolution for this panel." - - EditNum $Panel_Height_10, "\tTarget Y-Res:", DEC, - Help "This value specifies the Target Y-Resolutoin for this panel." - - - - - Combo $DPS_Panel_Type_10, " \tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n " - "Intel SDRRS Technology is a feature of the Intel graphics driver\r\n" - "which reduces display power\r\n" - "SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n" - "rate will not adversely impact the user experience\r\n" - "Seamless:- Allows power savings when on battery mode and when a lower refresh\r\n" - "rate will not adversely impact the user experience.Implements seamless refresh\r\n" - "rate switching, which eliminates the screen blink that occurred\r\n" - "during the refresh rate transitions\r\n" - - EditNum $Seamless_DRRS_Min_RR_10, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, - Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n\n" - "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" - - Combo $Blt_Control_10, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology.\r\n " - - Title " " - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "DTD Timings Table" , "DTD Timings" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - - #if ($Int_LFP1_Type == 0x1806) - TitleB "Integrated eDP Features" - - - Combo $Enable_SSC10, " \teDP Spread Spectrum Clock:", &Disabled_Enabled_List, - Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " - Combo $eDP_Panel_Color_Depth_10, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used. " - - Combo $eDP_VSwingPreEmph_10, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For CherryTrail, based on the selection respective table will be used.\r\n" - "Tables for CherryTrail:-\r\n" - "------------------------------------------------------------------------------------------------------\n" - "|Low Power VSwing Pre-Emphasis Setting Table |\n" - "-----------------------------------------------------------------------------------------------------|\n" - "| | Pre-Emphasis (db) |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" - "| Voltage |------------------------------------------------------------------------- ---------------|\n" - "| Swing | Level 0/200 | 200mV,0db | 200mV,3.5db | 200mV,6db | 200mV,9db |\n" - "| (mV) |------------------------------------------------------------------------------------------|\n" - "| | Level 1/250 | 250mV,0db | 250mV,3.5db | 250mV,6db | NA |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | Level 2/300 | 300mV,0db | 300mV,3.5d | NA | NA |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | Level 3/350 | 350 mv, 0db | NA | NA | NA |\n" - "-----------------------------------------------------------------------------------------------------\n\n" - - "-----------------------------------------------------------------------------------------------------\n" - "|Default VSwing Pre-Emphasis Setting Table |\n" - "---------------------------------------------------------------------------------------------------|\n" - "| | Pre-Emphasis (db) |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" - "| Voltage |----------------------------------------------------------------------------------------|\n" - "| Swing | Level 0/400 | 400mV,0db | 400mV,3.5db | 400mV,6db | 400mV,9db |\n" - "| (mV) |----------------------------------------------------------------------------------------|\n" - "| | Level 1/600 | 600mV,0db | 600mV,3.5db | 600mV,6db | NA |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | Level 2/800 | 800mV,0db | 800mV,3.5db | NA | NA |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | Level 3/1200| 1200mV, 0db | NA | NA | NA |\n" - "-----------------------------------------------------------------------------------------------------\n\n" - - - Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Power Sequencing" - Link "eDP Fast Link Training Configuration" , "eDP Fast Link Training Configuration" - - Page "eDP Panel Power Sequencing" - Link "Close Table", ".." - Combo $eDP_T3_Optimization_10, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/Graphics driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_10, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_10, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_10, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_10, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_10, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_10, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_10, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - - EndPage - - Page "eDP Fast Link Training Configuration" - - Link "Close Table" , ".." - Combo $Fast_Link_Training_Supported_10, " Is FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature if set to Yes will enable " - "Fast Link Training for eDp, if Panel also supports it." - - Combo $eDP_Link_DataRate_10, " Data Rate:", &eDP_Link_DataRate_List, - Help "This feature allows for the selection of the " - "Data Rate for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_10, " Lane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the " - "Lane Count (Port Width) for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_10, " Pre-Emphasis:", &eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the " - "Pre-emphasis value for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - - "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - "Column - Non-Transition VDiff \r\n" - "Row - Transition VDiff \r\n" - - Combo $eDP_Link_Vswing_10, " Voltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the " - "Voltage Swing value for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - - "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - "Column - Non-Transition VDiff \r\n" - "Row - Transition VDiff \r\n" - EndPage - #endif - - Page "DTD Timings" - - Link "Close Table" , ".." - - Table $DVO_Tbl_10 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD " - "timings parameters related to the LFP. The " - "table is the 18-byte DTD structure defined in the " - "VESA EDID version 1.x.\r\n" - "\r\n" - "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" - "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tDB ?\t; Vertical Active in lines, LSB\r\n" - "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Horizontal Image Size, LSB\r\n" - "\tDB ?\t; Vertical Image Size, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tDB 0\t; Horizontal Border in pixels\r\n" - "\tDB 0\t; Vertical Border in lines\r\n" - "\tDB ?\t; Flags:\r\n" - "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t; Bit 6-5: 00 = Reserved\r\n" - "\t \t; Bit 4-3: 11 = Digital Separate\r\n" - "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 0: 0 = Reserved" - - EndPage - - Page "LFP PnP ID" - - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_10 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor / " - "Product ID starting at offset 08h to be used as a " - "PnP ID.\r\n" - "\r\n" - " Table Definition:\r\n" - " Word: ID Manufacturer Name\r\n" - " Word: ID Product Code\r\n" - " DWord: ID Serial Number\r\n" - " Byte: Week of Manufacture\r\n" - " Byte: Year of Manufacture" - - EndPage - - Page "Backlight Control Parameters" - - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_10, " Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the " - "Backlight Inverter type that is to be used to " - "control the backlight brightness of the LFP. When " - "PWM is selected, the driver and VBIOS will control " - "the backlight brightness via the integrated PWM " - "solution for the applicable chipsets. When I2C is " - "selected, the driver and VBIOS will control the " - "backlight brightness via the I2C solution for the " - "applicable chipsets. When None/External is " - "selected, the system BIOS will control the backlight " - "brightness via the external solution." - - Combo $Lfp_Pwm_Source_Selection_10, " Pwm Source Selection:", &Edp_Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - "\r\n" - - Combo $BLC_Inv_Polarity_10, " Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity " - "to be specified.\r\n" - "\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_10, " Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum " - "backlight brightness setting. The graphics driver " - "will never decrease the backlight less than this " - "value. The value must be specified using normal " - "polarity semantics." - -EditNum $POST_BL_Brightness_10, " POST Backlight Intensity:", DEC, - Help "This feature is used to set default brightness value at POST." - "This is configurable field of 0-255. Value of 0 indicates 0 brightness, 255 indicates maximum brightness. " - - EditNum $PWM_Frequency_10, " PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the " - "frequency needed for PWM Inverter.\r\n" - "\r\n" - "Note: The frequency range, entered as a decimal " - "number, for the integrated PWM is 200Hz - 40KHz." - EndPage - - - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_10, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - Combo $Override_EDID_Data_10, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - EditNum $Red_Green_10, " Red_Green_bits (Bits 1&0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - EditNum $Blue_White_10, " Blue_White_bits (Bits 1&0 at 20h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - EditNum $Red_x_10, " Red_x (Bits 9->2 at 1Bh)" , EHEX, - Help " Bits 9->2 of red color x coordinate" - EditNum $Red_y_10, " Red_y (Bits 9->2 at 1Ch)" , EHEX, - Help " Bits 9->2 of red color y coordinate" - EditNum $Green_x_10, " Green_x (Bits 9->2 at 1Dh)" , EHEX, - Help " Bits 9->2 of Green color x coordinate" - EditNum $Green_y_10, " Green_y (Bits 9->2 at 1Eh)" , EHEX, - Help " Bits 9->2 of Green color y coordinate" - EditNum $Blue_x_10, " Blue_x (Bits 9->2 at 1Fh)" , EHEX, - Help " Bits 9->2 of Blue color x coordinate" - EditNum $Blue_y_10, " Blue_y (Bits 9->2 at 20h)" , EHEX, - Help " Bits 9->2 of Blue color y coordinate" - EditNum $White_x_10, " White_x (Bits 9->2 at 21h)" , EHEX, - Help " Bits 9->2 of White color x coordinate" - EditNum $White_y_10, " White_y (Bits 9->2 at 22h)" , EHEX, - Help " Bits 9->2 of White color y coordinate" - - EndPage ; Chromaticity Control - -EndPage -;============================================================================== -; Page - Panel #11 (Reserved) Flat Panel parameters -;------------------------------------------------------------------------------ - -Page "Panel #11 " - - TitleB "Common LFP Features" - - EditText $Panel_Name_11, "\tLFP Panel Name:", - Help "This feature defines the LVDS panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated. " - - Combo $Enable_Scaling_11, "\tScale to Target Resolution:", &No_Yes_List, - Help "Selecting this feature will make the graphics driver to enable Scaling feature by taking the Horizontal and Vertical resolution\r\n" - "from Target X-Res and Target Y-Res fields.\r\n" - - EditNum $Panel_Width_11, "\tTarget X-Res:", DEC, - Help "This value specifies the Target X-Resolution for this panel." - - EditNum $Panel_Height_11, "\tTarget Y-Res:", DEC, - Help "This value specifies the Target Y-Resolutoin for this panel." - - - - - Combo $DPS_Panel_Type_11, " \tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n " - "Intel SDRRS Technology is a feature of the Intel graphics driver\r\n" - "which reduces display power\r\n" - "SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n" - "rate will not adversely impact the user experience\r\n" - "Seamless:- Allows power savings when on battery mode and when a lower refresh\r\n" - "rate will not adversely impact the user experience.Implements seamless refresh\r\n" - "rate switching, which eliminates the screen blink that occurred\r\n" - "during the refresh rate transitions\r\n" - - EditNum $Seamless_DRRS_Min_RR_11, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, - Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n\n" - "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" - - Combo $Blt_Control_11, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology.\r\n " - - Title " " - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "DTD Timings Table" , "DTD Timings" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - - #if ($Int_LFP1_Type == 0x1806) - TitleB "Integrated eDP Features" - - -Combo $Enable_SSC11, " \teDP Spread Spectrum Clock:", &Disabled_Enabled_List, -Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " - Combo $eDP_Panel_Color_Depth_11, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used. " - - Combo $eDP_VSwingPreEmph_11, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For CherryTrail, based on the selection respective table will be used.\r\n" - "Tables for CherryTrail:-\r\n" - "------------------------------------------------------------------------------------------------------\n" - "|Low Power VSwing Pre-Emphasis Setting Table |\n" - "-----------------------------------------------------------------------------------------------------|\n" - "| | Pre-Emphasis (db) |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" - "| Voltage |------------------------------------------------------------------------- ---------------|\n" - "| Swing | Level 0/200 | 200mV,0db | 200mV,3.5db | 200mV,6db | 200mV,9db |\n" - "| (mV) |------------------------------------------------------------------------------------------|\n" - "| | Level 1/250 | 250mV,0db | 250mV,3.5db | 250mV,6db | NA |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | Level 2/300 | 300mV,0db | 300mV,3.5d | NA | NA |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | Level 3/350 | 350 mv, 0db | NA | NA | NA |\n" - "-----------------------------------------------------------------------------------------------------\n\n" - - "-----------------------------------------------------------------------------------------------------\n" - "|Default VSwing Pre-Emphasis Setting Table |\n" - "---------------------------------------------------------------------------------------------------|\n" - "| | Pre-Emphasis (db) |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" - "| Voltage |----------------------------------------------------------------------------------------|\n" - "| Swing | Level 0/400 | 400mV,0db | 400mV,3.5db | 400mV,6db | 400mV,9db |\n" - "| (mV) |----------------------------------------------------------------------------------------|\n" - "| | Level 1/600 | 600mV,0db | 600mV,3.5db | 600mV,6db | NA |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | Level 2/800 | 800mV,0db | 800mV,3.5db | NA | NA |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | Level 3/1200| 1200mV, 0db | NA | NA | NA |\n" - "-----------------------------------------------------------------------------------------------------\n\n" - - - Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Power Sequencing" - Link "eDP Fast Link Training Configuration" , "eDP Fast Link Training Configuration" - - Page "eDP Panel Power Sequencing" - Link "Close Table", ".." - - Combo $eDP_T3_Optimization_11, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/Graphics driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_11, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_11, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_11, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_11, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_11, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_11, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_11, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - - EndPage - - Page "eDP Fast Link Training Configuration" - - Link "Close Table" , ".." - Combo $Fast_Link_Training_Supported_11, " Is FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature if set to Yes will enable " - "Fast Link Training for eDp, if Panel also supports it." - - Combo $eDP_Link_DataRate_11, " Data Rate:", &eDP_Link_DataRate_List, - Help "This feature allows for the selection of the " - "Data Rate for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_11, " Lane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the " - "Lane Count (Port Width) for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_11, " Pre-Emphasis:", &eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the " - "Pre-emphasis value for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - - "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - "Column - Non-Transition VDiff \r\n" - "Row - Transition VDiff \r\n" - - Combo $eDP_Link_Vswing_11, " Voltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the " - "Voltage Swing value for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - - "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - "Column - Non-Transition VDiff \r\n" - "Row - Transition VDiff \r\n" - EndPage - #endif - - Page "DTD Timings" - - Link "Close Table" , ".." - - Table $DVO_Tbl_11 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD " - "timings parameters related to the LFP. The " - "table is the 18-byte DTD structure defined in the " - "VESA EDID version 1.x.\r\n" - "\r\n" - "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" - "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tDB ?\t; Vertical Active in lines, LSB\r\n" - "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Horizontal Image Size, LSB\r\n" - "\tDB ?\t; Vertical Image Size, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tDB 0\t; Horizontal Border in pixels\r\n" - "\tDB 0\t; Vertical Border in lines\r\n" - "\tDB ?\t; Flags:\r\n" - "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t; Bit 6-5: 00 = Reserved\r\n" - "\t \t; Bit 4-3: 11 = Digital Separate\r\n" - "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 0: 0 = Reserved" - - EndPage - - Page "LFP PnP ID" - - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_11 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor / " - "Product ID starting at offset 08h to be used as a " - "PnP ID.\r\n" - "\r\n" - " Table Definition:\r\n" - " Word: ID Manufacturer Name\r\n" - " Word: ID Product Code\r\n" - " DWord: ID Serial Number\r\n" - " Byte: Week of Manufacture\r\n" - " Byte: Year of Manufacture" - - EndPage - - Page "Backlight Control Parameters" - - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_11, " Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the " - "Backlight Inverter type that is to be used to " - "control the backlight brightness of the LFP. When " - "PWM is selected, the driver and VBIOS will control " - "the backlight brightness via the integrated PWM " - "solution for the applicable chipsets. When I2C is " - "selected, the driver and VBIOS will control the " - "backlight brightness via the I2C solution for the " - "applicable chipsets. When None/External is " - "selected, the system BIOS will control the backlight " - "brightness via the external solution." - - Combo $Lfp_Pwm_Source_Selection_11, " Pwm Source Selection:", &Edp_Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - "\r\n" - - Combo $BLC_Inv_Polarity_11, " Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity " - "to be specified.\r\n" - "\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_11, " Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum " - "backlight brightness setting. The graphics driver " - "will never decrease the backlight less than this " - "value. The value must be specified using normal " - "polarity semantics." - -EditNum $POST_BL_Brightness_11, " POST Backlight Intensity:", DEC, - Help "This feature is used to set default brightness value at POST." - "This is configurable field of 0-255. Value of 0 indicates 0 brightness, 255 indicates maximum brightness. " - - EditNum $PWM_Frequency_11, " PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the " - "frequency needed for PWM Inverter.\r\n" - "\r\n" - "Note: The frequency range, entered as a decimal " - "number, for the integrated PWM is 200Hz - 40KHz." - EndPage - - - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_11, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - Combo $Override_EDID_Data_11, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - EditNum $Red_Green_11, " Red_Green_bits (Bits 1&0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - EditNum $Blue_White_11, " Blue_White_bits (Bits 1&0 at 20h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - EditNum $Red_x_11, " Red_x (Bits 9->2 at 1Bh)" , EHEX, - Help " Bits 9->2 of red color x coordinate" - EditNum $Red_y_11, " Red_y (Bits 9->2 at 1Ch)" , EHEX, - Help " Bits 9->2 of red color y coordinate" - EditNum $Green_x_11, " Green_x (Bits 9->2 at 1Dh)" , EHEX, - Help " Bits 9->2 of Green color x coordinate" - EditNum $Green_y_11, " Green_y (Bits 9->2 at 1Eh)" , EHEX, - Help " Bits 9->2 of Green color y coordinate" - EditNum $Blue_x_11, " Blue_x (Bits 9->2 at 1Fh)" , EHEX, - Help " Bits 9->2 of Blue color x coordinate" - EditNum $Blue_y_11, " Blue_y (Bits 9->2 at 20h)" , EHEX, - Help " Bits 9->2 of Blue color y coordinate" - EditNum $White_x_11, " White_x (Bits 9->2 at 21h)" , EHEX, - Help " Bits 9->2 of White color x coordinate" - EditNum $White_y_11, " White_y (Bits 9->2 at 22h)" , EHEX, - Help " Bits 9->2 of White color y coordinate" - - EndPage ; Chromaticity Control -EndPage -;============================================================================== -; Page - Panel #12 (Reserved) Flat Panel parameters -;------------------------------------------------------------------------------ - -Page "Panel #12 " - - TitleB "Common LFP Features" - - EditText $Panel_Name_12, "\tLFP Panel Name:", - Help "This feature defines the LVDS panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated. " - - Combo $Enable_Scaling_12, "\tScale to Target Resolution:", &No_Yes_List, - Help "Selecting this feature will make the graphics driver to enable Scaling feature by taking the Horizontal and Vertical resolution\r\n" - "from Target X-Res and Target Y-Res fields.\r\n" - - EditNum $Panel_Width_12, "\tTarget X-Res:", DEC, - Help "This value specifies the Target X-Resolution for this panel." - - EditNum $Panel_Height_12, "\tTarget Y-Res:", DEC, - Help "This value specifies the Target Y-Resolutoin for this panel." - - - - Combo $DPS_Panel_Type_12, " \tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n " - "Intel SDRRS Technology is a feature of the Intel graphics driver\r\n" - "which reduces display power\r\n" - "SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n" - "rate will not adversely impact the user experience\r\n" - "Seamless:- Allows power savings when on battery mode and when a lower refresh\r\n" - "rate will not adversely impact the user experience.Implements seamless refresh\r\n" - "rate switching, which eliminates the screen blink that occurred\r\n" - "during the refresh rate transitions\r\n" - - EditNum $Seamless_DRRS_Min_RR_12, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, - Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n\n" - "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" - - Combo $Blt_Control_12, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology.\r\n " - - Title " " - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "DTD Timings Table" , "DTD Timings" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - - #if ($Int_LFP1_Type == 0x1806) - TitleB "Integrated eDP Features" - - -Combo $Enable_SSC12, " \teDP Spread Spectrum Clock:", &Disabled_Enabled_List, -Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " - - Combo $eDP_Panel_Color_Depth_12, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used. " - - Combo $eDP_VSwingPreEmph_12, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For CherryTrail, based on the selection respective table will be used.\r\n" - "Tables for CherryTrail:-\r\n" - "------------------------------------------------------------------------------------------------------\n" - "|Low Power VSwing Pre-Emphasis Setting Table |\n" - "-----------------------------------------------------------------------------------------------------|\n" - "| | Pre-Emphasis (db) |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" - "| Voltage |------------------------------------------------------------------------- ---------------|\n" - "| Swing | Level 0/200 | 200mV,0db | 200mV,3.5db | 200mV,6db | 200mV,9db |\n" - "| (mV) |------------------------------------------------------------------------------------------|\n" - "| | Level 1/250 | 250mV,0db | 250mV,3.5db | 250mV,6db | NA |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | Level 2/300 | 300mV,0db | 300mV,3.5d | NA | NA |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | Level 3/350 | 350 mv, 0db | NA | NA | NA |\n" - "-----------------------------------------------------------------------------------------------------\n\n" - - "-----------------------------------------------------------------------------------------------------\n" - "|Default VSwing Pre-Emphasis Setting Table |\n" - "---------------------------------------------------------------------------------------------------|\n" - "| | Pre-Emphasis (db) |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" - "| Voltage |----------------------------------------------------------------------------------------|\n" - "| Swing | Level 0/400 | 400mV,0db | 400mV,3.5db | 400mV,6db | 400mV,9db |\n" - "| (mV) |----------------------------------------------------------------------------------------|\n" - "| | Level 1/600 | 600mV,0db | 600mV,3.5db | 600mV,6db | NA |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | Level 2/800 | 800mV,0db | 800mV,3.5db | NA | NA |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | Level 3/1200| 1200mV, 0db | NA | NA | NA |\n" - "-----------------------------------------------------------------------------------------------------\n\n" - - - Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Power Sequencing" - Link "eDP Fast Link Training Configuration" , "eDP Fast Link Training Configuration" - - Page "eDP Panel Power Sequencing" - Link "Close Table", ".." - - Combo $eDP_T3_Optimization_12, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/Graphics driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_12, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_12, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_12, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_12, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_12, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_12, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_12, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - - EndPage - - Page "eDP Fast Link Training Configuration" - - Link "Close Table" , ".." - Combo $Fast_Link_Training_Supported_12, " Is FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature if set to Yes will enable " - "Fast Link Training for eDp, if Panel also supports it." - - Combo $eDP_Link_DataRate_12, " Data Rate:", &eDP_Link_DataRate_List, - Help "This feature allows for the selection of the " - "Data Rate for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_12, " Lane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the " - "Lane Count (Port Width) for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_12, " Pre-Emphasis:", &eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the " - "Pre-emphasis value for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - - "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - "Column - Non-Transition VDiff \r\n" - "Row - Transition VDiff \r\n" - - Combo $eDP_Link_Vswing_12, " Voltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the " - "Voltage Swing value for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - - "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - "Column - Non-Transition VDiff \r\n" - "Row - Transition VDiff \r\n" - EndPage - #endif - - Page "DTD Timings" - - Link "Close Table" , ".." - - Table $DVO_Tbl_12 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD " - "timings parameters related to the LFP. The " - "table is the 18-byte DTD structure defined in the " - "VESA EDID version 1.x.\r\n" - "\r\n" - "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" - "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tDB ?\t; Vertical Active in lines, LSB\r\n" - "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Horizontal Image Size, LSB\r\n" - "\tDB ?\t; Vertical Image Size, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tDB 0\t; Horizontal Border in pixels\r\n" - "\tDB 0\t; Vertical Border in lines\r\n" - "\tDB ?\t; Flags:\r\n" - "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t; Bit 6-5: 00 = Reserved\r\n" - "\t \t; Bit 4-3: 11 = Digital Separate\r\n" - "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 0: 0 = Reserved" - - EndPage - - Page "LFP PnP ID" - - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_12 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor / " - "Product ID starting at offset 08h to be used as a " - "PnP ID.\r\n" - "\r\n" - " Table Definition:\r\n" - " Word: ID Manufacturer Name\r\n" - " Word: ID Product Code\r\n" - " DWord: ID Serial Number\r\n" - " Byte: Week of Manufacture\r\n" - " Byte: Year of Manufacture" - - EndPage - - Page "Backlight Control Parameters" - - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_12, " Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the " - "Backlight Inverter type that is to be used to " - "control the backlight brightness of the LFP. When " - "PWM is selected, the driver and VBIOS will control " - "the backlight brightness via the integrated PWM " - "solution for the applicable chipsets. When I2C is " - "selected, the driver and VBIOS will control the " - "backlight brightness via the I2C solution for the " - "applicable chipsets. When None/External is " - "selected, the system BIOS will control the backlight " - "brightness via the external solution." - - Combo $Lfp_Pwm_Source_Selection_12, " Pwm Source Selection:", &Edp_Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - "\r\n" - - Combo $BLC_Inv_Polarity_12, " Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity " - "to be specified.\r\n" - "\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_12, " Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum " - "backlight brightness setting. The graphics driver " - "will never decrease the backlight less than this " - "value. The value must be specified using normal " - "polarity semantics." - -EditNum $POST_BL_Brightness_12, " POST Backlight Intensity:", DEC, - Help "This feature is used to set default brightness value at POST." - "This is configurable field of 0-255. Value of 0 indicates 0 brightness, 255 indicates maximum brightness. " - - EditNum $PWM_Frequency_12, " PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the " - "frequency needed for PWM Inverter.\r\n" - "\r\n" - "Note: The frequency range, entered as a decimal " - "number, for the integrated PWM is 200Hz - 40KHz." - EndPage - - - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_12, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - Combo $Override_EDID_Data_12, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - EditNum $Red_Green_12, " Red_Green_bits (Bits 1&0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - EditNum $Blue_White_12, " Blue_White_bits (Bits 1&0 at 20h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - EditNum $Red_x_12, " Red_x (Bits 9->2 at 1Bh)" , EHEX, - Help " Bits 9->2 of red color x coordinate" - EditNum $Red_y_12, " Red_y (Bits 9->2 at 1Ch)" , EHEX, - Help " Bits 9->2 of red color y coordinate" - EditNum $Green_x_12, " Green_x (Bits 9->2 at 1Dh)" , EHEX, - Help " Bits 9->2 of Green color x coordinate" - EditNum $Green_y_12, " Green_y (Bits 9->2 at 1Eh)" , EHEX, - Help " Bits 9->2 of Green color y coordinate" - EditNum $Blue_x_12, " Blue_x (Bits 9->2 at 1Fh)" , EHEX, - Help " Bits 9->2 of Blue color x coordinate" - EditNum $Blue_y_12, " Blue_y (Bits 9->2 at 20h)" , EHEX, - Help " Bits 9->2 of Blue color y coordinate" - EditNum $White_x_12, " White_x (Bits 9->2 at 21h)" , EHEX, - Help " Bits 9->2 of White color x coordinate" - EditNum $White_y_12, " White_y (Bits 9->2 at 22h)" , EHEX, - Help " Bits 9->2 of White color y coordinate" - - EndPage ; Chromaticity Control -EndPage -;============================================================================== -; Page - Panel #13 (Reserved) Flat Panel parameters -;------------------------------------------------------------------------------ - -Page "Panel #13 " - - TitleB "Common LFP Features" - - EditText $Panel_Name_13, "\tLFP Panel Name:", - Help "This feature defines the LVDS panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated. " - - Combo $Enable_Scaling_13, "\tScale to Target Resolution:", &No_Yes_List, - Help "Selecting this feature will make the graphics driver to enable Scaling feature by taking the Horizontal and Vertical resolution\r\n" - "from Target X-Res and Target Y-Res fields.\r\n" - - EditNum $Panel_Width_13, "\tTarget X-Res:", DEC, - Help "This value specifies the Target X-Resolution for this panel." - - EditNum $Panel_Height_13, "\tTarget Y-Res:", DEC, - Help "This value specifies the Target Y-Resolutoin for this panel." - - - - Combo $DPS_Panel_Type_13, " \tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n " - "Intel SDRRS Technology is a feature of the Intel graphics driver\r\n" - "which reduces display power\r\n" - "SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n" - "rate will not adversely impact the user experience\r\n" - "Seamless:- Allows power savings when on battery mode and when a lower refresh\r\n" - "rate will not adversely impact the user experience.Implements seamless refresh\r\n" - "rate switching, which eliminates the screen blink that occurred\r\n" - "during the refresh rate transitions\r\n" - - EditNum $Seamless_DRRS_Min_RR_13, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, - Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n\n" - "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" - - Combo $Blt_Control_13, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology.\r\n " - - Title " " - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "DTD Timings Table" , "DTD Timings" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - - #if ($Int_LFP1_Type == 0x1806) - TitleB "Integrated eDP Features" - -Combo $Enable_SSC13, " \teDP Spread Spectrum Clock:", &Disabled_Enabled_List, -Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " - - - Combo $eDP_Panel_Color_Depth_13, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used. " - - Combo $eDP_VSwingPreEmph_13, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For CherryTrail, based on the selection respective table will be used.\r\n" - "Tables for CherryTrail:-\r\n" - "------------------------------------------------------------------------------------------------------\n" - "|Low Power VSwing Pre-Emphasis Setting Table |\n" - "-----------------------------------------------------------------------------------------------------|\n" - "| | Pre-Emphasis (db) |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" - "| Voltage |------------------------------------------------------------------------- ---------------|\n" - "| Swing | Level 0/200 | 200mV,0db | 200mV,3.5db | 200mV,6db | 200mV,9db |\n" - "| (mV) |------------------------------------------------------------------------------------------|\n" - "| | Level 1/250 | 250mV,0db | 250mV,3.5db | 250mV,6db | NA |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | Level 2/300 | 300mV,0db | 300mV,3.5d | NA | NA |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | Level 3/350 | 350 mv, 0db | NA | NA | NA |\n" - "-----------------------------------------------------------------------------------------------------\n\n" - - "-----------------------------------------------------------------------------------------------------\n" - "|Default VSwing Pre-Emphasis Setting Table |\n" - "---------------------------------------------------------------------------------------------------|\n" - "| | Pre-Emphasis (db) |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" - "| Voltage |----------------------------------------------------------------------------------------|\n" - "| Swing | Level 0/400 | 400mV,0db | 400mV,3.5db | 400mV,6db | 400mV,9db |\n" - "| (mV) |----------------------------------------------------------------------------------------|\n" - "| | Level 1/600 | 600mV,0db | 600mV,3.5db | 600mV,6db | NA |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | Level 2/800 | 800mV,0db | 800mV,3.5db | NA | NA |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | Level 3/1200| 1200mV, 0db | NA | NA | NA |\n" - "-----------------------------------------------------------------------------------------------------\n\n" - - - Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Power Sequencing" - Link "eDP Fast Link Training Configuration" , "eDP Fast Link Training Configuration" - - Page "eDP Panel Power Sequencing" - Link "Close Table", ".." - - Combo $eDP_T3_Optimization_13, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/Graphics driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_13, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_13, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_13, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_13, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_13, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_13, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_13, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - - EndPage - - Page "eDP Fast Link Training Configuration" - - Link "Close Table" , ".." - Combo $Fast_Link_Training_Supported_13, " Is FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature if set to Yes will enable " - "Fast Link Training for eDp, if Panel also supports it." - - Combo $eDP_Link_DataRate_13, " Data Rate:", &eDP_Link_DataRate_List, - Help "This feature allows for the selection of the " - "Data Rate for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_13, " Lane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the " - "Lane Count (Port Width) for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_13, " Pre-Emphasis:", &eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the " - "Pre-emphasis value for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - - "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - "Column - Non-Transition VDiff \r\n" - "Row - Transition VDiff \r\n" - - Combo $eDP_Link_Vswing_13, " Voltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the " - "Voltage Swing value for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - - "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - "Column - Non-Transition VDiff \r\n" - "Row - Transition VDiff \r\n" - EndPage - #endif - - Page "DTD Timings" - - Link "Close Table" , ".." - - Table $DVO_Tbl_13 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD " - "timings parameters related to the LFP. The " - "table is the 18-byte DTD structure defined in the " - "VESA EDID version 1.x.\r\n" - "\r\n" - "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" - "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tDB ?\t; Vertical Active in lines, LSB\r\n" - "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Horizontal Image Size, LSB\r\n" - "\tDB ?\t; Vertical Image Size, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tDB 0\t; Horizontal Border in pixels\r\n" - "\tDB 0\t; Vertical Border in lines\r\n" - "\tDB ?\t; Flags:\r\n" - "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t; Bit 6-5: 00 = Reserved\r\n" - "\t \t; Bit 4-3: 11 = Digital Separate\r\n" - "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 0: 0 = Reserved" - - EndPage - - Page "LFP PnP ID" - - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_13 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor / " - "Product ID starting at offset 08h to be used as a " - "PnP ID.\r\n" - "\r\n" - " Table Definition:\r\n" - " Word: ID Manufacturer Name\r\n" - " Word: ID Product Code\r\n" - " DWord: ID Serial Number\r\n" - " Byte: Week of Manufacture\r\n" - " Byte: Year of Manufacture" - - EndPage - - Page "Backlight Control Parameters" - - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_13, " Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the " - "Backlight Inverter type that is to be used to " - "control the backlight brightness of the LFP. When " - "PWM is selected, the driver and VBIOS will control " - "the backlight brightness via the integrated PWM " - "solution for the applicable chipsets. When I2C is " - "selected, the driver and VBIOS will control the " - "backlight brightness via the I2C solution for the " - "applicable chipsets. When None/External is " - "selected, the system BIOS will control the backlight " - "brightness via the external solution." - - Combo $Lfp_Pwm_Source_Selection_13, " Pwm Source Selection:", &Edp_Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - "\r\n" - - Combo $BLC_Inv_Polarity_13, " Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity " - "to be specified.\r\n" - "\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_13, " Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum " - "backlight brightness setting. The graphics driver " - "will never decrease the backlight less than this " - "value. The value must be specified using normal " - "polarity semantics." - -EditNum $POST_BL_Brightness_13, " POST Backlight Intensity:", DEC, - Help "This feature is used to set default brightness value at POST." - "This is configurable field of 0-255. Value of 0 indicates 0 brightness, 255 indicates maximum brightness. " - - EditNum $PWM_Frequency_13, " PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the " - "frequency needed for PWM Inverter.\r\n" - "\r\n" - "Note: The frequency range, entered as a decimal " - "number, for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_13, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - Combo $Override_EDID_Data_13, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - EditNum $Red_Green_13, " Red_Green_bits (Bits 1&0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - EditNum $Blue_White_13, " Blue_White_bits (Bits 1&0 at 20h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - EditNum $Red_x_13, " Red_x (Bits 9->2 at 1Bh)" , EHEX, - Help " Bits 9->2 of red color x coordinate" - EditNum $Red_y_13, " Red_y (Bits 9->2 at 1Ch)" , EHEX, - Help " Bits 9->2 of red color y coordinate" - EditNum $Green_x_13, " Green_x (Bits 9->2 at 1Dh)" , EHEX, - Help " Bits 9->2 of Green color x coordinate" - EditNum $Green_y_13, " Green_y (Bits 9->2 at 1Eh)" , EHEX, - Help " Bits 9->2 of Green color y coordinate" - EditNum $Blue_x_13, " Blue_x (Bits 9->2 at 1Fh)" , EHEX, - Help " Bits 9->2 of Blue color x coordinate" - EditNum $Blue_y_13, " Blue_y (Bits 9->2 at 20h)" , EHEX, - Help " Bits 9->2 of Blue color y coordinate" - EditNum $White_x_13, " White_x (Bits 9->2 at 21h)" , EHEX, - Help " Bits 9->2 of White color x coordinate" - EditNum $White_y_13, " White_y (Bits 9->2 at 22h)" , EHEX, - Help " Bits 9->2 of White color y coordinate" - - EndPage ; Chromaticity Control - -EndPage -;============================================================================== -; Page - Panel #14 (1280x800) Flat Panel parameters -;------------------------------------------------------------------------------ - -Page "Panel #14 " - - TitleB "Common LFP Features" - - EditText $Panel_Name_14, "\tLFP Panel Name:", - Help "This feature defines the LVDS panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated. " - - Combo $Enable_Scaling_14, "\tScale to Target Resolution:", &No_Yes_List, - Help "Selecting this feature will make the graphics driver to enable Scaling feature by taking the Horizontal and Vertical resolution\r\n" - "from Target X-Res and Target Y-Res fields.\r\n" - - EditNum $Panel_Width_14, "\tTarget X-Res:", DEC, - Help "This value specifies the Target X-Resolution for this panel." - - EditNum $Panel_Height_14, "\tTarget Y-Res:", DEC, - Help "This value specifies the Target Y-Resolutoin for this panel." - - - - Combo $DPS_Panel_Type_14, " \tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n " - "Intel SDRRS Technology is a feature of the Intel graphics driver\r\n" - "which reduces display power\r\n" - "SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n" - "rate will not adversely impact the user experience\r\n" - "Seamless:- Allows power savings when on battery mode and when a lower refresh\r\n" - "rate will not adversely impact the user experience.Implements seamless refresh\r\n" - "rate switching, which eliminates the screen blink that occurred\r\n" - "during the refresh rate transitions\r\n" - - EditNum $Seamless_DRRS_Min_RR_14, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, - Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n\n" - "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" - - Combo $Blt_Control_14, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology.\r\n " - - Title " " - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "DTD Timings Table" , "DTD Timings" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - - #if ($Int_LFP1_Type == 0x1806) - TitleB "Integrated eDP Features" - - -Combo $Enable_SSC14, " \teDP Spread Spectrum Clock:", &Disabled_Enabled_List, -Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " - - Combo $eDP_Panel_Color_Depth_14, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used. " - - Combo $eDP_VSwingPreEmph_14, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For CherryTrail, based on the selection respective table will be used.\r\n" - "Tables for CherryTrail:-\r\n" - "------------------------------------------------------------------------------------------------------\n" - "|Low Power VSwing Pre-Emphasis Setting Table |\n" - "-----------------------------------------------------------------------------------------------------|\n" - "| | Pre-Emphasis (db) |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" - "| Voltage |------------------------------------------------------------------------- ---------------|\n" - "| Swing | Level 0/200 | 200mV,0db | 200mV,3.5db | 200mV,6db | 200mV,9db |\n" - "| (mV) |------------------------------------------------------------------------------------------|\n" - "| | Level 1/250 | 250mV,0db | 250mV,3.5db | 250mV,6db | NA |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | Level 2/300 | 300mV,0db | 300mV,3.5d | NA | NA |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | Level 3/350 | 350 mv, 0db | NA | NA | NA |\n" - "-----------------------------------------------------------------------------------------------------\n\n" - - "-----------------------------------------------------------------------------------------------------\n" - "|Default VSwing Pre-Emphasis Setting Table |\n" - "---------------------------------------------------------------------------------------------------|\n" - "| | Pre-Emphasis (db) |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" - "| Voltage |----------------------------------------------------------------------------------------|\n" - "| Swing | Level 0/400 | 400mV,0db | 400mV,3.5db | 400mV,6db | 400mV,9db |\n" - "| (mV) |----------------------------------------------------------------------------------------|\n" - "| | Level 1/600 | 600mV,0db | 600mV,3.5db | 600mV,6db | NA |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | Level 2/800 | 800mV,0db | 800mV,3.5db | NA | NA |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | Level 3/1200| 1200mV, 0db | NA | NA | NA |\n" - "-----------------------------------------------------------------------------------------------------\n\n" - - - Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Power Sequencing" - Link "eDP Fast Link Training Configuration" , "eDP Fast Link Training Configuration" - - Page "eDP Panel Power Sequencing" - Link "Close Table", ".." - - Combo $eDP_T3_Optimization_14, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/Graphics driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_14, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_14, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_14, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_14, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_14, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_14, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_14, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - - EndPage - - Page "eDP Fast Link Training Configuration" - - Link "Close Table" , ".." - Combo $Fast_Link_Training_Supported_14, " Is FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature if set to Yes will enable " - "Fast Link Training for eDp, if Panel also supports it." - - Combo $eDP_Link_DataRate_14, " Data Rate:", &eDP_Link_DataRate_List, - Help "This feature allows for the selection of the " - "Data Rate for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_14, " Lane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the " - "Lane Count (Port Width) for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_14, " Pre-Emphasis:", &eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the " - "Pre-emphasis value for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - - "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - "Column - Non-Transition VDiff \r\n" - "Row - Transition VDiff \r\n" - - Combo $eDP_Link_Vswing_14, " Voltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the " - "Voltage Swing value for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - - "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - "Column - Non-Transition VDiff \r\n" - "Row - Transition VDiff \r\n" - EndPage - #endif - - Page "DTD Timings" - - Link "Close Table" , ".." - - Table $DVO_Tbl_14 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD " - "timings parameters related to the LFP. The " - "table is the 18-byte DTD structure defined in the " - "VESA EDID version 1.x.\r\n" - "\r\n" - "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" - "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tDB ?\t; Vertical Active in lines, LSB\r\n" - "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Horizontal Image Size, LSB\r\n" - "\tDB ?\t; Vertical Image Size, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tDB 0\t; Horizontal Border in pixels\r\n" - "\tDB 0\t; Vertical Border in lines\r\n" - "\tDB ?\t; Flags:\r\n" - "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t; Bit 6-5: 00 = Reserved\r\n" - "\t \t; Bit 4-3: 11 = Digital Separate\r\n" - "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 0: 0 = Reserved" - - EndPage - - Page "LFP PnP ID" - - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_14 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor / " - "Product ID starting at offset 08h to be used as a " - "PnP ID.\r\n" - "\r\n" - " Table Definition:\r\n" - " Word: ID Manufacturer Name\r\n" - " Word: ID Product Code\r\n" - " DWord: ID Serial Number\r\n" - " Byte: Week of Manufacture\r\n" - " Byte: Year of Manufacture" - - EndPage - - Page "Backlight Control Parameters" - - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_14, " Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the " - "Backlight Inverter type that is to be used to " - "control the backlight brightness of the LFP. When " - "PWM is selected, the driver and VBIOS will control " - "the backlight brightness via the integrated PWM " - "solution for the applicable chipsets. When I2C is " - "selected, the driver and VBIOS will control the " - "backlight brightness via the I2C solution for the " - "applicable chipsets. When None/External is " - "selected, the system BIOS will control the backlight " - "brightness via the external solution." - - Combo $Lfp_Pwm_Source_Selection_14, " Pwm Source Selection:", &Edp_Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - "\r\n" - - Combo $BLC_Inv_Polarity_14, " Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity " - "to be specified.\r\n" - "\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_14, " Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum " - "backlight brightness setting. The graphics driver " - "will never decrease the backlight less than this " - "value. The value must be specified using normal " - "polarity semantics." - -EditNum $POST_BL_Brightness_14, " POST Backlight Intensity:", DEC, - Help "This feature is used to set default brightness value at POST." - "This is configurable field of 0-255. Value of 0 indicates 0 brightness, 255 indicates maximum brightness. " - - EditNum $PWM_Frequency_14, " PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the " - "frequency needed for PWM Inverter.\r\n" - "\r\n" - "Note: The frequency range, entered as a decimal " - "number, for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_14, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - Combo $Override_EDID_Data_14, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - EditNum $Red_Green_14, " Red_Green_bits (Bits 1&0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - EditNum $Blue_White_14, " Blue_White_bits (Bits 1&0 at 20h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - EditNum $Red_x_14, " Red_x (Bits 9->2 at 1Bh)" , EHEX, - Help " Bits 9->2 of red color x coordinate" - EditNum $Red_y_14, " Red_y (Bits 9->2 at 1Ch)" , EHEX, - Help " Bits 9->2 of red color y coordinate" - EditNum $Green_x_14, " Green_x (Bits 9->2 at 1Dh)" , EHEX, - Help " Bits 9->2 of Green color x coordinate" - EditNum $Green_y_14, " Green_y (Bits 9->2 at 1Eh)" , EHEX, - Help " Bits 9->2 of Green color y coordinate" - EditNum $Blue_x_14, " Blue_x (Bits 9->2 at 1Fh)" , EHEX, - Help " Bits 9->2 of Blue color x coordinate" - EditNum $Blue_y_14, " Blue_y (Bits 9->2 at 20h)" , EHEX, - Help " Bits 9->2 of Blue color y coordinate" - EditNum $White_x_14, " White_x (Bits 9->2 at 21h)" , EHEX, - Help " Bits 9->2 of White color x coordinate" - EditNum $White_y_14, " White_y (Bits 9->2 at 22h)" , EHEX, - Help " Bits 9->2 of White color y coordinate" - - EndPage ; Chromaticity Control - -EndPage - -;============================================================================== -; Page - Panel #15 (1280x600) Flat Panel parameters -;------------------------------------------------------------------------------ - -Page "Panel #15 " - - TitleB "Common LFP Features" - - EditText $Panel_Name_15, "\tLFP Panel Name:", - Help "This feature defines the LVDS panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated. " - - Combo $Enable_Scaling_15, "\tScale to Target Resolution:", &No_Yes_List, - Help "Selecting this feature will make the graphics driver to enable Scaling feature by taking the Horizontal and Vertical resolution\r\n" - "from Target X-Res and Target Y-Res fields.\r\n" - - EditNum $Panel_Width_15, "\tTarget X-Res:", DEC, - Help "This value specifies the Target X-Resolution for this panel." - - EditNum $Panel_Height_15, "\tTarget Y-Res:", DEC, - Help "This value specifies the Target Y-Resolutoin for this panel." - - - - - Combo $DPS_Panel_Type_15, " \tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n " - "Intel SDRRS Technology is a feature of the Intel graphics driver\r\n" - "which reduces display power\r\n" - "SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n" - "rate will not adversely impact the user experience\r\n" - "Seamless:- Allows power savings when on battery mode and when a lower refresh\r\n" - "rate will not adversely impact the user experience.Implements seamless refresh\r\n" - "rate switching, which eliminates the screen blink that occurred\r\n" - "during the refresh rate transitions\r\n" - - EditNum $Seamless_DRRS_Min_RR_15, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, - Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n\n" - "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" - - Combo $Blt_Control_15, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology.\r\n " - - Title " " - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "DTD Timings Table" , "DTD Timings" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - - #if ($Int_LFP1_Type == 0x1806) - TitleB "Integrated eDP Features" - -Combo $Enable_SSC15, " \teDP Spread Spectrum Clock:", &Disabled_Enabled_List, -Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " - - Combo $eDP_Panel_Color_Depth_15, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used. " - - Combo $eDP_VSwingPreEmph_15, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For CherryTrail, based on the selection respective table will be used.\r\n" - "Tables for CherryTrail:-\r\n" - "------------------------------------------------------------------------------------------------------\n" - "|Low Power VSwing Pre-Emphasis Setting Table |\n" - "-----------------------------------------------------------------------------------------------------|\n" - "| | Pre-Emphasis (db) |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" - "| Voltage |------------------------------------------------------------------------- ---------------|\n" - "| Swing | Level 0/200 | 200mV,0db | 200mV,3.5db | 200mV,6db | 200mV,9db |\n" - "| (mV) |------------------------------------------------------------------------------------------|\n" - "| | Level 1/250 | 250mV,0db | 250mV,3.5db | 250mV,6db | NA |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | Level 2/300 | 300mV,0db | 300mV,3.5d | NA | NA |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | Level 3/350 | 350 mv, 0db | NA | NA | NA |\n" - "-----------------------------------------------------------------------------------------------------\n\n" - - "-----------------------------------------------------------------------------------------------------\n" - "|Default VSwing Pre-Emphasis Setting Table |\n" - "---------------------------------------------------------------------------------------------------|\n" - "| | Pre-Emphasis (db) |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" - "| Voltage |----------------------------------------------------------------------------------------|\n" - "| Swing | Level 0/400 | 400mV,0db | 400mV,3.5db | 400mV,6db | 400mV,9db |\n" - "| (mV) |----------------------------------------------------------------------------------------|\n" - "| | Level 1/600 | 600mV,0db | 600mV,3.5db | 600mV,6db | NA |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | Level 2/800 | 800mV,0db | 800mV,3.5db | NA | NA |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | Level 3/1200| 1200mV, 0db | NA | NA | NA |\n" - "-----------------------------------------------------------------------------------------------------\n\n" - - - Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Power Sequencing" - Link "eDP Fast Link Training Configuration" , "eDP Fast Link Training Configuration" - - Page "eDP Panel Power Sequencing" - Link "Close Table", ".." - - Combo $eDP_T3_Optimization_15, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/Graphics driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_15, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_15, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_15, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_15, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_15, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_15, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_15, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - - EndPage - - Page "eDP Fast Link Training Configuration" - - Link "Close Table" , ".." - Combo $Fast_Link_Training_Supported_15, " Is FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature if set to Yes will enable " - "Fast Link Training for eDp, if Panel also supports it." - - Combo $eDP_Link_DataRate_15, " Data Rate:", &eDP_Link_DataRate_List, - Help "This feature allows for the selection of the " - "Data Rate for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_15, " Lane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the " - "Lane Count (Port Width) for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_15, " Pre-Emphasis:", &eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the " - "Pre-emphasis value for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - - "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - "Column - Non-Transition VDiff \r\n" - "Row - Transition VDiff \r\n" - - Combo $eDP_Link_Vswing_15, " Voltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the " - "Voltage Swing value for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - - "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - "Column - Non-Transition VDiff \r\n" - "Row - Transition VDiff \r\n" - EndPage - #endif - - Page "DTD Timings" - - Link "Close Table" , ".." - - Table $DVO_Tbl_15 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD " - "timings parameters related to the LFP. The " - "table is the 18-byte DTD structure defined in the " - "VESA EDID version 1.x.\r\n" - "\r\n" - "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" - "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tDB ?\t; Vertical Active in lines, LSB\r\n" - "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Horizontal Image Size, LSB\r\n" - "\tDB ?\t; Vertical Image Size, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tDB 0\t; Horizontal Border in pixels\r\n" - "\tDB 0\t; Vertical Border in lines\r\n" - "\tDB ?\t; Flags:\r\n" - "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t; Bit 6-5: 00 = Reserved\r\n" - "\t \t; Bit 4-3: 11 = Digital Separate\r\n" - "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 0: 0 = Reserved" - - EndPage - - Page "LFP PnP ID" - - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_15 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor / " - "Product ID starting at offset 08h to be used as a " - "PnP ID.\r\n" - "\r\n" - " Table Definition:\r\n" - " Word: ID Manufacturer Name\r\n" - " Word: ID Product Code\r\n" - " DWord: ID Serial Number\r\n" - " Byte: Week of Manufacture\r\n" - " Byte: Year of Manufacture" - - EndPage - - Page "Backlight Control Parameters" - - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_15, " Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the " - "Backlight Inverter type that is to be used to " - "control the backlight brightness of the LFP. When " - "PWM is selected, the driver and VBIOS will control " - "the backlight brightness via the integrated PWM " - "solution for the applicable chipsets. When I2C is " - "selected, the driver and VBIOS will control the " - "backlight brightness via the I2C solution for the " - "applicable chipsets. When None/External is " - "selected, the system BIOS will control the backlight " - "brightness via the external solution." - - Combo $Lfp_Pwm_Source_Selection_15, " Pwm Source Selection:", &Edp_Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - "\r\n" - - Combo $BLC_Inv_Polarity_15, " Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity " - "to be specified.\r\n" - "\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_15, " Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum " - "backlight brightness setting. The graphics driver " - "will never decrease the backlight less than this " - "value. The value must be specified using normal " - "polarity semantics." - -EditNum $POST_BL_Brightness_15, " POST Backlight Intensity:", DEC, - Help "This feature is used to set default brightness value at POST." - "This is configurable field of 0-255. Value of 0 indicates 0 brightness, 255 indicates maximum brightness. " - - - EditNum $PWM_Frequency_15, " PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the " - "frequency needed for PWM Inverter.\r\n" - "\r\n" - "Note: The frequency range, entered as a decimal " - "number, for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_15, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - Combo $Override_EDID_Data_15, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - EditNum $Red_Green_15, " Red_Green_bits (Bits 1&0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - EditNum $Blue_White_15, " Blue_White_bits (Bits 1&0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - EditNum $Red_x_15, " Red_x (Bits 9->2 at 1Bh)" , EHEX, - Help " Bits 9->2 of red color x coordinate" - EditNum $Red_y_15, " Red_y (Bits 9->2 at 1Ch)" , EHEX, - Help " Bits 9->2 of red color y coordinate" - EditNum $Green_x_15, " Green_x (Bits 9->2 at 1Dh)" , EHEX, - Help " Bits 9->2 of Green color x coordinate" - EditNum $Green_y_15, " Green_y (Bits 9->2 at 1Eh)" , EHEX, - Help " Bits 9->2 of Green color y coordinate" - EditNum $Blue_x_15, " Blue_x (Bits 9->2 at 1Fh)" , EHEX, - Help " Bits 9->2 of Blue color x coordinate" - EditNum $Blue_y_15, " Blue_y (Bits 9->2 at 20h)" , EHEX, - Help " Bits 9->2 of Blue color y coordinate" - EditNum $White_x_15, " White_x (Bits 9->2 at 21h)" , EHEX, - Help " Bits 9->2 of White color x coordinate" - EditNum $White_y_15, " White_y (Bits 9->2 at 22h)" , EHEX, - Help " Bits 9->2 of White color y coordinate" - - EndPage ; Chromaticity Control - -EndPage - -;============================================================================== -; Page - Panel #16 (Reserved) Flat Panel parameters -;------------------------------------------------------------------------------ - -Page "Panel #16 " - - TitleB "Common LFP Features" - - EditText $Panel_Name_16, "\tLFP Panel Name:", - Help "This feature defines the LVDS panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated. " - - Combo $Enable_Scaling_16, "\tScale to Target Resolution:", &No_Yes_List, - Help "Selecting this feature will make the graphics driver to enable Scaling feature by taking the Horizontal and Vertical resolution\r\n" - "from Target X-Res and Target Y-Res fields.\r\n" - - EditNum $Panel_Width_16, "\tTarget X-Res:", DEC, - Help "This value specifies the Target X-Resolution for this panel." - - EditNum $Panel_Height_16, "\tTarget Y-Res:", DEC, - Help "This value specifies the Target Y-Resolutoin for this panel." - - - - - Combo $DPS_Panel_Type_16, " \tDPS Panel Type:", &DPS_Panel_Type_List, - Help "This feature allows OEM to select the DPS Panel Type.\r\n " - "Intel SDRRS Technology is a feature of the Intel graphics driver\r\n" - "which reduces display power\r\n" - "SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n" - "rate will not adversely impact the user experience\r\n" - "Seamless:- Allows power savings when on battery mode and when a lower refresh\r\n" - "rate will not adversely impact the user experience.Implements seamless refresh\r\n" - "rate switching, which eliminates the screen blink that occurred\r\n" - "during the refresh rate transitions\r\n" - - EditNum $Seamless_DRRS_Min_RR_16, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, - Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n\n" - "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" - - Combo $Blt_Control_16, "\tBackLight Technology:", &Blt_Control_Type_List, - Help "This feature allows OEM to select the Backlight Technology.\r\n " - - Title " " - Link "LFP PnP ID Table" , "LFP PnP ID" - Link "DTD Timings Table" , "DTD Timings" - Link "Backlight Control Parameters" , "Backlight Control Parameters" - Link "Chromaticity Control" , "Chromaticity Control" - - #if ($Int_LFP1_Type == 0x1806) - TitleB "Integrated eDP Features" - -Combo $Enable_SSC16, " \teDP Spread Spectrum Clock:", &Disabled_Enabled_List, -Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " - - Combo $eDP_Panel_Color_Depth_16, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, - Help "This feature specifies the color depth of eDP panel used. " - - Combo $eDP_VSwingPreEmph_16, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, - Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " - "For CherryTrail, based on the selection respective table will be used.\r\n" - "Tables for CherryTrail:-\r\n" - "------------------------------------------------------------------------------------------------------\n" - "|Low Power VSwing Pre-Emphasis Setting Table |\n" - "-----------------------------------------------------------------------------------------------------|\n" - "| | Pre-Emphasis (db) |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" - "| Voltage |------------------------------------------------------------------------- ---------------|\n" - "| Swing | Level 0/200 | 200mV,0db | 200mV,3.5db | 200mV,6db | 200mV,9db |\n" - "| (mV) |------------------------------------------------------------------------------------------|\n" - "| | Level 1/250 | 250mV,0db | 250mV,3.5db | 250mV,6db | NA |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | Level 2/300 | 300mV,0db | 300mV,3.5d | NA | NA |\n" - "| |------------------------------------------------------------------------------------------|\n" - "| | Level 3/350 | 350 mv, 0db | NA | NA | NA |\n" - "-----------------------------------------------------------------------------------------------------\n\n" - - "-----------------------------------------------------------------------------------------------------\n" - "|Default VSwing Pre-Emphasis Setting Table |\n" - "---------------------------------------------------------------------------------------------------|\n" - "| | Pre-Emphasis (db) |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" - "| Voltage |----------------------------------------------------------------------------------------|\n" - "| Swing | Level 0/400 | 400mV,0db | 400mV,3.5db | 400mV,6db | 400mV,9db |\n" - "| (mV) |----------------------------------------------------------------------------------------|\n" - "| | Level 1/600 | 600mV,0db | 600mV,3.5db | 600mV,6db | NA |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | Level 2/800 | 800mV,0db | 800mV,3.5db | NA | NA |\n" - "| |----------------------------------------------------------------------------------------|\n" - "| | Level 3/1200| 1200mV, 0db | NA | NA | NA |\n" - "-----------------------------------------------------------------------------------------------------\n\n" - - - Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Power Sequencing" - Link "eDP Fast Link Training Configuration" , "eDP Fast Link Training Configuration" - - Page "eDP Panel Power Sequencing" - Link "Close Table", ".." - - Combo $eDP_T3_Optimization_16, "T3 optimization", &Disabled_Enabled_List, - Help "This feature enables or disables T3 optimization. \r\n" - "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" - "When disabled, VBIOS/Graphics driver will wait for T3 time before trying the first AUX transaction" - - EditNum $eDP_Vcc_To_Hpd_Delay_16, "LCDVCC to HPD high delay (T3):", DEC, - Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" - "Valid Range: 0 to 200msec\r\n" - - EditNum $eDP_DataOn_To_BkltEnable_Delay_16, "Valid video data to Backlight Enable delay (T8):", DEC, - Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" - "T8 is inclusive of T7.\r\n" - "Valid Range of T7: 0 to 50msec\r\n" - - EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_16, "PWM-On To Backlight Enable delay:", DEC, - Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" - "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" - "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" - - EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_16, "Backlight Disable to PWM-Off delay:", DEC, - Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" - "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" - "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" - - EditNum $eDP_BkltDisable_To_DataOff_Delay_16, "Backlight Disable to End of Valid video data delay (T9):", DEC, - Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" - - EditNum $eDP_DataOff_To_PowerOff_Delay_16, "End of Valid video data to Power-Off delay (T10):", DEC, - Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" - "Valid Range: 0 to 500 msec\r\n" - - EditNum $eDP_PowerCycle_Delay_16, "Power-off time (T12):", DEC, - Help "Using this field Power-off time can be specified in 100uS.\r\n" - - EndPage - - Page "eDP Fast Link Training Configuration" - - Link "Close Table" , ".." - Combo $Fast_Link_Training_Supported_16, " Is FastLinkTraining Feature Supported:", &No_Yes_List, - Help "This feature if set to Yes will enable " - "Fast Link Training for eDp, if Panel also supports it." - - Combo $eDP_Link_DataRate_16, " Data Rate:", &eDP_Link_DataRate_List, - Help "This feature allows for the selection of the " - "Data Rate for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_LaneCount_16, " Lane Count:", &eDP_Link_LaneCount_List, - Help "This feature allows for the selection of the " - "Lane Count (Port Width) for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - Combo $eDP_Link_PreEmp_16, " Pre-Emphasis:", &eDP_Link_PreEmp_List, - Help "This feature allows for the selection of the " - "Pre-emphasis value for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - - "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - "Column - Non-Transition VDiff \r\n" - "Row - Transition VDiff \r\n" - - Combo $eDP_Link_Vswing_16, " Voltage Swing:", &eDP_Link_VSwing_List, - Help "This feature allows for the selection of the " - "Voltage Swing value for the embedded DP link. It will be used if the " - "sink indicates that no aux handshake is required during link training." - - "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - - "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - " \t | \t\t PreEmphasis Levels\t\t | \r\n" - "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" - "---------------------------------------------------------------------------------------------------\r\n" - "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" - "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" - "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" - "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" - "------------------------------------------------------------------------------------------------------------ \r\n" - "Column - Non-Transition VDiff \r\n" - "Row - Transition VDiff \r\n" - EndPage - #endif - - Page "DTD Timings" - - Link "Close Table" , ".." - - Table $DVO_Tbl_16 " DTD Timings Values", - Column "Timings" , 1 byte , EHEX, - Help "This feature allows for the definition of the DTD " - "timings parameters related to the LFP. The " - "table is the 18-byte DTD structure defined in the " - "VESA EDID version 1.x.\r\n" - "\r\n" - "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" - "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tDB ?\t; Vertical Active in lines, LSB\r\n" - "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Horizontal Image Size, LSB\r\n" - "\tDB ?\t; Vertical Image Size, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tDB 0\t; Horizontal Border in pixels\r\n" - "\tDB 0\t; Vertical Border in lines\r\n" - "\tDB ?\t; Flags:\r\n" - "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t; Bit 6-5: 00 = Reserved\r\n" - "\t \t; Bit 4-3: 11 = Digital Separate\r\n" - "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 0: 0 = Reserved" - - EndPage - - Page "LFP PnP ID" - - Link "Close Table" , ".." - - Table $LVDS_PnP_ID_16 " LFP PnP ID Values", - Column "PnP ID" , 1 byte , EHEX, - Help "This feature allows the 10 bytes of EDID Vendor / " - "Product ID starting at offset 08h to be used as a " - "PnP ID.\r\n" - "\r\n" - " Table Definition:\r\n" - " Word: ID Manufacturer Name\r\n" - " Word: ID Product Code\r\n" - " DWord: ID Serial Number\r\n" - " Byte: Week of Manufacture\r\n" - " Byte: Year of Manufacture" - - EndPage - - Page "Backlight Control Parameters" - - Link "Close Table" , ".." - - Combo $BLC_Inv_Type_16, " Inverter Type:", &Inv_Type_List, - Help "This feature allows for the selection of the " - "Backlight Inverter type that is to be used to " - "control the backlight brightness of the LFP. When " - "PWM is selected, the driver and VBIOS will control " - "the backlight brightness via the integrated PWM " - "solution for the applicable chipsets. When I2C is " - "selected, the driver and VBIOS will control the " - "backlight brightness via the I2C solution for the " - "applicable chipsets. When None/External is " - "selected, the system BIOS will control the backlight " - "brightness via the external solution." - - Combo $Lfp_Pwm_Source_Selection_16, " Pwm Source Selection:", &Edp_Pwm_Source_List, - Help "This field allows to select the Source of the PWM to be used " - "for the selected Local Flat Panel.\r\n" - "\r\n" - - Combo $BLC_Inv_Polarity_16, " Inverter Polarity:", &Inv_Polarity_List, - Help "This feature allows the backlight inverter polarity " - "to be specified.\r\n" - "\r\n" - "Normal means 0 value is minimum brightness.\r\n" - "Inverted means 0 value is maximum brightness." - - EditNum $BLC_Min_Brightness_16, " Minimum Brightness:", DEC, - Help "This feature allows defining the absolute minimum " - "backlight brightness setting. The graphics driver " - "will never decrease the backlight less than this " - "value. The value must be specified using normal " - "polarity semantics." - -EditNum $POST_BL_Brightness_16, " POST Backlight Intensity:", DEC, - Help "This feature is used to set default brightness value at POST." - "This is configurable field of 0-255. Value of 0 indicates 0 brightness, 255 indicates maximum brightness. " - - EditNum $PWM_Frequency_16, " PWM Inverter Frequency (Hz):", DEC, - Help "This feature allows for the definition of the " - "frequency needed for PWM Inverter.\r\n" - "\r\n" - "Note: The frequency range, entered as a decimal " - "number, for the integrated PWM is 200Hz - 40KHz." - EndPage - - Page "Chromaticity Control" - Link "Close Table" , ".." - - Combo $Chromacity_Enable_16, "Chromaticity Control Feature", &Disabled_Enabled_List, - Help " This bit enables Chromaticity feature. \r\n" - " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" - " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" - " Please refer to section 3.7 of EDID Specification 1.4" - Combo $Override_EDID_Data_16, "Override the EDID values", &No_Yes_List, - Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" - EditNum $Red_Green_16, " Red_Green_bits (Bits 1&0 at 19h)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" - EditNum $Blue_White_16, " Blue_White_bits (Bits 1&0 at 1Ah)" , EHEX, - Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" - EditNum $Red_x_16, " Red_x (Bits 9->2 at 1Bh)" , EHEX, - Help " Bits 9->2 of red color x coordinate" - EditNum $Red_y_16, " Red_y (Bits 9->2 at 1Ch)" , EHEX, - Help " Bits 9->2 of red color y coordinate" - EditNum $Green_x_16, " Green_x (Bits 9->2 at 1Dh)" , EHEX, - Help " Bits 9->2 of Green color x coordinate" - EditNum $Green_y_16, " Green_y (Bits 9->2 at 1Eh)" , EHEX, - Help " Bits 9->2 of Green color y coordinate" - EditNum $Blue_x_16, " Blue_x (Bits 9->2 at 1F)" , EHEX, - Help " Bits 9->2 of Blue color x coordinate" - EditNum $Blue_y_16, " Blue_y (Bits 9->2 at 20h)" , EHEX, - Help " Bits 9->2 of Blue color y coordinate" - EditNum $White_x_16, " White_x (Bits 9->2 at 21h)" , EHEX, - Help " Bits 9->2 of White color x coordinate" - EditNum $White_y_16, " White_y (Bits 9->2 at 22h)h" , EHEX, - Help " Bits 9->2 of White color y coordinate" - - EndPage ; Chromaticity Control - - -EndPage -#endif - -EndPage ; "Integrated LFP Features" - - - -;============================================================================== -; Page - Display Device Toggle Lists -;------------------------------------------------------------------------------ - -Page "Display Device Toggle Lists" - - Link "Toggle/Capabilities List 1" , "Display Toggle List 1" - Link "Toggle/Capabilities List 2" , "Display Toggle List 2" - Link "Toggle/Capabilities List 3" , "Display Toggle List 3" - Link "Toggle/Capabilities List 4" , "Display Toggle List 4" - - Page "Display Toggle List 1" - - Link "Close Table" , ".." - - Table $Toggle_List1 "Display Toggle List 1", - Column "Display Select", 2 bytes, EHEX, - Help "These toggle lists are used by the video BIOS and " - "Graphics drivers to help support the system BIOS with " - "switch display device Hot Keys. The basic algorithm " - "in the current display is found on the list and the " - "next settable display combination is set. If no " - "settable display combinations are found the function " - "returns fail.\r\n" - "\r\n" - "Four lists are given to allow for multiple " - "Hot Keys or creative solutions.\r\n" - "\r\n" - "\t15\t14\t13\t12\t11\t10\t9\t8\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n" - "\tRsvd\tEFP3.3\tEFP2.3\tEFP1.3\tRsvd\tEFP3.2\tEFP2.2\tEFP1.2\tRsvd\tEFP2\tEFP3\tRsvd\tLFP\tEFP\tReserved\tReserved\r\n" - "\r\n" - "EFPx.x nomenclature\r\n" - "EFP1.2 - 2nd daisy chained DP port on EFP1 Port\r\n" - "EFP2.3 - 3rd daisy chained DP port on EFP2 Port\r\n" - "EFP3.2 - 2nd daisy chained DP port on EFP3 Port\r\n" - "Examples:\r\n" - "\t Display Config\r\n" - "\t00000000 00001100b ; Toggle display to EFP & LFP combination\r\n" - "\t00000100 00100100b ; Toggle display to EFP3 and EFP combination." - - EndPage - - Page "Display Toggle List 2" - - Link "Close Table" , ".." - - Table $Toggle_List2 "Display Toggle List 2", - Column "Display Select", 2 bytes, EHEX, - Help "These toggle lists are used by the video BIOS and " - "Graphics drivers to help support the system BIOS with " - "switch display device Hot Keys. The basic algorithm " - "in the current display is found on the list and the " - "next settable display combination is set. If no " - "settable display combinations are found the function " - "returns fail.\r\n" - "\r\n" - "Four lists are given to allow for multiple " - "Hot Keys or creative solutions.\r\n" - "\r\n" - "\t15\t14\t13\t12\t11\t10\t9\t8\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n" - "\tRsvd\tEFP3.3\tEFP2.3\tEFP1.3\tRsvd\tEFP3.2\tEFP2.2\tEFP1.2\tRsvd\tEFP2\tEFP3\tRsvd\tLFP\tEFP\tReserved\tReserved\r\n" - "\r\n" - "EFPx.x nomenclature\r\n" - "EFP1.2 - 2nd daisy chained DP port on EFP1 Port\r\n" - "EFP2.3 - 3rd daisy chained DP port on EFP2 Port\r\n" - "EFP3.2 - 2nd daisy chained DP port on EFP3 Port\r\n" - "Examples:\r\n" - "\t Display Config\r\n" - "\t00000000 00001100b ; Toggle display to EFP & LFP combination\r\n" - "\t00000100 00100100b ; Toggle display to EFP3 and EFP combination." - - EndPage - - Page "Display Toggle List 3" - - Link "Close Table" , ".." - - Table $Toggle_List3 "Display Toggle List 3", - Column "Display Select", 2 bytes, EHEX, - Help "These toggle lists are used by the video BIOS and " - "Graphics drivers to help support the system BIOS with " - "switch display device Hot Keys. The basic algorithm " - "in the current display is found on the list and the " - "next settable display combination is set. If no " - "settable display combinations are found the function " - "returns fail.\r\n" - "\r\n" - "Four lists are given to allow for multiple " - "Hot Keys or creative solutions.\r\n" - "\r\n" - "\t15\t14\t13\t12\t11\t10\t9\t8\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n" - "\tRsvd\tEFP3.3\tEFP2.3\tEFP1.3\tRsvd\tEFP3.2\tEFP2.2\tEFP1.2\tRsvd\tEFP2\tEFP3\tRsvd\tLFP\tEFP\tReserved\tReserved\r\n" - "\r\n" - "EFPx.x nomenclature\r\n" - "EFP1.2 - 2nd daisy chained DP port on EFP1 Port\r\n" - "EFP2.3 - 3rd daisy chained DP port on EFP2 Port\r\n" - "EFP3.2 - 2nd daisy chained DP port on EFP3 Port\r\n" - "Examples:\r\n" - "\t Display Config\r\n" - "\t00000000 00001100b ; Toggle display to EFP & LFP combination\r\n" - "\t00000100 00100100b ; Toggle display to EFP3 and EFP combination." - - EndPage - - Page "Display Toggle List 4" - - Link "Close Table" , ".." - - Table $Toggle_List4 "Display Toggle List 4", - Column "Display Select", 2 bytes, EHEX, - Help "These toggle lists are used by the video BIOS and " - "Graphics drivers to help support the system BIOS with " - "switch display device Hot Keys. The basic algorithm " - "in the current display is found on the list and the " - "next settable display combination is set. If no " - "settable display combinations are found the function " - "returns fail.\r\n" - "\r\n" - "Four lists are given to allow for multiple " - "Hot Keys or creative solutions.\r\n" - "\r\n" - "\t15\t14\t13\t12\t11\t10\t9\t8\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n" - "\tRsvd\tEFP3.3\tEFP2.3\tEFP1.3\tRsvd\tEFP3.2\tEFP2.2\tEFP1.2\tRsvd\tEFP2\tEFP3\tRsvd\tLFP\tEFP\tReserved\tReserved\r\n" - "\r\n" - "EFPx.x nomenclature\r\n" - "EFP1.2 - 2nd daisy chained DP port on EFP1 Port\r\n" - "EFP2.3 - 3rd daisy chained DP port on EFP2 Port\r\n" - "EFP3.2 - 2nd daisy chained DP port on EFP3 Port\r\n" - "Examples:\r\n" - "\t Display Config\r\n" - "\t00000000 00001100b ; Toggle display to EFP & LFP combination\r\n" - "\t00000100 00100100b ; Toggle display to EFP3 and EFP combination." - EndPage - -EndPage - -;============================================================================== -; Page - Modes Removal Table -;------------------------------------------------------------------------------ - -Page "Modes Removal Table" - - Table $Mode_Rem_Table "Modes Removal Table", - Column "X-Resolution", 2 bytes, DEC - Column "Y-Resolution", 2 bytes, DEC - Column "BPP", 1 byte, DEC - Column "Refresh Rate", 2 bytes, EHEX - Column "Removal Flags", 1 byte, EHEX - Column "Panel Type", 2 bytes, EHEX, - Help "This feature allows removing support for selected modes " - "resolutions.\r\n" - "\r\n" - "X-Resolution, Y-Resolution, and BPP in Decimal or " - "Hexadecimal (0FFFFh or 0FFh means disable all).\r\n" - "\r\n" - "Refresh Rate bitmap selection (0 = Do not remove, 1 = " - "Remove):\r\n" - "\r\n" - "\tBit 15-9 8 7 6 5 4 3 2 1 0 \r\n" - "\tRRate(Hz) Reserved 120 100 85 75 72 70 60 56 43i \r\n" - "\r\n" - "Removal Flags bitmap selection (0 = Do not remove, 1 = " - "Remove):\r\n" - "\r\n" - "\tBit 7 6 5 4 3 2 1 0 \r\n" - "\tComponent Rsvd Rsvd LFP EFP Rsvd CRT Driver VBIOS \r\n" - "\r\n" - "\tNote: 1) In order to remove mode from both Windows and DOS, " - "both Bit 1 and Bit 0 must be set to 1.\r\n" - "\r\n" - "(Mobile only) Panel Type bitmap selection (0 = Do not " - "remove, 1 = Remove if panel is active):/r/n" - "\r\n" - "\tBit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 \r\n" - "\tType 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 \r\n" - "\r\n" - "\tNote: Default is to remove a mode resolution from all " - "panel types." -EndPage - - -;============================================================================== -; Page - Display Configuration Removal Table -;------------------------------------------------------------------------------ - -Page "Display Configuration Removal Table" - - Table $Dev_Removed_Table " Display Device Configuration Removal Table", - Column "Pipe B" , 1 byte , BIN - Column "Pipe A" , 1 byte , BIN, - - Help "This feature allows blocking selected display configurations " - "by the video BIOS and driver.\r\n" - "\r\n" - "Display Devices are specified in the following bit patterns " - "(pipe A and B use the same bit pattern):\r\n" - "\r\n" - "\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n" - "\tLFP2\tEFP2\tRsvd\tRsvd\tLFP\tEFP\tRsvd\tCRT\r\n" - "\r\n" - "Examples:\r\n" - "\tPipe B Pipe A\r\n" - "\t00000000b, 00000101b ; EFP & CRT on Pipe A\r\n" - "\t00001100b, 00000001b ; EFP & LFP on Pipe B and CRT on " - "Pipe A" -EndPage - - -;============================================================================== -; Page - OEM Customizable Mode 2.0 -;------------------------------------------------------------------------------ - -Page "OEM Customizable Modes 2.0" - - Link "OEM Mode 1 Configuration", "OEM Mode #1" - Link "OEM Mode 2 Configuration", "OEM Mode #2" - Link "OEM Mode 3 Configuration", "OEM Mode #3" - Link "OEM Mode 4 Configuration", "OEM Mode #4" - Link "OEM Mode 5 Configuration", "OEM Mode #5" - Link "OEM Mode 6 Configuration", "OEM Mode #6" - - Page "OEM Mode #1" - - Link "Close Table" , ".." - - Title " 8 bpp = VGA mode 60h / VESA mode 160h" - Title " 16 bpp = VGA mode 61h / VESA mode 161h" - Title " 32 bpp = VGA mode 62h / VESA mode 162h" - - EditNum $OEM_Mode_Flags1, "Support Flags:", BIN, - Help "Support flags:" - "(0 = Disabled, 1 = Enabled)" - "\r\n\r\n" - "\tBit 7" - "\tBit 6" - "\tBit 5" - "\tBit 4" - "\tBit 3" - "\tBit 2" - "\tBit 1" - "\tBit 0" - "\r\n" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\tDriver" - "\tVBIOS" - "\r\n" - - EditNum $OEM_Display_Flags1, "Display Flags:", BIN, - Help "Display Flags:" - "(0 = Disabled, 1 = Enabled)" - "\r\n\r\n" - "\tBit 7" - "\tBit 6" - "\tBit 5" - "\tBit 4" - "\tBit 3" - "\tBit 2" - "\tBit 1" - "\tBit 0" - "\r\n" - "\tLFP2" - "\tEFP2" - "\tTV2" - "\tCRT2" - "\tLFP" - "\tEFP" - "\tTV" - "\tCRT" - "\r\n" - - Title "Mode Characteristics" - EditNum $OEM_Mode_X1, " X Resolution:", DEC, - Help "X Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Y1, " Y Resolution:", DEC, - Help "Y Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Color1, " Color Depth:", BIN, - Help "Color Depth, bits can be set simultaneously (binary)." - "\r\n\r\n" - "\tBit 7" - "\tBit 6" - "\tBit 5" - "\tBit 4" - "\tBit 3" - "\tBit 2" - "\tBit 1" - "\tBit 0" - "\r\n" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\t32 BPP" - "\t16 BPP" - "\t8 BPP" - "\r\n" - - EditNum $OEM_Mode_RRate1, " Refresh Rate:", DEC, - Help "Refresh rate for OEM customizable mode (decimal)." - Link "18 Bytes DTD" , "DTD" - - Page "DTD" - - Link "Close Table" , ".." - - Table $OEM_Mode_DTD1 " Detailed Timings Descriptor", - Column "Timings" , 1 byte , EHEX, - Help "This table is the 18-byte DTD(Detailed Timings" - " Descriptor) structure defined in the VESA" - " EDID version 1.x.\r\n" - "\r\n" - "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" - "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tDB ?\t; Vertical Active in lines, LSB\r\n" - "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Horizontal Image Size, LSB\r\n" - "\tDB ?\t; Vertical Image Size, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tDB 0\t; Horizontal Border in pixels\r\n" - "\tDB 0\t; Vertical Border in lines\r\n" - "\tDB ?\t; Flags:\r\n" - "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t; Bit 6-5: 00 = Reserved\r\n" - "\t \t; Bit 4-3: 11 = Digital Separate\r\n" - "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 0: 0 = Reserved" - EndPage - EndPage - - Page "OEM Mode #2" - - Link "Close Table" , ".." - - Title " 8 bpp = VGA mode 63h / VESA mode 163h" - Title " 16 bpp = VGA mode 64h / VESA mode 164h" - Title " 32 bpp = VGA mode 65h / VESA mode 165h" - - EditNum $OEM_Mode_Flags2, "Support Flags:", BIN, - Help "Support flags:" - "(0 = Disabled, 1 = Enabled)" - "\r\n\r\n" - "\tBit 7" - "\tBit 6" - "\tBit 5" - "\tBit 4" - "\tBit 3" - "\tBit 2" - "\tBit 1" - "\tBit 0" - "\r\n" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\tDriver" - "\tVBIOS" - "\r\n" - - EditNum $OEM_Display_Flags2, "Display Flags:", BIN, - Help "Display Flags:" - "(0 = Disabled, 1 = Enabled)" - "\r\n\r\n" - "\tBit 7" - "\tBit 6" - "\tBit 5" - "\tBit 4" - "\tBit 3" - "\tBit 2" - "\tBit 1" - "\tBit 0" - "\r\n" - "\tLFP2" - "\tEFP2" - "\tTV2" - "\tCRT2" - "\tLFP" - "\tEFP" - "\tTV" - "\tCRT" - "\r\n" - - Title "Mode Characteristics" - - EditNum $OEM_Mode_X2, " X Resolution:", DEC, - Help "X Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Y2, " Y Resolution:", DEC, - Help "Y Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Color2, " Color Depth:", BIN, - Help "Color Depth, bits can be set simultaneously (binary)." - "\r\n\r\n" - "\tBit 7" - "\tBit 6" - "\tBit 5" - "\tBit 4" - "\tBit 3" - "\tBit 2" - "\tBit 1" - "\tBit 0" - "\r\n" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\t32 BPP" - "\t16 BPP" - "\t8 BPP" - "\r\n" - - EditNum $OEM_Mode_RRate2, " Refresh Rate:", DEC, - Help "Refresh rate for OEM customizable mode (decimal)." - - Link "18 Bytes DTD" , "DTD" - - Page "DTD" - - Link "Close Table" , ".." - - Table $OEM_Mode_DTD2 " Detailed Timings Descriptor", - Column "Timings" , 1 byte , EHEX, - Help "This table is the 18-byte DTD(Detailed Timings" - " Descriptor) structure defined in the VESA" - " EDID version 1.x.\r\n" - "\r\n" - "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" - "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tDB ?\t; Vertical Active in lines, LSB\r\n" - "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Horizontal Image Size, LSB\r\n" - "\tDB ?\t; Vertical Image Size, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tDB 0\t; Horizontal Border in pixels\r\n" - "\tDB 0\t; Vertical Border in lines\r\n" - "\tDB ?\t; Flags:\r\n" - "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t; Bit 6-5: 00 = Reserved\r\n" - "\t \t; Bit 4-3: 11 = Digital Separate\r\n" - "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 0: 0 = Reserved" - EndPage - EndPage - - Page "OEM Mode #3" - - Link "Close Table" , ".." - - Title " 8 bpp = VGA mode 66h / VESA mode 166h" - Title " 16 bpp = VGA mode 67h / VESA mode 167h" - Title " 32 bpp = VGA mode 68h / VESA mode 168h" - - EditNum $OEM_Mode_Flags3, "Support Flags:", BIN, - Help "Support flags:" - "(0 = Disabled, 1 = Enabled)" - "\r\n\r\n" - "\tBit 7" - "\tBit 6" - "\tBit 5" - "\tBit 4" - "\tBit 3" - "\tBit 2" - "\tBit 1" - "\tBit 0" - "\r\n" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\tDriver" - "\tVBIOS" - "\r\n" - - EditNum $OEM_Display_Flags3, "Display Flags:", BIN, - Help "Display Flags:" - "(0 = Disabled, 1 = Enabled)" - "\r\n\r\n" - "\tBit 7" - "\tBit 6" - "\tBit 5" - "\tBit 4" - "\tBit 3" - "\tBit 2" - "\tBit 1" - "\tBit 0" - "\r\n" - "\tLFP2" - "\tEFP2" - "\tTV2" - "\tCRT2" - "\tLFP" - "\tEFP" - "\tTV" - "\tCRT" - "\r\n" - - Title "Mode Characteristics" - - EditNum $OEM_Mode_X3, " X Resolution:", DEC, - Help "X Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Y3, " Y Resolution:", DEC, - Help "Y Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Color3, " Color Depth:", BIN, - Help "Color Depth, bits can be set simultaneously (binary)." - "\r\n\r\n" - "\tBit 7" - "\tBit 6" - "\tBit 5" - "\tBit 4" - "\tBit 3" - "\tBit 2" - "\tBit 1" - "\tBit 0" - "\r\n" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\t32 BPP" - "\t16 BPP" - "\t8 BPP" - "\r\n" - - EditNum $OEM_Mode_RRate3, " Refresh Rate:", DEC, - Help "Refresh rate for OEM customizable mode (decimal)." - - Link "18 Bytes DTD" , "DTD" - - Page "DTD" - - Link "Close Table" , ".." - - Table $OEM_Mode_DTD3 " Detailed Timings Descriptor", - Column "Timings" , 1 byte , EHEX, - Help "This table is the 18-byte DTD(Detailed Timings" - " Descriptor) structure defined in the VESA" - " EDID version 1.x.\r\n" - "\r\n" - "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" - "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tDB ?\t; Vertical Active in lines, LSB\r\n" - "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Horizontal Image Size, LSB\r\n" - "\tDB ?\t; Vertical Image Size, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tDB 0\t; Horizontal Border in pixels\r\n" - "\tDB 0\t; Vertical Border in lines\r\n" - "\tDB ?\t; Flags:\r\n" - "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t; Bit 6-5: 00 = Reserved\r\n" - "\t \t; Bit 4-3: 11 = Digital Separate\r\n" - "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 0: 0 = Reserved" - EndPage - EndPage - - Page "OEM Mode #4" - - Link "Close Table" , ".." - - Title " 8 bpp = VGA mode 69h / VESA mode 169h" - Title " 16 bpp = VGA mode 6Ah / VESA mode 16Ah" - Title " 32 bpp = VGA mode 6Bh / VESA mode 16Bh" - - EditNum $OEM_Mode_Flags4, "Support Flags:", BIN, - Help "Support flags:" - "(0 = Disabled, 1 = Enabled)" - "\r\n\r\n" - "\tBit 7" - "\tBit 6" - "\tBit 5" - "\tBit 4" - "\tBit 3" - "\tBit 2" - "\tBit 1" - "\tBit 0" - "\r\n" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\tDriver" - "\tVBIOS" - "\r\n" - - EditNum $OEM_Display_Flags4, "Display Flags:", BIN, - Help "Display Flags:" - "(0 = Disabled, 1 = Enabled)" - "\r\n\r\n" - "\tBit 7" - "\tBit 6" - "\tBit 5" - "\tBit 4" - "\tBit 3" - "\tBit 2" - "\tBit 1" - "\tBit 0" - "\r\n" - "\tLFP2" - "\tEFP2" - "\tTV2" - "\tCRT2" - "\tLFP" - "\tEFP" - "\tTV" - "\tCRT" - "\r\n" - - Title "Mode Characteristics" - - EditNum $OEM_Mode_X4, " X Resolution:", DEC, - Help "X Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Y4, " Y Resolution:", DEC, - Help "Y Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Color4, " Color Depth:", BIN, - Help "Color Depth, bits can be set simultaneously (binary)." - "\r\n\r\n" - "\tBit 7" - "\tBit 6" - "\tBit 5" - "\tBit 4" - "\tBit 3" - "\tBit 2" - "\tBit 1" - "\tBit 0" - "\r\n" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\t32 BPP" - "\t16 BPP" - "\t8 BPP" - "\r\n" - - EditNum $OEM_Mode_RRate4, " Refresh Rate:", DEC, - Help "Refresh rate for OEM customizable mode (decimal)." - - Link "18 Bytes DTD" , "DTD" - - Page "DTD" - - Link "Close Table" , ".." - - Table $OEM_Mode_DTD4 " Detailed Timings Descriptor", - Column "Timings" , 1 byte , EHEX, - Help "This table is the 18-byte DTD(Detailed Timings" - " Descriptor) structure defined in the VESA" - " EDID version 1.x.\r\n" - "\r\n" - "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" - "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tDB ?\t; Vertical Active in lines, LSB\r\n" - "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Horizontal Image Size, LSB\r\n" - "\tDB ?\t; Vertical Image Size, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tDB 0\t; Horizontal Border in pixels\r\n" - "\tDB 0\t; Vertical Border in lines\r\n" - "\tDB ?\t; Flags:\r\n" - "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t; Bit 6-5: 00 = Reserved\r\n" - "\t \t; Bit 4-3: 11 = Digital Separate\r\n" - "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 0: 0 = Reserved" - EndPage - EndPage - - Page "OEM Mode #5" - - Link "Close Table" , ".." - - Title " 8 bpp = VGA mode 6Ch / VESA mode 16Ch" - Title " 16 bpp = VGA mode 6Dh / VESA mode 16Dh" - Title " 32 bpp = VGA mode 6Eh / VESA mode 16Eh" - - EditNum $OEM_Mode_Flags5, "Support Flags:", BIN, - Help "Support flags:" - "(0 = Disabled, 1 = Enabled)" - "\r\n\r\n" - "\tBit 7" - "\tBit 6" - "\tBit 5" - "\tBit 4" - "\tBit 3" - "\tBit 2" - "\tBit 1" - "\tBit 0" - "\r\n" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\tDriver" - "\tVBIOS" - "\r\n" - - EditNum $OEM_Display_Flags5, "Display Flags:", BIN, - Help "Display Flags:" - "(0 = Disabled, 1 = Enabled)" - "\r\n\r\n" - "\tBit 7" - "\tBit 6" - "\tBit 5" - "\tBit 4" - "\tBit 3" - "\tBit 2" - "\tBit 1" - "\tBit 0" - "\r\n" - "\tLFP2" - "\tEFP2" - "\tTV2" - "\tCRT2" - "\tLFP" - "\tEFP" - "\tTV" - "\tCRT" - "\r\n" - - Title "Mode Characteristics" - - EditNum $OEM_Mode_X5, " X Resolution:", DEC, - Help "X Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Y5, " Y Resolution:", DEC, - Help "Y Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Color5, " Color Depth:", BIN, - Help "Color Depth, bits can be set simultaneously (binary)." - "\r\n\r\n" - "\tBit 7" - "\tBit 6" - "\tBit 5" - "\tBit 4" - "\tBit 3" - "\tBit 2" - "\tBit 1" - "\tBit 0" - "\r\n" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\t32 BPP" - "\t16 BPP" - "\t8 BPP" - "\r\n" - - EditNum $OEM_Mode_RRate5, " Refresh Rate:", DEC, - Help "Refresh rate for OEM customizable mode (decimal)." - - Link "18 Bytes DTD" , "DTD" - - Page "DTD" - - Link "Close Table" , ".." - - Table $OEM_Mode_DTD5 " Detailed Timings Descriptor", - Column "Timings" , 1 byte , EHEX, - Help "This table is the 18-byte DTD(Detailed Timings" - " Descriptor) structure defined in the VESA" - " EDID version 1.x.\r\n" - "\r\n" - "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" - "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tDB ?\t; Vertical Active in lines, LSB\r\n" - "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Horizontal Image Size, LSB\r\n" - "\tDB ?\t; Vertical Image Size, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tDB 0\t; Horizontal Border in pixels\r\n" - "\tDB 0\t; Vertical Border in lines\r\n" - "\tDB ?\t; Flags:\r\n" - "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t; Bit 6-5: 00 = Reserved\r\n" - "\t \t; Bit 4-3: 11 = Digital Separate\r\n" - "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 0: 0 = Reserved" - EndPage - EndPage - - Page "OEM Mode #6" - - Link "Close Table" , ".." - - Title " 8 bpp = VGA mode 6Fh / VESA mode 16Fh" - Title " 16 bpp = VGA mode 70h / VESA mode 170h" - Title " 32 bpp = VGA mode 71h / VESA mode 171h" - - EditNum $OEM_Mode_Flags6, "Support Flags:", BIN, - Help "Support flags:" - "(0 = Disabled, 1 = Enabled)" - "\r\n\r\n" - "\tBit 7" - "\tBit 6" - "\tBit 5" - "\tBit 4" - "\tBit 3" - "\tBit 2" - "\tBit 1" - "\tBit 0" - "\r\n" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\tDriver" - "\tVBIOS" - "\r\n" - - EditNum $OEM_Display_Flags6, "Display Flags:", BIN, - Help "Display Flags:" - "(0 = Disabled, 1 = Enabled)" - "\r\n\r\n" - "\tBit 7" - "\tBit 6" - "\tBit 5" - "\tBit 4" - "\tBit 3" - "\tBit 2" - "\tBit 1" - "\tBit 0" - "\r\n" - "\tLFP2" - "\tEFP2" - "\tTV2" - "\tCRT2" - "\tLFP" - "\tEFP" - "\tTV" - "\tCRT" - "\r\n" - - Title "Mode Characteristics" - - EditNum $OEM_Mode_X6, " X Resolution:", DEC, - Help "X Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Y6, " Y Resolution:", DEC, - Help "Y Resolution in pixels (decimal)." - - EditNum $OEM_Mode_Color6, " Color Depth:", BIN, - Help "Color Depth, bits can be set simultaneously (binary)." - "\r\n\r\n" - "\tBit 7" - "\tBit 6" - "\tBit 5" - "\tBit 4" - "\tBit 3" - "\tBit 2" - "\tBit 1" - "\tBit 0" - "\r\n" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\tRsvd" - "\t32 BPP" - "\t16 BPP" - "\t8 BPP" - "\r\n" - - EditNum $OEM_Mode_RRate6, " Refresh Rate:", DEC, - Help "Refresh rate for OEM customizable mode (decimal)." - - Link "18 Bytes DTD" , "DTD" - - Page "DTD" - - Link "Close Table" , ".." - - Table $OEM_Mode_DTD6 " Detailed Timings Descriptor", - Column "Timings" , 1 byte , EHEX, - Help "This table is the 18-byte DTD(Detailed Timings" - " Descriptor) structure defined in the VESA" - " EDID version 1.x.\r\n" - "\r\n" - "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" - "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" - "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" - "\tDB ?\t; Vertical Active in lines, LSB\r\n" - "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" - "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" - "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" - "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" - "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" - "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" - "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" - "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" - "\tDB ?\t; Horizontal Image Size, LSB\r\n" - "\tDB ?\t; Vertical Image Size, LSB\r\n" - "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" - "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" - "\tDB 0\t; Horizontal Border in pixels\r\n" - "\tDB 0\t; Vertical Border in lines\r\n" - "\tDB ?\t; Flags:\r\n" - "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" - "\t \t; Bit 6-5: 00 = Reserved\r\n" - "\t \t; Bit 4-3: 11 = Digital Separate\r\n" - "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" - "\t \t; Bit 0: 0 = Reserved" - EndPage - EndPage -EndPage - - -;============================================================================ -; End of File -;------------------------------------------------------------------------------ - +; TITLE BMP.bsf - BMP Scrip File for Video BIOS +;============================================================================== +; Advance Graphics ROM BIOS +;------------------------------------------------------------------------------ +; Copyright (c) Intel Corporation (2000 - 2011). +; +; INTEL MAKES NO WARRANTY OF ANY KIND REGARDING THE CODE. THIS CODE IS +; LICENSED ON AN "AS IS" BASIS AND INTEL WILL NOT PROVIDE ANY SUPPORT, +; ASSISTANCE, INSTALLATION, TRAINING OR OTHER SERVICES. +; INTEL DOES NOT PROVIDE ANY UPDATES, ENHANCEMENTS OR EXTENSIONS. +; INTEL SPECIFICALLY DISCLAIMS ANY WARRANTY OF MERCHANTABILITY, +; NONINFRINGEMENT, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY OTHER +; WARRANTY. +; +; Intel disclaims all liability, including liability for infringement of +; any proprietary rights, relating to use of the code. No license, express +; or implied, by estoppel or otherwise, to any intellectual property rights +; is granted herein. +; +; File Description: +; This file is the script file use by the BMP utility which will allow +; OEM's to edit data and select features on a binary file. +; +;------------------------------------------------------------------------------ + + +;============================================================================== +; Header - Start of BMP Structure Definition +;------------------------------------------------------------------------------ + +StructDef + +Find "BIOS_DATA_BLOCK " + + ; The following block will determine the reference + ; pointer for all table pointer variables. + +Find_Ptr_Ref "BIOS_DATA_BLOCK" ; Reference to beginning of VB VBT data + +$BDB_Ver 2 bytes ; BIOS Data Block version number (decimal, e.g.201 = 02.01) +$BDB_Header_Size 2 bytes ; BIOS Data Block Header size +$BDB_Size 2 bytes ; BIOS Data Block size + +;============================================================================== +; Block 254 - Signon Strings and Other General Data +;------------------------------------------------------------------------------ + +SKIP 3 bytes ; Skip block ID and size + +$Bmp_BIOS_Size 2 bytes +$BIOS_Type 1 byte ; BIOS Type: + ; = 0, DESKTOP + ; = 1, MOBILE + +$RelStage 1 byte ; Release status + +$Chipset 1 byte ; = 17 - SandyBridge-Desktop + ; = 18 - Sandybridge-Mobile + ; = 19 - Ivybridge-Desktop + ; = 20 - Ivybridge-Mobile + ; = 21 - Haswell-Desktop + ; = 22 - Haswell-Mobile + + ; = 24 - VaalleyView + +$Integrated_LVDS 1 bit ; Integrated LVDS Support: + ; 1 = Yes + ; 0 = None + +$Integrated_TV 1 bit ; Integrated TV Support: + ; 1 = Yes + ; 0 = None + +$Integrated_EFP 1 bit ; Integrated EFP Support: + ; 1 = Yes + ; 0 = None + +$eDP 1 bit ; eDP: + ; 1 = Yes + ; 0 = None + +SKIP 4 bits +SKIP 4 bytes ; Skip build number string + + ; Signon and copyright strings + +$Signon 155 bytes ; Signon string +$Copyright 61 bytes ; Copyright string + + ; General Byte Definitions + +$bmp_BIOS_CS 2 bytes ; BIOS code segment +$bmp_VBIOS_Post_Mode 1 byte ; Mode number to set during V BIOS POST +$bmp_BW_Percent 1 byte ; Set percentage of total memory BW +SKIP 1 byte ; Popup Memory Size +$bmp_Resize_PCI_BIOS 1 byte ; BIOS size granularity in 0.5 KB +SKIP 1 byte ; Is the CRT already switched to DDC2 + +$Allow_Boot_DVI 1 bit ; Allow boot DVI even not attach +$Allow_Aspect_Ratio 1 bit ; VBIOS aspect ratio for DOS +SKIP 6 bits + +ALIGN + +;============================================================================== +; Block 1 - General Bit Definitions +;------------------------------------------------------------------------------ + +SKIP 3 bytes ; Skip block ID and size + + ; + ; bmp_Bits_1 + ; + +$Enable_Panel_Fitting 2 bits ; Enable / Disable panel fitting +$Flexaim_Support 1 bit ; Enable / Disable Flex-aim support +$Msg_Enable 1 bit ; Disable signon and copyright +$Cls_After_Signon 3 bits ; Clear screen after display message and pause +$bmp_DVO_A_Color_Flip 1 bit ; Flat color flip +ALIGN + + ; + ; bmp_Bits_2 + ; +$Download_Ext_VBT 1 bit ; Download external VBT flag +$Enable_SSC 1 bit ; Enable/Disable SSC +$SSC_Freq 1 bit ; SSC Frequency +$Enable_LFPOn_Override 1 bit ; Enable/Disable LFP ON Override +$Disable_SSC_DDT 1 bit ; Disable SSC in Dual Display Twin +$Override_VGA_720p 1 bit ; Enable/Disable Override 720p for VGA modes +$Display_Clock_Mode 1 bit ; Enables DCI mode or legacy BTM mode +$Hotplug_Support_Enb 1 bit ; Hot Plug support in DOS + +ALIGN + ; + ; bmp_Bits_3 + ; +SKIP 2 bits +$180_Deg_Rotation_Enable 1 bit ; 180 Degree Rotation Enable bit +SKIP 5 bits +ALIGN + +$bmp_Legacy_Monitor_Detect 1 bit ; Use legacy monitor detect algorithm +SKIP 7 bits +ALIGN + + ; + ; Int_Displays_Support + ; +$Int_CRT_Support 1 bit ; Integrated CRT support +$Int_TV_Support 1 bit ; Integrated TV support +$Int_EFP_Support 1 bit ; Integrated EFP support +$DP_SSC_Enb 1 bit ; DP SSC Enable bit +$DP_SSC_Freq 1 bit ; DP SSC Frequency bit +$DP_SSC_Dongle_Enb 1 bit ; DP SSC dongle Enable/Disable +SKIP 2 bits + +ALIGN + + +;============================================================================== +; Block 253 - PRD Boot Algorithm Table +;------------------------------------------------------------------------------ + +SKIP 3 bytes ; Skip block ID and size + +SKIP 1 byte +$ChildDevice1Primary 1 byte +$ChildDevice1Secondary 1 byte +SKIP 1 byte +$ChildDevice2Primary 1 byte +$ChildDevice2Secondary 1 byte +SKIP 1 byte +$ChildDevice3Primary 1 byte +$ChildDevice3Secondary 1 byte +SKIP 1 byte +$ChildDevice4Primary 1 byte +$ChildDevice4Secondary 1 byte +SKIP 1 byte +$ChildDevice5Primary 1 byte +$ChildDevice5Secondary 1 byte +SKIP 1 byte +$ChildDevice6Primary 1 byte +$ChildDevice6Secondary 1 byte +SKIP 1 byte +$ChildDevice7Primary 1 byte +$ChildDevice7Secondary 1 byte +SKIP 1 byte +$ChildDevice8Primary 1 byte +$ChildDevice8Secondary 1 byte +SKIP 1 byte +$ChildDevice9Primary 1 byte +$ChildDevice9Secondary 1 byte +SKIP 1 byte +$ChildDevice10Primary 1 byte +$ChildDevice10Secondary 1 byte +SKIP 1 byte +$ChildDevice11Primary 1 byte +$ChildDevice11Secondary 1 byte +SKIP 1 byte +$ChildDevice12Primary 1 byte +$ChildDevice12Secondary 1 byte +SKIP 1 byte +$ChildDevice13Primary 1 byte +$ChildDevice13Secondary 1 byte +SKIP 1 byte +$ChildDevice14Primary 1 byte +$ChildDevice14Secondary 1 byte +SKIP 1 byte +$ChildDevice15Primary 1 byte +$ChildDevice15Secondary 1 byte +SKIP 1 byte +$ChildDevice16Primary 1 byte +$ChildDevice16Secondary 1 byte + +SKIP 2 bytes ; No of entries + +;============================================================================== +; Block 2 - General Data Definitions +;------------------------------------------------------------------------------ + +SKIP 3 bytes ; Skip block ID and size + +$CRT_DDC_GMBUS_Pin 1 byte ; CRT DDC GMBUS pin pair + +$DPMS_ACPI_Bit 1 bit ; Apply ACPI DPMS CRT Power States +$Skip_Boot_CRT_Detect 1 bit ; Disable/Enable skip boot CRT detect +$DPMS_AIM_Bit 1 bit ; Apply DPMS to AIM devices +SKIP 5 bits +ALIGN + + +$Boot_Display 2 bytes ; Boot display type +$size_ChildStruc 1 byte + + +$Int_LFP1_DID 2 bytes ; Skip Device Handle +$Int_LFP1_Type 2 bytes ; Device type +SKIP 7 bytes ; Skip +SKIP 1 byte ; Skip +$Int_LFP1_Priority 1 byte ; primary/secondary panel select +ALIGN +SKIP 3 bytes ; Skip +$Int_LFP1_Port 1 byte ; eDP port select +SKIP 2 bytes ; Skip remaining Data structure +$Int_LFP1_DDC_Pin 1 byte ; LFP DDC GMBUS pin pair +SKIP 5 bytes +$Int_LFP1_AUX_Channel 1 byte ; DP AUX channel +SKIP 7 bytes +SKIP 4 bytes + + + + +$Int_EFP1_DID 2 bytes ; Skip Device Handle +$Int_EFP1_Type 2 bytes ; Device type +SKIP 1 byte ; Skip I2C Speed +$EFP1_OnBoard_PreEmph_Level 3 bits ; EFP1 On Board Dp Redriver PreEmphasis Level +$EFP1_OnBoard_VSwing_Level 3 bits ; EFP1 On Board Dp Redriver VSwing Level +$EFP1_OnBoard_Redriver_Present 1 bit ; Is OnBoard Redriver Present for EFP1 +SKIP 1 bit ; Reserved +$EFP1_OnDock_PreEmph_Level 3 bits ; EFP1 On Dock Dp Redriver PreEmphasis Level +$EFP1_OnDock_VSwing_Level 3 bits ; EFP1 On Dock Dp Redriver VSwing Level +$EFP1_OnDock_Redriver_Present 1 bit ; Is On Dock Redriver Present for EFP1 +SKIP 1 bit ; Reserved +$Int_EFP1_HDMI_LS_Type 5 bits ; HDMI Level shifter configuration +SKIP 3 bits ; Reserved +ALIGN +SKIP 2 bytes ; Skip EDIDless DTD offset +$EFP1_EDIDless_en 1 bit ; EDIDless enable bit +SKIP 7 bits ; Skip remaining bits +SKIP 3 bytes ; Skip Reserved_1 +SKIP 2 bytes ; skip Addin module table offset +$Int_EFP1_Port 1 byte ; EFP1 port +SKIP 2 bytes ; Skip +$Int_EFP1_DDC_Pin 1 byte ; EFP1 DDC Pin +SKIP 3 bytes +$Int_EFP1_Docked_Port 1 bit ; HDMI/DP Docked Port +SKIP 1 bit ; Skip Enabling Lane Reversal Bit +SKIP 6 bits ; Reserved +$Int_EFP1_HDMI_Compat 1 bit ; HDMI combatibility +$Int_EFP1_Conn_Info 3 bits ; Connector information +SKIP 4 bits +$Int_EFP1_AUX_Channel 1 byte ; DP AUX channel +$Int_EFP1_Dongle_Detect 1 byte ; Dongle Detect +SKIP 6 bytes ; Skip +$EFP1_USB_C_DongleFeature_Enabled 1 bit ;USB C dongle feature enabled +SKIP 7 bits +$EFP1_GPIO_Index 1 byte ;GPIO resource ID used by drivers +$EFP1_GPIO_Number 2 bytes ;GPIO number + + +$Int_EFP2_DID 2 bytes ; Skip Device Handle +$Int_EFP2_Type 2 bytes ; Device type +SKIP 1 byte ; Skip I2C Speed +$EFP2_OnBoard_PreEmph_Level 3 bits ; EFP2 On Board Dp Redriver PreEmphasis Level +$EFP2_OnBoard_VSwing_Level 3 bits ; EFP2 On Board Dp Redriver VSwing Level +$EFP2_OnBoard_Redriver_Present 1 bit ; Is OnBoard Redriver Present for EFP2 +SKIP 1 bit ; Reserved +$EFP2_OnDock_PreEmph_Level 3 bits ; EFP2 On Dock Dp Redriver PreEmphasis Level +$EFP2_OnDock_VSwing_Level 3 bits ; EFP2 On Dock Dp Redriver VSwing Level +$EFP2_OnDock_Redriver_Present 1 bit ; Is On Dock Redriver Present for EFP2 +SKIP 1 bit ; Reserved +$Int_EFP2_HDMI_LS_Type 5 bits ; HDMI Level shifter configuration +SKIP 3 bits ; Reserved +ALIGN +SKIP 2 bytes ; Skip EDIDless DTD offset +$EFP2_EDIDless_en 1 bit ; EDIDless enable bit +SKIP 7 bits ; Skip remaining bits +SKIP 3 bytes ; Skip Reserved_1 +SKIP 2 bytes ; skip Addin module table offset +$Int_EFP2_Port 1 byte ; EFP1 port +SKIP 2 bytes ; Skip +$Int_EFP2_DDC_Pin 1 byte ; EFP1 DDC Pin +SKIP 3 bytes +$Int_EFP2_Docked_Port 1 bit ; HDMI/DP Docked Port +SKIP 1 bit ; Skip Enabling Lane Reversal Bit +SKIP 6 bits ; Reserved +$Int_EFP2_HDMI_Compat 1 bit ; HDMI combatibility +$Int_EFP2_Conn_Info 3 bits ; Connector information +SKIP 4 bits +$Int_EFP2_AUX_Channel 1 byte ; DP AUX channel +$Int_EFP2_Dongle_Detect 1 byte ; Dongle Detect +SKIP 6 bytes ; Skip +$EFP2_USB_C_DongleFeature_Enabled 1 bit ;USB C dongle feature enabled +SKIP 7 bits +$EFP2_GPIO_Index 1 byte ;GPIO resource ID used by drivers +$EFP2_GPIO_Number 2 bytes ;GPIO number + + +$Int_EFP3_DID 2 bytes ; Skip Device Handle +$Int_EFP3_Type 2 bytes ; Device type +SKIP 1 byte ; Skip I2C Speed +$EFP3_OnBoard_PreEmph_Level 3 bits ; EFP3 On Board Dp Redriver PreEmphasis Level +$EFP3_OnBoard_VSwing_Level 3 bits ; EFP3 On Board Dp Redriver VSwing Level +$EFP3_OnBoard_Redriver_Present 1 bit ; Is OnBoard Redriver Present for EFP2 +SKIP 1 bit ; Reserved +$EFP3_OnDock_PreEmph_Level 3 bits ; EFP3 On Dock Dp Redriver PreEmphasis Level +$EFP3_OnDock_VSwing_Level 3 bits ; EFP3 On Dock Dp Redriver VSwing Level +$EFP3_OnDock_Redriver_Present 1 bit ; Is On Dock Redriver Present for EFP3 +SKIP 1 bit ; Reserved +$Int_EFP3_HDMI_LS_Type 5 bits ; HDMI Level shifter configuration +SKIP 3 bits ; Reserved +ALIGN +SKIP 2 bytes ; Skip EDIDless DTD offset +$EFP3_EDIDless_en 1 bit ; EDIDless enable bit +SKIP 7 bits ; Skip remaining bits +SKIP 3 bytes ; Skip Reserved_1 +SKIP 2 bytes ; skip Addin module table offset +$Int_EFP3_Port 1 byte ; EFP3 port +SKIP 2 bytes ; Skip +$Int_EFP3_DDC_Pin 1 byte ; EFP3 DDC Pin +SKIP 3 bytes +$Int_EFP3_Docked_Port 1 bit ; HDMI/DP Docked Port +SKIP 1 bit ; Skip Enabling Lane Reversal Bit +SKIP 6 bits ; Reserved +$Int_EFP3_HDMI_Compat 1 bit ; HDMI combatibility +$Int_EFP3_Conn_Info 3 bits ; Connector information +SKIP 4 bits +$Int_EFP3_AUX_Channel 1 byte ; DP AUX channel +$Int_EFP3_Dongle_Detect 1 byte ; Dongle Detect +SKIP 6 bytes ; Skip +$EFP3_USB_C_DongleFeature_Enabled 1 bit ;USB C dongle feature enabled +SKIP 7 bits +$EFP3_GPIO_Index 1 byte ;GPIO resource ID used by drivers +$EFP3_GPIO_Number 2 bytes ;GPIO number + + + + + +;============================================================================== +; Block 3 - Original Display Toggle List +;------------------------------------------------------------------------------ + +SKIP 3 bytes ; Skip block ID and size + +$bmp_Display_Detect 1 byte ; Display must be attached or not + +;============================================================================== +; Block 4 - Mode Support Bit Definitions +;------------------------------------------------------------------------------ + +SKIP 3 bytes ; Skip block ID and size + +SKIP 28 bytes ; Mode List + +;============================================================================== +; Block 252 - Hook Defintions +;------------------------------------------------------------------------------ + +SKIP 3 bytes ; Skip block ID and size + +$H31_POST_End_Hook 1 byte ; POST end hook int vector +$H33_After_Mode_Set 1 byte ; After mode set hook +$H35_Bootup_Display 1 byte ; Bootup display hook +$H38_Before_Mode_Set 1 byte ; Before mode set hook +$H45_VESA_DDC_Hook 1 byte ; VESA DDC hook interrupt vector +$H46_VESA_PM_Hook 1 byte ; VESA PM hook interrupt vector +$H47_Notify_Display_Sw 1 byte ; Notify display switch hook +$H48_After_VESA_PM 1 byte ; After VESA PM hook +$H14_Update_Display 1 byte ; Update Expansion/Display State Hook +$H14_Get_Misc_Status 1 byte ; Get Miscellaneous Status Hook +$H36_Boot_TV_Format 1 byte ; Boot TV to NTSC/PAL +$H34_Set_LFP_Fitting 1 byte ; Set panel fitting flags +$H40_Set_Panel_Type 1 byte ; Set panel fitting flags +$H49_Get_BL_Inv_Pol 1 byte ; Get inverter type and polarity for backlight +$H51_LFP_Panel_Type 1 byte ; Get active LFP configuration from CMOS setup +$H74_SR_Enable 1 byte ; Hook to enable/ disable Self Refresh as part of WA. + + ; BMP - Pointer tables + +$Dev_Boot_Table_Ptr 2 bytes ; Start at BMP Boot table +$Dev_Boot_Table_Size 2 bytes +$Dev_Boot_Table, $Dev_Boot_Table_Ptr, $Dev_Boot_Table_Size, Offset 0 byte + +$Dev_Removed_Table_Ptr 2 bytes ; Start at BMP Remove configurations table +$Dev_Removed_Table_Size 2 bytes +$Dev_Removed_Table, $Dev_Removed_Table_Ptr, $Dev_Removed_Table_Size, Offset 0 byte + +$MMIO_Boot_Table_Ptr 2 bytes ; Start at BMP Boot table +$MMIO_Boot_Table_Size 2 bytes +$MMIO_Boot_Table, $MMIO_Boot_Table_Ptr, $MMIO_Boot_Table_Size, Offset 0 byte + +$SWF_IO_Table_Ptr 2 bytes +$SWF_IO_Table_Size 2 bytes +$SWF_IO_Table, $SWF_IO_Table_Ptr, $SWF_IO_Table_Size, Offset 3 bytes + +$SWF_MMIO_Table_Ptr 2 bytes +$SWF_MMIO_Table_Size 2 bytes +$SWF_MMIO_Table, $SWF_MMIO_Table_Ptr, $SWF_MMIO_Table_Size, Offset 3 bytes + + +$Mode_Rem_Table_Ptr 2 bytes ; Start at BMP Boot table +$Mode_Rem_Table_Size 2 bytes +$Mode_Rem_Table, $Mode_Rem_Table_Ptr, $Mode_Rem_Table_Size, Offset 0 byte + +SKIP 80 bytes + +;============================================================================== +; Block 6 - Extended MMIO Register tables +;------------------------------------------------------------------------------ + +SKIP 3 bytes ; Skip block ID and size + +SKIP 117 bytes ; Skip data + +;============================================================================== +; Block 7 - IO Software flag register table for initializaton +;------------------------------------------------------------------------------ + +SKIP 3 bytes ; Skip block ID and size + +SKIP 7 bytes ; Skip data + +;============================================================================== +; Block 8 - MMIO Software flag register table for initializaton +;------------------------------------------------------------------------------ + +SKIP 3 bytes ; Skip block ID and size + +SKIP 61 bytes ; Skip data + +;============================================================================== + +;============================================================================== +; Block 9 - PSR Feature Table +;------------------------------------------------------------------------------ + +SKIP 3 bytes ; Skip block ID and size + +SKIP 96 bytes ; PSR Table data + +;============================================================================== + + +;============================================================================== +; Block 10 - Modes Removal Table. +;------------------------------------------------------------------------------ + +SKIP 3 bytes ; Skip block ID and size + +SKIP 203 bytes ; Skip data + + +;============================================================================== +; Block 12 - Driver default boot display +;------------------------------------------------------------------------------ + +SKIP 3 bytes ; Skip block ID and size +$Driver_Boot_Device 1 bit +$Block_Disp_Switch 1 bit +$Allow_FDOS_Disp_Switch 1 bit ; Allow FS DOS display switching +$Hot_Plug_DVO 1 bit +$Dual_View_Zoom 1 bit +$Drv_Int15_hook 1 bit +$DVD_Sprite_Clone 1 bit +$Use_110h_for_LFP 1 bit +ALIGN + +$Driver_Boot_Mode_X 2 bytes ; X resolution +$Driver_Boot_Mode_Y 2 bytes ; Y resolution +$Driver_Boot_Mode_BPP 1 byte ; Pixel depth +$Driver_Boot_Mode_RR 1 byte ; Refresh rate +; bmp_Ext_Driver_Bits + +$Enable_LFP_Primary 1 bit +$GTF_Mode_Pruning 1 bit +SKIP 1 bit ; DISABLE_DFGT +SKIP 1 bit ; DISABLE_DFGT +$NT4_Dual_Dsp_Clone_Spt 1 bit ; Dual display clone support for NT4 +$Default_Power_Scheme 1 bit +$Sprite_Display_Assign 1 bit ; Sprite Display Assignment for when Overlay is Active in Clone Mode +$CUI_Maintain_Aspect 1 bit ; Display "Maintain Aspect Ratio" via CUI +$Preserve_Aspect_Ratio 1 bit ; Preserve Aspect Ratio +$SDVO_Device_Power_Down 1 bit ; SDVO device power down +$Hot_Plug_CRT 1 bit ; CRT hot plug +$LVDS_Config 2 bits ; LVDS configuration +$Hot_Plug_TV 1 bit ; Hot plug TV enable/disable +$INT_HDMI_Config 2 bits ; Integrated HDMI Configuration +ALIGN + + ; bmp_Driver_Flags_1 + +$CUIHotK_Static_Display 1 bit +SKIP 7 bits +$Legacy_Monitor_Max_X 2 bytes +$Legacy_Monitor_Max_Y 2 bytes +$Legacy_Monitor_Max_RR 1 bytes +ALIGN + +; bmp_Ext2_Driver_Bits + +$Enable_Int_Src_Term 1 bit ; Enable Internal Source Termination for HDMI +SKIP 7 bits +ALIGN + +$VBT_Customization_Version 1 byte ; Customization VBT version number +ALIGN + + ; bmp_Driver_Feature_Flags + +SKIP 5 bits +$PM_DRRS_Enable 1 bit ; Intel ® Display Refresh Rate Switching (DRRS) Enable/Disable Flag. +SKIP 3 bits +$Panel_Self_Refresh 1 bit ; Panel Self refresh feature (PSR) +SKIP 2 bits +$DMRRS 1 bit ; Dynamic Media Refresh Rate Enable/Disable +SKIP 3 bits + +;============================================================================== +; Block 13 - Driver Persistence Algorithm +;------------------------------------------------------------------------------ + +SKIP 3 bytes ; Skip block ID and size + +$Driver_Persist_Hotkey 1 bit +$Driver_Persist_Lid_Switch 1 bit +$Driver_Persist_PM 1 bit +$PersistHotkeyRestoreCloneMDS 1 bit +$PersistHotkeyRestoreRefreshrate 1 bit +$PersistHotkeyRestorePipe 1 bit +$PersistHotkeyRestoreMode 1 bit +$PersistEDIDRestoreMode 1 bit +$PersistHotPlugRestoreMode 1 bit +$Driver_Persist_Docking 1 bit +SKIP 6 bits +ALIGN +$PersistMaxConfig 1 byte + +;============================================================================== +; Block 16 - VBIOS/Driver Toggle list, capabilities tables +;------------------------------------------------------------------------------ + +SKIP 3 bytes ; Skip block ID and size +SKIP 132 bytes ; Skip Toggle lists +ALIGN + + +;============================================================================== +; Block 17 - Test Feature +;------------------------------------------------------------------------------ + +SKIP 3 bytes ; Skip block ID and size + +$SV_Dis_Arbiter 1 bit ; Disable VGA fast arbiter +$SV_Setmode_No_DVO 1 bit ; Do Setmode without reprogramming DVO +$SV_Special_GMBus 1 bit ; Special GMBus support +$SV_Wait_Timeout_Hang 1 bit +SKIP 4 bits +ALIGN +SKIP 7 bytes ; Skip reserved space + + +;============================================================================== +; Block 18 - Driver Rotation Configuration +;------------------------------------------------------------------------------ + +SKIP 3 bytes ; Skip block ID and size +$Rotation_Support_Enable 1 bit ; Driver Rotation Feature Support bit +SKIP 7 bits +$Rot_Flags 1 byte +SKIP 10 bytes + + +;============================================================================== +; Block 19 - Removed Display Configurations +;------------------------------------------------------------------------------ + +SKIP 3 bytes ; Skip block ID and size +SKIP 2 bytes ; Table Row/Size Data +SKIP 30 bytes ; Skip Removed displays table + + +;============================================================================== +; Block 20 - OEM Customizable Modes +;------------------------------------------------------------------------------ + +SKIP 3 bytes ; Skip ID +SKIP 2 bytes ; Table Row/Size Data + +$OEM_Mode_Flags1 1 byte +$OEM_Display_Flags1 1 byte +$OEM_Mode_X1 2 bytes +$OEM_Mode_Y1 2 bytes +$OEM_Mode_Color1 1 byte +$OEM_Mode_RRate1 1 byte +$OEM_Mode_DTD1 18 bytes + +$OEM_Mode_Flags2 1 byte +$OEM_Display_Flags2 1 byte +$OEM_Mode_X2 2 bytes +$OEM_Mode_Y2 2 bytes +$OEM_Mode_Color2 1 byte +$OEM_Mode_RRate2 1 byte +$OEM_Mode_DTD2 18 bytes + +$OEM_Mode_Flags3 1 byte +$OEM_Display_Flags3 1 byte +$OEM_Mode_X3 2 bytes +$OEM_Mode_Y3 2 bytes +$OEM_Mode_Color3 1 byte +$OEM_Mode_RRate3 1 byte +$OEM_Mode_DTD3 18 bytes + +$OEM_Mode_Flags4 1 byte +$OEM_Display_Flags4 1 byte +$OEM_Mode_X4 2 bytes +$OEM_Mode_Y4 2 bytes +$OEM_Mode_Color4 1 byte +$OEM_Mode_RRate4 1 byte +$OEM_Mode_DTD4 18 bytes + +$OEM_Mode_Flags5 1 byte +$OEM_Display_Flags5 1 byte +$OEM_Mode_X5 2 bytes +$OEM_Mode_Y5 2 bytes +$OEM_Mode_Color5 1 byte +$OEM_Mode_RRate5 1 byte +$OEM_Mode_DTD5 18 bytes + +$OEM_Mode_Flags6 1 byte +$OEM_Display_Flags6 1 byte +$OEM_Mode_X6 2 bytes +$OEM_Mode_Y6 2 bytes +$OEM_Mode_Color6 1 byte +$OEM_Mode_RRate6 1 byte +$OEM_Mode_DTD6 18 bytes + +;============================================================================== +; Block 26 - TV Options +;------------------------------------------------------------------------------ + +SKIP 3 bytes ; Skip ID and size +$Under_Over_Scan_Via_YPrPb 2 bits ; Underscan/overscan for HDTV via YPrPb +SKIP 10 bits +$Under_Over_Scan_Via_DVI 2 bits ; Underscan/overscan for HDTV via DVI +$Add_Overscan_Mode 1 bit ; Add modes to avoid overscan issue +$D_Connector 1 bit ; D-Connector Support +ALIGN + +;============================================================================== +; Block #27 - eDP Power Sequencing +;------------------------------------------------------------------------------ +SKIP 3 bytes ; Skip block ID and size + + ; Panel#1 Power Sequencing +$eDP_Vcc_To_Hpd_Delay_01 2 bytes +$eDP_DataOn_To_BkltEnable_Delay_01 2 bytes +$eDP_BkltDisable_To_DataOff_Delay_01 2 bytes +$eDP_DataOff_To_PowerOff_Delay_01 2 bytes +$eDP_PowerCycle_Delay_01 2 bytes + + ; Panel#2 Power Sequencing +$eDP_Vcc_To_Hpd_Delay_02 2 bytes +$eDP_DataOn_To_BkltEnable_Delay_02 2 bytes +$eDP_BkltDisable_To_DataOff_Delay_02 2 bytes +$eDP_DataOff_To_PowerOff_Delay_02 2 bytes +$eDP_PowerCycle_Delay_02 2 bytes + + ; Panel#3 Power Sequencing +$eDP_Vcc_To_Hpd_Delay_03 2 bytes +$eDP_DataOn_To_BkltEnable_Delay_03 2 bytes +$eDP_BkltDisable_To_DataOff_Delay_03 2 bytes +$eDP_DataOff_To_PowerOff_Delay_03 2 bytes +$eDP_PowerCycle_Delay_03 2 bytes + + ; Panel#4 Power Sequencing +$eDP_Vcc_To_Hpd_Delay_04 2 bytes +$eDP_DataOn_To_BkltEnable_Delay_04 2 bytes +$eDP_BkltDisable_To_DataOff_Delay_04 2 bytes +$eDP_DataOff_To_PowerOff_Delay_04 2 bytes +$eDP_PowerCycle_Delay_04 2 bytes + + ; Panel#5 Power Sequencing +$eDP_Vcc_To_Hpd_Delay_05 2 bytes +$eDP_DataOn_To_BkltEnable_Delay_05 2 bytes +$eDP_BkltDisable_To_DataOff_Delay_05 2 bytes +$eDP_DataOff_To_PowerOff_Delay_05 2 bytes +$eDP_PowerCycle_Delay_05 2 bytes + + ; Panel#6 Power Sequencing +$eDP_Vcc_To_Hpd_Delay_06 2 bytes +$eDP_DataOn_To_BkltEnable_Delay_06 2 bytes +$eDP_BkltDisable_To_DataOff_Delay_06 2 bytes +$eDP_DataOff_To_PowerOff_Delay_06 2 bytes +$eDP_PowerCycle_Delay_06 2 bytes + + ; Panel#7 Power Sequencing +$eDP_Vcc_To_Hpd_Delay_07 2 bytes +$eDP_DataOn_To_BkltEnable_Delay_07 2 bytes +$eDP_BkltDisable_To_DataOff_Delay_07 2 bytes +$eDP_DataOff_To_PowerOff_Delay_07 2 bytes +$eDP_PowerCycle_Delay_07 2 bytes + + ; Panel#8 Power Sequencing +$eDP_Vcc_To_Hpd_Delay_08 2 bytes +$eDP_DataOn_To_BkltEnable_Delay_08 2 bytes +$eDP_BkltDisable_To_DataOff_Delay_08 2 bytes +$eDP_DataOff_To_PowerOff_Delay_08 2 bytes +$eDP_PowerCycle_Delay_08 2 bytes + + ; Panel#9 Power Sequencing +$eDP_Vcc_To_Hpd_Delay_09 2 bytes +$eDP_DataOn_To_BkltEnable_Delay_09 2 bytes +$eDP_BkltDisable_To_DataOff_Delay_09 2 bytes +$eDP_DataOff_To_PowerOff_Delay_09 2 bytes +$eDP_PowerCycle_Delay_09 2 bytes + + ; Panel#10 Power Sequencing +$eDP_Vcc_To_Hpd_Delay_10 2 bytes +$eDP_DataOn_To_BkltEnable_Delay_10 2 bytes +$eDP_BkltDisable_To_DataOff_Delay_10 2 bytes +$eDP_DataOff_To_PowerOff_Delay_10 2 bytes +$eDP_PowerCycle_Delay_10 2 bytes + + ; Panel#11 Power Sequencing +$eDP_Vcc_To_Hpd_Delay_11 2 bytes +$eDP_DataOn_To_BkltEnable_Delay_11 2 bytes +$eDP_BkltDisable_To_DataOff_Delay_11 2 bytes +$eDP_DataOff_To_PowerOff_Delay_11 2 bytes +$eDP_PowerCycle_Delay_11 2 bytes + + ; Panel#12 Power Sequencing +$eDP_Vcc_To_Hpd_Delay_12 2 bytes +$eDP_DataOn_To_BkltEnable_Delay_12 2 bytes +$eDP_BkltDisable_To_DataOff_Delay_12 2 bytes +$eDP_DataOff_To_PowerOff_Delay_12 2 bytes +$eDP_PowerCycle_Delay_12 2 bytes + + ; Panel#13 Power Sequencing +$eDP_Vcc_To_Hpd_Delay_13 2 bytes +$eDP_DataOn_To_BkltEnable_Delay_13 2 bytes +$eDP_BkltDisable_To_DataOff_Delay_13 2 bytes +$eDP_DataOff_To_PowerOff_Delay_13 2 bytes +$eDP_PowerCycle_Delay_13 2 bytes + + ; Panel#14 Power Sequencing +$eDP_Vcc_To_Hpd_Delay_14 2 bytes +$eDP_DataOn_To_BkltEnable_Delay_14 2 bytes +$eDP_BkltDisable_To_DataOff_Delay_14 2 bytes +$eDP_DataOff_To_PowerOff_Delay_14 2 bytes +$eDP_PowerCycle_Delay_14 2 bytes + + ; Panel#15 Power Sequencing +$eDP_Vcc_To_Hpd_Delay_15 2 bytes +$eDP_DataOn_To_BkltEnable_Delay_15 2 bytes +$eDP_BkltDisable_To_DataOff_Delay_15 2 bytes +$eDP_DataOff_To_PowerOff_Delay_15 2 bytes +$eDP_PowerCycle_Delay_15 2 bytes + + ; Panel#16 Power Sequencing +$eDP_Vcc_To_Hpd_Delay_16 2 bytes +$eDP_DataOn_To_BkltEnable_Delay_16 2 bytes +$eDP_BkltDisable_To_DataOff_Delay_16 2 bytes +$eDP_DataOff_To_PowerOff_Delay_16 2 bytes +$eDP_PowerCycle_Delay_16 2 bytes + +$eDP_Panel_Color_Depth_01 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp +$eDP_Panel_Color_Depth_02 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp +$eDP_Panel_Color_Depth_03 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp +$eDP_Panel_Color_Depth_04 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp +$eDP_Panel_Color_Depth_05 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp +$eDP_Panel_Color_Depth_06 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp +$eDP_Panel_Color_Depth_07 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp +$eDP_Panel_Color_Depth_08 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp +$eDP_Panel_Color_Depth_09 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp +$eDP_Panel_Color_Depth_10 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp +$eDP_Panel_Color_Depth_11 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp +$eDP_Panel_Color_Depth_12 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp +$eDP_Panel_Color_Depth_13 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp +$eDP_Panel_Color_Depth_14 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp +$eDP_Panel_Color_Depth_15 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp +$eDP_Panel_Color_Depth_16 2 bits ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp + +$eDP_Link_DataRate_01 4 bits ; Panel #1 Link Data Rate +$eDP_Link_LaneCount_01 4 bits ; Panel #1 Link Lane Count +$eDP_Link_PreEmp_01 4 bits ; Panel #1 Link Pre-emphasis +$eDP_Link_Vswing_01 4 bits ; Panel #1 Link Voltage Swing + +$eDP_Link_DataRate_02 4 bits ; Panel #2 Link Data Rate +$eDP_Link_LaneCount_02 4 bits ; Panel #2 Link Lane Count +$eDP_Link_PreEmp_02 4 bits ; Panel #2 Link Pre-emphasis +$eDP_Link_Vswing_02 4 bits ; Panel #2 Link Voltage Swing + +$eDP_Link_DataRate_03 4 bits ; Panel #3 Link Data Rate +$eDP_Link_LaneCount_03 4 bits ; Panel #3 Link Lane Count +$eDP_Link_PreEmp_03 4 bits ; Panel #3 Link Pre-emphasis +$eDP_Link_Vswing_03 4 bits ; Panel #3 Link Voltage Swing + +$eDP_Link_DataRate_04 4 bits ; Panel #4 Link Data Rate +$eDP_Link_LaneCount_04 4 bits ; Panel #4 Link Lane Count +$eDP_Link_PreEmp_04 4 bits ; Panel #4 Link Pre-emphasis +$eDP_Link_Vswing_04 4 bits ; Panel #4 Link Voltage Swing + +$eDP_Link_DataRate_05 4 bits ; Panel #5 Link Data Rate +$eDP_Link_LaneCount_05 4 bits ; Panel #5 Link Lane Count +$eDP_Link_PreEmp_05 4 bits ; Panel #5 Link Pre-emphasis +$eDP_Link_Vswing_05 4 bits ; Panel #5 Link Voltage Swing + +$eDP_Link_DataRate_06 4 bits ; Panel #6 Link Data Rate +$eDP_Link_LaneCount_06 4 bits ; Panel #6 Link Lane Count +$eDP_Link_PreEmp_06 4 bits ; Panel #6 Link Pre-emphasis +$eDP_Link_Vswing_06 4 bits ; Panel #6 Link Voltage Swing + +$eDP_Link_DataRate_07 4 bits ; Panel #7 Link Data Rate +$eDP_Link_LaneCount_07 4 bits ; Panel #7 Link Lane Count +$eDP_Link_PreEmp_07 4 bits ; Panel #7 Link Pre-emphasis +$eDP_Link_Vswing_07 4 bits ; Panel #7 Link Voltage Swing + +$eDP_Link_DataRate_08 4 bits ; Panel #8 Link Data Rate +$eDP_Link_LaneCount_08 4 bits ; Panel #8 Link Lane Count +$eDP_Link_PreEmp_08 4 bits ; Panel #8 Link Pre-emphasis +$eDP_Link_Vswing_08 4 bits ; Panel #8 Link Voltage Swing + +$eDP_Link_DataRate_09 4 bits ; Panel #9 Link Data Rate +$eDP_Link_LaneCount_09 4 bits ; Panel #9 Link Lane Count +$eDP_Link_PreEmp_09 4 bits ; Panel #9 Link Pre-emphasis +$eDP_Link_Vswing_09 4 bits ; Panel #9 Link Voltage Swing + +$eDP_Link_DataRate_10 4 bits ; Panel #10 Link Data Rate +$eDP_Link_LaneCount_10 4 bits ; Panel #10 Link Lane Count +$eDP_Link_PreEmp_10 4 bits ; Panel #10 Link Pre-emphasis +$eDP_Link_Vswing_10 4 bits ; Panel #10 Link Voltage Swing + +$eDP_Link_DataRate_11 4 bits ; Panel #11 Link Data Rate +$eDP_Link_LaneCount_11 4 bits ; Panel #11 Link Lane Count +$eDP_Link_PreEmp_11 4 bits ; Panel #11 Link Pre-emphasis +$eDP_Link_Vswing_11 4 bits ; Panel #11 Link Voltage Swing + +$eDP_Link_DataRate_12 4 bits ; Panel #12 Link Data Rate +$eDP_Link_LaneCount_12 4 bits ; Panel #12 Link Lane Count +$eDP_Link_PreEmp_12 4 bits ; Panel #12 Link Pre-emphasis +$eDP_Link_Vswing_12 4 bits ; Panel #12 Link Voltage Swing + +$eDP_Link_DataRate_13 4 bits ; Panel #13 Link Data Rate +$eDP_Link_LaneCount_13 4 bits ; Panel #13 Link Lane Count +$eDP_Link_PreEmp_13 4 bits ; Panel #13 Link Pre-emphasis +$eDP_Link_Vswing_13 4 bits ; Panel #13 Link Voltage Swing + +$eDP_Link_DataRate_14 4 bits ; Panel #14 Link Data Rate +$eDP_Link_LaneCount_14 4 bits ; Panel #14 Link Lane Count +$eDP_Link_PreEmp_14 4 bits ; Panel #14 Link Pre-emphasis +$eDP_Link_Vswing_14 4 bits ; Panel #14 Link Voltage Swing + +$eDP_Link_DataRate_15 4 bits ; Panel #15 Link Data Rate +$eDP_Link_LaneCount_15 4 bits ; Panel #15 Link Lane Count +$eDP_Link_PreEmp_15 4 bits ; Panel #15 Link Pre-emphasis +$eDP_Link_Vswing_15 4 bits ; Panel #15 Link Voltage Swing + +$eDP_Link_DataRate_16 4 bits ; Panel #16 Link Data Rate +$eDP_Link_LaneCount_16 4 bits ; Panel #16 Link Lane Count +$eDP_Link_PreEmp_16 4 bits ; Panel #16 Link Pre-emphasis +$eDP_Link_Vswing_16 4 bits ; Panel #16 Link Voltage Swing + +$eDP_sDRRS_MSA_Delay_01 2 bits ; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4 +$eDP_sDRRS_MSA_Delay_02 2 bits ; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4 +$eDP_sDRRS_MSA_Delay_03 2 bits ; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4 +$eDP_sDRRS_MSA_Delay_04 2 bits ; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4 +$eDP_sDRRS_MSA_Delay_05 2 bits ; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4 +$eDP_sDRRS_MSA_Delay_06 2 bits ; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4 +$eDP_sDRRS_MSA_Delay_07 2 bits ; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4 +$eDP_sDRRS_MSA_Delay_08 2 bits ; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4 +$eDP_sDRRS_MSA_Delay_09 2 bits ; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4 +$eDP_sDRRS_MSA_Delay_10 2 bits ; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4 +$eDP_sDRRS_MSA_Delay_11 2 bits ; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4 +$eDP_sDRRS_MSA_Delay_12 2 bits ; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4 +$eDP_sDRRS_MSA_Delay_13 2 bits ; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4 +$eDP_sDRRS_MSA_Delay_14 2 bits ; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4 +$eDP_sDRRS_MSA_Delay_15 2 bits ; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4 +$eDP_sDRRS_MSA_Delay_16 2 bits ; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4 + +SKIP 2 bytes ; S3D Feature +$eDP_T3_Optimization_01 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #01 +$eDP_T3_Optimization_02 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #02 +$eDP_T3_Optimization_03 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #03 +$eDP_T3_Optimization_04 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #04 +$eDP_T3_Optimization_05 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #05 +$eDP_T3_Optimization_06 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #06 +$eDP_T3_Optimization_07 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #07 +$eDP_T3_Optimization_08 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #08 +$eDP_T3_Optimization_09 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #09 +$eDP_T3_Optimization_10 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #10 +$eDP_T3_Optimization_11 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #11 +$eDP_T3_Optimization_12 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #12 +$eDP_T3_Optimization_13 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #13 +$eDP_T3_Optimization_14 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #14 +$eDP_T3_Optimization_15 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #15 +$eDP_T3_Optimization_16 1 bit ; eDP T3 Optimization enable disabled VBT bit panel #16 + +$eDP_VSwingPreEmph_1 4 bits; eDp selects VSwing Preemph table for panel #1 +$eDP_VSwingPreEmph_2 4 bits; eDp selects VSwing Preemph table for panel #2 +$eDP_VSwingPreEmph_3 4 bits; eDp selects VSwing Preemph table for panel #3 +$eDP_VSwingPreEmph_4 4 bits; eDp selects VSwing Preemph table for panel #4 +$eDP_VSwingPreEmph_5 4 bits; eDp selects VSwing Preemph table for panel #5 +$eDP_VSwingPreEmph_6 4 bits; eDp selects VSwing Preemph table for panel #6 +$eDP_VSwingPreEmph_7 4 bits; eDp selects VSwing Preemph table for panel #7 +$eDP_VSwingPreEmph_8 4 bits; eDp selects VSwing Preemph table for panel #8 +$eDP_VSwingPreEmph_9 4 bits; eDp selects VSwing Preemph table for panel #9 +$eDP_VSwingPreEmph_10 4 bits; eDp selects VSwing Preemph table for panel #10 +$eDP_VSwingPreEmph_11 4 bits; eDp selects VSwing Preemph table for panel #11 +$eDP_VSwingPreEmph_12 4 bits; eDp selects VSwing Preemph table for panel #12 +$eDP_VSwingPreEmph_13 4 bits; eDp selects VSwing Preemph table for panel #13 +$eDP_VSwingPreEmph_14 4 bits; eDp selects VSwing Preemph table for panel #14 +$eDP_VSwingPreEmph_15 4 bits; eDp selects VSwing Preemph table for panel #15 +$eDP_VSwingPreEmph_16 4 bits; eDp selects VSwing Preemph table for panel #16 + +$Fast_Link_Training_Supported_01 1 bit ; eDP Selects Fast Link Training if supported for Panel #1 +$Fast_Link_Training_Supported_02 1 bit ; eDP Selects Fast Link Training if supported for Panel #2 +$Fast_Link_Training_Supported_03 1 bit ; eDP Selects Fast Link Training if supported for Panel #3 +$Fast_Link_Training_Supported_04 1 bit ; eDP Selects Fast Link Training if supported for Panel #4 +$Fast_Link_Training_Supported_05 1 bit ; eDP Selects Fast Link Training if supported for Panel #5 +$Fast_Link_Training_Supported_06 1 bit ; eDP Selects Fast Link Training if supported for Panel #6 +$Fast_Link_Training_Supported_07 1 bit ; eDP Selects Fast Link Training if supported for Panel #7 +$Fast_Link_Training_Supported_08 1 bit ; eDP Selects Fast Link Training if supported for Panel #8 +$Fast_Link_Training_Supported_09 1 bit ; eDP Selects Fast Link Training if supported for Panel #9 +$Fast_Link_Training_Supported_10 1 bit ; eDP Selects Fast Link Training if supported for Panel #10 +$Fast_Link_Training_Supported_11 1 bit ; eDP Selects Fast Link Training if supported for Panel #11 +$Fast_Link_Training_Supported_12 1 bit ; eDP Selects Fast Link Training if supported for Panel #12 +$Fast_Link_Training_Supported_13 1 bit ; eDP Selects Fast Link Training if supported for Panel #13 +$Fast_Link_Training_Supported_14 1 bit ; eDP Selects Fast Link Training if supported for Panel #14 +$Fast_Link_Training_Supported_15 1 bit ; eDP Selects Fast Link Training if supported for Panel #15 +$Fast_Link_Training_Supported_16 1 bit ; eDP Selects Fast Link Training if supported for Panel #16 + +SKIP 2 bytes ;Skip Enable Power State at DPCD 600h + +$eDP_PwmOn_To_Bklt_Enable_Delay_01 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#1 +$eDP_Bklt_Disable_To_PwmOff_Delay_01 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#1 + +$eDP_PwmOn_To_Bklt_Enable_Delay_02 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#2 +$eDP_Bklt_Disable_To_PwmOff_Delay_02 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#2 + +$eDP_PwmOn_To_Bklt_Enable_Delay_03 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#3 +$eDP_Bklt_Disable_To_PwmOff_Delay_03 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#3 + +$eDP_PwmOn_To_Bklt_Enable_Delay_04 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#4 +$eDP_Bklt_Disable_To_PwmOff_Delay_04 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#4 + +$eDP_PwmOn_To_Bklt_Enable_Delay_05 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#5 +$eDP_Bklt_Disable_To_PwmOff_Delay_05 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#5 + +$eDP_PwmOn_To_Bklt_Enable_Delay_06 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#6 +$eDP_Bklt_Disable_To_PwmOff_Delay_06 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#6 + +$eDP_PwmOn_To_Bklt_Enable_Delay_07 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#7 +$eDP_Bklt_Disable_To_PwmOff_Delay_07 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#7 + +$eDP_PwmOn_To_Bklt_Enable_Delay_08 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#8 +$eDP_Bklt_Disable_To_PwmOff_Delay_08 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#8 + +$eDP_PwmOn_To_Bklt_Enable_Delay_09 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#9 +$eDP_Bklt_Disable_To_PwmOff_Delay_09 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#9 + +$eDP_PwmOn_To_Bklt_Enable_Delay_10 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#10 +$eDP_Bklt_Disable_To_PwmOff_Delay_10 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#10 + +$eDP_PwmOn_To_Bklt_Enable_Delay_11 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#11 +$eDP_Bklt_Disable_To_PwmOff_Delay_11 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#11 + +$eDP_PwmOn_To_Bklt_Enable_Delay_12 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#12 +$eDP_Bklt_Disable_To_PwmOff_Delay_12 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#12 + +$eDP_PwmOn_To_Bklt_Enable_Delay_13 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#13 +$eDP_Bklt_Disable_To_PwmOff_Delay_13 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#13 + +$eDP_PwmOn_To_Bklt_Enable_Delay_14 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#14 +$eDP_Bklt_Disable_To_PwmOff_Delay_14 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#14 + +$eDP_PwmOn_To_Bklt_Enable_Delay_15 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#15 +$eDP_Bklt_Disable_To_PwmOff_Delay_15 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#15 + +$eDP_PwmOn_To_Bklt_Enable_Delay_16 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#16 +$eDP_Bklt_Disable_To_PwmOff_Delay_16 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#16 + +;============================================================================== +; Block 28 - EDID-less EFP support - Panel data +;------------------------------------------------------------------------------ +SKIP 3 bytes ; Skip block ID and size +$EFP1_DTD 18 bytes ; DTD for Device 1 DP/HDMI/DVI panel +$EFP2_DTD 18 bytes ; DTD for Device 2 DP/HDMI/DVI panel +$EFP3_DTD 18 bytes ; DTD for Device 3 DP/HDMI/DVI panel +$EFP4_DTD 18 bytes ; DTD for Device 4 DP/HDMI/DVI panel + +;============================================================================== +; Block 31 - VBIOS/Driver Toggle list for HSW/BDW/CHV +;------------------------------------------------------------------------------ + +SKIP 3 bytes ; Skip block ID and size +SKIP 3 bytes ; Skip number of entries and entry size +$Toggle_List1 32 bytes ; Toggle list 1 +SKIP 3 bytes ; Skip number of entries and entry size +$Toggle_List2 16 bytes ; Toggle list 2 +SKIP 3 bytes ; Skip number of entries and entry size +$Toggle_List3 16 bytes ; Toggle list 3 +SKIP 3 bytes ; Skip number of entries and entry size +$Toggle_List4 16 bytes ; Toggle list 4 +ALIGN + +;============================================================================== +; Block 40 - Start of LVDS BMP Structure Definition +;------------------------------------------------------------------------------ + +SKIP 3 bytes ; Skip block ID and size + +$bmp_Panel_type 1 byte ; Flat panel type +SKIP 1 byte ; Obsoleted +SKIP 6 bits +$bmp_Panel_EDID 1 bit ; LVDS panel EDID enable/disable bit +SKIP 1 bit +SKIP 1 byte + + ; INT_LVDS_Panel_Channel_Bits + +$Int_LVDS_Panel_1_Channel_Type 2 bits ; Bits [2:3] = Panel #1 + ; = 00, Automatic (algorithm) + ; = 01, Single Channel + ; = 10, Dual Channel + ; = 11, Reserved +$Int_LVDS_Panel_2_Channel_Type 2 bits ; Bits [2:3] = Panel #2 + ; = 00, Automatic (algorithm) + ; = 01, Single Channel + ; = 10, Dual Channel + ; = 11, Reserved +$Int_LVDS_Panel_3_Channel_Type 2 bits ; Bits [2:3] = Panel #3 + ; = 00, Automatic (algorithm) + ; = 01, Single Channel + ; = 10, Dual Channel + ; = 11, Reserved +$Int_LVDS_Panel_4_Channel_Type 2 bits ; Bits [2:3] = Panel #4 + ; = 00, Automatic (algorithm) + ; = 01, Single Channel + ; = 10, Dual Channel + ; = 11, Reserved +$Int_LVDS_Panel_5_Channel_Type 2 bits ; Bits [2:3] = Panel #5 + ; = 00, Automatic (algorithm) + ; = 01, Single Channel + ; = 10, Dual Channel + ; = 11, Reserved +$Int_LVDS_Panel_6_Channel_Type 2 bits ; Bits [2:3] = Panel #6 + ; = 00, Automatic (algorithm) + ; = 01, Single Channel + ; = 10, Dual Channel + ; = 11, Reserved +$Int_LVDS_Panel_7_Channel_Type 2 bits ; Bits [2:3] = Panel #7 + ; = 00, Automatic (algorithm) + ; = 01, Single Channel + ; = 10, Dual Channel + ; = 11, Reserved +$Int_LVDS_Panel_8_Channel_Type 2 bits ; Bits [2:3] = Panel #8 + ; = 00, Automatic (algorithm) + ; = 01, Single Channel + ; = 10, Dual Channel + ; = 11, Reserved +$Int_LVDS_Panel_9_Channel_Type 2 bits ; Bits [2:3] = Panel #9 + ; = 00, Automatic (algorithm) + ; = 01, Single Channel + ; = 10, Dual Channel + ; = 11, Reserved +$Int_LVDS_Panel_10_Channel_Type 2 bits ; Bits [2:3] = Panel #10 + ; = 00, Automatic (algorithm) + ; = 01, Single Channel + ; = 10, Dual Channel + ; = 11, Reserved +$Int_LVDS_Panel_11_Channel_Type 2 bits ; Bits [2:3] = Panel #11 + ; = 00, Automatic (algorithm) + ; = 01, Single Channel + ; = 10, Dual Channel + ; = 11, Reserved +$Int_LVDS_Panel_12_Channel_Type 2 bits ; Bits [2:3] = Panel #12 + ; = 00, Automatic (algorithm) + ; = 01, Single Channel + ; = 10, Dual Channel + ; = 11, Reserved +$Int_LVDS_Panel_13_Channel_Type 2 bits ; Bits [2:3] = Panel #13 + ; = 00, Automatic (algorithm) + ; = 01, Single Channel + ; = 10, Dual Channel + ; = 11, Reserved +$Int_LVDS_Panel_14_Channel_Type 2 bits ; Bits [2:3] = Panel #14 + ; = 00, Automatic (algorithm) + ; = 01, Single Channel + ; = 10, Dual Channel + ; = 11, Reserved +$Int_LVDS_Panel_15_Channel_Type 2 bits ; Bits [2:3] = Panel #15 + ; = 00, Automatic (algorithm) + ; = 01, Single Channel + ; = 10, Dual Channel + ; = 11, Reserved +$Int_LVDS_Panel_16_Channel_Type 2 bits ; Bits [2:3] = Panel #16 + ; = 00, Automatic (algorithm) + ; = 01, Single Channel + ; = 10, Dual Channel + ; = 11, Reserved + + ; LVDS Spread Spectrum Clock + ; Enabel/Disable SSC +$Enable_SSC01 1 bit ; Panel #01, 0=No, 1=Yes +$Enable_SSC02 1 bit ; Panel #02, 0=No, 1=Yes +$Enable_SSC03 1 bit ; Panel #03, 0=No, 1=Yes +$Enable_SSC04 1 bit ; Panel #04, 0=No, 1=Yes +$Enable_SSC05 1 bit ; Panel #05, 0=No, 1=Yes +$Enable_SSC06 1 bit ; Panel #06, 0=No, 1=Yes +$Enable_SSC07 1 bit ; Panel #07, 0=No, 1=Yes +$Enable_SSC08 1 bit ; Panel #08, 0=No, 1=Yes +$Enable_SSC09 1 bit ; Panel #09, 0=No, 1=Yes +$Enable_SSC10 1 bit ; Panel #10, 0=No, 1=Yes +$Enable_SSC11 1 bit ; Panel #11, 0=No, 1=Yes +$Enable_SSC12 1 bit ; Panel #12, 0=No, 1=Yes +$Enable_SSC13 1 bit ; Panel #13, 0=No, 1=Yes +$Enable_SSC14 1 bit ; Panel #14, 0=No, 1=Yes +$Enable_SSC15 1 bit ; Panel #15, 0=No, 1=Yes +$Enable_SSC16 1 bit ; Panel #16, 0=No, 1=Yes + + ; LVDS Spread Spectrum Clock Frequency + ; SSC Frequency +$SSC_Freq01 1 bit ; Panel #01, 0=48MHz, 1=66MHz +$SSC_Freq02 1 bit ; Panel #02, 0=48MHz, 1=66MHz +$SSC_Freq03 1 bit ; Panel #03, 0=48MHz, 1=66MHz +$SSC_Freq04 1 bit ; Panel #04, 0=48MHz, 1=66MHz +$SSC_Freq05 1 bit ; Panel #05, 0=48MHz, 1=66MHz +$SSC_Freq06 1 bit ; Panel #06, 0=48MHz, 1=66MHz +$SSC_Freq07 1 bit ; Panel #07, 0=48MHz, 1=66MHz +$SSC_Freq08 1 bit ; Panel #08, 0=48MHz, 1=66MHz +$SSC_Freq09 1 bit ; Panel #09, 0=48MHz, 1=66MHz +$SSC_Freq10 1 bit ; Panel #10, 0=48MHz, 1=66MHz +$SSC_Freq11 1 bit ; Panel #11, 0=48MHz, 1=66MHz +$SSC_Freq12 1 bit ; Panel #12, 0=48MHz, 1=66MHz +$SSC_Freq13 1 bit ; Panel #13, 0=48MHz, 1=66MHz +$SSC_Freq14 1 bit ; Panel #14, 0=48MHz, 1=66MHz +$SSC_Freq15 1 bit ; Panel #15, 0=48MHz, 1=66MHz +$SSC_Freq16 1 bit ; Panel #16, 0=48MHz, 1=66MHz + + ; Disable SSC in Dual Display Twin +$Disable_SSC_DDT01 1 bit ; panel #01, 0=Disable, 1=Enable +$Disable_SSC_DDT02 1 bit ; panel #02, 0=Disable, 1=Enable +$Disable_SSC_DDT03 1 bit ; panel #03, 0=Disable, 1=Enable +$Disable_SSC_DDT04 1 bit ; panel #04, 0=Disable, 1=Enable +$Disable_SSC_DDT05 1 bit ; panel #05, 0=Disable, 1=Enable +$Disable_SSC_DDT06 1 bit ; panel #06, 0=Disable, 1=Enable +$Disable_SSC_DDT07 1 bit ; panel #07, 0=Disable, 1=Enable +$Disable_SSC_DDT08 1 bit ; panel #08, 0=Disable, 1=Enable +$Disable_SSC_DDT09 1 bit ; panel #09, 0=Disable, 1=Enable +$Disable_SSC_DDT10 1 bit ; panel #10, 0=Disable, 1=Enable +$Disable_SSC_DDT11 1 bit ; panel #11, 0=Disable, 1=Enable +$Disable_SSC_DDT12 1 bit ; panel #12, 0=Disable, 1=Enable +$Disable_SSC_DDT13 1 bit ; panel #13, 0=Disable, 1=Enable +$Disable_SSC_DDT14 1 bit ; panel #14, 0=Disable, 1=Enable +$Disable_SSC_DDT15 1 bit ; panel #15, 0=Disable, 1=Enable +$Disable_SSC_DDT16 1 bit ; panel #16, 0=Disable, 1=Enable + +$INT_Panel_Color_Depth01 1 bit ; Panel #01, 0 = 18bpps, 1 = 24bpps +$INT_Panel_Color_Depth02 1 bit ; Panel #02, 0 = 18bpps, 1 = 24bpps +$INT_Panel_Color_Depth03 1 bit ; Panel #03, 0 = 18bpps, 1 = 24bpps +$INT_Panel_Color_Depth04 1 bit ; Panel #04, 0 = 18bpps, 1 = 24bpps +$INT_Panel_Color_Depth05 1 bit ; Panel #05, 0 = 18bpps, 1 = 24bpps +$INT_Panel_Color_Depth06 1 bit ; Panel #06, 0 = 18bpps, 1 = 24bpps +$INT_Panel_Color_Depth07 1 bit ; Panel #07, 0 = 18bpps, 1 = 24bpps +$INT_Panel_Color_Depth08 1 bit ; Panel #08, 0 = 18bpps, 1 = 24bpps +$INT_Panel_Color_Depth09 1 bit ; Panel #09, 0 = 18bpps, 1 = 24bpps +$INT_Panel_Color_Depth10 1 bit ; Panel #10, 0 = 18bpps, 1 = 24bpps +$INT_Panel_Color_Depth11 1 bit ; Panel #11, 0 = 18bpps, 1 = 24bpps +$INT_Panel_Color_Depth12 1 bit ; Panel #12, 0 = 18bpps, 1 = 24bpps +$INT_Panel_Color_Depth13 1 bit ; Panel #13, 0 = 18bpps, 1 = 24bpps +$INT_Panel_Color_Depth14 1 bit ; Panel #14, 0 = 18bpps, 1 = 24bpps +$INT_Panel_Color_Depth15 1 bit ; Panel #15, 0 = 18bpps, 1 = 24bpps +$INT_Panel_Color_Depth16 1 bit ; Panel #16, 0 = 18bpps, 1 = 24bpps + +$DPS_Panel_Type_01 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless +$DPS_Panel_Type_02 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless +$DPS_Panel_Type_03 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless +$DPS_Panel_Type_04 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless +$DPS_Panel_Type_05 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless +$DPS_Panel_Type_06 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless +$DPS_Panel_Type_07 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless +$DPS_Panel_Type_08 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless +$DPS_Panel_Type_09 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless +$DPS_Panel_Type_10 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless +$DPS_Panel_Type_11 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless +$DPS_Panel_Type_12 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless +$DPS_Panel_Type_13 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless +$DPS_Panel_Type_14 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless +$DPS_Panel_Type_15 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless +$DPS_Panel_Type_16 2 bits ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless + +$Blt_Control_01 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight +$Blt_Control_02 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight +$Blt_Control_03 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight +$Blt_Control_04 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight +$Blt_Control_05 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight +$Blt_Control_06 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight +$Blt_Control_07 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight +$Blt_Control_08 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight +$Blt_Control_09 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight +$Blt_Control_10 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight +$Blt_Control_11 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight +$Blt_Control_12 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight +$Blt_Control_13 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight +$Blt_Control_14 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight +$Blt_Control_15 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight +$Blt_Control_16 2 bits ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight + + +;============================================================================== +; Block 41 - Flat Panel Data Tables Pointers +;------------------------------------------------------------------------------ + +SKIP 3 bytes ; SKIP block ID and size +SKIP 1 byte ; Skip entries number byte + +$LVDS_Tbl_Ptr_01 2 bytes +$LVDS_Tbl_Size_01 1 byte +$LVDS_Tbl_01, $LVDS_Tbl_Ptr_01, $LVDS_Tbl_Size_01, Offset 4 bytes +$DVO_Tbl_Ptr_01 2 bytes +$DVO_Tbl_Size_01 1 byte +$DVO_Tbl_01, $DVO_Tbl_Ptr_01, $DVO_Tbl_Size_01, Offset 0 byte +$LVDS_PnP_ID_Ptr_01 2 bytes +$LVDS_PnP_ID_Size_01 1 byte +$LVDS_PnP_ID_01, $LVDS_PnP_ID_Ptr_01, $LVDS_PnP_ID_Size_01, Offset 0 byte + +$LVDS_Tbl_Ptr_02 2 bytes +$LVDS_Tbl_Size_02 1 byte +$LVDS_Tbl_02, $LVDS_Tbl_Ptr_02, $LVDS_Tbl_Size_02, Offset 4 bytes +$DVO_Tbl_Ptr_02 2 bytes +$DVO_Tbl_Size_02 1 byte +$DVO_Tbl_02, $DVO_Tbl_Ptr_02, $DVO_Tbl_Size_02, Offset 0 byte +$LVDS_PnP_ID_Ptr_02 2 bytes +$LVDS_PnP_ID_Size_02 1 byte +$LVDS_PnP_ID_02, $LVDS_PnP_ID_Ptr_02, $LVDS_PnP_ID_Size_02, Offset 0 byte + +$LVDS_Tbl_Ptr_03 2 bytes +$LVDS_Tbl_Size_03 1 byte +$LVDS_Tbl_03, $LVDS_Tbl_Ptr_03, $LVDS_Tbl_Size_03, Offset 4 bytes +$DVO_Tbl_Ptr_03 2 bytes +$DVO_Tbl_Size_03 1 byte +$DVO_Tbl_03, $DVO_Tbl_Ptr_03, $DVO_Tbl_Size_03, Offset 0 byte +$LVDS_PnP_ID_Ptr_03 2 bytes +$LVDS_PnP_ID_Size_03 1 byte +$LVDS_PnP_ID_03, $LVDS_PnP_ID_Ptr_03, $LVDS_PnP_ID_Size_03, Offset 0 byte + +$LVDS_Tbl_Ptr_04 2 bytes +$LVDS_Tbl_Size_04 1 byte +$LVDS_Tbl_04, $LVDS_Tbl_Ptr_04, $LVDS_Tbl_Size_04, Offset 4 bytes +$DVO_Tbl_Ptr_04 2 bytes +$DVO_Tbl_Size_04 1 byte +$DVO_Tbl_04, $DVO_Tbl_Ptr_04, $DVO_Tbl_Size_04, Offset 0 byte +$LVDS_PnP_ID_Ptr_04 2 bytes +$LVDS_PnP_ID_Size_04 1 byte +$LVDS_PnP_ID_04, $LVDS_PnP_ID_Ptr_04, $LVDS_PnP_ID_Size_04, Offset 0 byte + +$LVDS_Tbl_Ptr_05 2 bytes +$LVDS_Tbl_Size_05 1 byte +$LVDS_Tbl_05, $LVDS_Tbl_Ptr_05, $LVDS_Tbl_Size_05, Offset 4 bytes +$DVO_Tbl_Ptr_05 2 bytes +$DVO_Tbl_Size_05 1 byte +$DVO_Tbl_05, $DVO_Tbl_Ptr_05, $DVO_Tbl_Size_05, Offset 0 byte +$LVDS_PnP_ID_Ptr_05 2 bytes +$LVDS_PnP_ID_Size_05 1 byte +$LVDS_PnP_ID_05, $LVDS_PnP_ID_Ptr_05, $LVDS_PnP_ID_Size_05, Offset 0 byte + +$LVDS_Tbl_Ptr_06 2 bytes +$LVDS_Tbl_Size_06 1 byte +$LVDS_Tbl_06, $LVDS_Tbl_Ptr_06, $LVDS_Tbl_Size_06, Offset 4 bytes +$DVO_Tbl_Ptr_06 2 bytes +$DVO_Tbl_Size_06 1 byte +$DVO_Tbl_06, $DVO_Tbl_Ptr_06, $DVO_Tbl_Size_06, Offset 0 byte +$LVDS_PnP_ID_Ptr_06 2 bytes +$LVDS_PnP_ID_Size_06 1 byte +$LVDS_PnP_ID_06, $LVDS_PnP_ID_Ptr_06, $LVDS_PnP_ID_Size_06, Offset 0 byte + +$LVDS_Tbl_Ptr_07 2 bytes +$LVDS_Tbl_Size_07 1 byte +$LVDS_Tbl_07, $LVDS_Tbl_Ptr_07, $LVDS_Tbl_Size_07, Offset 4 bytes +$DVO_Tbl_Ptr_07 2 bytes +$DVO_Tbl_Size_07 1 byte +$DVO_Tbl_07, $DVO_Tbl_Ptr_07, $DVO_Tbl_Size_07, Offset 0 byte +$LVDS_PnP_ID_Ptr_07 2 bytes +$LVDS_PnP_ID_Size_07 1 byte +$LVDS_PnP_ID_07, $LVDS_PnP_ID_Ptr_07, $LVDS_PnP_ID_Size_07, Offset 0 byte + +$LVDS_Tbl_Ptr_08 2 bytes +$LVDS_Tbl_Size_08 1 byte +$LVDS_Tbl_08, $LVDS_Tbl_Ptr_08, $LVDS_Tbl_Size_08, Offset 4 bytes +$DVO_Tbl_Ptr_08 2 bytes +$DVO_Tbl_Size_08 1 byte +$DVO_Tbl_08, $DVO_Tbl_Ptr_08, $DVO_Tbl_Size_08, Offset 0 byte +$LVDS_PnP_ID_Ptr_08 2 bytes +$LVDS_PnP_ID_Size_08 1 byte +$LVDS_PnP_ID_08, $LVDS_PnP_ID_Ptr_08, $LVDS_PnP_ID_Size_08, Offset 0 byte + +$LVDS_Tbl_Ptr_09 2 bytes +$LVDS_Tbl_Size_09 1 byte +$LVDS_Tbl_09, $LVDS_Tbl_Ptr_09, $LVDS_Tbl_Size_09, Offset 4 bytes +$DVO_Tbl_Ptr_09 2 bytes +$DVO_Tbl_Size_09 1 byte +$DVO_Tbl_09, $DVO_Tbl_Ptr_09, $DVO_Tbl_Size_09, Offset 0 byte +$LVDS_PnP_ID_Ptr_09 2 bytes +$LVDS_PnP_ID_Size_09 1 byte +$LVDS_PnP_ID_09, $LVDS_PnP_ID_Ptr_09, $LVDS_PnP_ID_Size_09, Offset 0 byte + +$LVDS_Tbl_Ptr_10 2 bytes +$LVDS_Tbl_Size_10 1 byte +$LVDS_Tbl_10, $LVDS_Tbl_Ptr_10, $LVDS_Tbl_Size_10, Offset 4 bytes +$DVO_Tbl_Ptr_10 2 bytes +$DVO_Tbl_Size_10 1 byte +$DVO_Tbl_10, $DVO_Tbl_Ptr_10, $DVO_Tbl_Size_10, Offset 0 byte +$LVDS_PnP_ID_Ptr_10 2 bytes +$LVDS_PnP_ID_Size_10 1 byte +$LVDS_PnP_ID_10, $LVDS_PnP_ID_Ptr_10, $LVDS_PnP_ID_Size_10, Offset 0 byte + +$LVDS_Tbl_Ptr_11 2 bytes +$LVDS_Tbl_Size_11 1 byte +$LVDS_Tbl_11, $LVDS_Tbl_Ptr_11, $LVDS_Tbl_Size_11, Offset 4 bytes +$DVO_Tbl_Ptr_11 2 bytes +$DVO_Tbl_Size_11 1 byte +$DVO_Tbl_11, $DVO_Tbl_Ptr_11, $DVO_Tbl_Size_11, Offset 0 byte +$LVDS_PnP_ID_Ptr_11 2 bytes +$LVDS_PnP_ID_Size_11 1 byte +$LVDS_PnP_ID_11, $LVDS_PnP_ID_Ptr_11, $LVDS_PnP_ID_Size_11, Offset 0 byte + +$LVDS_Tbl_Ptr_12 2 bytes +$LVDS_Tbl_Size_12 1 byte +$LVDS_Tbl_12, $LVDS_Tbl_Ptr_12, $LVDS_Tbl_Size_12, Offset 4 bytes +$DVO_Tbl_Ptr_12 2 bytes +$DVO_Tbl_Size_12 1 byte +$DVO_Tbl_12, $DVO_Tbl_Ptr_12, $DVO_Tbl_Size_12, Offset 0 byte +$LVDS_PnP_ID_Ptr_12 2 bytes +$LVDS_PnP_ID_Size_12 1 byte +$LVDS_PnP_ID_12, $LVDS_PnP_ID_Ptr_12, $LVDS_PnP_ID_Size_12, Offset 0 byte + +$LVDS_Tbl_Ptr_13 2 bytes +$LVDS_Tbl_Size_13 1 byte +$LVDS_Tbl_13, $LVDS_Tbl_Ptr_13, $LVDS_Tbl_Size_13, Offset 4 bytes +$DVO_Tbl_Ptr_13 2 bytes +$DVO_Tbl_Size_13 1 byte +$DVO_Tbl_13, $DVO_Tbl_Ptr_13, $DVO_Tbl_Size_13, Offset 0 byte +$LVDS_PnP_ID_Ptr_13 2 bytes +$LVDS_PnP_ID_Size_13 1 byte +$LVDS_PnP_ID_13, $LVDS_PnP_ID_Ptr_13, $LVDS_PnP_ID_Size_13, Offset 0 byte + +$LVDS_Tbl_Ptr_14 2 bytes +$LVDS_Tbl_Size_14 1 byte +$LVDS_Tbl_14, $LVDS_Tbl_Ptr_14, $LVDS_Tbl_Size_14, Offset 4 bytes +$DVO_Tbl_Ptr_14 2 bytes +$DVO_Tbl_Size_14 1 byte +$DVO_Tbl_14, $DVO_Tbl_Ptr_14, $DVO_Tbl_Size_14, Offset 0 byte +$LVDS_PnP_ID_Ptr_14 2 bytes +$LVDS_PnP_ID_Size_14 1 byte +$LVDS_PnP_ID_14, $LVDS_PnP_ID_Ptr_14, $LVDS_PnP_ID_Size_14, Offset 0 byte + +$LVDS_Tbl_Ptr_15 2 bytes +$LVDS_Tbl_Size_15 1 byte +$LVDS_Tbl_15, $LVDS_Tbl_Ptr_15, $LVDS_Tbl_Size_15, Offset 4 bytes +$DVO_Tbl_Ptr_15 2 bytes +$DVO_Tbl_Size_15 1 byte +$DVO_Tbl_15, $DVO_Tbl_Ptr_15, $DVO_Tbl_Size_15, Offset 0 byte +$LVDS_PnP_ID_Ptr_15 2 bytes +$LVDS_PnP_ID_Size_15 1 byte +$LVDS_PnP_ID_15, $LVDS_PnP_ID_Ptr_15, $LVDS_PnP_ID_Size_15, Offset 0 byte + +$LVDS_Tbl_Ptr_16 2 bytes +$LVDS_Tbl_Size_16 1 byte +$LVDS_Tbl_16, $LVDS_Tbl_Ptr_16, $LVDS_Tbl_Size_16, Offset 4 bytes +$DVO_Tbl_Ptr_16 2 bytes +$DVO_Tbl_Size_16 1 byte +$DVO_Tbl_16, $DVO_Tbl_Ptr_16, $DVO_Tbl_Size_16, Offset 0 byte +$LVDS_PnP_ID_Ptr_16 2 bytes +$LVDS_PnP_ID_Size_16 1 byte +$LVDS_PnP_ID_16, $LVDS_PnP_ID_Ptr_16, $LVDS_PnP_ID_Size_16, Offset 0 byte + +SKIP 2 bytes ;LfpPanelNameTable Offset +SKIP 1 byte ;LfpPanelName Length + + + +;============================================================================== +; Block 42 - Flat Panel Data Tables +;------------------------------------------------------------------------------ + +SKIP 3 bytes ; Skip block ID and size + + ; Flat Panel #1 + +$Panel_Width_01 2 bytes ; Panel Width +$Panel_Height_01 2 bytes ; Panel Height + +SKIP 4 bytes ;address-0x61180 or 0x0E1180 (for ILM) - Port control +SKIP 3 bytes ; bits[23:0] +SKIP 1 bit ; bit[24] +$Enable_Dither01 1 bit ; Panel #01, 0=No, 1=Yes +SKIP 6 bits ; bits[31:26] +ALIGN + +SKIP 4 bytes ; address-0x61208 or 0x0C7208 (for ILM) - Panel power on sequencing +$Power_On_Backlight_Enable_Delay_01 13 bits ; Power on Backlight Enable delay +SKIP 3 bits ; bits[15:13] +$PowerUpDelay_01 13 bits ; Power up delay +SKIP 3 bits ; bits[31:29] +ALIGN + +SKIP 4 bytes ; address-0x6120C or 0x0C720C (for ILM) -Panel Power off sequencing +$Power_Backlight_Off_Power_Down_Delay_01 13 bits ;Backlight off power down delay +SKIP 3 bits ; bits[15:13] +$PowerDownDelay_01 13 bits ; Power down delay +SKIP 3 bits ; bits[31:29] +ALIGN + +SKIP 4 bytes ;address-0x61210h or 0x0C7210 (for ILM) -Panel power cycle delay and reference divider +$PowerCycleDelay_01 5 bits ; Power Cycle delay +SKIP 3 bits ; bits[5:7] +ALIGN +SKIP 3 bytes + +SKIP 2 bytes ; 2 bytes at the end + +SKIP 18 bytes ; DTD +SKIP 10 bytes ; PnP ID + + ; Flat Panel #2 + +$Panel_Width_02 2 bytes ; Panel Width +$Panel_Height_02 2 bytes ; Panel Height + +SKIP 4 bytes ;address-0x61180 or 0x0E1180 (for ILM) - Port control +SKIP 3 bytes ; bits[23:0] +SKIP 1 bit ; bit[24] +$Enable_Dither02 1 bit ; Panel #02, 0=No, 1=Yes +SKIP 6 bits ; bits[31:26] +ALIGN + +SKIP 4 bytes ;address-0x61208 or 0x0C7208 (for ILM) - Panel power on sequencing +$Power_On_Backlight_Enable_Delay_02 13 bits ; Power on backlight enable delay +SKIP 3 bits ; bits[15:13] +$PowerUpDelay_02 13 bits ; Power up delay +SKIP 3 bits ; bits[31:29] +ALIGN + +SKIP 4 bytes ;address-0x6120C or 0x0C720C (for ILM)-Panel Power off sequencing +$Power_Backlight_Off_Power_Down_Delay_02 13 bits ; Backlight off power down delay +SKIP 3 bits ; bits[15:13] +$PowerDownDelay_02 13 bits ; Power down delay +SKIP 3 bits ; bits[31:29] +ALIGN + +SKIP 4 bytes ;address-0x61210h or 0x0C7210 (for ILM)-Panel power cycle delay and reference divider +$PowerCycleDelay_02 5 bits ; Power Cycle delay +SKIP 3 bits ; bits[5:7] +SKIP 3 bytes + +SKIP 2 bytes ; 2 bytes at the end +SKIP 18 bytes ; DTD +SKIP 10 bytes ; PnP ID + + ; Flat Panel #3 + +$Panel_Width_03 2 bytes ; Panel Width +$Panel_Height_03 2 bytes ; Panel Height +SKIP 4 bytes ;address-0x61180 or 0x0E1180 (for ILM) - Port control +SKIP 3 bytes ; bits[23:0] +SKIP 1 bit ; bit[24] +$Enable_Dither03 1 bit ; Panel #03, 0=No, 1=Yes +SKIP 6 bits ; bits[31:26] +ALIGN + +SKIP 4 bytes ;address-0x61208 or 0x0C7208 (for ILM) - Panel power on sequencing +$Power_On_Backlight_Enable_Delay_03 13 bits ; Power on backlight enable delay +SKIP 3 bits ; bits[15:13] +$PowerUpDelay_03 13 bits ; Power up delay +SKIP 3 bits ; bits[31:29] +ALIGN + +SKIP 4 bytes ;address-0x6120C or 0x0C720C (for ILM)-Panel Power off sequencing +$Power_Backlight_Off_Power_Down_Delay_03 13 bits ; Backlight off power down delay +SKIP 3 bits ; bits[15:13] +$PowerDownDelay_03 13 bits ; Power down delay +SKIP 3 bits ; bits[31:29] +ALIGN + +SKIP 4 bytes ;aaddress-0x61210h or 0x0C7210 (for ILM)-Panel power cycle delay and reference divider +$PowerCycleDelay_03 5 bits ; Power Cycle delay +SKIP 3 bits ; bits[5:7] +SKIP 3 bytes + +SKIP 2 bytes ; 2 bytes at the end +SKIP 18 bytes ; DTD +SKIP 10 bytes ; PnP ID + + ; Flat Panel #4 + +$Panel_Width_04 2 bytes ; Panel Width +$Panel_Height_04 2 bytes ; Panel Height +SKIP 4 bytes ;address-0x61180 or 0x0E1180 (for ILM) - Port control +SKIP 3 bytes ; bits[23:0] +SKIP 1 bit ; bit[24] +$Enable_Dither04 1 bit ; Panel #04, 0=No, 1=Yes +SKIP 6 bits ; bits[31:26] +ALIGN + +SKIP 4 bytes ;address-0x61208 or 0x0C7208 (for ILM) - Panel power on sequencing +$Power_On_Backlight_Enable_Delay_04 13 bits ; Power on backlight enable delay +SKIP 3 bits ; bits[15:13] +$PowerUpDelay_04 13 bits ; Power up delay +SKIP 3 bits ; bits[31:29] +ALIGN + +SKIP 4 bytes ;address-0x6120C or 0x0C720C (for ILM)-Panel Power off sequencing +$Power_Backlight_Off_Power_Down_Delay_04 13 bits ; Backlight off power down delay +SKIP 3 bits ; bits[15:13] +$PowerDownDelay_04 13 bits ; Power down delay +SKIP 3 bits ; bits[31:29] +ALIGN + +SKIP 4 bytes ;address-0x61210h or 0x0C7210 (for ILM)-Panel power cycle delay and reference divider +$PowerCycleDelay_04 5 bits ; Power Cycle delay +SKIP 3 bits ; bits[5:7] +SKIP 3 bytes + +SKIP 2 bytes ; 2 bytes at the end +SKIP 18 bytes ; DTD +SKIP 10 bytes ; PnP ID + + ; Flat Panel #5 + +$Panel_Width_05 2 bytes ; Panel Width +$Panel_Height_05 2 bytes ; Panel Height +SKIP 4 bytes ;address-0x61180 or 0x0E1180 (for ILM) - Port control +SKIP 3 bytes ; bits[23:0] +SKIP 1 bit ; bit[24] +$Enable_Dither05 1 bit ; Panel #05, 0=No, 1=Yes +SKIP 6 bits ; bits[31:26] +ALIGN + +SKIP 4 bytes ;address-0x61208 or 0x0C7208 (for ILM) - Panel power on sequencing +$Power_On_Backlight_Enable_Delay_05 13 bits ; Power on backlight enable delay +SKIP 3 bits ; bits[15:13] +$PowerUpDelay_05 13 bits ; Power up delay +SKIP 3 bits ; bits[31:29] +ALIGN + +SKIP 4 bytes ;address-0x6120C or 0x0C720C (for ILM)-Panel Power off sequencing +$Power_Backlight_Off_Power_Down_Delay_05 13 bits ; Backlight off power down delay +SKIP 3 bits ; bits[15:13] +$PowerDownDelay_05 13 bits ; Power down delay +SKIP 3 bits ; bits[31:29] +ALIGN + +SKIP 4 bytes ;address-0x61210h or 0x0C7210 (for ILM)-Panel power cycle delay and reference divider +$PowerCycleDelay_05 5 bits ; Power Cycle delay +SKIP 3 bits ; bits[5:7] +SKIP 3 bytes + +SKIP 2 bytes ; 2 bytes at the end +SKIP 18 bytes ; DTD +SKIP 10 bytes ; PnP ID + + ; Flat Panel #6 + +$Panel_Width_06 2 bytes ; Panel Width +$Panel_Height_06 2 bytes ; Panel Height +SKIP 4 bytes ;address-0x61180 or 0x0E1180 (for ILM) - Port control +SKIP 3 bytes ; bits[23:0] +SKIP 1 bit ; bit[24] +$Enable_Dither06 1 bit ; Panel #06, 0=No, 1=Yes +SKIP 6 bits ; bits[31:26] +ALIGN + +SKIP 4 bytes ;address-0x61208 or 0x0C7208 (for ILM) - Panel power on sequencing +$Power_On_Backlight_Enable_Delay_06 13 bits ; Power on backlight enable delay +SKIP 3 bits ; bits[15:13] +$PowerUpDelay_06 13 bits ; Power up delay +SKIP 3 bits ; bits[31:29] +ALIGN + +SKIP 4 bytes ;address-0x6120C or 0x0C720C (for ILM)-Panel Power off sequencing +$Power_Backlight_Off_Power_Down_Delay_06 13 bits ; Backlight off power down delay +SKIP 3 bits ; bits[15:13] +$PowerDownDelay_06 13 bits ; Power down delay +SKIP 3 bits ; bits[31:29] +ALIGN + +SKIP 4 bytes ;address-0x61210h or 0x0C7210 (for ILM)-Panel power cycle delay and reference divider +$PowerCycleDelay_06 5 bits ; Power Cycle delay +SKIP 3 bits ; bits[5:7] +SKIP 3 bytes + +SKIP 2 bytes ; 2 bytes at the end +SKIP 18 bytes ; DTD +SKIP 10 bytes ; PnP ID + + ; Flat Panel #7 + +$Panel_Width_07 2 bytes ; Panel Width +$Panel_Height_07 2 bytes ; Panel Height +SKIP 4 bytes ;address-0x61180 or 0x0E1180 (for ILM) - Port control +SKIP 3 bytes ; bits[23:0] +SKIP 1 bit ; bit[24] +$Enable_Dither07 1 bit ; Panel #07, 0=No, 1=Yes +SKIP 6 bits ; bits[31:26] +ALIGN + +SKIP 4 bytes ;address-0x61208 or 0x0C7208 (for ILM) - Panel power on sequencing +$Power_On_Backlight_Enable_Delay_07 13 bits ; Power on Backlight enable delay delay +SKIP 3 bits ; bits[15:13] +$PowerUpDelay_07 13 bits ; Power up delay +SKIP 3 bits ; bits[31:29] +ALIGN + +SKIP 4 bytes ;address-0x6120C or 0x0C720C (for ILM)-Panel Power off sequencing +$Power_Backlight_Off_Power_Down_Delay_07 13 bits ; Backlight off delay power down delay +SKIP 3 bits ; bits[15:13] +$PowerDownDelay_07 13 bits ; Power down delay +SKIP 3 bits ; bits[31:29] +ALIGN + +SKIP 4 bytes ;address-0x61210h or 0x0C7210 (for ILM)-Panel power cycle delay and reference divider +$PowerCycleDelay_07 5 bits ; Power Cycle delay +SKIP 3 bits ; bits[5:7] +SKIP 3 bytes + +SKIP 2 bytes ; 2 bytes at the end +SKIP 18 bytes ; DTD +SKIP 10 bytes ; PnP ID + + ; Flat Panel #8 + +$Panel_Width_08 2 bytes ; Panel Width +$Panel_Height_08 2 bytes ; Panel Height +SKIP 4 bytes ;address-0x61180 or 0x0E1180 (for ILM) - Port control +SKIP 3 bytes ; bits[23:0] +SKIP 1 bit ; bit[24] +$Enable_Dither08 1 bit ; Panel #08, 0=No, 1=Yes +SKIP 6 bits ; bits[31:26] +ALIGN + +SKIP 4 bytes ;address-0x61208 or 0x0C7208 (for ILM) - Panel power on sequencing +$Power_On_Backlight_Enable_Delay_08 13 bits ; Power on backlight enable delay +SKIP 3 bits ; bits[15:13] +$PowerUpDelay_08 13 bits ; Power up delay +SKIP 3 bits ; bits[31:29] +ALIGN + +SKIP 4 bytes ;address-0x6120C or 0x0C720C (for ILM)-Panel Power off sequencing +$Power_Backlight_Off_Power_Down_Delay_08 13 bits ; Backlight off power down delay +SKIP 3 bits ; bits[15:13] +$PowerDownDelay_08 13 bits ; Power down delay +SKIP 3 bits ; bits[31:29] +ALIGN + +SKIP 4 bytes ;address-0x61210h or 0x0C7210 (for ILM)-Panel power cycle delay and reference divider +$PowerCycleDelay_08 5 bits ; Power Cycle delay +SKIP 3 bits ; bits[5:7] +SKIP 3 bytes + +SKIP 2 bytes ; 2 bytes at the end +SKIP 18 bytes ; DTD +SKIP 10 bytes ; PnP ID + + ; Flat Panel #9 + +$Panel_Width_09 2 bytes ; Panel Width +$Panel_Height_09 2 bytes ; Panel Height +SKIP 4 bytes ;address-0x61180 or 0x0E1180 (for ILM) - Port control +SKIP 3 bytes ; bits[23:0] +SKIP 1 bit ; bit[24] +$Enable_Dither09 1 bit ; Panel #09, 0=No, 1=Yes +SKIP 6 bits ; bits[31:26] +ALIGN + +SKIP 4 bytes ;address-0x61208 or 0x0C7208 (for ILM) - Panel power on sequencing +$Power_On_Backlight_Enable_Delay_09 13 bits ; Power on backlight enable delay +SKIP 3 bits ; bits[15:13] +$PowerUpDelay_09 13 bits ; Power up delay +SKIP 3 bits ; bits[31:29] +ALIGN + +SKIP 4 bytes ;address-0x6120C or 0x0C720C (for ILM)-Panel Power off sequencing +$Power_Backlight_Off_Power_Down_Delay_09 13 bits ;Backlight off power down delay +SKIP 3 bits ; bits[15:13] +$PowerDownDelay_09 13 bits ; Power down delay +SKIP 3 bits ; bits[31:29] +ALIGN + +SKIP 4 bytes ;address-0x61210h or 0x0C7210 (for ILM)-Panel power cycle delay and reference divider +$PowerCycleDelay_09 5 bits ; Power Cycle delay +SKIP 3 bits ; bits[5:7] +SKIP 3 bytes + +SKIP 2 bytes ; 2 bytes at the end +SKIP 18 bytes ; DTD +SKIP 10 bytes ; PnP ID + + ; Flat Panel #10 + +$Panel_Width_10 2 bytes ; Panel Width +$Panel_Height_10 2 bytes ; Panel Height +SKIP 4 bytes ;address-0x61180 or 0x0E1180 (for ILM) - Port control +SKIP 3 bytes ; bits[23:0] +SKIP 1 bit ; bit[24] +$Enable_Dither10 1 bit ; Panel #10, 0=No, 1=Yes +SKIP 6 bits ; bits[31:26] +ALIGN + +SKIP 4 bytes ;address-0x61208 or 0x0C7208 (for ILM) - Panel power on sequencing +$Power_On_Backlight_Enable_Delay_10 13 bits ; Power on backlight enable delay +SKIP 3 bits ; bits[15:13] +$PowerUpDelay_10 13 bits ; Power up delay +SKIP 3 bits ; bits[31:29] +ALIGN + +SKIP 4 bytes ;address-0x6120C or 0x0C720C (for ILM)-Panel Power off sequencing +$Power_Backlight_Off_Power_Down_Delay_10 13 bits ;Backlight off power down delay +SKIP 3 bits ; bits[15:13] +$PowerDownDelay_10 13 bits ; Power down delay +SKIP 3 bits ; bits[31:29] +ALIGN + +SKIP 4 bytes ;address-0x61210h or 0x0C7210 (for ILM)-Panel power cycle delay and reference divider +$PowerCycleDelay_10 5 bits ; Power Cycle delay +SKIP 3 bits ; bits[5:7] +SKIP 3 bytes + +SKIP 2 bytes ; 2 bytes at the end +SKIP 18 bytes ; DTD +SKIP 10 bytes ; PnP ID + + ; Flat Panel #11 + +$Panel_Width_11 2 bytes ; Panel Width +$Panel_Height_11 2 bytes ; Panel Height +SKIP 4 bytes ;address-0x61180 or 0x0E1180 (for ILM) - Port control +SKIP 3 bytes ; bits[23:0] +SKIP 1 bit ; bit[24] +$Enable_Dither11 1 bit ; Panel #11, 0=No, 1=Yes +SKIP 6 bits ; bits[31:26] +ALIGN + +SKIP 4 bytes ;address-0x61208 or 0x0C7208 (for ILM) - Panel power on sequencing +$Power_On_Backlight_Enable_Delay_11 13 bits ; Power on backlight enable delay +SKIP 3 bits ; bits[15:13] +$PowerUpDelay_11 13 bits ; Power up delay +SKIP 3 bits ; bits[31:29] +ALIGN + +SKIP 4 bytes ;address-0x6120C or 0x0C720C (for ILM)-Panel Power off sequencing +$Power_Backlight_Off_Power_Down_Delay_11 13 bits ; Backlight off power down delay +SKIP 3 bits ; bits[15:13] +$PowerDownDelay_11 13 bits ; Power down delay +SKIP 3 bits ; bits[31:29] +ALIGN + +SKIP 4 bytes ;address-0x61210h or 0x0C7210 (for ILM)-Panel power cycle delay and reference divider +$PowerCycleDelay_11 5 bits ; Power Cycle delay +SKIP 3 bits ; bits[5:7] +SKIP 3 bytes + +SKIP 2 bytes ; 2 bytes at the end +SKIP 18 bytes ; DTD +SKIP 10 bytes ; PnP ID + + ; Flat Panel #12 + +$Panel_Width_12 2 bytes ; Panel Width +$Panel_Height_12 2 bytes ; Panel Height +SKIP 4 bytes ;address-0x61180 or 0x0E1180 (for ILM) - Port control +SKIP 3 bytes ; bits[23:0] +SKIP 1 bit ; bit[24] +$Enable_Dither12 1 bit ; Panel #12, 0=No, 1=Yes +SKIP 6 bits ; bits[31:26] +ALIGN + +SKIP 4 bytes ;address-0x61208 or 0x0C7208 (for ILM) - Panel power on sequencing +$Power_On_Backlight_Enable_Delay_12 13 bits ; Powen on backlight enable delay +SKIP 3 bits ; bits[15:13] +$PowerUpDelay_12 13 bits ; Power up delay +SKIP 3 bits ; bits[31:29] +ALIGN + +SKIP 4 bytes ;address-0x6120C or 0x0C720C (for ILM)-Panel Power off sequencing +$Power_Backlight_Off_Power_Down_Delay_12 13 bits ; Backlight off power down delay +SKIP 3 bits ; bits[15:13] +$PowerDownDelay_12 13 bits ; Power down delay +SKIP 3 bits ; bits[31:29] +ALIGN + +SKIP 4 bytes ;address-0x61210h or 0x0C7210 (for ILM)-Panel power cycle delay and reference divider +$PowerCycleDelay_12 5 bits ; Power Cycle delay +SKIP 3 bits ; bits[5:7] +SKIP 3 bytes + +SKIP 2 bytes ; 2 bytes at the end +SKIP 18 bytes ; DTD +SKIP 10 bytes ; PnP ID + + ; Flat Panel #13 + +$Panel_Width_13 2 bytes ; Panel Width +$Panel_Height_13 2 bytes ; Panel Height +SKIP 4 bytes ;address-0x61180 or 0x0E1180 (for ILM) - Port control +SKIP 3 bytes ; bits[23:0] +SKIP 1 bit ; bit[24] +$Enable_Dither13 1 bit ; Panel #13, 0=No, 1=Yes +SKIP 6 bits ; bits[31:26] +ALIGN + +SKIP 4 bytes ;address-0x61208 or 0x0C7208 (for ILM) - Panel power on sequencing +$Power_On_Backlight_Enable_Delay_13 13 bits ; Power on backlight enable delay +SKIP 3 bits ; bits[15:13] +$PowerUpDelay_13 13 bits ; Power up delay +SKIP 3 bits ; bits[31:29] +ALIGN + +SKIP 4 bytes ;address-0x6120C or 0x0C720C (for ILM)-Panel Power off sequencing +$Power_Backlight_Off_Power_Down_Delay_13 13 bits ;Backlight off power down delay +SKIP 3 bits ; bits[15:13] +$PowerDownDelay_13 13 bits ; Power down delay +SKIP 3 bits ; bits[31:29] +ALIGN + +SKIP 4 bytes ;address-0x61210h or 0x0C7210 (for ILM)-Panel power cycle delay and reference divider +$PowerCycleDelay_13 5 bits ; Power Cycle delay +SKIP 3 bits ; bits[5:7] +SKIP 3 bytes + +SKIP 2 bytes ; 2 bytes at the end +SKIP 18 bytes ; DTD +SKIP 10 bytes ; PnP ID + + ; Flat Panel #14 + +$Panel_Width_14 2 bytes ; Panel Width +$Panel_Height_14 2 bytes ; Panel Height +SKIP 4 bytes ;address-0x61180 or 0x0E1180 (for ILM) - Port control +SKIP 3 bytes ; bits[23:0] +SKIP 1 bit ; bit[24] +$Enable_Dither14 1 bit ; Panel #14, 0=No, 1=Yes +SKIP 6 bits ; bits[31:26] +ALIGN + +SKIP 4 bytes ;address-0x61208 or 0x0C7208 (for ILM) - Panel power on sequencing +$Power_On_Backlight_Enable_Delay_14 13 bits ; Power on baklight enable delay +SKIP 3 bits ; bits[15:13] +$PowerUpDelay_14 13 bits ; Power up delay +SKIP 3 bits ; bits[31:29] +ALIGN + +SKIP 4 bytes ;address-0x6120C or 0x0C720C (for ILM)-Panel Power off sequencing +$Power_Backlight_Off_Power_Down_Delay_14 13 bits ;Backlight off power down delay +SKIP 3 bits ; bits[15:13] +$PowerDownDelay_14 13 bits ; Power down delay +SKIP 3 bits ; bits[31:29] +ALIGN + +SKIP 4 bytes ;address-0x61210h or 0x0C7210 (for ILM)-Panel power cycle delay and reference divider +$PowerCycleDelay_14 5 bits ; Power Cycle delay +SKIP 3 bits ; bits[5:7] +SKIP 3 bytes + +SKIP 2 bytes ; 2 bytes at the end +SKIP 18 bytes ; DTD +SKIP 10 bytes ; PnP ID + + ; Flat Panel #15 + +$Panel_Width_15 2 bytes ; Panel Width +$Panel_Height_15 2 bytes ; Panel Height +SKIP 4 bytes ;address-0x61180 or 0x0E1180 (for ILM) - Port control +SKIP 3 bytes ; bits[23:0] +SKIP 1 bit ; bit[24] +$Enable_Dither15 1 bit ; Panel #15, 0=No, 1=Yes +SKIP 6 bits ; bits[31:26] +ALIGN + +SKIP 4 bytes ;address-0x61208 or 0x0C7208 (for ILM) - Panel power on sequencing +$Power_On_Backlight_Enable_Delay_15 13 bits ; Power on backlight enable delay +SKIP 3 bits ; bits[15:13] +$PowerUpDelay_15 13 bits ; Power up delay +SKIP 3 bits ; bits[31:29] +ALIGN + +SKIP 4 bytes ;address-0x6120C or 0x0C720C (for ILM)-Panel Power off sequencing +$Power_Backlight_Off_Power_Down_Delay_15 13 bits ; Backlight off power down delay +SKIP 3 bits ; bits[15:13] +$PowerDownDelay_15 13 bits ; Power down delay +SKIP 3 bits ; bits[31:29] +ALIGN + +SKIP 4 bytes ;address-0x61210h or 0x0C7210 (for ILM)-Panel power cycle delay and reference divider +$PowerCycleDelay_15 5 bits ; Power Cycle delay +SKIP 3 bits ; bits[5:7] +SKIP 3 bytes + +SKIP 2 bytes ; 2 bytes at the end +SKIP 18 bytes ; DTD +SKIP 10 bytes ; PnP ID + + ; Flat Panel #16 + +$Panel_Width_16 2 bytes ; Panel Width +$Panel_Height_16 2 bytes ; Panel Height +SKIP 4 bytes ;address-0x61180 or 0x0E1180 (for ILM) - Port control +SKIP 3 bytes ; bits[23:0] +SKIP 1 bit ; bit[24] +$Enable_Dither16 1 bit ; Panel #16, 0=No, 1=Yes +SKIP 6 bits ; bits[31:26] +ALIGN + +SKIP 4 bytes ;address-0x61208 or 0x0C7208 (for ILM) - Panel power on sequencing +$Power_On_Backlight_Enable_Delay_16 13 bits ; Power on backlight enable delay +SKIP 3 bits ; bits[15:13] +$PowerUpDelay_16 13 bits ; Power up delay +SKIP 3 bits ; bits[31:29] +ALIGN + +SKIP 4 bytes ;address-0x6120C or 0x0C720C (for ILM)-Panel Power off sequencing +$Power_Backlight_Off_Power_Down_Delay_16 13 bits ; backlight off power down delay +SKIP 3 bits ; bits[15:13] +$PowerDownDelay_16 13 bits ; Power down delay +SKIP 3 bits ; bits[31:29] +ALIGN + +SKIP 4 bytes ;address-0x61210h or 0x0C7210 (for ILM)-Panel power cycle delay and reference divider +$PowerCycleDelay_16 5 bits ; Power cycle delay +SKIP 3 bits ; bits[5:7] +SKIP 3 bytes + +SKIP 2 bytes ; 2 bytes at the end +SKIP 18 bytes ; DTD +SKIP 10 bytes ; PnP ID + +$Panel_Name_01 13 bytes ; LFP Panel Name +$Panel_Name_02 13 bytes ; LFP Panel Name +$Panel_Name_03 13 bytes ; LFP Panel Name +$Panel_Name_04 13 bytes ; LFP Panel Name +$Panel_Name_05 13 bytes ; LFP Panel Name +$Panel_Name_06 13 bytes ; LFP Panel Name +$Panel_Name_07 13 bytes ; LFP Panel Name +$Panel_Name_08 13 bytes ; LFP Panel Name +$Panel_Name_09 13 bytes ; LFP Panel Name +$Panel_Name_10 13 bytes ; LFP Panel Name +$Panel_Name_11 13 bytes ; LFP Panel Name +$Panel_Name_12 13 bytes ; LFP Panel Name +$Panel_Name_13 13 bytes ; LFP Panel Name +$Panel_Name_14 13 bytes ; LFP Panel Name +$Panel_Name_15 13 bytes ; LFP Panel Name +$Panel_Name_16 13 bytes ; LFP Panel Name + +$Enable_Scaling_01 1 bit ; Scaling Enable bit for Panel#1 +$Enable_Scaling_02 1 bit ; Scaling Enable bit for Panel#2 +$Enable_Scaling_03 1 bit ; Scaling Enable bit for Panel#3 +$Enable_Scaling_04 1 bit ; Scaling Enable bit for Panel#4 +$Enable_Scaling_05 1 bit ; Scaling Enable bit for Panel#5 +$Enable_Scaling_06 1 bit ; Scaling Enable bit for Panel#6 +$Enable_Scaling_07 1 bit ; Scaling Enable bit for Panel#7 +$Enable_Scaling_08 1 bit ; Scaling Enable bit for Panel#8 +$Enable_Scaling_09 1 bit ; Scaling Enable bit for Panel#9 +$Enable_Scaling_10 1 bit ; Scaling Enable bit for Panel#10 +$Enable_Scaling_11 1 bit ; Scaling Enable bit for Panel#11 +$Enable_Scaling_12 1 bit ; Scaling Enable bit for Panel#12 +$Enable_Scaling_13 1 bit ; Scaling Enable bit for Panel#13 +$Enable_Scaling_14 1 bit ; Scaling Enable bit for Panel#14 +$Enable_Scaling_15 1 bit ; Scaling Enable bit for Panel#15 +$Enable_Scaling_16 1 bit ; Scaling Enable bit for Panel#16 + +$Seamless_DRRS_Min_RR_01 1 byte ; Seamless DRRS Min Refresh Rate for Panel#1 +$Seamless_DRRS_Min_RR_02 1 byte ; Seamless DRRS Min Refresh Rate for Panel#2 +$Seamless_DRRS_Min_RR_03 1 byte ; Seamless DRRS Min Refresh Rate for Panel#3 +$Seamless_DRRS_Min_RR_04 1 byte ; Seamless DRRS Min Refresh Rate for Panel#4 +$Seamless_DRRS_Min_RR_05 1 byte ; Seamless DRRS Min Refresh Rate for Panel#5 +$Seamless_DRRS_Min_RR_06 1 byte ; Seamless DRRS Min Refresh Rate for Panel#6 +$Seamless_DRRS_Min_RR_07 1 byte ; Seamless DRRS Min Refresh Rate for Panel#7 +$Seamless_DRRS_Min_RR_08 1 byte ; Seamless DRRS Min Refresh Rate for Panel#8 +$Seamless_DRRS_Min_RR_09 1 byte ; Seamless DRRS Min Refresh Rate for Panel#9 +$Seamless_DRRS_Min_RR_10 1 byte ; Seamless DRRS Min Refresh Rate for Panel#10 +$Seamless_DRRS_Min_RR_11 1 byte ; Seamless DRRS Min Refresh Rate for Panel#11 +$Seamless_DRRS_Min_RR_12 1 byte ; Seamless DRRS Min Refresh Rate for Panel#12 +$Seamless_DRRS_Min_RR_13 1 byte ; Seamless DRRS Min Refresh Rate for Panel#13 +$Seamless_DRRS_Min_RR_14 1 byte ; Seamless DRRS Min Refresh Rate for Panel#14 +$Seamless_DRRS_Min_RR_15 1 byte ; Seamless DRRS Min Refresh Rate for Panel#15 +$Seamless_DRRS_Min_RR_16 1 byte ; Seamless DRRS Min Refresh Rate for Panel#16 + + +;============================================================================== +; Block 43 - BLC (Backlight Control) Support +;------------------------------------------------------------------------------ + +SKIP 3 bytes ; Skip block ID and size +SKIP 1 byte ; Skip row size + + ; Flat Panel #1 +$BLC_Inv_Type_1 2 bits ; BLC inverter type +$BLC_Inv_Polarity_1 1 bit ; BLC inverter polarity +$BLC_GPIO_Pins_1 3 bits ; BLC inverter GPIO Pins +$BLC_GMBus_Speed_1 2 bits ; BLC inverter GMBus speed +$PWM_Frequency_1 2 bytes ; PWM inverter frequency +$BLC_Min_Brightness_1 1 byte ; Minimum Brightness, 0 - 255 +$BLC_I2C_Addr_1 1 byte ; I2C inverter Slave address +$BLC_Brightness_Cmd_1 1 byte ; I2C inverter command code + + + ; Flat Panel #2 +$BLC_Inv_Type_2 2 bits ; BLC inverter type +$BLC_Inv_Polarity_2 1 bit ; BLC inverter polarity +$BLC_GPIO_Pins_2 3 bits ; BLC inverter GPIO Pins +$BLC_GMBus_Speed_2 2 bits ; BLC inverter GMBus speed +$PWM_Frequency_2 2 bytes ; PWM inverter frequency +$BLC_Min_Brightness_2 1 byte ; Minimum Brightness, 0 - 255 +$BLC_I2C_Addr_2 1 byte ; I2C inverter Slave address +$BLC_Brightness_Cmd_2 1 byte ; I2C inverter command code + + ; Flat Panel #3 +$BLC_Inv_Type_3 2 bits ; BLC inverter type +$BLC_Inv_Polarity_3 1 bit ; BLC inverter polarity +$BLC_GPIO_Pins_3 3 bits ; BLC inverter GPIO Pins +$BLC_GMBus_Speed_3 2 bits ; BLC inverter GMBus speed +$PWM_Frequency_3 2 bytes ; PWM inverter frequency +$BLC_Min_Brightness_3 1 byte ; Minimum Brightness, 0 - 255 +$BLC_I2C_Addr_3 1 byte ; I2C inverter Slave address +$BLC_Brightness_Cmd_3 1 byte ; I2C inverter command code + + + ; Flat Panel #4 +$BLC_Inv_Type_4 2 bits ; BLC inverter type +$BLC_Inv_Polarity_4 1 bit ; BLC inverter polarity +$BLC_GPIO_Pins_4 3 bits ; BLC inverter GPIO Pins +$BLC_GMBus_Speed_4 2 bits ; BLC inverter GMBus speed +$PWM_Frequency_4 2 bytes ; PWM inverter frequency +$BLC_Min_Brightness_4 1 byte ; Minimum Brightness, 0 - 255 +$BLC_I2C_Addr_4 1 byte ; I2C inverter Slave address +$BLC_Brightness_Cmd_4 1 byte ; I2C inverter command code + + ; Flat Panel #5 +$BLC_Inv_Type_5 2 bits ; BLC inverter type +$BLC_Inv_Polarity_5 1 bit ; BLC inverter polarity +$BLC_GPIO_Pins_5 3 bits ; BLC inverter GPIO Pins +$BLC_GMBus_Speed_5 2 bits ; BLC inverter GMBus speed +$PWM_Frequency_5 2 bytes ; PWM inverter frequency +$BLC_Min_Brightness_5 1 byte ; Minimum Brightness, 0 - 255 +$BLC_I2C_Addr_5 1 byte ; I2C inverter Slave address +$BLC_Brightness_Cmd_5 1 byte ; I2C inverter command code + + + ; Flat Panel #6 +$BLC_Inv_Type_6 2 bits ; BLC inverter type +$BLC_Inv_Polarity_6 1 bit ; BLC inverter polarity +$BLC_GPIO_Pins_6 3 bits ; BLC inverter GPIO Pins +$BLC_GMBus_Speed_6 2 bits ; BLC inverter GMBus speed +$PWM_Frequency_6 2 bytes ; PWM inverter frequency +$BLC_Min_Brightness_6 1 byte ; Minimum Brightness, 0 - 255 +$BLC_I2C_Addr_6 1 byte ; I2C inverter Slave address +$BLC_Brightness_Cmd_6 1 byte ; I2C inverter command code + + ; Flat Panel #7 +$BLC_Inv_Type_7 2 bits ; BLC inverter type +$BLC_Inv_Polarity_7 1 bit ; BLC inverter polarity +$BLC_GPIO_Pins_7 3 bits ; BLC inverter GPIO Pins +$BLC_GMBus_Speed_7 2 bits ; BLC inverter GMBus speed +$PWM_Frequency_7 2 bytes ; PWM inverter frequency +$BLC_Min_Brightness_7 1 byte ; Minimum Brightness, 0 - 255 +$BLC_I2C_Addr_7 1 byte ; I2C inverter Slave address +$BLC_Brightness_Cmd_7 1 byte ; I2C inverter command code + + + ; Flat Panel #8 +$BLC_Inv_Type_8 2 bits ; BLC inverter type +$BLC_Inv_Polarity_8 1 bit ; BLC inverter polarity +$BLC_GPIO_Pins_8 3 bits ; BLC inverter GPIO Pins +$BLC_GMBus_Speed_8 2 bits ; BLC inverter GMBus speed +$PWM_Frequency_8 2 bytes ; PWM inverter frequency +$BLC_Min_Brightness_8 1 byte ; Minimum Brightness, 0 - 255 +$BLC_I2C_Addr_8 1 byte ; I2C inverter Slave address +$BLC_Brightness_Cmd_8 1 byte ; I2C inverter command code + + + ; Flat Panel #9 +$BLC_Inv_Type_9 2 bits ; BLC inverter type +$BLC_Inv_Polarity_9 1 bit ; BLC inverter polarity +$BLC_GPIO_Pins_9 3 bits ; BLC inverter GPIO Pins +$BLC_GMBus_Speed_9 2 bits ; BLC inverter GMBus speed +$PWM_Frequency_9 2 bytes ; PWM inverter frequency +$BLC_Min_Brightness_9 1 byte ; Minimum Brightness, 0 - 255 +$BLC_I2C_Addr_9 1 byte ; I2C inverter Slave address +$BLC_Brightness_Cmd_9 1 byte ; I2C inverter command code + + ; Flat Panel #10 +$BLC_Inv_Type_10 2 bits ; BLC inverter type +$BLC_Inv_Polarity_10 1 bit ; BLC inverter polarity +$BLC_GPIO_Pins_10 3 bits ; BLC inverter GPIO Pins +$BLC_GMBus_Speed_10 2 bits ; BLC inverter GMBus speed +$PWM_Frequency_10 2 bytes ; PWM inverter frequency +$BLC_Min_Brightness_10 1 byte ; Minimum Brightness, 0 - 255 +$BLC_I2C_Addr_10 1 byte ; I2C inverter Slave address +$BLC_Brightness_Cmd_10 1 byte ; I2C inverter command code + + + ; Flat Panel #11 +$BLC_Inv_Type_11 2 bits ; BLC inverter type +$BLC_Inv_Polarity_11 1 bit ; BLC inverter polarity +$BLC_GPIO_Pins_11 3 bits ; BLC inverter GPIO Pins +$BLC_GMBus_Speed_11 2 bits ; BLC inverter GMBus speed +$PWM_Frequency_11 2 bytes ; PWM inverter frequency +$BLC_Min_Brightness_11 1 byte ; Minimum Brightness, 0 - 255 +$BLC_I2C_Addr_11 1 byte ; I2C inverter Slave address +$BLC_Brightness_Cmd_11 1 byte ; I2C inverter command code + + + ; Flat Panel #12 +$BLC_Inv_Type_12 2 bits ; BLC inverter type +$BLC_Inv_Polarity_12 1 bit ; BLC inverter polarity +$BLC_GPIO_Pins_12 3 bits ; BLC inverter GPIO Pins +$BLC_GMBus_Speed_12 2 bits ; BLC inverter GMBus speed +$PWM_Frequency_12 2 bytes ; PWM inverter frequency +$BLC_Min_Brightness_12 1 byte ; Minimum Brightness, 0 - 255 +$BLC_I2C_Addr_12 1 byte ; I2C inverter Slave address +$BLC_Brightness_Cmd_12 1 byte ; I2C inverter command code + + ; Flat Panel #13 +$BLC_Inv_Type_13 2 bits ; BLC inverter type +$BLC_Inv_Polarity_13 1 bit ; BLC inverter polarity +$BLC_GPIO_Pins_13 3 bits ; BLC inverter GPIO Pins +$BLC_GMBus_Speed_13 2 bits ; BLC inverter GMBus speed +$PWM_Frequency_13 2 bytes ; PWM inverter frequency +$BLC_Min_Brightness_13 1 byte ; Minimum Brightness, 0 - 255 +$BLC_I2C_Addr_13 1 byte ; I2C inverter Slave address +$BLC_Brightness_Cmd_13 1 byte ; I2C inverter command code + + + ; Flat Panel #14 +$BLC_Inv_Type_14 2 bits ; BLC inverter type +$BLC_Inv_Polarity_14 1 bit ; BLC inverter polarity +$BLC_GPIO_Pins_14 3 bits ; BLC inverter GPIO Pins +$BLC_GMBus_Speed_14 2 bits ; BLC inverter GMBus speed +$PWM_Frequency_14 2 bytes ; PWM inverter frequency +$BLC_Min_Brightness_14 1 byte ; Minimum Brightness, 0 - 255 +$BLC_I2C_Addr_14 1 byte ; I2C inverter Slave address +$BLC_Brightness_Cmd_14 1 byte ; I2C inverter command code + + + ; Flat Panel #15 +$BLC_Inv_Type_15 2 bits ; BLC inverter type +$BLC_Inv_Polarity_15 1 bit ; BLC inverter polarity +$BLC_GPIO_Pins_15 3 bits ; BLC inverter GPIO Pins +$BLC_GMBus_Speed_15 2 bits ; BLC inverter GMBus speed +$PWM_Frequency_15 2 bytes ; PWM inverter frequency +$BLC_Min_Brightness_15 1 byte ; Minimum Brightness, 0 - 255 +$BLC_I2C_Addr_15 1 byte ; I2C inverter Slave address +$BLC_Brightness_Cmd_15 1 byte ; I2C inverter command code + + + ; Flat Panel #16 +$BLC_Inv_Type_16 2 bits ; BLC inverter type +$BLC_Inv_Polarity_16 1 bit ; BLC inverter polarity +$BLC_GPIO_Pins_16 3 bits ; BLC inverter GPIO Pins +$BLC_GMBus_Speed_16 2 bits ; BLC inverter GMBus speed +$PWM_Frequency_16 2 bytes ; PWM inverter frequency +$BLC_Min_Brightness_16 1 byte ; Minimum Brightness, 0 - 255 +$BLC_I2C_Addr_16 1 byte ; I2C inverter Slave address +$BLC_Brightness_Cmd_16 1 byte ; I2C inverter command code + +$POST_BL_Brightness_01 1 byte ; Intial brightness value at POST for Flat Panel #1 + $POST_BL_Brightness_02 1 byte ; Intial brightness value at POST for Flat Panel #2 + $POST_BL_Brightness_03 1 byte ; Intial brightness value at POST for Flat Panel #3 + $POST_BL_Brightness_04 1 byte ; Intial brightness value at POST for Flat Panel #4 + $POST_BL_Brightness_05 1 byte ; Intial brightness value at POST for Flat Panel #5 + $POST_BL_Brightness_06 1 byte ; Intial brightness value at POST for Flat Panel #6 + $POST_BL_Brightness_07 1 byte ; Intial brightness value at POST for Flat Panel #7 + $POST_BL_Brightness_08 1 byte ; Intial brightness value at POST for Flat Panel #8 + $POST_BL_Brightness_09 1 byte ; Intial brightness value at POST for Flat Panel #9 + $POST_BL_Brightness_10 1 byte ; Intial brightness value at POST for Flat Panel #10 + $POST_BL_Brightness_11 1 byte ; Intial brightness value at POST for Flat Panel #11 + $POST_BL_Brightness_12 1 byte ; Intial brightness value at POST for Flat Panel #12 + $POST_BL_Brightness_13 1 byte ; Intial brightness value at POST for Flat Panel #13 + $POST_BL_Brightness_14 1 byte ; Intial brightness value at POST for Flat Panel #14 + $POST_BL_Brightness_15 1 byte ; Intial brightness value at POST for Flat Panel #15 + $POST_BL_Brightness_16 1 byte ; Intial brightness value at POST for Flat Panel #16 + + $Lfp_Pwm_Source_Selection_01 4 bits ; Pwm Source Selection for Panel #1 + $Lfp_Pwm_Controller_Selection_01 4 bits ; Pwm Controller Selection for Panel #1 + + $Lfp_Pwm_Source_Selection_02 4 bits ; Pwm Source Selection for Panel #2 + $Lfp_Pwm_Controller_Selection_02 4 bits ; Pwm Controller Selection for Panel #2 + + $Lfp_Pwm_Source_Selection_03 4 bits ; Pwm Source Selection for Panel #3 + $Lfp_Pwm_Controller_Selection_03 4 bits ; Pwm Controller Selection for Panel #3 + + $Lfp_Pwm_Source_Selection_04 4 bits ; Pwm Source Selection for Panel #4 + $Lfp_Pwm_Controller_Selection_04 4 bits ; Pwm Controller Selection for Panel #4 + + $Lfp_Pwm_Source_Selection_05 4 bits ; Pwm Source Selection for Panel #5 + $Lfp_Pwm_Controller_Selection_05 4 bits ; Pwm Controller Selection for Panel #5 + + $Lfp_Pwm_Source_Selection_06 4 bits ; Pwm Source Selection for Panel #6 + $Lfp_Pwm_Controller_Selection_06 4 bits ; Pwm Controller Selection for Panel #6 + + $Lfp_Pwm_Source_Selection_07 4 bits ; Pwm Source Selection for Panel #7 + $Lfp_Pwm_Controller_Selection_07 4 bits ; Pwm Controller Selection for Panel #7 + + $Lfp_Pwm_Source_Selection_08 4 bits ; Pwm Source Selection for Panel #8 + $Lfp_Pwm_Controller_Selection_08 4 bits ; Pwm Controller Selection for Panel #8 + + $Lfp_Pwm_Source_Selection_09 4 bits ; Pwm Source Selection for Panel #9 + $Lfp_Pwm_Controller_Selection_09 4 bits ; Pwm Controller Selection for Panel #9 + + $Lfp_Pwm_Source_Selection_10 4 bits ; Pwm Source Selection for Panel #10 + $Lfp_Pwm_Controller_Selection_10 4 bits ; Pwm Controller Selection for Panel #10 + + $Lfp_Pwm_Source_Selection_11 4 bits ; Pwm Source Selection for Panel #11 + $Lfp_Pwm_Controller_Selection_11 4 bits ; Pwm Controller Selection for Panel #11 + + $Lfp_Pwm_Source_Selection_12 4 bits ; Pwm Source Selection for Panel #12 + $Lfp_Pwm_Controller_Selection_12 4 bits ; Pwm Controller Selection for Panel #12 + + $Lfp_Pwm_Source_Selection_13 4 bits ; Pwm Source Selection for Panel #13 + $Lfp_Pwm_Controller_Selection_13 4 bits ; Pwm Controller Selection for Panel #13 + + $Lfp_Pwm_Source_Selection_14 4 bits ; Pwm Source Selection for Panel #14 + $Lfp_Pwm_Controller_Selection_14 4 bits ; Pwm Controller Selection for Panel #14 + + $Lfp_Pwm_Source_Selection_15 4 bits ; Pwm Source Selection for Panel #15 + $Lfp_Pwm_Controller_Selection_15 4 bits ; Pwm Controller Selection for Panel #15 + + $Lfp_Pwm_Source_Selection_16 4 bits ; Pwm Source Selection for Panel #16 + $Lfp_Pwm_Controller_Selection_16 4 bits ; Pwm Controller Selection for Panel #16 + +;============================================================================== +; Block 44 - BIA (Backlight Image Adaption) Support +;------------------------------------------------------------------------------ + +SKIP 3 bytes ; Skip block ID and size + +$BIA_Enable 1 bit ; DPST support enable bit +$BIA_Aggress_Level 3 bits ; Power Conservation Preference level +SKIP 3 bits ; Reserved +$ALS_Enable 1 bit ; ALS enable bit +$ALS_Response_Data 20 bytes ; ALS Response Data + + ;============================================================================== + ; Block 46 - Chromaticity Support + ;------------------------------------------------------------------------------ + + SKIP 3 bytes ; Skip block ID and size + + + $Chromacity_Enable_1 1 bit ; enable or disable the chromacity bit + $Override_EDID_Data_1 1 bit ; Override the chromaticity bit + SKIP 6 bits ; Reserved bits + $Red_Green_1 1 byte ; Red/green chormaticity coordinates at 19h + $Blue_White_1 1 byte ; Blue/white chromatiity coordinates at 1Ah + $Red_x_1 1 byte ; Red x coordinate at 1Bh + $Red_y_1 1 byte ; Red y coordinate at 1Ch + $Green_x_1 1 byte ; Green x coordinate at 1Dh + $Green_y_1 1 byte ; Green y ccoordinate at 1Eh + $Blue_x_1 1 byte ; Blue x coordinate at 1Fh + $Blue_y_1 1 byte ; Blue y coordinate at 20h + $White_x_1 1 byte ; White x coordiante at 21h + $White_y_1 1 byte ; White y coordinate at 22h + + $Chromacity_Enable_2 1 bit ; enable or disable the chromacity bit + $Override_EDID_Data_2 1 bit ; Override the chromaticity bit + SKIP 6 bits ; Reserved bits + $Red_Green_2 1 byte ; Red/green chormaticity coordinates at 19h + $Blue_White_2 1 byte ; Blue/white chromatiity coordinates at 1Ah + $Red_x_2 1 byte ; Red x coordinate at 1Bh + $Red_y_2 1 byte ; Red y coordinate at 1Ch + $Green_x_2 1 byte ; Green x coordinate at 1Dh + $Green_y_2 1 byte ; Green y ccoordinate at 1Eh + $Blue_x_2 1 byte ; Blue x coordinate at 1Fh + $Blue_y_2 1 byte ; Blue y coordinate at 20h + $White_x_2 1 byte ; White x coordiante at 21h + $White_y_2 1 byte ; White y coordinate at 22h + + $Chromacity_Enable_3 1 bit ; enable or disable the chromacity bit + $Override_EDID_Data_3 1 bit ; Override the chromaticity bit + SKIP 6 bits ; Reserved bits + $Red_Green_3 1 byte ; Red/green chormaticity coordinates at 19h + $Blue_White_3 1 byte ; Blue/white chromatiity coordinates at 1Ah + $Red_x_3 1 byte ; Red x coordinate at 1Bh + $Red_y_3 1 byte ; Red y coordinate at 1Ch + $Green_x_3 1 byte ; Green x coordinate at 1Dh + $Green_y_3 1 byte ; Green y ccoordinate at 1Eh + $Blue_x_3 1 byte ; Blue x coordinate at 1Fh + $Blue_y_3 1 byte ; Blue y coordinate at 20h + $White_x_3 1 byte ; White x coordiante at 21h + $White_y_3 1 byte ; White y coordinate at 22h + + $Chromacity_Enable_4 1 bit ; enable or disable the chromacity bit + $Override_EDID_Data_4 1 bit ; Override the chromaticity bit + SKIP 6 bits ; Reserved bits + $Red_Green_4 1 byte ; Red/green chormaticity coordinates at 19h + $Blue_White_4 1 byte ; Blue/white chromatiity coordinates at 1Ah + $Red_x_4 1 byte ; Red x coordinate at 1Bh + $Red_y_4 1 byte ; Red y coordinate at 1Ch + $Green_x_4 1 byte ; Green x coordinate at 1Dh + $Green_y_4 1 byte ; Green y ccoordinate at 1Eh + $Blue_x_4 1 byte ; Blue x coordinate at 1Fh + $Blue_y_4 1 byte ; Blue y coordinate at 20h + $White_x_4 1 byte ; White x coordiante at 21h + $White_y_4 1 byte ; White y coordinate at 22h + + $Chromacity_Enable_5 1 bit ; enable or disable the chromacity bit + $Override_EDID_Data_5 1 bit ; Override the chromaticity bit + SKIP 6 bits ; Reserved bits + $Red_Green_5 1 byte ; Red/green chormaticity coordinates at 19h + $Blue_White_5 1 byte ; Blue/white chromatiity coordinates at 1Ah + $Red_x_5 1 byte ; Red x coordinate at 1Bh + $Red_y_5 1 byte ; Red y coordinate at 1Ch + $Green_x_5 1 byte ; Green x coordinate at 1Dh + $Green_y_5 1 byte ; Green y ccoordinate at 1Eh + $Blue_x_5 1 byte ; Blue x coordinate at 1Fh + $Blue_y_5 1 byte ; Blue y coordinate at 20h + $White_x_5 1 byte ; White x coordiante at 21h + $White_y_5 1 byte ; White y coordinate at 22h + + $Chromacity_Enable_6 1 bit ; enable or disable the chromacity bit + $Override_EDID_Data_6 1 bit ; Override the chromaticity bit + SKIP 6 bits ; Reserved bits + $Red_Green_6 1 byte ; Red/green chormaticity coordinates at 19h + $Blue_White_6 1 byte ; Blue/white chromatiity coordinates at 1Ah + $Red_x_6 1 byte ; Red x coordinate at 1Bh + $Red_y_6 1 byte ; Red y coordinate at 1Ch + $Green_x_6 1 byte ; Green x coordinate at 1Dh + $Green_y_6 1 byte ; Green y ccoordinate at 1Eh + $Blue_x_6 1 byte ; Blue x coordinate at 1Fh + $Blue_y_6 1 byte ; Blue y coordinate at 20h + $White_x_6 1 byte ; White x coordiante at 21h + $White_y_6 1 byte ; White y coordinate at 22h + + $Chromacity_Enable_7 1 bit ; enable or disable the chromacity bit + $Override_EDID_Data_7 1 bit ; Override the chromaticity bit + SKIP 6 bits ; Reserved bits + $Red_Green_7 1 byte ; Red/green chormaticity coordinates at 19h + $Blue_White_7 1 byte ; Blue/white chromatiity coordinates at 1Ah + $Red_x_7 1 byte ; Red x coordinate at 1Bh + $Red_y_7 1 byte ; Red y coordinate at 1Ch + $Green_x_7 1 byte ; Green x coordinate at 1Dh + $Green_y_7 1 byte ; Green y ccoordinate at 1Eh + $Blue_x_7 1 byte ; Blue x coordinate at 1Fh + $Blue_y_7 1 byte ; Blue y coordinate at 20h + $White_x_7 1 byte ; White x coordiante at 21h + $White_y_7 1 byte ; White y coordinate at 22h + + $Chromacity_Enable_8 1 bit ; enable or disable the chromacity bit + $Override_EDID_Data_8 1 bit ; Override the chromaticity bit + SKIP 6 bits ; Reserved bits + $Red_Green_8 1 byte ; Red/green chormaticity coordinates at 19h + $Blue_White_8 1 byte ; Blue/white chromatiity coordinates at 1Ah + $Red_x_8 1 byte ; Red x coordinate at 1Bh + $Red_y_8 1 byte ; Red y coordinate at 1Ch + $Green_x_8 1 byte ; Green x coordinate at 1Dh + $Green_y_8 1 byte ; Green y ccoordinate at 1Eh + $Blue_x_8 1 byte ; Blue x coordinate at 1Fh + $Blue_y_8 1 byte ; Blue y coordinate at 20h + $White_x_8 1 byte ; White x coordiante at 21h + $White_y_8 1 byte ; White y coordinate at 22h + + $Chromacity_Enable_9 1 bit ; enable or disable the chromacity bit + $Override_EDID_Data_9 1 bit ; Override the chromaticity bit + SKIP 6 bits ; Reserved bits + $Red_Green_9 1 byte ; Red/green chormaticity coordinates at 19h + $Blue_White_9 1 byte ; Blue/white chromatiity coordinates at 1Ah + $Red_x_9 1 byte ; Red x coordinate at 1Bh + $Red_y_9 1 byte ; Red y coordinate at 1Ch + $Green_x_9 1 byte ; Green x coordinate at 1Dh + $Green_y_9 1 byte ; Green y ccoordinate at 1Eh + $Blue_x_9 1 byte ; Blue x coordinate at 1Fh + $Blue_y_9 1 byte ; Blue y coordinate at 20h + $White_x_9 1 byte ; White x coordiante at 21h + $White_y_9 1 byte ; White y coordinate at 22h + + $Chromacity_Enable_10 1 bit ; enable or disable the chromacity bit + $Override_EDID_Data_10 1 bit ; Override the chromaticity bit + SKIP 6 bits ; Reserved bits + $Red_Green_10 1 byte ; Red/green chormaticity coordinates at 19h + $Blue_White_10 1 byte ; Blue/white chromatiity coordinates at 1Ah + $Red_x_10 1 byte ; Red x coordinate at 1Bh + $Red_y_10 1 byte ; Red y coordinate at 1Ch + $Green_x_10 1 byte ; Green x coordinate at 1Dh + $Green_y_10 1 byte ; Green y ccoordinate at 1Eh + $Blue_x_10 1 byte ; Blue x coordinate at 1Fh + $Blue_y_10 1 byte ; Blue y coordinate at 20h + $White_x_10 1 byte ; White x coordiante at 21h + $White_y_10 1 byte ; White y coordinate at 22h + + $Chromacity_Enable_11 1 bit ; enable or disable the chromacity bit + $Override_EDID_Data_11 1 bit ; Override the chromaticity bit + SKIP 6 bits ; Reserved bits + $Red_Green_11 1 byte ; Red/green chormaticity coordinates at 19h + $Blue_White_11 1 byte ; Blue/white chromatiity coordinates at 1Ah + $Red_x_11 1 byte ; Red x coordinate at 1Bh + $Red_y_11 1 byte ; Red y coordinate at 1Ch + $Green_x_11 1 byte ; Green x coordinate at 1Dh + $Green_y_11 1 byte ; Green y ccoordinate at 1Eh + $Blue_x_11 1 byte ; Blue x coordinate at 1Fh + $Blue_y_11 1 byte ; Blue y coordinate at 20h + $White_x_11 1 byte ; White x coordiante at 21h + $White_y_11 1 byte ; White y coordinate at 22h + + $Chromacity_Enable_12 1 bit ; enable or disable the chromacity bit + $Override_EDID_Data_12 1 bit ; Override the chromaticity bit + SKIP 6 bits ; Reserved bits + $Red_Green_12 1 byte ; Red/green chormaticity coordinates at 19h + $Blue_White_12 1 byte ; Blue/white chromatiity coordinates at 1Ah + $Red_x_12 1 byte ; Red x coordinate at 1Bh + $Red_y_12 1 byte ; Red y coordinate at 1Ch + $Green_x_12 1 byte ; Green x coordinate at 1Dh + $Green_y_12 1 byte ; Green y ccoordinate at 1Eh + $Blue_x_12 1 byte ; Blue x coordinate at 1Fh + $Blue_y_12 1 byte ; Blue y coordinate at 20h + $White_x_12 1 byte ; White x coordiante at 21h + $White_y_12 1 byte ; White y coordinate at 22h + + $Chromacity_Enable_13 1 bit ; enable or disable the chromacity bit + $Override_EDID_Data_13 1 bit ; Override the chromaticity bit + SKIP 6 bits ; Reserved bits + $Red_Green_13 1 byte ; Red/green chormaticity coordinates at 19h + $Blue_White_13 1 byte ; Blue/white chromatiity coordinates at 1Ah + $Red_x_13 1 byte ; Red x coordinate at 1Bh + $Red_y_13 1 byte ; Red y coordinate at 1Ch + $Green_x_13 1 byte ; Green x coordinate at 1Dh + $Green_y_13 1 byte ; Green y ccoordinate at 1Eh + $Blue_x_13 1 byte ; Blue x coordinate at 1Fh + $Blue_y_13 1 byte ; Blue y coordinate at 20h + $White_x_13 1 byte ; White x coordiante at 21h + $White_y_13 1 byte ; White y coordinate at 22h + + $Chromacity_Enable_14 1 bit ; enable or disable the chromacity bit + $Override_EDID_Data_14 1 bit ; Override the chromaticity bit + SKIP 6 bits ; Reserved bits + $Red_Green_14 1 byte ; Red/green chormaticity coordinates at 19h + $Blue_White_14 1 byte ; Blue/white chromatiity coordinates at 1Ah + $Red_x_14 1 byte ; Red x coordinate at 1Bh + $Red_y_14 1 byte ; Red y coordinate at 1Ch + $Green_x_14 1 byte ; Green x coordinate at 1Dh + $Green_y_14 1 byte ; Green y ccoordinate at 1Eh + $Blue_x_14 1 byte ; Blue x coordinate at 1Fh + $Blue_y_14 1 byte ; Blue y coordinate at 20h + $White_x_14 1 byte ; White x coordiante at 21h + $White_y_14 1 byte ; White y coordinate at 22h + + $Chromacity_Enable_15 1 bit ; enable or disable the chromacity bit + $Override_EDID_Data_15 1 bit ; Override the chromaticity bit + SKIP 6 bits ; Reserved bits + $Red_Green_15 1 byte ; Red/green chormaticity coordinates at 19h + $Blue_White_15 1 byte ; Blue/white chromatiity coordinates at 1Ah + $Red_x_15 1 byte ; Red x coordinate at 1Bh + $Red_y_15 1 byte ; Red y coordinate at 1Ch + $Green_x_15 1 byte ; Green x coordinate at 1Dh + $Green_y_15 1 byte ; Green y ccoordinate at 1Eh + $Blue_x_15 1 byte ; Blue x coordinate at 1Fh + $Blue_y_15 1 byte ; Blue y coordinate at 20h + $White_x_15 1 byte ; White x coordiante at 21h + $White_y_15 1 byte ; White y coordinate at 22h + + + $Chromacity_Enable_16 1 bit ; enable or disable the chromacity bit + $Override_EDID_Data_16 1 bit ; Override the chromaticity bit + SKIP 6 bits ; Reserved bits + $Red_Green_16 1 byte ; Red/green chormaticity coordinates at 19h + $Blue_White_16 1 byte ; Blue/white chromatiity coordinates at 1Ah + $Red_x_16 1 byte ; Red x coordinate at 1Bh + $Red_y_16 1 byte ; Red y coordinate at 1Ch + $Green_x_16 1 byte ; Green x coordinate at 1Dh + $Green_y_16 1 byte ; Green y ccoordinate at 1Eh + $Blue_x_16 1 byte ; Blue x coordinate at 1Fh + $Blue_y_16 1 byte ; Blue y coordinate at 20h + $White_x_16 1 byte ; White x coordiante at 21h + $White_y_16 1 byte ; White y coordinate at 22h + +;============================================================================== +; Block 51 - Fixed Mode +;------------------------------------------------------------------------------ + +SKIP 3 bytes ; Skip block ID and size +$Feature_Enable 1 byte ; enable or disable the feature +$X_res 4 bytes ; X resolution +$Y_res 4 bytes ; Y resolution + +;============================================================================== +; Block 52 - MIPI DSI Configuration Block +;----------------------------------------------------------------------------- + +$MIPI_DSI_CONF_BLOCKID 1 byte +$MIPI_DSI_CONF_BLOCKSIZE 2 bytes + + ;MIPI DSI CONF Panel#1 +$PanelIdentifier_1 2 bytes ;PanelIdentifier + +$Dithering_1 1 bit ;GeneralMIPIParams +SKIP 1 bit +$Panel_Type_1 1 bit +$MIPI_DSI_Panel_Architecture_Type_1 2 bits +$Video_Command_Mode_1 1 bit +$Packet_Sequence_Video_Mode_1 2 bits +$CABC_Support_1 1 bit +$PmicSocSelection_1 1 bit +$Colour_Format_Video_Mode_1 4 bits +$Panel_Rotation_1 2 bits +$Bta_Disable_1 1 bit +SKIP 15 bits + +$Dual_Link_1 2 bits ;PortDesc +$Number_Of_Lanes_1 2 bits +$Pixel_Overlap_Count_1 3 bits +$RGBFlip_1 1 bit +SKIP 8 bits + +SKIP 16 bits ;DsiControllerParams +SKIP 8 bits ;Reserved0 +$RequiredBurstModeRate_1 32 bits ;RequiredBurstModeRate + +$DsiDDRClock_1 4 bytes ;DsiDDRClock + +SKIP 32 bits ;BridgeRefClock + +$EscapeClk_1 2 bits ;EscapeClk +SKIP 6 bits + +$DPhyParamFlag_1 1 bit ;DphyFlags +$EoTpSupport_1 1 bit ;EoTpSupport +$ClockStop_1 1 bit +SKIP 13 bits + +$HsTxTimeOut_1 4 bytes ;HsTxTimeOut +$LpRxTimeOut_1 4 bytes ;LpRxTimeOut +$TurnAroundTimeOut_1 4 bytes ;TurnAroundTimeOut +$DeviceResetTimer_1 4 bytes ;DeviceResetTimer +$MasterInitTimer_1 4 bytes ;MasterInitTimer +$DbiBwTimer_1 32 bits ;DbiBwTimer + +$LpByteClkRegValue_1 32 bits ;LpByteClkRegValue +$DphyParamRegValue_1 32 bits ;DphyParamRegValue +$ClkLaneSwitchingTimeCount_1 32 bits ;ClkLaneSwitchingTimeCount +$HighLowSwitchCount_1 32 bits ;HighLowSwitchCount + +SKIP 32 bits ;Reserved1 +SKIP 32 bits ;Reserved2 +SKIP 32 bits ;Reserved3 +SKIP 32 bits ;Reserved4 +SKIP 32 bits ;Reserved5 +SKIP 32 bits ;Reserved6 + +SKIP 8 bits ;TClkMiss +SKIP 8 bits ;TClkPost +SKIP 8 bits ;Reserved7 +SKIP 8 bits ;TClkPre +$TClkPrepare_1 1 byte ;TClkPrepare +SKIP 8 bits ;TClkSettle +SKIP 8 bits ;TClkTermEn +$TClkTrail_1 1 byte ;TClkTrail +$TClkPrepareTClkZero_1 2 bytes ;TClkPrepareTClkZero +SKIP 8 bits ;Reserved8 +SKIP 8 bits ;TDTermEn +SKIP 8 bits ;TEot +SKIP 8 bits ;THsExit +$THsPrepare_1 1 byte ;THsPrepare +$THsPrepareTHsZero_1 2 bytes ;THsPrepareTHsZero +SKIP 8 bits ;Reserved9 +SKIP 8 bits ;THsSettle +SKIP 8 bits ;THsSkip +$THsTrail_1 8 bits ;THsTrail +SKIP 8 bits ;TInit +SKIP 8 bits ;TLpx +SKIP 8 bits ;Reserved10 +SKIP 16 bits ;Reserved11 + +$PanelEnable_1 1 bit ;PanelEnable +SKIP 7 bits +$BkltEnable_1 1 bit ;BkltEnable +SKIP 7 bits +$PWMEnable_1 1 bit ;PWMEnable +SKIP 7 bits +$RstRN_1 1 bit ;RstRN +SKIP 7 bits +$PwrDownR_1 1 bit ;PwrDownR +SKIP 7 bits +$StbyRN_1 1 bit ;StbyRN +SKIP 7 bits + + ;MIPI DSI CONF Panel#2 +$PanelIdentifier_2 2 bytes ;PanelIdentifier + +$Dithering_2 1 bit ;GeneralMIPIParams +SKIP 1 bit +$Panel_Type_2 1 bit +$MIPI_DSI_Panel_Architecture_Type_2 2 bits +$Video_Command_Mode_2 1 bit +$Packet_Sequence_Video_Mode_2 2 bits +$CABC_Support_2 1 bit +$PmicSocSelection_2 1 bit +$Colour_Format_Video_Mode_2 4 bits +$Panel_Rotation_2 2 bits +$Bta_Disable_2 1 bit +SKIP 15 bits + +$Dual_Link_2 2 bits ;PortDesc +$Number_Of_Lanes_2 2 bits +$Pixel_Overlap_Count_2 3 bits +$RGBFlip_2 1 bit +SKIP 8 bits + +SKIP 16 bits ;DsiControllerParams +SKIP 8 bits ;Reserved0 +$RequiredBurstModeRate_2 32 bits ;RequiredBurstModeRate + +$DsiDDRClock_2 4 bytes ;DsiDDRClock + +SKIP 32 bits ;BridgeRefClock + +$EscapeClk_2 2 bits ;EscapeClk +SKIP 6 bits + +$DPhyParamFlag_2 1 bit ;DphyFlags +$EoTpSupport_2 1 bit ;EoTpSupport +$ClockStop_2 1 bit +SKIP 13 bits + +$HsTxTimeOut_2 4 bytes ;HsTxTimeOut +$LpRxTimeOut_2 4 bytes ;LpRxTimeOut +$TurnAroundTimeOut_2 4 bytes ;TurnAroundTimeOut +$DeviceResetTimer_2 4 bytes ;DeviceResetTimer +$MasterInitTimer_2 4 bytes ;MasterInitTimer +$DbiBwTimer_2 32 bits ;DbiBwTimer + +$LpByteClkRegValue_2 32 bits ;LpByteClkRegValue +$DphyParamRegValue_2 32 bits ;DphyParamRegValue +$ClkLaneSwitchingTimeCount_2 32 bits ;ClkLaneSwitchingTimeCount +$HighLowSwitchCount_2 32 bits ;HighLowSwitchCount + +SKIP 32 bits ;Reserved1 +SKIP 32 bits ;Reserved2 +SKIP 32 bits ;Reserved3 +SKIP 32 bits ;Reserved4 +SKIP 32 bits ;Reserved5 +SKIP 32 bits ;Reserved6 + +SKIP 8 bits ;TClkMiss +SKIP 8 bits ;TClkPost +SKIP 8 bits ;Reserved7 +SKIP 8 bits ;TClkPre +$TClkPrepare_2 1 byte ;TClkPrepare +SKIP 8 bits ;TClkSettle +SKIP 8 bits ;TClkTermEn +$TClkTrail_2 1 byte ;TClkTrail +$TClkPrepareTClkZero_2 2 bytes ;TClkPrepareTClkZero +SKIP 8 bits ;Reserved8 +SKIP 8 bits ;TDTermEn +SKIP 8 bits ;TEot +SKIP 8 bits ;THsExit +$THsPrepare_2 1 byte ;THsPrepare +$THsPrepareTHsZero_2 2 bytes ;THsPrepareTHsZero +SKIP 8 bits ;Reserved9 +SKIP 8 bits ;THsSettle +SKIP 8 bits ;THsSkip +$THsTrail_2 8 bits ;THsTrail +SKIP 8 bits ;TInit +SKIP 8 bits ;TLpx +SKIP 8 bits ;Reserved10 +SKIP 16 bits ;Reserved11 + +$PanelEnable_2 1 bit ;PanelEnable +SKIP 7 bits +$BkltEnable_2 1 bit ;BkltEnable +SKIP 7 bits +$PWMEnable_2 1 bit ;PWMEnable +SKIP 7 bits +$RstRN_2 1 bit ;RstRN +SKIP 7 bits +$PwrDownR_2 1 bit ;PwrDownR +SKIP 7 bits +$StbyRN_2 1 bit ;StbyRN +SKIP 7 bits + + ;MIPI DSI CONF Panel#3 +$PanelIdentifier_3 2 bytes ;PanelIdentifier + +$Dithering_3 1 bit ;GeneralMIPIParams +SKIP 1 bit +$Panel_Type_3 1 bit +$MIPI_DSI_Panel_Architecture_Type_3 2 bits +$Video_Command_Mode_3 1 bit +$Packet_Sequence_Video_Mode_3 2 bits +$CABC_Support_3 1 bit +$PmicSocSelection_3 1 bit +$Colour_Format_Video_Mode_3 4 bits +$Panel_Rotation_3 2 bits +$Bta_Disable_3 1 bit +SKIP 15 bits + +$Dual_Link_3 2 bits ;PortDesc +$Number_Of_Lanes_3 2 bits +$Pixel_Overlap_Count_3 3 bits +$RGBFlip_3 1 bit +SKIP 8 bits + +SKIP 16 bits ;DsiControllerParams +SKIP 8 bits ;Reserved0 +$RequiredBurstModeRate_3 32 bits ;RequiredBurstModeRate + +$DsiDDRClock_3 4 bytes ;DsiDDRClock + +SKIP 32 bits ;BridgeRefClock + +$EscapeClk_3 2 bits ;EscapeClk +SKIP 6 bits + +$DPhyParamFlag_3 1 bit ;DphyFlags +$EoTpSupport_3 1 bit ;EoTpSupport +$ClockStop_3 1 bit +SKIP 13 bits + +$HsTxTimeOut_3 4 bytes ;HsTxTimeOut +$LpRxTimeOut_3 4 bytes ;LpRxTimeOut +$TurnAroundTimeOut_3 4 bytes ;TurnAroundTimeOut +$DeviceResetTimer_3 4 bytes ;DeviceResetTimer +$MasterInitTimer_3 4 bytes ;MasterInitTimer +$DbiBwTimer_3 32 bits ;DbiBwTimer + +$LpByteClkRegValue_3 32 bits ;LpByteClkRegValue +$DphyParamRegValue_3 32 bits ;DphyParamRegValue +$ClkLaneSwitchingTimeCount_3 32 bits ;ClkLaneSwitchingTimeCount +$HighLowSwitchCount_3 32 bits ;HighLowSwitchCount + +SKIP 32 bits ;Reserved1 +SKIP 32 bits ;Reserved2 +SKIP 32 bits ;Reserved3 +SKIP 32 bits ;Reserved4 +SKIP 32 bits ;Reserved5 +SKIP 32 bits ;Reserved6 + +SKIP 8 bits ;TClkMiss +SKIP 8 bits ;TClkPost +SKIP 8 bits ;Reserved7 +SKIP 8 bits ;TClkPre +$TClkPrepare_3 1 byte ;TClkPrepare +SKIP 8 bits ;TClkSettle +SKIP 8 bits ;TClkTermEn +$TClkTrail_3 1 byte ;TClkTrail +$TClkPrepareTClkZero_3 2 bytes ;TClkPrepareTClkZero +SKIP 8 bits ;Reserved8 +SKIP 8 bits ;TDTermEn +SKIP 8 bits ;TEot +SKIP 8 bits ;THsExit +$THsPrepare_3 1 byte ;THsPrepare +$THsPrepareTHsZero_3 2 bytes ;THsPrepareTHsZero +SKIP 8 bits ;Reserved9 +SKIP 8 bits ;THsSettle +SKIP 8 bits ;THsSkip +$THsTrail_3 8 bits ;THsTrail +SKIP 8 bits ;TInit +SKIP 8 bits ;TLpx +SKIP 8 bits ;Reserved10 +SKIP 16 bits ;Reserved11 + +$PanelEnable_3 1 bit ;PanelEnable +SKIP 7 bits +$BkltEnable_3 1 bit ;BkltEnable +SKIP 7 bits +$PWMEnable_3 1 bit ;PWMEnable +SKIP 7 bits +$RstRN_3 1 bit ;RstRN +SKIP 7 bits +$PwrDownR_3 1 bit ;PwrDownR +SKIP 7 bits +$StbyRN_3 1 bit ;StbyRN +SKIP 7 bits + + ;MIPI DSI CONF Panel#4 +$PanelIdentifier_4 2 bytes ;PanelIdentifier + +$Dithering_4 1 bit ;GeneralMIPIParams +SKIP 1 bit +$Panel_Type_4 1 bit +$MIPI_DSI_Panel_Architecture_Type_4 2 bits +$Video_Command_Mode_4 1 bit +$Packet_Sequence_Video_Mode_4 2 bits +$CABC_Support_4 1 bit +$PmicSocSelection_4 1 bit +$Colour_Format_Video_Mode_4 4 bits +$Panel_Rotation_4 2 bits +$Bta_Disable_4 1 bit +SKIP 15 bits + +$Dual_Link_4 2 bits ;PortDesc +$Number_Of_Lanes_4 2 bits +$Pixel_Overlap_Count_4 3 bits +$RGBFlip_4 1 bit +SKIP 8 bits + +SKIP 16 bits ;DsiControllerParams +SKIP 8 bits ;Reserved0 +$RequiredBurstModeRate_4 32 bits ;RequiredBurstModeRate + +$DsiDDRClock_4 4 bytes ;DsiDDRClock + +SKIP 32 bits ;BridgeRefClock + +$EscapeClk_4 2 bits ;EscapeClk +SKIP 6 bits + +$DPhyParamFlag_4 1 bit ;DphyFlags +$EoTpSupport_4 1 bit ;EoTpSupport +$ClockStop_4 1 bit +SKIP 13 bits + +$HsTxTimeOut_4 4 bytes ;HsTxTimeOut +$LpRxTimeOut_4 4 bytes ;LpRxTimeOut +$TurnAroundTimeOut_4 4 bytes ;TurnAroundTimeOut +$DeviceResetTimer_4 4 bytes ;DeviceResetTimer +$MasterInitTimer_4 4 bytes ;MasterInitTimer +$DbiBwTimer_4 32 bits ;DbiBwTimer + +$LpByteClkRegValue_4 32 bits ;LpByteClkRegValue +$DphyParamRegValue_4 32 bits ;DphyParamRegValue +$ClkLaneSwitchingTimeCount_4 32 bits ;ClkLaneSwitchingTimeCount +$HighLowSwitchCount_4 32 bits ;HighLowSwitchCount + +SKIP 32 bits ;Reserved1 +SKIP 32 bits ;Reserved2 +SKIP 32 bits ;Reserved3 +SKIP 32 bits ;Reserved4 +SKIP 32 bits ;Reserved5 +SKIP 32 bits ;Reserved6 + +SKIP 8 bits ;TClkMiss +SKIP 8 bits ;TClkPost +SKIP 8 bits ;Reserved7 +SKIP 8 bits ;TClkPre +$TClkPrepare_4 1 byte ;TClkPrepare +SKIP 8 bits ;TClkSettle +SKIP 8 bits ;TClkTermEn +$TClkTrail_4 1 byte ;TClkTrail +$TClkPrepareTClkZero_4 2 bytes ;TClkPrepareTClkZero +SKIP 8 bits ;Reserved8 +SKIP 8 bits ;TDTermEn +SKIP 8 bits ;TEot +SKIP 8 bits ;THsExit +$THsPrepare_4 1 byte ;THsPrepare +$THsPrepareTHsZero_4 2 bytes ;THsPrepareTHsZero +SKIP 8 bits ;Reserved9 +SKIP 8 bits ;THsSettle +SKIP 8 bits ;THsSkip +$THsTrail_4 8 bits ;THsTrail +SKIP 8 bits ;TInit +SKIP 8 bits ;TLpx +SKIP 8 bits ;Reserved10 +SKIP 16 bits ;Reserved11 + +$PanelEnable_4 1 bit ;PanelEnable +SKIP 7 bits +$BkltEnable_4 1 bit ;BkltEnable +SKIP 7 bits +$PWMEnable_4 1 bit ;PWMEnable +SKIP 7 bits +$RstRN_4 1 bit ;RstRN +SKIP 7 bits +$PwrDownR_4 1 bit ;PwrDownR +SKIP 7 bits +$StbyRN_4 1 bit ;StbyRN +SKIP 7 bits + + ;MIPI DSI CONF Panel#5 +$PanelIdentifier_5 2 bytes ;PanelIdentifier + +$Dithering_5 1 bit ;GeneralMIPIParams +SKIP 1 bit +$Panel_Type_5 1 bit +$MIPI_DSI_Panel_Architecture_Type_5 2 bits +$Video_Command_Mode_5 1 bit +$Packet_Sequence_Video_Mode_5 2 bits +$CABC_Support_5 1 bit +$PmicSocSelection_5 1 bit +$Colour_Format_Video_Mode_5 4 bits +$Panel_Rotation_5 2 bits +$Bta_Disable_5 1 bit +SKIP 15 bits + +$Dual_Link_5 2 bits ;PortDesc +$Number_Of_Lanes_5 2 bits +$Pixel_Overlap_Count_5 3 bits +$RGBFlip_5 1 bit +SKIP 8 bits + +SKIP 16 bits ;DsiControllerParams +SKIP 8 bits ;Reserved0 +$RequiredBurstModeRate_5 32 bits ;RequiredBurstModeRate + +$DsiDDRClock_5 4 bytes ;DsiDDRClock + +SKIP 32 bits ;BridgeRefClock + +$EscapeClk_5 2 bits ;EscapeClk +SKIP 6 bits + +$DPhyParamFlag_5 1 bit ;DphyFlags +$EoTpSupport_5 1 bit ;EoTpSupport +$ClockStop_5 1 bit +SKIP 13 bits + +$HsTxTimeOut_5 4 bytes ;HsTxTimeOut +$LpRxTimeOut_5 4 bytes ;LpRxTimeOut +$TurnAroundTimeOut_5 4 bytes ;TurnAroundTimeOut +$DeviceResetTimer_5 4 bytes ;DeviceResetTimer +$MasterInitTimer_5 4 bytes ;MasterInitTimer +$DbiBwTimer_5 32 bits ;DbiBwTimer + +$LpByteClkRegValue_5 32 bits ;LpByteClkRegValue +$DphyParamRegValue_5 32 bits ;DphyParamRegValue +$ClkLaneSwitchingTimeCount_5 32 bits ;ClkLaneSwitchingTimeCount +$HighLowSwitchCount_5 32 bits ;HighLowSwitchCount + +SKIP 32 bits ;Reserved1 +SKIP 32 bits ;Reserved2 +SKIP 32 bits ;Reserved3 +SKIP 32 bits ;Reserved4 +SKIP 32 bits ;Reserved5 +SKIP 32 bits ;Reserved6 + +SKIP 8 bits ;TClkMiss +SKIP 8 bits ;TClkPost +SKIP 8 bits ;Reserved7 +SKIP 8 bits ;TClkPre +$TClkPrepare_5 1 byte ;TClkPrepare +SKIP 8 bits ;TClkSettle +SKIP 8 bits ;TClkTermEn +$TClkTrail_5 1 byte ;TClkTrail +$TClkPrepareTClkZero_5 2 bytes ;TClkPrepareTClkZero +SKIP 8 bits ;Reserved8 +SKIP 8 bits ;TDTermEn +SKIP 8 bits ;TEot +SKIP 8 bits ;THsExit +$THsPrepare_5 1 byte ;THsPrepare +$THsPrepareTHsZero_5 2 bytes ;THsPrepareTHsZero +SKIP 8 bits ;Reserved9 +SKIP 8 bits ;THsSettle +SKIP 8 bits ;THsSkip +$THsTrail_5 8 bits ;THsTrail +SKIP 8 bits ;TInit +SKIP 8 bits ;TLpx +SKIP 8 bits ;Reserved10 +SKIP 16 bits ;Reserved11 + +$PanelEnable_5 1 bit ;PanelEnable +SKIP 7 bits +$BkltEnable_5 1 bit ;BkltEnable +SKIP 7 bits +$PWMEnable_5 1 bit ;PWMEnable +SKIP 7 bits +$RstRN_5 1 bit ;RstRN +SKIP 7 bits +$PwrDownR_5 1 bit ;PwrDownR +SKIP 7 bits +$StbyRN_5 1 bit ;StbyRN +SKIP 7 bits + + ;MIPI DSI CONF Panel#6 +$PanelIdentifier_6 2 bytes ;PanelIdentifier + +$Dithering_6 1 bit ;GeneralMIPIParams +SKIP 1 bit +$Panel_Type_6 1 bit +$MIPI_DSI_Panel_Architecture_Type_6 2 bits +$Video_Command_Mode_6 1 bit +$Packet_Sequence_Video_Mode_6 2 bits +$CABC_Support_6 1 bit +$PmicSocSelection_6 1 bit +$Colour_Format_Video_Mode_6 4 bits +$Panel_Rotation_6 2 bits +$Bta_Disable_6 1 bit +SKIP 15 bits + +$Dual_Link_6 2 bits ;PortDesc +$Number_Of_Lanes_6 2 bits +$Pixel_Overlap_Count_6 3 bits +$RGBFlip_6 1 bit +SKIP 8 bits + +SKIP 16 bits ;DsiControllerParams +SKIP 8 bits ;Reserved0 +$RequiredBurstModeRate_6 32 bits ;RequiredBurstModeRate + +$DsiDDRClock_6 4 bytes ;DsiDDRClock + +SKIP 32 bits ;BridgeRefClock + +$EscapeClk_6 2 bits ;EscapeClk +SKIP 6 bits + +$DPhyParamFlag_6 1 bit ;DphyFlags +$EoTpSupport_6 1 bit ;EoTpSupport +$ClockStop_6 1 bit +SKIP 13 bits + +$HsTxTimeOut_6 4 bytes ;HsTxTimeOut +$LpRxTimeOut_6 4 bytes ;LpRxTimeOut +$TurnAroundTimeOut_6 4 bytes ;TurnAroundTimeOut +$DeviceResetTimer_6 4 bytes ;DeviceResetTimer +$MasterInitTimer_6 4 bytes ;MasterInitTimer +$DbiBwTimer_6 32 bits ;DbiBwTimer + +$LpByteClkRegValue_6 32 bits ;LpByteClkRegValue +$DphyParamRegValue_6 32 bits ;DphyParamRegValue +$ClkLaneSwitchingTimeCount_6 32 bits ;ClkLaneSwitchingTimeCount +$HighLowSwitchCount_6 32 bits ;HighLowSwitchCount + +SKIP 32 bits ;Reserved1 +SKIP 32 bits ;Reserved2 +SKIP 32 bits ;Reserved3 +SKIP 32 bits ;Reserved4 +SKIP 32 bits ;Reserved5 +SKIP 32 bits ;Reserved6 + +SKIP 8 bits ;TClkMiss +SKIP 8 bits ;TClkPost +SKIP 8 bits ;Reserved7 +SKIP 8 bits ;TClkPre +$TClkPrepare_6 1 byte ;TClkPrepare +SKIP 8 bits ;TClkSettle +SKIP 8 bits ;TClkTermEn +$TClkTrail_6 1 byte ;TClkTrail +$TClkPrepareTClkZero_6 2 bytes ;TClkPrepareTClkZero +SKIP 8 bits ;Reserved8 +SKIP 8 bits ;TDTermEn +SKIP 8 bits ;TEot +SKIP 8 bits ;THsExit +$THsPrepare_6 1 byte ;THsPrepare +$THsPrepareTHsZero_6 2 bytes ;THsPrepareTHsZero +SKIP 8 bits ;Reserved9 +SKIP 8 bits ;THsSettle +SKIP 8 bits ;THsSkip +$THsTrail_6 8 bits ;THsTrail +SKIP 8 bits ;TInit +SKIP 8 bits ;TLpx +SKIP 8 bits ;Reserved10 +SKIP 16 bits ;Reserved11 + +$PanelEnable_6 1 bit ;PanelEnable +SKIP 7 bits +$BkltEnable_6 1 bit ;BkltEnable +SKIP 7 bits +$PWMEnable_6 1 bit ;PWMEnable +SKIP 7 bits +$RstRN_6 1 bit ;RstRN +SKIP 7 bits +$PwrDownR_6 1 bit ;PwrDownR +SKIP 7 bits +$StbyRN_6 1 bit ;StbyRN +SKIP 7 bits + + ; MIPI DSI PPS for Panel#1 +$PowerUpDelay_1 16 bits +$DataTurnOnToPanelBacklightEnableDelay_1 16 bits +$BacklightOffToDataTurnOffDelay_1 16 bits +$PowerDownDelay_1 16 bits +$PowerCycleDelay_1 16 bits + + ; MIPI DSI PPS for Panel#2 +$PowerUpDelay_2 16 bits +$DataTurnOnToPanelBacklightEnableDelay_2 16 bits +$BacklightOffToDataTurnOffDelay_2 16 bits +$PowerDownDelay_2 16 bits +$PowerCycleDelay_2 16 bits + + ; MIPI DSI PPS for Panel#3 +$PowerUpDelay_3 16 bits +$DataTurnOnToPanelBacklightEnableDelay_3 16 bits +$BacklightOffToDataTurnOffDelay_3 16 bits +$PowerDownDelay_3 16 bits +$PowerCycleDelay_3 16 bits + + ; MIPI DSI PPS for Panel#4 +$PowerUpDelay_4 16 bits +$DataTurnOnToPanelBacklightEnableDelay_4 16 bits +$BacklightOffToDataTurnOffDelay_4 16 bits +$PowerDownDelay_4 16 bits +$PowerCycleDelay_4 16 bits + + ; MIPI DSI PPS for Panel#5 +$PowerUpDelay_5 16 bits +$DataTurnOnToPanelBacklightEnableDelay_5 16 bits +$BacklightOffToDataTurnOffDelay_5 16 bits +$PowerDownDelay_5 16 bits +$PowerCycleDelay_5 16 bits + + ; MIPI DSI PPS for Panel#6 +$PowerUpDelay_6 16 bits +$DataTurnOnToPanelBacklightEnableDelay_6 16 bits +$BacklightOffToDataTurnOffDelay_6 16 bits +$PowerDownDelay_6 16 bits +$PowerCycleDelay_6 16 bits + +$Mipi_PwmOn_To_Bklt_Enable_Delay_01 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#1 +$Mipi_Bklt_Disable_To_PwmOff_Delay_01 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#1 + +$Mipi_PwmOn_To_Bklt_Enable_Delay_02 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#2 +$Mipi_Bklt_Disable_To_PwmOff_Delay_02 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#2 + +$Mipi_PwmOn_To_Bklt_Enable_Delay_03 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#3 +$Mipi_Bklt_Disable_To_PwmOff_Delay_03 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#3 + +$Mipi_PwmOn_To_Bklt_Enable_Delay_04 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#4 +$Mipi_Bklt_Disable_To_PwmOff_Delay_04 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#4 + +$Mipi_PwmOn_To_Bklt_Enable_Delay_05 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#5 +$Mipi_Bklt_Disable_To_PwmOff_Delay_05 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#5 + +$Mipi_PwmOn_To_Bklt_Enable_Delay_06 2 bytes ; Delay from Pwm On to Backlight Enable for Panel#6 +$Mipi_Bklt_Disable_To_PwmOff_Delay_06 2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#6 + +$Mipi_PmicI2cBusNo_1 1 byte +$Mipi_PmicI2cBusNo_2 1 byte +$Mipi_PmicI2cBusNo_3 1 byte +$Mipi_PmicI2cBusNo_4 1 byte +$Mipi_PmicI2cBusNo_5 1 byte +$Mipi_PmicI2cBusNo_6 1 byte + +EndStruct + + +;============================================================================== +; List Definitions +;------------------------------------------------------------------------------ + +List &Disabled_Enabled_List + Selection 0, "Disabled" + Selection 1, "Enabled" +EndList + +List &Pwr_Pref_List + Selection 0x01, "1 - Maximum Quality with No DPST" + Selection 0x02, "2" + Selection 0x03, "3" + Selection 0x04, "4" + Selection 0x05, "5" + Selection 0x06, "6 - Maximum Battery" +EndList + +List &Cls_After_Signon_List + Selection 0x00, "No CLS" + Selection 0x01, "0.5 Second Delay + CLS" + Selection 0x02, "1.0 Second Delay + CLS" + Selection 0x03, "1.5 Second Delay + CLS" + Selection 0x04, "2.0 Second Delay + CLS" + Selection 0x05, "2.5 Second Delay + CLS" + Selection 0x06, "3.0 Second Delay + CLS" + Selection 0x07, "3.5 Second Delay + CLS" +EndList + +List &Int_CRT_Device_Type_List + Selection 0x0000, "No Device" + Selection 0x0001, "CRT" + ;Selection 0x0011, "DVI with CRT" +EndList + +List &Int_EFP_Device_Type_List + Selection 0x0000, "No Device" + Selection 0x68C6, "DisplayPort" + Selection 0x60D2, "HDMI/DVI" + Selection 0x68D2, "Integrated DVI Only" + Selection 0x60D6, "DisplayPort with HDMI/DVI Compatible" + Selection 0x68D6, "DisplayPort with DVI Compatible" + ; Selection 0x68D3, "DVI with CRT" +EndList + +List &CRT_Device_Id_List + Selection 01h, "CRT" +EndList + +List &EFP1_Device_Id_List + Selection 04h, "EFP 1" + Selection 40h, "EFP 2" + Selection 08h, "LFP" + ;Selection 80h, "LFP 2" +EndList + +List &EFP2_Device_Id_List + Selection 04h, "EFP 1" + Selection 40h, "EFP 2" + Selection 08h, "LFP" + ;Selection 80h, "LFP 2" +EndList + +List &LVDS_Device_Id_List + Selection 08h, "LFP" +EndList + +List &DOS_Boot_Mode_List + Selection 0x03, "03h" + Selection 0x12, "12h" + Selection 0x13, "13h" + Selection 0x30, "30h" + Selection 0x32, "32h" + Selection 0x34, "34h" + Selection 0x40, "40h" + Selection 0x41, "41h" + Selection 0x42, "42h" + Selection 0x43, "43h" + Selection 0x44, "44h" + Selection 0x45, "45h" + Selection 0x50, "50h" + Selection 0x52, "52h" + Selection 0x54, "54h" +EndList + +List &LFP_Port_List + Selection 0x07, "eDP Port B" + Selection 0x08, "eDP Port C" + ; Selection 0x15, "MIPI Port A" + ;Selection 0x17, "MIPI Port C" + +EndList + +List &LVDS_eDP_Port_List + Selection 0x04, "LVDS" + Selection 0x07, "Port B" + Selection 0x08, "Port C" +EndList + + + +List &Int_EFP_Port_List + Selection 0x00, "N/A" + Selection 0x01, "Port B" + Selection 0x02, "Port C" + Selection 0x03, "Port D" + +EndList + +List &Int_eDP_AUX_Channel_List + Selection 0x00, "N/A" + Selection 0x10, "eDP-B AUX Channel" + Selection 0x20, "eDP-C AUX Channel" +EndList + +List &Int_DP_AUX_Channel_List + Selection 0x00, "N/A" + Selection 0x10, "DisplayPort-B AUX Channel" + Selection 0x20, "DisplayPort-C AUX Channel" + Selection 0x30, "DisplayPort-D AUX Channel" +EndList + +List &GPIO_Pin_List + Selection 0x00, "N/A" + Selection 0x05, "Integrated HDMI-B DDC GPIO Pins" + Selection 0x04, "Integrated HDMI-C DDC GPIO Pins" + Selection 0x03, "Integrated HDMI-D DDC GPIO Pins" ; as mentioned in CHV Bspec + Selection 0x01, "I2C GPIO pins" +; Selection 0x02, "Analog CRT DDC GPIO pins" +EndList + + +List &GMBus_Speed_List + Selection 0x01, "50 KHz" + Selection 0x00, "100 KHz" + Selection 0x02, "400 KHz" + Selection 0x03, "1 MHz" +EndList + + +List &Inv_Type_List + Selection 0x00, "None/External" + Selection 0x01, "I2C" + Selection 0x02, "PWM" +EndList + +List &Inv_Polarity_List + Selection 0x00, "Normal" + Selection 0x01, "Inverted" +EndList + +List &IntXXh_List + Selection 0x00, "Disabled" + Selection 0x01, "Use Interrupt 15h" +EndList + +List &LVDS_Channel_List + Selection 0x00, "Single Channel" + Selection 0x01, "Dual Channel" +EndList + +List &INT_LVDS_Channel_List + Selection 0x00, "Automatic Selection" + Selection 0x01, "Single Channel" + Selection 0x02, "Dual Channel" +EndList + +List &LVDS_Config_List + Selection 0x00, "No Device" + Selection 0x1020, "LVDS" +EndList + +List &eDP_Config_List + Selection 0x00, "No Device" + Selection 0x1806, "eDP" + ; Selection 0x1400, "MIPI" +EndList + +List &eDP_LVDS_Config_List + Selection 0x00, "No Device" + Selection 0x1020, "LVDS" + Selection 0x1806, "eDP" +EndList + + +List &No_Yes_List + Selection 0, "No" + Selection 1, "Yes" +EndList + +List &Off_On_List + Selection 0, "Off" + Selection 1, "On" +EndList + +List &OS_Driver_List + Selection 0, "OS Default Algorithm" + Selection 1, "Driver Algorithm" +EndList + +List &OS_DriverP_List + Selection 0, "OS Default Algorithm" + Selection 1, "Driver Persistence Algorithm" +EndList + +List &Panel_Color_Depth_List + Selection 0x00, "18-bit Color Depth" + Selection 0x01, "24-bit Color Depth" +EndList + +List &eDP_Panel_Color_Depth_List + Selection 0x00, "18-bit Color Depth" + Selection 0x01, "24-bit Color Depth" + Selection 0x02, "30-bit Color Depth" +EndList + +List &eDP_Link_DataRate_List + Selection 0x00, "1.62 Gbps" + Selection 0x01, "2.70 Gbps" +EndList + +List &eDP_Link_LaneCount_List + Selection 0x00, "x1" + Selection 0x01, "x2" + Selection 0x03, "x4" +EndList + +List &eDP_Link_PreEmp_List + Selection 0x00, "Level 0" + Selection 0x01, "Level 1" + Selection 0x02, "Level 2" + Selection 0x03, "Level 3" +EndList + +List &eDP_Link_VSwing_List + Selection 0x00, "Level 0" + Selection 0x01, "Level 1" + Selection 0x02, "Level 2" + Selection 0x03, "Level 3" +EndList + + +List &Panel_Connector_List + Selection 0x00, "SPGW" + Selection 0x01, "OpenLDI" +EndList + +List &Panel_List + Selection 0x00, "PANEL #01" + Selection 0x01, "PANEL #02" + Selection 0x02, "PANEL #03" + Selection 0x03, "PANEL #04" + Selection 0x04, "PANEL #05" + Selection 0x05, "PANEL #06" + Selection 0x06, "PANEL #07" + Selection 0x07, "PANEL #08" + Selection 0x08, "PANEL #09" + Selection 0x09, "PANEL #10" + Selection 0x0A, "PANEL #11" + Selection 0x0B, "PANEL #12" + Selection 0x0C, "PANEL #13" + Selection 0x0D, "PANEL #14" + Selection 0x0E, "PANEL #15" + Selection 0x0F, "PANEL #16" +EndList + + +List &Panel_Stretch_List + Selection 0x00, "Disable Panel Fitting" + Selection 0x01, "Enabled for Text Modes Only" + Selection 0x02, "Enabled for Graphics Modes Only" + Selection 0x03, "Enabled for Both Text and Graphics Modes" +EndList + +List &PCI_BIOS_Disabled_Enabled_List + Selection 0x00, "Disabled" + Selection 0x01, "Resize to 0.5K boundary" + Selection 0x20, "Resize to 16K boundary" +EndList + +List &RelStage + Selection 1, "Production" + Selection 254, "Evaluation" +EndList + +List &Power_Scheme_List + Selection 0, "CUI" + Selection 1, "3rd Party Application" +EndList + +List &Render_Freq_List + Selection 0, "High Frequency" + Selection 1, "Low Frequency" +EndList + +List &SSC_List + Selection 0, "96 MHz" + Selection 1, "100 MHz" +EndList + +List &SDVO_Panel_List + Selection 0x00, "PANEL #01" + Selection 0x01, "PANEL #02" + Selection 0x02, "PANEL #03" + Selection 0x03, "PANEL #04" +EndList + +List &Yes_No_List + Selection 0, "Yes" + Selection 1, "No" +EndList + +List &Sprite_Display_List + Selection 0, "Secondary Display" + Selection 1, "Primary Display" +EndList + +List &Under_Over_List + Selection 0x0, "Enable Underscan and Overscan modes" + Selection 0x1, "Enable only overscan modes" + Selection 0x2, "Enable only underscan modes" +EndList + +List &Inter_Exter_List + Selection 0, "External Termination" + Selection 1, "Internal Termination" +EndList + +List &DPS_Panel_Type_List + Selection 0x00, "Static DRRS" + Selection 0x02, "Seamless" +EndList + +List &MSA_TimingDelay_List + Selection 0x00, "Line 1" + Selection 0x01, "Line 2" + Selection 0x02, "Line 3" + Selection 0x03, "Line 4" +EndList + +List &Blt_Control_Type_List + ;Selection 0x00, "Default" + Selection 0x01, "CCFL Backlight" + Selection 0x02, "LED Backlight" +EndList + + +List &Mode_Preferred_List + Selection 0x00, "Mode Timing" + Selection 0x01, "Preferred Timing" +EndList + +List &DisplayList + Selection 0x08, "LFP" + ;Selection 0x80, "LFP 2" + ;Selection 0x01, "CRT" + Selection 0x04, "EFP 1" + Selection 0x40, "EFP 2" + Selection 0x20, "EFP 3" + Selection 0x00, "None" +EndList + +List &Dither_Select_Bit + Selection 0, "Dithering in Panel controller" + Selection 1, "Dithering in Display Controller" +EndList + +List &MIPI_Bridge_Ref_Clock_List + Selection 0, "19.2" + Selection 1, "26" +EndList + +List &Panel_Identifier_List + Selection 0x0, "Use Sequence Block" + Selection 0x1, "MIPI DSI Panel-1" + Selection 0x2, "MIPI DSI Panel-2" + Selection 0x3, "MIPI DSI Panel-3" + Selection 0x4, "MIPI DSI Panel-4" + Selection 0x5, "MIPI DSI Panel-5" + Selection 0x6, "MIPI DSI Panel-6" + Selection 0x7, "MIPI DSI Panel-7" + Selection 0x8, "MIPI DSI Panel-8" + ;Selection 0x9, "MIPI DSI Panel-9" + ;Selection 0xA, "MIPI DSI Panel-10" + ;Selection 0xB, "MIPI DSI Panel-11" + ;Selection 0xC, "MIPI DSI Panel-12" + ;Selection 0xD, "MIPI DSI Panel-13" + ;Selection 0xE, "MIPI DSI Panel-14" + ;Selection 0xF, "MIPI DSI Panel-15" + ;Selection 0x10, "MIPI DSI Panel-16" +EndList + +List &Panel_Type_List + Selection 0, "Native MIPI DSI" + Selection 1, "MIPI DSI to LVDS Bridge" +EndList + +List &MIPI_DSI_Panel_Architecture_Type_List + Selection 0x0, "Type 1" + Selection 0x1, "Type 2" + Selection 0x2, "Type 3" + Selection 0x3, "Type 4" +EndList + +List &Video_Command_Mode_List + Selection 0, "Video Mode" + Selection 1, "Command Mode" +EndList + +List &Packet_Sequence_Video_Mode_List + ;Selection 0x0, "Reserved" + Selection 0x1, "Non-burst with sync pulse" + Selection 0x2, "Non-burst with sync events" + Selection 0x3, "Burst Mode" +EndList + +List &Colour_Format_Video_Mode_List + Selection 0x1, "RGB565" + Selection 0x2, "RGB666" + Selection 0x3, "RGB 666(Loosely Packed Format)" + Selection 0x4, "RGB888" +EndList + +List &Panel_Rotation_List + Selection 0x0, "0 degree" + Selection 0x1, "90 degree" + Selection 0x2, "180 degree" + Selection 0x3, "270 degree" +EndList + +List &Enable_Disable_List + Selection 0, "Enable" + Selection 1, "Disable" +EndList + +List &EscapeClk_List + Selection 0x0, "20 MHz" + Selection 0x1, "10 MHz" + Selection 0x2, "5 MHz" + ;Selection 0x3, "Undefined" +EndList + +List &DPhyParamFlag_List + Selection 0, "Dphy Param is not valid" + Selection 1, "Dphy Param is valid" +EndList + +List &MIPI_DSI_Panel_Color_Depth_List + Selection 0x0, "18Bpp" + Selection 0x1, "24Bpp" +EndList + +List &Lane_Count_List + Selection 0x0, "1" + Selection 0x1, "2" + Selection 0x2, "3" + Selection 0x3, "4" +EndList + +List &Dual_Link_List + Selection 0x0, "Dual Link Not Supported" + Selection 0x1, "Dual Link Front Back Mode" + Selection 0x2, "Dual Link Pixel Alternative Mode" + ;Selection 0x3, "Reserved" +EndList + +List &Hdmi_LS_List_CHV + Selection 0x00, "1.2V 3dB" + Selection 0x01, "1.0V 0dB" +EndList + +List &Edp_Pwm_Source_List + Selection 0x1, "LPSS PWM" + Selection 0x2, "DISPLAY PWM" +EndList + +List &eDP_VSwing_Preemph_table_List + Selection 0x00, "Low Power VSwing/Pre-Emphasis Table" + Selection 0x01, "Default VSwing/Pre-Emphasis Table" +EndList + +;============================================================================== +; Page Definitions +;------------------------------------------------------------------------------ + +BeginInfoBlock + PPVer "2.01" + Image EOF Thru EOF At EOF +EndInfoBlock + + +;============================================================================== +; Page - VBT version +;------------------------------------------------------------------------------ + +Page "VBT version" + + Title "PLATFORM : CherryView" + Title "VBT version: 195" + +EndPage ; VBT version + + + +;============================================================================== +; Page - UEFI GOP Driver Configuration +;------------------------------------------------------------------------------ + +Page "UEFI GOP Driver Configuration" + + ;Combo $Hotplug_Support_Enb, " Hot Plug Support:", &Disabled_Enabled_List, + ;Help "This feature is to enable/disable Hot Plug Suppport for CRT/DP/HDMI displays " + + Title "Child Device Configuration" + Link "Child Device List", "Child Device List" + + Title "Fixed Mode" + Link "Fixed Mode Feature", "Fixed Mode Feature" + + ;============================================================================== + ; Page - Boot Display Algorithm + ;------------------------------------------------------------------------------ + + Page "Child Device List" + + Title "Select the child devices that the GOP driver should enumerate if detected." + Title "Note: The child devices are listed here in decreasing order of priority. In case the system BIOS does not specify " + "the child device to start, then GOP driver selects the highest priority child device" + + Link "Close Window", ".." + + Title "Child Device 1" + Combo $ChildDevice1Primary, "Primary display:" , &DisplayList, + Help "Primary Display\r\n" + Combo $ChildDevice1Secondary, " Secondary display: " , &DisplayList, + Help "Secondary Display\r\n" + + Title " " + Title "Child Device 2" + Combo $ChildDevice2Primary, "Primary display:" , &DisplayList, + Help "Primary Display\r\n" + Combo $ChildDevice2Secondary, " Secondary display: " , &DisplayList, + Help "Secondary Display\r\n" + + Title " " + Title "Child Device 3" + Combo $ChildDevice3Primary, "Primary display:" , &DisplayList, + Help "Primary Display\r\n" + Combo $ChildDevice3Secondary, " Secondary display: " , &DisplayList, + Help "Secondary Display\r\n" + + Title " " + Title "Child Device 4" + Combo $ChildDevice4Primary, "Primary display:" , &DisplayList, + Help "Primary Display\r\n" + Combo $ChildDevice4Secondary, " Secondary display: " , &DisplayList, + Help "Secondary Display\r\n" + + Title " " + Title "Child Device 5" + Combo $ChildDevice5Primary, "Primary display:" , &DisplayList, + Help "Primary Display\r\n" + Combo $ChildDevice5Secondary, " Secondary display: " , &DisplayList, + Help "Secondary Display\r\n" + + Title " " + Title "Child Device 6" + Combo $ChildDevice6Primary, "Primary display:" , &DisplayList, + Help "Primary Display\r\n" + Combo $ChildDevice6Secondary, " Secondary display: " , &DisplayList, + Help "Secondary Display\r\n" + + Title " " + Title "Child Device 7" + Combo $ChildDevice7Primary, "Primary display:" , &DisplayList, + Help "Primary Display\r\n" + Combo $ChildDevice7Secondary, " Secondary display: " , &DisplayList, + Help "Secondary Display\r\n" + + Title " " + Title "Child Device 8" + Combo $ChildDevice8Primary, "Primary display:" , &DisplayList, + Help "Primary Display\r\n" + Combo $ChildDevice8Secondary, " Secondary display: " , &DisplayList, + Help "Secondary Display\r\n" + + Title " " + Title "Child Device 9" + Combo $ChildDevice9Primary, "Primary display:" , &DisplayList, + Help "Primary Display\r\n" + Combo $ChildDevice9Secondary, " Secondary display: " , &DisplayList, + Help "Secondary Display\r\n" + + Title " " + Title "Child Device 10" + Combo $ChildDevice10Primary, "Primary display:" , &DisplayList, + Help "Primary Display\r\n" + Combo $ChildDevice10Secondary, " Secondary display: " , &DisplayList, + Help "Secondary Display\r\n" + + Title " " + Title "Child Device 11" + Combo $ChildDevice11Primary, "Primary display:" , &DisplayList, + Help "Primary Display\r\n" + Combo $ChildDevice11Secondary, " Secondary display: " , &DisplayList, + Help "Secondary Display\r\n" + + Title " " + Title "Child Device 12" + Combo $ChildDevice12Primary, "Primary display:" , &DisplayList, + Help "Primary Display\r\n" + Combo $ChildDevice12Secondary, " Secondary display: " , &DisplayList, + Help "Secondary Display\r\n" + + Title " " + Title "Child Device 13" + Combo $ChildDevice13Primary, "Primary display:" , &DisplayList, + Help "Primary Display\r\n" + Combo $ChildDevice13Secondary, " Secondary display: " , &DisplayList, + Help "Secondary Display\r\n" + + Title " " + Title "Child Device 14" + Combo $ChildDevice14Primary, "Primary display:" , &DisplayList, + Help "Primary Display\r\n" + Combo $ChildDevice14Secondary, " Secondary display: " , &DisplayList, + Help "Secondary Display\r\n" + + Title " " + Title "Child Device 15" + Combo $ChildDevice15Primary, "Primary display:" , &DisplayList, + Help "Primary Display\r\n" + Combo $ChildDevice15Secondary, " Secondary display: " , &DisplayList, + Help "Secondary Display\r\n" + + Title " " + Title "Child Device 16" + Combo $ChildDevice16Primary, "Primary display:" , &DisplayList, + Help "Primary Display\r\n" + Combo $ChildDevice16Secondary, " Secondary display: " , &DisplayList, + Help "Secondary Display\r\n" + EndPage ;"Child Device List" + +;============================================================================ +; Page - Fixed Mode Configuration +;---------------------------------------------------------------------------- + + Page "Fixed Mode Feature" + Link "Close Table", ".." + Combo $Feature_Enable, "Enable Feature:", &No_Yes_List, + Help "Fixed Mode Feature allows user to fix a mode during POST such that only that particular mode will be always set.\r\n" + "This field specifies if user wants to enable/disable the feature.\r\n" + "When enabled user is expected to provide a valid input." + + EditNum $X_res, "Horizontal Pixels:", DEC, + Help "This value specifies the horizontal pixels of the mode. It should be always less than or equal to the native horizontal resolution.\r\n" + + EditNum $Y_res, "Vertical Pixels:", DEC, + Help "This value specifies the vertical pixels of the mode. It should be always less than or equal to the native vertical resolution.\r\n" + + EndPage +EndPage ; "UEFI GOP Driver Configuration" + + + +;============================================================================ +; Page - Windows Graphics Driver Configuration +;---------------------------------------------------------------------------- + +Page "Windows Graphics Driver Configuration" + + Link "General Features" , "General Features" + Link "Display Features" , "Display Features" + Link "Power Conservation" , "Power Conservation" + + Page "General Features" + Link "Close Table" , ".." + + EditNum $VBT_Customization_Version, " VBT Customization Version:", DEC, + Help "This feature allows the OEM to have a customized VBT version " + "number. The permissible values for VBT Customization version " + "is from 0 to 255.\r\n" + + Combo $Driver_Boot_Device, " First Boot Display Device:", &OS_Driver_List, + Help "This feature allows the OEM to select which algorithm to " + "follow on the first boot after the driver has been " + "installed.\r\n" + "\r\n" + "OS Default - If this is selected, the operating system's " + "algorithm will be used.\r\n" + "\r\n" + "Driver Default - If this is selected, the boot device will " + "follow the driver algorithm. The expected behavior can be " + "found in the Driver PRD chapter: 'First Boot Default " + "Display Resolutions'." + + ;Combo $Allow_FDOS_Disp_Switch, " Allow Full Screen DOS Display Switching:", &No_Yes_List, + ;Help "This feature allows display switching when the system is in " + ; "full screen DOS. When set to yes, display switching will be " + ; "allowed while system is in full screen DOS. When set to no, " + ; "display switching will be blocked when system is in full " + ;"screen DOS." + + ;Combo $Hot_Plug_DVO, " DVO/SDVO Hot Plug:", &Disabled_Enabled_List, + ;Help "This feature allows the OEM to disable the DVO/SDVO Hot Plug " + ; "capability." + + + Combo $Use_110h_for_LFP, " Use _DOD 00000110h ID for Primary LFP:", &No_Yes_List, + Help "This feature when set to yes will use the legacy value " + "00000110h as the ID for primary LFP in the ACPI _DOD, _DGS " + "method. The ID is passed to the system BIOS through INT10h function 5F64h " + "The ID 00000110h is the backwards compatible ACPI ID " + "for LFP, which may be necessary in where Microsoft* WindowsXP " + "TabletPC*'s Graphical User Interface is required for Backlight " + "Control(hardcoded by some Windows OSes). In all other cases, " + "the default new ID is strongly preferred." + + + ;Combo $DVD_Sprite_Clone, " Disable Sprite (DVD) in Clone Mode:", &Yes_No_List, + ;Help "This feature when selected 'No', will allow the sprite to be " + ; "active during DVD playback when the platform is in a Dual " + ; "Display Clone configuration. Otherwise, when selected 'Yes', " + ; "the overlay sprite will be disabled during DVD playback when the " + ; "platform is in a Dual Display Clone configuration." + + Combo $GTF_Mode_Pruning, " Selective Mode Pruning:", &Disabled_Enabled_List, + Help "This feature when enabled will instruct driver software not " + "to enumerate or set specific display modes determined as " + "unsupported according to the EDID capabilities of the " + "display. If the display indicates support for all GTF/DMTS " + "timings in the display's EDID, then all modes supported by " + "the graphics host will be enumerated. If the display does " + "NOT indicate support for GTF/DMTS timings in the display's " + "EDID, then some modes/timings that may have been enumerated " + "by the display driver shall not be set." + "\r\n" + "\r\n" + "Note: This option applies for all display types. And in the " + "absence of other platform configuration information (e.g. " + "OEM Customizable Mode) requiring inclusion of that display " + "mode/timings." + + ;Combo $Sprite_Display_Assign, " Sprite Display Assignment for When Overlay is Active in Clone Mode:", &Sprite_Display_List, + ;Help "This feature when set to Primary Display, the driver will " + ; "assign the Sprite (2ndary overlay) to the primary display " + ; "defined in the current Dual Display Clone configuration, " + ; "otherwise when this feature is set to Secondary Display, the " + ;"driver will assign the Sprite (2ndary overlay) to the " + ;"secondary display defined in the current Dual Display Clone " + ;"configuration. Note: This bit will have no affect if an " + ;"application is using the VMR API. " + + + + Combo $CUIHotK_Static_Display, " Display must be attached for CUI/Hot Key:", &Yes_No_List, + Help "This feature allows a selectable option to determine whether " + "the display device must be attached for CUI Hot Key.\r\n" + "\r\n" + "With the 'No' option the display devices do not have to be " + "attached when enabling the displays via CUI Devices Pages, " + "CUI Hot Key. Note: This feature may cause the user to have " + "a blank display device due to switching to a display that is " + "not attached.\r\n" + "\r\n" + "With the 'Yes' option the display device must be attached or " + "the display switch attempt will be blocked." + EndPage + + Page "Display Features" + Link "Close Table" , ".." + + Combo $CUI_Maintain_Aspect, " Enable 'Maintain Aspect Ratio':", &No_Yes_List, + Help "This feature allows the OEM to enable or disable the 'Maintain " + "Aspect Ratio' feature. When the option is set to Yes, the " + "feature will be enabled and CUI will show for end user " + "selection 'Maintain Aspect Ratio'. When the option is set to " + "No, the complete 'Maintain Aspect Ratio' feature will be disabled." + + Combo $Preserve_Aspect_Ratio, " Preserve Aspect Ratio:", &Disabled_Enabled_List, + Help "This feature allows the OEM to configure the default option " + "for aspect ratio settings. When enabled, the CUI will reflect " + "preserve the aspect ratio as active setting. Otherwise, when " + "disabled, the CUI will use the setting 'Panel Fitting Initial " + "States' as default aspect ratio setting. This option will " + "only be available for initial boot value. Any subsequent " + "change in CUI will have higher priority." + + Title " " + TitleB "Legacy Monitor Mode Limit" + + EditNum $Legacy_Monitor_Max_X, " Maximum X Resolution (Pixels):", DEC, + Help "This feature allows the limiting of selectable display modes " + "when a legacy monitor is detected. The maximum resolution is " + "specified by a maximum number of horizontal active pixels." + "\r\n" + "Note: A legacy monitor is defined as a monitor with no DDC " + "available." + + EditNum $Legacy_Monitor_Max_Y, " Maximum Y Resolution (Pixels):", DEC, + Help "This feature allows the limiting of selectable display modes " + "when a legacy monitor is detected. The maximum resolution is " + "specified by a maximum number of vertical active pixels." + "\r\n" + "Note: A legacy monitor is defined as a monitor with no DDC " + "available." + + EditNum $Legacy_Monitor_Max_RR, " Maximum Refresh Rate (Hz):", DEC, + Help "This feature allows the limiting of selectable display modes " + "when a legacy monitor is detected. The maximum refresh rate " + "is specified in Hz." + "\r\n" + "Note: A legacy monitor is defined as a monitor with no DDC " + "available." + + + Title " " + TitleB "Rotation Support Configuration" + + + Combo $Rotation_Support_Enable, "Support Rotation Feature:", &No_Yes_List, + Help "This feature when set to yes, can cause the graphics driver to " + "support rotation feature, otherwise rotation feature support " + "will be disabled." + "\r\n" + "Note: Setting this field to Yes is a necessary condition for driver to " + "support rotation feature, but it is not sufficient." + + + Title " " + TitleB "Graphics Mode to Boot on Windows" + + + EditNum $Driver_Boot_Mode_X, " X Resolution (Pixels):", DEC, + Help "This feature allows the OEM to select which resolution the " + "system will use on the first reboot after the driver has " + "been installed.\r\n" + "\r\n" + "X Resolution (Pixels)\r\n" + "\r\n" + "Note: This feature is only used when the Boot Display " + "Algorithm is set to Driver Default." + + EditNum $Driver_Boot_Mode_Y, " Y Resolution (Pixels):", DEC, + Help "This feature allows the OEM to select which resolution the " + "system will use on the first reboot after the driver has " + "been installed.\r\n" + "\r\n" + "Y Resolution (Pixels)\r\n" + "\r\n" + "Note: This feature is only used when the Boot Display " + "Algorithm is set to Driver Default." + + EditNum $Driver_Boot_Mode_BPP, " Color Depth (Bits/Pixel):", DEC, + Help "This feature allows the OEM to select which resolution the " + "system will use on the first reboot after the driver has " + "been installed.\r\n" + "\r\n" + "Color Depth (BPP)\r\n" + "\r\n" + "Note: This feature is only used when the Boot Display " + "Algorithm is set to Driver Default." + + EditNum $Driver_Boot_Mode_RR, " Refresh Rate (Hz):", DEC, + Help "This feature allows the OEM to select which resolution the " + "system will use on the first reboot after the driver has " + "been installed.\r\n" + "\r\n" + "Refresh Rate (Hz)\r\n" + "\r\n" + "Note: This feature is only used when the Boot Display " + "Algorithm is set to Driver Default." +Title " " +TitleB "TV features" + + Combo $Under_Over_Scan_Via_YPrPb, " Enable underscanned modes for HDTV via Component (YPrPb):", &Under_Over_List, + Help "For 720p format when enable underscan and overscan modes " + "option is selected, expose 1184x666 and 1280x720 through CUI" + "\r\n" + "For 1080i format when enable underscan and overscan modes " + "option is selected, expose 1776x1080 and 1920x1080 through CUI" + + Combo $Under_Over_Scan_Via_DVI, " Enable underscanned modes for HDTV via HDMI:", &Under_Over_List, + Help "When 720p is found in the EDID structure of the active HDMI " + "display and enable underscan modes is selected, 1184x666 will " + "be available and be centered in 720p timings when enabled. " + "\r\n" + "When 1080i or 1080p is found in the EDID structure of the " + "active DVI display and enable underscan modes is selected, " + "1776x1000 will be centered in appropriate 1080 timings. " + + Title "\r\n" + Title " Add 1776x1000 when 1080i is selected and add 1184x666 when 720p is selected for HDTV via HDMI:" + Combo $Add_Overscan_Mode, " ", &Disabled_Enabled_List, + Help "For 1080i format, 1776x1000 will be made available in CUI " + "along with native resolution 1920x1080. For 720p format, " + "1184x666 will be made available in CUI along with native " + "resolution 1280x720. These resolutions are exposed to get the " + "HDMI image under scanned with task bar visible." + EndPage ; Display features + + + + + Page "Power Conservation" + Link "Close Table" , ".." + + ;Combo $SDVO_Device_Power_Down, " SDVO device power down:", &Disabled_Enabled_List, + ;Help "This feature powers down the SDVO device when the system is " + "running in battery mode (DC) and the corresponding display " + "not connected." + + Combo $BIA_Enable, " Intel® Display Power Saving Technology Support for the LFP:", &Disabled_Enabled_List, + Help "This feature determines whether the Intel® Display Power " + "Savings Technology (DPST) is enabled or disabled. Intel® DPST " + "is a display power savings technology that changes the " + "intensity of colors in order to conserve backlight power." + "\r\n\r\nNote: This technology is only active when the system " + "is running in battery mode and the LFP is the only active " + "display device." + + Combo $BIA_Aggress_Level, " Power Conservation Preference Level for the LFP:", &Pwr_Pref_List, + Help "This feature defines the Intel® Display Power Saving Technology " + "aggressiveness level if and only if the feature Intel® Display Power Saving " + "Technology is enabled." + "\r\n\r\nThe following are the definitions for each level:" + "\r\n1 - Maximum Quality - shall use no DPST " + "\r\n2 - Provides the user the maximum " + "brightness for their embedded Local Flat Panel (LFP)while DPST is in use" + "\r\n3 - This level defines maximum amount of brightness with " + "minimal power savings" + "\r\n4 - This level defines an intermediate value for brightness amount" + "\r\n5 - This level defines an intermediate value for the brightness amount" + "\r\n6 - Maximum Battery - Provided the user with the minimum amount of " + "brightness capable for their LFP with the maximum power savings" + + Combo $Panel_Self_Refresh, " Panel Self Refresh (PSR):", &Disabled_Enabled_List, + Help "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled. " + + Combo $PM_DRRS_Enable, " Intel ® Display Refresh Rate Switching (DRRS):", &Disabled_Enabled_List, + Help "This feature determines whether Intel ® Display Refresh Rate Switching (DRRS) is to be " + "enabled or not. " + + Combo $ALS_Enable, " Intel ® Automatic Display Brightness Support for the LFP:", &Disabled_Enabled_List, + Help "This feature determines whether Intel ® Automatic Display Brightness is to be " + "enabled. Intel ® Automatic Display Brightness adjusts the brightness of the " + "embedded Local Flat Panel (LFP) depending on the current " + "ambient light environment. When enabled, the driver and VBIOS" + " will control the backlight brightness of the LFP depending " + "on the ambient environment if and only if the LFP is the only " + "active display. When disabled, the driver and VBIOS will " + "perform no action." + + Combo $DMRRS, " Dynamic Media Refresh Rate Switching (DMRRS):", &Disabled_Enabled_List, + Help "This feature determines whether Dynamic Media Refresh Rate Switching feature is to be enabled. " + + Link "Ambient Light Response Data" , "Ambient Light Response Data" + + Page "Ambient Light Response Data" + Link "Close Table" , ".." + + Table $ALS_Response_Data " Ambient Light Response Data", + Column "Backlight Adjust", 2 bytes, EHEX + Column "Lux", 2 bytes, EHEX, + Help "This feature defines values used to calibrate the " + "Intel® Automatic Display Brightness policy's " + "response to account for specific hardware implementation " + "details such as sensor placement and optics. Up to five " + "points can be specified, where each point indicates a given " + "ambient light illuminance to display luminance mapping " + "specified as (<%BacklightAdjust>, ). Points should be " + "listed in monotonically increasing order by ambient light " + "illuminance (lux). A minimum of two points are required " + "(min and max)." + EndPage + + EndPage + EndPage +;============================================================================== +; Page - Display Configuration +;------------------------------------------------------------------------------ + +Page "Display Configuration" + + Link "LFP" , "LFP" + Link "EFP 1" , "EFP 1" + Link "EFP 2" , "EFP 2" + Link "EFP 3" , "EFP 3" + + TitleB "DisplayPort SSC configuration: " + Combo $DP_SSC_Enb, " DisplayPort (External Connectors) Spread Spectrum Clock:", &Disabled_Enabled_List, + Help "This feature allow OEMs to enable/disable SSC for external DisplayPort. " + "This feature is valid only the attached DisplayPort panel support SSC. " + "\r\n" + + Combo $DP_SSC_Dongle_Enb, " DisplayPort Spread Spectrum Clock Enable/Disable for Dongles:", &Disabled_Enabled_List, + Help "This feature is to enable or disable DisplayPort Dongle Spread Spectrum Clock when dongle are used " + "and the attached DisplayPort panel should support SSC\r\n" + + + Page "LFP" + Link "Close Table", ".." + + Combo $Int_LFP1_Type , "Active Local Flat Panel Configuration", &eDP_Config_List, + Help "This option select Device type." + + ; #IF ($Int_LFP1_Type == 0x1806) + Combo $Int_LFP1_Port, "Select Output Port:", &LFP_Port_List, + Help "This feature specifies which DVO port to use for the selected LFP Device." + ;#ENDIF + + Combo $Int_LFP1_AUX_Channel, "Select AUX Channel:", &Int_eDP_AUX_Channel_List, + Help "This feature specifies the AUX Channel for int-Embedded DisplayPort. " + "This field is valid only if integrated eDP is selected for Device Type." + + ;Combo $Int_LFP1_Priority, "Primary LFP panel: ", &Yes_No_List, + ;Help "This feature will select if the panel is primary or not. " + ;"The VLV platform has only one panel fitter. So, stretched mode will be only applicable " + ;"to primary panel . In secondary panel only native mode or " + ;"centering modes will be supported." + + Combo $bmp_Panel_type, "Select Panel Type:", &Panel_List, + Help "This feature selects the Local Flat Panel (LFP) the VBIOS " + "and driver is to enable.\r\n" + "\r\n" + "Note, a valid return from the system BIOS hook 5F40h will " + "replace this default value.\r\n" + "\r\n" + "Default LFP parameter values:\r\n" + "\tPANEL #01: 640x480 LVDS\r\n" + "\tPANEL #02: 800x600 LVDS\r\n" + "\tPANEL #03: 1024x768 LVDS\r\n" + "\tPANEL #04: 1280x1024 LVDS\r\n " + "\tPANEL #05: 1400x1050 Reduced Blanking LVDS\r\n" + "\tPANEL #06: 1400x1050 Non-Reduced Blanking LVDS\r\n" + "\tPANEL #07: 1600x1200 LVDS\r\n" + "\tPANEL #08: 1280x768 LVDS\r\n" + "\tPANEL #09: 1680x1050 LVDS\r\n" + "\tPANEL #10: 1920x1200 LVDS\r\n" + "\tPANEL #11: Reserved\r\n" + "\tPANEL #12: Reserved\r\n " + "\tPANEL #13: Reserved\r\n" + "\tPANEL #14: 1280x800 LVDS\r\n" + "\tPANEL #15: 1280x600 LVDS\r\n" + "\tPANEL #16: Reserved" + + Combo $bmp_Panel_EDID, "Local Flat Panel (LFP) EDID Support: ", &Disabled_Enabled_List, + Help "This feature, when enabled, will activate support for a LFP " + "with an EDID. The video BIOS and drivers will load the EDID " + "and use its data to set appropriate timing on current panel. " + "If disabled, there will be no attempt to read an EDID and other methods " + "will be used to set panel timing." + "\r\n\r\nNote: The backlight data may need to be updated." + "\r\n The option on page General" + " Features must be correct for platform." + + Combo $180_Deg_Rotation_Enable, "Enable 180 Degree Rotation:", &No_Yes_List, + Help "This feature when set to yes, will enable 180 Degree rotation " + "otherwise, the rotation functionality will be disabled." + + + EndPage + + + ;Page "CRT" + ; Link "Close Window" , ".." + + ; Combo $Int_CRT_Support, "CRT Device:", &Int_CRT_Device_Type_List, + ; Help "This option select CRT Device." + + ;Combo $CRT_DDC_GMBUS_Pin, "Select DDC Bus GPIO Pin Pair:", &GPIO_Pin_List, + ;Help "This feature specifies the GPIO pin pair " + ; "used as DDC bus by this device. If this device " + ; "doesn't support DDC bus, this field will be ignored." + + ;EndPage + + Page "EFP 1" + Link "Close Window" , ".." + + Combo $Int_EFP1_Type, "Device Type", &Int_EFP_Device_Type_List, + Help "This option specifies the Device Type." + + Combo $Int_EFP1_Port, "Select Output Port:", &Int_EFP_Port_List, + Help "This feature specifies which DVO port to use for the selected EFP Device." + + Combo $Int_EFP1_AUX_Channel, "Select AUX Channel:", &Int_DP_AUX_Channel_List, + Help "This feature specifies the AUX Channel for int-DisplayPort. " + "This field is valid only if integrated DP is selected for Device Type." + + Combo $Int_EFP1_DDC_Pin, "Select DDC Bus GPIO Pin Pair:", &GPIO_Pin_List, + Help "This feature specifies the GPIO pin pair " + "used as DDC bus by this device. If this device " + "doesn't support DDC bus, this field will be ignored." + + Combo $Int_EFP1_HDMI_LS_Type, "Select HDMI level shifter configuration:", &Hdmi_LS_List_CHV, + Help "This feature specifies the Level shifter configuration for HDMI. " + "This field is valid only if HDMI is selected for Device Type." + + ;Combo $Int_EFP1_Dongle_Detect, "Select Dongle Detect:", &Disabled_Enabled_List, + ;Help "This option Enables/Disables detection of type of dongle connected to DP port.\r\n" + ; "This option is used only by the GFX driver." + + Combo $Int_EFP1_Docked_Port, "Dockable: ", &No_Yes_List, + Help "This field describes if the Display Port is routed through Dock or not." + + Link "USB-Type-C Dongle Feature Configuration" , "USB-Type-C Dongle Feature Configuration" + Link "DisplayPort Redriver Configuration" , "DisplayPort Redriver Configuration" + + Page "USB-Type-C Dongle Feature Configuration" + + Combo $EFP1_USB_C_DongleFeature_Enabled, "USB-Type-C Dongle Feature Enabled:", &Disabled_Enabled_List, + Help "This option Enables/Disables USB-Type-C Dongle Feature for USB Type C port for DP panels.\r\n" + EditNum $EFP1_GPIO_Index, "GPIO Index:", DEC, + Help "Enter the GPIO index/GPIO resource ID which is being used by Gfx driver" + EditNum $EFP1_GPIO_Number, "GPIO Number:", DEC, + Help "Enter the GPIO number which will be read to identify whether it is 2xDP or 4xDP DP over USB cable attached." + "If 2xDP cable is attached, microcontroller will set the this gpio pin to high." + "If 4xDP cable is attached, microcontroller will set the this pin to low." + EndPage + + Page "DisplayPort Redriver Configuration" + + Combo $EFP1_OnBoard_Redriver_Present, "Non-dock topology:", &No_Yes_List, + Help "This feature will describe if Non-dock topology/OnBoard Redriver DP Link is present or not." + + Combo $EFP1_OnBoard_PreEmph_Level, " Pre-Emphasis Level:", &eDP_Link_PreEmp_List, + Help "This feature allows for the selection of " + "Pre-emphasis level for the OnBoard redriver DP link.\n" + "\r\n\n\t\t\tDefault Swing Setting Table\n" + "\t---------------------------------------------------------------------------------------------------\n" + "\t \t | \t\t PreEmphasis Levels\t\t |\n" + "\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\n " + "\t---------------------------------------------------------------------------------------------------\n" + "\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\n" + "\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\n" + "\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\n" + "\t| Level 3(1200mV) | 1200mV | N/A | N/A | N/A |\n" + "\t---------------------------------------------------------------------------------------------------\n" + "\tColumn - Non-Transition VDiff \r\n" + "\tRow - Transition VDiff \r\n" + + + Combo $EFP1_OnBoard_VSwing_Level, " Voltage Swing Level:", &eDP_Link_VSwing_List, + Help "This feature allows for the selection of " + "Voltage Swing level for the OnBoard redriver DP link.\n" + "\r\n\n\t\t\tDefault Swing Setting Table\n" + "\t---------------------------------------------------------------------------------------------------\n" + "\t \t | \t\t PreEmphasis Levels\t\t |\n" + "\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\n " + "\t---------------------------------------------------------------------------------------------------\n" + "\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\n" + "\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\n" + "\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\n" + "\t| Level 3(1200mV) | 1200mV | N/A | N/A | N/A |\n" + "\t---------------------------------------------------------------------------------------------------\n" + "\tColumn - Non-Transition VDiff \r\n" + "\tRow - Transition VDiff \r\n" + + + Title " " + + Combo $EFP1_OnDock_Redriver_Present, "Dock Topology: (Mobile only)", &No_Yes_List, + Help "This feature will describe if Dock Topology/Dock Redriver DP Link is present or not.\r\n\r\n" + "Note: For Dock Topology to work SBIOS should implement a GOP Policy Protocol to provide the" + " docking status of the platform to GOP.\n" + + Combo $EFP1_OnDock_PreEmph_Level, " Pre-Emphasis Level:", &eDP_Link_PreEmp_List, + Help "This feature allows for the selection of " + "Pre-emphasis level for the Dock redriver DP link." + "\r\n\n\t\t\tDefault Swing Setting Table\n" + "\t---------------------------------------------------------------------------------------------------\n" + "\t \t | \t\t PreEmphasis Levels\t\t |\n" + "\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\n " + "\t---------------------------------------------------------------------------------------------------\n" + "\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\n" + "\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\n" + "\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\n" + "\t| Level 3(1200mV) | 1200mV | N/A | N/A | N/A |\n" + "\t---------------------------------------------------------------------------------------------------\n" + "\tColumn - Non-Transition VDiff \r\n" + "\tRow - Transition VDiff \r\n" + + Combo $EFP1_OnDock_VSwing_Level, " Voltage Swing Level:", &eDP_Link_VSwing_List, + Help "This feature allows for the selection of " + "Voltage Swing level for the Dock redriver DP link." + "\r\n\n\t\t\tDefault Swing Setting Table\n" + "\t---------------------------------------------------------------------------------------------------\n" + "\t \t | \t\t PreEmphasis Levels\t\t |\n" + "\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\n " + "\t---------------------------------------------------------------------------------------------------\n" + "\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\n" + "\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\n" + "\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\n" + "\t| Level 3(1200mV) | 1200mV | N/A | N/A | N/A |\n" + "\t---------------------------------------------------------------------------------------------------\n" + "\tColumn - Non-Transition VDiff \r\n" + "\tRow - Transition VDiff \r\n" + + EndPage ; "DisplayPort Redriver Configuration" + + EndPage + + + Page "EFP 2" + Link "Close Window" , ".." + + Combo $Int_EFP2_Type, "Device Type:", &Int_EFP_Device_Type_List, + Help "This option specifies the Device Type." + + Combo $Int_EFP2_Port, "Select Output Port:", &Int_EFP_Port_List, + Help "This feature specifies which DVO port to use for the selected EFP Device." + + Combo $Int_EFP2_AUX_Channel, "Select AUX Channel:", &Int_DP_AUX_Channel_List, + Help "This feature specifies the AUX Channel for int-DisplayPort. " + "This field is valid only if integrated DP is selected for Device Type." + + Combo $Int_EFP2_DDC_Pin, "Select DDC Bus GPIO Pin Pair:", &GPIO_Pin_List, + Help "This feature specifies the GPIO pin pair " + "used as DDC bus by this device. If this device " + "doesn't support DDC bus, this field will be ignored." + + Combo $Int_EFP2_HDMI_LS_Type, "Select HDMI level shifter configuration:", &Hdmi_LS_List_CHV, + Help "This feature specifies the Level shifter configuration for HDMI. " + "This field is valid only if HDMI is selected for Device Type." + + + ;Combo $Int_EFP2_Dongle_Detect, "Select Dongle Detect:", &Disabled_Enabled_List, + ;Help "This option Enables/Disables detection of type of dongle connected to DP port.\r\n" + ; "This option is used only by the GFX driver." + + Combo $Int_EFP2_Docked_Port, "Dockable: ", &No_Yes_List, + Help "This field describes if the Display Port is routed through Dock or not." + + Link "USB-Type-C Dongle Feature Configuration" , "USB-Type-C Dongle Feature Configuration" + Link "DisplayPort Redriver Configuration" , "DisplayPort Redriver Configuration" + + Page "USB-Type-C Dongle Feature Configuration" + Combo $EFP2_USB_C_DongleFeature_Enabled, "USB-Type-C Dongle Feature Enabled:", &Disabled_Enabled_List, + Help "This option Enables/Disables USB-Type-C Dongle Feature for USB Type C port for DP panels.\r\n" + EditNum $EFP2_GPIO_Index, "GPIO Index:", DEC, + Help "Enter the GPIO index/GPIO resource ID which is being used by Gfx driver" + EditNum $EFP2_GPIO_Number, "GPIO Number:", DEC, + Help "Enter the GPIO number which will be read to identify whether it is 2xDP or 4xDP DP over USB cable attached." + "If 2xDP cable is attached, microcontroller will set the this gpio pin to high." + "If 4xDP cable is attached, microcontroller will set the this pin to low." + EndPage + + Page "DisplayPort Redriver Configuration" + + Combo $EFP2_OnBoard_Redriver_Present, "Non-dock topology:", &No_Yes_List, + Help "This feature will describe if Non-dock topology/OnBoard Redriver DP Link is present or not." + + Combo $EFP2_OnBoard_PreEmph_Level, " Pre-Emphasis Level:", &eDP_Link_PreEmp_List, + Help "This feature allows for the selection of " + "Pre-emphasis level for the OnBoard redriver DP link.\n" + "\r\n\n\t\t\tDefault Swing Setting Table\n" + "\t---------------------------------------------------------------------------------------------------\n" + "\t \t | \t\t PreEmphasis Levels\t\t |\n" + "\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\n " + "\t---------------------------------------------------------------------------------------------------\n" + "\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\n" + "\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\n" + "\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\n" + "\t| Level 3(1200mV) | 1200mV | N/A | N/A | N/A |\n" + "\t---------------------------------------------------------------------------------------------------\n" + "\tColumn - Non-Transition VDiff \r\n" + "\tRow - Transition VDiff \r\n" + + + Combo $EFP2_OnBoard_VSwing_Level, " Voltage Swing Level:", &eDP_Link_VSwing_List, + Help "This feature allows for the selection of " + "Voltage Swing level for the OnBoard redriver DP link.\n" + "\r\n\n\t\t\tDefault Swing Setting Table\n" + "\t---------------------------------------------------------------------------------------------------\n" + "\t \t | \t\t PreEmphasis Levels\t\t |\n" + "\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\n " + "\t---------------------------------------------------------------------------------------------------\n" + "\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\n" + "\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\n" + "\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\n" + "\t| Level 3(1200mV) | 1200mV | N/A | N/A | N/A |\n" + "\t---------------------------------------------------------------------------------------------------\n" + "\tColumn - Non-Transition VDiff \r\n" + "\tRow - Transition VDiff \r\n" + + + Title " " + + Combo $EFP2_OnDock_Redriver_Present, "Dock Topology: (Mobile only)", &No_Yes_List, + Help "This feature will describe if Dock Topology/Dock Redriver DP Link is present or not.\r\n\r\n" + "Note: For Dock Topology to work SBIOS should implement a GOP Policy Protocol to provide the" + " docking status of the platform to GOP.\n" + + Combo $EFP2_OnDock_PreEmph_Level, " Pre-Emphasis Level:", &eDP_Link_PreEmp_List, + Help "This feature allows for the selection of " + "Pre-emphasis level for the Dock redriver DP link." + "\r\n\n\t\t\tDefault Swing Setting Table\n" + "\t---------------------------------------------------------------------------------------------------\n" + "\t \t | \t\t PreEmphasis Levels\t\t |\n" + "\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\n " + "\t---------------------------------------------------------------------------------------------------\n" + "\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\n" + "\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\n" + "\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\n" + "\t| Level 3(1200mV) | 1200mV | N/A | N/A | N/A |\n" + "\t---------------------------------------------------------------------------------------------------\n" + "\tColumn - Non-Transition VDiff \r\n" + "\tRow - Transition VDiff \r\n" + + Combo $EFP2_OnDock_VSwing_Level, " Voltage Swing Level:", &eDP_Link_VSwing_List, + Help "This feature allows for the selection of " + "Voltage Swing level for the Dock redriver DP link." + "\r\n\n\t\t\tDefault Swing Setting Table\n" + "\t---------------------------------------------------------------------------------------------------\n" + "\t \t | \t\t PreEmphasis Levels\t\t |\n" + "\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\n " + "\t---------------------------------------------------------------------------------------------------\n" + "\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\n" + "\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\n" + "\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\n" + "\t| Level 3(1200mV) | 1200mV | N/A | N/A | N/A |\n" + "\t---------------------------------------------------------------------------------------------------\n" + "\tColumn - Non-Transition VDiff \r\n" + "\tRow - Transition VDiff \r\n" + + EndPage ; "DisplayPort Redriver Configuration" + + + EndPage + + Page "EFP 3" + Link "Close Window" , ".." + + Combo $Int_EFP3_Type, "Device Type:", &Int_EFP_Device_Type_List, + Help "This option specifies the Device Type." + + Combo $Int_EFP3_Port, "Select Output Port:", &Int_EFP_Port_List, + Help "This feature specifies which DVO port to use for the selected EFP Device." + + Combo $Int_EFP3_AUX_Channel, "Select AUX Channel:", &Int_DP_AUX_Channel_List, + Help "This feature specifies the AUX Channel for int-DisplayPort. " + "This field is valid only if integrated DP is selected for Device Type." + + Combo $Int_EFP3_DDC_Pin, "Select DDC Bus GPIO Pin Pair:", &GPIO_Pin_List, + Help "This feature specifies the GPIO pin pair " + "used as DDC bus by this device. If this device " + "doesn't support DDC bus, this field will be ignored." + + Combo $Int_EFP3_HDMI_LS_Type, "Select HDMI level shifter configuration:", &Hdmi_LS_List_CHV, + Help "This feature specifies the Level shifter configuration for HDMI. " + "This field is valid only if HDMI is selected for Device Type." + + ;Combo $Int_EFP3_Dongle_Detect, "Select Dongle Detect:", &Disabled_Enabled_List, + ;Help "This option Enables/Disables detection of type of dongle connected to DP port.\r\n" + Combo $Int_EFP3_Docked_Port, "Dockable: ", &No_Yes_List, + Help "This field describes if the Display Port is routed through Dock or not." + + Link "USB-Type-C Dongle Feature Configuration" , "USB-Type-C Dongle Feature Configuration" + Link "DisplayPort Redriver Configuration" , "DisplayPort Redriver Configuration" + + Page "USB-Type-C Dongle Feature Configuration" + Combo $EFP3_USB_C_DongleFeature_Enabled, "USB-Type-C Dongle Feature Enabled:", &Disabled_Enabled_List, + Help "This option Enables/Disables USB-Type-C Dongle Feature for USB Type C port for DP panels.\r\n" + EditNum $EFP3_GPIO_Index, "GPIO Index:", DEC, + Help "Enter the GPIO index/GPIO resource ID which is being used by Gfx driver" + EditNum $EFP3_GPIO_Number, "GPIO Number:", DEC, + Help "Enter the GPIO number which will be read to identify whether it is 2xDP or 4xDP DP over USB cable attached." + "If 2xDP cable is attached, microcontroller will set the this gpio pin to high." + "If 4xDP cable is attached, microcontroller will set the this pin to low." + EndPage + + Page "DisplayPort Redriver Configuration" + + Combo $EFP3_OnBoard_Redriver_Present, "Non-dock topology:", &No_Yes_List, + Help "This feature will describe if Non-dock topology/OnBoard Redriver DP Link is present or not." + + Combo $EFP3_OnBoard_PreEmph_Level, " Pre-Emphasis Level:", &eDP_Link_PreEmp_List, + Help "This feature allows for the selection of " + "Pre-emphasis level for the OnBoard redriver DP link.\n" + "\r\n\n\t\t\tDefault Swing Setting Table\n" + "\t---------------------------------------------------------------------------------------------------\n" + "\t \t | \t\t PreEmphasis Levels\t\t |\n" + "\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\n " + "\t---------------------------------------------------------------------------------------------------\n" + "\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\n" + "\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\n" + "\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\n" + "\t| Level 3(1200mV) | 1200mV | N/A | N/A | N/A |\n" + "\t---------------------------------------------------------------------------------------------------\n" + "\tColumn - Non-Transition VDiff \r\n" + "\tRow - Transition VDiff \r\n" + + + Combo $EFP3_OnBoard_VSwing_Level, " Voltage Swing Level:", &eDP_Link_VSwing_List, + Help "This feature allows for the selection of " + "Voltage Swing level for the OnBoard redriver DP link.\n" + "\r\n\n\t\t\tDefault Swing Setting Table\n" + "\t---------------------------------------------------------------------------------------------------\n" + "\t \t | \t\t PreEmphasis Levels\t\t |\n" + "\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\n " + "\t---------------------------------------------------------------------------------------------------\n" + "\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\n" + "\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\n" + "\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\n" + "\t| Level 3(1200mV) | 1200mV | N/A | N/A | N/A |\n" + "\t---------------------------------------------------------------------------------------------------\n" + "\tColumn - Non-Transition VDiff \r\n" + "\tRow - Transition VDiff \r\n" + + + Title " " + + Combo $EFP3_OnDock_Redriver_Present, "Dock Topology: (Mobile only)", &No_Yes_List, + Help "This feature will describe if Dock Topology/Dock Redriver DP Link is present or not.\r\n\r\n" + "Note: For Dock Topology to work SBIOS should implement a GOP Policy Protocol to provide the" + " docking status of the platform to GOP.\n" + + Combo $EFP3_OnDock_PreEmph_Level, " Pre-Emphasis Level:", &eDP_Link_PreEmp_List, + Help "This feature allows for the selection of " + "Pre-emphasis level for the Dock redriver DP link." + "\r\n\n\t\t\tDefault Swing Setting Table\n" + "\t---------------------------------------------------------------------------------------------------\n" + "\t \t | \t\t PreEmphasis Levels\t\t |\n" + "\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\n " + "\t---------------------------------------------------------------------------------------------------\n" + "\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\n" + "\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\n" + "\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\n" + "\t| Level 3(1200mV) | 1200mV | N/A | N/A | N/A |\n" + "\t---------------------------------------------------------------------------------------------------\n" + "\tColumn - Non-Transition VDiff \r\n" + "\tRow - Transition VDiff \r\n" + + Combo $EFP3_OnDock_VSwing_Level, " Voltage Swing Level:", &eDP_Link_VSwing_List, + Help "This feature allows for the selection of " + "Voltage Swing level for the Dock redriver DP link." + "\r\n\n\t\t\tDefault Swing Setting Table\n" + "\t---------------------------------------------------------------------------------------------------\n" + "\t \t | \t\t PreEmphasis Levels\t\t |\n" + "\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) |\n " + "\t---------------------------------------------------------------------------------------------------\n" + "\t| Level 0(400mV) | 400mV | 600mV | 800mV | 1200mV |\n" + "\t| Level 1(600mV) | 600mV | 800mV | 1200mV | N/A |\n" + "\t| Level 2(800mV) | 800mV | 1200mV | N/A | N/A |\n" + "\t| Level 3(1200mV) | 1200mV | N/A | N/A | N/A |\n" + "\t---------------------------------------------------------------------------------------------------\n" + "\tColumn - Non-Transition VDiff \r\n" + "\tRow - Transition VDiff \r\n" + + EndPage ; "DisplayPort Redriver Configuration" + ; "This option is used only by the GFX driver." + + EndPage + + +EndPage + + + + +;============================================================================ +; Page - LFP Panel configuration +;---------------------------------------------------------------------------- +Page "LFP Panel configuration" + Link "Panel #1 ", "Panel #1 " + Link "Panel #2 ", "Panel #2 " + Link "Panel #3 ", "Panel #3 " + Link "Panel #4 ", "Panel #4 " + Link "Panel #5 ", "Panel #5 " + Link "Panel #6 ", "Panel #6 " + Link "Panel #7 ", "Panel #7 " + Link "Panel #8 ", "Panel #8 " + Link "Panel #9 ", "Panel #9 " + Link "Panel #10 ", "Panel #10 " + Link "Panel #11 ", "Panel #11 " + Link "Panel #12 ", "Panel #12 " + Link "Panel #13 ", "Panel #13 " + Link "Panel #14 ", "Panel #14 " + Link "Panel #15 ", "Panel #15 " + Link "Panel #16 ", "Panel #16 " + +;============================================================================== +; Page - Panel #1 (640x480) Flat Panel parameters +;------------------------------------------------------------------------------ + +Page "Panel #1 " + + TitleB "Common LFP Features" + + EditText $Panel_Name_01, "\tLFP Panel Name:", + Help "This feature defines the LVDS panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated. " + + Combo $Enable_Scaling_01, "\tScale to Target Resolution:", &No_Yes_List, + Help "Selecting this feature will make the graphics driver to enable Scaling feature by taking the Horizontal and Vertical resolution\r\n" + "from Target X-Res and Target Y-Res fields.\r\n" + + EditNum $Panel_Width_01, "\tTarget X-Res:", DEC, + Help "This value specifies the Target X-Resolution for this panel." + + EditNum $Panel_Height_01, "\tTarget Y-Res:", DEC, + Help "This value specifies the Target Y-Resolutoin for this panel." + "lines) for this panel." + + + Combo $DPS_Panel_Type_01, "\tDPS Panel Type:", &DPS_Panel_Type_List, + Help "This feature allows OEM to select the DPS Panel Type.\r\n " + "Intel SDRRS Technology is a feature of the Intel graphics driver\r\n" + "which reduces display power\r\n" + "SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n" + "rate will not adversely impact the user experience\r\n" + "Seamless:- Allows power savings when on battery mode and when a lower refresh\r\n" + "rate will not adversely impact the user experience.Implements seamless refresh\r\n" + "rate switching, which eliminates the screen blink that occurred\r\n" + "during the refresh rate transitions\r\n" + + EditNum $Seamless_DRRS_Min_RR_01, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, + Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n\n" + "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" + + Combo $Blt_Control_01, "\tBackLight Technology:", &Blt_Control_Type_List, + Help "This feature allows OEM to select the Backlight Technology.\r\n " + + Title " " + Link "LFP PnP ID Table" , "LFP PnP ID" + Link "DTD Timings Table" , "DTD Timings" + Link "Backlight Control Parameters" , "Backlight Control Parameters" + Link "Chromaticity Control" , "Chromaticity Control" + + + + #if ($Int_LFP1_Type == 0x1806) + TitleB "Integrated eDP Features" + + Combo $Enable_SSC01, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, + Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " + Combo $eDP_Panel_Color_Depth_01, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, + Help "This feature specifies the color depth of eDP panel used. " + + Combo $eDP_VSwingPreEmph_1, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, + Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " + "For CherryTrail, based on the selection respective table will be used.\r\n" + "Tables for CherryTrail:-\r\n" + "------------------------------------------------------------------------------------------------------\n" + "|Low Power VSwing Pre-Emphasis Setting Table |\n" + "-----------------------------------------------------------------------------------------------------|\n" + "| | Pre-Emphasis (db) |\n" + "| |------------------------------------------------------------------------------------------|\n" + "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" + "| Voltage |------------------------------------------------------------------------- ---------------|\n" + "| Swing | Level 0/200 | 200mV,0db | 200mV,3.5db | 200mV,6db | 200mV,9db |\n" + "| (mV) |------------------------------------------------------------------------------------------|\n" + "| | Level 1/250 | 250mV,0db | 250mV,3.5db | 250mV,6db | NA |\n" + "| |------------------------------------------------------------------------------------------|\n" + "| | Level 2/300 | 300mV,0db | 300mV,3.5d | NA | NA |\n" + "| |------------------------------------------------------------------------------------------|\n" + "| | Level 3/350 | 350 mv, 0db | NA | NA | NA |\n" + "-----------------------------------------------------------------------------------------------------\n\n" + + "-----------------------------------------------------------------------------------------------------\n" + "|Default VSwing Pre-Emphasis Setting Table |\n" + "---------------------------------------------------------------------------------------------------|\n" + "| | Pre-Emphasis (db) |\n" + "| |----------------------------------------------------------------------------------------|\n" + "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" + "| Voltage |----------------------------------------------------------------------------------------|\n" + "| Swing | Level 0/400 | 400mV,0db | 400mV,3.5db | 400mV,6db | 400mV,9db |\n" + "| (mV) |----------------------------------------------------------------------------------------|\n" + "| | Level 1/600 | 600mV,0db | 600mV,3.5db | 600mV,6db | NA |\n" + "| |----------------------------------------------------------------------------------------|\n" + "| | Level 2/800 | 800mV,0db | 800mV,3.5db | NA | NA |\n" + "| |----------------------------------------------------------------------------------------|\n" + "| | Level 3/1200| 1200mV, 0db | NA | NA | NA |\n" + "-----------------------------------------------------------------------------------------------------\n\n" + + + Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Power Sequencing" + Link "eDP Fast Link Training Configuration" , "eDP Fast Link Training Configuration" + + Page "eDP Panel Power Sequencing" + Link "Close Table", ".." + + Combo $eDP_T3_Optimization_01, "T3 optimization", &Disabled_Enabled_List, + Help "This feature enables or disables T3 optimization. \r\n" + "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" + "When disabled, VBIOS/Graphics driver will wait for T3 time before trying the first AUX transaction" + + EditNum $eDP_Vcc_To_Hpd_Delay_01, "LCDVCC to HPD high delay (T3):", DEC, + Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" + "Valid Range: 0 to 200msec\r\n" + + EditNum $eDP_DataOn_To_BkltEnable_Delay_01, "Valid video data to Backlight Enable delay (T8):", DEC, + Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" + "T8 is inclusive of T7.\r\n" + "Valid Range of T7: 0 to 50msec\r\n" + + EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_01, "PWM-On To Backlight Enable delay:", DEC, + Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" + "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" + "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" + + EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_01, "Backlight Disable to PWM-Off delay:", DEC, + Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" + "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" + "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" + + EditNum $eDP_BkltDisable_To_DataOff_Delay_01, "Backlight Disable to End of Valid video data delay (T9):", DEC, + Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" + + EditNum $eDP_DataOff_To_PowerOff_Delay_01, "End of Valid video data to Power-Off delay (T10):", DEC, + Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" + "Valid Range: 0 to 500 msec\r\n" + + EditNum $eDP_PowerCycle_Delay_01, "Power-off time (T12):", DEC, + Help "Using this field Power-off time can be specified in 100uS.\r\n" + + EndPage + + Page "eDP Fast Link Training Configuration" + + Link "Close Table" , ".." + Combo $Fast_Link_Training_Supported_01, " Is FastLinkTraining Feature Supported:", &No_Yes_List, + Help "This feature if set to Yes will enable " + "Fast Link Training for eDp, if Panel also supports it." + + Combo $eDP_Link_DataRate_01, " Data Rate:", &eDP_Link_DataRate_List, + Help "This feature allows for the selection of the " + "Data Rate for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + Combo $eDP_Link_LaneCount_01, " Lane Count:", &eDP_Link_LaneCount_List, + Help "This feature allows for the selection of the " + "Lane Count (Port Width) for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + Combo $eDP_Link_PreEmp_01, " Pre-Emphasis:", &eDP_Link_PreEmp_List, + Help "This feature allows for the selection of the " + "Pre-emphasis value for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" + "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" + "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" + "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" + "------------------------------------------------------------------------------------------------------------ \r\n" + + "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" + "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" + "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" + "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" + "------------------------------------------------------------------------------------------------------------ \r\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + Combo $eDP_Link_Vswing_01, " Voltage Swing:", &eDP_Link_VSwing_List, + Help "This feature allows for the selection of the " + "Voltage Swing value for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" + "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" + "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" + "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" + "------------------------------------------------------------------------------------------------------------ \r\n" + + "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" + "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" + "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" + "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" + "------------------------------------------------------------------------------------------------------------ \r\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + EndPage + #endif + Page "DTD Timings" + + Link "Close Table" , ".." + + Table $DVO_Tbl_01 " DTD Timings Values", + Column "Timings" , 1 byte , EHEX, + Help "This feature allows for the definition of the DTD " + "timings parameters related to the LFP. The " + "table is the 18-byte DTD structure defined in the " + "VESA EDID version 1.x.\r\n" + "\r\n" + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" + "\tDB ?\t; Vertical Active in lines, LSB\r\n" + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Horizontal Image Size, LSB\r\n" + "\tDB ?\t; Vertical Image Size, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" + "\tDB 0\t; Horizontal Border in pixels\r\n" + "\tDB 0\t; Vertical Border in lines\r\n" + "\tDB ?\t; Flags:\r\n" + "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" + "\t \t; Bit 6-5: 00 = Reserved\r\n" + "\t \t; Bit 4-3: 11 = Digital Separate\r\n" + "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 0: 0 = Reserved" + + EndPage + + Page "LFP PnP ID" + + Link "Close Table" , ".." + + Table $LVDS_PnP_ID_01 " LFP PnP ID Values", + Column "PnP ID" , 1 byte , EHEX, + Help "This feature allows the 10 bytes of EDID Vendor / " + "Product ID starting at offset 08h to be used as a " + "PnP ID.\r\n" + "\r\n" + " Table Definition:\r\n" + " Word: ID Manufacturer Name\r\n" + " Word: ID Product Code\r\n" + " DWord: ID Serial Number\r\n" + " Byte: Week of Manufacture\r\n" + " Byte: Year of Manufacture" + + EndPage + + Page "Backlight Control Parameters" + + Link "Close Table" , ".." + + Combo $BLC_Inv_Type_1, " Inverter Type:", &Inv_Type_List, + Help "This feature allows for the selection of the " + "Backlight Inverter type that is to be used to " + "control the backlight brightness of the LFP. When " + "PWM is selected, the driver and VBIOS will control " + "the backlight brightness via the integrated PWM " + "solution for the applicable chipsets. When I2C is " + "selected, the driver and VBIOS will control the " + "backlight brightness via the I2C solution for the " + "applicable chipsets. When None/External is " + "selected, the system BIOS will control the backlight " + "brightness via the external solution." + + Combo $Lfp_Pwm_Source_Selection_01, " Pwm Source Selection:", &Edp_Pwm_Source_List, + Help "This field allows to select the Source of the PWM to be used " + "for the selected Local Flat Panel.\r\n" + "\r\n" + + Combo $BLC_Inv_Polarity_1, " Inverter Polarity:", &Inv_Polarity_List, + Help "This feature allows the backlight inverter polarity " + "to be specified.\r\n" + "\r\n" + "Normal means 0 value is minimum brightness.\r\n" + "Inverted means 0 value is maximum brightness." + + EditNum $BLC_Min_Brightness_1, " Minimum Brightness:", DEC, + Help "This feature allows defining the absolute minimum " + "backlight brightness setting. The graphics driver " + "will never decrease the backlight less than this " + "value. The value must be specified using normal " + "polarity semantics." + + EditNum $POST_BL_Brightness_01, " POST Backlight Intensity:", DEC, + Help "This feature is used to set default brightness value at POST." + "This is configurable field of 0-255. Value of 0 indicates 0 brightness, 255 indicates maximum brightness. " + + EditNum $PWM_Frequency_1, " PWM Inverter Frequency (Hz):", DEC, + Help "This feature allows for the definition of the " + "frequency needed for PWM Inverter.\r\n" + "\r\n" + "Note: The frequency range, entered as a decimal " + "number, for the integrated PWM is 200Hz - 40KHz." + + EndPage + Page "Chromaticity Control" + Link "Close Table" , ".." + + Combo $Chromacity_Enable_1, "Chromaticity Control Feature", &Disabled_Enabled_List, + Help " This bit enables Chromaticity feature. \r\n" + " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" + " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" + " Please refer to section 3.7 of EDID Specification 1.4" + Combo $Override_EDID_Data_1, "Override the EDID values", &No_Yes_List, + Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" + EditNum $Red_Green_1, " Red_Green_bits (Bits 1&0 at 19h)" , EHEX, + Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" + EditNum $Blue_White_1, " Blue_White_bits (Bits 1&0 at 1Ah)" , EHEX, + Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" + EditNum $Red_x_1, " Red_x (Bits 9->2 at 1Bh)" , EHEX, + Help " Bits 9->2 of red color x coordinate" + EditNum $Red_y_1, " Red_y (Bits 9->2 at 1Ch)" , EHEX, + Help " Bits 9->2 of red color y coordinate" + EditNum $Green_x_1, " Green_x (Bits 9->2 at 1Dh)" , EHEX, + Help " Bits 9->2 of Green color x coordinate" + EditNum $Green_y_1, " Green_y (Bits 9->2 at 1Eh)" , EHEX, + Help " Bits 9->2 of Green color y coordinate" + EditNum $Blue_x_1, " Blue_x (Bits 9->2 at 1Fh)" , EHEX, + Help " Bits 9->2 of Blue color x coordinate" + EditNum $Blue_y_1, " Blue_y (Bits 9->2 at 20h)" , EHEX, + Help " Bits 9->2 of Blue color y coordinate" + EditNum $White_x_1, " White_x (Bits 9->2 at 21h)" , EHEX, + Help " Bits 9->2 of White color x coordinate" + EditNum $White_y_1, " White_y (Bits 9->2 at 22h)" , EHEX, + Help " Bits 9->2 of White color y coordinate" + + EndPage ; Chromaticity Control + + + + +EndPage + +;============================================================================== +; Page - Panel #2 (800x600) Flat Panel parameters +;------------------------------------------------------------------------------ + +Page "Panel #2 " + + TitleB "Common LFP Features" + + EditText $Panel_Name_02, "\tLFP Panel Name:", + Help "This feature defines the LVDS panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated. " + + Combo $Enable_Scaling_02, "\tScale to Target Resolution:", &No_Yes_List, + Help "Selecting this feature will make the graphics driver to enable Scaling feature by taking the Horizontal and Vertical resolution\r\n" + "from Target X-Res and Target Y-Res fields.\r\n" + + EditNum $Panel_Width_02, "\tTarget X-Res:", DEC, + Help "This value specifies the Target X-Resolution for this panel." + + EditNum $Panel_Height_02, "\tTarget Y-Res:", DEC, + Help "This value specifies the Target Y-Resolutoin for this panel." + + + Combo $DPS_Panel_Type_02, " \tDPS Panel Type:", &DPS_Panel_Type_List, + Help "This feature allows OEM to select the DPS Panel Type.\r\n " + "Intel SDRRS Technology is a feature of the Intel graphics driver\r\n" + "which reduces display power\r\n" + "SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n" + "rate will not adversely impact the user experience\r\n" + "Seamless:- Allows power savings when on battery mode and when a lower refresh\r\n" + "rate will not adversely impact the user experience.Implements seamless refresh\r\n" + "rate switching, which eliminates the screen blink that occurred\r\n" + "during the refresh rate transitions\r\n" + + EditNum $Seamless_DRRS_Min_RR_02, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, + Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n\n" + "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" + + Combo $Blt_Control_02, "\tBackLight Technology:", &Blt_Control_Type_List, + Help "This feature allows OEM to select the Backlight Technology.\r\n " + + Title " " + Link "LFP PnP ID Table" , "LFP PnP ID" + Link "DTD Timings Table" , "DTD Timings" + Link "Backlight Control Parameters" , "Backlight Control Parameters" + Link "Chromaticity Control" , "Chromaticity Control" + + + + #if ($Int_LFP1_Type == 0x1806) + TitleB "Integrated eDP Features" + + + Combo $Enable_SSC02, " \teDP Spread Spectrum Clock:", &Disabled_Enabled_List, + Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " + Combo $eDP_Panel_Color_Depth_02, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, + Help "This feature specifies the color depth of eDP panel used. " + + Combo $eDP_VSwingPreEmph_2, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, + Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " + "For CherryTrail, based on the selection respective table will be used.\r\n" + "Tables for CherryTrail:-\r\n" + "------------------------------------------------------------------------------------------------------\n" + "|Low Power VSwing Pre-Emphasis Setting Table |\n" + "-----------------------------------------------------------------------------------------------------|\n" + "| | Pre-Emphasis (db) |\n" + "| |------------------------------------------------------------------------------------------|\n" + "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" + "| Voltage |------------------------------------------------------------------------- ---------------|\n" + "| Swing | Level 0/200 | 200mV,0db | 200mV,3.5db | 200mV,6db | 200mV,9db |\n" + "| (mV) |------------------------------------------------------------------------------------------|\n" + "| | Level 1/250 | 250mV,0db | 250mV,3.5db | 250mV,6db | NA |\n" + "| |------------------------------------------------------------------------------------------|\n" + "| | Level 2/300 | 300mV,0db | 300mV,3.5d | NA | NA |\n" + "| |------------------------------------------------------------------------------------------|\n" + "| | Level 3/350 | 350 mv, 0db | NA | NA | NA |\n" + "-----------------------------------------------------------------------------------------------------\n\n" + + "-----------------------------------------------------------------------------------------------------\n" + "|Default VSwing Pre-Emphasis Setting Table |\n" + "---------------------------------------------------------------------------------------------------|\n" + "| | Pre-Emphasis (db) |\n" + "| |----------------------------------------------------------------------------------------|\n" + "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" + "| Voltage |----------------------------------------------------------------------------------------|\n" + "| Swing | Level 0/400 | 400mV,0db | 400mV,3.5db | 400mV,6db | 400mV,9db |\n" + "| (mV) |----------------------------------------------------------------------------------------|\n" + "| | Level 1/600 | 600mV,0db | 600mV,3.5db | 600mV,6db | NA |\n" + "| |----------------------------------------------------------------------------------------|\n" + "| | Level 2/800 | 800mV,0db | 800mV,3.5db | NA | NA |\n" + "| |----------------------------------------------------------------------------------------|\n" + "| | Level 3/1200| 1200mV, 0db | NA | NA | NA |\n" + "-----------------------------------------------------------------------------------------------------\n\n" + + + Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Power Sequencing" + Link "eDP Fast Link Training Configuration" , "eDP Fast Link Training Configuration" + + Page "eDP Panel Power Sequencing" + Link "Close Table", ".." + + Combo $eDP_T3_Optimization_02, "T3 optimization", &Disabled_Enabled_List, + Help "This feature enables or disables T3 optimization. \r\n" + "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" + "When disabled, VBIOS/Graphics driver will wait for T3 time before trying the first AUX transaction" + + EditNum $eDP_Vcc_To_Hpd_Delay_02, "LCDVCC to HPD high delay (T3):", DEC, + Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" + "Valid Range: 0 to 200msec\r\n" + + EditNum $eDP_DataOn_To_BkltEnable_Delay_02, "Valid video data to Backlight Enable delay (T8):", DEC, + Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" + "T8 is inclusive of T7.\r\n" + "Valid Range of T7: 0 to 50msec\r\n" + + EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_02, "PWM-On To Backlight Enable delay:", DEC, + Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" + "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" + "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" + + EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_02, "Backlight Disable to PWM-Off delay:", DEC, + Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" + "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" + "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" + + EditNum $eDP_BkltDisable_To_DataOff_Delay_02, "Backlight Disable to End of Valid video data delay (T9):", DEC, + Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" + + EditNum $eDP_DataOff_To_PowerOff_Delay_02, "End of Valid video data to Power-Off delay (T10):", DEC, + Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" + "Valid Range: 0 to 500 msec\r\n" + + EditNum $eDP_PowerCycle_Delay_02, "Power-off time (T12):", DEC, + Help "Using this field Power-off time can be specified in 100uS.\r\n" + + EndPage + + Page "eDP Fast Link Training Configuration" + + Link "Close Table" , ".." + Combo $Fast_Link_Training_Supported_02, " Is FastLinkTraining Feature Supported:", &No_Yes_List, + Help "This feature if set to Yes will enable " + "Fast Link Training for eDp, if Panel also supports it." + + Combo $eDP_Link_DataRate_02, " Data Rate:", &eDP_Link_DataRate_List, + Help "This feature allows for the selection of the " + "Data Rate for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + Combo $eDP_Link_LaneCount_02, " Lane Count:", &eDP_Link_LaneCount_List, + Help "This feature allows for the selection of the " + "Lane Count (Port Width) for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + Combo $eDP_Link_PreEmp_02, " Pre-Emphasis:", &eDP_Link_PreEmp_List, + Help "This feature allows for the selection of the " + "Pre-emphasis value for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" + "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" + "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" + "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" + "------------------------------------------------------------------------------------------------------------ \r\n" + + "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" + "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" + "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" + "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" + "------------------------------------------------------------------------------------------------------------ \r\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + Combo $eDP_Link_Vswing_02, " Voltage Swing:", &eDP_Link_VSwing_List, + Help "This feature allows for the selection of the " + "Voltage Swing value for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" + "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" + "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" + "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" + "------------------------------------------------------------------------------------------------------------ \r\n" + + "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" + "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" + "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" + "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" + "------------------------------------------------------------------------------------------------------------ \r\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + EndPage + #endif + + Page "DTD Timings" + + Link "Close Table" , ".." + + Table $DVO_Tbl_02 " DTD Timings Values", + Column "Timings" , 1 byte , EHEX, + Help "This feature allows for the definition of the DTD " + "timings parameters related to the LFP. The " + "table is the 18-byte DTD structure defined in the " + "VESA EDID version 1.x.\r\n" + "\r\n" + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" + "\tDB ?\t; Vertical Active in lines, LSB\r\n" + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Horizontal Image Size, LSB\r\n" + "\tDB ?\t; Vertical Image Size, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" + "\tDB 0\t; Horizontal Border in pixels\r\n" + "\tDB 0\t; Vertical Border in lines\r\n" + "\tDB ?\t; Flags:\r\n" + "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" + "\t \t; Bit 6-5: 00 = Reserved\r\n" + "\t \t; Bit 4-3: 11 = Digital Separate\r\n" + "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 0: 0 = Reserved" + + EndPage + + Page "LFP PnP ID" + + Link "Close Table" , ".." + + Table $LVDS_PnP_ID_02 " LFP PnP ID Values", + Column "PnP ID" , 1 byte , EHEX, + Help "This feature allows the 10 bytes of EDID Vendor / " + "Product ID starting at offset 08h to be used as a " + "PnP ID.\r\n" + "\r\n" + " Table Definition:\r\n" + " Word: ID Manufacturer Name\r\n" + " Word: ID Product Code\r\n" + " DWord: ID Serial Number\r\n" + " Byte: Week of Manufacture\r\n" + " Byte: Year of Manufacture" + + EndPage + + Page "Backlight Control Parameters" + + Link "Close Table" , ".." + + Combo $BLC_Inv_Type_2, " Inverter Type:", &Inv_Type_List, + Help "This feature allows for the selection of the " + "Backlight Inverter type that is to be used to " + "control the backlight brightness of the LFP. When " + "PWM is selected, the driver and VBIOS will control " + "the backlight brightness via the integrated PWM " + "solution for the applicable chipsets. When I2C is " + "selected, the driver and VBIOS will control the " + "backlight brightness via the I2C solution for the " + "applicable chipsets. When None/External is " + "selected, the system BIOS will control the backlight " + "brightness via the external solution." + + Combo $Lfp_Pwm_Source_Selection_02, " Pwm Source Selection:", &Edp_Pwm_Source_List, + Help "This field allows to select the Source of the PWM to be used " + "for the selected Local Flat Panel.\r\n" + "\r\n" + + Combo $BLC_Inv_Polarity_2, " Inverter Polarity:", &Inv_Polarity_List, + Help "This feature allows the backlight inverter polarity " + "to be specified.\r\n" + "\r\n" + "Normal means 0 value is minimum brightness.\r\n" + "Inverted means 0 value is maximum brightness." + + EditNum $BLC_Min_Brightness_2, " Minimum Brightness:", DEC, + Help "This feature allows defining the absolute minimum " + "backlight brightness setting. The graphics driver " + "will never decrease the backlight less than this " + "value. The value must be specified using normal " + "polarity semantics." + + EditNum $POST_BL_Brightness_02, " POST Backlight Intensity:", DEC, + Help "This feature is used to set default brightness value at POST." + "This is configurable field of 0-255. Value of 0 indicates 0 brightness, 255 indicates maximum brightness. " + + EditNum $PWM_Frequency_2, " PWM Inverter Frequency (Hz):", DEC, + Help "This feature allows for the definition of the " + "frequency needed for PWM Inverter.\r\n" + "\r\n" + "Note: The frequency range, entered as a decimal " + "number, for the integrated PWM is 200Hz - 40KHz." + EndPage + + Page "Chromaticity Control" + Link "Close Table" , ".." + + Combo $Chromacity_Enable_2, "Chromaticity Control Feature", &Disabled_Enabled_List, + Help " This bit enables Chromaticity feature. \r\n" + " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" + " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" + " Please refer to section 3.7 of EDID Specification 1.4" + Combo $Override_EDID_Data_2, "Override the EDID values", &No_Yes_List, + Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" + EditNum $Red_Green_2, " Red_Green_bits (Bits 1&0 at 19h)" , EHEX, + Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" + EditNum $Blue_White_2, " Blue_White_bits (Bits 1&0 at 20h)" , EHEX, + Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" + EditNum $Red_x_2, " Red_x (Bits 9->2 at 1Bh)" , EHEX, + Help " Bits 9->2 of red color x coordinate" + EditNum $Red_y_2, " Red_y (Bits 9->2 at 1Ch)" , EHEX, + Help " Bits 9->2 of red color y coordinate" + EditNum $Green_x_2, " Green_x (Bits 9->2 at 1Dh)" , EHEX, + Help " Bits 9->2 of Green color x coordinate" + EditNum $Green_y_2, " Green_y (Bits 9->2 at 1Eh)" , EHEX, + Help " Bits 9->2 of Green color y coordinate" + EditNum $Blue_x_2, " Blue_x (Bits 9->2 at 1Fh)" , EHEX, + Help " Bits 9->2 of Blue color x coordinate" + EditNum $Blue_y_2, " Blue_y (Bits 9->2 at 20h)" , EHEX, + Help " Bits 9->2 of Blue color y coordinate" + EditNum $White_x_2, " White_x (Bits 9->2 at 21h)" , EHEX, + Help " Bits 9->2 of White color x coordinate" + EditNum $White_y_2, " White_y (Bits 9->2 at 22h)" , EHEX, + Help " Bits 9->2 of White color y coordinate" + + EndPage ; Chromaticity Control + + +EndPage + + +;============================================================================== +; Page - Panel #3 (1024x768 LVDS) Flat Panel parameters +;------------------------------------------------------------------------------ + +Page "Panel #3 " + + TitleB "Common LFP Features" + + EditText $Panel_Name_03, "\tLFP Panel Name:", + Help "This feature defines the LVDS panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated. " + + Combo $Enable_Scaling_03, "\tScale to Target Resolution:", &No_Yes_List, + Help "Selecting this feature will make the graphics driver to enable Scaling feature by taking the Horizontal and Vertical resolution\r\n" + "from Target X-Res and Target Y-Res fields.\r\n" + + EditNum $Panel_Width_03, "\tTarget X-Res:", DEC, + Help "This value specifies the Target X-Resolution for this panel." + + EditNum $Panel_Height_03, "\tTarget Y-Res:", DEC, + Help "This value specifies the Target Y-Resolutoin for this panel." + + + Combo $DPS_Panel_Type_03, " \tDPS Panel Type:", &DPS_Panel_Type_List, + Help "This feature allows OEM to select the DPS Panel Type.\r\n " + "Intel SDRRS Technology is a feature of the Intel graphics driver\r\n" + "which reduces display power\r\n" + "SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n" + "rate will not adversely impact the user experience\r\n" + "Seamless:- Allows power savings when on battery mode and when a lower refresh\r\n" + "rate will not adversely impact the user experience.Implements seamless refresh\r\n" + "rate switching, which eliminates the screen blink that occurred\r\n" + "during the refresh rate transitions\r\n" + + EditNum $Seamless_DRRS_Min_RR_03, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, + Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n\n" + "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" + + Combo $Blt_Control_03, "\tBackLight Technology:", &Blt_Control_Type_List, + Help "This feature allows OEM to select the Backlight Technology.\r\n " + + Title " " + Link "LFP PnP ID Table" , "LFP PnP ID" + Link "DTD Timings Table" , "DTD Timings" + Link "Backlight Control Parameters" , "Backlight Control Parameters" + Link "Chromaticity Control" , "Chromaticity Control" + + + + #if ($Int_LFP1_Type == 0x1806) + TitleB "Integrated eDP Features" + + + Combo $Enable_SSC03, " \teDP Spread Spectrum Clock:", &Disabled_Enabled_List, + Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " + + + Combo $eDP_Panel_Color_Depth_03, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, + Help "This feature specifies the color depth of eDP panel used. " + + Combo $eDP_VSwingPreEmph_3, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, + Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " + "For CherryTrail, based on the selection respective table will be used.\r\n" + "Tables for CherryTrail:-\r\n" + "------------------------------------------------------------------------------------------------------\n" + "|Low Power VSwing Pre-Emphasis Setting Table |\n" + "-----------------------------------------------------------------------------------------------------|\n" + "| | Pre-Emphasis (db) |\n" + "| |------------------------------------------------------------------------------------------|\n" + "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" + "| Voltage |------------------------------------------------------------------------- ---------------|\n" + "| Swing | Level 0/200 | 200mV,0db | 200mV,3.5db | 200mV,6db | 200mV,9db |\n" + "| (mV) |------------------------------------------------------------------------------------------|\n" + "| | Level 1/250 | 250mV,0db | 250mV,3.5db | 250mV,6db | NA |\n" + "| |------------------------------------------------------------------------------------------|\n" + "| | Level 2/300 | 300mV,0db | 300mV,3.5d | NA | NA |\n" + "| |------------------------------------------------------------------------------------------|\n" + "| | Level 3/350 | 350 mv, 0db | NA | NA | NA |\n" + "-----------------------------------------------------------------------------------------------------\n\n" + + "-----------------------------------------------------------------------------------------------------\n" + "|Default VSwing Pre-Emphasis Setting Table |\n" + "---------------------------------------------------------------------------------------------------|\n" + "| | Pre-Emphasis (db) |\n" + "| |----------------------------------------------------------------------------------------|\n" + "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" + "| Voltage |----------------------------------------------------------------------------------------|\n" + "| Swing | Level 0/400 | 400mV,0db | 400mV,3.5db | 400mV,6db | 400mV,9db |\n" + "| (mV) |----------------------------------------------------------------------------------------|\n" + "| | Level 1/600 | 600mV,0db | 600mV,3.5db | 600mV,6db | NA |\n" + "| |----------------------------------------------------------------------------------------|\n" + "| | Level 2/800 | 800mV,0db | 800mV,3.5db | NA | NA |\n" + "| |----------------------------------------------------------------------------------------|\n" + "| | Level 3/1200| 1200mV, 0db | NA | NA | NA |\n" + "-----------------------------------------------------------------------------------------------------\n\n" + + + Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Power Sequencing" + Link "eDP Fast Link Training Configuration" , "eDP Fast Link Training Configuration" + + Page "eDP Panel Power Sequencing" + Link "Close Table", ".." + + Combo $eDP_T3_Optimization_03, "T3 optimization", &Disabled_Enabled_List, + Help "This feature enables or disables T3 optimization. \r\n" + "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" + "When disabled, VBIOS/Graphics driver will wait for T3 time before trying the first AUX transaction" + + EditNum $eDP_Vcc_To_Hpd_Delay_03, "LCDVCC to HPD high delay (T3):", DEC, + Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" + "Valid Range: 0 to 200msec\r\n" + + EditNum $eDP_DataOn_To_BkltEnable_Delay_03, "Valid video data to Backlight Enable delay (T8):", DEC, + Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" + "T8 is inclusive of T7.\r\n" + "Valid Range of T7: 0 to 50msec\r\n" + + EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_03, "PWM-On To Backlight Enable delay:", DEC, + Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" + "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" + "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" + + EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_03, "Backlight Disable to PWM-Off delay:", DEC, + Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" + "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" + "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" + + EditNum $eDP_BkltDisable_To_DataOff_Delay_03, "Backlight Disable to End of Valid video data delay (T9):", DEC, + Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" + + EditNum $eDP_DataOff_To_PowerOff_Delay_03, "End of Valid video data to Power-Off delay (T10):", DEC, + Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" + "Valid Range: 0 to 500 msec\r\n" + + EditNum $eDP_PowerCycle_Delay_03, "Power-off time (T12):", DEC, + Help "Using this field Power-off time can be specified in 100uS.\r\n" + + EndPage + + Page "eDP Fast Link Training Configuration" + + Link "Close Table" , ".." + Combo $Fast_Link_Training_Supported_03, " Is FastLinkTraining Feature Supported:", &No_Yes_List, + Help "This feature if set to Yes will enable " + "Fast Link Training for eDp, if Panel also supports it." + + Combo $eDP_Link_DataRate_03, " Data Rate:", &eDP_Link_DataRate_List, + Help "This feature allows for the selection of the " + "Data Rate for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + Combo $eDP_Link_LaneCount_03, " Lane Count:", &eDP_Link_LaneCount_List, + Help "This feature allows for the selection of the " + "Lane Count (Port Width) for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + Combo $eDP_Link_PreEmp_03, " Pre-Emphasis:", &eDP_Link_PreEmp_List, + Help "This feature allows for the selection of the " + "Pre-emphasis value for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" + "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" + "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" + "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" + "------------------------------------------------------------------------------------------------------------ \r\n" + + "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" + "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" + "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" + "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" + "------------------------------------------------------------------------------------------------------------ \r\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + Combo $eDP_Link_Vswing_03, " Voltage Swing:", &eDP_Link_VSwing_List, + Help "This feature allows for the selection of the " + "Voltage Swing value for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" + "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" + "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" + "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" + "------------------------------------------------------------------------------------------------------------ \r\n" + + "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" + "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" + "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" + "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" + "------------------------------------------------------------------------------------------------------------ \r\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + EndPage + #endif + + Page "DTD Timings" + + Link "Close Table" , ".." + + Table $DVO_Tbl_03 " DTD Timings Values", + Column "Timings" , 1 byte , EHEX, + Help "This feature allows for the definition of the DTD " + "timings parameters related to the LFP. The " + "table is the 18-byte DTD structure defined in the " + "VESA EDID version 1.x.\r\n" + "\r\n" + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" + "\tDB ?\t; Vertical Active in lines, LSB\r\n" + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Horizontal Image Size, LSB\r\n" + "\tDB ?\t; Vertical Image Size, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" + "\tDB 0\t; Horizontal Border in pixels\r\n" + "\tDB 0\t; Vertical Border in lines\r\n" + "\tDB ?\t; Flags:\r\n" + "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" + "\t \t; Bit 6-5: 00 = Reserved\r\n" + "\t \t; Bit 4-3: 11 = Digital Separate\r\n" + "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 0: 0 = Reserved" + + EndPage + + Page "LFP PnP ID" + + Link "Close Table" , ".." + + Table $LVDS_PnP_ID_03 " LFP PnP ID Values", + Column "PnP ID" , 1 byte , EHEX, + Help "This feature allows the 10 bytes of EDID Vendor / " + "Product ID starting at offset 08h to be used as a " + "PnP ID.\r\n" + "\r\n" + " Table Definition:\r\n" + " Word: ID Manufacturer Name\r\n" + " Word: ID Product Code\r\n" + " DWord: ID Serial Number\r\n" + " Byte: Week of Manufacture\r\n" + " Byte: Year of Manufacture" + + EndPage + + Page "Backlight Control Parameters" + + Link "Close Table" , ".." + + Combo $BLC_Inv_Type_3, " Inverter Type:", &Inv_Type_List, + Help "This feature allows for the selection of the " + "Backlight Inverter type that is to be used to " + "control the backlight brightness of the LFP. When " + "PWM is selected, the driver and VBIOS will control " + "the backlight brightness via the integrated PWM " + "solution for the applicable chipsets. When I2C is " + "selected, the driver and VBIOS will control the " + "backlight brightness via the I2C solution for the " + "applicable chipsets. When None/External is " + "selected, the system BIOS will control the backlight " + "brightness via the external solution." + + Combo $Lfp_Pwm_Source_Selection_03, " Pwm Source Selection:", &Edp_Pwm_Source_List, + Help "This field allows to select the Source of the PWM to be used " + "for the selected Local Flat Panel.\r\n" + "\r\n" + + Combo $BLC_Inv_Polarity_3, " Inverter Polarity:", &Inv_Polarity_List, + Help "This feature allows the backlight inverter polarity " + "to be specified.\r\n" + "\r\n" + "Normal means 0 value is minimum brightness.\r\n" + "Inverted means 0 value is maximum brightness." + + EditNum $BLC_Min_Brightness_3, " Minimum Brightness:", DEC, + Help "This feature allows defining the absolute minimum " + "backlight brightness setting. The graphics driver " + "will never decrease the backlight less than this " + "value. The value must be specified using normal " + "polarity semantics." + +EditNum $POST_BL_Brightness_03, " POST Backlight Intensity:", DEC, + Help "This feature is used to set default brightness value at POST." + "This is configurable field of 0-255. Value of 0 indicates 0 brightness, 255 indicates maximum brightness. " + + EditNum $PWM_Frequency_3, " PWM Inverter Frequency (Hz):", DEC, + Help "This feature allows for the definition of the " + "frequency needed for PWM Inverter.\r\n" + "\r\n" + "Note: The frequency range, entered as a decimal " + "number, for the integrated PWM is 200Hz - 40KHz." + EndPage + Page "Chromaticity Control" + Link "Close Table" , ".." + + Combo $Chromacity_Enable_3, "Chromaticity Control Feature", &Disabled_Enabled_List, + Help " This bit enables Chromaticity feature. \r\n" + " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" + " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" + " Please refer to section 3.7 of EDID Specification 1.4" + Combo $Override_EDID_Data_3, "Override the EDID values", &No_Yes_List, + Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" + EditNum $Red_Green_3, " Red_Green_bits (Bits 1&0 at 19h)" , EHEX, + Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" + EditNum $Blue_White_3, " Blue_White_bits (Bits 1&0 at 20h)" , EHEX, + Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" + EditNum $Red_x_3, " Red_x (Bits 9->2 at 1Bh)" , EHEX, + Help " Bits 9->2 of red color x coordinate" + EditNum $Red_y_3, " Red_y (Bits 9->2 at 1Ch)" , EHEX, + Help " Bits 9->2 of red color y coordinate" + EditNum $Green_x_3, " Green_x (Bits 9->2 at 1Dh)" , EHEX, + Help " Bits 9->2 of Green color x coordinate" + EditNum $Green_y_3, " Green_y (Bits 9->2 at 1Eh)" , EHEX, + Help " Bits 9->2 of Green color y coordinate" + EditNum $Blue_x_3, " Blue_x (Bits 9->2 at 1Fh)" , EHEX, + Help " Bits 9->2 of Blue color x coordinate" + EditNum $Blue_y_3, " Blue_y (Bits 9->2 at 20h)" , EHEX, + Help " Bits 9->2 of Blue color y coordinate" + EditNum $White_x_3, " White_x (Bits 9->2 at 21h)" , EHEX, + Help " Bits 9->2 of White color x coordinate" + EditNum $White_y_3, " White_y (Bits 9->2 at 22h)" , EHEX, + Help " Bits 9->2 of White color y coordinate" + + EndPage ; Chromaticity Control + + + +EndPage + + +;============================================================================== +; Page - Panel #4 (1280x1024 LVDS) Flat Panel parameters +;------------------------------------------------------------------------------ + +Page "Panel #4 " + + TitleB "Common LFP Features" + + EditText $Panel_Name_04, "\tLFP Panel Name:", + Help "This feature defines the LVDS panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated. " + + Combo $Enable_Scaling_04, "\tScale to Target Resolution:", &No_Yes_List, + Help "Selecting this feature will make the graphics driver to enable Scaling feature by taking the Horizontal and Vertical resolution\r\n" + "from Target X-Res and Target Y-Res fields.\r\n" + + EditNum $Panel_Width_04, "\tTarget X-Res:", DEC, + Help "This value specifies the Target X-Resolution for this panel." + + EditNum $Panel_Height_04, "\tTarget Y-Res:", DEC, + Help "This value specifies the Target Y-Resolutoin for this panel." + + + Combo $DPS_Panel_Type_04, " \tDPS Panel Type:", &DPS_Panel_Type_List, + Help "This feature allows OEM to select the DPS Panel Type.\r\n " + "Intel SDRRS Technology is a feature of the Intel graphics driver\r\n" + "which reduces display power\r\n" + "SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n" + "rate will not adversely impact the user experience\r\n" + "Seamless:- Allows power savings when on battery mode and when a lower refresh\r\n" + "rate will not adversely impact the user experience.Implements seamless refresh\r\n" + "rate switching, which eliminates the screen blink that occurred\r\n" + "during the refresh rate transitions\r\n" + + EditNum $Seamless_DRRS_Min_RR_04, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, + Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n\n" + "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" + + Combo $Blt_Control_04, "\tBackLight Technology:", &Blt_Control_Type_List, + Help "This feature allows OEM to select the Backlight Technology.\r\n " + + Title " " + Link "LFP PnP ID Table" , "LFP PnP ID" + Link "DTD Timings Table" , "DTD Timings" + Link "Backlight Control Parameters" , "Backlight Control Parameters" + Link "Chromaticity Control" , "Chromaticity Control" + + + + #if ($Int_LFP1_Type == 0x1806) + TitleB "Integrated eDP Features" + + + Combo $Enable_SSC04, " \teDP Spread Spectrum Clock:", &Disabled_Enabled_List, + Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " + + Combo $eDP_Panel_Color_Depth_04, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, + Help "This feature specifies the color depth of eDP panel used. " + + Combo $eDP_VSwingPreEmph_4, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, + Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " + "For CherryTrail, based on the selection respective table will be used.\r\n" + "Tables for CherryTrail:-\r\n" + "------------------------------------------------------------------------------------------------------\n" + "|Low Power VSwing Pre-Emphasis Setting Table |\n" + "-----------------------------------------------------------------------------------------------------|\n" + "| | Pre-Emphasis (db) |\n" + "| |------------------------------------------------------------------------------------------|\n" + "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" + "| Voltage |------------------------------------------------------------------------- ---------------|\n" + "| Swing | Level 0/200 | 200mV,0db | 200mV,3.5db | 200mV,6db | 200mV,9db |\n" + "| (mV) |------------------------------------------------------------------------------------------|\n" + "| | Level 1/250 | 250mV,0db | 250mV,3.5db | 250mV,6db | NA |\n" + "| |------------------------------------------------------------------------------------------|\n" + "| | Level 2/300 | 300mV,0db | 300mV,3.5d | NA | NA |\n" + "| |------------------------------------------------------------------------------------------|\n" + "| | Level 3/350 | 350 mv, 0db | NA | NA | NA |\n" + "-----------------------------------------------------------------------------------------------------\n\n" + + "-----------------------------------------------------------------------------------------------------\n" + "|Default VSwing Pre-Emphasis Setting Table |\n" + "---------------------------------------------------------------------------------------------------|\n" + "| | Pre-Emphasis (db) |\n" + "| |----------------------------------------------------------------------------------------|\n" + "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" + "| Voltage |----------------------------------------------------------------------------------------|\n" + "| Swing | Level 0/400 | 400mV,0db | 400mV,3.5db | 400mV,6db | 400mV,9db |\n" + "| (mV) |----------------------------------------------------------------------------------------|\n" + "| | Level 1/600 | 600mV,0db | 600mV,3.5db | 600mV,6db | NA |\n" + "| |----------------------------------------------------------------------------------------|\n" + "| | Level 2/800 | 800mV,0db | 800mV,3.5db | NA | NA |\n" + "| |----------------------------------------------------------------------------------------|\n" + "| | Level 3/1200| 1200mV, 0db | NA | NA | NA |\n" + "-----------------------------------------------------------------------------------------------------\n\n" + + + Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Power Sequencing" + Link "eDP Fast Link Training Configuration" , "eDP Fast Link Training Configuration" + + Page "eDP Panel Power Sequencing" + Link "Close Table", ".." + Combo $eDP_T3_Optimization_04, "T3 optimization", &Disabled_Enabled_List, + Help "This feature enables or disables T3 optimization. \r\n" + "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" + "When disabled, VBIOS/Graphics driver will wait for T3 time before trying the first AUX transaction" + + EditNum $eDP_Vcc_To_Hpd_Delay_04, "LCDVCC to HPD high delay (T3):", DEC, + Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" + "Valid Range: 0 to 200msec\r\n" + + EditNum $eDP_DataOn_To_BkltEnable_Delay_04, "Valid video data to Backlight Enable delay (T8):", DEC, + Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" + "T8 is inclusive of T7.\r\n" + "Valid Range of T7: 0 to 50msec\r\n" + + EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_04, "PWM-On To Backlight Enable delay:", DEC, + Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" + "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" + "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" + + EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_04, "Backlight Disable to PWM-Off delay:", DEC, + Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" + "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" + "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" + + EditNum $eDP_BkltDisable_To_DataOff_Delay_04, "Backlight Disable to End of Valid video data delay (T9):", DEC, + Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" + + EditNum $eDP_DataOff_To_PowerOff_Delay_04, "End of Valid video data to Power-Off delay (T10):", DEC, + Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" + "Valid Range: 0 to 500 msec\r\n" + + EditNum $eDP_PowerCycle_Delay_04, "Power-off time (T12):", DEC, + Help "Using this field Power-off time can be specified in 100uS.\r\n" + + EndPage + + Page "eDP Fast Link Training Configuration" + + Link "Close Table" , ".." + Combo $Fast_Link_Training_Supported_04, " Is FastLinkTraining Feature Supported:", &No_Yes_List, + Help "This feature if set to Yes will enable " + "Fast Link Training for eDp, if Panel also supports it." + + Combo $eDP_Link_DataRate_04, " Data Rate:", &eDP_Link_DataRate_List, + Help "This feature allows for the selection of the " + "Data Rate for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + Combo $eDP_Link_LaneCount_04, " Lane Count:", &eDP_Link_LaneCount_List, + Help "This feature allows for the selection of the " + "Lane Count (Port Width) for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + Combo $eDP_Link_PreEmp_04, " Pre-Emphasis:", &eDP_Link_PreEmp_List, + Help "This feature allows for the selection of the " + "Pre-emphasis value for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" + "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" + "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" + "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" + "------------------------------------------------------------------------------------------------------------ \r\n" + + "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" + "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" + "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" + "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" + "------------------------------------------------------------------------------------------------------------ \r\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + Combo $eDP_Link_Vswing_04, " Voltage Swing:", &eDP_Link_VSwing_List, + Help "This feature allows for the selection of the " + "Voltage Swing value for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" + "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" + "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" + "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" + "------------------------------------------------------------------------------------------------------------ \r\n" + + "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" + "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" + "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" + "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" + "------------------------------------------------------------------------------------------------------------ \r\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + EndPage + #endif + + Page "DTD Timings" + + Link "Close Table" , ".." + + Table $DVO_Tbl_04 " DTD Timings Values", + Column "Timings" , 1 byte , EHEX, + Help "This feature allows for the definition of the DTD " + "timings parameters related to the LFP. The " + "table is the 18-byte DTD structure defined in the " + "VESA EDID version 1.x.\r\n" + "\r\n" + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" + "\tDB ?\t; Vertical Active in lines, LSB\r\n" + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Horizontal Image Size, LSB\r\n" + "\tDB ?\t; Vertical Image Size, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" + "\tDB 0\t; Horizontal Border in pixels\r\n" + "\tDB 0\t; Vertical Border in lines\r\n" + "\tDB ?\t; Flags:\r\n" + "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" + "\t \t; Bit 6-5: 00 = Reserved\r\n" + "\t \t; Bit 4-3: 11 = Digital Separate\r\n" + "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 0: 0 = Reserved" + + EndPage + + Page "LFP PnP ID" + + Link "Close Table" , ".." + + Table $LVDS_PnP_ID_04 " LFP PnP ID Values", + Column "PnP ID" , 1 byte , EHEX, + Help "This feature allows the 10 bytes of EDID Vendor / " + "Product ID starting at offset 08h to be used as a " + "PnP ID.\r\n" + "\r\n" + " Table Definition:\r\n" + " Word: ID Manufacturer Name\r\n" + " Word: ID Product Code\r\n" + " DWord: ID Serial Number\r\n" + " Byte: Week of Manufacture\r\n" + " Byte: Year of Manufacture" + + EndPage + + Page "Backlight Control Parameters" + + Link "Close Table" , ".." + + Combo $BLC_Inv_Type_4, " Inverter Type:", &Inv_Type_List, + Help "This feature allows for the selection of the " + "Backlight Inverter type that is to be used to " + "control the backlight brightness of the LFP. When " + "PWM is selected, the driver and VBIOS will control " + "the backlight brightness via the integrated PWM " + "solution for the applicable chipsets. When I2C is " + "selected, the driver and VBIOS will control the " + "backlight brightness via the I2C solution for the " + "applicable chipsets. When None/External is " + "selected, the system BIOS will control the backlight " + "brightness via the external solution." + + Combo $Lfp_Pwm_Source_Selection_04, " Pwm Source Selection:", &Edp_Pwm_Source_List, + Help "This field allows to select the Source of the PWM to be used " + "for the selected Local Flat Panel.\r\n" + "\r\n" + + Combo $BLC_Inv_Polarity_4, " Inverter Polarity:", &Inv_Polarity_List, + Help "This feature allows the backlight inverter polarity " + "to be specified.\r\n" + "\r\n" + "Normal means 0 value is minimum brightness.\r\n" + "Inverted means 0 value is maximum brightness." + + EditNum $BLC_Min_Brightness_4, " Minimum Brightness:", DEC, + Help "This feature allows defining the absolute minimum " + "backlight brightness setting. The graphics driver " + "will never decrease the backlight less than this " + "value. The value must be specified using normal " + "polarity semantics." + +EditNum $POST_BL_Brightness_04, " POST Backlight Intensity:", DEC, + Help "This feature is used to set default brightness value at POST." + "This is configurable field of 0-255. Value of 0 indicates 0 brightness, 255 indicates maximum brightness. " + + EditNum $PWM_Frequency_4, " PWM Inverter Frequency (Hz):", DEC, + Help "This feature allows for the definition of the " + "frequency needed for PWM Inverter.\r\n" + "\r\n" + "Note: The frequency range, entered as a decimal " + "number, for the integrated PWM is 200Hz - 40KHz." + EndPage + Page "Chromaticity Control" + Link "Close Table" , ".." + + Combo $Chromacity_Enable_4, "Chromaticity Control Feature", &Disabled_Enabled_List, + Help " This bit enables Chromaticity feature. \r\n" + " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" + " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" + " Please refer to section 3.7 of EDID Specification 1.4" + Combo $Override_EDID_Data_4, "Override the EDID values", &No_Yes_List, + Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" + EditNum $Red_Green_4, " Red_Green_bits (Bits 1&0 at 19h)" , EHEX, + Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" + EditNum $Blue_White_4, " Blue_White_bits (Bits 1&0 at 20h)" , EHEX, + Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" + EditNum $Red_x_4, " Red_x (Bits 9->2 at 1Bh)" , EHEX, + Help " Bits 9->2 of red color x coordinate" + EditNum $Red_y_4, " Red_y (Bits 9->2 at 1Ch)" , EHEX, + Help " Bits 9->2 of red color y coordinate" + EditNum $Green_x_4, " Green_x (Bits 9->2 at 1Dh)" , EHEX, + Help " Bits 9->2 of Green color x coordinate" + EditNum $Green_y_4, " Green_y (Bits 9->2 at 1Eh)" , EHEX, + Help " Bits 9->2 of Green color y coordinate" + EditNum $Blue_x_4, " Blue_x (Bits 9->2 at 1Fh)" , EHEX, + Help " Bits 9->2 of Blue color x coordinate" + EditNum $Blue_y_4, " Blue_y (Bits 9->2 at 20h)" , EHEX, + Help " Bits 9->2 of Blue color y coordinate" + EditNum $White_x_4, " White_x (Bits 9->2 at 21h)" , EHEX, + Help " Bits 9->2 of White color x coordinate" + EditNum $White_y_4, " White_y (Bits 9->2 at 22h)" , EHEX, + Help " Bits 9->2 of White color y coordinate" + + EndPage ; Chromaticity Control + + + +EndPage + + +;============================================================================== +; Page - Panel #5 (1400x1050 LVDS - Reduced Blank) Flat Panel parameters +;------------------------------------------------------------------------------ + +Page "Panel #5 " + + TitleB "Common LFP Features" + + EditText $Panel_Name_05, "\tLFP Panel Name:", + Help "This feature defines the LVDS panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated. " + + Combo $Enable_Scaling_05, "\tScale to Target Resolution:", &No_Yes_List, + Help "Selecting this feature will make the graphics driver to enable Scaling feature by taking the Horizontal and Vertical resolution\r\n" + "from Target X-Res and Target Y-Res fields.\r\n" + + EditNum $Panel_Width_05, "\tTarget X-Res:", DEC, + Help "This value specifies the Target X-Resolution for this panel." + + EditNum $Panel_Height_05, "\tTarget Y-Res:", DEC, + Help "This value specifies the Target Y-Resolutoin for this panel." + + + Combo $DPS_Panel_Type_05, " \tDPS Panel Type:", &DPS_Panel_Type_List, + Help "This feature allows OEM to select the DPS Panel Type.\r\n " + "Intel SDRRS Technology is a feature of the Intel graphics driver\r\n" + "which reduces display power\r\n" + "SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n" + "rate will not adversely impact the user experience\r\n" + "Seamless:- Allows power savings when on battery mode and when a lower refresh\r\n" + "rate will not adversely impact the user experience.Implements seamless refresh\r\n" + "rate switching, which eliminates the screen blink that occurred\r\n" + "during the refresh rate transitions\r\n" + + EditNum $Seamless_DRRS_Min_RR_05, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, + Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n\n" + "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" + + Combo $Blt_Control_05, "\tBackLight Technology:", &Blt_Control_Type_List, + Help "This feature allows OEM to select the Backlight Technology.\r\n " + + Title " " + Link "LFP PnP ID Table" , "LFP PnP ID" + Link "DTD Timings Table" , "DTD Timings" + Link "Backlight Control Parameters" , "Backlight Control Parameters" + Link "Chromaticity Control" , "Chromaticity Control" + + + #if ($Int_LFP1_Type == 0x1806) + TitleB "Integrated eDP Features" + Combo $Enable_SSC05, " \teDP Spread Spectrum Clock:", &Disabled_Enabled_List, + Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " + + + + Combo $eDP_Panel_Color_Depth_05, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, + Help "This feature specifies the color depth of eDP panel used. " + + Combo $eDP_VSwingPreEmph_5, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, + Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " + "For CherryTrail, based on the selection respective table will be used.\r\n" + "Tables for CherryTrail:-\r\n" + "------------------------------------------------------------------------------------------------------\n" + "|Low Power VSwing Pre-Emphasis Setting Table |\n" + "-----------------------------------------------------------------------------------------------------|\n" + "| | Pre-Emphasis (db) |\n" + "| |------------------------------------------------------------------------------------------|\n" + "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" + "| Voltage |------------------------------------------------------------------------- ---------------|\n" + "| Swing | Level 0/200 | 200mV,0db | 200mV,3.5db | 200mV,6db | 200mV,9db |\n" + "| (mV) |------------------------------------------------------------------------------------------|\n" + "| | Level 1/250 | 250mV,0db | 250mV,3.5db | 250mV,6db | NA |\n" + "| |------------------------------------------------------------------------------------------|\n" + "| | Level 2/300 | 300mV,0db | 300mV,3.5d | NA | NA |\n" + "| |------------------------------------------------------------------------------------------|\n" + "| | Level 3/350 | 350 mv, 0db | NA | NA | NA |\n" + "-----------------------------------------------------------------------------------------------------\n\n" + + "-----------------------------------------------------------------------------------------------------\n" + "|Default VSwing Pre-Emphasis Setting Table |\n" + "---------------------------------------------------------------------------------------------------|\n" + "| | Pre-Emphasis (db) |\n" + "| |----------------------------------------------------------------------------------------|\n" + "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" + "| Voltage |----------------------------------------------------------------------------------------|\n" + "| Swing | Level 0/400 | 400mV,0db | 400mV,3.5db | 400mV,6db | 400mV,9db |\n" + "| (mV) |----------------------------------------------------------------------------------------|\n" + "| | Level 1/600 | 600mV,0db | 600mV,3.5db | 600mV,6db | NA |\n" + "| |----------------------------------------------------------------------------------------|\n" + "| | Level 2/800 | 800mV,0db | 800mV,3.5db | NA | NA |\n" + "| |----------------------------------------------------------------------------------------|\n" + "| | Level 3/1200| 1200mV, 0db | NA | NA | NA |\n" + "-----------------------------------------------------------------------------------------------------\n\n" + + + Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Power Sequencing" + Link "eDP Fast Link Training Configuration" , "eDP Fast Link Training Configuration" + + + Page "eDP Panel Power Sequencing" + Link "Close Table", ".." + Combo $eDP_T3_Optimization_05, "T3 optimization", &Disabled_Enabled_List, + Help "This feature enables or disables T3 optimization. \r\n" + "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" + "When disabled, VBIOS/Graphics driver will wait for T3 time before trying the first AUX transaction" + + EditNum $eDP_Vcc_To_Hpd_Delay_05, "LCDVCC to HPD high delay (T3):", DEC, + Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" + "Valid Range: 0 to 200msec\r\n" + + EditNum $eDP_DataOn_To_BkltEnable_Delay_05, "Valid video data to Backlight Enable delay (T8):", DEC, + Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" + "T8 is inclusive of T7.\r\n" + "Valid Range of T7: 0 to 50msec\r\n" + + EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_05, "PWM-On To Backlight Enable delay:", DEC, + Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" + "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" + "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" + + EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_05, "Backlight Disable to PWM-Off delay:", DEC, + Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" + "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" + "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" + + EditNum $eDP_BkltDisable_To_DataOff_Delay_05, "Backlight Disable to End of Valid video data delay (T9):", DEC, + Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" + + EditNum $eDP_DataOff_To_PowerOff_Delay_05, "End of Valid video data to Power-Off delay (T10):", DEC, + Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" + "Valid Range: 0 to 500 msec\r\n" + + EditNum $eDP_PowerCycle_Delay_05, "Power-off time (T12):", DEC, + Help "Using this field Power-off time can be specified in 100uS.\r\n" + + EndPage + + Page "eDP Fast Link Training Configuration" + + Link "Close Table" , ".." + Combo $Fast_Link_Training_Supported_05, " Is FastLinkTraining Feature Supported:", &No_Yes_List, + Help "This feature if set to Yes will enable " + "Fast Link Training for eDp, if Panel also supports it." + + Combo $eDP_Link_DataRate_05, " Data Rate:", &eDP_Link_DataRate_List, + Help "This feature allows for the selection of the " + "Data Rate for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + Combo $eDP_Link_LaneCount_05, " Lane Count:", &eDP_Link_LaneCount_List, + Help "This feature allows for the selection of the " + "Lane Count (Port Width) for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + Combo $eDP_Link_PreEmp_05, " Pre-Emphasis:", &eDP_Link_PreEmp_List, + Help "This feature allows for the selection of the " + "Pre-emphasis value for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" + "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" + "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" + "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" + "------------------------------------------------------------------------------------------------------------ \r\n" + + "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" + "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" + "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" + "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" + "------------------------------------------------------------------------------------------------------------ \r\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + Combo $eDP_Link_Vswing_05, " Voltage Swing:", &eDP_Link_VSwing_List, + Help "This feature allows for the selection of the " + "Voltage Swing value for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" + "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" + "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" + "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" + "------------------------------------------------------------------------------------------------------------ \r\n" + + "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" + "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" + "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" + "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" + "------------------------------------------------------------------------------------------------------------ \r\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + EndPage + #endif + + Page "DTD Timings" + + Link "Close Table" , ".." + + Table $DVO_Tbl_05 " DTD Timings Values", + Column "Timings" , 1 byte , EHEX, + Help "This feature allows for the definition of the DTD " + "timings parameters related to the LFP. The " + "table is the 18-byte DTD structure defined in the " + "VESA EDID version 1.x.\r\n" + "\r\n" + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" + "\tDB ?\t; Vertical Active in lines, LSB\r\n" + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Horizontal Image Size, LSB\r\n" + "\tDB ?\t; Vertical Image Size, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" + "\tDB 0\t; Horizontal Border in pixels\r\n" + "\tDB 0\t; Vertical Border in lines\r\n" + "\tDB ?\t; Flags:\r\n" + "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" + "\t \t; Bit 6-5: 00 = Reserved\r\n" + "\t \t; Bit 4-3: 11 = Digital Separate\r\n" + "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 0: 0 = Reserved" + + EndPage + + Page "LFP PnP ID" + + Link "Close Table" , ".." + + Table $LVDS_PnP_ID_05 " LFP PnP ID Values", + Column "PnP ID" , 1 byte , EHEX, + Help "This feature allows the 10 bytes of EDID Vendor / " + "Product ID starting at offset 08h to be used as a " + "PnP ID.\r\n" + "\r\n" + " Table Definition:\r\n" + " Word: ID Manufacturer Name\r\n" + " Word: ID Product Code\r\n" + " DWord: ID Serial Number\r\n" + " Byte: Week of Manufacture\r\n" + " Byte: Year of Manufacture" + + EndPage + + Page "Backlight Control Parameters" + + Link "Close Table" , ".." + + Combo $BLC_Inv_Type_5, " Inverter Type:", &Inv_Type_List, + Help "This feature allows for the selection of the " + "Backlight Inverter type that is to be used to " + "control the backlight brightness of the LFP. When " + "PWM is selected, the driver and VBIOS will control " + "the backlight brightness via the integrated PWM " + "solution for the applicable chipsets. When I2C is " + "selected, the driver and VBIOS will control the " + "backlight brightness via the I2C solution for the " + "applicable chipsets. When None/External is " + "selected, the system BIOS will control the backlight " + "brightness via the external solution." + + Combo $Lfp_Pwm_Source_Selection_05, " Pwm Source Selection:", &Edp_Pwm_Source_List, + Help "This field allows to select the Source of the PWM to be used " + "for the selected Local Flat Panel.\r\n" + "\r\n" + + Combo $BLC_Inv_Polarity_5, " Inverter Polarity:", &Inv_Polarity_List, + Help "This feature allows the backlight inverter polarity " + "to be specified.\r\n" + "\r\n" + "Normal means 0 value is minimum brightness.\r\n" + "Inverted means 0 value is maximum brightness." + + EditNum $BLC_Min_Brightness_5, " Minimum Brightness:", DEC, + Help "This feature allows defining the absolute minimum " + "backlight brightness setting. The graphics driver " + "will never decrease the backlight less than this " + "value. The value must be specified using normal " + "polarity semantics." + +EditNum $POST_BL_Brightness_05, " POST Backlight Intensity:", DEC, + Help "This feature is used to set default brightness value at POST." + "This is configurable field of 0-255. Value of 0 indicates 0 brightness, 255 indicates maximum brightness. " + + EditNum $PWM_Frequency_5, " PWM Inverter Frequency (Hz):", DEC, + Help "This feature allows for the definition of the " + "frequency needed for PWM Inverter.\r\n" + "\r\n" + "Note: The frequency range, entered as a decimal " + "number, for the integrated PWM is 200Hz - 40KHz." + EndPage + + + Page "Chromaticity Control" + Link "Close Table" , ".." + + Combo $Chromacity_Enable_5, "Chromaticity Control Feature", &Disabled_Enabled_List, + Help " This bit enables Chromaticity feature. \r\n" + " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" + " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" + " Please refer to section 3.7 of EDID Specification 1.4" + Combo $Override_EDID_Data_5, "Override the EDID values", &No_Yes_List, + Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" + EditNum $Red_Green_5, " Red_Green_bits (Bits 1&0 at 19h)" , EHEX, + Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" + EditNum $Blue_White_5, " Blue_White_bits (Bits 1&0 at 20h)" , EHEX, + Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" + EditNum $Red_x_5, " Red_x (Bits 9->2 at 1Bh)" , EHEX, + Help " Bits 9->2 of red color x coordinate" + EditNum $Red_y_5, " Red_y (Bits 9->2 at 1Ch)" , EHEX, + Help " Bits 9->2 of red color y coordinate" + EditNum $Green_x_5, " Green_x (Bits 9->2 at 1Dh)" , EHEX, + Help " Bits 9->2 of Green color x coordinate" + EditNum $Green_y_5, " Green_y (Bits 9->2 at 1Eh)" , EHEX, + Help " Bits 9->2 of Green color y coordinate" + EditNum $Blue_x_5, " Blue_x (Bits 9->2 at 1Fh)" , EHEX, + Help " Bits 9->2 of Blue color x coordinate" + EditNum $Blue_y_5, " Blue_y (Bits 9->2 at 20h)" , EHEX, + Help " Bits 9->2 of Blue color y coordinate" + EditNum $White_x_5, " White_x (Bits 9->2 at 21h)" , EHEX, + Help " Bits 9->2 of White color x coordinate" + EditNum $White_y_5, " White_y (Bits 9->2 at 22h)" , EHEX, + Help " Bits 9->2 of White color y coordinate" + + EndPage ; Chromaticity Control + +EndPage + + +;============================================================================== +; Page - Panel #6 (1400x1050) Flat Panel parameters +;------------------------------------------------------------------------------ + +Page "Panel #6 " + + TitleB "Common LFP Features" + + EditText $Panel_Name_06, "\tLFP Panel Name:", + Help "This feature defines the LVDS panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated. " + + Combo $Enable_Scaling_06, "\tScale to Target Resolution:", &No_Yes_List, + Help "Selecting this feature will make the graphics driver to enable Scaling feature by taking the Horizontal and Vertical resolution\r\n" + "from Target X-Res and Target Y-Res fields.\r\n" + + EditNum $Panel_Width_06, "\tTarget X-Res:", DEC, + Help "This value specifies the Target X-Resolution for this panel." + + EditNum $Panel_Height_06, "\tTarget Y-Res:", DEC, + Help "This value specifies the Target Y-Resolutoin for this panel." + + + + + Combo $DPS_Panel_Type_06, " \tDPS Panel Type:", &DPS_Panel_Type_List, + Help "This feature allows OEM to select the DPS Panel Type.\r\n " + "Intel SDRRS Technology is a feature of the Intel graphics driver\r\n" + "which reduces display power\r\n" + "SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n" + "rate will not adversely impact the user experience\r\n" + "Seamless:- Allows power savings when on battery mode and when a lower refresh\r\n" + "rate will not adversely impact the user experience.Implements seamless refresh\r\n" + "rate switching, which eliminates the screen blink that occurred\r\n" + "during the refresh rate transitions\r\n" + + EditNum $Seamless_DRRS_Min_RR_06, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, + Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n\n" + "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" + + Combo $Blt_Control_06, "\tBackLight Technology:", &Blt_Control_Type_List, + Help "This feature allows OEM to select the Backlight Technology.\r\n " + + Title " " + Link "LFP PnP ID Table" , "LFP PnP ID" + Link "DTD Timings Table" , "DTD Timings" + Link "Backlight Control Parameters" , "Backlight Control Parameters" + Link "Chromaticity Control" , "Chromaticity Control" + + + #if ($Int_LFP1_Type == 0x1806) + TitleB "Integrated eDP Features" + + Combo $Enable_SSC06, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List, + Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " + + + Combo $eDP_Panel_Color_Depth_06, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, + Help "This feature specifies the color depth of eDP panel used. " + + Combo $eDP_VSwingPreEmph_6, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, + Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " + "For CherryTrail, based on the selection respective table will be used.\r\n" + "Tables for CherryTrail:-\r\n" + "------------------------------------------------------------------------------------------------------\n" + "|Low Power VSwing Pre-Emphasis Setting Table |\n" + "-----------------------------------------------------------------------------------------------------|\n" + "| | Pre-Emphasis (db) |\n" + "| |------------------------------------------------------------------------------------------|\n" + "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" + "| Voltage |------------------------------------------------------------------------- ---------------|\n" + "| Swing | Level 0/200 | 200mV,0db | 200mV,3.5db | 200mV,6db | 200mV,9db |\n" + "| (mV) |------------------------------------------------------------------------------------------|\n" + "| | Level 1/250 | 250mV,0db | 250mV,3.5db | 250mV,6db | NA |\n" + "| |------------------------------------------------------------------------------------------|\n" + "| | Level 2/300 | 300mV,0db | 300mV,3.5d | NA | NA |\n" + "| |------------------------------------------------------------------------------------------|\n" + "| | Level 3/350 | 350 mv, 0db | NA | NA | NA |\n" + "-----------------------------------------------------------------------------------------------------\n\n" + + "-----------------------------------------------------------------------------------------------------\n" + "|Default VSwing Pre-Emphasis Setting Table |\n" + "---------------------------------------------------------------------------------------------------|\n" + "| | Pre-Emphasis (db) |\n" + "| |----------------------------------------------------------------------------------------|\n" + "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" + "| Voltage |----------------------------------------------------------------------------------------|\n" + "| Swing | Level 0/400 | 400mV,0db | 400mV,3.5db | 400mV,6db | 400mV,9db |\n" + "| (mV) |----------------------------------------------------------------------------------------|\n" + "| | Level 1/600 | 600mV,0db | 600mV,3.5db | 600mV,6db | NA |\n" + "| |----------------------------------------------------------------------------------------|\n" + "| | Level 2/800 | 800mV,0db | 800mV,3.5db | NA | NA |\n" + "| |----------------------------------------------------------------------------------------|\n" + "| | Level 3/1200| 1200mV, 0db | NA | NA | NA |\n" + "-----------------------------------------------------------------------------------------------------\n\n" + + + Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Power Sequencing" + Link "eDP Fast Link Training Configuration" , "eDP Fast Link Training Configuration" + + Page "eDP Panel Power Sequencing" + Link "Close Table", ".." + + Combo $eDP_T3_Optimization_06, "T3 optimization", &Disabled_Enabled_List, + Help "This feature enables or disables T3 optimization. \r\n" + "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" + "When disabled, VBIOS/Graphics driver will wait for T3 time before trying the first AUX transaction" + + EditNum $eDP_Vcc_To_Hpd_Delay_06, "LCDVCC to HPD high delay (T3):", DEC, + Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" + "Valid Range: 0 to 200msec\r\n" + + EditNum $eDP_DataOn_To_BkltEnable_Delay_06, "Valid video data to Backlight Enable delay (T8):", DEC, + Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" + "T8 is inclusive of T7.\r\n" + "Valid Range of T7: 0 to 50msec\r\n" + + EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_06, "PWM-On To Backlight Enable delay:", DEC, + Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" + "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" + "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" + + EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_06, "Backlight Disable to PWM-Off delay:", DEC, + Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" + "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" + "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" + + EditNum $eDP_BkltDisable_To_DataOff_Delay_06, "Backlight Disable to End of Valid video data delay (T9):", DEC, + Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" + + EditNum $eDP_DataOff_To_PowerOff_Delay_06, "End of Valid video data to Power-Off delay (T10):", DEC, + Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" + "Valid Range: 0 to 500 msec\r\n" + + EditNum $eDP_PowerCycle_Delay_06, "Power-off time (T12):", DEC, + Help "Using this field Power-off time can be specified in 100uS.\r\n" + + EndPage + + Page "eDP Fast Link Training Configuration" + + Link "Close Table" , ".." + Combo $Fast_Link_Training_Supported_06, " Is FastLinkTraining Feature Supported:", &No_Yes_List, + Help "This feature if set to Yes will enable " + "Fast Link Training for eDp, if Panel also supports it." + + Combo $eDP_Link_DataRate_06, " Data Rate:", &eDP_Link_DataRate_List, + Help "This feature allows for the selection of the " + "Data Rate for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + Combo $eDP_Link_LaneCount_06, " Lane Count:", &eDP_Link_LaneCount_List, + Help "This feature allows for the selection of the " + "Lane Count (Port Width) for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + Combo $eDP_Link_PreEmp_06, " Pre-Emphasis:", &eDP_Link_PreEmp_List, + Help "This feature allows for the selection of the " + "Pre-emphasis value for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" + "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" + "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" + "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" + "------------------------------------------------------------------------------------------------------------ \r\n" + + "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" + "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" + "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" + "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" + "------------------------------------------------------------------------------------------------------------ \r\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + Combo $eDP_Link_Vswing_06, " Voltage Swing:", &eDP_Link_VSwing_List, + Help "This feature allows for the selection of the " + "Voltage Swing value for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" + "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" + "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" + "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" + "------------------------------------------------------------------------------------------------------------ \r\n" + + "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" + "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" + "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" + "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" + "------------------------------------------------------------------------------------------------------------ \r\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + EndPage + #endif + + Page "DTD Timings" + + Link "Close Table" , ".." + + Table $DVO_Tbl_06 " DTD Timings Values", + Column "Timings" , 1 byte , EHEX, + Help "This feature allows for the definition of the DTD " + "timings parameters related to the LFP. The " + "table is the 18-byte DTD structure defined in the " + "VESA EDID version 1.x.\r\n" + "\r\n" + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" + "\tDB ?\t; Vertical Active in lines, LSB\r\n" + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Horizontal Image Size, LSB\r\n" + "\tDB ?\t; Vertical Image Size, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" + "\tDB 0\t; Horizontal Border in pixels\r\n" + "\tDB 0\t; Vertical Border in lines\r\n" + "\tDB ?\t; Flags:\r\n" + "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" + "\t \t; Bit 6-5: 00 = Reserved\r\n" + "\t \t; Bit 4-3: 11 = Digital Separate\r\n" + "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 0: 0 = Reserved" + + EndPage + + Page "LFP PnP ID" + + Link "Close Table" , ".." + + Table $LVDS_PnP_ID_06 " LFP PnP ID Values", + Column "PnP ID" , 1 byte , EHEX, + Help "This feature allows the 10 bytes of EDID Vendor / " + "Product ID starting at offset 08h to be used as a " + "PnP ID.\r\n" + "\r\n" + " Table Definition:\r\n" + " Word: ID Manufacturer Name\r\n" + " Word: ID Product Code\r\n" + " DWord: ID Serial Number\r\n" + " Byte: Week of Manufacture\r\n" + " Byte: Year of Manufacture" + + EndPage + + Page "Backlight Control Parameters" + + Link "Close Table" , ".." + + Combo $BLC_Inv_Type_6, " Inverter Type:", &Inv_Type_List, + Help "This feature allows for the selection of the " + "Backlight Inverter type that is to be used to " + "control the backlight brightness of the LFP. When " + "PWM is selected, the driver and VBIOS will control " + "the backlight brightness via the integrated PWM " + "solution for the applicable chipsets. When I2C is " + "selected, the driver and VBIOS will control the " + "backlight brightness via the I2C solution for the " + "applicable chipsets. When None/External is " + "selected, the system BIOS will control the backlight " + "brightness via the external solution." + + Combo $Lfp_Pwm_Source_Selection_06, " Pwm Source Selection:", &Edp_Pwm_Source_List, + Help "This field allows to select the Source of the PWM to be used " + "for the selected Local Flat Panel.\r\n" + "\r\n" + + Combo $BLC_Inv_Polarity_6, " Inverter Polarity:", &Inv_Polarity_List, + Help "This feature allows the backlight inverter polarity " + "to be specified.\r\n" + "\r\n" + "Normal means 0 value is minimum brightness.\r\n" + "Inverted means 0 value is maximum brightness." + + EditNum $BLC_Min_Brightness_6, " Minimum Brightness:", DEC, + Help "This feature allows defining the absolute minimum " + "backlight brightness setting. The graphics driver " + "will never decrease the backlight less than this " + "value. The value must be specified using normal " + "polarity semantics." + +EditNum $POST_BL_Brightness_06, " POST Backlight Intensity:", DEC, + Help "This feature is used to set default brightness value at POST." + "This is configurable field of 0-255. Value of 0 indicates 0 brightness, 255 indicates maximum brightness. " + + EditNum $PWM_Frequency_6, " PWM Inverter Frequency (Hz):", DEC, + Help "This feature allows for the definition of the " + "frequency needed for PWM Inverter.\r\n" + "\r\n" + "Note: The frequency range, entered as a decimal " + "number, for the integrated PWM is 200Hz - 40KHz." + EndPage + + Page "Chromaticity Control" + Link "Close Table" , ".." + + Combo $Chromacity_Enable_6, "Chromaticity Control Feature", &Disabled_Enabled_List, + Help " This bit enables Chromaticity feature. \r\n" + " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" + " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" + " Please refer to section 3.7 of EDID Specification 1.4" + Combo $Override_EDID_Data_6, "Override the EDID values", &No_Yes_List, + Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" + EditNum $Red_Green_6, " Red_Green_bits (Bits 1&0 at 19h)" , EHEX, + Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" + EditNum $Blue_White_6, " Blue_White_bits (Bits 1&0 at 20h)" , EHEX, + Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" + EditNum $Red_x_6, " Red_x (Bits 9->2 at 1Bh)" , EHEX, + Help " Bits 9->2 of red color x coordinate" + EditNum $Red_y_6, " Red_y (Bits 9->2 at 1Ch)" , EHEX, + Help " Bits 9->2 of red color y coordinate" + EditNum $Green_x_6, " Green_x (Bits 9->2 at 1Dh)" , EHEX, + Help " Bits 9->2 of Green color x coordinate" + EditNum $Green_y_6, " Green_y (Bits 9->2 at 1Eh)" , EHEX, + Help " Bits 9->2 of Green color y coordinate" + EditNum $Blue_x_6, " Blue_x (Bits 9->2 at 1Fh)" , EHEX, + Help " Bits 9->2 of Blue color x coordinate" + EditNum $Blue_y_6, " Blue_y (Bits 9->2 at 20h)" , EHEX, + Help " Bits 9->2 of Blue color y coordinate" + EditNum $White_x_6, " White_x (Bits 9->2 at 21h)" , EHEX, + Help " Bits 9->2 of White color x coordinate" + EditNum $White_y_6, " White_y (Bits 9->2 at 22h)" , EHEX, + Help " Bits 9->2 of White color y coordinate" + + EndPage ; Chromaticity Control + + + + +EndPage + +; +; Panel#7 to Panel#16 are not shown in BMP UI for MIPI panels +; +#if ($Int_LFP1_Type != 0x1400) +;============================================================================== +; Page - Panel #7 (1600x1200) Flat Panel parameters +;------------------------------------------------------------------------------ + +Page "Panel #7 " + + TitleB "Common LFP Features" + + EditText $Panel_Name_07, "\tLFP Panel Name:", + Help "This feature defines the LVDS panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated. " + + Combo $Enable_Scaling_07, "\tScale to Target Resolution:", &No_Yes_List, + Help "Selecting this feature will make the graphics driver to enable Scaling feature by taking the Horizontal and Vertical resolution\r\n" + "from Target X-Res and Target Y-Res fields.\r\n" + + EditNum $Panel_Width_07, "\tTarget X-Res:", DEC, + Help "This value specifies the Target X-Resolution for this panel." + + EditNum $Panel_Height_07, "\tTarget Y-Res:", DEC, + Help "This value specifies the Target Y-Resolutoin for this panel." + + + + + Combo $DPS_Panel_Type_07, " \tDPS Panel Type:", &DPS_Panel_Type_List, + Help "This feature allows OEM to select the DPS Panel Type.\r\n " + "Intel SDRRS Technology is a feature of the Intel graphics driver\r\n" + "which reduces display power\r\n" + "SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n" + "rate will not adversely impact the user experience\r\n" + "Seamless:- Allows power savings when on battery mode and when a lower refresh\r\n" + "rate will not adversely impact the user experience.Implements seamless refresh\r\n" + "rate switching, which eliminates the screen blink that occurred\r\n" + "during the refresh rate transitions\r\n" + + EditNum $Seamless_DRRS_Min_RR_07, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, + Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n\n" + "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" + + Combo $Blt_Control_07, "\tBackLight Technology:", &Blt_Control_Type_List, + Help "This feature allows OEM to select the Backlight Technology.\r\n " + + Title " " + Link "LFP PnP ID Table" , "LFP PnP ID" + Link "DTD Timings Table" , "DTD Timings" + Link "Backlight Control Parameters" , "Backlight Control Parameters" + Link "Chromaticity Control" , "Chromaticity Control" + + #if ($Int_LFP1_Type == 0x1806) + TitleB "Integrated eDP Features" + + + Combo $Enable_SSC07, " \teDP Spread Spectrum Clock:", &Disabled_Enabled_List, + Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " + + Combo $eDP_Panel_Color_Depth_07, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, + Help "This feature specifies the color depth of eDP panel used. " + + Combo $eDP_VSwingPreEmph_7, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, + Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " + "For CherryTrail, based on the selection respective table will be used.\r\n" + "Tables for CherryTrail:-\r\n" + "------------------------------------------------------------------------------------------------------\n" + "|Low Power VSwing Pre-Emphasis Setting Table |\n" + "-----------------------------------------------------------------------------------------------------|\n" + "| | Pre-Emphasis (db) |\n" + "| |------------------------------------------------------------------------------------------|\n" + "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" + "| Voltage |------------------------------------------------------------------------- ---------------|\n" + "| Swing | Level 0/200 | 200mV,0db | 200mV,3.5db | 200mV,6db | 200mV,9db |\n" + "| (mV) |------------------------------------------------------------------------------------------|\n" + "| | Level 1/250 | 250mV,0db | 250mV,3.5db | 250mV,6db | NA |\n" + "| |------------------------------------------------------------------------------------------|\n" + "| | Level 2/300 | 300mV,0db | 300mV,3.5d | NA | NA |\n" + "| |------------------------------------------------------------------------------------------|\n" + "| | Level 3/350 | 350 mv, 0db | NA | NA | NA |\n" + "-----------------------------------------------------------------------------------------------------\n\n" + + "-----------------------------------------------------------------------------------------------------\n" + "|Default VSwing Pre-Emphasis Setting Table |\n" + "---------------------------------------------------------------------------------------------------|\n" + "| | Pre-Emphasis (db) |\n" + "| |----------------------------------------------------------------------------------------|\n" + "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" + "| Voltage |----------------------------------------------------------------------------------------|\n" + "| Swing | Level 0/400 | 400mV,0db | 400mV,3.5db | 400mV,6db | 400mV,9db |\n" + "| (mV) |----------------------------------------------------------------------------------------|\n" + "| | Level 1/600 | 600mV,0db | 600mV,3.5db | 600mV,6db | NA |\n" + "| |----------------------------------------------------------------------------------------|\n" + "| | Level 2/800 | 800mV,0db | 800mV,3.5db | NA | NA |\n" + "| |----------------------------------------------------------------------------------------|\n" + "| | Level 3/1200| 1200mV, 0db | NA | NA | NA |\n" + "-----------------------------------------------------------------------------------------------------\n\n" + + + Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Power Sequencing" + Link "eDP Fast Link Training Configuration" , "eDP Fast Link Training Configuration" + + Page "eDP Panel Power Sequencing" + Link "Close Table", ".." + + Combo $eDP_T3_Optimization_07, "T3 optimization", &Disabled_Enabled_List, + Help "This feature enables or disables T3 optimization. \r\n" + "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" + "When disabled, VBIOS/Graphics driver will wait for T3 time before trying the first AUX transaction" + + EditNum $eDP_Vcc_To_Hpd_Delay_07, "LCDVCC to HPD high delay (T3):", DEC, + Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" + "Valid Range: 0 to 200msec\r\n" + + EditNum $eDP_DataOn_To_BkltEnable_Delay_07, "Valid video data to Backlight Enable delay (T8):", DEC, + Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" + "T8 is inclusive of T7.\r\n" + "Valid Range of T7: 0 to 50msec\r\n" + + EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_07, "PWM-On To Backlight Enable delay:", DEC, + Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" + "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" + "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" + + EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_07, "Backlight Disable to PWM-Off delay:", DEC, + Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" + "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" + "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" + + EditNum $eDP_BkltDisable_To_DataOff_Delay_07, "Backlight Disable to End of Valid video data delay (T9):", DEC, + Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" + + EditNum $eDP_DataOff_To_PowerOff_Delay_07, "End of Valid video data to Power-Off delay (T10):", DEC, + Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" + "Valid Range: 0 to 500 msec\r\n" + + EditNum $eDP_PowerCycle_Delay_07, "Power-off time (T12):", DEC, + Help "Using this field Power-off time can be specified in 100uS.\r\n" + + EndPage + + Page "eDP Fast Link Training Configuration" + + Link "Close Table" , ".." + Combo $Fast_Link_Training_Supported_07, " Is FastLinkTraining Feature Supported:", &No_Yes_List, + Help "This feature if set to Yes will enable " + "Fast Link Training for eDp, if Panel also supports it." + + Combo $eDP_Link_DataRate_07, " Data Rate:", &eDP_Link_DataRate_List, + Help "This feature allows for the selection of the " + "Data Rate for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + Combo $eDP_Link_LaneCount_07, " Lane Count:", &eDP_Link_LaneCount_List, + Help "This feature allows for the selection of the " + "Lane Count (Port Width) for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + Combo $eDP_Link_PreEmp_07, " Pre-Emphasis:", &eDP_Link_PreEmp_List, + Help "This feature allows for the selection of the " + "Pre-emphasis value for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" + "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" + "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" + "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" + "------------------------------------------------------------------------------------------------------------ \r\n" + + "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" + "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" + "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" + "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" + "------------------------------------------------------------------------------------------------------------ \r\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + Combo $eDP_Link_Vswing_07, " Voltage Swing:", &eDP_Link_VSwing_List, + Help "This feature allows for the selection of the " + "Voltage Swing value for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" + "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" + "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" + "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" + "------------------------------------------------------------------------------------------------------------ \r\n" + + "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" + "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" + "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" + "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" + "------------------------------------------------------------------------------------------------------------ \r\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + EndPage + #endif + + Page "DTD Timings" + + Link "Close Table" , ".." + + Table $DVO_Tbl_07 " DTD Timings Values", + Column "Timings" , 1 byte , EHEX, + Help "This feature allows for the definition of the DTD " + "timings parameters related to the LFP. The " + "table is the 18-byte DTD structure defined in the " + "VESA EDID version 1.x.\r\n" + "\r\n" + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" + "\tDB ?\t; Vertical Active in lines, LSB\r\n" + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Horizontal Image Size, LSB\r\n" + "\tDB ?\t; Vertical Image Size, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" + "\tDB 0\t; Horizontal Border in pixels\r\n" + "\tDB 0\t; Vertical Border in lines\r\n" + "\tDB ?\t; Flags:\r\n" + "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" + "\t \t; Bit 6-5: 00 = Reserved\r\n" + "\t \t; Bit 4-3: 11 = Digital Separate\r\n" + "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 0: 0 = Reserved" + + EndPage + + Page "LFP PnP ID" + + Link "Close Table" , ".." + + Table $LVDS_PnP_ID_07 " LFP PnP ID Values", + Column "PnP ID" , 1 byte , EHEX, + Help "This feature allows the 10 bytes of EDID Vendor / " + "Product ID starting at offset 08h to be used as a " + "PnP ID.\r\n" + "\r\n" + " Table Definition:\r\n" + " Word: ID Manufacturer Name\r\n" + " Word: ID Product Code\r\n" + " DWord: ID Serial Number\r\n" + " Byte: Week of Manufacture\r\n" + " Byte: Year of Manufacture" + + EndPage + + Page "Backlight Control Parameters" + + Link "Close Table" , ".." + + Combo $BLC_Inv_Type_7, " Inverter Type:", &Inv_Type_List, + Help "This feature allows for the selection of the " + "Backlight Inverter type that is to be used to " + "control the backlight brightness of the LFP. When " + "PWM is selected, the driver and VBIOS will control " + "the backlight brightness via the integrated PWM " + "solution for the applicable chipsets. When I2C is " + "selected, the driver and VBIOS will control the " + "backlight brightness via the I2C solution for the " + "applicable chipsets. When None/External is " + "selected, the system BIOS will control the backlight " + "brightness via the external solution." + + Combo $Lfp_Pwm_Source_Selection_07, " Pwm Source Selection:", &Edp_Pwm_Source_List, + Help "This field allows to select the Source of the PWM to be used " + "for the selected Local Flat Panel.\r\n" + "\r\n" + + Combo $BLC_Inv_Polarity_7, " Inverter Polarity:", &Inv_Polarity_List, + Help "This feature allows the backlight inverter polarity " + "to be specified.\r\n" + "\r\n" + "Normal means 0 value is minimum brightness.\r\n" + "Inverted means 0 value is maximum brightness." + + EditNum $BLC_Min_Brightness_7, " Minimum Brightness:", DEC, + Help "This feature allows defining the absolute minimum " + "backlight brightness setting. The graphics driver " + "will never decrease the backlight less than this " + "value. The value must be specified using normal " + "polarity semantics." + +EditNum $POST_BL_Brightness_07, " POST Backlight Intensity:", DEC, + Help "This feature is used to set default brightness value at POST." + "This is configurable field of 0-255. Value of 0 indicates 0 brightness, 255 indicates maximum brightness. " + + EditNum $PWM_Frequency_7, " PWM Inverter Frequency (Hz):", DEC, + Help "This feature allows for the definition of the " + "frequency needed for PWM Inverter.\r\n" + "\r\n" + "Note: The frequency range, entered as a decimal " + "number, for the integrated PWM is 200Hz - 40KHz." + EndPage + + Page "Chromaticity Control" + Link "Close Table" , ".." + + Combo $Chromacity_Enable_7, "Chromaticity Control Feature", &Disabled_Enabled_List, + Help " This bit enables Chromaticity feature. \r\n" + " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" + " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" + " Please refer to section 3.7 of EDID Specification 1.4" + Combo $Override_EDID_Data_7, "Override the EDID values", &No_Yes_List, + Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" + EditNum $Red_Green_7, " Red_Green_bits (Bits 1&0 at 19h)" , EHEX, + Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" + EditNum $Blue_White_7, " Blue_White_bits (Bits 1&0 at 20h)" , EHEX, + Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" + EditNum $Red_x_7, " Red_x (Bits 9->2 at 1Bh)" , EHEX, + Help " Bits 9->2 of red color x coordinate" + EditNum $Red_y_7, " Red_y (Bits 9->2 at 1Ch)" , EHEX, + Help " Bits 9->2 of red color y coordinate" + EditNum $Green_x_7, " Green_x (Bits 9->2 at 1Dh)" , EHEX, + Help " Bits 9->2 of Green color x coordinate" + EditNum $Green_y_7, " Green_y (Bits 9->2 at 1Eh)" , EHEX, + Help " Bits 9->2 of Green color y coordinate" + EditNum $Blue_x_7, " Blue_x (Bits 9->2 at 1Fh)" , EHEX, + Help " Bits 9->2 of Blue color x coordinate" + EditNum $Blue_y_7, " Blue_y (Bits 9->2 at 20h)" , EHEX, + Help " Bits 9->2 of Blue color y coordinate" + EditNum $White_x_7, " White_x (Bits 9->2 at 21h)" , EHEX, + Help " Bits 9->2 of White color x coordinate" + EditNum $White_y_7, " White_y (Bits 9->2 at 22h)" , EHEX, + Help " Bits 9->2 of White color y coordinate" + + EndPage ; Chromaticity Control +EndPage + + + +;============================================================================== +; Page - Panel #8 (1280x768) Flat Panel parameters +;------------------------------------------------------------------------------ + +Page "Panel #8 " + + TitleB "Common LFP Features" + + EditText $Panel_Name_08, "\tLFP Panel Name:", + Help "This feature defines the LVDS panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated. " + + Combo $Enable_Scaling_08, "\tScale to Target Resolution:", &No_Yes_List, + Help "Selecting this feature will make the graphics driver to enable Scaling feature by taking the Horizontal and Vertical resolution\r\n" + "from Target X-Res and Target Y-Res fields.\r\n" + + EditNum $Panel_Width_08, "\tTarget X-Res:", DEC, + Help "This value specifies the Target X-Resolution for this panel." + + EditNum $Panel_Height_08, "\tTarget Y-Res:", DEC, + Help "This value specifies the Target Y-Resolutoin for this panel." + + + + + Combo $DPS_Panel_Type_08, " \tDPS Panel Type:", &DPS_Panel_Type_List, + Help "This feature allows OEM to select the DPS Panel Type.\r\n " + "Intel SDRRS Technology is a feature of the Intel graphics driver\r\n" + "which reduces display power\r\n" + "SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n" + "rate will not adversely impact the user experience\r\n" + "Seamless:- Allows power savings when on battery mode and when a lower refresh\r\n" + "rate will not adversely impact the user experience.Implements seamless refresh\r\n" + "rate switching, which eliminates the screen blink that occurred\r\n" + "during the refresh rate transitions\r\n" + + EditNum $Seamless_DRRS_Min_RR_08, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, + Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n\n" + "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" + + Combo $Blt_Control_08, "\tBackLight Technology:", &Blt_Control_Type_List, + Help "This feature allows OEM to select the Backlight Technology.\r\n " + + Title " " + Link "LFP PnP ID Table" , "LFP PnP ID" + Link "DTD Timings Table" , "DTD Timings" + Link "Backlight Control Parameters" , "Backlight Control Parameters" + Link "Chromaticity Control" , "Chromaticity Control" + + #if ($Int_LFP1_Type == 0x1806) + TitleB "Integrated eDP Features" + + Combo $Enable_SSC08, " \teDP Spread Spectrum Clock:", &Disabled_Enabled_List, + Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " + + + Combo $eDP_Panel_Color_Depth_08, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, + Help "This feature specifies the color depth of eDP panel used. " + + Combo $eDP_VSwingPreEmph_8, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, + Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " + "For CherryTrail, based on the selection respective table will be used.\r\n" + "Tables for CherryTrail:-\r\n" + "------------------------------------------------------------------------------------------------------\n" + "|Low Power VSwing Pre-Emphasis Setting Table |\n" + "-----------------------------------------------------------------------------------------------------|\n" + "| | Pre-Emphasis (db) |\n" + "| |------------------------------------------------------------------------------------------|\n" + "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" + "| Voltage |------------------------------------------------------------------------- ---------------|\n" + "| Swing | Level 0/200 | 200mV,0db | 200mV,3.5db | 200mV,6db | 200mV,9db |\n" + "| (mV) |------------------------------------------------------------------------------------------|\n" + "| | Level 1/250 | 250mV,0db | 250mV,3.5db | 250mV,6db | NA |\n" + "| |------------------------------------------------------------------------------------------|\n" + "| | Level 2/300 | 300mV,0db | 300mV,3.5d | NA | NA |\n" + "| |------------------------------------------------------------------------------------------|\n" + "| | Level 3/350 | 350 mv, 0db | NA | NA | NA |\n" + "-----------------------------------------------------------------------------------------------------\n\n" + + "-----------------------------------------------------------------------------------------------------\n" + "|Default VSwing Pre-Emphasis Setting Table |\n" + "---------------------------------------------------------------------------------------------------|\n" + "| | Pre-Emphasis (db) |\n" + "| |----------------------------------------------------------------------------------------|\n" + "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" + "| Voltage |----------------------------------------------------------------------------------------|\n" + "| Swing | Level 0/400 | 400mV,0db | 400mV,3.5db | 400mV,6db | 400mV,9db |\n" + "| (mV) |----------------------------------------------------------------------------------------|\n" + "| | Level 1/600 | 600mV,0db | 600mV,3.5db | 600mV,6db | NA |\n" + "| |----------------------------------------------------------------------------------------|\n" + "| | Level 2/800 | 800mV,0db | 800mV,3.5db | NA | NA |\n" + "| |----------------------------------------------------------------------------------------|\n" + "| | Level 3/1200| 1200mV, 0db | NA | NA | NA |\n" + "-----------------------------------------------------------------------------------------------------\n\n" + + + Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Power Sequencing" + Link "eDP Fast Link Training Configuration" , "eDP Fast Link Training Configuration" + + Page "eDP Panel Power Sequencing" + Link "Close Table", ".." + + Combo $eDP_T3_Optimization_08, "T3 optimization", &Disabled_Enabled_List, + Help "This feature enables or disables T3 optimization. \r\n" + "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" + "When disabled, VBIOS/Graphics driver will wait for T3 time before trying the first AUX transaction" + + EditNum $eDP_Vcc_To_Hpd_Delay_08, "LCDVCC to HPD high delay (T3):", DEC, + Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" + "Valid Range: 0 to 200msec\r\n" + + EditNum $eDP_DataOn_To_BkltEnable_Delay_08, "Valid video data to Backlight Enable delay (T8):", DEC, + Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" + "T8 is inclusive of T7.\r\n" + "Valid Range of T7: 0 to 50msec\r\n" + + EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_08, "PWM-On To Backlight Enable delay:", DEC, + Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" + "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" + "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" + + EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_08, "Backlight Disable to PWM-Off delay:", DEC, + Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" + "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" + "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" + + EditNum $eDP_BkltDisable_To_DataOff_Delay_08, "Backlight Disable to End of Valid video data delay (T9):", DEC, + Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" + + EditNum $eDP_DataOff_To_PowerOff_Delay_08, "End of Valid video data to Power-Off delay (T10):", DEC, + Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" + "Valid Range: 0 to 500 msec\r\n" + + EditNum $eDP_PowerCycle_Delay_08, "Power-off time (T12):", DEC, + Help "Using this field Power-off time can be specified in 100uS.\r\n" + + EndPage + + Page "eDP Fast Link Training Configuration" + + Link "Close Table" , ".." + Combo $Fast_Link_Training_Supported_08, " Is FastLinkTraining Feature Supported:", &No_Yes_List, + Help "This feature if set to Yes will enable " + "Fast Link Training for eDp, if Panel also supports it." + + Combo $eDP_Link_DataRate_08, " Data Rate:", &eDP_Link_DataRate_List, + Help "This feature allows for the selection of the " + "Data Rate for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + Combo $eDP_Link_LaneCount_08, " Lane Count:", &eDP_Link_LaneCount_List, + Help "This feature allows for the selection of the " + "Lane Count (Port Width) for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + Combo $eDP_Link_PreEmp_08, " Pre-Emphasis:", &eDP_Link_PreEmp_List, + Help "This feature allows for the selection of the " + "Pre-emphasis value for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" + "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" + "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" + "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" + "------------------------------------------------------------------------------------------------------------ \r\n" + + "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" + "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" + "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" + "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" + "------------------------------------------------------------------------------------------------------------ \r\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + Combo $eDP_Link_Vswing_08, " Voltage Swing:", &eDP_Link_VSwing_List, + Help "This feature allows for the selection of the " + "Voltage Swing value for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" + "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" + "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" + "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" + "------------------------------------------------------------------------------------------------------------ \r\n" + + "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" + "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" + "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" + "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" + "------------------------------------------------------------------------------------------------------------ \r\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + EndPage + #endif + + Page "DTD Timings" + + Link "Close Table" , ".." + + Table $DVO_Tbl_08 " DTD Timings Values", + Column "Timings" , 1 byte , EHEX, + Help "This feature allows for the definition of the DTD " + "timings parameters related to the LFP. The " + "table is the 18-byte DTD structure defined in the " + "VESA EDID version 1.x.\r\n" + "\r\n" + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" + "\tDB ?\t; Vertical Active in lines, LSB\r\n" + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Horizontal Image Size, LSB\r\n" + "\tDB ?\t; Vertical Image Size, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" + "\tDB 0\t; Horizontal Border in pixels\r\n" + "\tDB 0\t; Vertical Border in lines\r\n" + "\tDB ?\t; Flags:\r\n" + "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" + "\t \t; Bit 6-5: 00 = Reserved\r\n" + "\t \t; Bit 4-3: 11 = Digital Separate\r\n" + "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 0: 0 = Reserved" + + EndPage + + Page "LFP PnP ID" + + Link "Close Table" , ".." + + Table $LVDS_PnP_ID_08 " LFP PnP ID Values", + Column "PnP ID" , 1 byte , EHEX, + Help "This feature allows the 10 bytes of EDID Vendor / " + "Product ID starting at offset 08h to be used as a " + "PnP ID.\r\n" + "\r\n" + " Table Definition:\r\n" + " Word: ID Manufacturer Name\r\n" + " Word: ID Product Code\r\n" + " DWord: ID Serial Number\r\n" + " Byte: Week of Manufacture\r\n" + " Byte: Year of Manufacture" + + EndPage + + Page "Backlight Control Parameters" + + Link "Close Table" , ".." + + Combo $BLC_Inv_Type_8, " Inverter Type:", &Inv_Type_List, + Help "This feature allows for the selection of the " + "Backlight Inverter type that is to be used to " + "control the backlight brightness of the LFP. When " + "PWM is selected, the driver and VBIOS will control " + "the backlight brightness via the integrated PWM " + "solution for the applicable chipsets. When I2C is " + "selected, the driver and VBIOS will control the " + "backlight brightness via the I2C solution for the " + "applicable chipsets. When None/External is " + "selected, the system BIOS will control the backlight " + "brightness via the external solution." + + Combo $Lfp_Pwm_Source_Selection_08, " Pwm Source Selection:", &Edp_Pwm_Source_List, + Help "This field allows to select the Source of the PWM to be used " + "for the selected Local Flat Panel.\r\n" + "\r\n" + + Combo $BLC_Inv_Polarity_8, " Inverter Polarity:", &Inv_Polarity_List, + Help "This feature allows the backlight inverter polarity " + "to be specified.\r\n" + "\r\n" + "Normal means 0 value is minimum brightness.\r\n" + "Inverted means 0 value is maximum brightness." + + EditNum $BLC_Min_Brightness_8, " Minimum Brightness:", DEC, + Help "This feature allows defining the absolute minimum " + "backlight brightness setting. The graphics driver " + "will never decrease the backlight less than this " + "value. The value must be specified using normal " + "polarity semantics." + + EditNum $POST_BL_Brightness_08, " POST Backlight Intensity:", DEC, + Help "This feature is used to set default brightness value at POST." + "This is configurable field of 0-255. Value of 0 indicates 0 brightness, 255 indicates maximum brightness. " + + EditNum $PWM_Frequency_8, " PWM Inverter Frequency (Hz):", DEC, + Help "This feature allows for the definition of the " + "frequency needed for PWM Inverter.\r\n" + "\r\n" + "Note: The frequency range, entered as a decimal " + "number, for the integrated PWM is 200Hz - 40KHz." + EndPage + + + + Page "Chromaticity Control" + Link "Close Table" , ".." + + Combo $Chromacity_Enable_8, "Chromaticity Control Feature", &Disabled_Enabled_List, + Help " This bit enables Chromaticity feature. \r\n" + " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" + " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" + " Please refer to section 3.7 of EDID Specification 1.4" + Combo $Override_EDID_Data_8, "Override the EDID values", &No_Yes_List, + Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" + EditNum $Red_Green_8, " Red_Green_bits (Bits 1&0 at 19h)" , EHEX, + Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" + EditNum $Blue_White_8, " Blue_White_bits (Bits 1&0 at 20h)" , EHEX, + Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" + EditNum $Red_x_8, " Red_x (Bits 9->2 at 1Bh)" , EHEX, + Help " Bits 9->2 of red color x coordinate" + EditNum $Red_y_8, " Red_y (Bits 9->2 at 1Ch)" , EHEX, + Help " Bits 9->2 of red color y coordinate" + EditNum $Green_x_8, " Green_x (Bits 9->2 at 1Dh)" , EHEX, + Help " Bits 9->2 of Green color x coordinate" + EditNum $Green_y_8, " Green_y (Bits 9->2 at 1Eh)" , EHEX, + Help " Bits 9->2 of Green color y coordinate" + EditNum $Blue_x_8, " Blue_x (Bits 9->2 at 1Fh)" , EHEX, + Help " Bits 9->2 of Blue color x coordinate" + EditNum $Blue_y_8, " Blue_y (Bits 9->2 at 20h)" , EHEX, + Help " Bits 9->2 of Blue color y coordinate" + EditNum $White_x_8, " White_x (Bits 9->2 at 21h)" , EHEX, + Help " Bits 9->2 of White color x coordinate" + EditNum $White_y_8, " White_y (Bits 9->2 at 22h)" , EHEX, + Help " Bits 9->2 of White color y coordinate" + + EndPage ; Chromaticity Control +EndPage + +;============================================================================== +; Page - Panel #9 (1680x1050) Flat Panel parameters +;------------------------------------------------------------------------------ + +Page "Panel #9 " + + TitleB "Common LFP Features" + + EditText $Panel_Name_09, "\tLFP Panel Name:", + Help "This feature defines the LVDS panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated. " + + Combo $Enable_Scaling_09, "\tScale to Target Resolution:", &No_Yes_List, + Help "Selecting this feature will make the graphics driver to enable Scaling feature by taking the Horizontal and Vertical resolution\r\n" + "from Target X-Res and Target Y-Res fields.\r\n" + + EditNum $Panel_Width_09, "\tTarget X-Res:", DEC, + Help "This value specifies the Target X-Resolution for this panel." + + EditNum $Panel_Height_09, "\tTarget Y-Res:", DEC, + Help "This value specifies the Target Y-Resolutoin for this panel." + + + + + Combo $DPS_Panel_Type_09, " \tDPS Panel Type:", &DPS_Panel_Type_List, + Help "This feature allows OEM to select the DPS Panel Type.\r\n " + "Intel SDRRS Technology is a feature of the Intel graphics driver\r\n" + "which reduces display power\r\n" + "SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n" + "rate will not adversely impact the user experience\r\n" + "Seamless:- Allows power savings when on battery mode and when a lower refresh\r\n" + "rate will not adversely impact the user experience.Implements seamless refresh\r\n" + "rate switching, which eliminates the screen blink that occurred\r\n" + "during the refresh rate transitions\r\n" + + EditNum $Seamless_DRRS_Min_RR_09, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, + Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n\n" + "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" + + Combo $Blt_Control_09, "\tBackLight Technology:", &Blt_Control_Type_List, + Help "This feature allows OEM to select the Backlight Technology.\r\n " + + Title " " + Link "LFP PnP ID Table" , "LFP PnP ID" + Link "DTD Timings Table" , "DTD Timings" + Link "Backlight Control Parameters" , "Backlight Control Parameters" + Link "Chromaticity Control" , "Chromaticity Control" + + #if ($Int_LFP1_Type == 0x1806) + TitleB "Integrated eDP Features" + + Combo $Enable_SSC09, " \teDP Spread Spectrum Clock:", &Disabled_Enabled_List, + Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " + + Combo $eDP_Panel_Color_Depth_09, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, + Help "This feature specifies the color depth of eDP panel used. " + + Combo $eDP_VSwingPreEmph_9, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, + Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " + "For CherryTrail, based on the selection respective table will be used.\r\n" + "Tables for CherryTrail:-\r\n" + "------------------------------------------------------------------------------------------------------\n" + "|Low Power VSwing Pre-Emphasis Setting Table |\n" + "-----------------------------------------------------------------------------------------------------|\n" + "| | Pre-Emphasis (db) |\n" + "| |------------------------------------------------------------------------------------------|\n" + "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" + "| Voltage |------------------------------------------------------------------------- ---------------|\n" + "| Swing | Level 0/200 | 200mV,0db | 200mV,3.5db | 200mV,6db | 200mV,9db |\n" + "| (mV) |------------------------------------------------------------------------------------------|\n" + "| | Level 1/250 | 250mV,0db | 250mV,3.5db | 250mV,6db | NA |\n" + "| |------------------------------------------------------------------------------------------|\n" + "| | Level 2/300 | 300mV,0db | 300mV,3.5d | NA | NA |\n" + "| |------------------------------------------------------------------------------------------|\n" + "| | Level 3/350 | 350 mv, 0db | NA | NA | NA |\n" + "-----------------------------------------------------------------------------------------------------\n\n" + + "-----------------------------------------------------------------------------------------------------\n" + "|Default VSwing Pre-Emphasis Setting Table |\n" + "---------------------------------------------------------------------------------------------------|\n" + "| | Pre-Emphasis (db) |\n" + "| |----------------------------------------------------------------------------------------|\n" + "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" + "| Voltage |----------------------------------------------------------------------------------------|\n" + "| Swing | Level 0/400 | 400mV,0db | 400mV,3.5db | 400mV,6db | 400mV,9db |\n" + "| (mV) |----------------------------------------------------------------------------------------|\n" + "| | Level 1/600 | 600mV,0db | 600mV,3.5db | 600mV,6db | NA |\n" + "| |----------------------------------------------------------------------------------------|\n" + "| | Level 2/800 | 800mV,0db | 800mV,3.5db | NA | NA |\n" + "| |----------------------------------------------------------------------------------------|\n" + "| | Level 3/1200| 1200mV, 0db | NA | NA | NA |\n" + "-----------------------------------------------------------------------------------------------------\n\n" + + + Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Power Sequencing" + Link "eDP Fast Link Training Configuration" , "eDP Fast Link Training Configuration" + + Page "eDP Panel Power Sequencing" + Link "Close Table", ".." + + Combo $eDP_T3_Optimization_09, "T3 optimization", &Disabled_Enabled_List, + Help "This feature enables or disables T3 optimization. \r\n" + "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" + "When disabled, VBIOS/Graphics driver will wait for T3 time before trying the first AUX transaction" + + EditNum $eDP_Vcc_To_Hpd_Delay_09, "LCDVCC to HPD high delay (T3):", DEC, + Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" + "Valid Range: 0 to 200msec\r\n" + + EditNum $eDP_DataOn_To_BkltEnable_Delay_09, "Valid video data to Backlight Enable delay (T8):", DEC, + Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" + "T8 is inclusive of T7.\r\n" + "Valid Range of T7: 0 to 50msec\r\n" + + EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_09, "PWM-On To Backlight Enable delay:", DEC, + Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" + "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" + "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" + + EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_09, "Backlight Disable to PWM-Off delay:", DEC, + Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" + "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" + "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" + + EditNum $eDP_BkltDisable_To_DataOff_Delay_09, "Backlight Disable to End of Valid video data delay (T9):", DEC, + Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" + + EditNum $eDP_DataOff_To_PowerOff_Delay_09, "End of Valid video data to Power-Off delay (T10):", DEC, + Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" + "Valid Range: 0 to 500 msec\r\n" + + EditNum $eDP_PowerCycle_Delay_09, "Power-off time (T12):", DEC, + Help "Using this field Power-off time can be specified in 100uS.\r\n" + + EndPage + + Page "eDP Fast Link Training Configuration" + + Link "Close Table" , ".." + Combo $Fast_Link_Training_Supported_09, " Is FastLinkTraining Feature Supported:", &No_Yes_List, + Help "This feature if set to Yes will enable " + "Fast Link Training for eDp, if Panel also supports it." + + Combo $eDP_Link_DataRate_09, " Data Rate:", &eDP_Link_DataRate_List, + Help "This feature allows for the selection of the " + "Data Rate for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + Combo $eDP_Link_LaneCount_09, " Lane Count:", &eDP_Link_LaneCount_List, + Help "This feature allows for the selection of the " + "Lane Count (Port Width) for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + Combo $eDP_Link_PreEmp_09, " Pre-Emphasis:", &eDP_Link_PreEmp_List, + Help "This feature allows for the selection of the " + "Pre-emphasis value for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(400mV) | Supported | Supported | Supported | Support | \r\n" + "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" + "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" + "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" + "------------------------------------------------------------------------------------------------------------ \r\n" + + "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" + "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" + "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" + "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" + "------------------------------------------------------------------------------------------------------------ \r\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + Combo $eDP_Link_Vswing_09, " Voltage Swing:", &eDP_Link_VSwing_List, + Help "This feature allows for the selection of the " + "Voltage Swing value for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" + "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" + "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" + "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" + "------------------------------------------------------------------------------------------------------------ \r\n" + + "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" + "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" + "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" + "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" + "------------------------------------------------------------------------------------------------------------ \r\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + EndPage + #endif + + Page "DTD Timings" + + Link "Close Table" , ".." + + Table $DVO_Tbl_09 " DTD Timings Values", + Column "Timings" , 1 byte , EHEX, + Help "This feature allows for the definition of the DTD " + "timings parameters related to the LFP. The " + "table is the 18-byte DTD structure defined in the " + "VESA EDID version 1.x.\r\n" + "\r\n" + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" + "\tDB ?\t; Vertical Active in lines, LSB\r\n" + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Horizontal Image Size, LSB\r\n" + "\tDB ?\t; Vertical Image Size, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" + "\tDB 0\t; Horizontal Border in pixels\r\n" + "\tDB 0\t; Vertical Border in lines\r\n" + "\tDB ?\t; Flags:\r\n" + "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" + "\t \t; Bit 6-5: 00 = Reserved\r\n" + "\t \t; Bit 4-3: 11 = Digital Separate\r\n" + "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 0: 0 = Reserved" + + EndPage + + Page "LFP PnP ID" + + Link "Close Table" , ".." + + Table $LVDS_PnP_ID_09 " LFP PnP ID Values", + Column "PnP ID" , 1 byte , EHEX, + Help "This feature allows the 10 bytes of EDID Vendor / " + "Product ID starting at offset 08h to be used as a " + "PnP ID.\r\n" + "\r\n" + " Table Definition:\r\n" + " Word: ID Manufacturer Name\r\n" + " Word: ID Product Code\r\n" + " DWord: ID Serial Number\r\n" + " Byte: Week of Manufacture\r\n" + " Byte: Year of Manufacture" + + EndPage + + Page "Backlight Control Parameters" + + Link "Close Table" , ".." + + Combo $BLC_Inv_Type_9, " Inverter Type:", &Inv_Type_List, + Help "This feature allows for the selection of the " + "Backlight Inverter type that is to be used to " + "control the backlight brightness of the LFP. When " + "PWM is selected, the driver and VBIOS will control " + "the backlight brightness via the integrated PWM " + "solution for the applicable chipsets. When I2C is " + "selected, the driver and VBIOS will control the " + "backlight brightness via the I2C solution for the " + "applicable chipsets. When None/External is " + "selected, the system BIOS will control the backlight " + "brightness via the external solution." + + Combo $Lfp_Pwm_Source_Selection_09, " Pwm Source Selection:", &Edp_Pwm_Source_List, + Help "This field allows to select the Source of the PWM to be used " + "for the selected Local Flat Panel.\r\n" + "\r\n" + + Combo $BLC_Inv_Polarity_9, " Inverter Polarity:", &Inv_Polarity_List, + Help "This feature allows the backlight inverter polarity " + "to be specified.\r\n" + "\r\n" + "Normal means 0 value is minimum brightness.\r\n" + "Inverted means 0 value is maximum brightness." + + EditNum $BLC_Min_Brightness_9, " Minimum Brightness:", DEC, + Help "This feature allows defining the absolute minimum " + "backlight brightness setting. The graphics driver " + "will never decrease the backlight less than this " + "value. The value must be specified using normal " + "polarity semantics." + +EditNum $POST_BL_Brightness_09, " POST Backlight Intensity:", DEC, + Help "This feature is used to set default brightness value at POST." + "This is configurable field of 0-255. Value of 0 indicates 0 brightness, 255 indicates maximum brightness. " + + EditNum $PWM_Frequency_9, " PWM Inverter Frequency (Hz):", DEC, + Help "This feature allows for the definition of the " + "frequency needed for PWM Inverter.\r\n" + "\r\n" + "Note: The frequency range, entered as a decimal " + "number, for the integrated PWM is 200Hz - 40KHz." + EndPage + + + + Page "Chromaticity Control" + Link "Close Table" , ".." + + Combo $Chromacity_Enable_9, "Chromaticity Control Feature", &Disabled_Enabled_List, + Help " This bit enables Chromaticity feature. \r\n" + " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" + " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" + " Please refer to section 3.7 of EDID Specification 1.4" + Combo $Override_EDID_Data_9, "Override the EDID values", &No_Yes_List, + Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" + EditNum $Red_Green_9, " Red_Green_bits (Bits 1&0 at 19h)" , EHEX, + Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" + EditNum $Blue_White_9, " Blue_White_bits (Bits 1&0 at 20h)" , EHEX, + Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" + EditNum $Red_x_9, " Red_x (Bits 9->2 at 1Bh)" , EHEX, + Help " Bits 9->2 of red color x coordinate" + EditNum $Red_y_9, " Red_y (Bits 9->2 at 1Ch)" , EHEX, + Help " Bits 9->2 of red color y coordinate" + EditNum $Green_x_9, " Green_x (Bits 9->2 at 1Dh)" , EHEX, + Help " Bits 9->2 of Green color x coordinate" + EditNum $Green_y_9, " Green_y (Bits 9->2 at 1Eh)" , EHEX, + Help " Bits 9->2 of Green color y coordinate" + EditNum $Blue_x_9, " Blue_x (Bits 9->2 at 1Fh)" , EHEX, + Help " Bits 9->2 of Blue color x coordinate" + EditNum $Blue_y_9, " Blue_y (Bits 9->2 at 20h)" , EHEX, + Help " Bits 9->2 of Blue color y coordinate" + EditNum $White_x_9, " White_x (Bits 9->2 at 21h)" , EHEX, + Help " Bits 9->2 of White color x coordinate" + EditNum $White_y_9, " White_y (Bits 9->2 at 22h)" , EHEX, + Help " Bits 9->2 of White color y coordinate" + + EndPage ; Chromaticity Control + +EndPage +;============================================================================== +; Page - Panel #10 (1920x1200) Flat Panel parameters +;------------------------------------------------------------------------------ + +Page "Panel #10 " + + TitleB "Common LFP Features" + + EditText $Panel_Name_10, "\tLFP Panel Name:", + Help "This feature defines the LVDS panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated. " + + Combo $Enable_Scaling_10, "\tScale to Target Resolution:", &No_Yes_List, + Help "Selecting this feature will make the graphics driver to enable Scaling feature by taking the Horizontal and Vertical resolution\r\n" + "from Target X-Res and Target Y-Res fields.\r\n" + + EditNum $Panel_Width_10, "\tTarget X-Res:", DEC, + Help "This value specifies the Target X-Resolution for this panel." + + EditNum $Panel_Height_10, "\tTarget Y-Res:", DEC, + Help "This value specifies the Target Y-Resolutoin for this panel." + + + + + Combo $DPS_Panel_Type_10, " \tDPS Panel Type:", &DPS_Panel_Type_List, + Help "This feature allows OEM to select the DPS Panel Type.\r\n " + "Intel SDRRS Technology is a feature of the Intel graphics driver\r\n" + "which reduces display power\r\n" + "SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n" + "rate will not adversely impact the user experience\r\n" + "Seamless:- Allows power savings when on battery mode and when a lower refresh\r\n" + "rate will not adversely impact the user experience.Implements seamless refresh\r\n" + "rate switching, which eliminates the screen blink that occurred\r\n" + "during the refresh rate transitions\r\n" + + EditNum $Seamless_DRRS_Min_RR_10, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, + Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n\n" + "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" + + Combo $Blt_Control_10, "\tBackLight Technology:", &Blt_Control_Type_List, + Help "This feature allows OEM to select the Backlight Technology.\r\n " + + Title " " + Link "LFP PnP ID Table" , "LFP PnP ID" + Link "DTD Timings Table" , "DTD Timings" + Link "Backlight Control Parameters" , "Backlight Control Parameters" + Link "Chromaticity Control" , "Chromaticity Control" + + #if ($Int_LFP1_Type == 0x1806) + TitleB "Integrated eDP Features" + + + Combo $Enable_SSC10, " \teDP Spread Spectrum Clock:", &Disabled_Enabled_List, + Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " + Combo $eDP_Panel_Color_Depth_10, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, + Help "This feature specifies the color depth of eDP panel used. " + + Combo $eDP_VSwingPreEmph_10, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, + Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " + "For CherryTrail, based on the selection respective table will be used.\r\n" + "Tables for CherryTrail:-\r\n" + "------------------------------------------------------------------------------------------------------\n" + "|Low Power VSwing Pre-Emphasis Setting Table |\n" + "-----------------------------------------------------------------------------------------------------|\n" + "| | Pre-Emphasis (db) |\n" + "| |------------------------------------------------------------------------------------------|\n" + "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" + "| Voltage |------------------------------------------------------------------------- ---------------|\n" + "| Swing | Level 0/200 | 200mV,0db | 200mV,3.5db | 200mV,6db | 200mV,9db |\n" + "| (mV) |------------------------------------------------------------------------------------------|\n" + "| | Level 1/250 | 250mV,0db | 250mV,3.5db | 250mV,6db | NA |\n" + "| |------------------------------------------------------------------------------------------|\n" + "| | Level 2/300 | 300mV,0db | 300mV,3.5d | NA | NA |\n" + "| |------------------------------------------------------------------------------------------|\n" + "| | Level 3/350 | 350 mv, 0db | NA | NA | NA |\n" + "-----------------------------------------------------------------------------------------------------\n\n" + + "-----------------------------------------------------------------------------------------------------\n" + "|Default VSwing Pre-Emphasis Setting Table |\n" + "---------------------------------------------------------------------------------------------------|\n" + "| | Pre-Emphasis (db) |\n" + "| |----------------------------------------------------------------------------------------|\n" + "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" + "| Voltage |----------------------------------------------------------------------------------------|\n" + "| Swing | Level 0/400 | 400mV,0db | 400mV,3.5db | 400mV,6db | 400mV,9db |\n" + "| (mV) |----------------------------------------------------------------------------------------|\n" + "| | Level 1/600 | 600mV,0db | 600mV,3.5db | 600mV,6db | NA |\n" + "| |----------------------------------------------------------------------------------------|\n" + "| | Level 2/800 | 800mV,0db | 800mV,3.5db | NA | NA |\n" + "| |----------------------------------------------------------------------------------------|\n" + "| | Level 3/1200| 1200mV, 0db | NA | NA | NA |\n" + "-----------------------------------------------------------------------------------------------------\n\n" + + + Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Power Sequencing" + Link "eDP Fast Link Training Configuration" , "eDP Fast Link Training Configuration" + + Page "eDP Panel Power Sequencing" + Link "Close Table", ".." + Combo $eDP_T3_Optimization_10, "T3 optimization", &Disabled_Enabled_List, + Help "This feature enables or disables T3 optimization. \r\n" + "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" + "When disabled, VBIOS/Graphics driver will wait for T3 time before trying the first AUX transaction" + + EditNum $eDP_Vcc_To_Hpd_Delay_10, "LCDVCC to HPD high delay (T3):", DEC, + Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" + "Valid Range: 0 to 200msec\r\n" + + EditNum $eDP_DataOn_To_BkltEnable_Delay_10, "Valid video data to Backlight Enable delay (T8):", DEC, + Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" + "T8 is inclusive of T7.\r\n" + "Valid Range of T7: 0 to 50msec\r\n" + + EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_10, "PWM-On To Backlight Enable delay:", DEC, + Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" + "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" + "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" + + EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_10, "Backlight Disable to PWM-Off delay:", DEC, + Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" + "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" + "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" + + EditNum $eDP_BkltDisable_To_DataOff_Delay_10, "Backlight Disable to End of Valid video data delay (T9):", DEC, + Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" + + EditNum $eDP_DataOff_To_PowerOff_Delay_10, "End of Valid video data to Power-Off delay (T10):", DEC, + Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" + "Valid Range: 0 to 500 msec\r\n" + + EditNum $eDP_PowerCycle_Delay_10, "Power-off time (T12):", DEC, + Help "Using this field Power-off time can be specified in 100uS.\r\n" + + EndPage + + Page "eDP Fast Link Training Configuration" + + Link "Close Table" , ".." + Combo $Fast_Link_Training_Supported_10, " Is FastLinkTraining Feature Supported:", &No_Yes_List, + Help "This feature if set to Yes will enable " + "Fast Link Training for eDp, if Panel also supports it." + + Combo $eDP_Link_DataRate_10, " Data Rate:", &eDP_Link_DataRate_List, + Help "This feature allows for the selection of the " + "Data Rate for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + Combo $eDP_Link_LaneCount_10, " Lane Count:", &eDP_Link_LaneCount_List, + Help "This feature allows for the selection of the " + "Lane Count (Port Width) for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + Combo $eDP_Link_PreEmp_10, " Pre-Emphasis:", &eDP_Link_PreEmp_List, + Help "This feature allows for the selection of the " + "Pre-emphasis value for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" + "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" + "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" + "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" + "------------------------------------------------------------------------------------------------------------ \r\n" + + "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" + "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" + "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" + "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" + "------------------------------------------------------------------------------------------------------------ \r\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + Combo $eDP_Link_Vswing_10, " Voltage Swing:", &eDP_Link_VSwing_List, + Help "This feature allows for the selection of the " + "Voltage Swing value for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" + "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" + "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" + "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" + "------------------------------------------------------------------------------------------------------------ \r\n" + + "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" + "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" + "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" + "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" + "------------------------------------------------------------------------------------------------------------ \r\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + EndPage + #endif + + Page "DTD Timings" + + Link "Close Table" , ".." + + Table $DVO_Tbl_10 " DTD Timings Values", + Column "Timings" , 1 byte , EHEX, + Help "This feature allows for the definition of the DTD " + "timings parameters related to the LFP. The " + "table is the 18-byte DTD structure defined in the " + "VESA EDID version 1.x.\r\n" + "\r\n" + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" + "\tDB ?\t; Vertical Active in lines, LSB\r\n" + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Horizontal Image Size, LSB\r\n" + "\tDB ?\t; Vertical Image Size, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" + "\tDB 0\t; Horizontal Border in pixels\r\n" + "\tDB 0\t; Vertical Border in lines\r\n" + "\tDB ?\t; Flags:\r\n" + "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" + "\t \t; Bit 6-5: 00 = Reserved\r\n" + "\t \t; Bit 4-3: 11 = Digital Separate\r\n" + "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 0: 0 = Reserved" + + EndPage + + Page "LFP PnP ID" + + Link "Close Table" , ".." + + Table $LVDS_PnP_ID_10 " LFP PnP ID Values", + Column "PnP ID" , 1 byte , EHEX, + Help "This feature allows the 10 bytes of EDID Vendor / " + "Product ID starting at offset 08h to be used as a " + "PnP ID.\r\n" + "\r\n" + " Table Definition:\r\n" + " Word: ID Manufacturer Name\r\n" + " Word: ID Product Code\r\n" + " DWord: ID Serial Number\r\n" + " Byte: Week of Manufacture\r\n" + " Byte: Year of Manufacture" + + EndPage + + Page "Backlight Control Parameters" + + Link "Close Table" , ".." + + Combo $BLC_Inv_Type_10, " Inverter Type:", &Inv_Type_List, + Help "This feature allows for the selection of the " + "Backlight Inverter type that is to be used to " + "control the backlight brightness of the LFP. When " + "PWM is selected, the driver and VBIOS will control " + "the backlight brightness via the integrated PWM " + "solution for the applicable chipsets. When I2C is " + "selected, the driver and VBIOS will control the " + "backlight brightness via the I2C solution for the " + "applicable chipsets. When None/External is " + "selected, the system BIOS will control the backlight " + "brightness via the external solution." + + Combo $Lfp_Pwm_Source_Selection_10, " Pwm Source Selection:", &Edp_Pwm_Source_List, + Help "This field allows to select the Source of the PWM to be used " + "for the selected Local Flat Panel.\r\n" + "\r\n" + + Combo $BLC_Inv_Polarity_10, " Inverter Polarity:", &Inv_Polarity_List, + Help "This feature allows the backlight inverter polarity " + "to be specified.\r\n" + "\r\n" + "Normal means 0 value is minimum brightness.\r\n" + "Inverted means 0 value is maximum brightness." + + EditNum $BLC_Min_Brightness_10, " Minimum Brightness:", DEC, + Help "This feature allows defining the absolute minimum " + "backlight brightness setting. The graphics driver " + "will never decrease the backlight less than this " + "value. The value must be specified using normal " + "polarity semantics." + +EditNum $POST_BL_Brightness_10, " POST Backlight Intensity:", DEC, + Help "This feature is used to set default brightness value at POST." + "This is configurable field of 0-255. Value of 0 indicates 0 brightness, 255 indicates maximum brightness. " + + EditNum $PWM_Frequency_10, " PWM Inverter Frequency (Hz):", DEC, + Help "This feature allows for the definition of the " + "frequency needed for PWM Inverter.\r\n" + "\r\n" + "Note: The frequency range, entered as a decimal " + "number, for the integrated PWM is 200Hz - 40KHz." + EndPage + + + + Page "Chromaticity Control" + Link "Close Table" , ".." + + Combo $Chromacity_Enable_10, "Chromaticity Control Feature", &Disabled_Enabled_List, + Help " This bit enables Chromaticity feature. \r\n" + " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" + " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" + " Please refer to section 3.7 of EDID Specification 1.4" + Combo $Override_EDID_Data_10, "Override the EDID values", &No_Yes_List, + Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" + EditNum $Red_Green_10, " Red_Green_bits (Bits 1&0 at 19h)" , EHEX, + Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" + EditNum $Blue_White_10, " Blue_White_bits (Bits 1&0 at 20h)" , EHEX, + Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" + EditNum $Red_x_10, " Red_x (Bits 9->2 at 1Bh)" , EHEX, + Help " Bits 9->2 of red color x coordinate" + EditNum $Red_y_10, " Red_y (Bits 9->2 at 1Ch)" , EHEX, + Help " Bits 9->2 of red color y coordinate" + EditNum $Green_x_10, " Green_x (Bits 9->2 at 1Dh)" , EHEX, + Help " Bits 9->2 of Green color x coordinate" + EditNum $Green_y_10, " Green_y (Bits 9->2 at 1Eh)" , EHEX, + Help " Bits 9->2 of Green color y coordinate" + EditNum $Blue_x_10, " Blue_x (Bits 9->2 at 1Fh)" , EHEX, + Help " Bits 9->2 of Blue color x coordinate" + EditNum $Blue_y_10, " Blue_y (Bits 9->2 at 20h)" , EHEX, + Help " Bits 9->2 of Blue color y coordinate" + EditNum $White_x_10, " White_x (Bits 9->2 at 21h)" , EHEX, + Help " Bits 9->2 of White color x coordinate" + EditNum $White_y_10, " White_y (Bits 9->2 at 22h)" , EHEX, + Help " Bits 9->2 of White color y coordinate" + + EndPage ; Chromaticity Control + +EndPage +;============================================================================== +; Page - Panel #11 (Reserved) Flat Panel parameters +;------------------------------------------------------------------------------ + +Page "Panel #11 " + + TitleB "Common LFP Features" + + EditText $Panel_Name_11, "\tLFP Panel Name:", + Help "This feature defines the LVDS panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated. " + + Combo $Enable_Scaling_11, "\tScale to Target Resolution:", &No_Yes_List, + Help "Selecting this feature will make the graphics driver to enable Scaling feature by taking the Horizontal and Vertical resolution\r\n" + "from Target X-Res and Target Y-Res fields.\r\n" + + EditNum $Panel_Width_11, "\tTarget X-Res:", DEC, + Help "This value specifies the Target X-Resolution for this panel." + + EditNum $Panel_Height_11, "\tTarget Y-Res:", DEC, + Help "This value specifies the Target Y-Resolutoin for this panel." + + + + + Combo $DPS_Panel_Type_11, " \tDPS Panel Type:", &DPS_Panel_Type_List, + Help "This feature allows OEM to select the DPS Panel Type.\r\n " + "Intel SDRRS Technology is a feature of the Intel graphics driver\r\n" + "which reduces display power\r\n" + "SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n" + "rate will not adversely impact the user experience\r\n" + "Seamless:- Allows power savings when on battery mode and when a lower refresh\r\n" + "rate will not adversely impact the user experience.Implements seamless refresh\r\n" + "rate switching, which eliminates the screen blink that occurred\r\n" + "during the refresh rate transitions\r\n" + + EditNum $Seamless_DRRS_Min_RR_11, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, + Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n\n" + "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" + + Combo $Blt_Control_11, "\tBackLight Technology:", &Blt_Control_Type_List, + Help "This feature allows OEM to select the Backlight Technology.\r\n " + + Title " " + Link "LFP PnP ID Table" , "LFP PnP ID" + Link "DTD Timings Table" , "DTD Timings" + Link "Backlight Control Parameters" , "Backlight Control Parameters" + Link "Chromaticity Control" , "Chromaticity Control" + + #if ($Int_LFP1_Type == 0x1806) + TitleB "Integrated eDP Features" + + +Combo $Enable_SSC11, " \teDP Spread Spectrum Clock:", &Disabled_Enabled_List, +Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " + Combo $eDP_Panel_Color_Depth_11, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, + Help "This feature specifies the color depth of eDP panel used. " + + Combo $eDP_VSwingPreEmph_11, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, + Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " + "For CherryTrail, based on the selection respective table will be used.\r\n" + "Tables for CherryTrail:-\r\n" + "------------------------------------------------------------------------------------------------------\n" + "|Low Power VSwing Pre-Emphasis Setting Table |\n" + "-----------------------------------------------------------------------------------------------------|\n" + "| | Pre-Emphasis (db) |\n" + "| |------------------------------------------------------------------------------------------|\n" + "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" + "| Voltage |------------------------------------------------------------------------- ---------------|\n" + "| Swing | Level 0/200 | 200mV,0db | 200mV,3.5db | 200mV,6db | 200mV,9db |\n" + "| (mV) |------------------------------------------------------------------------------------------|\n" + "| | Level 1/250 | 250mV,0db | 250mV,3.5db | 250mV,6db | NA |\n" + "| |------------------------------------------------------------------------------------------|\n" + "| | Level 2/300 | 300mV,0db | 300mV,3.5d | NA | NA |\n" + "| |------------------------------------------------------------------------------------------|\n" + "| | Level 3/350 | 350 mv, 0db | NA | NA | NA |\n" + "-----------------------------------------------------------------------------------------------------\n\n" + + "-----------------------------------------------------------------------------------------------------\n" + "|Default VSwing Pre-Emphasis Setting Table |\n" + "---------------------------------------------------------------------------------------------------|\n" + "| | Pre-Emphasis (db) |\n" + "| |----------------------------------------------------------------------------------------|\n" + "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" + "| Voltage |----------------------------------------------------------------------------------------|\n" + "| Swing | Level 0/400 | 400mV,0db | 400mV,3.5db | 400mV,6db | 400mV,9db |\n" + "| (mV) |----------------------------------------------------------------------------------------|\n" + "| | Level 1/600 | 600mV,0db | 600mV,3.5db | 600mV,6db | NA |\n" + "| |----------------------------------------------------------------------------------------|\n" + "| | Level 2/800 | 800mV,0db | 800mV,3.5db | NA | NA |\n" + "| |----------------------------------------------------------------------------------------|\n" + "| | Level 3/1200| 1200mV, 0db | NA | NA | NA |\n" + "-----------------------------------------------------------------------------------------------------\n\n" + + + Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Power Sequencing" + Link "eDP Fast Link Training Configuration" , "eDP Fast Link Training Configuration" + + Page "eDP Panel Power Sequencing" + Link "Close Table", ".." + + Combo $eDP_T3_Optimization_11, "T3 optimization", &Disabled_Enabled_List, + Help "This feature enables or disables T3 optimization. \r\n" + "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" + "When disabled, VBIOS/Graphics driver will wait for T3 time before trying the first AUX transaction" + + EditNum $eDP_Vcc_To_Hpd_Delay_11, "LCDVCC to HPD high delay (T3):", DEC, + Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" + "Valid Range: 0 to 200msec\r\n" + + EditNum $eDP_DataOn_To_BkltEnable_Delay_11, "Valid video data to Backlight Enable delay (T8):", DEC, + Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" + "T8 is inclusive of T7.\r\n" + "Valid Range of T7: 0 to 50msec\r\n" + + EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_11, "PWM-On To Backlight Enable delay:", DEC, + Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" + "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" + "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" + + EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_11, "Backlight Disable to PWM-Off delay:", DEC, + Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" + "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" + "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" + + EditNum $eDP_BkltDisable_To_DataOff_Delay_11, "Backlight Disable to End of Valid video data delay (T9):", DEC, + Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" + + EditNum $eDP_DataOff_To_PowerOff_Delay_11, "End of Valid video data to Power-Off delay (T10):", DEC, + Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" + "Valid Range: 0 to 500 msec\r\n" + + EditNum $eDP_PowerCycle_Delay_11, "Power-off time (T12):", DEC, + Help "Using this field Power-off time can be specified in 100uS.\r\n" + + EndPage + + Page "eDP Fast Link Training Configuration" + + Link "Close Table" , ".." + Combo $Fast_Link_Training_Supported_11, " Is FastLinkTraining Feature Supported:", &No_Yes_List, + Help "This feature if set to Yes will enable " + "Fast Link Training for eDp, if Panel also supports it." + + Combo $eDP_Link_DataRate_11, " Data Rate:", &eDP_Link_DataRate_List, + Help "This feature allows for the selection of the " + "Data Rate for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + Combo $eDP_Link_LaneCount_11, " Lane Count:", &eDP_Link_LaneCount_List, + Help "This feature allows for the selection of the " + "Lane Count (Port Width) for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + Combo $eDP_Link_PreEmp_11, " Pre-Emphasis:", &eDP_Link_PreEmp_List, + Help "This feature allows for the selection of the " + "Pre-emphasis value for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" + "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" + "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" + "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" + "------------------------------------------------------------------------------------------------------------ \r\n" + + "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" + "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" + "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" + "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" + "------------------------------------------------------------------------------------------------------------ \r\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + Combo $eDP_Link_Vswing_11, " Voltage Swing:", &eDP_Link_VSwing_List, + Help "This feature allows for the selection of the " + "Voltage Swing value for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" + "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" + "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" + "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" + "------------------------------------------------------------------------------------------------------------ \r\n" + + "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" + "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" + "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" + "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" + "------------------------------------------------------------------------------------------------------------ \r\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + EndPage + #endif + + Page "DTD Timings" + + Link "Close Table" , ".." + + Table $DVO_Tbl_11 " DTD Timings Values", + Column "Timings" , 1 byte , EHEX, + Help "This feature allows for the definition of the DTD " + "timings parameters related to the LFP. The " + "table is the 18-byte DTD structure defined in the " + "VESA EDID version 1.x.\r\n" + "\r\n" + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" + "\tDB ?\t; Vertical Active in lines, LSB\r\n" + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Horizontal Image Size, LSB\r\n" + "\tDB ?\t; Vertical Image Size, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" + "\tDB 0\t; Horizontal Border in pixels\r\n" + "\tDB 0\t; Vertical Border in lines\r\n" + "\tDB ?\t; Flags:\r\n" + "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" + "\t \t; Bit 6-5: 00 = Reserved\r\n" + "\t \t; Bit 4-3: 11 = Digital Separate\r\n" + "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 0: 0 = Reserved" + + EndPage + + Page "LFP PnP ID" + + Link "Close Table" , ".." + + Table $LVDS_PnP_ID_11 " LFP PnP ID Values", + Column "PnP ID" , 1 byte , EHEX, + Help "This feature allows the 10 bytes of EDID Vendor / " + "Product ID starting at offset 08h to be used as a " + "PnP ID.\r\n" + "\r\n" + " Table Definition:\r\n" + " Word: ID Manufacturer Name\r\n" + " Word: ID Product Code\r\n" + " DWord: ID Serial Number\r\n" + " Byte: Week of Manufacture\r\n" + " Byte: Year of Manufacture" + + EndPage + + Page "Backlight Control Parameters" + + Link "Close Table" , ".." + + Combo $BLC_Inv_Type_11, " Inverter Type:", &Inv_Type_List, + Help "This feature allows for the selection of the " + "Backlight Inverter type that is to be used to " + "control the backlight brightness of the LFP. When " + "PWM is selected, the driver and VBIOS will control " + "the backlight brightness via the integrated PWM " + "solution for the applicable chipsets. When I2C is " + "selected, the driver and VBIOS will control the " + "backlight brightness via the I2C solution for the " + "applicable chipsets. When None/External is " + "selected, the system BIOS will control the backlight " + "brightness via the external solution." + + Combo $Lfp_Pwm_Source_Selection_11, " Pwm Source Selection:", &Edp_Pwm_Source_List, + Help "This field allows to select the Source of the PWM to be used " + "for the selected Local Flat Panel.\r\n" + "\r\n" + + Combo $BLC_Inv_Polarity_11, " Inverter Polarity:", &Inv_Polarity_List, + Help "This feature allows the backlight inverter polarity " + "to be specified.\r\n" + "\r\n" + "Normal means 0 value is minimum brightness.\r\n" + "Inverted means 0 value is maximum brightness." + + EditNum $BLC_Min_Brightness_11, " Minimum Brightness:", DEC, + Help "This feature allows defining the absolute minimum " + "backlight brightness setting. The graphics driver " + "will never decrease the backlight less than this " + "value. The value must be specified using normal " + "polarity semantics." + +EditNum $POST_BL_Brightness_11, " POST Backlight Intensity:", DEC, + Help "This feature is used to set default brightness value at POST." + "This is configurable field of 0-255. Value of 0 indicates 0 brightness, 255 indicates maximum brightness. " + + EditNum $PWM_Frequency_11, " PWM Inverter Frequency (Hz):", DEC, + Help "This feature allows for the definition of the " + "frequency needed for PWM Inverter.\r\n" + "\r\n" + "Note: The frequency range, entered as a decimal " + "number, for the integrated PWM is 200Hz - 40KHz." + EndPage + + + + Page "Chromaticity Control" + Link "Close Table" , ".." + + Combo $Chromacity_Enable_11, "Chromaticity Control Feature", &Disabled_Enabled_List, + Help " This bit enables Chromaticity feature. \r\n" + " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" + " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" + " Please refer to section 3.7 of EDID Specification 1.4" + Combo $Override_EDID_Data_11, "Override the EDID values", &No_Yes_List, + Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" + EditNum $Red_Green_11, " Red_Green_bits (Bits 1&0 at 19h)" , EHEX, + Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" + EditNum $Blue_White_11, " Blue_White_bits (Bits 1&0 at 20h)" , EHEX, + Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" + EditNum $Red_x_11, " Red_x (Bits 9->2 at 1Bh)" , EHEX, + Help " Bits 9->2 of red color x coordinate" + EditNum $Red_y_11, " Red_y (Bits 9->2 at 1Ch)" , EHEX, + Help " Bits 9->2 of red color y coordinate" + EditNum $Green_x_11, " Green_x (Bits 9->2 at 1Dh)" , EHEX, + Help " Bits 9->2 of Green color x coordinate" + EditNum $Green_y_11, " Green_y (Bits 9->2 at 1Eh)" , EHEX, + Help " Bits 9->2 of Green color y coordinate" + EditNum $Blue_x_11, " Blue_x (Bits 9->2 at 1Fh)" , EHEX, + Help " Bits 9->2 of Blue color x coordinate" + EditNum $Blue_y_11, " Blue_y (Bits 9->2 at 20h)" , EHEX, + Help " Bits 9->2 of Blue color y coordinate" + EditNum $White_x_11, " White_x (Bits 9->2 at 21h)" , EHEX, + Help " Bits 9->2 of White color x coordinate" + EditNum $White_y_11, " White_y (Bits 9->2 at 22h)" , EHEX, + Help " Bits 9->2 of White color y coordinate" + + EndPage ; Chromaticity Control +EndPage +;============================================================================== +; Page - Panel #12 (Reserved) Flat Panel parameters +;------------------------------------------------------------------------------ + +Page "Panel #12 " + + TitleB "Common LFP Features" + + EditText $Panel_Name_12, "\tLFP Panel Name:", + Help "This feature defines the LVDS panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated. " + + Combo $Enable_Scaling_12, "\tScale to Target Resolution:", &No_Yes_List, + Help "Selecting this feature will make the graphics driver to enable Scaling feature by taking the Horizontal and Vertical resolution\r\n" + "from Target X-Res and Target Y-Res fields.\r\n" + + EditNum $Panel_Width_12, "\tTarget X-Res:", DEC, + Help "This value specifies the Target X-Resolution for this panel." + + EditNum $Panel_Height_12, "\tTarget Y-Res:", DEC, + Help "This value specifies the Target Y-Resolutoin for this panel." + + + + Combo $DPS_Panel_Type_12, " \tDPS Panel Type:", &DPS_Panel_Type_List, + Help "This feature allows OEM to select the DPS Panel Type.\r\n " + "Intel SDRRS Technology is a feature of the Intel graphics driver\r\n" + "which reduces display power\r\n" + "SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n" + "rate will not adversely impact the user experience\r\n" + "Seamless:- Allows power savings when on battery mode and when a lower refresh\r\n" + "rate will not adversely impact the user experience.Implements seamless refresh\r\n" + "rate switching, which eliminates the screen blink that occurred\r\n" + "during the refresh rate transitions\r\n" + + EditNum $Seamless_DRRS_Min_RR_12, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, + Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n\n" + "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" + + Combo $Blt_Control_12, "\tBackLight Technology:", &Blt_Control_Type_List, + Help "This feature allows OEM to select the Backlight Technology.\r\n " + + Title " " + Link "LFP PnP ID Table" , "LFP PnP ID" + Link "DTD Timings Table" , "DTD Timings" + Link "Backlight Control Parameters" , "Backlight Control Parameters" + Link "Chromaticity Control" , "Chromaticity Control" + + #if ($Int_LFP1_Type == 0x1806) + TitleB "Integrated eDP Features" + + +Combo $Enable_SSC12, " \teDP Spread Spectrum Clock:", &Disabled_Enabled_List, +Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " + + Combo $eDP_Panel_Color_Depth_12, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, + Help "This feature specifies the color depth of eDP panel used. " + + Combo $eDP_VSwingPreEmph_12, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, + Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " + "For CherryTrail, based on the selection respective table will be used.\r\n" + "Tables for CherryTrail:-\r\n" + "------------------------------------------------------------------------------------------------------\n" + "|Low Power VSwing Pre-Emphasis Setting Table |\n" + "-----------------------------------------------------------------------------------------------------|\n" + "| | Pre-Emphasis (db) |\n" + "| |------------------------------------------------------------------------------------------|\n" + "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" + "| Voltage |------------------------------------------------------------------------- ---------------|\n" + "| Swing | Level 0/200 | 200mV,0db | 200mV,3.5db | 200mV,6db | 200mV,9db |\n" + "| (mV) |------------------------------------------------------------------------------------------|\n" + "| | Level 1/250 | 250mV,0db | 250mV,3.5db | 250mV,6db | NA |\n" + "| |------------------------------------------------------------------------------------------|\n" + "| | Level 2/300 | 300mV,0db | 300mV,3.5d | NA | NA |\n" + "| |------------------------------------------------------------------------------------------|\n" + "| | Level 3/350 | 350 mv, 0db | NA | NA | NA |\n" + "-----------------------------------------------------------------------------------------------------\n\n" + + "-----------------------------------------------------------------------------------------------------\n" + "|Default VSwing Pre-Emphasis Setting Table |\n" + "---------------------------------------------------------------------------------------------------|\n" + "| | Pre-Emphasis (db) |\n" + "| |----------------------------------------------------------------------------------------|\n" + "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" + "| Voltage |----------------------------------------------------------------------------------------|\n" + "| Swing | Level 0/400 | 400mV,0db | 400mV,3.5db | 400mV,6db | 400mV,9db |\n" + "| (mV) |----------------------------------------------------------------------------------------|\n" + "| | Level 1/600 | 600mV,0db | 600mV,3.5db | 600mV,6db | NA |\n" + "| |----------------------------------------------------------------------------------------|\n" + "| | Level 2/800 | 800mV,0db | 800mV,3.5db | NA | NA |\n" + "| |----------------------------------------------------------------------------------------|\n" + "| | Level 3/1200| 1200mV, 0db | NA | NA | NA |\n" + "-----------------------------------------------------------------------------------------------------\n\n" + + + Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Power Sequencing" + Link "eDP Fast Link Training Configuration" , "eDP Fast Link Training Configuration" + + Page "eDP Panel Power Sequencing" + Link "Close Table", ".." + + Combo $eDP_T3_Optimization_12, "T3 optimization", &Disabled_Enabled_List, + Help "This feature enables or disables T3 optimization. \r\n" + "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" + "When disabled, VBIOS/Graphics driver will wait for T3 time before trying the first AUX transaction" + + EditNum $eDP_Vcc_To_Hpd_Delay_12, "LCDVCC to HPD high delay (T3):", DEC, + Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" + "Valid Range: 0 to 200msec\r\n" + + EditNum $eDP_DataOn_To_BkltEnable_Delay_12, "Valid video data to Backlight Enable delay (T8):", DEC, + Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" + "T8 is inclusive of T7.\r\n" + "Valid Range of T7: 0 to 50msec\r\n" + + EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_12, "PWM-On To Backlight Enable delay:", DEC, + Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" + "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" + "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" + + EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_12, "Backlight Disable to PWM-Off delay:", DEC, + Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" + "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" + "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" + + EditNum $eDP_BkltDisable_To_DataOff_Delay_12, "Backlight Disable to End of Valid video data delay (T9):", DEC, + Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" + + EditNum $eDP_DataOff_To_PowerOff_Delay_12, "End of Valid video data to Power-Off delay (T10):", DEC, + Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" + "Valid Range: 0 to 500 msec\r\n" + + EditNum $eDP_PowerCycle_Delay_12, "Power-off time (T12):", DEC, + Help "Using this field Power-off time can be specified in 100uS.\r\n" + + EndPage + + Page "eDP Fast Link Training Configuration" + + Link "Close Table" , ".." + Combo $Fast_Link_Training_Supported_12, " Is FastLinkTraining Feature Supported:", &No_Yes_List, + Help "This feature if set to Yes will enable " + "Fast Link Training for eDp, if Panel also supports it." + + Combo $eDP_Link_DataRate_12, " Data Rate:", &eDP_Link_DataRate_List, + Help "This feature allows for the selection of the " + "Data Rate for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + Combo $eDP_Link_LaneCount_12, " Lane Count:", &eDP_Link_LaneCount_List, + Help "This feature allows for the selection of the " + "Lane Count (Port Width) for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + Combo $eDP_Link_PreEmp_12, " Pre-Emphasis:", &eDP_Link_PreEmp_List, + Help "This feature allows for the selection of the " + "Pre-emphasis value for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" + "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" + "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" + "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" + "------------------------------------------------------------------------------------------------------------ \r\n" + + "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" + "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" + "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" + "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" + "------------------------------------------------------------------------------------------------------------ \r\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + Combo $eDP_Link_Vswing_12, " Voltage Swing:", &eDP_Link_VSwing_List, + Help "This feature allows for the selection of the " + "Voltage Swing value for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" + "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" + "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" + "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" + "------------------------------------------------------------------------------------------------------------ \r\n" + + "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" + "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" + "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" + "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" + "------------------------------------------------------------------------------------------------------------ \r\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + EndPage + #endif + + Page "DTD Timings" + + Link "Close Table" , ".." + + Table $DVO_Tbl_12 " DTD Timings Values", + Column "Timings" , 1 byte , EHEX, + Help "This feature allows for the definition of the DTD " + "timings parameters related to the LFP. The " + "table is the 18-byte DTD structure defined in the " + "VESA EDID version 1.x.\r\n" + "\r\n" + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" + "\tDB ?\t; Vertical Active in lines, LSB\r\n" + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Horizontal Image Size, LSB\r\n" + "\tDB ?\t; Vertical Image Size, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" + "\tDB 0\t; Horizontal Border in pixels\r\n" + "\tDB 0\t; Vertical Border in lines\r\n" + "\tDB ?\t; Flags:\r\n" + "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" + "\t \t; Bit 6-5: 00 = Reserved\r\n" + "\t \t; Bit 4-3: 11 = Digital Separate\r\n" + "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 0: 0 = Reserved" + + EndPage + + Page "LFP PnP ID" + + Link "Close Table" , ".." + + Table $LVDS_PnP_ID_12 " LFP PnP ID Values", + Column "PnP ID" , 1 byte , EHEX, + Help "This feature allows the 10 bytes of EDID Vendor / " + "Product ID starting at offset 08h to be used as a " + "PnP ID.\r\n" + "\r\n" + " Table Definition:\r\n" + " Word: ID Manufacturer Name\r\n" + " Word: ID Product Code\r\n" + " DWord: ID Serial Number\r\n" + " Byte: Week of Manufacture\r\n" + " Byte: Year of Manufacture" + + EndPage + + Page "Backlight Control Parameters" + + Link "Close Table" , ".." + + Combo $BLC_Inv_Type_12, " Inverter Type:", &Inv_Type_List, + Help "This feature allows for the selection of the " + "Backlight Inverter type that is to be used to " + "control the backlight brightness of the LFP. When " + "PWM is selected, the driver and VBIOS will control " + "the backlight brightness via the integrated PWM " + "solution for the applicable chipsets. When I2C is " + "selected, the driver and VBIOS will control the " + "backlight brightness via the I2C solution for the " + "applicable chipsets. When None/External is " + "selected, the system BIOS will control the backlight " + "brightness via the external solution." + + Combo $Lfp_Pwm_Source_Selection_12, " Pwm Source Selection:", &Edp_Pwm_Source_List, + Help "This field allows to select the Source of the PWM to be used " + "for the selected Local Flat Panel.\r\n" + "\r\n" + + Combo $BLC_Inv_Polarity_12, " Inverter Polarity:", &Inv_Polarity_List, + Help "This feature allows the backlight inverter polarity " + "to be specified.\r\n" + "\r\n" + "Normal means 0 value is minimum brightness.\r\n" + "Inverted means 0 value is maximum brightness." + + EditNum $BLC_Min_Brightness_12, " Minimum Brightness:", DEC, + Help "This feature allows defining the absolute minimum " + "backlight brightness setting. The graphics driver " + "will never decrease the backlight less than this " + "value. The value must be specified using normal " + "polarity semantics." + +EditNum $POST_BL_Brightness_12, " POST Backlight Intensity:", DEC, + Help "This feature is used to set default brightness value at POST." + "This is configurable field of 0-255. Value of 0 indicates 0 brightness, 255 indicates maximum brightness. " + + EditNum $PWM_Frequency_12, " PWM Inverter Frequency (Hz):", DEC, + Help "This feature allows for the definition of the " + "frequency needed for PWM Inverter.\r\n" + "\r\n" + "Note: The frequency range, entered as a decimal " + "number, for the integrated PWM is 200Hz - 40KHz." + EndPage + + + + Page "Chromaticity Control" + Link "Close Table" , ".." + + Combo $Chromacity_Enable_12, "Chromaticity Control Feature", &Disabled_Enabled_List, + Help " This bit enables Chromaticity feature. \r\n" + " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" + " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" + " Please refer to section 3.7 of EDID Specification 1.4" + Combo $Override_EDID_Data_12, "Override the EDID values", &No_Yes_List, + Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" + EditNum $Red_Green_12, " Red_Green_bits (Bits 1&0 at 19h)" , EHEX, + Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" + EditNum $Blue_White_12, " Blue_White_bits (Bits 1&0 at 20h)" , EHEX, + Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" + EditNum $Red_x_12, " Red_x (Bits 9->2 at 1Bh)" , EHEX, + Help " Bits 9->2 of red color x coordinate" + EditNum $Red_y_12, " Red_y (Bits 9->2 at 1Ch)" , EHEX, + Help " Bits 9->2 of red color y coordinate" + EditNum $Green_x_12, " Green_x (Bits 9->2 at 1Dh)" , EHEX, + Help " Bits 9->2 of Green color x coordinate" + EditNum $Green_y_12, " Green_y (Bits 9->2 at 1Eh)" , EHEX, + Help " Bits 9->2 of Green color y coordinate" + EditNum $Blue_x_12, " Blue_x (Bits 9->2 at 1Fh)" , EHEX, + Help " Bits 9->2 of Blue color x coordinate" + EditNum $Blue_y_12, " Blue_y (Bits 9->2 at 20h)" , EHEX, + Help " Bits 9->2 of Blue color y coordinate" + EditNum $White_x_12, " White_x (Bits 9->2 at 21h)" , EHEX, + Help " Bits 9->2 of White color x coordinate" + EditNum $White_y_12, " White_y (Bits 9->2 at 22h)" , EHEX, + Help " Bits 9->2 of White color y coordinate" + + EndPage ; Chromaticity Control +EndPage +;============================================================================== +; Page - Panel #13 (Reserved) Flat Panel parameters +;------------------------------------------------------------------------------ + +Page "Panel #13 " + + TitleB "Common LFP Features" + + EditText $Panel_Name_13, "\tLFP Panel Name:", + Help "This feature defines the LVDS panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated. " + + Combo $Enable_Scaling_13, "\tScale to Target Resolution:", &No_Yes_List, + Help "Selecting this feature will make the graphics driver to enable Scaling feature by taking the Horizontal and Vertical resolution\r\n" + "from Target X-Res and Target Y-Res fields.\r\n" + + EditNum $Panel_Width_13, "\tTarget X-Res:", DEC, + Help "This value specifies the Target X-Resolution for this panel." + + EditNum $Panel_Height_13, "\tTarget Y-Res:", DEC, + Help "This value specifies the Target Y-Resolutoin for this panel." + + + + Combo $DPS_Panel_Type_13, " \tDPS Panel Type:", &DPS_Panel_Type_List, + Help "This feature allows OEM to select the DPS Panel Type.\r\n " + "Intel SDRRS Technology is a feature of the Intel graphics driver\r\n" + "which reduces display power\r\n" + "SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n" + "rate will not adversely impact the user experience\r\n" + "Seamless:- Allows power savings when on battery mode and when a lower refresh\r\n" + "rate will not adversely impact the user experience.Implements seamless refresh\r\n" + "rate switching, which eliminates the screen blink that occurred\r\n" + "during the refresh rate transitions\r\n" + + EditNum $Seamless_DRRS_Min_RR_13, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, + Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n\n" + "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" + + Combo $Blt_Control_13, "\tBackLight Technology:", &Blt_Control_Type_List, + Help "This feature allows OEM to select the Backlight Technology.\r\n " + + Title " " + Link "LFP PnP ID Table" , "LFP PnP ID" + Link "DTD Timings Table" , "DTD Timings" + Link "Backlight Control Parameters" , "Backlight Control Parameters" + Link "Chromaticity Control" , "Chromaticity Control" + + #if ($Int_LFP1_Type == 0x1806) + TitleB "Integrated eDP Features" + +Combo $Enable_SSC13, " \teDP Spread Spectrum Clock:", &Disabled_Enabled_List, +Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " + + + Combo $eDP_Panel_Color_Depth_13, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, + Help "This feature specifies the color depth of eDP panel used. " + + Combo $eDP_VSwingPreEmph_13, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, + Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " + "For CherryTrail, based on the selection respective table will be used.\r\n" + "Tables for CherryTrail:-\r\n" + "------------------------------------------------------------------------------------------------------\n" + "|Low Power VSwing Pre-Emphasis Setting Table |\n" + "-----------------------------------------------------------------------------------------------------|\n" + "| | Pre-Emphasis (db) |\n" + "| |------------------------------------------------------------------------------------------|\n" + "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" + "| Voltage |------------------------------------------------------------------------- ---------------|\n" + "| Swing | Level 0/200 | 200mV,0db | 200mV,3.5db | 200mV,6db | 200mV,9db |\n" + "| (mV) |------------------------------------------------------------------------------------------|\n" + "| | Level 1/250 | 250mV,0db | 250mV,3.5db | 250mV,6db | NA |\n" + "| |------------------------------------------------------------------------------------------|\n" + "| | Level 2/300 | 300mV,0db | 300mV,3.5d | NA | NA |\n" + "| |------------------------------------------------------------------------------------------|\n" + "| | Level 3/350 | 350 mv, 0db | NA | NA | NA |\n" + "-----------------------------------------------------------------------------------------------------\n\n" + + "-----------------------------------------------------------------------------------------------------\n" + "|Default VSwing Pre-Emphasis Setting Table |\n" + "---------------------------------------------------------------------------------------------------|\n" + "| | Pre-Emphasis (db) |\n" + "| |----------------------------------------------------------------------------------------|\n" + "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" + "| Voltage |----------------------------------------------------------------------------------------|\n" + "| Swing | Level 0/400 | 400mV,0db | 400mV,3.5db | 400mV,6db | 400mV,9db |\n" + "| (mV) |----------------------------------------------------------------------------------------|\n" + "| | Level 1/600 | 600mV,0db | 600mV,3.5db | 600mV,6db | NA |\n" + "| |----------------------------------------------------------------------------------------|\n" + "| | Level 2/800 | 800mV,0db | 800mV,3.5db | NA | NA |\n" + "| |----------------------------------------------------------------------------------------|\n" + "| | Level 3/1200| 1200mV, 0db | NA | NA | NA |\n" + "-----------------------------------------------------------------------------------------------------\n\n" + + + Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Power Sequencing" + Link "eDP Fast Link Training Configuration" , "eDP Fast Link Training Configuration" + + Page "eDP Panel Power Sequencing" + Link "Close Table", ".." + + Combo $eDP_T3_Optimization_13, "T3 optimization", &Disabled_Enabled_List, + Help "This feature enables or disables T3 optimization. \r\n" + "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" + "When disabled, VBIOS/Graphics driver will wait for T3 time before trying the first AUX transaction" + + EditNum $eDP_Vcc_To_Hpd_Delay_13, "LCDVCC to HPD high delay (T3):", DEC, + Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" + "Valid Range: 0 to 200msec\r\n" + + EditNum $eDP_DataOn_To_BkltEnable_Delay_13, "Valid video data to Backlight Enable delay (T8):", DEC, + Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" + "T8 is inclusive of T7.\r\n" + "Valid Range of T7: 0 to 50msec\r\n" + + EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_13, "PWM-On To Backlight Enable delay:", DEC, + Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" + "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" + "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" + + EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_13, "Backlight Disable to PWM-Off delay:", DEC, + Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" + "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" + "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" + + EditNum $eDP_BkltDisable_To_DataOff_Delay_13, "Backlight Disable to End of Valid video data delay (T9):", DEC, + Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" + + EditNum $eDP_DataOff_To_PowerOff_Delay_13, "End of Valid video data to Power-Off delay (T10):", DEC, + Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" + "Valid Range: 0 to 500 msec\r\n" + + EditNum $eDP_PowerCycle_Delay_13, "Power-off time (T12):", DEC, + Help "Using this field Power-off time can be specified in 100uS.\r\n" + + EndPage + + Page "eDP Fast Link Training Configuration" + + Link "Close Table" , ".." + Combo $Fast_Link_Training_Supported_13, " Is FastLinkTraining Feature Supported:", &No_Yes_List, + Help "This feature if set to Yes will enable " + "Fast Link Training for eDp, if Panel also supports it." + + Combo $eDP_Link_DataRate_13, " Data Rate:", &eDP_Link_DataRate_List, + Help "This feature allows for the selection of the " + "Data Rate for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + Combo $eDP_Link_LaneCount_13, " Lane Count:", &eDP_Link_LaneCount_List, + Help "This feature allows for the selection of the " + "Lane Count (Port Width) for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + Combo $eDP_Link_PreEmp_13, " Pre-Emphasis:", &eDP_Link_PreEmp_List, + Help "This feature allows for the selection of the " + "Pre-emphasis value for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" + "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" + "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" + "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" + "------------------------------------------------------------------------------------------------------------ \r\n" + + "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" + "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" + "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" + "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" + "------------------------------------------------------------------------------------------------------------ \r\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + Combo $eDP_Link_Vswing_13, " Voltage Swing:", &eDP_Link_VSwing_List, + Help "This feature allows for the selection of the " + "Voltage Swing value for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" + "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" + "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" + "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" + "------------------------------------------------------------------------------------------------------------ \r\n" + + "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" + "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" + "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" + "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" + "------------------------------------------------------------------------------------------------------------ \r\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + EndPage + #endif + + Page "DTD Timings" + + Link "Close Table" , ".." + + Table $DVO_Tbl_13 " DTD Timings Values", + Column "Timings" , 1 byte , EHEX, + Help "This feature allows for the definition of the DTD " + "timings parameters related to the LFP. The " + "table is the 18-byte DTD structure defined in the " + "VESA EDID version 1.x.\r\n" + "\r\n" + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" + "\tDB ?\t; Vertical Active in lines, LSB\r\n" + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Horizontal Image Size, LSB\r\n" + "\tDB ?\t; Vertical Image Size, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" + "\tDB 0\t; Horizontal Border in pixels\r\n" + "\tDB 0\t; Vertical Border in lines\r\n" + "\tDB ?\t; Flags:\r\n" + "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" + "\t \t; Bit 6-5: 00 = Reserved\r\n" + "\t \t; Bit 4-3: 11 = Digital Separate\r\n" + "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 0: 0 = Reserved" + + EndPage + + Page "LFP PnP ID" + + Link "Close Table" , ".." + + Table $LVDS_PnP_ID_13 " LFP PnP ID Values", + Column "PnP ID" , 1 byte , EHEX, + Help "This feature allows the 10 bytes of EDID Vendor / " + "Product ID starting at offset 08h to be used as a " + "PnP ID.\r\n" + "\r\n" + " Table Definition:\r\n" + " Word: ID Manufacturer Name\r\n" + " Word: ID Product Code\r\n" + " DWord: ID Serial Number\r\n" + " Byte: Week of Manufacture\r\n" + " Byte: Year of Manufacture" + + EndPage + + Page "Backlight Control Parameters" + + Link "Close Table" , ".." + + Combo $BLC_Inv_Type_13, " Inverter Type:", &Inv_Type_List, + Help "This feature allows for the selection of the " + "Backlight Inverter type that is to be used to " + "control the backlight brightness of the LFP. When " + "PWM is selected, the driver and VBIOS will control " + "the backlight brightness via the integrated PWM " + "solution for the applicable chipsets. When I2C is " + "selected, the driver and VBIOS will control the " + "backlight brightness via the I2C solution for the " + "applicable chipsets. When None/External is " + "selected, the system BIOS will control the backlight " + "brightness via the external solution." + + Combo $Lfp_Pwm_Source_Selection_13, " Pwm Source Selection:", &Edp_Pwm_Source_List, + Help "This field allows to select the Source of the PWM to be used " + "for the selected Local Flat Panel.\r\n" + "\r\n" + + Combo $BLC_Inv_Polarity_13, " Inverter Polarity:", &Inv_Polarity_List, + Help "This feature allows the backlight inverter polarity " + "to be specified.\r\n" + "\r\n" + "Normal means 0 value is minimum brightness.\r\n" + "Inverted means 0 value is maximum brightness." + + EditNum $BLC_Min_Brightness_13, " Minimum Brightness:", DEC, + Help "This feature allows defining the absolute minimum " + "backlight brightness setting. The graphics driver " + "will never decrease the backlight less than this " + "value. The value must be specified using normal " + "polarity semantics." + +EditNum $POST_BL_Brightness_13, " POST Backlight Intensity:", DEC, + Help "This feature is used to set default brightness value at POST." + "This is configurable field of 0-255. Value of 0 indicates 0 brightness, 255 indicates maximum brightness. " + + EditNum $PWM_Frequency_13, " PWM Inverter Frequency (Hz):", DEC, + Help "This feature allows for the definition of the " + "frequency needed for PWM Inverter.\r\n" + "\r\n" + "Note: The frequency range, entered as a decimal " + "number, for the integrated PWM is 200Hz - 40KHz." + EndPage + + Page "Chromaticity Control" + Link "Close Table" , ".." + + Combo $Chromacity_Enable_13, "Chromaticity Control Feature", &Disabled_Enabled_List, + Help " This bit enables Chromaticity feature. \r\n" + " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" + " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" + " Please refer to section 3.7 of EDID Specification 1.4" + Combo $Override_EDID_Data_13, "Override the EDID values", &No_Yes_List, + Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" + EditNum $Red_Green_13, " Red_Green_bits (Bits 1&0 at 19h)" , EHEX, + Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" + EditNum $Blue_White_13, " Blue_White_bits (Bits 1&0 at 20h)" , EHEX, + Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" + EditNum $Red_x_13, " Red_x (Bits 9->2 at 1Bh)" , EHEX, + Help " Bits 9->2 of red color x coordinate" + EditNum $Red_y_13, " Red_y (Bits 9->2 at 1Ch)" , EHEX, + Help " Bits 9->2 of red color y coordinate" + EditNum $Green_x_13, " Green_x (Bits 9->2 at 1Dh)" , EHEX, + Help " Bits 9->2 of Green color x coordinate" + EditNum $Green_y_13, " Green_y (Bits 9->2 at 1Eh)" , EHEX, + Help " Bits 9->2 of Green color y coordinate" + EditNum $Blue_x_13, " Blue_x (Bits 9->2 at 1Fh)" , EHEX, + Help " Bits 9->2 of Blue color x coordinate" + EditNum $Blue_y_13, " Blue_y (Bits 9->2 at 20h)" , EHEX, + Help " Bits 9->2 of Blue color y coordinate" + EditNum $White_x_13, " White_x (Bits 9->2 at 21h)" , EHEX, + Help " Bits 9->2 of White color x coordinate" + EditNum $White_y_13, " White_y (Bits 9->2 at 22h)" , EHEX, + Help " Bits 9->2 of White color y coordinate" + + EndPage ; Chromaticity Control + +EndPage +;============================================================================== +; Page - Panel #14 (1280x800) Flat Panel parameters +;------------------------------------------------------------------------------ + +Page "Panel #14 " + + TitleB "Common LFP Features" + + EditText $Panel_Name_14, "\tLFP Panel Name:", + Help "This feature defines the LVDS panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated. " + + Combo $Enable_Scaling_14, "\tScale to Target Resolution:", &No_Yes_List, + Help "Selecting this feature will make the graphics driver to enable Scaling feature by taking the Horizontal and Vertical resolution\r\n" + "from Target X-Res and Target Y-Res fields.\r\n" + + EditNum $Panel_Width_14, "\tTarget X-Res:", DEC, + Help "This value specifies the Target X-Resolution for this panel." + + EditNum $Panel_Height_14, "\tTarget Y-Res:", DEC, + Help "This value specifies the Target Y-Resolutoin for this panel." + + + + Combo $DPS_Panel_Type_14, " \tDPS Panel Type:", &DPS_Panel_Type_List, + Help "This feature allows OEM to select the DPS Panel Type.\r\n " + "Intel SDRRS Technology is a feature of the Intel graphics driver\r\n" + "which reduces display power\r\n" + "SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n" + "rate will not adversely impact the user experience\r\n" + "Seamless:- Allows power savings when on battery mode and when a lower refresh\r\n" + "rate will not adversely impact the user experience.Implements seamless refresh\r\n" + "rate switching, which eliminates the screen blink that occurred\r\n" + "during the refresh rate transitions\r\n" + + EditNum $Seamless_DRRS_Min_RR_14, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, + Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n\n" + "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" + + Combo $Blt_Control_14, "\tBackLight Technology:", &Blt_Control_Type_List, + Help "This feature allows OEM to select the Backlight Technology.\r\n " + + Title " " + Link "LFP PnP ID Table" , "LFP PnP ID" + Link "DTD Timings Table" , "DTD Timings" + Link "Backlight Control Parameters" , "Backlight Control Parameters" + Link "Chromaticity Control" , "Chromaticity Control" + + #if ($Int_LFP1_Type == 0x1806) + TitleB "Integrated eDP Features" + + +Combo $Enable_SSC14, " \teDP Spread Spectrum Clock:", &Disabled_Enabled_List, +Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " + + Combo $eDP_Panel_Color_Depth_14, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, + Help "This feature specifies the color depth of eDP panel used. " + + Combo $eDP_VSwingPreEmph_14, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, + Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " + "For CherryTrail, based on the selection respective table will be used.\r\n" + "Tables for CherryTrail:-\r\n" + "------------------------------------------------------------------------------------------------------\n" + "|Low Power VSwing Pre-Emphasis Setting Table |\n" + "-----------------------------------------------------------------------------------------------------|\n" + "| | Pre-Emphasis (db) |\n" + "| |------------------------------------------------------------------------------------------|\n" + "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" + "| Voltage |------------------------------------------------------------------------- ---------------|\n" + "| Swing | Level 0/200 | 200mV,0db | 200mV,3.5db | 200mV,6db | 200mV,9db |\n" + "| (mV) |------------------------------------------------------------------------------------------|\n" + "| | Level 1/250 | 250mV,0db | 250mV,3.5db | 250mV,6db | NA |\n" + "| |------------------------------------------------------------------------------------------|\n" + "| | Level 2/300 | 300mV,0db | 300mV,3.5d | NA | NA |\n" + "| |------------------------------------------------------------------------------------------|\n" + "| | Level 3/350 | 350 mv, 0db | NA | NA | NA |\n" + "-----------------------------------------------------------------------------------------------------\n\n" + + "-----------------------------------------------------------------------------------------------------\n" + "|Default VSwing Pre-Emphasis Setting Table |\n" + "---------------------------------------------------------------------------------------------------|\n" + "| | Pre-Emphasis (db) |\n" + "| |----------------------------------------------------------------------------------------|\n" + "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" + "| Voltage |----------------------------------------------------------------------------------------|\n" + "| Swing | Level 0/400 | 400mV,0db | 400mV,3.5db | 400mV,6db | 400mV,9db |\n" + "| (mV) |----------------------------------------------------------------------------------------|\n" + "| | Level 1/600 | 600mV,0db | 600mV,3.5db | 600mV,6db | NA |\n" + "| |----------------------------------------------------------------------------------------|\n" + "| | Level 2/800 | 800mV,0db | 800mV,3.5db | NA | NA |\n" + "| |----------------------------------------------------------------------------------------|\n" + "| | Level 3/1200| 1200mV, 0db | NA | NA | NA |\n" + "-----------------------------------------------------------------------------------------------------\n\n" + + + Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Power Sequencing" + Link "eDP Fast Link Training Configuration" , "eDP Fast Link Training Configuration" + + Page "eDP Panel Power Sequencing" + Link "Close Table", ".." + + Combo $eDP_T3_Optimization_14, "T3 optimization", &Disabled_Enabled_List, + Help "This feature enables or disables T3 optimization. \r\n" + "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" + "When disabled, VBIOS/Graphics driver will wait for T3 time before trying the first AUX transaction" + + EditNum $eDP_Vcc_To_Hpd_Delay_14, "LCDVCC to HPD high delay (T3):", DEC, + Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" + "Valid Range: 0 to 200msec\r\n" + + EditNum $eDP_DataOn_To_BkltEnable_Delay_14, "Valid video data to Backlight Enable delay (T8):", DEC, + Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" + "T8 is inclusive of T7.\r\n" + "Valid Range of T7: 0 to 50msec\r\n" + + EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_14, "PWM-On To Backlight Enable delay:", DEC, + Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" + "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" + "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" + + EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_14, "Backlight Disable to PWM-Off delay:", DEC, + Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" + "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" + "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" + + EditNum $eDP_BkltDisable_To_DataOff_Delay_14, "Backlight Disable to End of Valid video data delay (T9):", DEC, + Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" + + EditNum $eDP_DataOff_To_PowerOff_Delay_14, "End of Valid video data to Power-Off delay (T10):", DEC, + Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" + "Valid Range: 0 to 500 msec\r\n" + + EditNum $eDP_PowerCycle_Delay_14, "Power-off time (T12):", DEC, + Help "Using this field Power-off time can be specified in 100uS.\r\n" + + EndPage + + Page "eDP Fast Link Training Configuration" + + Link "Close Table" , ".." + Combo $Fast_Link_Training_Supported_14, " Is FastLinkTraining Feature Supported:", &No_Yes_List, + Help "This feature if set to Yes will enable " + "Fast Link Training for eDp, if Panel also supports it." + + Combo $eDP_Link_DataRate_14, " Data Rate:", &eDP_Link_DataRate_List, + Help "This feature allows for the selection of the " + "Data Rate for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + Combo $eDP_Link_LaneCount_14, " Lane Count:", &eDP_Link_LaneCount_List, + Help "This feature allows for the selection of the " + "Lane Count (Port Width) for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + Combo $eDP_Link_PreEmp_14, " Pre-Emphasis:", &eDP_Link_PreEmp_List, + Help "This feature allows for the selection of the " + "Pre-emphasis value for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" + "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" + "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" + "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" + "------------------------------------------------------------------------------------------------------------ \r\n" + + "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" + "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" + "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" + "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" + "------------------------------------------------------------------------------------------------------------ \r\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + Combo $eDP_Link_Vswing_14, " Voltage Swing:", &eDP_Link_VSwing_List, + Help "This feature allows for the selection of the " + "Voltage Swing value for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" + "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" + "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" + "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" + "------------------------------------------------------------------------------------------------------------ \r\n" + + "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" + "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" + "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" + "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" + "------------------------------------------------------------------------------------------------------------ \r\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + EndPage + #endif + + Page "DTD Timings" + + Link "Close Table" , ".." + + Table $DVO_Tbl_14 " DTD Timings Values", + Column "Timings" , 1 byte , EHEX, + Help "This feature allows for the definition of the DTD " + "timings parameters related to the LFP. The " + "table is the 18-byte DTD structure defined in the " + "VESA EDID version 1.x.\r\n" + "\r\n" + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" + "\tDB ?\t; Vertical Active in lines, LSB\r\n" + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Horizontal Image Size, LSB\r\n" + "\tDB ?\t; Vertical Image Size, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" + "\tDB 0\t; Horizontal Border in pixels\r\n" + "\tDB 0\t; Vertical Border in lines\r\n" + "\tDB ?\t; Flags:\r\n" + "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" + "\t \t; Bit 6-5: 00 = Reserved\r\n" + "\t \t; Bit 4-3: 11 = Digital Separate\r\n" + "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 0: 0 = Reserved" + + EndPage + + Page "LFP PnP ID" + + Link "Close Table" , ".." + + Table $LVDS_PnP_ID_14 " LFP PnP ID Values", + Column "PnP ID" , 1 byte , EHEX, + Help "This feature allows the 10 bytes of EDID Vendor / " + "Product ID starting at offset 08h to be used as a " + "PnP ID.\r\n" + "\r\n" + " Table Definition:\r\n" + " Word: ID Manufacturer Name\r\n" + " Word: ID Product Code\r\n" + " DWord: ID Serial Number\r\n" + " Byte: Week of Manufacture\r\n" + " Byte: Year of Manufacture" + + EndPage + + Page "Backlight Control Parameters" + + Link "Close Table" , ".." + + Combo $BLC_Inv_Type_14, " Inverter Type:", &Inv_Type_List, + Help "This feature allows for the selection of the " + "Backlight Inverter type that is to be used to " + "control the backlight brightness of the LFP. When " + "PWM is selected, the driver and VBIOS will control " + "the backlight brightness via the integrated PWM " + "solution for the applicable chipsets. When I2C is " + "selected, the driver and VBIOS will control the " + "backlight brightness via the I2C solution for the " + "applicable chipsets. When None/External is " + "selected, the system BIOS will control the backlight " + "brightness via the external solution." + + Combo $Lfp_Pwm_Source_Selection_14, " Pwm Source Selection:", &Edp_Pwm_Source_List, + Help "This field allows to select the Source of the PWM to be used " + "for the selected Local Flat Panel.\r\n" + "\r\n" + + Combo $BLC_Inv_Polarity_14, " Inverter Polarity:", &Inv_Polarity_List, + Help "This feature allows the backlight inverter polarity " + "to be specified.\r\n" + "\r\n" + "Normal means 0 value is minimum brightness.\r\n" + "Inverted means 0 value is maximum brightness." + + EditNum $BLC_Min_Brightness_14, " Minimum Brightness:", DEC, + Help "This feature allows defining the absolute minimum " + "backlight brightness setting. The graphics driver " + "will never decrease the backlight less than this " + "value. The value must be specified using normal " + "polarity semantics." + +EditNum $POST_BL_Brightness_14, " POST Backlight Intensity:", DEC, + Help "This feature is used to set default brightness value at POST." + "This is configurable field of 0-255. Value of 0 indicates 0 brightness, 255 indicates maximum brightness. " + + EditNum $PWM_Frequency_14, " PWM Inverter Frequency (Hz):", DEC, + Help "This feature allows for the definition of the " + "frequency needed for PWM Inverter.\r\n" + "\r\n" + "Note: The frequency range, entered as a decimal " + "number, for the integrated PWM is 200Hz - 40KHz." + EndPage + + Page "Chromaticity Control" + Link "Close Table" , ".." + + Combo $Chromacity_Enable_14, "Chromaticity Control Feature", &Disabled_Enabled_List, + Help " This bit enables Chromaticity feature. \r\n" + " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" + " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" + " Please refer to section 3.7 of EDID Specification 1.4" + Combo $Override_EDID_Data_14, "Override the EDID values", &No_Yes_List, + Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" + EditNum $Red_Green_14, " Red_Green_bits (Bits 1&0 at 19h)" , EHEX, + Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" + EditNum $Blue_White_14, " Blue_White_bits (Bits 1&0 at 20h)" , EHEX, + Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" + EditNum $Red_x_14, " Red_x (Bits 9->2 at 1Bh)" , EHEX, + Help " Bits 9->2 of red color x coordinate" + EditNum $Red_y_14, " Red_y (Bits 9->2 at 1Ch)" , EHEX, + Help " Bits 9->2 of red color y coordinate" + EditNum $Green_x_14, " Green_x (Bits 9->2 at 1Dh)" , EHEX, + Help " Bits 9->2 of Green color x coordinate" + EditNum $Green_y_14, " Green_y (Bits 9->2 at 1Eh)" , EHEX, + Help " Bits 9->2 of Green color y coordinate" + EditNum $Blue_x_14, " Blue_x (Bits 9->2 at 1Fh)" , EHEX, + Help " Bits 9->2 of Blue color x coordinate" + EditNum $Blue_y_14, " Blue_y (Bits 9->2 at 20h)" , EHEX, + Help " Bits 9->2 of Blue color y coordinate" + EditNum $White_x_14, " White_x (Bits 9->2 at 21h)" , EHEX, + Help " Bits 9->2 of White color x coordinate" + EditNum $White_y_14, " White_y (Bits 9->2 at 22h)" , EHEX, + Help " Bits 9->2 of White color y coordinate" + + EndPage ; Chromaticity Control + +EndPage + +;============================================================================== +; Page - Panel #15 (1280x600) Flat Panel parameters +;------------------------------------------------------------------------------ + +Page "Panel #15 " + + TitleB "Common LFP Features" + + EditText $Panel_Name_15, "\tLFP Panel Name:", + Help "This feature defines the LVDS panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated. " + + Combo $Enable_Scaling_15, "\tScale to Target Resolution:", &No_Yes_List, + Help "Selecting this feature will make the graphics driver to enable Scaling feature by taking the Horizontal and Vertical resolution\r\n" + "from Target X-Res and Target Y-Res fields.\r\n" + + EditNum $Panel_Width_15, "\tTarget X-Res:", DEC, + Help "This value specifies the Target X-Resolution for this panel." + + EditNum $Panel_Height_15, "\tTarget Y-Res:", DEC, + Help "This value specifies the Target Y-Resolutoin for this panel." + + + + + Combo $DPS_Panel_Type_15, " \tDPS Panel Type:", &DPS_Panel_Type_List, + Help "This feature allows OEM to select the DPS Panel Type.\r\n " + "Intel SDRRS Technology is a feature of the Intel graphics driver\r\n" + "which reduces display power\r\n" + "SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n" + "rate will not adversely impact the user experience\r\n" + "Seamless:- Allows power savings when on battery mode and when a lower refresh\r\n" + "rate will not adversely impact the user experience.Implements seamless refresh\r\n" + "rate switching, which eliminates the screen blink that occurred\r\n" + "during the refresh rate transitions\r\n" + + EditNum $Seamless_DRRS_Min_RR_15, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, + Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n\n" + "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" + + Combo $Blt_Control_15, "\tBackLight Technology:", &Blt_Control_Type_List, + Help "This feature allows OEM to select the Backlight Technology.\r\n " + + Title " " + Link "LFP PnP ID Table" , "LFP PnP ID" + Link "DTD Timings Table" , "DTD Timings" + Link "Backlight Control Parameters" , "Backlight Control Parameters" + Link "Chromaticity Control" , "Chromaticity Control" + + #if ($Int_LFP1_Type == 0x1806) + TitleB "Integrated eDP Features" + +Combo $Enable_SSC15, " \teDP Spread Spectrum Clock:", &Disabled_Enabled_List, +Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " + + Combo $eDP_Panel_Color_Depth_15, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, + Help "This feature specifies the color depth of eDP panel used. " + + Combo $eDP_VSwingPreEmph_15, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, + Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " + "For CherryTrail, based on the selection respective table will be used.\r\n" + "Tables for CherryTrail:-\r\n" + "------------------------------------------------------------------------------------------------------\n" + "|Low Power VSwing Pre-Emphasis Setting Table |\n" + "-----------------------------------------------------------------------------------------------------|\n" + "| | Pre-Emphasis (db) |\n" + "| |------------------------------------------------------------------------------------------|\n" + "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" + "| Voltage |------------------------------------------------------------------------- ---------------|\n" + "| Swing | Level 0/200 | 200mV,0db | 200mV,3.5db | 200mV,6db | 200mV,9db |\n" + "| (mV) |------------------------------------------------------------------------------------------|\n" + "| | Level 1/250 | 250mV,0db | 250mV,3.5db | 250mV,6db | NA |\n" + "| |------------------------------------------------------------------------------------------|\n" + "| | Level 2/300 | 300mV,0db | 300mV,3.5d | NA | NA |\n" + "| |------------------------------------------------------------------------------------------|\n" + "| | Level 3/350 | 350 mv, 0db | NA | NA | NA |\n" + "-----------------------------------------------------------------------------------------------------\n\n" + + "-----------------------------------------------------------------------------------------------------\n" + "|Default VSwing Pre-Emphasis Setting Table |\n" + "---------------------------------------------------------------------------------------------------|\n" + "| | Pre-Emphasis (db) |\n" + "| |----------------------------------------------------------------------------------------|\n" + "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" + "| Voltage |----------------------------------------------------------------------------------------|\n" + "| Swing | Level 0/400 | 400mV,0db | 400mV,3.5db | 400mV,6db | 400mV,9db |\n" + "| (mV) |----------------------------------------------------------------------------------------|\n" + "| | Level 1/600 | 600mV,0db | 600mV,3.5db | 600mV,6db | NA |\n" + "| |----------------------------------------------------------------------------------------|\n" + "| | Level 2/800 | 800mV,0db | 800mV,3.5db | NA | NA |\n" + "| |----------------------------------------------------------------------------------------|\n" + "| | Level 3/1200| 1200mV, 0db | NA | NA | NA |\n" + "-----------------------------------------------------------------------------------------------------\n\n" + + + Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Power Sequencing" + Link "eDP Fast Link Training Configuration" , "eDP Fast Link Training Configuration" + + Page "eDP Panel Power Sequencing" + Link "Close Table", ".." + + Combo $eDP_T3_Optimization_15, "T3 optimization", &Disabled_Enabled_List, + Help "This feature enables or disables T3 optimization. \r\n" + "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" + "When disabled, VBIOS/Graphics driver will wait for T3 time before trying the first AUX transaction" + + EditNum $eDP_Vcc_To_Hpd_Delay_15, "LCDVCC to HPD high delay (T3):", DEC, + Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" + "Valid Range: 0 to 200msec\r\n" + + EditNum $eDP_DataOn_To_BkltEnable_Delay_15, "Valid video data to Backlight Enable delay (T8):", DEC, + Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" + "T8 is inclusive of T7.\r\n" + "Valid Range of T7: 0 to 50msec\r\n" + + EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_15, "PWM-On To Backlight Enable delay:", DEC, + Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" + "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" + "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" + + EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_15, "Backlight Disable to PWM-Off delay:", DEC, + Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" + "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" + "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" + + EditNum $eDP_BkltDisable_To_DataOff_Delay_15, "Backlight Disable to End of Valid video data delay (T9):", DEC, + Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" + + EditNum $eDP_DataOff_To_PowerOff_Delay_15, "End of Valid video data to Power-Off delay (T10):", DEC, + Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" + "Valid Range: 0 to 500 msec\r\n" + + EditNum $eDP_PowerCycle_Delay_15, "Power-off time (T12):", DEC, + Help "Using this field Power-off time can be specified in 100uS.\r\n" + + EndPage + + Page "eDP Fast Link Training Configuration" + + Link "Close Table" , ".." + Combo $Fast_Link_Training_Supported_15, " Is FastLinkTraining Feature Supported:", &No_Yes_List, + Help "This feature if set to Yes will enable " + "Fast Link Training for eDp, if Panel also supports it." + + Combo $eDP_Link_DataRate_15, " Data Rate:", &eDP_Link_DataRate_List, + Help "This feature allows for the selection of the " + "Data Rate for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + Combo $eDP_Link_LaneCount_15, " Lane Count:", &eDP_Link_LaneCount_List, + Help "This feature allows for the selection of the " + "Lane Count (Port Width) for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + Combo $eDP_Link_PreEmp_15, " Pre-Emphasis:", &eDP_Link_PreEmp_List, + Help "This feature allows for the selection of the " + "Pre-emphasis value for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" + "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" + "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" + "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" + "------------------------------------------------------------------------------------------------------------ \r\n" + + "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" + "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" + "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" + "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" + "------------------------------------------------------------------------------------------------------------ \r\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + Combo $eDP_Link_Vswing_15, " Voltage Swing:", &eDP_Link_VSwing_List, + Help "This feature allows for the selection of the " + "Voltage Swing value for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" + "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" + "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" + "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" + "------------------------------------------------------------------------------------------------------------ \r\n" + + "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" + "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" + "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" + "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" + "------------------------------------------------------------------------------------------------------------ \r\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + EndPage + #endif + + Page "DTD Timings" + + Link "Close Table" , ".." + + Table $DVO_Tbl_15 " DTD Timings Values", + Column "Timings" , 1 byte , EHEX, + Help "This feature allows for the definition of the DTD " + "timings parameters related to the LFP. The " + "table is the 18-byte DTD structure defined in the " + "VESA EDID version 1.x.\r\n" + "\r\n" + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" + "\tDB ?\t; Vertical Active in lines, LSB\r\n" + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Horizontal Image Size, LSB\r\n" + "\tDB ?\t; Vertical Image Size, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" + "\tDB 0\t; Horizontal Border in pixels\r\n" + "\tDB 0\t; Vertical Border in lines\r\n" + "\tDB ?\t; Flags:\r\n" + "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" + "\t \t; Bit 6-5: 00 = Reserved\r\n" + "\t \t; Bit 4-3: 11 = Digital Separate\r\n" + "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 0: 0 = Reserved" + + EndPage + + Page "LFP PnP ID" + + Link "Close Table" , ".." + + Table $LVDS_PnP_ID_15 " LFP PnP ID Values", + Column "PnP ID" , 1 byte , EHEX, + Help "This feature allows the 10 bytes of EDID Vendor / " + "Product ID starting at offset 08h to be used as a " + "PnP ID.\r\n" + "\r\n" + " Table Definition:\r\n" + " Word: ID Manufacturer Name\r\n" + " Word: ID Product Code\r\n" + " DWord: ID Serial Number\r\n" + " Byte: Week of Manufacture\r\n" + " Byte: Year of Manufacture" + + EndPage + + Page "Backlight Control Parameters" + + Link "Close Table" , ".." + + Combo $BLC_Inv_Type_15, " Inverter Type:", &Inv_Type_List, + Help "This feature allows for the selection of the " + "Backlight Inverter type that is to be used to " + "control the backlight brightness of the LFP. When " + "PWM is selected, the driver and VBIOS will control " + "the backlight brightness via the integrated PWM " + "solution for the applicable chipsets. When I2C is " + "selected, the driver and VBIOS will control the " + "backlight brightness via the I2C solution for the " + "applicable chipsets. When None/External is " + "selected, the system BIOS will control the backlight " + "brightness via the external solution." + + Combo $Lfp_Pwm_Source_Selection_15, " Pwm Source Selection:", &Edp_Pwm_Source_List, + Help "This field allows to select the Source of the PWM to be used " + "for the selected Local Flat Panel.\r\n" + "\r\n" + + Combo $BLC_Inv_Polarity_15, " Inverter Polarity:", &Inv_Polarity_List, + Help "This feature allows the backlight inverter polarity " + "to be specified.\r\n" + "\r\n" + "Normal means 0 value is minimum brightness.\r\n" + "Inverted means 0 value is maximum brightness." + + EditNum $BLC_Min_Brightness_15, " Minimum Brightness:", DEC, + Help "This feature allows defining the absolute minimum " + "backlight brightness setting. The graphics driver " + "will never decrease the backlight less than this " + "value. The value must be specified using normal " + "polarity semantics." + +EditNum $POST_BL_Brightness_15, " POST Backlight Intensity:", DEC, + Help "This feature is used to set default brightness value at POST." + "This is configurable field of 0-255. Value of 0 indicates 0 brightness, 255 indicates maximum brightness. " + + + EditNum $PWM_Frequency_15, " PWM Inverter Frequency (Hz):", DEC, + Help "This feature allows for the definition of the " + "frequency needed for PWM Inverter.\r\n" + "\r\n" + "Note: The frequency range, entered as a decimal " + "number, for the integrated PWM is 200Hz - 40KHz." + EndPage + + Page "Chromaticity Control" + Link "Close Table" , ".." + + Combo $Chromacity_Enable_15, "Chromaticity Control Feature", &Disabled_Enabled_List, + Help " This bit enables Chromaticity feature. \r\n" + " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" + " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" + " Please refer to section 3.7 of EDID Specification 1.4" + Combo $Override_EDID_Data_15, "Override the EDID values", &No_Yes_List, + Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" + EditNum $Red_Green_15, " Red_Green_bits (Bits 1&0 at 19h)" , EHEX, + Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" + EditNum $Blue_White_15, " Blue_White_bits (Bits 1&0 at 1Ah)" , EHEX, + Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" + EditNum $Red_x_15, " Red_x (Bits 9->2 at 1Bh)" , EHEX, + Help " Bits 9->2 of red color x coordinate" + EditNum $Red_y_15, " Red_y (Bits 9->2 at 1Ch)" , EHEX, + Help " Bits 9->2 of red color y coordinate" + EditNum $Green_x_15, " Green_x (Bits 9->2 at 1Dh)" , EHEX, + Help " Bits 9->2 of Green color x coordinate" + EditNum $Green_y_15, " Green_y (Bits 9->2 at 1Eh)" , EHEX, + Help " Bits 9->2 of Green color y coordinate" + EditNum $Blue_x_15, " Blue_x (Bits 9->2 at 1Fh)" , EHEX, + Help " Bits 9->2 of Blue color x coordinate" + EditNum $Blue_y_15, " Blue_y (Bits 9->2 at 20h)" , EHEX, + Help " Bits 9->2 of Blue color y coordinate" + EditNum $White_x_15, " White_x (Bits 9->2 at 21h)" , EHEX, + Help " Bits 9->2 of White color x coordinate" + EditNum $White_y_15, " White_y (Bits 9->2 at 22h)" , EHEX, + Help " Bits 9->2 of White color y coordinate" + + EndPage ; Chromaticity Control + +EndPage + +;============================================================================== +; Page - Panel #16 (Reserved) Flat Panel parameters +;------------------------------------------------------------------------------ + +Page "Panel #16 " + + TitleB "Common LFP Features" + + EditText $Panel_Name_16, "\tLFP Panel Name:", + Help "This feature defines the LVDS panel name, used by driver only. Panel name can be only of 13 characters maximum and rest of the characters will be truncated. " + + Combo $Enable_Scaling_16, "\tScale to Target Resolution:", &No_Yes_List, + Help "Selecting this feature will make the graphics driver to enable Scaling feature by taking the Horizontal and Vertical resolution\r\n" + "from Target X-Res and Target Y-Res fields.\r\n" + + EditNum $Panel_Width_16, "\tTarget X-Res:", DEC, + Help "This value specifies the Target X-Resolution for this panel." + + EditNum $Panel_Height_16, "\tTarget Y-Res:", DEC, + Help "This value specifies the Target Y-Resolutoin for this panel." + + + + + Combo $DPS_Panel_Type_16, " \tDPS Panel Type:", &DPS_Panel_Type_List, + Help "This feature allows OEM to select the DPS Panel Type.\r\n " + "Intel SDRRS Technology is a feature of the Intel graphics driver\r\n" + "which reduces display power\r\n" + "SDRRS:- Allows power savings when on battery mode and when a lower refresh\r\n" + "rate will not adversely impact the user experience\r\n" + "Seamless:- Allows power savings when on battery mode and when a lower refresh\r\n" + "rate will not adversely impact the user experience.Implements seamless refresh\r\n" + "rate switching, which eliminates the screen blink that occurred\r\n" + "during the refresh rate transitions\r\n" + + EditNum $Seamless_DRRS_Min_RR_16, "\tSeamless DRRS Minimum Refresh Rate (Hz):", DEC, + Help "Using this field the minimum Refresh Rate to be used for Seamless DRRS feature can be entered in Hertz.\r\n\n" + "Note: Graphics driver will use this field only when EDID support is disabled in VBT configuration.\r\n" + + Combo $Blt_Control_16, "\tBackLight Technology:", &Blt_Control_Type_List, + Help "This feature allows OEM to select the Backlight Technology.\r\n " + + Title " " + Link "LFP PnP ID Table" , "LFP PnP ID" + Link "DTD Timings Table" , "DTD Timings" + Link "Backlight Control Parameters" , "Backlight Control Parameters" + Link "Chromaticity Control" , "Chromaticity Control" + + #if ($Int_LFP1_Type == 0x1806) + TitleB "Integrated eDP Features" + +Combo $Enable_SSC16, " \teDP Spread Spectrum Clock:", &Disabled_Enabled_List, +Help "This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n " + + Combo $eDP_Panel_Color_Depth_16, "\tPanel Color Depth:", &eDP_Panel_Color_Depth_List, + Help "This feature specifies the color depth of eDP panel used. " + + Combo $eDP_VSwingPreEmph_16, "\tSelect VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List, + Help "This feature selects the VSwing Pre-Emphasis setting table to be used. " + "For CherryTrail, based on the selection respective table will be used.\r\n" + "Tables for CherryTrail:-\r\n" + "------------------------------------------------------------------------------------------------------\n" + "|Low Power VSwing Pre-Emphasis Setting Table |\n" + "-----------------------------------------------------------------------------------------------------|\n" + "| | Pre-Emphasis (db) |\n" + "| |------------------------------------------------------------------------------------------|\n" + "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" + "| Voltage |------------------------------------------------------------------------- ---------------|\n" + "| Swing | Level 0/200 | 200mV,0db | 200mV,3.5db | 200mV,6db | 200mV,9db |\n" + "| (mV) |------------------------------------------------------------------------------------------|\n" + "| | Level 1/250 | 250mV,0db | 250mV,3.5db | 250mV,6db | NA |\n" + "| |------------------------------------------------------------------------------------------|\n" + "| | Level 2/300 | 300mV,0db | 300mV,3.5d | NA | NA |\n" + "| |------------------------------------------------------------------------------------------|\n" + "| | Level 3/350 | 350 mv, 0db | NA | NA | NA |\n" + "-----------------------------------------------------------------------------------------------------\n\n" + + "-----------------------------------------------------------------------------------------------------\n" + "|Default VSwing Pre-Emphasis Setting Table |\n" + "---------------------------------------------------------------------------------------------------|\n" + "| | Pre-Emphasis (db) |\n" + "| |----------------------------------------------------------------------------------------|\n" + "| | DP Applet | Level 0/0 | Level 1/3.5 | Level 2/6 | Level 3/9 |\n" + "| Voltage |----------------------------------------------------------------------------------------|\n" + "| Swing | Level 0/400 | 400mV,0db | 400mV,3.5db | 400mV,6db | 400mV,9db |\n" + "| (mV) |----------------------------------------------------------------------------------------|\n" + "| | Level 1/600 | 600mV,0db | 600mV,3.5db | 600mV,6db | NA |\n" + "| |----------------------------------------------------------------------------------------|\n" + "| | Level 2/800 | 800mV,0db | 800mV,3.5db | NA | NA |\n" + "| |----------------------------------------------------------------------------------------|\n" + "| | Level 3/1200| 1200mV, 0db | NA | NA | NA |\n" + "-----------------------------------------------------------------------------------------------------\n\n" + + + Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Power Sequencing" + Link "eDP Fast Link Training Configuration" , "eDP Fast Link Training Configuration" + + Page "eDP Panel Power Sequencing" + Link "Close Table", ".." + + Combo $eDP_T3_Optimization_16, "T3 optimization", &Disabled_Enabled_List, + Help "This feature enables or disables T3 optimization. \r\n" + "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n" + "When disabled, VBIOS/Graphics driver will wait for T3 time before trying the first AUX transaction" + + EditNum $eDP_Vcc_To_Hpd_Delay_16, "LCDVCC to HPD high delay (T3):", DEC, + Help "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n" + "Valid Range: 0 to 200msec\r\n" + + EditNum $eDP_DataOn_To_BkltEnable_Delay_16, "Valid video data to Backlight Enable delay (T8):", DEC, + Help "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n" + "T8 is inclusive of T7.\r\n" + "Valid Range of T7: 0 to 50msec\r\n" + + EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_16, "PWM-On To Backlight Enable delay:", DEC, + Help "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n" + "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n" + "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n" + + EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_16, "Backlight Disable to PWM-Off delay:", DEC, + Help "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n" + "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n" + "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n" + + EditNum $eDP_BkltDisable_To_DataOff_Delay_16, "Backlight Disable to End of Valid video data delay (T9):", DEC, + Help "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n" + + EditNum $eDP_DataOff_To_PowerOff_Delay_16, "End of Valid video data to Power-Off delay (T10):", DEC, + Help "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n" + "Valid Range: 0 to 500 msec\r\n" + + EditNum $eDP_PowerCycle_Delay_16, "Power-off time (T12):", DEC, + Help "Using this field Power-off time can be specified in 100uS.\r\n" + + EndPage + + Page "eDP Fast Link Training Configuration" + + Link "Close Table" , ".." + Combo $Fast_Link_Training_Supported_16, " Is FastLinkTraining Feature Supported:", &No_Yes_List, + Help "This feature if set to Yes will enable " + "Fast Link Training for eDp, if Panel also supports it." + + Combo $eDP_Link_DataRate_16, " Data Rate:", &eDP_Link_DataRate_List, + Help "This feature allows for the selection of the " + "Data Rate for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + Combo $eDP_Link_LaneCount_16, " Lane Count:", &eDP_Link_LaneCount_List, + Help "This feature allows for the selection of the " + "Lane Count (Port Width) for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + Combo $eDP_Link_PreEmp_16, " Pre-Emphasis:", &eDP_Link_PreEmp_List, + Help "This feature allows for the selection of the " + "Pre-emphasis value for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" + "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" + "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" + "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" + "------------------------------------------------------------------------------------------------------------ \r\n" + + "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" + "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" + "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" + "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" + "------------------------------------------------------------------------------------------------------------ \r\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + Combo $eDP_Link_Vswing_16, " Voltage Swing:", &eDP_Link_VSwing_List, + Help "This feature allows for the selection of the " + "Voltage Swing value for the embedded DP link. It will be used if the " + "sink indicates that no aux handshake is required during link training." + + "\r\n\n\t\t Default Swing Setting Table \t\t\t\t \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9.5dB) | \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(400mV) | Supported | Supported | Supported | Supported | \r\n" + "| Level 1(600mV) | Supported | Supported | Supported | N/A | \r\n" + "| Level 2(800mV) | Supported | Supported | N/A | N/A | \r\n" + "| Level 3(1200mV) | Supported | N/A | N/A | N/A | \r\n" + "------------------------------------------------------------------------------------------------------------ \r\n" + + "\r\n\n\t\t Low Vswing Setting Table \t\t\t\t \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) | Level 3(9dB) | \r\n" + "---------------------------------------------------------------------------------------------------\r\n" + "| Level 0(200mV) | Supported | Supported | Supported | Supported | \r\n" + "| Level 1(250mV) | Supported | Supported | Supported | N/A | \r\n" + "| Level 2(300mV) | Supported | Supported | N/A | N/A | \r\n" + "| Level 3(350mV) | Supported | N/A | N/A | N/A | \r\n" + "------------------------------------------------------------------------------------------------------------ \r\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + EndPage + #endif + + Page "DTD Timings" + + Link "Close Table" , ".." + + Table $DVO_Tbl_16 " DTD Timings Values", + Column "Timings" , 1 byte , EHEX, + Help "This feature allows for the definition of the DTD " + "timings parameters related to the LFP. The " + "table is the 18-byte DTD structure defined in the " + "VESA EDID version 1.x.\r\n" + "\r\n" + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" + "\tDB ?\t; Vertical Active in lines, LSB\r\n" + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Horizontal Image Size, LSB\r\n" + "\tDB ?\t; Vertical Image Size, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" + "\tDB 0\t; Horizontal Border in pixels\r\n" + "\tDB 0\t; Vertical Border in lines\r\n" + "\tDB ?\t; Flags:\r\n" + "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" + "\t \t; Bit 6-5: 00 = Reserved\r\n" + "\t \t; Bit 4-3: 11 = Digital Separate\r\n" + "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 0: 0 = Reserved" + + EndPage + + Page "LFP PnP ID" + + Link "Close Table" , ".." + + Table $LVDS_PnP_ID_16 " LFP PnP ID Values", + Column "PnP ID" , 1 byte , EHEX, + Help "This feature allows the 10 bytes of EDID Vendor / " + "Product ID starting at offset 08h to be used as a " + "PnP ID.\r\n" + "\r\n" + " Table Definition:\r\n" + " Word: ID Manufacturer Name\r\n" + " Word: ID Product Code\r\n" + " DWord: ID Serial Number\r\n" + " Byte: Week of Manufacture\r\n" + " Byte: Year of Manufacture" + + EndPage + + Page "Backlight Control Parameters" + + Link "Close Table" , ".." + + Combo $BLC_Inv_Type_16, " Inverter Type:", &Inv_Type_List, + Help "This feature allows for the selection of the " + "Backlight Inverter type that is to be used to " + "control the backlight brightness of the LFP. When " + "PWM is selected, the driver and VBIOS will control " + "the backlight brightness via the integrated PWM " + "solution for the applicable chipsets. When I2C is " + "selected, the driver and VBIOS will control the " + "backlight brightness via the I2C solution for the " + "applicable chipsets. When None/External is " + "selected, the system BIOS will control the backlight " + "brightness via the external solution." + + Combo $Lfp_Pwm_Source_Selection_16, " Pwm Source Selection:", &Edp_Pwm_Source_List, + Help "This field allows to select the Source of the PWM to be used " + "for the selected Local Flat Panel.\r\n" + "\r\n" + + Combo $BLC_Inv_Polarity_16, " Inverter Polarity:", &Inv_Polarity_List, + Help "This feature allows the backlight inverter polarity " + "to be specified.\r\n" + "\r\n" + "Normal means 0 value is minimum brightness.\r\n" + "Inverted means 0 value is maximum brightness." + + EditNum $BLC_Min_Brightness_16, " Minimum Brightness:", DEC, + Help "This feature allows defining the absolute minimum " + "backlight brightness setting. The graphics driver " + "will never decrease the backlight less than this " + "value. The value must be specified using normal " + "polarity semantics." + +EditNum $POST_BL_Brightness_16, " POST Backlight Intensity:", DEC, + Help "This feature is used to set default brightness value at POST." + "This is configurable field of 0-255. Value of 0 indicates 0 brightness, 255 indicates maximum brightness. " + + EditNum $PWM_Frequency_16, " PWM Inverter Frequency (Hz):", DEC, + Help "This feature allows for the definition of the " + "frequency needed for PWM Inverter.\r\n" + "\r\n" + "Note: The frequency range, entered as a decimal " + "number, for the integrated PWM is 200Hz - 40KHz." + EndPage + + Page "Chromaticity Control" + Link "Close Table" , ".." + + Combo $Chromacity_Enable_16, "Chromaticity Control Feature", &Disabled_Enabled_List, + Help " This bit enables Chromaticity feature. \r\n" + " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n" + " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n" + " Please refer to section 3.7 of EDID Specification 1.4" + Combo $Override_EDID_Data_16, "Override the EDID values", &No_Yes_List, + Help "This option when enabled along with Chromaticity feature will override EDID values through following VBT data" + EditNum $Red_Green_16, " Red_Green_bits (Bits 1&0 at 19h)" , EHEX, + Help " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" + EditNum $Blue_White_16, " Blue_White_bits (Bits 1&0 at 1Ah)" , EHEX, + Help " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0" + EditNum $Red_x_16, " Red_x (Bits 9->2 at 1Bh)" , EHEX, + Help " Bits 9->2 of red color x coordinate" + EditNum $Red_y_16, " Red_y (Bits 9->2 at 1Ch)" , EHEX, + Help " Bits 9->2 of red color y coordinate" + EditNum $Green_x_16, " Green_x (Bits 9->2 at 1Dh)" , EHEX, + Help " Bits 9->2 of Green color x coordinate" + EditNum $Green_y_16, " Green_y (Bits 9->2 at 1Eh)" , EHEX, + Help " Bits 9->2 of Green color y coordinate" + EditNum $Blue_x_16, " Blue_x (Bits 9->2 at 1F)" , EHEX, + Help " Bits 9->2 of Blue color x coordinate" + EditNum $Blue_y_16, " Blue_y (Bits 9->2 at 20h)" , EHEX, + Help " Bits 9->2 of Blue color y coordinate" + EditNum $White_x_16, " White_x (Bits 9->2 at 21h)" , EHEX, + Help " Bits 9->2 of White color x coordinate" + EditNum $White_y_16, " White_y (Bits 9->2 at 22h)h" , EHEX, + Help " Bits 9->2 of White color y coordinate" + + EndPage ; Chromaticity Control + + +EndPage +#endif + +EndPage ; "Integrated LFP Features" + + + +;============================================================================== +; Page - Display Device Toggle Lists +;------------------------------------------------------------------------------ + +Page "Display Device Toggle Lists" + + Link "Toggle/Capabilities List 1" , "Display Toggle List 1" + Link "Toggle/Capabilities List 2" , "Display Toggle List 2" + Link "Toggle/Capabilities List 3" , "Display Toggle List 3" + Link "Toggle/Capabilities List 4" , "Display Toggle List 4" + + Page "Display Toggle List 1" + + Link "Close Table" , ".." + + Table $Toggle_List1 "Display Toggle List 1", + Column "Display Select", 2 bytes, EHEX, + Help "These toggle lists are used by the video BIOS and " + "Graphics drivers to help support the system BIOS with " + "switch display device Hot Keys. The basic algorithm " + "in the current display is found on the list and the " + "next settable display combination is set. If no " + "settable display combinations are found the function " + "returns fail.\r\n" + "\r\n" + "Four lists are given to allow for multiple " + "Hot Keys or creative solutions.\r\n" + "\r\n" + "\t15\t14\t13\t12\t11\t10\t9\t8\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n" + "\tRsvd\tEFP3.3\tEFP2.3\tEFP1.3\tRsvd\tEFP3.2\tEFP2.2\tEFP1.2\tRsvd\tEFP2\tEFP3\tRsvd\tLFP\tEFP\tReserved\tReserved\r\n" + "\r\n" + "EFPx.x nomenclature\r\n" + "EFP1.2 - 2nd daisy chained DP port on EFP1 Port\r\n" + "EFP2.3 - 3rd daisy chained DP port on EFP2 Port\r\n" + "EFP3.2 - 2nd daisy chained DP port on EFP3 Port\r\n" + "Examples:\r\n" + "\t Display Config\r\n" + "\t00000000 00001100b ; Toggle display to EFP & LFP combination\r\n" + "\t00000100 00100100b ; Toggle display to EFP3 and EFP combination." + + EndPage + + Page "Display Toggle List 2" + + Link "Close Table" , ".." + + Table $Toggle_List2 "Display Toggle List 2", + Column "Display Select", 2 bytes, EHEX, + Help "These toggle lists are used by the video BIOS and " + "Graphics drivers to help support the system BIOS with " + "switch display device Hot Keys. The basic algorithm " + "in the current display is found on the list and the " + "next settable display combination is set. If no " + "settable display combinations are found the function " + "returns fail.\r\n" + "\r\n" + "Four lists are given to allow for multiple " + "Hot Keys or creative solutions.\r\n" + "\r\n" + "\t15\t14\t13\t12\t11\t10\t9\t8\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n" + "\tRsvd\tEFP3.3\tEFP2.3\tEFP1.3\tRsvd\tEFP3.2\tEFP2.2\tEFP1.2\tRsvd\tEFP2\tEFP3\tRsvd\tLFP\tEFP\tReserved\tReserved\r\n" + "\r\n" + "EFPx.x nomenclature\r\n" + "EFP1.2 - 2nd daisy chained DP port on EFP1 Port\r\n" + "EFP2.3 - 3rd daisy chained DP port on EFP2 Port\r\n" + "EFP3.2 - 2nd daisy chained DP port on EFP3 Port\r\n" + "Examples:\r\n" + "\t Display Config\r\n" + "\t00000000 00001100b ; Toggle display to EFP & LFP combination\r\n" + "\t00000100 00100100b ; Toggle display to EFP3 and EFP combination." + + EndPage + + Page "Display Toggle List 3" + + Link "Close Table" , ".." + + Table $Toggle_List3 "Display Toggle List 3", + Column "Display Select", 2 bytes, EHEX, + Help "These toggle lists are used by the video BIOS and " + "Graphics drivers to help support the system BIOS with " + "switch display device Hot Keys. The basic algorithm " + "in the current display is found on the list and the " + "next settable display combination is set. If no " + "settable display combinations are found the function " + "returns fail.\r\n" + "\r\n" + "Four lists are given to allow for multiple " + "Hot Keys or creative solutions.\r\n" + "\r\n" + "\t15\t14\t13\t12\t11\t10\t9\t8\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n" + "\tRsvd\tEFP3.3\tEFP2.3\tEFP1.3\tRsvd\tEFP3.2\tEFP2.2\tEFP1.2\tRsvd\tEFP2\tEFP3\tRsvd\tLFP\tEFP\tReserved\tReserved\r\n" + "\r\n" + "EFPx.x nomenclature\r\n" + "EFP1.2 - 2nd daisy chained DP port on EFP1 Port\r\n" + "EFP2.3 - 3rd daisy chained DP port on EFP2 Port\r\n" + "EFP3.2 - 2nd daisy chained DP port on EFP3 Port\r\n" + "Examples:\r\n" + "\t Display Config\r\n" + "\t00000000 00001100b ; Toggle display to EFP & LFP combination\r\n" + "\t00000100 00100100b ; Toggle display to EFP3 and EFP combination." + + EndPage + + Page "Display Toggle List 4" + + Link "Close Table" , ".." + + Table $Toggle_List4 "Display Toggle List 4", + Column "Display Select", 2 bytes, EHEX, + Help "These toggle lists are used by the video BIOS and " + "Graphics drivers to help support the system BIOS with " + "switch display device Hot Keys. The basic algorithm " + "in the current display is found on the list and the " + "next settable display combination is set. If no " + "settable display combinations are found the function " + "returns fail.\r\n" + "\r\n" + "Four lists are given to allow for multiple " + "Hot Keys or creative solutions.\r\n" + "\r\n" + "\t15\t14\t13\t12\t11\t10\t9\t8\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n" + "\tRsvd\tEFP3.3\tEFP2.3\tEFP1.3\tRsvd\tEFP3.2\tEFP2.2\tEFP1.2\tRsvd\tEFP2\tEFP3\tRsvd\tLFP\tEFP\tReserved\tReserved\r\n" + "\r\n" + "EFPx.x nomenclature\r\n" + "EFP1.2 - 2nd daisy chained DP port on EFP1 Port\r\n" + "EFP2.3 - 3rd daisy chained DP port on EFP2 Port\r\n" + "EFP3.2 - 2nd daisy chained DP port on EFP3 Port\r\n" + "Examples:\r\n" + "\t Display Config\r\n" + "\t00000000 00001100b ; Toggle display to EFP & LFP combination\r\n" + "\t00000100 00100100b ; Toggle display to EFP3 and EFP combination." + EndPage + +EndPage + +;============================================================================== +; Page - Modes Removal Table +;------------------------------------------------------------------------------ + +Page "Modes Removal Table" + + Table $Mode_Rem_Table "Modes Removal Table", + Column "X-Resolution", 2 bytes, DEC + Column "Y-Resolution", 2 bytes, DEC + Column "BPP", 1 byte, DEC + Column "Refresh Rate", 2 bytes, EHEX + Column "Removal Flags", 1 byte, EHEX + Column "Panel Type", 2 bytes, EHEX, + Help "This feature allows removing support for selected modes " + "resolutions.\r\n" + "\r\n" + "X-Resolution, Y-Resolution, and BPP in Decimal or " + "Hexadecimal (0FFFFh or 0FFh means disable all).\r\n" + "\r\n" + "Refresh Rate bitmap selection (0 = Do not remove, 1 = " + "Remove):\r\n" + "\r\n" + "\tBit 15-9 8 7 6 5 4 3 2 1 0 \r\n" + "\tRRate(Hz) Reserved 120 100 85 75 72 70 60 56 43i \r\n" + "\r\n" + "Removal Flags bitmap selection (0 = Do not remove, 1 = " + "Remove):\r\n" + "\r\n" + "\tBit 7 6 5 4 3 2 1 0 \r\n" + "\tComponent Rsvd Rsvd LFP EFP Rsvd CRT Driver VBIOS \r\n" + "\r\n" + "\tNote: 1) In order to remove mode from both Windows and DOS, " + "both Bit 1 and Bit 0 must be set to 1.\r\n" + "\r\n" + "(Mobile only) Panel Type bitmap selection (0 = Do not " + "remove, 1 = Remove if panel is active):/r/n" + "\r\n" + "\tBit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 \r\n" + "\tType 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 \r\n" + "\r\n" + "\tNote: Default is to remove a mode resolution from all " + "panel types." +EndPage + + +;============================================================================== +; Page - Display Configuration Removal Table +;------------------------------------------------------------------------------ + +Page "Display Configuration Removal Table" + + Table $Dev_Removed_Table " Display Device Configuration Removal Table", + Column "Pipe B" , 1 byte , BIN + Column "Pipe A" , 1 byte , BIN, + + Help "This feature allows blocking selected display configurations " + "by the video BIOS and driver.\r\n" + "\r\n" + "Display Devices are specified in the following bit patterns " + "(pipe A and B use the same bit pattern):\r\n" + "\r\n" + "\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n" + "\tLFP2\tEFP2\tRsvd\tRsvd\tLFP\tEFP\tRsvd\tCRT\r\n" + "\r\n" + "Examples:\r\n" + "\tPipe B Pipe A\r\n" + "\t00000000b, 00000101b ; EFP & CRT on Pipe A\r\n" + "\t00001100b, 00000001b ; EFP & LFP on Pipe B and CRT on " + "Pipe A" +EndPage + + +;============================================================================== +; Page - OEM Customizable Mode 2.0 +;------------------------------------------------------------------------------ + +Page "OEM Customizable Modes 2.0" + + Link "OEM Mode 1 Configuration", "OEM Mode #1" + Link "OEM Mode 2 Configuration", "OEM Mode #2" + Link "OEM Mode 3 Configuration", "OEM Mode #3" + Link "OEM Mode 4 Configuration", "OEM Mode #4" + Link "OEM Mode 5 Configuration", "OEM Mode #5" + Link "OEM Mode 6 Configuration", "OEM Mode #6" + + Page "OEM Mode #1" + + Link "Close Table" , ".." + + Title " 8 bpp = VGA mode 60h / VESA mode 160h" + Title " 16 bpp = VGA mode 61h / VESA mode 161h" + Title " 32 bpp = VGA mode 62h / VESA mode 162h" + + EditNum $OEM_Mode_Flags1, "Support Flags:", BIN, + Help "Support flags:" + "(0 = Disabled, 1 = Enabled)" + "\r\n\r\n" + "\tBit 7" + "\tBit 6" + "\tBit 5" + "\tBit 4" + "\tBit 3" + "\tBit 2" + "\tBit 1" + "\tBit 0" + "\r\n" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tDriver" + "\tVBIOS" + "\r\n" + + EditNum $OEM_Display_Flags1, "Display Flags:", BIN, + Help "Display Flags:" + "(0 = Disabled, 1 = Enabled)" + "\r\n\r\n" + "\tBit 7" + "\tBit 6" + "\tBit 5" + "\tBit 4" + "\tBit 3" + "\tBit 2" + "\tBit 1" + "\tBit 0" + "\r\n" + "\tLFP2" + "\tEFP2" + "\tTV2" + "\tCRT2" + "\tLFP" + "\tEFP" + "\tTV" + "\tCRT" + "\r\n" + + Title "Mode Characteristics" + EditNum $OEM_Mode_X1, " X Resolution:", DEC, + Help "X Resolution in pixels (decimal)." + + EditNum $OEM_Mode_Y1, " Y Resolution:", DEC, + Help "Y Resolution in pixels (decimal)." + + EditNum $OEM_Mode_Color1, " Color Depth:", BIN, + Help "Color Depth, bits can be set simultaneously (binary)." + "\r\n\r\n" + "\tBit 7" + "\tBit 6" + "\tBit 5" + "\tBit 4" + "\tBit 3" + "\tBit 2" + "\tBit 1" + "\tBit 0" + "\r\n" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\t32 BPP" + "\t16 BPP" + "\t8 BPP" + "\r\n" + + EditNum $OEM_Mode_RRate1, " Refresh Rate:", DEC, + Help "Refresh rate for OEM customizable mode (decimal)." + Link "18 Bytes DTD" , "DTD" + + Page "DTD" + + Link "Close Table" , ".." + + Table $OEM_Mode_DTD1 " Detailed Timings Descriptor", + Column "Timings" , 1 byte , EHEX, + Help "This table is the 18-byte DTD(Detailed Timings" + " Descriptor) structure defined in the VESA" + " EDID version 1.x.\r\n" + "\r\n" + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" + "\tDB ?\t; Vertical Active in lines, LSB\r\n" + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Horizontal Image Size, LSB\r\n" + "\tDB ?\t; Vertical Image Size, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" + "\tDB 0\t; Horizontal Border in pixels\r\n" + "\tDB 0\t; Vertical Border in lines\r\n" + "\tDB ?\t; Flags:\r\n" + "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" + "\t \t; Bit 6-5: 00 = Reserved\r\n" + "\t \t; Bit 4-3: 11 = Digital Separate\r\n" + "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 0: 0 = Reserved" + EndPage + EndPage + + Page "OEM Mode #2" + + Link "Close Table" , ".." + + Title " 8 bpp = VGA mode 63h / VESA mode 163h" + Title " 16 bpp = VGA mode 64h / VESA mode 164h" + Title " 32 bpp = VGA mode 65h / VESA mode 165h" + + EditNum $OEM_Mode_Flags2, "Support Flags:", BIN, + Help "Support flags:" + "(0 = Disabled, 1 = Enabled)" + "\r\n\r\n" + "\tBit 7" + "\tBit 6" + "\tBit 5" + "\tBit 4" + "\tBit 3" + "\tBit 2" + "\tBit 1" + "\tBit 0" + "\r\n" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tDriver" + "\tVBIOS" + "\r\n" + + EditNum $OEM_Display_Flags2, "Display Flags:", BIN, + Help "Display Flags:" + "(0 = Disabled, 1 = Enabled)" + "\r\n\r\n" + "\tBit 7" + "\tBit 6" + "\tBit 5" + "\tBit 4" + "\tBit 3" + "\tBit 2" + "\tBit 1" + "\tBit 0" + "\r\n" + "\tLFP2" + "\tEFP2" + "\tTV2" + "\tCRT2" + "\tLFP" + "\tEFP" + "\tTV" + "\tCRT" + "\r\n" + + Title "Mode Characteristics" + + EditNum $OEM_Mode_X2, " X Resolution:", DEC, + Help "X Resolution in pixels (decimal)." + + EditNum $OEM_Mode_Y2, " Y Resolution:", DEC, + Help "Y Resolution in pixels (decimal)." + + EditNum $OEM_Mode_Color2, " Color Depth:", BIN, + Help "Color Depth, bits can be set simultaneously (binary)." + "\r\n\r\n" + "\tBit 7" + "\tBit 6" + "\tBit 5" + "\tBit 4" + "\tBit 3" + "\tBit 2" + "\tBit 1" + "\tBit 0" + "\r\n" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\t32 BPP" + "\t16 BPP" + "\t8 BPP" + "\r\n" + + EditNum $OEM_Mode_RRate2, " Refresh Rate:", DEC, + Help "Refresh rate for OEM customizable mode (decimal)." + + Link "18 Bytes DTD" , "DTD" + + Page "DTD" + + Link "Close Table" , ".." + + Table $OEM_Mode_DTD2 " Detailed Timings Descriptor", + Column "Timings" , 1 byte , EHEX, + Help "This table is the 18-byte DTD(Detailed Timings" + " Descriptor) structure defined in the VESA" + " EDID version 1.x.\r\n" + "\r\n" + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" + "\tDB ?\t; Vertical Active in lines, LSB\r\n" + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Horizontal Image Size, LSB\r\n" + "\tDB ?\t; Vertical Image Size, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" + "\tDB 0\t; Horizontal Border in pixels\r\n" + "\tDB 0\t; Vertical Border in lines\r\n" + "\tDB ?\t; Flags:\r\n" + "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" + "\t \t; Bit 6-5: 00 = Reserved\r\n" + "\t \t; Bit 4-3: 11 = Digital Separate\r\n" + "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 0: 0 = Reserved" + EndPage + EndPage + + Page "OEM Mode #3" + + Link "Close Table" , ".." + + Title " 8 bpp = VGA mode 66h / VESA mode 166h" + Title " 16 bpp = VGA mode 67h / VESA mode 167h" + Title " 32 bpp = VGA mode 68h / VESA mode 168h" + + EditNum $OEM_Mode_Flags3, "Support Flags:", BIN, + Help "Support flags:" + "(0 = Disabled, 1 = Enabled)" + "\r\n\r\n" + "\tBit 7" + "\tBit 6" + "\tBit 5" + "\tBit 4" + "\tBit 3" + "\tBit 2" + "\tBit 1" + "\tBit 0" + "\r\n" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tDriver" + "\tVBIOS" + "\r\n" + + EditNum $OEM_Display_Flags3, "Display Flags:", BIN, + Help "Display Flags:" + "(0 = Disabled, 1 = Enabled)" + "\r\n\r\n" + "\tBit 7" + "\tBit 6" + "\tBit 5" + "\tBit 4" + "\tBit 3" + "\tBit 2" + "\tBit 1" + "\tBit 0" + "\r\n" + "\tLFP2" + "\tEFP2" + "\tTV2" + "\tCRT2" + "\tLFP" + "\tEFP" + "\tTV" + "\tCRT" + "\r\n" + + Title "Mode Characteristics" + + EditNum $OEM_Mode_X3, " X Resolution:", DEC, + Help "X Resolution in pixels (decimal)." + + EditNum $OEM_Mode_Y3, " Y Resolution:", DEC, + Help "Y Resolution in pixels (decimal)." + + EditNum $OEM_Mode_Color3, " Color Depth:", BIN, + Help "Color Depth, bits can be set simultaneously (binary)." + "\r\n\r\n" + "\tBit 7" + "\tBit 6" + "\tBit 5" + "\tBit 4" + "\tBit 3" + "\tBit 2" + "\tBit 1" + "\tBit 0" + "\r\n" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\t32 BPP" + "\t16 BPP" + "\t8 BPP" + "\r\n" + + EditNum $OEM_Mode_RRate3, " Refresh Rate:", DEC, + Help "Refresh rate for OEM customizable mode (decimal)." + + Link "18 Bytes DTD" , "DTD" + + Page "DTD" + + Link "Close Table" , ".." + + Table $OEM_Mode_DTD3 " Detailed Timings Descriptor", + Column "Timings" , 1 byte , EHEX, + Help "This table is the 18-byte DTD(Detailed Timings" + " Descriptor) structure defined in the VESA" + " EDID version 1.x.\r\n" + "\r\n" + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" + "\tDB ?\t; Vertical Active in lines, LSB\r\n" + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Horizontal Image Size, LSB\r\n" + "\tDB ?\t; Vertical Image Size, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" + "\tDB 0\t; Horizontal Border in pixels\r\n" + "\tDB 0\t; Vertical Border in lines\r\n" + "\tDB ?\t; Flags:\r\n" + "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" + "\t \t; Bit 6-5: 00 = Reserved\r\n" + "\t \t; Bit 4-3: 11 = Digital Separate\r\n" + "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 0: 0 = Reserved" + EndPage + EndPage + + Page "OEM Mode #4" + + Link "Close Table" , ".." + + Title " 8 bpp = VGA mode 69h / VESA mode 169h" + Title " 16 bpp = VGA mode 6Ah / VESA mode 16Ah" + Title " 32 bpp = VGA mode 6Bh / VESA mode 16Bh" + + EditNum $OEM_Mode_Flags4, "Support Flags:", BIN, + Help "Support flags:" + "(0 = Disabled, 1 = Enabled)" + "\r\n\r\n" + "\tBit 7" + "\tBit 6" + "\tBit 5" + "\tBit 4" + "\tBit 3" + "\tBit 2" + "\tBit 1" + "\tBit 0" + "\r\n" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tDriver" + "\tVBIOS" + "\r\n" + + EditNum $OEM_Display_Flags4, "Display Flags:", BIN, + Help "Display Flags:" + "(0 = Disabled, 1 = Enabled)" + "\r\n\r\n" + "\tBit 7" + "\tBit 6" + "\tBit 5" + "\tBit 4" + "\tBit 3" + "\tBit 2" + "\tBit 1" + "\tBit 0" + "\r\n" + "\tLFP2" + "\tEFP2" + "\tTV2" + "\tCRT2" + "\tLFP" + "\tEFP" + "\tTV" + "\tCRT" + "\r\n" + + Title "Mode Characteristics" + + EditNum $OEM_Mode_X4, " X Resolution:", DEC, + Help "X Resolution in pixels (decimal)." + + EditNum $OEM_Mode_Y4, " Y Resolution:", DEC, + Help "Y Resolution in pixels (decimal)." + + EditNum $OEM_Mode_Color4, " Color Depth:", BIN, + Help "Color Depth, bits can be set simultaneously (binary)." + "\r\n\r\n" + "\tBit 7" + "\tBit 6" + "\tBit 5" + "\tBit 4" + "\tBit 3" + "\tBit 2" + "\tBit 1" + "\tBit 0" + "\r\n" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\t32 BPP" + "\t16 BPP" + "\t8 BPP" + "\r\n" + + EditNum $OEM_Mode_RRate4, " Refresh Rate:", DEC, + Help "Refresh rate for OEM customizable mode (decimal)." + + Link "18 Bytes DTD" , "DTD" + + Page "DTD" + + Link "Close Table" , ".." + + Table $OEM_Mode_DTD4 " Detailed Timings Descriptor", + Column "Timings" , 1 byte , EHEX, + Help "This table is the 18-byte DTD(Detailed Timings" + " Descriptor) structure defined in the VESA" + " EDID version 1.x.\r\n" + "\r\n" + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" + "\tDB ?\t; Vertical Active in lines, LSB\r\n" + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Horizontal Image Size, LSB\r\n" + "\tDB ?\t; Vertical Image Size, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" + "\tDB 0\t; Horizontal Border in pixels\r\n" + "\tDB 0\t; Vertical Border in lines\r\n" + "\tDB ?\t; Flags:\r\n" + "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" + "\t \t; Bit 6-5: 00 = Reserved\r\n" + "\t \t; Bit 4-3: 11 = Digital Separate\r\n" + "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 0: 0 = Reserved" + EndPage + EndPage + + Page "OEM Mode #5" + + Link "Close Table" , ".." + + Title " 8 bpp = VGA mode 6Ch / VESA mode 16Ch" + Title " 16 bpp = VGA mode 6Dh / VESA mode 16Dh" + Title " 32 bpp = VGA mode 6Eh / VESA mode 16Eh" + + EditNum $OEM_Mode_Flags5, "Support Flags:", BIN, + Help "Support flags:" + "(0 = Disabled, 1 = Enabled)" + "\r\n\r\n" + "\tBit 7" + "\tBit 6" + "\tBit 5" + "\tBit 4" + "\tBit 3" + "\tBit 2" + "\tBit 1" + "\tBit 0" + "\r\n" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tDriver" + "\tVBIOS" + "\r\n" + + EditNum $OEM_Display_Flags5, "Display Flags:", BIN, + Help "Display Flags:" + "(0 = Disabled, 1 = Enabled)" + "\r\n\r\n" + "\tBit 7" + "\tBit 6" + "\tBit 5" + "\tBit 4" + "\tBit 3" + "\tBit 2" + "\tBit 1" + "\tBit 0" + "\r\n" + "\tLFP2" + "\tEFP2" + "\tTV2" + "\tCRT2" + "\tLFP" + "\tEFP" + "\tTV" + "\tCRT" + "\r\n" + + Title "Mode Characteristics" + + EditNum $OEM_Mode_X5, " X Resolution:", DEC, + Help "X Resolution in pixels (decimal)." + + EditNum $OEM_Mode_Y5, " Y Resolution:", DEC, + Help "Y Resolution in pixels (decimal)." + + EditNum $OEM_Mode_Color5, " Color Depth:", BIN, + Help "Color Depth, bits can be set simultaneously (binary)." + "\r\n\r\n" + "\tBit 7" + "\tBit 6" + "\tBit 5" + "\tBit 4" + "\tBit 3" + "\tBit 2" + "\tBit 1" + "\tBit 0" + "\r\n" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\t32 BPP" + "\t16 BPP" + "\t8 BPP" + "\r\n" + + EditNum $OEM_Mode_RRate5, " Refresh Rate:", DEC, + Help "Refresh rate for OEM customizable mode (decimal)." + + Link "18 Bytes DTD" , "DTD" + + Page "DTD" + + Link "Close Table" , ".." + + Table $OEM_Mode_DTD5 " Detailed Timings Descriptor", + Column "Timings" , 1 byte , EHEX, + Help "This table is the 18-byte DTD(Detailed Timings" + " Descriptor) structure defined in the VESA" + " EDID version 1.x.\r\n" + "\r\n" + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" + "\tDB ?\t; Vertical Active in lines, LSB\r\n" + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Horizontal Image Size, LSB\r\n" + "\tDB ?\t; Vertical Image Size, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" + "\tDB 0\t; Horizontal Border in pixels\r\n" + "\tDB 0\t; Vertical Border in lines\r\n" + "\tDB ?\t; Flags:\r\n" + "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" + "\t \t; Bit 6-5: 00 = Reserved\r\n" + "\t \t; Bit 4-3: 11 = Digital Separate\r\n" + "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 0: 0 = Reserved" + EndPage + EndPage + + Page "OEM Mode #6" + + Link "Close Table" , ".." + + Title " 8 bpp = VGA mode 6Fh / VESA mode 16Fh" + Title " 16 bpp = VGA mode 70h / VESA mode 170h" + Title " 32 bpp = VGA mode 71h / VESA mode 171h" + + EditNum $OEM_Mode_Flags6, "Support Flags:", BIN, + Help "Support flags:" + "(0 = Disabled, 1 = Enabled)" + "\r\n\r\n" + "\tBit 7" + "\tBit 6" + "\tBit 5" + "\tBit 4" + "\tBit 3" + "\tBit 2" + "\tBit 1" + "\tBit 0" + "\r\n" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tDriver" + "\tVBIOS" + "\r\n" + + EditNum $OEM_Display_Flags6, "Display Flags:", BIN, + Help "Display Flags:" + "(0 = Disabled, 1 = Enabled)" + "\r\n\r\n" + "\tBit 7" + "\tBit 6" + "\tBit 5" + "\tBit 4" + "\tBit 3" + "\tBit 2" + "\tBit 1" + "\tBit 0" + "\r\n" + "\tLFP2" + "\tEFP2" + "\tTV2" + "\tCRT2" + "\tLFP" + "\tEFP" + "\tTV" + "\tCRT" + "\r\n" + + Title "Mode Characteristics" + + EditNum $OEM_Mode_X6, " X Resolution:", DEC, + Help "X Resolution in pixels (decimal)." + + EditNum $OEM_Mode_Y6, " Y Resolution:", DEC, + Help "Y Resolution in pixels (decimal)." + + EditNum $OEM_Mode_Color6, " Color Depth:", BIN, + Help "Color Depth, bits can be set simultaneously (binary)." + "\r\n\r\n" + "\tBit 7" + "\tBit 6" + "\tBit 5" + "\tBit 4" + "\tBit 3" + "\tBit 2" + "\tBit 1" + "\tBit 0" + "\r\n" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\t32 BPP" + "\t16 BPP" + "\t8 BPP" + "\r\n" + + EditNum $OEM_Mode_RRate6, " Refresh Rate:", DEC, + Help "Refresh rate for OEM customizable mode (decimal)." + + Link "18 Bytes DTD" , "DTD" + + Page "DTD" + + Link "Close Table" , ".." + + Table $OEM_Mode_DTD6 " Detailed Timings Descriptor", + Column "Timings" , 1 byte , EHEX, + Help "This table is the 18-byte DTD(Detailed Timings" + " Descriptor) structure defined in the VESA" + " EDID version 1.x.\r\n" + "\r\n" + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" + "\tDB ?\t; Vertical Active in lines, LSB\r\n" + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\n" + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Horizontal Image Size, LSB\r\n" + "\tDB ?\t; Vertical Image Size, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" + "\tDB 0\t; Horizontal Border in pixels\r\n" + "\tDB 0\t; Vertical Border in lines\r\n" + "\tDB ?\t; Flags:\r\n" + "\t \t; Bit 7: 0 = Non-interlaced, 1 = Interlaced\r\n" + "\t \t; Bit 6-5: 00 = Reserved\r\n" + "\t \t; Bit 4-3: 11 = Digital Separate\r\n" + "\t \t; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)\r\n" + "\t \t; Bit 0: 0 = Reserved" + EndPage + EndPage +EndPage + + +;============================================================================ +; End of File +;------------------------------------------------------------------------------ +