mirror of https://review.coreboot.org/fsp.git
Ice Lake FSP 8.0.4B.40
This commit is contained in:
Nate DeSimone
parent
b4cd6daaf0
commit
0afb6b6130
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## @file
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# FSP description for DynamicEx PCDs.
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#
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# @copyright
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# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
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#
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# SPDX-License-Identifier: BSD-2-Clause-Patent
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#
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# @par Specification
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##
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## Specifies max supported number of Logical Processors.
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# @Prompt Configure max supported number of Logical Processorss
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gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|16
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gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress |0xC0000000
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gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength |0x10000000
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## Specifies the base address of the first microcode Patch in the microcode Region.
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# @Prompt Microcode Region base address.
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gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0x0
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## Specifies the size of the microcode Region.
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# @Prompt Microcode Region size.
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gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x0
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## Specifies the AP wait loop state during POST phase.
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# The value is defined as below.
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# 1: Place AP in the Hlt-Loop state.
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# 2: Place AP in the Mwait-Loop state.
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# 3: Place AP in the Run-Loop state.
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# @Prompt The AP wait loop state.
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gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|2
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## Specifies the AP target C-state for Mwait during POST phase.
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# The default value 0 means C1 state.
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# The value is defined as below.<BR><BR>
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# @Prompt The specified AP target C-state for Mwait.
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gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate|0
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## @file
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# Component description file for IceLake Fsp Bin package.
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#
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# @copyright
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# Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>
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#
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# SPDX-License-Identifier: BSD-2-Clause-Patent
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#
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# @par Specification
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##
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[Defines]
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DEC_SPECIFICATION = 0x00010005
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PACKAGE_NAME = IceLakeFspBinPkg
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PACKAGE_GUID = 5A536013-A46E-44AD-8B30-738235F77B06
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PACKAGE_VERSION = 1.02
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[Includes]
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Include
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[Guids]
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gFspInfoGuid = { 0x067e0f25, 0x374f, 0x47c2, { 0x17, 0x92, 0x86, 0xdc, 0xdb, 0xc4, 0x8a, 0xc9 }}
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[Ppis]
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gEfiReadyToInstallPciEnumerationCompleteProtocolGuid = { 0x84E3F112, 0x3C91, 0x476C, { 0xA0, 0x61, 0xE3, 0x3F, 0xA0, 0x8C, 0xCA, 0xF8 }}
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gEfiReadyToInstallEventReadyToBootGuid = { 0xDB0F224F, 0x0D43, 0x4D77, { 0x86, 0x21, 0x96, 0xBB, 0xD4, 0xAD, 0x5C, 0x91 }}
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gFspReadyToInstallEventEndOfFirmwareGuid = { 0xD8D9A0E1, 0xC34E, 0x4FDB, { 0x8C, 0xCF, 0x10, 0x51, 0x5B, 0xE4, 0x76, 0x5D }}
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gEndOfFspS3NotifyGuid = { 0x4AF40FFA, 0x60CB, 0x4A9F, { 0xA0, 0xAA, 0x0A, 0x66, 0xC0, 0x13, 0xBA, 0xF0 }}
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/** @file
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Header file for Firmware Version Information
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@copyright
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Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _FIRMWARE_VERSION_INFO_HOB_H_
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#define _FIRMWARE_VERSION_INFO_HOB_H_
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#include <Uefi/UefiMultiPhase.h>
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#include <Pi/PiBootMode.h>
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#include <Pi/PiHob.h>
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#pragma pack(1)
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///
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/// Firmware Version Structure
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///
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typedef struct {
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UINT8 MajorVersion;
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UINT8 MinorVersion;
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UINT8 Revision;
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UINT16 BuildNumber;
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} FIRMWARE_VERSION;
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///
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/// Firmware Version Information Structure
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///
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typedef struct {
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UINT8 ComponentNameIndex; ///< Offset 0 Index of Component Name
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UINT8 VersionStringIndex; ///< Offset 1 Index of Version String
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FIRMWARE_VERSION Version; ///< Offset 2-6 Firmware version
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} FIRMWARE_VERSION_INFO;
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#ifndef __SMBIOS_STANDARD_H__
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///
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/// The Smbios structure header.
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///
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typedef struct {
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UINT8 Type;
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UINT8 Length;
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UINT16 Handle;
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} SMBIOS_STRUCTURE;
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#endif
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///
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/// Firmware Version Information HOB Structure
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///
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typedef struct {
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EFI_HOB_GUID_TYPE Header; ///< Offset 0-23 The header of FVI HOB
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SMBIOS_STRUCTURE SmbiosData; ///< Offset 24-27 The SMBIOS header of FVI HOB
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UINT8 Count; ///< Offset 28 Number of FVI elements included.
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///
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/// FIRMWARE_VERSION_INFO structures followed by the null terminated string buffer
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///
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} FIRMWARE_VERSION_INFO_HOB;
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#pragma pack()
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#endif // _FIRMWARE_VERSION_INFO_HOB_H_
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/** @file
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Header file for FSP Information HOB.
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@copyright
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Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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@par Specification Reference:
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**/
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#ifndef _FSP_INFO_HOB_H_
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#define _FSP_INFO_HOB_H_
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extern EFI_GUID gFspInfoGuid;
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#pragma pack (push, 1)
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typedef struct {
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UINT8 SiliconInitVersionMajor;
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UINT8 SiliconInitVersionMinor;
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UINT8 SiliconInitVersionRevision;
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UINT8 SiliconInitVersionBuild;
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UINT8 FspVersionRevision;
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UINT8 FspVersionBuild;
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UINT8 TimeStamp [12];
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} FSP_INFO_HOB;
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#pragma pack (pop)
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#endif // _FSP_INFO_HOB_H_
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/** @file
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Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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This file is automatically generated. Please do NOT modify !!!
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**/
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#ifndef __FSPUPD_H__
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#define __FSPUPD_H__
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#include <FspEas.h>
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#pragma pack(1)
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#define FSPT_UPD_SIGNATURE 0x545F4450554C4349 /* 'ICLUPD_T' */
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#define FSPM_UPD_SIGNATURE 0x4D5F4450554C4349 /* 'ICLUPD_M' */
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#define FSPS_UPD_SIGNATURE 0x535F4450554C4349 /* 'ICLUPD_S' */
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#pragma pack()
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#endif
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/** @file
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Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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This file is automatically generated. Please do NOT modify !!!
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**/
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#ifndef __FSPTUPD_H__
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#define __FSPTUPD_H__
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#include <FspUpd.h>
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#pragma pack(1)
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/** Fsp T Core UPD
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**/
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typedef struct {
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/** Offset 0x0020
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**/
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UINT32 MicrocodeRegionBase;
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/** Offset 0x0024
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**/
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UINT32 MicrocodeRegionSize;
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/** Offset 0x0028
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**/
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UINT32 CodeRegionBase;
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/** Offset 0x002C
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**/
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UINT32 CodeRegionSize;
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/** Offset 0x0030
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**/
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UINT8 Reserved[16];
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} FSPT_CORE_UPD;
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/** Fsp T Configuration
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**/
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typedef struct {
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/** Offset 0x0040 - Pci Express Base Address
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Base address to be programmed for Pci Express
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**/
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UINT64 PcdPciExpressBaseAddress;
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/** Offset 0x0048 - Pci Express Region Length
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Region Length to be programmed for Pci Express
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**/
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UINT32 PcdPciExpressRegionLength;
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/** Offset 0x004C
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**/
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UINT8 SaFsptRsvd[16];
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/** Offset 0x005C - PcdSerialIoUartDebugEnable
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Enable SerialIo Uart debug library with/without initializing SerialIo Uart device in FSP.
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0:Disable, 1:Enable and Initialize, 2:Enable without Initializing
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**/
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UINT8 PcdSerialIoUartDebugEnable;
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/** Offset 0x005D - PcdSerialIoUartNumber - FSPT
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Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT
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Core interface, it cannot be used for debug purpose.
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0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2
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**/
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UINT8 PcdSerialIoUartNumber;
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/** Offset 0x005E - PcdSerialIoUartMode - FSPT
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Select SerialIo Uart Controller mode
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0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom,
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4:SerialIoUartSkipInit
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**/
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UINT8 PcdSerialIoUartMode;
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/** Offset 0x005F
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**/
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UINT8 UnusedUpdSpace0;
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/** Offset 0x0060 - PcdSerialIoUartBaudRate - FSPT
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Set default BaudRate Supported from 0 - default to 6000000
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**/
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UINT32 PcdSerialIoUartBaudRate;
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/** Offset 0x0064 - PcdSerialIoUartParity - FSPT
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Set default Parity.
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0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity
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**/
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UINT8 PcdSerialIoUartParity;
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/** Offset 0x0065 - PcdSerialIoUartDataBits - FSPT
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Set default word length. 0: Default, 5,6,7,8
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**/
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UINT8 PcdSerialIoUartDataBits;
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/** Offset 0x0066 - PcdSerialIoUartStopBits - FSPT
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Set default stop bits.
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0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits
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**/
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UINT8 PcdSerialIoUartStopBits;
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/** Offset 0x0067 - PcdSerialIoUartAutoFlow - FSPT
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Enables UART hardware flow control, CTS and RTS lines.
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0: Disable, 1:Enable
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**/
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UINT8 PcdSerialIoUartAutoFlow;
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/** Offset 0x0068 - PcdSerialIoUartRxPinMux - FSPT
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Select RX pin muxing for SerialIo UART used for debug
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**/
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UINT32 PcdSerialIoUartRxPinMux;
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/** Offset 0x006C - PcdSerialIoUartTxPinMux - FSPT
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Select TX pin muxing for SerialIo UART used for debug
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**/
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UINT32 PcdSerialIoUartTxPinMux;
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/** Offset 0x0070 - PcdSerialIoUartRtsPinMux - FSPT
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Select SerialIo Uart used for debug Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS*
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for possible values.
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**/
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UINT32 PcdSerialIoUartRtsPinMux;
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/** Offset 0x0074 - PcdSerialIoUartCtsPinMux - FSPT
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Select SerialIo Uart used for debug Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS*
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for possible values.
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**/
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UINT32 PcdSerialIoUartCtsPinMux;
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/** Offset 0x0078 - PcdLpcUartDebugEnable
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Enable to initialize LPC Uart device in FSP.
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0:Disable, 1:Enable
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**/
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UINT8 PcdLpcUartDebugEnable;
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/** Offset 0x0079
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**/
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UINT8 ReservedFsptUpd1[7];
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} FSP_T_CONFIG;
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/** Fsp T UPD Configuration
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**/
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typedef struct {
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/** Offset 0x0000
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**/
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FSP_UPD_HEADER FspUpdHeader;
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/** Offset 0x0020
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**/
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FSPT_CORE_UPD FsptCoreUpd;
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/** Offset 0x0040
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**/
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FSP_T_CONFIG FsptConfig;
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/** Offset 0x0080
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||||
**/
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UINT8 UnusedUpdSpace1[6];
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/** Offset 0x0086
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||||
**/
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UINT16 UpdTerminator;
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} FSPT_UPD;
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#pragma pack()
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#endif
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/** @file
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||||
Header file for GpioConfig structure used by GPIO library.
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|
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@copyright
|
||||
Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.<BR>
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||||
|
||||
SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||
|
||||
@par Specification Reference:
|
||||
**/
|
||||
#ifndef _GPIO_CONFIG_H_
|
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#define _GPIO_CONFIG_H_
|
||||
|
||||
#pragma pack(push, 1)
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||||
|
||||
///
|
||||
/// For any GpioPad usage in code use GPIO_PAD type
|
||||
///
|
||||
typedef UINT32 GPIO_PAD;
|
||||
|
||||
///
|
||||
/// GpioPad with additional native function information.
|
||||
/// This type is used to represent signal muxing alternatives. Platform will provide such value to
|
||||
/// identify muxing selection for given signal on a specific SOC.
|
||||
/// Please refer to the board layout
|
||||
///
|
||||
typedef UINT32 GPIO_NATIVE_PAD;
|
||||
|
||||
|
||||
///
|
||||
/// For any GpioGroup usage in code use GPIO_GROUP type
|
||||
///
|
||||
typedef UINT32 GPIO_GROUP;
|
||||
|
||||
/**
|
||||
GPIO configuration structure used for pin programming.
|
||||
Structure contains fields that can be used to configure pad.
|
||||
**/
|
||||
typedef struct {
|
||||
/**
|
||||
Pad Mode
|
||||
Pad can be set as GPIO or one of its native functions.
|
||||
When in native mode setting Direction (except Inversion), OutputState,
|
||||
InterruptConfig, Host Software Pad Ownership and OutputStateLock are unnecessary.
|
||||
Refer to definition of GPIO_PAD_MODE.
|
||||
Refer to EDS for each native mode according to the pad.
|
||||
**/
|
||||
UINT32 PadMode : 5;
|
||||
/**
|
||||
Host Software Pad Ownership
|
||||
Set pad to ACPI mode or GPIO Driver Mode.
|
||||
Refer to definition of GPIO_HOSTSW_OWN.
|
||||
**/
|
||||
UINT32 HostSoftPadOwn : 2;
|
||||
/**
|
||||
GPIO Direction
|
||||
Can choose between In, In with inversion, Out, both In and Out, both In with inversion and out or disabling both.
|
||||
Refer to definition of GPIO_DIRECTION for supported settings.
|
||||
**/
|
||||
UINT32 Direction : 6;
|
||||
/**
|
||||
Output State
|
||||
Set Pad output value.
|
||||
Refer to definition of GPIO_OUTPUT_STATE for supported settings.
|
||||
This setting takes place when output is enabled.
|
||||
**/
|
||||
UINT32 OutputState : 2;
|
||||
/**
|
||||
GPIO Interrupt Configuration
|
||||
Set Pad to cause one of interrupts (IOxAPIC/SCI/SMI/NMI).
|
||||
This setting is applicable only if GPIO is in GpioMode with input enabled.
|
||||
Refer to definition of GPIO_INT_CONFIG for supported settings.
|
||||
**/
|
||||
UINT32 InterruptConfig : 9;
|
||||
/**
|
||||
GPIO Power Configuration.
|
||||
This setting controls Pad Reset Configuration.
|
||||
Refer to definition of GPIO_RESET_CONFIG for supported settings.
|
||||
**/
|
||||
UINT32 PowerConfig : 8;
|
||||
/**
|
||||
GPIO Electrical Configuration
|
||||
This setting controls pads termination.
|
||||
Refer to definition of GPIO_ELECTRICAL_CONFIG for supported settings.
|
||||
**/
|
||||
UINT32 ElectricalConfig : 9;
|
||||
/**
|
||||
GPIO Lock Configuration
|
||||
This setting controls pads lock.
|
||||
Refer to definition of GPIO_LOCK_CONFIG for supported settings.
|
||||
**/
|
||||
UINT32 LockConfig : 4;
|
||||
/**
|
||||
Additional GPIO configuration
|
||||
Refer to definition of GPIO_OTHER_CONFIG for supported settings.
|
||||
**/
|
||||
UINT32 OtherSettings : 9;
|
||||
UINT32 RsvdBits : 10; ///< Reserved bits for future extension
|
||||
} GPIO_CONFIG;
|
||||
|
||||
|
||||
typedef enum {
|
||||
GpioHardwareDefault = 0x0 ///< Leave setting unmodified
|
||||
} GPIO_HARDWARE_DEFAULT;
|
||||
|
||||
/**
|
||||
GPIO Pad Mode
|
||||
Refer to GPIO documentation on native functions available for certain pad.
|
||||
If GPIO is set to one of NativeX modes then following settings are not applicable
|
||||
and can be skipped:
|
||||
- Interrupt related settings
|
||||
- Host Software Ownership
|
||||
- Output/Input enabling/disabling
|
||||
- Output lock
|
||||
**/
|
||||
typedef enum {
|
||||
GpioPadModeGpio = 0x1,
|
||||
GpioPadModeNative1 = 0x3,
|
||||
GpioPadModeNative2 = 0x5,
|
||||
GpioPadModeNative3 = 0x7,
|
||||
GpioPadModeNative4 = 0x9,
|
||||
GpioPadModeNative5 = 0xB,
|
||||
GpioPadModeNative6 = 0xD
|
||||
} GPIO_PAD_MODE;
|
||||
|
||||
/**
|
||||
Host Software Pad Ownership modes
|
||||
This setting affects GPIO interrupt status registers. Depending on chosen ownership
|
||||
some GPIO Interrupt status register get updated and other masked.
|
||||
Please refer to EDS for HOSTSW_OWN register description.
|
||||
**/
|
||||
typedef enum {
|
||||
GpioHostOwnDefault = 0x0, ///< Leave ownership value unmodified
|
||||
/**
|
||||
Set HOST ownership to ACPI.
|
||||
Use this setting if pad is not going to be used by GPIO OS driver.
|
||||
If GPIO is configured to generate SCI/SMI/NMI then this setting must be
|
||||
used for interrupts to work
|
||||
**/
|
||||
GpioHostOwnAcpi = 0x1,
|
||||
/**
|
||||
Set HOST ownership to GPIO Driver mode.
|
||||
Use this setting only if GPIO pad should be controlled by GPIO OS Driver.
|
||||
GPIO OS Driver will be able to control the pad if appropriate entry in
|
||||
ACPI exists (refer to ACPI specification for GpioIo and GpioInt descriptors)
|
||||
**/
|
||||
GpioHostOwnGpio = 0x3
|
||||
} GPIO_HOSTSW_OWN;
|
||||
|
||||
///
|
||||
/// GPIO Direction
|
||||
///
|
||||
typedef enum {
|
||||
GpioDirDefault = 0x0, ///< Leave pad direction setting unmodified
|
||||
GpioDirInOut = (0x1 | (0x1 << 3)), ///< Set pad for both output and input
|
||||
GpioDirInInvOut = (0x1 | (0x3 << 3)), ///< Set pad for both output and input with inversion
|
||||
GpioDirIn = (0x3 | (0x1 << 3)), ///< Set pad for input only
|
||||
GpioDirInInv = (0x3 | (0x3 << 3)), ///< Set pad for input with inversion
|
||||
GpioDirOut = 0x5, ///< Set pad for output only
|
||||
GpioDirNone = 0x7 ///< Disable both output and input
|
||||
} GPIO_DIRECTION;
|
||||
|
||||
/**
|
||||
GPIO Output State
|
||||
This field is relevant only if output is enabled
|
||||
**/
|
||||
typedef enum {
|
||||
GpioOutDefault = 0x0, ///< Leave output value unmodified
|
||||
GpioOutLow = 0x1, ///< Set output to low
|
||||
GpioOutHigh = 0x3 ///< Set output to high
|
||||
} GPIO_OUTPUT_STATE;
|
||||
|
||||
/**
|
||||
GPIO interrupt configuration
|
||||
This setting is applicable only if pad is in GPIO mode and has input enabled.
|
||||
GPIO_INT_CONFIG allows to choose which interrupt is generated (IOxAPIC/SCI/SMI/NMI)
|
||||
and how it is triggered (edge or level). Refer to PADCFG_DW0 register description in
|
||||
EDS for details on this settings.
|
||||
Field from GpioIntNmi to GpioIntApic can be OR'ed with GpioIntLevel to GpioIntBothEdge
|
||||
to describe an interrupt e.g. GpioIntApic | GpioIntLevel
|
||||
If GPIO is set to cause an SCI then also GPI_GPE_EN is enabled for this pad.
|
||||
If GPIO is set to cause an NMI then also GPI_NMI_EN is enabled for this pad.
|
||||
Not all GPIO are capable of generating an SMI or NMI interrupt.
|
||||
When routing GPIO to cause an IOxAPIC interrupt care must be taken, as this
|
||||
interrupt cannot be shared and its IRQn number is not configurable.
|
||||
Refer to EDS for GPIO pads IRQ numbers (PADCFG_DW1.IntSel)
|
||||
If GPIO is under GPIO OS driver control and appropriate ACPI GpioInt descriptor
|
||||
exist then use only trigger type setting (from GpioIntLevel to GpioIntBothEdge).
|
||||
This type of GPIO Driver interrupt doesn't have any additional routing setting
|
||||
required to be set by BIOS. Interrupt is handled by GPIO OS Driver.
|
||||
**/
|
||||
|
||||
typedef enum {
|
||||
GpioIntDefault = 0x0, ///< Leave value of interrupt routing unmodified
|
||||
GpioIntDis = 0x1, ///< Disable IOxAPIC/SCI/SMI/NMI interrupt generation
|
||||
GpioIntNmi = 0x3, ///< Enable NMI interrupt only
|
||||
GpioIntSmi = 0x5, ///< Enable SMI interrupt only
|
||||
GpioIntSci = 0x9, ///< Enable SCI interrupt only
|
||||
GpioIntApic = 0x11, ///< Enable IOxAPIC interrupt only
|
||||
GpioIntLevel = (0x1 << 5), ///< Set interrupt as level triggered
|
||||
GpioIntEdge = (0x3 << 5), ///< Set interrupt as edge triggered (type of edge depends on input inversion)
|
||||
GpioIntLvlEdgDis = (0x5 << 5), ///< Disable interrupt trigger
|
||||
GpioIntBothEdge = (0x7 << 5) ///< Set interrupt as both edge triggered
|
||||
} GPIO_INT_CONFIG;
|
||||
|
||||
#define B_GPIO_INT_CONFIG_INT_SOURCE_MASK 0x1F ///< Mask for GPIO_INT_CONFIG for interrupt source
|
||||
#define B_GPIO_INT_CONFIG_INT_TYPE_MASK 0xE0 ///< Mask for GPIO_INT_CONFIG for interrupt type
|
||||
|
||||
/**
|
||||
GPIO Power Configuration
|
||||
GPIO_RESET_CONFIG allows to set GPIO Reset type (PADCFG_DW0.PadRstCfg) which will
|
||||
be used to reset certain GPIO settings.
|
||||
Refer to EDS for settings that are controllable by PadRstCfg.
|
||||
**/
|
||||
typedef enum {
|
||||
GpioResetDefault = 0x00, ///< Leave value of pad reset unmodified
|
||||
/**
|
||||
Resume Reset (RSMRST)
|
||||
GPP: PadRstCfg = 00b = "Powergood"
|
||||
GPD: PadRstCfg = 11b = "Resume Reset"
|
||||
Pad setting will reset on:
|
||||
- DeepSx transition
|
||||
- G3
|
||||
Pad settings will not reset on:
|
||||
- S3/S4/S5 transition
|
||||
- Warm/Cold/Global reset
|
||||
**/
|
||||
GpioResumeReset = 0x01,
|
||||
/**
|
||||
Host Deep Reset
|
||||
PadRstCfg = 01b = "Deep GPIO Reset"
|
||||
Pad settings will reset on:
|
||||
- Warm/Cold/Global reset
|
||||
- DeepSx transition
|
||||
- G3
|
||||
Pad settings will not reset on:
|
||||
- S3/S4/S5 transition
|
||||
**/
|
||||
GpioHostDeepReset = 0x03,
|
||||
/**
|
||||
Platform Reset (PLTRST)
|
||||
PadRstCfg = 10b = "GPIO Reset"
|
||||
Pad settings will reset on:
|
||||
- S3/S4/S5 transition
|
||||
- Warm/Cold/Global reset
|
||||
- DeepSx transition
|
||||
- G3
|
||||
**/
|
||||
GpioPlatformReset = 0x05,
|
||||
/**
|
||||
Deep Sleep Well Reset (DSW_PWROK)
|
||||
GPP: not applicable
|
||||
GPD: PadRstCfg = 00b = "Powergood"
|
||||
Pad settings will reset on:
|
||||
- G3
|
||||
Pad settings will not reset on:
|
||||
- S3/S4/S5 transition
|
||||
- Warm/Cold/Global reset
|
||||
- DeepSx transition
|
||||
**/
|
||||
GpioDswReset = 0x07
|
||||
} GPIO_RESET_CONFIG;
|
||||
|
||||
/**
|
||||
GPIO Electrical Configuration
|
||||
Configuration options for GPIO termination setting
|
||||
**/
|
||||
typedef enum {
|
||||
GpioTermDefault = 0x0, ///< Leave termination setting unmodified
|
||||
GpioTermNone = 0x1, ///< none
|
||||
GpioTermWpd5K = 0x5, ///< 5kOhm weak pull-down
|
||||
GpioTermWpd20K = 0x9, ///< 20kOhm weak pull-down
|
||||
GpioTermWpu1K = 0x13, ///< 1kOhm weak pull-up
|
||||
GpioTermWpu2K = 0x17, ///< 2kOhm weak pull-up
|
||||
GpioTermWpu5K = 0x15, ///< 5kOhm weak pull-up
|
||||
GpioTermWpu20K = 0x19, ///< 20kOhm weak pull-up
|
||||
GpioTermWpu1K2K = 0x1B, ///< 1kOhm & 2kOhm weak pull-up
|
||||
/**
|
||||
Native function controls pads termination
|
||||
This setting is applicable only to some native modes.
|
||||
Please check EDS to determine which native functionality
|
||||
can control pads termination
|
||||
**/
|
||||
GpioTermNative = 0x1F
|
||||
} GPIO_ELECTRICAL_CONFIG;
|
||||
|
||||
#define B_GPIO_ELECTRICAL_CONFIG_TERMINATION_MASK 0x1F ///< Mask for GPIO_ELECTRICAL_CONFIG for termination value
|
||||
|
||||
/**
|
||||
GPIO LockConfiguration
|
||||
Set GPIO configuration lock and output state lock.
|
||||
GpioPadConfigUnlock/Lock and GpioOutputStateUnlock can be OR'ed.
|
||||
By default GPIO pads will be locked unless GPIO lib is explicitly
|
||||
informed that certain pad is to be left unlocked.
|
||||
Lock settings reset is in Powergood domain. Care must be taken when using this setting
|
||||
as fields it locks may be reset by a different signal and can be controlled
|
||||
by what is in GPIO_RESET_CONFIG (PADCFG_DW0.PadRstCfg). GPIO library provides
|
||||
functions which allow to unlock a GPIO pad. If possible each GPIO lib function will try to unlock
|
||||
an already locked pad upon request for reconfiguration
|
||||
**/
|
||||
typedef enum {
|
||||
/**
|
||||
Perform default action
|
||||
- if pad is an GPO, lock configuration but leave output unlocked
|
||||
- if pad is an GPI, lock everything
|
||||
- if pad is in native, lock everything
|
||||
**/
|
||||
GpioLockDefault = 0x0,
|
||||
GpioPadConfigUnlock = 0x3, ///< Leave Pad configuration unlocked
|
||||
GpioPadConfigLock = 0x1, ///< Lock Pad configuration
|
||||
GpioOutputStateUnlock = 0xC, ///< Leave Pad output control unlocked
|
||||
GpioPadUnlock = 0xF, ///< Leave both Pad configuration and output control unlocked
|
||||
GpioPadLock = 0x5, ///< Lock both Pad configuration and output control
|
||||
/**
|
||||
Below statuses are used for
|
||||
return from GpioGetPadConfig function
|
||||
**/
|
||||
GpioLockTxLockCfgUnLock = 0x7, ///< Tx State locked, Pad Configuration unlocked
|
||||
GpioLockTxUnLockCfgLock = 0xD ///< Tx State unlocked, Pad Configuration locked
|
||||
} GPIO_LOCK_CONFIG;
|
||||
|
||||
#define B_GPIO_LOCK_CONFIG_PAD_CONF_LOCK_MASK 0x3 ///< Mask for GPIO_LOCK_CONFIG for Pad Configuration Lock
|
||||
#define B_GPIO_LOCK_CONFIG_OUTPUT_LOCK_MASK 0xC ///< Mask for GPIO_LOCK_CONFIG for Pad Output Lock
|
||||
|
||||
/**
|
||||
Other GPIO Configuration
|
||||
GPIO_OTHER_CONFIG is used for less often settings and for future extensions
|
||||
Supported settings:
|
||||
- RX raw override to '1' - allows to override input value to '1'
|
||||
This setting is applicable only if in input mode (both in GPIO and native usage).
|
||||
The override takes place at the internal pad state directly from buffer and before the RXINV.
|
||||
**/
|
||||
typedef enum {
|
||||
GpioRxRaw1Default = 0x0, ///< Use default input override value
|
||||
GpioRxRaw1Dis = 0x1, ///< Don't override input
|
||||
GpioRxRaw1En = 0x3 ///< Override input to '1'
|
||||
} GPIO_OTHER_CONFIG;
|
||||
|
||||
#define B_GPIO_OTHER_CONFIG_RXRAW_MASK 0x3 ///< Mask for GPIO_OTHER_CONFIG for RxRaw1 setting
|
||||
|
||||
#pragma pack(pop)
|
||||
|
||||
#endif //_GPIO_CONFIG_H_
|
||||
|
|
@ -0,0 +1,360 @@
|
|||
/** @file
|
||||
Sample enum definitions for GPIO table.
|
||||
|
||||
@copyright
|
||||
Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>
|
||||
|
||||
SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||
|
||||
@par Specification Reference:
|
||||
**/
|
||||
#ifndef __GPIOCONFIG_H__
|
||||
#define __GPIOCONFIG_H__
|
||||
#include <FsptUpd.h>
|
||||
#include <FspmUpd.h>
|
||||
#include <FspsUpd.h>
|
||||
|
||||
/*
|
||||
SKL LP GPIO pins
|
||||
Use below for functions from PCH GPIO Lib which
|
||||
require GpioPad as argument. Encoding used here
|
||||
has all information required by library functions
|
||||
*/
|
||||
#define GPIO_SKL_LP_GPP_A0 0x02000000
|
||||
#define GPIO_SKL_LP_GPP_A1 0x02000001
|
||||
#define GPIO_SKL_LP_GPP_A2 0x02000002
|
||||
#define GPIO_SKL_LP_GPP_A3 0x02000003
|
||||
#define GPIO_SKL_LP_GPP_A4 0x02000004
|
||||
#define GPIO_SKL_LP_GPP_A5 0x02000005
|
||||
#define GPIO_SKL_LP_GPP_A6 0x02000006
|
||||
#define GPIO_SKL_LP_GPP_A7 0x02000007
|
||||
#define GPIO_SKL_LP_GPP_A8 0x02000008
|
||||
#define GPIO_SKL_LP_GPP_A9 0x02000009
|
||||
#define GPIO_SKL_LP_GPP_A10 0x0200000A
|
||||
#define GPIO_SKL_LP_GPP_A11 0x0200000B
|
||||
#define GPIO_SKL_LP_GPP_A12 0x0200000C
|
||||
#define GPIO_SKL_LP_GPP_A13 0x0200000D
|
||||
#define GPIO_SKL_LP_GPP_A14 0x0200000E
|
||||
#define GPIO_SKL_LP_GPP_A15 0x0200000F
|
||||
#define GPIO_SKL_LP_GPP_A16 0x02000010
|
||||
#define GPIO_SKL_LP_GPP_A17 0x02000011
|
||||
#define GPIO_SKL_LP_GPP_A18 0x02000012
|
||||
#define GPIO_SKL_LP_GPP_A19 0x02000013
|
||||
#define GPIO_SKL_LP_GPP_A20 0x02000014
|
||||
#define GPIO_SKL_LP_GPP_A21 0x02000015
|
||||
#define GPIO_SKL_LP_GPP_A22 0x02000016
|
||||
#define GPIO_SKL_LP_GPP_A23 0x02000017
|
||||
#define GPIO_SKL_LP_GPP_B0 0x02010000
|
||||
#define GPIO_SKL_LP_GPP_B1 0x02010001
|
||||
#define GPIO_SKL_LP_GPP_B2 0x02010002
|
||||
#define GPIO_SKL_LP_GPP_B3 0x02010003
|
||||
#define GPIO_SKL_LP_GPP_B4 0x02010004
|
||||
#define GPIO_SKL_LP_GPP_B5 0x02010005
|
||||
#define GPIO_SKL_LP_GPP_B6 0x02010006
|
||||
#define GPIO_SKL_LP_GPP_B7 0x02010007
|
||||
#define GPIO_SKL_LP_GPP_B8 0x02010008
|
||||
#define GPIO_SKL_LP_GPP_B9 0x02010009
|
||||
#define GPIO_SKL_LP_GPP_B10 0x0201000A
|
||||
#define GPIO_SKL_LP_GPP_B11 0x0201000B
|
||||
#define GPIO_SKL_LP_GPP_B12 0x0201000C
|
||||
#define GPIO_SKL_LP_GPP_B13 0x0201000D
|
||||
#define GPIO_SKL_LP_GPP_B14 0x0201000E
|
||||
#define GPIO_SKL_LP_GPP_B15 0x0201000F
|
||||
#define GPIO_SKL_LP_GPP_B16 0x02010010
|
||||
#define GPIO_SKL_LP_GPP_B17 0x02010011
|
||||
#define GPIO_SKL_LP_GPP_B18 0x02010012
|
||||
#define GPIO_SKL_LP_GPP_B19 0x02010013
|
||||
#define GPIO_SKL_LP_GPP_B20 0x02010014
|
||||
#define GPIO_SKL_LP_GPP_B21 0x02010015
|
||||
#define GPIO_SKL_LP_GPP_B22 0x02010016
|
||||
#define GPIO_SKL_LP_GPP_B23 0x02010017
|
||||
#define GPIO_SKL_LP_GPP_C0 0x02020000
|
||||
#define GPIO_SKL_LP_GPP_C1 0x02020001
|
||||
#define GPIO_SKL_LP_GPP_C2 0x02020002
|
||||
#define GPIO_SKL_LP_GPP_C3 0x02020003
|
||||
#define GPIO_SKL_LP_GPP_C4 0x02020004
|
||||
#define GPIO_SKL_LP_GPP_C5 0x02020005
|
||||
#define GPIO_SKL_LP_GPP_C6 0x02020006
|
||||
#define GPIO_SKL_LP_GPP_C7 0x02020007
|
||||
#define GPIO_SKL_LP_GPP_C8 0x02020008
|
||||
#define GPIO_SKL_LP_GPP_C9 0x02020009
|
||||
#define GPIO_SKL_LP_GPP_C10 0x0202000A
|
||||
#define GPIO_SKL_LP_GPP_C11 0x0202000B
|
||||
#define GPIO_SKL_LP_GPP_C12 0x0202000C
|
||||
#define GPIO_SKL_LP_GPP_C13 0x0202000D
|
||||
#define GPIO_SKL_LP_GPP_C14 0x0202000E
|
||||
#define GPIO_SKL_LP_GPP_C15 0x0202000F
|
||||
#define GPIO_SKL_LP_GPP_C16 0x02020010
|
||||
#define GPIO_SKL_LP_GPP_C17 0x02020011
|
||||
#define GPIO_SKL_LP_GPP_C18 0x02020012
|
||||
#define GPIO_SKL_LP_GPP_C19 0x02020013
|
||||
#define GPIO_SKL_LP_GPP_C20 0x02020014
|
||||
#define GPIO_SKL_LP_GPP_C21 0x02020015
|
||||
#define GPIO_SKL_LP_GPP_C22 0x02020016
|
||||
#define GPIO_SKL_LP_GPP_C23 0x02020017
|
||||
#define GPIO_SKL_LP_GPP_D0 0x02030000
|
||||
#define GPIO_SKL_LP_GPP_D1 0x02030001
|
||||
#define GPIO_SKL_LP_GPP_D2 0x02030002
|
||||
#define GPIO_SKL_LP_GPP_D3 0x02030003
|
||||
#define GPIO_SKL_LP_GPP_D4 0x02030004
|
||||
#define GPIO_SKL_LP_GPP_D5 0x02030005
|
||||
#define GPIO_SKL_LP_GPP_D6 0x02030006
|
||||
#define GPIO_SKL_LP_GPP_D7 0x02030007
|
||||
#define GPIO_SKL_LP_GPP_D8 0x02030008
|
||||
#define GPIO_SKL_LP_GPP_D9 0x02030009
|
||||
#define GPIO_SKL_LP_GPP_D10 0x0203000A
|
||||
#define GPIO_SKL_LP_GPP_D11 0x0203000B
|
||||
#define GPIO_SKL_LP_GPP_D12 0x0203000C
|
||||
#define GPIO_SKL_LP_GPP_D13 0x0203000D
|
||||
#define GPIO_SKL_LP_GPP_D14 0x0203000E
|
||||
#define GPIO_SKL_LP_GPP_D15 0x0203000F
|
||||
#define GPIO_SKL_LP_GPP_D16 0x02030010
|
||||
#define GPIO_SKL_LP_GPP_D17 0x02030011
|
||||
#define GPIO_SKL_LP_GPP_D18 0x02030012
|
||||
#define GPIO_SKL_LP_GPP_D19 0x02030013
|
||||
#define GPIO_SKL_LP_GPP_D20 0x02030014
|
||||
#define GPIO_SKL_LP_GPP_D21 0x02030015
|
||||
#define GPIO_SKL_LP_GPP_D22 0x02030016
|
||||
#define GPIO_SKL_LP_GPP_D23 0x02030017
|
||||
#define GPIO_SKL_LP_GPP_E0 0x02040000
|
||||
#define GPIO_SKL_LP_GPP_E1 0x02040001
|
||||
#define GPIO_SKL_LP_GPP_E2 0x02040002
|
||||
#define GPIO_SKL_LP_GPP_E3 0x02040003
|
||||
#define GPIO_SKL_LP_GPP_E4 0x02040004
|
||||
#define GPIO_SKL_LP_GPP_E5 0x02040005
|
||||
#define GPIO_SKL_LP_GPP_E6 0x02040006
|
||||
#define GPIO_SKL_LP_GPP_E7 0x02040007
|
||||
#define GPIO_SKL_LP_GPP_E8 0x02040008
|
||||
#define GPIO_SKL_LP_GPP_E9 0x02040009
|
||||
#define GPIO_SKL_LP_GPP_E10 0x0204000A
|
||||
#define GPIO_SKL_LP_GPP_E11 0x0204000B
|
||||
#define GPIO_SKL_LP_GPP_E12 0x0204000C
|
||||
#define GPIO_SKL_LP_GPP_E13 0x0204000D
|
||||
#define GPIO_SKL_LP_GPP_E14 0x0204000E
|
||||
#define GPIO_SKL_LP_GPP_E15 0x0204000F
|
||||
#define GPIO_SKL_LP_GPP_E16 0x02040010
|
||||
#define GPIO_SKL_LP_GPP_E17 0x02040011
|
||||
#define GPIO_SKL_LP_GPP_E18 0x02040012
|
||||
#define GPIO_SKL_LP_GPP_E19 0x02040013
|
||||
#define GPIO_SKL_LP_GPP_E20 0x02040014
|
||||
#define GPIO_SKL_LP_GPP_E21 0x02040015
|
||||
#define GPIO_SKL_LP_GPP_E22 0x02040016
|
||||
#define GPIO_SKL_LP_GPP_E23 0x02040017
|
||||
#define GPIO_SKL_LP_GPP_F0 0x02050000
|
||||
#define GPIO_SKL_LP_GPP_F1 0x02050001
|
||||
#define GPIO_SKL_LP_GPP_F2 0x02050002
|
||||
#define GPIO_SKL_LP_GPP_F3 0x02050003
|
||||
#define GPIO_SKL_LP_GPP_F4 0x02050004
|
||||
#define GPIO_SKL_LP_GPP_F5 0x02050005
|
||||
#define GPIO_SKL_LP_GPP_F6 0x02050006
|
||||
#define GPIO_SKL_LP_GPP_F7 0x02050007
|
||||
#define GPIO_SKL_LP_GPP_F8 0x02050008
|
||||
#define GPIO_SKL_LP_GPP_F9 0x02050009
|
||||
#define GPIO_SKL_LP_GPP_F10 0x0205000A
|
||||
#define GPIO_SKL_LP_GPP_F11 0x0205000B
|
||||
#define GPIO_SKL_LP_GPP_F12 0x0205000C
|
||||
#define GPIO_SKL_LP_GPP_F13 0x0205000D
|
||||
#define GPIO_SKL_LP_GPP_F14 0x0205000E
|
||||
#define GPIO_SKL_LP_GPP_F15 0x0205000F
|
||||
#define GPIO_SKL_LP_GPP_F16 0x02050010
|
||||
#define GPIO_SKL_LP_GPP_F17 0x02050011
|
||||
#define GPIO_SKL_LP_GPP_F18 0x02050012
|
||||
#define GPIO_SKL_LP_GPP_F19 0x02050013
|
||||
#define GPIO_SKL_LP_GPP_F20 0x02050014
|
||||
#define GPIO_SKL_LP_GPP_F21 0x02050015
|
||||
#define GPIO_SKL_LP_GPP_F22 0x02050016
|
||||
#define GPIO_SKL_LP_GPP_F23 0x02050017
|
||||
#define GPIO_SKL_LP_GPP_G0 0x02060000
|
||||
#define GPIO_SKL_LP_GPP_G1 0x02060001
|
||||
#define GPIO_SKL_LP_GPP_G2 0x02060002
|
||||
#define GPIO_SKL_LP_GPP_G3 0x02060003
|
||||
#define GPIO_SKL_LP_GPP_G4 0x02060004
|
||||
#define GPIO_SKL_LP_GPP_G5 0x02060005
|
||||
#define GPIO_SKL_LP_GPP_G6 0x02060006
|
||||
#define GPIO_SKL_LP_GPP_G7 0x02060007
|
||||
#define GPIO_SKL_LP_GPD0 0x02070000
|
||||
#define GPIO_SKL_LP_GPD1 0x02070001
|
||||
#define GPIO_SKL_LP_GPD2 0x02070002
|
||||
#define GPIO_SKL_LP_GPD3 0x02070003
|
||||
#define GPIO_SKL_LP_GPD4 0x02070004
|
||||
#define GPIO_SKL_LP_GPD5 0x02070005
|
||||
#define GPIO_SKL_LP_GPD6 0x02070006
|
||||
#define GPIO_SKL_LP_GPD7 0x02070007
|
||||
#define GPIO_SKL_LP_GPD8 0x02070008
|
||||
#define GPIO_SKL_LP_GPD9 0x02070009
|
||||
#define GPIO_SKL_LP_GPD10 0x0207000A
|
||||
#define GPIO_SKL_LP_GPD11 0x0207000B
|
||||
|
||||
#define END_OF_GPIO_TABLE 0xFFFFFFFF
|
||||
|
||||
//Sample GPIO Table
|
||||
|
||||
static GPIO_INIT_CONFIG mGpioTableLpDdr3Rvp3[] =
|
||||
{
|
||||
//skip for eSPI function {GPIO_SKL_LP_GPP_A0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//H_RCIN_N
|
||||
//skip for eSPI function {GPIO_SKL_LP_GPP_A1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD0_ESPI_IO0
|
||||
//skip for eSPI function {GPIO_SKL_LP_GPP_A2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD1_ESPI_IO1
|
||||
//skip for eSPI function {GPIO_SKL_LP_GPP_A3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD2_ESPI_IO2
|
||||
//skip for eSPI function {GPIO_SKL_LP_GPP_A4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD3_ESPI_IO3
|
||||
//skip for eSPI function {GPIO_SKL_LP_GPP_A5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//LPC_FRAME_ESPI_CS_N
|
||||
//skip for eSPI function {GPIO_SKL_LP_GPP_A6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//INT_SERIRQ
|
||||
//skip for eSPI function {GPIO_SKL_LP_GPP_A7, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PM_SLP_S0ix_R_N
|
||||
{GPIO_SKL_LP_GPP_A8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PM_CLKRUN_N
|
||||
//skip for eSPI function {GPIO_SKL_LP_GPP_A9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_CLK_ESPI_CLK
|
||||
{GPIO_SKL_LP_GPP_A10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//PCH_CLK_PCI_TPM
|
||||
{GPIO_SKL_LP_GPP_A11, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//EC_HID_INTR
|
||||
{GPIO_SKL_LP_GPP_A12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//M.2_WWAN_GNSS_UART_RST_N
|
||||
{GPIO_SKL_LP_GPP_A13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SUS_PWR_ACK_R
|
||||
//skip for eSPI function {GPIO_SKL_LP_GPP_A14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PM_SUS_STAT_ESPI_RST_N
|
||||
{GPIO_SKL_LP_GPP_A15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SUSACK_R_N
|
||||
{GPIO_SKL_LP_GPP_A16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_1P8_SEL
|
||||
{GPIO_SKL_LP_GPP_A17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_PWR_EN_N
|
||||
{GPIO_SKL_LP_GPP_A18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_GP_0_SENSOR
|
||||
{GPIO_SKL_LP_GPP_A19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_GP_1_SENSOR
|
||||
{GPIO_SKL_LP_GPP_A20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_GP_2_SENSOR
|
||||
{GPIO_SKL_LP_GPP_A21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//GNSS_CHUB_IRQ
|
||||
{GPIO_SKL_LP_GPP_A22, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//FPS_SLP_N
|
||||
{GPIO_SKL_LP_GPP_A23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//FPS_DRDY
|
||||
{GPIO_SKL_LP_GPP_B0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//V0.85A_VID0
|
||||
{GPIO_SKL_LP_GPP_B1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//V0.85A_VID1
|
||||
{GPIO_SKL_LP_GPP_B2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//GP_VRALERTB
|
||||
{GPIO_SKL_LP_GPP_B3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioPlatformReset, GpioTermNone}},//TCH_PAD_INTR_R_N
|
||||
{GPIO_SKL_LP_GPP_B4, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//BT_RF_KILL_N
|
||||
{GPIO_SKL_LP_GPP_B5, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//M.2_BT_UART_WAKE_N
|
||||
// {GPIO_SKL_LP_GPP_B6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_SLOT1_N
|
||||
// {GPIO_SKL_LP_GPP_B7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_SLOT2_LAN_N
|
||||
// {GPIO_SKL_LP_GPP_B8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_M.2_SSD_SLOT3_N
|
||||
// {GPIO_SKL_LP_GPP_B9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_M.2_WIGIG_N
|
||||
// {GPIO_SKL_LP_GPP_B10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_M.2_WLAN_N
|
||||
{GPIO_SKL_LP_GPP_B11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//MPHY_EXT_PWR_GATEB
|
||||
{GPIO_SKL_LP_GPP_B12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_SLP_S0_N
|
||||
{GPIO_SKL_LP_GPP_B13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PLT_RST_N
|
||||
{GPIO_SKL_LP_GPP_B14, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//TCH_PNL_PWREN
|
||||
{GPIO_SKL_LP_GPP_B15, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_NFC_DFU
|
||||
{GPIO_SKL_LP_GPP_B16, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, GpioTermNone}},//M.2_WLAN_WIFI_WAKE_N
|
||||
{GPIO_SKL_LP_GPP_B17, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntSci, GpioHostDeepReset, GpioTermWpd20K}},//TBT_CIO_PLUG_EVENT_N
|
||||
{GPIO_SKL_LP_GPP_B18, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, GpioTermWpu20K}},//PCH_SLOT1_WAKE_N
|
||||
{GPIO_SKL_LP_GPP_B19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//FPS_GSPI1_CS_R1_N
|
||||
{GPIO_SKL_LP_GPP_B20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//FPS_GSPI1_CLK_R1
|
||||
{GPIO_SKL_LP_GPP_B21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//FPS_GSPI1_MISO_R1
|
||||
{GPIO_SKL_LP_GPP_B22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//FPS_GSPI1_MOSI_R1
|
||||
{GPIO_SKL_LP_GPP_B23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DISCRETE_GNSS_RESET_N
|
||||
{GPIO_SKL_LP_GPP_C0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SMB_CLK
|
||||
{GPIO_SKL_LP_GPP_C1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SMB_DATA
|
||||
{GPIO_SKL_LP_GPP_C2, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SKIN_THRM_SNSR_ALERT_N
|
||||
{GPIO_SKL_LP_GPP_C3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SML0_CLK
|
||||
{GPIO_SKL_LP_GPP_C4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SML0_DATA
|
||||
{GPIO_SKL_LP_GPP_C5, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermWpd20K}},//M.2_WIGIG_WAKE_N
|
||||
{GPIO_SKL_LP_GPP_C6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SML1_CLK
|
||||
{GPIO_SKL_LP_GPP_C7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SML1_DATA
|
||||
{GPIO_SKL_LP_GPP_C8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_RXD
|
||||
{GPIO_SKL_LP_GPP_C9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_TXD
|
||||
{GPIO_SKL_LP_GPP_C10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_RTS_N
|
||||
{GPIO_SKL_LP_GPP_C11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_CTS_N
|
||||
{GPIO_SKL_LP_GPP_C12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_RXD
|
||||
{GPIO_SKL_LP_GPP_C13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_TXD
|
||||
{GPIO_SKL_LP_GPP_C14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_RTS_N
|
||||
{GPIO_SKL_LP_GPP_C15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_CTS_N
|
||||
{GPIO_SKL_LP_GPP_C16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C0_SDA
|
||||
{GPIO_SKL_LP_GPP_C17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C0_SCL
|
||||
{GPIO_SKL_LP_GPP_C18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C1_SDA
|
||||
{GPIO_SKL_LP_GPP_C19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C1_SCL
|
||||
{GPIO_SKL_LP_GPP_C20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_RXD
|
||||
{GPIO_SKL_LP_GPP_C21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_TXD
|
||||
{GPIO_SKL_LP_GPP_C22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_RTS_N
|
||||
{GPIO_SKL_LP_GPP_C23, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_CTS_N
|
||||
{GPIO_SKL_LP_GPP_D0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_CS_N
|
||||
{GPIO_SKL_LP_GPP_D1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_CLK
|
||||
{GPIO_SKL_LP_GPP_D2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_MISO
|
||||
{GPIO_SKL_LP_GPP_D3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_MOSI
|
||||
{GPIO_SKL_LP_GPP_D4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CSI2_FLASH_STROBE
|
||||
{GPIO_SKL_LP_GPP_D5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C0_SDA
|
||||
{GPIO_SKL_LP_GPP_D6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C0_SCL
|
||||
{GPIO_SKL_LP_GPP_D7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C1_SDA
|
||||
{GPIO_SKL_LP_GPP_D8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C1_SCL
|
||||
{GPIO_SKL_LP_GPP_D9, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//HOME_BTN
|
||||
{GPIO_SKL_LP_GPP_D10, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SCREEN_LOCK_PCH
|
||||
{GPIO_SKL_LP_GPP_D11, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//VOL_UP_PCH
|
||||
{GPIO_SKL_LP_GPP_D12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//VOL_DOWN_PCH
|
||||
{GPIO_SKL_LP_GPP_D13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_RXD_SML0B_DATA
|
||||
{GPIO_SKL_LP_GPP_D14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_TXD_SML0B_CLK
|
||||
{GPIO_SKL_LP_GPP_D15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_RTS_N
|
||||
{GPIO_SKL_LP_GPP_D16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_CTS_SML0B_ALERT_N
|
||||
{GPIO_SKL_LP_GPP_D17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DMIC_CLK_1
|
||||
{GPIO_SKL_LP_GPP_D18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DMIC_DATA_1
|
||||
{GPIO_SKL_LP_GPP_D19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DMIC_CLK_0
|
||||
{GPIO_SKL_LP_GPP_D20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DMIC_DATA_0
|
||||
{GPIO_SKL_LP_GPP_D21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_IO2
|
||||
{GPIO_SKL_LP_GPP_D22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_IO3
|
||||
{GPIO_SKL_LP_GPP_D23, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP_MCLK
|
||||
{GPIO_SKL_LP_GPP_E0, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//SPI_TPM_HDR_IRQ_N
|
||||
{GPIO_SKL_LP_GPP_E1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SATA_ODD_PRSNT_N
|
||||
{GPIO_SKL_LP_GPP_E2, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntLvlEdgDis | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//M.2_SSD_SATA2_PCIE3_DET_N
|
||||
{GPIO_SKL_LP_GPP_E3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone}},//EINK_SSR_DFU_N
|
||||
{GPIO_SKL_LP_GPP_E4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_NFC_RESET
|
||||
{GPIO_SKL_LP_GPP_E5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SATA1_PHYSLP1_DIRECT_R
|
||||
{GPIO_SKL_LP_GPP_E6, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SATA2_PHYSLP2_M.2SSD_R
|
||||
{GPIO_SKL_LP_GPP_E8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_SATA_LED_N
|
||||
{GPIO_SKL_LP_GPP_E9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//USB_OC_0_WP1_OTG_N
|
||||
{GPIO_SKL_LP_GPP_E10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//USB_OC_1_WP4_N
|
||||
{GPIO_SKL_LP_GPP_E11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//USB_OC_2_WP2_WP3_WP5_R_N
|
||||
{GPIO_SKL_LP_GPP_E12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_NFC_IRQ
|
||||
{GPIO_SKL_LP_GPP_E13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI1_HPD_Q
|
||||
{GPIO_SKL_LP_GPP_E14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI2_HPD_Q
|
||||
{GPIO_SKL_LP_GPP_E15, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntSmi, GpioHostDeepReset, GpioTermNone}},//SMC_EXTSMI_R_N
|
||||
{GPIO_SKL_LP_GPP_E16, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, GpioTermNone}},//SMC_RUNTIME_SCI_R_N
|
||||
{GPIO_SKL_LP_GPP_E17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EDP_HPD
|
||||
{GPIO_SKL_LP_GPP_E18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI1_CTRL_CLK
|
||||
{GPIO_SKL_LP_GPP_E19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DDI1_CTRL_DATA
|
||||
{GPIO_SKL_LP_GPP_E20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI2_CTRL_CLK
|
||||
{GPIO_SKL_LP_GPP_E21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DDI2_CTRL_DATA
|
||||
{GPIO_SKL_LP_GPP_E22, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//PCH_CODEC_IRQ
|
||||
{GPIO_SKL_LP_GPP_E23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//TCH_PNL_RST_N
|
||||
{GPIO_SKL_LP_GPP_F0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_SCLK
|
||||
{GPIO_SKL_LP_GPP_F1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_SFRM
|
||||
{GPIO_SKL_LP_GPP_F2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_TXD
|
||||
{GPIO_SKL_LP_GPP_F3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_RXD
|
||||
{GPIO_SKL_LP_GPP_F4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C2_SDA
|
||||
{GPIO_SKL_LP_GPP_F5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C2_SCL
|
||||
{GPIO_SKL_LP_GPP_F6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C3_SDA
|
||||
{GPIO_SKL_LP_GPP_F7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C3_SCL
|
||||
{GPIO_SKL_LP_GPP_F8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C4_SDA
|
||||
{GPIO_SKL_LP_GPP_F9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C4_SCL
|
||||
{GPIO_SKL_LP_GPP_F10, {GpioPadModeNative2, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C5_ISH_12C2_SDA
|
||||
{GPIO_SKL_LP_GPP_F11, {GpioPadModeNative2, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C5_ISH_12C2_SCL
|
||||
{GPIO_SKL_LP_GPP_F12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_CMD
|
||||
{GPIO_SKL_LP_GPP_F13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA0
|
||||
{GPIO_SKL_LP_GPP_F14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA1
|
||||
{GPIO_SKL_LP_GPP_F15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA2
|
||||
{GPIO_SKL_LP_GPP_F16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA3
|
||||
{GPIO_SKL_LP_GPP_F17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA4
|
||||
{GPIO_SKL_LP_GPP_F18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA5
|
||||
{GPIO_SKL_LP_GPP_F19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA6
|
||||
{GPIO_SKL_LP_GPP_F20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA7
|
||||
{GPIO_SKL_LP_GPP_F21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_RCLK
|
||||
{GPIO_SKL_LP_GPP_F22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_CLK
|
||||
{GPIO_SKL_LP_GPP_F23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//PCH_M.2_WWAN_UIM_SIM_DET
|
||||
{GPIO_SKL_LP_GPP_G0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_CMD
|
||||
{GPIO_SKL_LP_GPP_G1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA0
|
||||
{GPIO_SKL_LP_GPP_G2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA1
|
||||
{GPIO_SKL_LP_GPP_G3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA2
|
||||
{GPIO_SKL_LP_GPP_G4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA3
|
||||
{GPIO_SKL_LP_GPP_G5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_CDB
|
||||
{GPIO_SKL_LP_GPP_G6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_CLK
|
||||
{GPIO_SKL_LP_GPP_G7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_WP
|
||||
{GPIO_SKL_LP_GPD0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//PM_BATLOW_R_N
|
||||
{GPIO_SKL_LP_GPD1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//AC_PRESENT_R
|
||||
{GPIO_SKL_LP_GPD2, {GpioPadModeNative1, GpioHostOwnAcpi, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioDswReset, GpioTermNone}},//LANWAKE_SMC_WAKE_SCI_N
|
||||
{GPIO_SKL_LP_GPD3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermWpu20K}},//PM_PWRBTN_R_N
|
||||
{GPIO_SKL_LP_GPD4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_S3_R_N
|
||||
{GPIO_SKL_LP_GPD5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_S4_R_N
|
||||
{GPIO_SKL_LP_GPD6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_M_R_N
|
||||
{GPIO_SKL_LP_GPD7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//USB_WAKEOUT_INTRUDET_N
|
||||
{GPIO_SKL_LP_GPD8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SUS_CLK
|
||||
{GPIO_SKL_LP_GPD9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//PCH_SLP_WLAN_N
|
||||
{GPIO_SKL_LP_GPD10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_S5_R_N
|
||||
{GPIO_SKL_LP_GPD11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//PM_LANPHY_ENABLE
|
||||
{END_OF_GPIO_TABLE, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//Marking End of Table
|
||||
};
|
||||
|
||||
#endif //_GPIO_CONFIG_H_
|
||||
|
|
@ -0,0 +1,35 @@
|
|||
/** @file
|
||||
Definitions for Hob Usage data HOB
|
||||
|
||||
@copyright
|
||||
Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
|
||||
|
||||
SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||
|
||||
@par Specification Reference:
|
||||
**/
|
||||
|
||||
#ifndef _HOB_USAGE_DATA_HOB_H_
|
||||
#define _HOB_USAGE_DATA_HOB_H_
|
||||
|
||||
extern EFI_GUID gHobUsageDataGuid;
|
||||
|
||||
#pragma pack (push, 1)
|
||||
|
||||
/**
|
||||
Hob Usage Data Hob
|
||||
|
||||
<b>Revision 1:</b>
|
||||
- Initial version.
|
||||
**/
|
||||
typedef struct {
|
||||
EFI_PHYSICAL_ADDRESS EfiMemoryTop;
|
||||
EFI_PHYSICAL_ADDRESS EfiMemoryBottom;
|
||||
EFI_PHYSICAL_ADDRESS EfiFreeMemoryTop;
|
||||
EFI_PHYSICAL_ADDRESS EfiFreeMemoryBottom;
|
||||
UINTN FreeMemory;
|
||||
} HOB_USAGE_DATA_HOB;
|
||||
|
||||
#pragma pack (pop)
|
||||
|
||||
#endif // _HOB_USAGE_DATA_HOB_H_
|
||||
|
|
@ -0,0 +1,244 @@
|
|||
/** @file
|
||||
This file contains definitions required for creation of
|
||||
Memory S3 Save data, Memory Info data and Memory Platform
|
||||
data hobs.
|
||||
|
||||
@copyright
|
||||
Copyright (c) 1999 - 2019, Intel Corporation. All rights reserved.<BR>
|
||||
|
||||
SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||
|
||||
@par Specification Reference:
|
||||
**/
|
||||
#ifndef _MEM_INFO_HOB_H_
|
||||
#define _MEM_INFO_HOB_H_
|
||||
|
||||
#pragma pack (push, 1)
|
||||
|
||||
extern EFI_GUID gSiMemoryS3DataGuid;
|
||||
extern EFI_GUID gSiMemoryInfoDataGuid;
|
||||
extern EFI_GUID gSiMemoryPlatformDataGuid;
|
||||
|
||||
#define MAX_NODE 1
|
||||
#define MAX_CH 2
|
||||
#define MAX_DIMM 2
|
||||
|
||||
///
|
||||
/// Host reset states from MRC.
|
||||
///
|
||||
#define WARM_BOOT 2
|
||||
|
||||
#define R_MC_CHNL_RANK_PRESENT 0x7C
|
||||
#define B_RANK0_PRS BIT0
|
||||
#define B_RANK1_PRS BIT1
|
||||
#define B_RANK2_PRS BIT4
|
||||
#define B_RANK3_PRS BIT5
|
||||
|
||||
// @todo remove and use the MdePkg\Include\Pi\PiHob.h
|
||||
#if !defined(_PEI_HOB_H_) && !defined(__PI_HOB_H__)
|
||||
#ifndef __HOB__H__
|
||||
typedef struct _EFI_HOB_GENERIC_HEADER {
|
||||
UINT16 HobType;
|
||||
UINT16 HobLength;
|
||||
UINT32 Reserved;
|
||||
} EFI_HOB_GENERIC_HEADER;
|
||||
|
||||
typedef struct _EFI_HOB_GUID_TYPE {
|
||||
EFI_HOB_GENERIC_HEADER Header;
|
||||
EFI_GUID Name;
|
||||
///
|
||||
/// Guid specific data goes here
|
||||
///
|
||||
} EFI_HOB_GUID_TYPE;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
///
|
||||
/// Defines taken from MRC so avoid having to include MrcInterface.h
|
||||
///
|
||||
|
||||
//
|
||||
// Matches MAX_SPD_SAVE define in MRC
|
||||
//
|
||||
#ifndef MAX_SPD_SAVE
|
||||
#define MAX_SPD_SAVE 29
|
||||
#endif
|
||||
|
||||
//
|
||||
// MRC version description.
|
||||
//
|
||||
typedef struct {
|
||||
UINT8 Major; ///< Major version number
|
||||
UINT8 Minor; ///< Minor version number
|
||||
UINT8 Rev; ///< Revision number
|
||||
UINT8 Build; ///< Build number
|
||||
} SiMrcVersion;
|
||||
|
||||
//
|
||||
// Matches MrcDimmSts enum in MRC
|
||||
//
|
||||
#ifndef DIMM_ENABLED
|
||||
#define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be detected.
|
||||
#endif
|
||||
#ifndef DIMM_DISABLED
|
||||
#define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of presence.
|
||||
#endif
|
||||
#ifndef DIMM_PRESENT
|
||||
#define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pair and it will be used.
|
||||
#endif
|
||||
#ifndef DIMM_NOT_PRESENT
|
||||
#define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank pair.
|
||||
#endif
|
||||
|
||||
//
|
||||
// Matches MrcBootMode enum in MRC
|
||||
//
|
||||
#ifndef __MRC_BOOT_MODE__
|
||||
#define __MRC_BOOT_MODE__ //The below values are originated from MrcCommonTypes.h
|
||||
#ifndef INT32_MAX
|
||||
#define INT32_MAX (0x7FFFFFFF)
|
||||
#endif //INT32_MAX
|
||||
typedef enum {
|
||||
bmCold, ///< Cold boot
|
||||
bmWarm, ///< Warm boot
|
||||
bmS3, ///< S3 resume
|
||||
bmFast, ///< Fast boot
|
||||
MrcBootModeMax, ///< MRC_BOOT_MODE enumeration maximum value.
|
||||
MrcBootModeDelim = INT32_MAX ///< This value ensures the enum size is consistent on both sides of the PPI.
|
||||
} MRC_BOOT_MODE;
|
||||
#endif //__MRC_BOOT_MODE__
|
||||
|
||||
//
|
||||
// Matches MrcDdrType enum in MRC
|
||||
//
|
||||
#ifndef MRC_DDR_TYPE_DDR4
|
||||
#define MRC_DDR_TYPE_DDR4 0
|
||||
#endif
|
||||
#ifndef MRC_DDR_TYPE_DDR3
|
||||
#define MRC_DDR_TYPE_DDR3 1
|
||||
#endif
|
||||
#ifndef MRC_DDR_TYPE_LPDDR3
|
||||
#define MRC_DDR_TYPE_LPDDR3 2
|
||||
#endif
|
||||
#ifndef MRC_DDR_TYPE_UNKNOWN
|
||||
#define MRC_DDR_TYPE_UNKNOWN 3
|
||||
#endif
|
||||
|
||||
#define MAX_PROFILE_NUM 4 // number of memory profiles supported
|
||||
#define MAX_XMP_PROFILE_NUM 2 // number of XMP profiles supported
|
||||
|
||||
//
|
||||
// DIMM timings
|
||||
//
|
||||
typedef struct {
|
||||
UINT32 tCK; ///< Memory cycle time, in femtoseconds.
|
||||
UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's command rate mode.
|
||||
UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS latency.
|
||||
UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time.
|
||||
UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time.
|
||||
UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time.
|
||||
UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time.
|
||||
UINT16 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval.
|
||||
UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
|
||||
UINT16 tRFCpb; ///< Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time.
|
||||
UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
|
||||
UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
|
||||
UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks.
|
||||
UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time.
|
||||
UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups.
|
||||
UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups.
|
||||
UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time.
|
||||
UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time.
|
||||
UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time.
|
||||
UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups.
|
||||
UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups.
|
||||
UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group.
|
||||
} MRC_CH_TIMING;
|
||||
|
||||
///
|
||||
/// Memory SMBIOS & OC Memory Data Hob
|
||||
///
|
||||
typedef struct {
|
||||
UINT8 Status; ///< See MrcDimmStatus for the definition of this field.
|
||||
UINT8 DimmId;
|
||||
UINT32 DimmCapacity; ///< DIMM size in MBytes.
|
||||
UINT16 MfgId;
|
||||
UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes
|
||||
UINT8 RankInDimm; ///< The number of ranks in this DIMM.
|
||||
UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation.
|
||||
UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation.
|
||||
UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation.
|
||||
UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation.
|
||||
UINT16 Speed; ///< The maximum capable speed of the device, in MHz
|
||||
} DIMM_INFO;
|
||||
|
||||
typedef struct {
|
||||
UINT8 Status; ///< Indicates whether this channel should be used.
|
||||
UINT8 ChannelId;
|
||||
UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel.
|
||||
MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values.
|
||||
DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output characteristics.
|
||||
} CHANNEL_INFO;
|
||||
|
||||
typedef struct {
|
||||
UINT8 Status; ///< Indicates whether this controller should be used.
|
||||
UINT16 DeviceId; ///< The PCI device id of this memory controller.
|
||||
UINT8 RevisionId; ///< The PCI revision id of this memory controller.
|
||||
UINT8 ChannelCount; ///< Number of valid channels that exist on the controller.
|
||||
CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions.
|
||||
} CONTROLLER_INFO;
|
||||
|
||||
typedef struct {
|
||||
UINT8 Revision;
|
||||
UINT16 DataWidth; ///< Data width, in bits, of this memory device
|
||||
/** As defined in SMBIOS 3.0 spec
|
||||
Section 7.18.2 and Table 75
|
||||
**/
|
||||
UINT8 MemoryType; ///< DDR type: DDR3, DDR4, or LPDDR3
|
||||
UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz)
|
||||
UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz)
|
||||
/** As defined in SMBIOS 3.0 spec
|
||||
Section 7.17.3 and Table 72
|
||||
**/
|
||||
UINT8 ErrorCorrectionType;
|
||||
|
||||
SiMrcVersion Version;
|
||||
BOOLEAN EccSupport;
|
||||
UINT8 MemoryProfile;
|
||||
UINT32 TotalPhysicalMemorySize;
|
||||
UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist.
|
||||
UINT8 XmpProfileEnable; ///< If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs.
|
||||
UINT8 Ratio;
|
||||
UINT8 RefClk;
|
||||
UINT32 VddVoltage[MAX_PROFILE_NUM];
|
||||
CONTROLLER_INFO Controller[MAX_NODE];
|
||||
} MEMORY_INFO_DATA_HOB;
|
||||
|
||||
/**
|
||||
Memory Platform Data Hob
|
||||
|
||||
<b>Revision 1:</b>
|
||||
- Initial version.
|
||||
**/
|
||||
typedef struct {
|
||||
UINT8 Revision;
|
||||
UINT8 Reserved[3];
|
||||
UINT32 BootMode;
|
||||
UINT32 TsegSize;
|
||||
UINT32 TsegBase;
|
||||
UINT32 PrmrrSize;
|
||||
UINT32 PrmrrBase;
|
||||
UINT32 GttBase;
|
||||
UINT32 MmioSize;
|
||||
UINT32 PciEBaseAddress;
|
||||
} MEMORY_PLATFORM_DATA;
|
||||
|
||||
typedef struct {
|
||||
EFI_HOB_GUID_TYPE EfiHobGuidType;
|
||||
MEMORY_PLATFORM_DATA Data;
|
||||
UINT8 *Buffer;
|
||||
} MEMORY_PLATFORM_DATA_HOB;
|
||||
|
||||
#pragma pack (pop)
|
||||
|
||||
#endif // _MEM_INFO_HOB_H_
|
||||
|
|
@ -0,0 +1,49 @@
|
|||
/** @file
|
||||
Header file for SMBIOS Cache Info HOB
|
||||
|
||||
@copyright
|
||||
Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>
|
||||
|
||||
SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||
|
||||
System Management BIOS (SMBIOS) Reference Specification v3.1.0
|
||||
dated 2016-Nov-16 (DSP0134)
|
||||
http://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.1.0.pdf
|
||||
**/
|
||||
|
||||
#ifndef _SMBIOS_CACHE_INFO_HOB_H_
|
||||
#define _SMBIOS_CACHE_INFO_HOB_H_
|
||||
|
||||
#include <Uefi.h>
|
||||
#include <Pi/PiHob.h>
|
||||
|
||||
#pragma pack(1)
|
||||
///
|
||||
/// SMBIOS Cache Info HOB Structure
|
||||
///
|
||||
typedef struct {
|
||||
UINT16 ProcessorSocketNumber;
|
||||
UINT16 NumberOfCacheLevels; ///< Based on Number of Cache Types L1/L2/L3
|
||||
UINT8 SocketDesignationStrIndex; ///< String Index in the string Buffer. Example "L1-CACHE"
|
||||
UINT16 CacheConfiguration; ///< Format defined in SMBIOS Spec v3.1 Section7.8 Table36
|
||||
UINT16 MaxCacheSize; ///< Format defined in SMBIOS Spec v3.1 Section7.8.1
|
||||
UINT16 InstalledSize; ///< Format defined in SMBIOS Spec v3.1 Section7.8.1
|
||||
UINT16 SupportedSramType; ///< Format defined in SMBIOS Spec v3.1 Section7.8.2
|
||||
UINT16 CurrentSramType; ///< Format defined in SMBIOS Spec v3.1 Section7.8.2
|
||||
UINT8 CacheSpeed; ///< Cache Speed in nanoseconds. 0 if speed is unknown.
|
||||
UINT8 ErrorCorrectionType; ///< ENUM Format defined in SMBIOS Spec v3.1 Section 7.8.3
|
||||
UINT8 SystemCacheType; ///< ENUM Format defined in SMBIOS Spec v3.1 Section 7.8.4
|
||||
UINT8 Associativity; ///< ENUM Format defined in SMBIOS Spec v3.1 Section 7.8.5
|
||||
//
|
||||
// Add for smbios 3.1.0
|
||||
//
|
||||
UINT32 MaximumCacheSize2; ///< Format defined in SMBIOS Spec v3.1 Section7.8.1
|
||||
UINT32 InstalledSize2; ///< Format defined in SMBIOS Spec v3.1 Section7.8.1
|
||||
/**
|
||||
String Buffer - each string terminated by NULL "0x00"
|
||||
String buffer terminated by double NULL "0x0000"
|
||||
**/
|
||||
} SMBIOS_CACHE_INFO;
|
||||
#pragma pack()
|
||||
|
||||
#endif // _SMBIOS_CACHE_INFO_HOB_H_
|
||||
|
|
@ -0,0 +1,60 @@
|
|||
/** @file
|
||||
Header file for SMBIOS Processor Info HOB
|
||||
|
||||
@copyright
|
||||
Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>
|
||||
|
||||
SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||
|
||||
System Management BIOS (SMBIOS) Reference Specification v3.1.0
|
||||
dated 2016-Nov-16 (DSP0134)
|
||||
http://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.1.0.pdf
|
||||
**/
|
||||
|
||||
#ifndef _SMBIOS_PROCESSOR_INFO_HOB_H_
|
||||
#define _SMBIOS_PROCESSOR_INFO_HOB_H_
|
||||
|
||||
#include <Uefi.h>
|
||||
#include <Pi/PiHob.h>
|
||||
|
||||
#pragma pack(1)
|
||||
///
|
||||
/// SMBIOS Processor Info HOB Structure
|
||||
///
|
||||
typedef struct {
|
||||
UINT16 TotalNumberOfSockets;
|
||||
UINT16 CurrentSocketNumber;
|
||||
UINT8 ProcessorType; ///< ENUM defined in SMBIOS Spec v3.1 Section 7.5.1
|
||||
/** This info is used for both ProcessorFamily and ProcessorFamily2 fields
|
||||
See ENUM defined in SMBIOS Spec v3.1 Section 7.5.2
|
||||
**/
|
||||
UINT16 ProcessorFamily;
|
||||
UINT8 ProcessorManufacturerStrIndex; ///< Index of the String in the String Buffer
|
||||
UINT64 ProcessorId; ///< ENUM defined in SMBIOS Spec v3.1 Section 7.5.3
|
||||
UINT8 ProcessorVersionStrIndex; ///< Index of the String in the String Buffer
|
||||
UINT8 Voltage; ///< Format defined in SMBIOS Spec v3.1 Section 7.5.4
|
||||
UINT16 ExternalClockInMHz; ///< External Clock Frequency. Set to 0 if unknown.
|
||||
UINT16 CurrentSpeedInMHz; ///< Snapshot of current processor speed during boot
|
||||
UINT8 Status; ///< Format defined in the SMBIOS Spec v3.1 Table 21
|
||||
UINT8 ProcessorUpgrade; ///< ENUM defined in SMBIOS Spec v3.1 Section 7.5.5
|
||||
/** This info is used for both CoreCount & CoreCount2 fields
|
||||
See detailed description in SMBIOS Spec v3.1 Section 7.5.6
|
||||
**/
|
||||
UINT16 CoreCount;
|
||||
/** This info is used for both CoreEnabled & CoreEnabled2 fields
|
||||
See detailed description in SMBIOS Spec v3.1 Section 7.5.7
|
||||
**/
|
||||
UINT16 EnabledCoreCount;
|
||||
/** This info is used for both ThreadCount & ThreadCount2 fields
|
||||
See detailed description in SMBIOS Spec v3.1 Section 7.5.8
|
||||
**/
|
||||
UINT16 ThreadCount;
|
||||
UINT16 ProcessorCharacteristics; ///< Format defined in SMBIOS Spec v3.1 Section 7.5.9
|
||||
/**
|
||||
String Buffer - each string terminated by NULL "0x00"
|
||||
String buffer terminated by double NULL "0x0000"
|
||||
**/
|
||||
} SMBIOS_PROCESSOR_INFO;
|
||||
#pragma pack()
|
||||
|
||||
#endif // _SMBIOS_PROCESSOR_INFO_HOB_H_
|
||||
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Reference in New Issue