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Kaby Lake FSP 3.7.1

This commit is contained in:
ClientSysFWGit 2019-05-15 19:57:05 -07:00
parent ad0ddde9d6
commit 05ff0abc25
12 changed files with 30903 additions and 30821 deletions
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KabylakeFspBinPkg/Docs/Kabylake_FSP_Integration_Guide.chm
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KabylakeFspBinPkg/Docs/Kabylake_FSP_Integration_Guide.pdf
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KabylakeFspBinPkg/Fsp.bsf
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@ -2,7 +2,7 @@
Boot Setting File for Platform Configuration.
@copyright
Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -60,7 +60,8 @@ StructDef
Skip 2 bytes
$gKabylakeFspPkgTokenSpaceGuid_SmbusEnable 1 bytes $_DEFAULT_ = 0x01
$gKabylakeFspPkgTokenSpaceGuid_EnableTraceHub 1 bytes $_DEFAULT_ = 0x00
Skip 60 bytes
$gKabylakeFspPkgTokenSpaceGuid_DpSscMarginEnable 1 bytes $_DEFAULT_ = 0x00
Skip 59 bytes
$gKabylakeFspPkgTokenSpaceGuid_IgdDvmt50PreAlloc 1 bytes $_DEFAULT_ = 0x01
$gKabylakeFspPkgTokenSpaceGuid_InternalGfx 1 bytes $_DEFAULT_ = 0x01
$gKabylakeFspPkgTokenSpaceGuid_ApertureSize 1 bytes $_DEFAULT_ = 0x01
@ -241,7 +242,7 @@ StructDef
$gSiPkgTokenSpaceGuid_PcdSerialIoUartNumber 1 bytes $_DEFAULT_ = 0x02
$gSiPkgTokenSpaceGuid_PcdIsaSerialUartBase 1 bytes $_DEFAULT_ = 0x00
$gKabylakeFspPkgTokenSpaceGuid_PchPmPciePllSsc 1 bytes $_DEFAULT_ = 0xFF
$gKabylakeFspPkgTokenSpaceGuid_PeciC10Reset 1 bytes $_DEFAULT_ = 0x00
$gKabylakeFspPkgTokenSpaceGuid_PeciC10Reset 1 bytes $_DEFAULT_ = 0x1
$gKabylakeFspPkgTokenSpaceGuid_PeciSxReset 1 bytes $_DEFAULT_ = 0x00
$gKabylakeFspPkgTokenSpaceGuid_PcdSerialDebugBaudRate 1 bytes $_DEFAULT_ = 0x07
$gKabylakeFspPkgTokenSpaceGuid_PcdSerialDebugLevel 1 bytes $_DEFAULT_ = 0x03
@ -381,7 +382,8 @@ StructDef
$gKabylakeFspPkgTokenSpaceGuid_WatchDogTimerBios 2 bytes $_DEFAULT_ = 0x0
$gKabylakeFspPkgTokenSpaceGuid_AmtSolEnabled 1 bytes $_DEFAULT_ = 0x0
$gKabylakeFspPkgTokenSpaceGuid_PcieRpClkSrcNumber 24 bytes $_DEFAULT_ = 0x02, 0x1f, 0x1f, 0x1f, 0x03, 0x01, 0x1f, 0x1f, 0x05, 0x04, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f
Skip 139 bytes
$gKabylakeFspPkgTokenSpaceGuid_PcieRpForceClkDisableWhenRpDisable 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
Skip 115 bytes
$gKabylakeFspPkgTokenSpaceGuid_DefaultSvid 2 bytes $_DEFAULT_ = 0x8086
$gKabylakeFspPkgTokenSpaceGuid_DefaultSid 2 bytes $_DEFAULT_ = 0x2015
$gKabylakeFspPkgTokenSpaceGuid_CridEnable 1 bytes $_DEFAULT_ = 0x0
@ -398,9 +400,10 @@ StructDef
$gKabylakeFspPkgTokenSpaceGuid_X2ApicOptOut 1 bytes $_DEFAULT_ = 0x0
Skip 1 bytes
$gKabylakeFspPkgTokenSpaceGuid_VtdBaseAddress 8 bytes $_DEFAULT_ = 0x00,0x00,0xD9,0xFE,0x00,0x10,0xD9,0xFE
Skip 19 bytes
$gKabylakeFspPkgTokenSpaceGuid_SaPostMemProductionRsvd 16 bytes $_DEFAULT_ = 0x00
Skip 7 bytes
$gPlatformFspPkgTokenSpaceGuid_ProgramGtChickenBits 1 bytes $_DEFAULT_ = 0xE
Skip 18 bytes
$gKabylakeFspPkgTokenSpaceGuid_SaPostMemProductionRsvd 15 bytes $_DEFAULT_ = 0x00
Skip 8 bytes
$gKabylakeFspPkgTokenSpaceGuid_Psi3Enable 5 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01
$gKabylakeFspPkgTokenSpaceGuid_Psi4Enable 5 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01
$gKabylakeFspPkgTokenSpaceGuid_ImonSlope 5 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00
@ -1575,6 +1578,9 @@ Page "Sunrise Point PCH"
EditNum $gKabylakeFspPkgTokenSpaceGuid_PcieRpClkSrcNumber, "Configure CLKSRC Number", HEX,
Help "Configure Root Port CLKSRC Number. Each value in arrary can be between 0-6 for valid clock numbers or 0x1F for an invalid number. One byte for each port, byte0 for port1, byte1 for port2, and so on."
"Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
EditNum $gKabylakeFspPkgTokenSpaceGuid_PcieRpForceClkDisableWhenRpDisable, "Force Disable clock ", HEX,
Help "Disables clock even if link is inactive default value is 0"
"Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
EditNum $gKabylakeFspPkgTokenSpaceGuid_DefaultSvid, "Subsystem Vendor ID for SA devices", HEX,
Help "Subsystem ID that will be programmed to SA devices: Default SubSystemVendorId=0x8086"
"Valid range: 0x00 ~ 0xFFFF"
@ -1612,6 +1618,9 @@ Page "Sunrise Point PCH"
EditNum $gKabylakeFspPkgTokenSpaceGuid_VtdBaseAddress, "Base addresses for VT-d function MMIO access", HEX,
Help "Base addresses for VT-d MMIO access per VT-d engine"
"Valid range: 0 ~ 0xFFFFFFFF"
EditNum $gPlatformFspPkgTokenSpaceGuid_ProgramGtChickenBits, "Program GT Chicken bits", HEX,
Help "Progarm the GT chicken bits in GTTMMADR + 0xD00 BITS [3:1]"
"Valid range: 0 ~ 0xFFFFFFFF"
Combo $gKabylakeFspPkgTokenSpaceGuid_SaPostMemProductionRsvd, "SaPostMemProductionRsvd", &EN_DIS,
Help "Reserved for SA Post-Mem Production"
EditNum $gKabylakeFspPkgTokenSpaceGuid_Psi3Enable, "Power State 3 enable/disable", HEX,
@ -1947,7 +1956,7 @@ Page "Sunrise Point PCH"
Help "Specifies the Pcie Pll Spread Spectrum Percentage. The default is 0xFF: AUTO - No BIOS override."
"Valid range: 0x0 ~ 0xFF"
Combo $gKabylakeFspPkgTokenSpaceGuid_PeciC10Reset, "Enable or Disable Peci C10 Reset command", &EN_DIS,
Help "Enable or Disable Peci C10 Reset command; <b>0: Disable;</b> 1: Enable."
Help "Enable or Disable Peci C10 Reset command; 0: Disable; <b>1: Enable.</b>"
Combo $gKabylakeFspPkgTokenSpaceGuid_PeciSxReset, "Enable or Disable Peci Sx Reset command", &EN_DIS,
Help "Enable or Disable Peci Sx Reset command; <b>0: Disable;</b> 1: Enable."
Combo $gKabylakeFspPkgTokenSpaceGuid_PcdSerialDebugBaudRate, "PcdSerialDebugBaudRate", &gKabylakeFspPkgTokenSpaceGuid_PcdSerialDebugBaudRate,
@ -2284,7 +2293,7 @@ Page "Sunrise Point PCH"
Combo $gKabylakeFspPkgTokenSpaceGuid_SerialIoGpio, "Enable Pch Serial IO GPIO", &EN_DIS,
Help "Determines if enable Serial IO GPIO."
EditNum $gKabylakeFspPkgTokenSpaceGuid_SerialIoI2cVoltage, "IO voltage for I2C controllers", HEX,
Help "Selects the IO voltage for I2C controllers, 0: PchSerialIoIs33V, 1: PchSerialIoIs18V."
Help "Selects the IO voltage for I2C controllers, 0: PchSerialIoIs33V, 1: PchSerialIoIs18V. Note: I2C 2/3/4/5 does not support 3.3V (only 1.8V), due to GPIO GPP_F limitation"
"Valid range: 0x00 ~ 0xFFFFFFFFFFFF"
EditNum $gKabylakeFspPkgTokenSpaceGuid_SerialIoSpiCsPolarity, "SPI ChipSelect signal polarity", HEX,
Help "Selects SPI ChipSelect signal polarity."
@ -2858,6 +2867,8 @@ Page "Memory Reference Code"
Help "Enable/disable SMBus controller."
Combo $gKabylakeFspPkgTokenSpaceGuid_EnableTraceHub, "Enable Trace Hub", &EN_DIS,
Help "Enable/disable Trace Hub function."
Combo $gKabylakeFspPkgTokenSpaceGuid_DpSscMarginEnable, "DpSscMarginEnable", &EN_DIS,
Help "Enable/Disable. 0: Disable, Use default DisplayPort SSC modulation range 0.5% down spread, 1: Enable DisplayPort SSC range reduction. Note this should only be used on systems that exceeds allowed SSC modulation range as defined in VESA's spec"
Combo $gKabylakeFspPkgTokenSpaceGuid_IgdDvmt50PreAlloc, "Internal Graphics Pre-allocated Memory", &gKabylakeFspPkgTokenSpaceGuid_IgdDvmt50PreAlloc,
Help "Size of memory preallocated for internal graphics."
Combo $gKabylakeFspPkgTokenSpaceGuid_InternalGfx, "Internal Graphics", &EN_DIS,

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KabylakeFspBinPkg/FspPcds.dsc Normal file
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@ -0,0 +1,10 @@
## @file
# FSP description for DynamicEx PCDs.
#
# @copyright
# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
# @par Specification
##

2
KabylakeFspBinPkg/Include/FspUpd.h
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@ -1,7 +1,7 @@
/** @file
@copyright
Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:

16
KabylakeFspBinPkg/Include/FspmUpd.h
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@ -1,7 +1,7 @@
/** @file
@copyright
Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
@ -186,9 +186,17 @@ typedef struct {
**/
UINT8 EnableTraceHub;
/** Offset 0x00A7
/** Offset 0x00A7 - DpSscMarginEnable
Enable/Disable. 0: Disable, Use default DisplayPort SSC modulation range 0.5% down
spread, 1: Enable DisplayPort SSC range reduction. Note this should only be used
on systems that exceeds allowed SSC modulation range as defined in VESA's spec
$EN_DIS
**/
UINT8 UnusedUpdSpace2[60];
UINT8 DpSscMarginEnable;
/** Offset 0x00A8
**/
UINT8 UnusedUpdSpace2[59];
/** Offset 0x00E3 - Internal Graphics Pre-allocated Memory
Size of memory preallocated for internal graphics.
@ -1202,7 +1210,7 @@ typedef struct {
UINT8 PchPmPciePllSsc;
/** Offset 0x0510 - Enable or Disable Peci C10 Reset command
Enable or Disable Peci C10 Reset command; <b>0: Disable;</b> 1: Enable.
Enable or Disable Peci C10 Reset command; 0: Disable; <b>1: Enable.</b>
$EN_DIS
**/
UINT8 PeciC10Reset;

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KabylakeFspBinPkg/Include/FspsUpd.h
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@ -1,7 +1,7 @@
/** @file
@copyright
Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
@ -459,9 +459,14 @@ typedef struct {
**/
UINT8 PcieRpClkSrcNumber[24];
/** Offset 0x0175
/** Offset 0x0175 - Force Disable clock
Disables clock even if link is inactive default value is 0
**/
UINT8 UnusedUpdSpace6[139];
UINT8 PcieRpForceClkDisableWhenRpDisable[24];
/** Offset 0x018D
**/
UINT8 UnusedUpdSpace6[115];
/** Offset 0x0200 - Subsystem Vendor ID for SA devices
Subsystem ID that will be programmed to SA devices: Default SubSystemVendorId=0x8086
@ -552,19 +557,24 @@ typedef struct {
**/
UINT32 VtdBaseAddress[2];
/** Offset 0x0224
/** Offset 0x0224 - Program GT Chicken bits
Progarm the GT chicken bits in GTTMMADR + 0xD00 BITS [3:1]
**/
UINT8 UnusedUpdSpace8[19];
UINT8 ProgramGtChickenBits;
/** Offset 0x0225
**/
UINT8 UnusedUpdSpace8[18];
/** Offset 0x0237 - SaPostMemProductionRsvd
Reserved for SA Post-Mem Production
$EN_DIS
**/
UINT8 SaPostMemProductionRsvd[16];
UINT8 SaPostMemProductionRsvd[15];
/** Offset 0x0247
/** Offset 0x0246
**/
UINT8 UnusedUpdSpace9[7];
UINT8 UnusedUpdSpace9[8];
/** Offset 0x024E - Power State 3 enable/disable
PCODE MMIO Mailbox: Power State 3 enable/disable; 0: Disable; <b>1: Enable</b>.
@ -1732,6 +1742,7 @@ typedef struct {
/** Offset 0x06CB - IO voltage for I2C controllers
Selects the IO voltage for I2C controllers, 0: PchSerialIoIs33V, 1: PchSerialIoIs18V.
Note: I2C 2/3/4/5 does not support 3.3V (only 1.8V), due to GPIO GPP_F limitation
**/
UINT8 SerialIoI2cVoltage[6];

2
KabylakeFspBinPkg/Include/FsptUpd.h
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@ -1,7 +1,7 @@
/** @file
@copyright
Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:

30
KabylakeFspBinPkg/KabylakeFspBinPkg.dec
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@ -1,34 +1,10 @@
## @file
# Component description file for Kabylake Fsp Bin package.
# Component description file for KabyLake Fsp Bin package.
#
# @copyright
# INTEL CONFIDENTIAL
# Copyright 2015 - 2016 Intel Corporation.
# Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>
#
# The source code contained or described herein and all documents related to the
# source code ("Material") are owned by Intel Corporation or its suppliers or
# licensors. Title to the Material remains with Intel Corporation or its suppliers
# and licensors. The Material may contain trade secrets and proprietary and
# confidential information of Intel Corporation and its suppliers and licensors,
# and is protected by worldwide copyright and trade secret laws and treaty
# provisions. No part of the Material may be used, copied, reproduced, modified,
# published, uploaded, posted, transmitted, distributed, or disclosed in any way
# without Intel's prior express written permission.
#
# No license under any patent, copyright, trade secret or other intellectual
# property right is granted to or conferred upon you by disclosure or delivery
# of the Materials, either expressly, by implication, inducement, estoppel or
# otherwise. Any license under such intellectual property rights must be
# express and approved by Intel in writing.
#
# Unless otherwise agreed by Intel in writing, you may not remove or alter
# this notice or any other notice embedded in Materials by Intel or
# Intel's suppliers or licensors in any way.
#
# This file contains an 'Intel Peripheral Driver' and is uniquely identified as
# "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
# the terms of your license agreement with Intel or your vendor. This file may
# be modified by the user, subject to additional terms of the license agreement.
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
# @par Specification
##

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KabylakeFspBinPkg/SampleCode/Vbt/Vbt.bsf
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@ -213,6 +213,7 @@ $Int_LFP_AUX_Channel 1 byte ; eDP AUX channel
SKIP 11 bytes ; Skip 11 bytes
$Int_LFP_Dp_Boost_Magnitude 4 bits ; eDP IBoost magnitude level
SKIP 4 bits ; Skip HDMI IBoost magnitude level field for LFP struct
SKIP 1 byte ; Skip DP Max link rate for EDP.
; Internal EFP (HDMI/DP) Data structure
; Device 1
@ -267,6 +268,7 @@ $EFP1_DP_Port_Trace_Length 4 bits ; DP port trace length for
SKIP 3 bytes ; GPIO resource ID and GPIO number
$Int_EFP1_Dp_Boost_Magnitude 4 bits ; DP IBoost magnitude level
$Int_EFP1_Hdmi_Boost_Magnitude 4 bits ; HDMI IBoost magnitude level
SKIP 1 byte ; Skip DP Max link rate
; Device 2
SKIP 2 bytes ; Skip Device Handle
@ -320,6 +322,7 @@ $EFP2_DP_Port_Trace_Length 4 bits ; DP port trace length for
SKIP 3 bytes ; GPIO resource ID and GPIO number
$Int_EFP2_Dp_Boost_Magnitude 4 bits ; DP IBoost magnitude level
$Int_EFP2_Hdmi_Boost_Magnitude 4 bits ; HDMI IBoost magnitude level
SKIP 1 byte ; Skip DP Max link rate.
; Device 3
SKIP 2 bytes ; Skip Device Handle
@ -373,6 +376,7 @@ $EFP3_DP_Port_Trace_Length 4 bits ; DP port trace length for
SKIP 3 bytes ; GPIO resource ID and GPIO number
$Int_EFP3_Dp_Boost_Magnitude 4 bits ; DP IBoost magnitude level
$Int_EFP3_Hdmi_Boost_Magnitude 4 bits ; HDMI IBoost magnitude level
SKIP 1 byte ; Skip DP Max link rate
; Device 4
SKIP 2 bytes ; Skip Device Handle
@ -426,10 +430,11 @@ $EFP4_DP_Port_Trace_Length 4 bits ; DP port trace length for
SKIP 3 bytes ; GPIO resource ID and GPIO number
$Int_EFP4_Dp_Boost_Magnitude 4 bits ; DP IBoost magnitude level
$Int_EFP4_Hdmi_Boost_Magnitude 4 bits ; HDMI IBoost magnitude level
SKIP 1 byte ; Skip DP Max link rate
SKIP 38 bytes ; Skip device data structure
SKIP 38 bytes ; Skip device data structure
SKIP 38 bytes ; Skip device data structure
SKIP 39 bytes ; Skip device data structure
SKIP 39 bytes ; Skip device data structure
SKIP 39 bytes ; Skip device data structure
;==============================================================================
; Block 3 - Original Display Toggle List
@ -2870,6 +2875,7 @@ List &Pwm_Source_List
Selection 0x2, "PWM From Display Engine"
; Selection 0x3, "PWM From LCD Panel"
Selection 0x4, "Panel driver interface (OLED)"
Selection 0x5, "VESA eDP AUX Interface"
EndList
List &Dp_Port_Trace_Length_List
@ -2892,7 +2898,7 @@ EndInfoBlock
;------------------------------------------------------------------------------
Page "VBT Information"
Title "PLATFORM : Skylake/Kabylake"
Title "VBT version: 212"
Title "VBT version: 221"
#IF $LVDS_Config == 3
Title "Supported LFP type: eDP"