coreboot/src/device/dram/Makefile.inc

mirror of https://review.coreboot.org/coreboot.git
romstage-y += ddr4.c ddr3.c ddr2.c ddr_common.c

ramstage-y += ddr4.c ddr3.c ddr2.c ddr_common.c spd.c
	`romstage-y += ddr4.c ddr3.c ddr2.c ddr_common.c`

	`ramstage-y += ddr4.c ddr3.c ddr2.c ddr_common.c spd.c`