136 lines
3.9 KiB
C
136 lines
3.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <cpu/x86/smm.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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#include <acpi/acpi.h>
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#include <stddef.h>
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#include <soc/iomap.h>
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#include <soc/iosf.h>
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#include <soc/pci_devs.h>
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#include <soc/ramstage.h>
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/* Host Memory Map:
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*
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* +--------------------------+ BMBOUND_HI
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* | Usable DRAM |
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* +--------------------------+ 4GiB
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* | PCI Address Space |
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* +--------------------------+ BMBOUND
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* | TPM |
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* +--------------------------+ IMR2
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* | TXE |
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* +--------------------------+ IMR1
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* | iGD |
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* +--------------------------+
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* | GTT |
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* +--------------------------+ SMMRRH, IRM0
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* | TSEG |
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* +--------------------------+ SMMRRL
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* | Usable DRAM |
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* +--------------------------+ 0
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*
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* Note that there are really only a few regions that need to enumerated w.r.t.
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* coreboot's resource model:
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*
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* +--------------------------+ BMBOUND_HI
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* | Cacheable/Usable |
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* +--------------------------+ 4GiB
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*
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* +--------------------------+ BMBOUND
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* | Uncacheable/Reserved |
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* +--------------------------+ SMMRRH
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* | Cacheable/Reserved |
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* +--------------------------+ SMMRRL
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* | Cacheable/Usable |
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* +--------------------------+ 0
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*/
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#define RES_IN_KiB(r) ((r) >> 10)
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uint32_t nc_read_top_of_low_memory(void)
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{
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static uint32_t tolm;
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if (tolm)
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return tolm;
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tolm = iosf_bunit_read(BUNIT_BMBOUND) & ~((1 << 27) - 1);
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return tolm;
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}
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static void nc_read_resources(struct device *dev)
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{
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unsigned long mmconf;
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unsigned long bmbound;
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unsigned long bmbound_hi;
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unsigned long smmrrh;
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unsigned long smmrrl;
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unsigned long base_k, size_k;
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const unsigned long four_gig_kib = (4 << (30 - 10));
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int index = 0;
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/* Read standard PCI resources. */
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pci_dev_read_resources(dev);
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/* PCIe memory-mapped config space access - 256 MiB. */
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mmconf = iosf_bunit_read(BUNIT_MMCONF_REG) & ~((1 << 28) - 1);
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mmio_resource(dev, BUNIT_MMCONF_REG, RES_IN_KiB(mmconf), 256 * 1024);
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/* 0 -> 0xa0000 */
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base_k = RES_IN_KiB(0);
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size_k = RES_IN_KiB(0xa0000) - base_k;
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ram_resource(dev, index++, base_k, size_k);
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/* The SMMRR registers are 1MiB granularity with smmrrh being
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* inclusive of the SMM region. */
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smmrrl = (iosf_bunit_read(BUNIT_SMRRL) & 0xffff) << 10;
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smmrrh = ((iosf_bunit_read(BUNIT_SMRRH) & 0xffff) + 1) << 10;
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/* 0xc0000 -> smrrl - cacheable and usable */
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base_k = RES_IN_KiB(0xc0000);
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size_k = smmrrl - base_k;
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ram_resource(dev, index++, base_k, size_k);
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if (smmrrh > smmrrl)
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reserved_ram_resource(dev, index++, smmrrl, smmrrh - smmrrl);
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/* All address space between bmbound and smmrrh is unusable. */
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bmbound = RES_IN_KiB(nc_read_top_of_low_memory());
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mmio_resource(dev, index++, smmrrh, bmbound - smmrrh);
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/* The BMBOUND_HI register matches register bits of 31:24 with address
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* bits of 35:28. Therefore, shift register to align properly. */
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bmbound_hi = iosf_bunit_read(BUNIT_BMBOUND_HI) & ~((1 << 24) - 1);
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bmbound_hi = RES_IN_KiB(bmbound_hi) << 4;
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if (bmbound_hi > four_gig_kib)
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ram_resource(dev, index++, four_gig_kib,
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bmbound_hi - four_gig_kib);
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/* Reserve everything between A segment and 1MB:
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*
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* 0xa0000 - 0xbffff: legacy VGA
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* 0xc0000 - 0xfffff: RAM
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*/
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mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10);
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reserved_ram_resource(dev, index++, (0xc0000 >> 10),
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(0x100000 - 0xc0000) >> 10);
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if (CONFIG(CHROMEOS))
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chromeos_reserve_ram_oops(dev, index++);
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}
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static struct device_operations nc_ops = {
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.read_resources = nc_read_resources,
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.acpi_fill_ssdt = generate_cpu_entries,
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.ops_pci = &soc_pci_ops,
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};
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static const struct pci_driver nc_driver __pci_driver = {
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.ops = &nc_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = SOC_DEVID,
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};
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