515 lines
22 KiB
C
515 lines
22 KiB
C
/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#define ME_NOT_PRESENT 0
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#define ME_FOUND_NOTHING 1
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#define ME_FOUND_SOMETHING_NOT_SURE 2
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#define ME_CAN_DISABLE_IF_PRESENT 3
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#define ME_PRESENT_CAN_DISABLE 4
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#define ME_PRESENT_CANNOT_DISABLE 5
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#define INTELMETOOL_VERSION "1.1"
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#define GPLV2COPYRIGHT \
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"This program is free software: you can redistribute it and/or modify\n" \
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"it under the terms of the GNU General Public License as published by\n" \
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"the Free Software Foundation, version 2 of the License.\n\n" \
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"This program is distributed in the hope that it will be useful,\n" \
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"but WITHOUT ANY WARRANTY; without even the implied warranty of\n" \
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"MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n" \
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"GNU General Public License for more details.\n\n"
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#if defined(__GLIBC__)
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#include <sys/io.h>
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#endif
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#if (defined(__MACH__) && defined(__APPLE__))
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/* DirectHW is available here: https://www.coreboot.org/DirectHW */
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#define __DARWIN__
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#include <DirectHW/DirectHW.h>
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#endif
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#ifdef __NetBSD__
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#include <pciutils/pci.h>
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#else
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#include <pci/pci.h>
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#endif
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#define CNRM "\x1B[0m"
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#define CRED "\x1B[31m"
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#define CGRN "\x1B[32m"
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#define CYEL "\x1B[33m"
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#define CBLU "\x1B[34m"
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#define CMAG "\x1B[35m"
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#define CCYN "\x1B[36m"
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#define CWHT "\x1B[37m"
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#define RESET "\033[0m"
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#define CPU_ID_SIZE 13
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#define FD2 0x3428
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#define ME_COMMAND_DELAY 10000
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#define ME_MESSAGE_LEN 256
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extern int debug;
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static inline void print_cap(const char *name, int state)
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{
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printf("ME Capability: %-30s : %s\n",
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name, state ? CRED "ON" RESET : CGRN "OFF" RESET);
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}
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#define PCI_VENDOR_ID_INTEL 0x8086
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// Chipset does not have ME
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#define PCI_DEVICE_ID_INTEL_82810 0x7120
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#define PCI_DEVICE_ID_INTEL_82810_DC 0x7122
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#define PCI_DEVICE_ID_INTEL_82810E_DC 0x7124
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#define PCI_DEVICE_ID_INTEL_82830M 0x3575
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#define PCI_DEVICE_ID_INTEL_82845 0x1a30
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#define PCI_DEVICE_ID_INTEL_82865 0x2570
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#define PCI_DEVICE_ID_INTEL_82915 0x2580
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#define PCI_DEVICE_ID_INTEL_82945P 0x2770
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#define PCI_DEVICE_ID_INTEL_82945GM 0x27a0
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#define PCI_DEVICE_ID_INTEL_82945GSE 0x27ac
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#define PCI_DEVICE_ID_INTEL_82X58 0x3405
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#define PCI_DEVICE_ID_INTEL_ATOM_DXXX 0xa000
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#define PCI_DEVICE_ID_INTEL_I63XX 0x2670
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#define PCI_DEVICE_ID_INTEL_I5000X 0x25c0
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#define PCI_DEVICE_ID_INTEL_I5000Z 0x25d0
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#define PCI_DEVICE_ID_INTEL_I5000V 0x25d4
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#define PCI_DEVICE_ID_INTEL_I5000P 0x25d8
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#define PCI_DEVICE_ID_INTEL_82443LX 0x7180
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#define PCI_DEVICE_ID_INTEL_82443BX 0x7190
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#define PCI_DEVICE_ID_INTEL_82443BX_NO_AGP 0x7192
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#define PCI_DEVICE_ID_INTEL_82371XX 0x7110
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#define PCI_DEVICE_ID_INTEL_ICH 0x2410
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#define PCI_DEVICE_ID_INTEL_ICH0 0x2420
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#define PCI_DEVICE_ID_INTEL_ICH2 0x2440
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#define PCI_DEVICE_ID_INTEL_ICH4 0x24c0
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#define PCI_DEVICE_ID_INTEL_ICH4M 0x24cc
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#define PCI_DEVICE_ID_INTEL_ICH5 0x24d0
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#define PCI_DEVICE_ID_INTEL_ICH6 0x2640
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#define PCI_DEVICE_ID_INTEL_ICH7DH 0x27b0
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#define PCI_DEVICE_ID_INTEL_ICH7 0x27b8
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#define PCI_DEVICE_ID_INTEL_ICH7M 0x27b9
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#define PCI_DEVICE_ID_INTEL_ICH7MDH 0x27bd
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#define PCI_DEVICE_ID_INTEL_NM10 0x27bc
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#define PCI_DEV_NO_ME(x) ( \
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((x) == PCI_DEVICE_ID_INTEL_82810) || \
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((x) == PCI_DEVICE_ID_INTEL_82810_DC) || \
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((x) == PCI_DEVICE_ID_INTEL_82810E_DC) || \
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((x) == PCI_DEVICE_ID_INTEL_82830M) || \
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((x) == PCI_DEVICE_ID_INTEL_82845) || \
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((x) == PCI_DEVICE_ID_INTEL_82865) || \
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((x) == PCI_DEVICE_ID_INTEL_82915) || \
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((x) == PCI_DEVICE_ID_INTEL_82945P) || \
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((x) == PCI_DEVICE_ID_INTEL_82945GM) || \
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((x) == PCI_DEVICE_ID_INTEL_82945GSE) || \
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((x) == PCI_DEVICE_ID_INTEL_82X58) || \
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((x) == PCI_DEVICE_ID_INTEL_ATOM_DXXX) || \
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((x) == PCI_DEVICE_ID_INTEL_I63XX) || \
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((x) == PCI_DEVICE_ID_INTEL_I5000X) || \
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((x) == PCI_DEVICE_ID_INTEL_I5000Z) || \
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((x) == PCI_DEVICE_ID_INTEL_I5000V) || \
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((x) == PCI_DEVICE_ID_INTEL_I5000P) || \
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((x) == PCI_DEVICE_ID_INTEL_82443LX) || \
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((x) == PCI_DEVICE_ID_INTEL_82443BX) || \
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((x) == PCI_DEVICE_ID_INTEL_82443BX_NO_AGP) || \
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((x) == PCI_DEVICE_ID_INTEL_82371XX) || \
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((x) == PCI_DEVICE_ID_INTEL_ICH) || \
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((x) == PCI_DEVICE_ID_INTEL_ICH0) || \
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((x) == PCI_DEVICE_ID_INTEL_ICH2) || \
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((x) == PCI_DEVICE_ID_INTEL_ICH4) || \
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((x) == PCI_DEVICE_ID_INTEL_ICH4M) || \
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((x) == PCI_DEVICE_ID_INTEL_ICH5) || \
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((x) == PCI_DEVICE_ID_INTEL_ICH6) || \
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((x) == PCI_DEVICE_ID_INTEL_ICH7DH) || \
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((x) == PCI_DEVICE_ID_INTEL_ICH7) || \
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((x) == PCI_DEVICE_ID_INTEL_ICH7M) || \
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((x) == PCI_DEVICE_ID_INTEL_ICH7MDH) || \
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((x) == PCI_DEVICE_ID_INTEL_NM10))
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// Definitely has ME and can be disabled
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#define PCI_DEVICE_ID_INTEL_ICH8ME 0x2811
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#define PCI_DEVICE_ID_INTEL_ICH9ME 0x2917
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#define PCI_DEVICE_ID_INTEL_ICH9M 0x2919
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#define PCI_DEV_HAS_ME_DISABLE(x) ( \
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((x) == PCI_DEVICE_ID_INTEL_ICH8ME) || \
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((x) == PCI_DEVICE_ID_INTEL_ICH9ME) || \
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((x) == PCI_DEVICE_ID_INTEL_ICH9M))
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// Definitely has ME and is very difficult to remove
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#define PCI_DEVICE_ID_INTEL_ICH10R 0x3a16
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#define PCI_DEVICE_ID_INTEL_3400_DESKTOP 0x3b00
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#define PCI_DEVICE_ID_INTEL_3400_MOBILE 0x3b01
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#define PCI_DEVICE_ID_INTEL_P55 0x3b02
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#define PCI_DEVICE_ID_INTEL_PM55 0x3b03
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#define PCI_DEVICE_ID_INTEL_H55 0x3b06
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#define PCI_DEVICE_ID_INTEL_QM57 0x3b07
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#define PCI_DEVICE_ID_INTEL_H57 0x3b08
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#define PCI_DEVICE_ID_INTEL_HM55 0x3b09
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#define PCI_DEVICE_ID_INTEL_Q57 0x3b0a
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#define PCI_DEVICE_ID_INTEL_HM57 0x3b0b
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#define PCI_DEVICE_ID_INTEL_3400_MOBILE_SFF 0x3b0d
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#define PCI_DEVICE_ID_INTEL_B55_A 0x3b0e
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#define PCI_DEVICE_ID_INTEL_QS57 0x3b0f
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#define PCI_DEVICE_ID_INTEL_3400 0x3b12
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#define PCI_DEVICE_ID_INTEL_3420 0x3b14
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#define PCI_DEVICE_ID_INTEL_3450 0x3b16
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#define PCI_DEVICE_ID_INTEL_B55_B 0x3b1e
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#define PCI_DEVICE_ID_INTEL_Z68 0x1c44
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#define PCI_DEVICE_ID_INTEL_P67 0x1c46
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#define PCI_DEVICE_ID_INTEL_UM67 0x1c47
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#define PCI_DEVICE_ID_INTEL_HM65 0x1c49
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#define PCI_DEVICE_ID_INTEL_H67 0x1c4a
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#define PCI_DEVICE_ID_INTEL_HM67 0x1c4b
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#define PCI_DEVICE_ID_INTEL_Q65 0x1c4c
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#define PCI_DEVICE_ID_INTEL_QS67 0x1c4d
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#define PCI_DEVICE_ID_INTEL_Q67 0x1c4e
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#define PCI_DEVICE_ID_INTEL_QM67 0x1c4f
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#define PCI_DEVICE_ID_INTEL_B65 0x1c50
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#define PCI_DEVICE_ID_INTEL_C202 0x1c52
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#define PCI_DEVICE_ID_INTEL_C204 0x1c54
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#define PCI_DEVICE_ID_INTEL_C206 0x1c56
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#define PCI_DEVICE_ID_INTEL_H61 0x1c5c
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#define PCI_DEVICE_ID_INTEL_Z77 0x1e44
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#define PCI_DEVICE_ID_INTEL_Z75 0x1e46
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#define PCI_DEVICE_ID_INTEL_Q77 0x1e47
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#define PCI_DEVICE_ID_INTEL_Q75 0x1e48
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#define PCI_DEVICE_ID_INTEL_B75 0x1e49
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#define PCI_DEVICE_ID_INTEL_H77 0x1e4a
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#define PCI_DEVICE_ID_INTEL_C216 0x1e53
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#define PCI_DEVICE_ID_INTEL_QM77 0x1e55
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#define PCI_DEVICE_ID_INTEL_QS77 0x1e56
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#define PCI_DEVICE_ID_INTEL_HM77 0x1e57
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#define PCI_DEVICE_ID_INTEL_UM77 0x1e58
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#define PCI_DEVICE_ID_INTEL_HM76 0x1e59
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#define PCI_DEVICE_ID_INTEL_HM75 0x1e5d
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#define PCI_DEVICE_ID_INTEL_HM70 0x1e5e
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#define PCI_DEVICE_ID_INTEL_NM70 0x1e5f
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#define PCI_DEVICE_ID_INTEL_DH89XXCC 0x2310
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#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL 0x9c41
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#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM 0x9c43
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#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE 0x9c45
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#define PCI_DEVICE_ID_INTEL_H81 0x8c5c
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#define PCI_DEVICE_ID_INTEL_B85 0x8c50
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#define PCI_DEVICE_ID_INTEL_Q85 0x8c4c
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#define PCI_DEVICE_ID_INTEL_Q87 0x8c4e
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#define PCI_DEVICE_ID_INTEL_QM87 0x8c4f
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#define PCI_DEVICE_ID_INTEL_H87 0x8c4a
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#define PCI_DEVICE_ID_INTEL_HM87 0x8c4b
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#define PCI_DEVICE_ID_INTEL_Z87 0x8c44
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#define PCI_DEVICE_ID_INTEL_X99 0x8d47
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#define PCI_DEVICE_ID_INTEL_WILDCAT_LP1 0x9cc1
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#define PCI_DEVICE_ID_INTEL_WILDCAT_LP2 0x9cc2
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#define PCI_DEVICE_ID_INTEL_WILDCAT_LP3 0x9cc3
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#define PCI_DEVICE_ID_INTEL_WILDCAT_LP4 0x9cc5
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#define PCI_DEVICE_ID_INTEL_WILDCAT_LP5 0x9cc6
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#define PCI_DEVICE_ID_INTEL_WILDCAT_LP6 0x9cc7
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#define PCI_DEVICE_ID_INTEL_WILDCAT_LP7 0x9cc9
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#define PCI_DEVICE_ID_INTEL_SUNRISE_LP1 0x9d43
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#define PCI_DEVICE_ID_INTEL_SUNRISE_LP2 0x9d48
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#define PCI_DEVICE_ID_INTEL_SUNRISE_LP3 0x9d4e
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#define PCI_DEVICE_ID_INTEL_SUNRISE_LP4 0x9d56
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#define PCI_DEVICE_ID_INTEL_SUNRISE_LP5 0x9d58
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#define PCI_DEVICE_ID_INTEL_SUNRISE_H0 0xa140
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#define PCI_DEVICE_ID_INTEL_SUNRISE_H1 0xa141
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#define PCI_DEVICE_ID_INTEL_SUNRISE_H2 0xa142
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#define PCI_DEVICE_ID_INTEL_SUNRISE_H3 0xa143
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#define PCI_DEVICE_ID_INTEL_SUNRISE_H4 0xa144
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#define PCI_DEVICE_ID_INTEL_SUNRISE_H5 0xa145
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#define PCI_DEVICE_ID_INTEL_SUNRISE_H6 0xa146
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#define PCI_DEVICE_ID_INTEL_SUNRISE_H7 0xa147
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#define PCI_DEVICE_ID_INTEL_SUNRISE_H8 0xa148
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#define PCI_DEVICE_ID_INTEL_SUNRISE_H9 0xa149
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#define PCI_DEVICE_ID_INTEL_SUNRISE_H10 0xa14a
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#define PCI_DEVICE_ID_INTEL_SUNRISE_H11 0xa14b
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#define PCI_DEVICE_ID_INTEL_SUNRISE_H12 0xa14c
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#define PCI_DEVICE_ID_INTEL_SUNRISE_H13 0xa14d
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#define PCI_DEVICE_ID_INTEL_SUNRISE_H14 0xa14e
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#define PCI_DEVICE_ID_INTEL_SUNRISE_H15 0xa14f
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#define PCI_DEVICE_ID_INTEL_SUNRISE_H16 0xa150
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#define PCI_DEVICE_ID_INTEL_SUNRISE_H17 0xa151
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#define PCI_DEVICE_ID_INTEL_SUNRISE_H18 0xa152
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#define PCI_DEVICE_ID_INTEL_SUNRISE_H19 0xa153
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#define PCI_DEVICE_ID_INTEL_SUNRISE_H20 0xa154
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#define PCI_DEVICE_ID_INTEL_SUNRISE_H21 0xa155
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#define PCI_DEVICE_ID_INTEL_SUNRISE_H22 0xa156
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#define PCI_DEVICE_ID_INTEL_SUNRISE_H23 0xa157
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#define PCI_DEVICE_ID_INTEL_SUNRISE_H24 0xa158
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#define PCI_DEVICE_ID_INTEL_SUNRISE_H25 0xa159
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#define PCI_DEVICE_ID_INTEL_SUNRISE_H26 0xa15a
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#define PCI_DEVICE_ID_INTEL_SUNRISE_H27 0xa15b
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#define PCI_DEVICE_ID_INTEL_SUNRISE_H28 0xa15c
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#define PCI_DEVICE_ID_INTEL_SUNRISE_H29 0xa15d
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#define PCI_DEVICE_ID_INTEL_SUNRISE_H30 0xa15e
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#define PCI_DEVICE_ID_INTEL_SUNRISE_H31 0xa15f
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#define PCI_DEVICE_ID_INTEL_LEWISBURG_1 0xa1c1
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#define PCI_DEVICE_ID_INTEL_LEWISBURG_2 0xa1c2
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#define PCI_DEVICE_ID_INTEL_LEWISBURG_3 0xa1c3
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#define PCI_DEVICE_ID_INTEL_LEWISBURG_4 0xa1c4
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#define PCI_DEVICE_ID_INTEL_LEWISBURG_5 0xa1c5
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#define PCI_DEVICE_ID_INTEL_LEWISBURG_6 0xa1c6
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#define PCI_DEVICE_ID_INTEL_LEWISBURG_7 0xa1c7
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#define PCI_DEV_HAS_ME_DIFFICULT(x) ( \
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((x) == PCI_DEVICE_ID_INTEL_ICH10R) || \
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((x) == PCI_DEVICE_ID_INTEL_3400_DESKTOP) || \
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((x) == PCI_DEVICE_ID_INTEL_3400_MOBILE) || \
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((x) == PCI_DEVICE_ID_INTEL_P55) || \
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((x) == PCI_DEVICE_ID_INTEL_PM55) || \
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((x) == PCI_DEVICE_ID_INTEL_H55) || \
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((x) == PCI_DEVICE_ID_INTEL_QM57) || \
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((x) == PCI_DEVICE_ID_INTEL_H57) || \
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((x) == PCI_DEVICE_ID_INTEL_HM55) || \
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((x) == PCI_DEVICE_ID_INTEL_Q57) || \
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((x) == PCI_DEVICE_ID_INTEL_HM57) || \
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((x) == PCI_DEVICE_ID_INTEL_3400_MOBILE_SFF) || \
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((x) == PCI_DEVICE_ID_INTEL_B55_A) || \
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((x) == PCI_DEVICE_ID_INTEL_QS57) || \
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((x) == PCI_DEVICE_ID_INTEL_3400) || \
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((x) == PCI_DEVICE_ID_INTEL_3420) || \
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((x) == PCI_DEVICE_ID_INTEL_3450) || \
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((x) == PCI_DEVICE_ID_INTEL_B55_B) || \
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((x) == PCI_DEVICE_ID_INTEL_Z68) || \
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((x) == PCI_DEVICE_ID_INTEL_P67) || \
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((x) == PCI_DEVICE_ID_INTEL_UM67) || \
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((x) == PCI_DEVICE_ID_INTEL_HM65) || \
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((x) == PCI_DEVICE_ID_INTEL_H67) || \
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((x) == PCI_DEVICE_ID_INTEL_HM67) || \
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((x) == PCI_DEVICE_ID_INTEL_Q65) || \
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((x) == PCI_DEVICE_ID_INTEL_QS67) || \
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((x) == PCI_DEVICE_ID_INTEL_Q67) || \
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((x) == PCI_DEVICE_ID_INTEL_QM67) || \
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((x) == PCI_DEVICE_ID_INTEL_B65) || \
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((x) == PCI_DEVICE_ID_INTEL_C202) || \
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((x) == PCI_DEVICE_ID_INTEL_C204) || \
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((x) == PCI_DEVICE_ID_INTEL_C206) || \
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((x) == PCI_DEVICE_ID_INTEL_H61) || \
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((x) == PCI_DEVICE_ID_INTEL_Z77) || \
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((x) == PCI_DEVICE_ID_INTEL_Z75) || \
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((x) == PCI_DEVICE_ID_INTEL_Q77) || \
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((x) == PCI_DEVICE_ID_INTEL_Q75) || \
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((x) == PCI_DEVICE_ID_INTEL_B75) || \
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((x) == PCI_DEVICE_ID_INTEL_H77) || \
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((x) == PCI_DEVICE_ID_INTEL_C216) || \
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((x) == PCI_DEVICE_ID_INTEL_QM77) || \
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((x) == PCI_DEVICE_ID_INTEL_QS77) || \
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((x) == PCI_DEVICE_ID_INTEL_HM77) || \
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((x) == PCI_DEVICE_ID_INTEL_UM77) || \
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((x) == PCI_DEVICE_ID_INTEL_HM76) || \
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((x) == PCI_DEVICE_ID_INTEL_HM75) || \
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((x) == PCI_DEVICE_ID_INTEL_HM70) || \
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((x) == PCI_DEVICE_ID_INTEL_NM70) || \
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((x) == PCI_DEVICE_ID_INTEL_DH89XXCC) || \
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((x) == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL) || \
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((x) == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM) || \
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((x) == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE) || \
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((x) == PCI_DEVICE_ID_INTEL_H81) || \
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((x) == PCI_DEVICE_ID_INTEL_B85) || \
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((x) == PCI_DEVICE_ID_INTEL_Q85) || \
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((x) == PCI_DEVICE_ID_INTEL_Q87) || \
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((x) == PCI_DEVICE_ID_INTEL_QM87) || \
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((x) == PCI_DEVICE_ID_INTEL_H87) || \
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((x) == PCI_DEVICE_ID_INTEL_HM87) || \
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((x) == PCI_DEVICE_ID_INTEL_Z87) || \
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((x) == PCI_DEVICE_ID_INTEL_X99) || \
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((x) == PCI_DEVICE_ID_INTEL_WILDCAT_LP1) || \
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((x) == PCI_DEVICE_ID_INTEL_WILDCAT_LP2) || \
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((x) == PCI_DEVICE_ID_INTEL_WILDCAT_LP3) || \
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((x) == PCI_DEVICE_ID_INTEL_WILDCAT_LP4) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_WILDCAT_LP5) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_WILDCAT_LP6) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_WILDCAT_LP7) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_SUNRISE_LP1) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_SUNRISE_LP2) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_SUNRISE_LP3) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_SUNRISE_LP4) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_SUNRISE_LP5) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H0) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H1) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H2) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H3) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H4) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H5) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H6) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H7) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H8) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H9) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H10) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H11) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H12) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H13) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H14) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H15) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H16) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H17) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H18) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H19) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H20) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H21) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H22) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H23) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H24) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H25) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H26) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H27) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H28) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H29) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H30) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H31) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_LEWISBURG_1) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_LEWISBURG_2) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_LEWISBURG_3) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_LEWISBURG_4) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_LEWISBURG_5) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_LEWISBURG_6) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_LEWISBURG_7) || \
|
|
0)
|
|
|
|
// Not sure if ME present, but should be able to disable it easily
|
|
#define PCI_DEVICE_ID_INTEL_ICH8 0x2810
|
|
#define PCI_DEVICE_ID_INTEL_ICH8M 0x2815
|
|
#define PCI_DEVICE_ID_INTEL_ICH9DH 0x2912
|
|
#define PCI_DEVICE_ID_INTEL_ICH9DO 0x2914
|
|
#define PCI_DEVICE_ID_INTEL_ICH9R 0x2916
|
|
#define PCI_DEVICE_ID_INTEL_ICH9 0x2918
|
|
|
|
#define PCI_DEV_CAN_DISABLE_ME_IF_PRESENT(x) ( \
|
|
((x) == PCI_DEVICE_ID_INTEL_ICH8) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_ICH8M) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_ICH9DH) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_ICH9DO) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_ICH9R) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_ICH9))
|
|
|
|
// Not sure at all
|
|
#define PCI_DEVICE_ID_INTEL_SCH_POULSBO_LPC 0x8119
|
|
#define PCI_DEVICE_ID_INTEL_SCH_POULSBO 0x8100
|
|
|
|
#define PCI_DEV_ME_NOT_SURE(x) ( \
|
|
((x) == PCI_DEVICE_ID_INTEL_SCH_POULSBO_LPC) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_SCH_POULSBO))
|
|
|
|
// ME PCI IDs (HECI)
|
|
#define PCI_DEVICE_ID_INTEL_COUGARPOINT_1 0x1C3A /* Cougar Point */
|
|
#define PCI_DEVICE_ID_INTEL_PATSBURG_1 0x1D3A /* C600/X79 Patsburg */
|
|
#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_1 0x1CBA /* Panther Point */
|
|
#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_2 0x1DBA /* Panther Point */
|
|
#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_3 0x1E3A /* Panther Point */
|
|
#define PCI_DEVICE_ID_INTEL_CAVECREEK 0x2364 /* Cave Creek */
|
|
#define PCI_DEVICE_ID_INTEL_BEARLAKE_1 0x28B4 /* Bearlake */
|
|
#define PCI_DEVICE_ID_INTEL_BEARLAKE_2 0x28C4 /* Bearlake */
|
|
#define PCI_DEVICE_ID_INTEL_BEARLAKE_3 0x28D4 /* Bearlake */
|
|
#define PCI_DEVICE_ID_INTEL_BEARLAKE_4 0x28E4 /* Bearlake */
|
|
#define PCI_DEVICE_ID_INTEL_BEARLAKE_5 0x28F4 /* Bearlake */
|
|
#define PCI_DEVICE_ID_INTEL_82946GZ 0x2974 /* 82946GZ/GL */
|
|
#define PCI_DEVICE_ID_INTEL_82G35 0x2984 /* 82G35 Express */
|
|
#define PCI_DEVICE_ID_INTEL_82Q963 0x2994 /* 82Q963/Q965 */
|
|
#define PCI_DEVICE_ID_INTEL_82P965 0x29A4 /* 82P965/G965 */
|
|
#define PCI_DEVICE_ID_INTEL_82Q35 0x29B4 /* 82Q35 Express */
|
|
#define PCI_DEVICE_ID_INTEL_82G33 0x29C4 /* 82G33/G31/P35/P31 Express */
|
|
#define PCI_DEVICE_ID_INTEL_82Q33 0x29D4 /* 82Q33 Express */
|
|
#define PCI_DEVICE_ID_INTEL_82X38 0x29E4 /* 82X38/X48 Express */
|
|
#define PCI_DEVICE_ID_INTEL_3200 0x29F4 /* 3200/3210 Server */
|
|
#define PCI_DEVICE_ID_INTEL_PM965 0x2A04 /* Mobile PM965/GM965 */
|
|
#define PCI_DEVICE_ID_INTEL_GME965 0x2A14 /* Mobile GME965/GLE960 */
|
|
#define PCI_DEVICE_ID_INTEL_CANTIGA_1 0x2A44 /* Cantiga */
|
|
#define PCI_DEVICE_ID_INTEL_CANTIGA_2 0x2a50 /* Cantiga */
|
|
#define PCI_DEVICE_ID_INTEL_CANTIGA_3 0x2A54 /* Cantiga */
|
|
#define PCI_DEVICE_ID_INTEL_CANTIGA_4 0x2A64 /* Cantiga */
|
|
#define PCI_DEVICE_ID_INTEL_CANTIGA_5 0x2A74 /* Cantiga */
|
|
#define PCI_DEVICE_ID_INTEL_EAGLELAKE_1 0x2E04 /* Eaglelake */
|
|
#define PCI_DEVICE_ID_INTEL_EAGLELAKE_2 0x2E14 /* Eaglelake */
|
|
#define PCI_DEVICE_ID_INTEL_EAGLELAKE_3 0x2E24 /* Eaglelake */
|
|
#define PCI_DEVICE_ID_INTEL_EAGLELAKE_4 0x2E34 /* Eaglelake */
|
|
#define PCI_DEVICE_ID_INTEL_CALPELLA_1 0x3B64 /* Calpella */
|
|
#define PCI_DEVICE_ID_INTEL_CALPELLA_2 0x3B65 /* Calpella */
|
|
#define PCI_DEVICE_ID_INTEL_LYNXPOINT_1 0x8C3A /* Lynx Point H */
|
|
#define PCI_DEVICE_ID_INTEL_LYNXPOINT_2 0x8CBA /* Lynx Point H Refresh */
|
|
#define PCI_DEVICE_ID_INTEL_LYNXPOINT_3 0x8D3A /* Lynx Point - Wellsburg */
|
|
#define PCI_DEVICE_ID_INTEL_LYNXPOINT_4 0x9C3A /* Lynx Point LP */
|
|
#define PCI_DEVICE_ID_INTEL_WILDCAT_1 0x9CBA /* Wildcat Point LP */
|
|
#define PCI_DEVICE_ID_INTEL_WILDCAT_2 0x9CBB /* Wildcat Point LP 2 */
|
|
#define PCI_DEVICE_ID_INTEL_SUNRISE_LP 0x9d3a /* SUNRISE Point-LP */
|
|
#define PCI_DEVICE_ID_INTEL_SUNRISE_H1_ME 0xa13a /* SUNRISE Point-H 1 */
|
|
#define PCI_DEVICE_ID_INTEL_SUNRISE_H2_ME 0xa13b /* SUNRISE Point-H 2 */
|
|
#define PCI_DEVICE_ID_INTEL_SUNRISE_H3_ME 0xA13E /* SUNRISE Point-H 3 */
|
|
#define PCI_DEVICE_ID_INTEL_LEWISBURG_CSME1 0xA1BA /* CSME Lewisburg #1 */
|
|
#define PCI_DEVICE_ID_INTEL_LEWISBURG_CSME2 0xA1BB /* CSME Lewisburg #2 */
|
|
#define PCI_DEVICE_ID_INTEL_LEWISBURG_CSME3 0xA1BE /* CSME Lewisburg #3 */
|
|
#define PCI_DEVICE_ID_INTEL_LEWISBURG_IE1 0xA1F8 /* IE Lewisburg #1 */
|
|
#define PCI_DEVICE_ID_INTEL_LEWISBURG_IE2 0xA1F9 /* IE Lewisburg #2 */
|
|
#define PCI_DEVICE_ID_INTEL_LEWISBURG_IE3 0xA1FC /* IE Lewisburg #3 */
|
|
#define PCI_DEVICE_ID_INTEL_CANNONLAKE 0xA360 /* Cannon Lake */
|
|
|
|
#define PCI_DEV_HAS_SUPPORTED_ME(x) ( \
|
|
((x) == PCI_DEVICE_ID_INTEL_COUGARPOINT_1) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_PATSBURG_1) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_PANTHERPOINT_1) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_PANTHERPOINT_2) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_PANTHERPOINT_3) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_CAVECREEK) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_BEARLAKE_1) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_BEARLAKE_2) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_BEARLAKE_3) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_BEARLAKE_4) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_BEARLAKE_5) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_82946GZ) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_82G35) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_82Q963) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_82P965) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_82Q35) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_82G33) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_82Q33) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_82X38) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_3200) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_PM965) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_GME965) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_CANTIGA_1) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_CANTIGA_2) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_CANTIGA_3) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_CANTIGA_4) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_CANTIGA_5) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_EAGLELAKE_1) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_EAGLELAKE_2) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_EAGLELAKE_3) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_EAGLELAKE_4) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_CALPELLA_1) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_CALPELLA_2) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_LYNXPOINT_1) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_LYNXPOINT_2) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_LYNXPOINT_3) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_LYNXPOINT_4) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_WILDCAT_1) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_WILDCAT_2) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_SUNRISE_LP) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H1_ME) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H2_ME) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H3_ME) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_LEWISBURG_CSME1) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_LEWISBURG_CSME2) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_LEWISBURG_CSME3) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_LEWISBURG_IE1) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_LEWISBURG_IE2) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_LEWISBURG_IE3) || \
|
|
((x) == PCI_DEVICE_ID_INTEL_CANNONLAKE) || \
|
|
0)
|
|
|
|
#define BOOTGUARD_DISABLED 0x400000000
|
|
#define BOOTGUARD_ENABLED_VERIFIED_MODE 0x100000000
|
|
#define BOOTGUARD_ENABLED_MEASUREMENT_MODE 0x200000000
|
|
#define BOOTGUARD_ENABLED_COMBI_MODE 0x300000000
|
|
#define BOOTGUARD_CAPABILITY(x) ( \
|
|
((x) == BOOTGUARD_DISABLED) || \
|
|
((x) == BOOTGUARD_ENABLED_VERIFIED_MODE) || \
|
|
((x) == BOOTGUARD_ENABLED_MEASUREMENT_MODE) || \
|
|
((x) == BOOTGUARD_ENABLED_COMBI_MODE))
|