70 lines
1.9 KiB
C
70 lines
1.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <device/pci_def.h>
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#include <reg_script.h>
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#include <stdint.h>
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#include <uart8250.h>
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#include <soc/iobp.h>
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#include <soc/serialio.h>
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const struct reg_script uart_init[] = {
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/* Set MMIO BAR */
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REG_PCI_WRITE32(PCI_BASE_ADDRESS_0, CONFIG_TTYS0_BASE),
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/* Enable Memory access and Bus Master */
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REG_PCI_OR32(PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER),
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/* Initialize LTR */
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REG_MMIO_RMW32(CONFIG_TTYS0_BASE + SIO_REG_PPR_GEN,
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~SIO_REG_PPR_GEN_LTR_MODE_MASK, 0),
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REG_MMIO_RMW32(CONFIG_TTYS0_BASE + SIO_REG_PPR_RST,
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~(SIO_REG_PPR_RST_ASSERT), 0),
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/* Take UART out of reset */
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REG_MMIO_OR32(CONFIG_TTYS0_BASE + SIO_REG_PPR_RST,
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SIO_REG_PPR_RST_ASSERT),
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/* Set M and N divisor inputs and enable clock */
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REG_MMIO_WRITE32(CONFIG_TTYS0_BASE + SIO_REG_PPR_CLOCK,
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SIO_REG_PPR_CLOCK_EN | SIO_REG_PPR_CLOCK_UPDATE |
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(SIO_REG_PPR_CLOCK_N_DIV << 16) |
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(SIO_REG_PPR_CLOCK_M_DIV << 1)),
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REG_SCRIPT_END
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};
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void pch_uart_init(void)
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{
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/* Program IOBP CB000154h[12,9:8,4:0] = 1001100011111b */
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u32 gpiodf = 0x131f;
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#if defined(__SIMPLE_DEVICE__)
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pci_devfn_t dev;
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#else
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struct device *dev;
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#endif
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/* Put UART in byte access mode for 16550 compatibility */
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switch (CONFIG_INTEL_PCH_UART_CONSOLE_NUMBER) {
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case 0:
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dev = PCH_DEV_UART0;
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gpiodf |= SIO_IOBP_GPIODF_UART0_BYTE_ACCESS;
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break;
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case 1:
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dev = PCH_DEV_UART1;
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gpiodf |= SIO_IOBP_GPIODF_UART1_BYTE_ACCESS;
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break;
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default:
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return;
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}
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/* Program IOBP GPIODF */
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pch_iobp_update(SIO_IOBP_GPIODF, ~gpiodf, gpiodf);
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/* Program IOBP CB000180h[5:0] = 111111b (undefined register) */
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pch_iobp_update(0xcb000180, ~0x0000003f, 0x0000003f);
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/* Initialize chipset uart interface */
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reg_script_run_on_dev(dev, uart_init);
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/*
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* Perform standard UART initialization
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* Divisor 1 is 115200 BAUD
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*/
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uart8250_mem_init(CONFIG_TTYS0_BASE, 1);
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}
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