178 lines
4.9 KiB
ArmAsm
178 lines
4.9 KiB
ArmAsm
/*
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* This file is part of the coreboot project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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// FIXME: Is this piece of code southbridge specific, or
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// can it be cleaned up so this include is not required?
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// It's needed right now because we get our DEFAULT_PMBASE from
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// here.
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#if CONFIG(SOUTHBRIDGE_INTEL_I82801DX)
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#include <southbridge/intel/i82801dx/i82801dx.h>
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#elif CONFIG(SOUTHBRIDGE_INTEL_I82801IX)
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#include <southbridge/intel/i82801ix/i82801ix.h>
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#else
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#error "Southbridge needs SMM handler support."
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#endif
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// ADDR32() macro
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#include <arch/registers.h>
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#if !CONFIG(SMM_ASEG)
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#error "Only use this file with ASEG."
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#endif /* CONFIG_SMM_ASEG */
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#define LAPIC_ID 0xfee00020
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.global smm_relocation_start
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.global smm_relocation_end
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/* initially SMM is some sort of real mode. */
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.code16
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/**
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* When starting up, x86 CPUs have their SMBASE set to 0x30000. However,
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* this is not a good place for the SMM handler to live, so it needs to
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* be relocated.
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* Traditionally SMM handlers used to live in the A segment (0xa0000).
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* With growing SMM handlers, more CPU cores, etc. CPU vendors started
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* allowing to relocate the handler to the end of physical memory, which
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* they refer to as TSEG.
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* This trampoline code relocates SMBASE to base address - ( lapicid * 0x400 )
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*
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* Why 0x400? It is a safe value to cover the save state area per CPU. On
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* current AMD CPUs this area is _documented_ to be 0x200 bytes. On Intel
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* Core 2 CPUs the _documented_ parts of the save state area is 48 bytes
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* bigger, effectively sizing our data structures 0x300 bytes.
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*
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* Example (with SMM handler living at 0xa0000):
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*
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* LAPICID SMBASE SMM Entry SAVE STATE
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* 0 0xa0000 0xa8000 0xafd00
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* 1 0x9fc00 0xa7c00 0xaf900
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* 2 0x9f800 0xa7800 0xaf500
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* 3 0x9f400 0xa7400 0xaf100
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* 4 0x9f000 0xa7000 0xaed00
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* 5 0x9ec00 0xa6c00 0xae900
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* 6 0x9e800 0xa6800 0xae500
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* 7 0x9e400 0xa6400 0xae100
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* 8 0x9e000 0xa6000 0xadd00
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* 9 0x9dc00 0xa5c00 0xad900
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* 10 0x9d800 0xa5800 0xad500
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* 11 0x9d400 0xa5400 0xad100
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* 12 0x9d000 0xa5000 0xacd00
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* 13 0x9cc00 0xa4c00 0xac900
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* 14 0x9c800 0xa4800 0xac500
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* 15 0x9c400 0xa4400 0xac100
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* . . . .
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* . . . .
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* . . . .
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* 31 0x98400 0xa0400 0xa8100
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*
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* With 32 cores, the SMM handler would need to fit between
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* 0xa0000-0xa0400 and the stub plus stack would need to go
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* at 0xa8000-0xa8100 (example for core 0). That is not enough.
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*
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* This means we're basically limited to 16 CPU cores before
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* we need to move the SMM handler to TSEG.
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*
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* Note: Some versions of Pentium M need their SMBASE aligned to 32k.
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* On those the above only works for up to 2 cores. But for now we only
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* care fore Core (2) Duo/Solo
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*
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*/
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smm_relocation_start:
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/* Check revision to see if AMD64 style SMM_BASE
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* Intel Core Solo/Duo: 0x30007
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* Intel Core2 Solo/Duo: 0x30100
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* Intel SandyBridge: 0x30101
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* AMD64: 0x3XX64
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* This check does not make much sense, unless someone ports
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* SMI handling to AMD64 CPUs.
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*/
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mov $0x38000 + 0x7efc, %ebx
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ADDR32(mov) (%ebx), %al
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cmp $0x64, %al
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je 1f
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mov $0x38000 + 0x7ef8, %ebx
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jmp smm_relocate
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1:
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mov $0x38000 + 0x7f00, %ebx
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smm_relocate:
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/* Get this CPU's LAPIC ID */
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movl $LAPIC_ID, %esi
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ADDR32(movl) (%esi), %ecx
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shr $24, %ecx
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/* calculate offset by multiplying the
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* APIC ID by 1024 (0x400)
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*/
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movl %ecx, %edx
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shl $10, %edx
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movl $0xa0000, %eax
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subl %edx, %eax /* subtract offset, see above */
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ADDR32(movl) %eax, (%ebx)
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/* The next section of code is potentially southbridge specific */
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/* Clear SMI status */
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movw $(DEFAULT_PMBASE + 0x34), %dx
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inw %dx, %ax
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outw %ax, %dx
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/* Clear PM1 status */
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movw $(DEFAULT_PMBASE + 0x00), %dx
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inw %dx, %ax
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outw %ax, %dx
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/* Set EOS bit so other SMIs can occur */
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movw $(DEFAULT_PMBASE + 0x30), %dx
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inl %dx, %eax
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orl $(1 << 1), %eax
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outl %eax, %dx
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/* End of southbridge specific section. */
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#if CONFIG(DEBUG_SMM_RELOCATION)
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/* print [SMM-x] so we can determine if CPUx went to SMM */
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movw $CONFIG_TTYS0_BASE, %dx
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mov $'[', %al
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outb %al, %dx
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mov $'S', %al
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outb %al, %dx
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mov $'M', %al
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outb %al, %dx
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outb %al, %dx
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movb $'-', %al
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outb %al, %dx
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/* calculate ascii of CPU number. More than 9 cores? -> FIXME */
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movb %cl, %al
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addb $'0', %al
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outb %al, %dx
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mov $']', %al
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outb %al, %dx
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mov $'\r', %al
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outb %al, %dx
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mov $'\n', %al
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outb %al, %dx
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#endif
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/* That's it. return */
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rsm
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smm_relocation_end:
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