218 lines
4.4 KiB
ArmAsm
218 lines
4.4 KiB
ArmAsm
/*
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* This file is part of the coreboot project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <cpu/x86/cr.h>
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#include <cpu/amd/mtrr.h>
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#include <cpu/x86/msr.h>
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/* The SIPI vector is responsible for initializing the APs in the system. It
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* loads microcode, sets up MSRs, and enables caching before calling into
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* C code. */
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/* These segment selectors need to match the gdt entries in c_start.S. */
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#define CODE_SEG 0x10
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#define DATA_SEG 0x18
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.section ".module_parameters", "aw", @progbits
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ap_start_params:
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gdtaddr:
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.word 0 /* limit */
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.long 0 /* table */
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.word 0 /* unused */
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idt_ptr:
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.long 0
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stack_top:
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.long 0
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stack_size:
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.long 0
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microcode_lock:
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.long 0
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microcode_ptr:
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.long 0
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msr_table_ptr:
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.long 0
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msr_count:
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.long 0
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c_handler:
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.long 0
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ap_count:
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.long 0
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#define CR0_CLEAR_FLAGS_CACHE_ENABLE (CR0_CD | CR0_NW)
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#define CR0_SET_FLAGS (CR0_CLEAR_FLAGS_CACHE_ENABLE | CR0_PE)
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#define CR0_CLEAR_FLAGS \
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(CR0_PG | CR0_AM | CR0_WP | CR0_NE | CR0_TS | CR0_EM | CR0_MP)
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.text
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.code16
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.global _start
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_start:
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cli
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xorl %eax, %eax
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movl %eax, %cr3 /* Invalidate TLB*/
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/* On hyper threaded cpus, invalidating the cache here is
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* very very bad. Don't.
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*/
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/* setup the data segment */
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movw %cs, %ax
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movw %ax, %ds
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/* The gdtaddr needs to be releative to the data segment in order
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* to properly dereference it. The .text section comes first in an
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* rmodule so _start can be used as a proxy for the load address. */
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movl $(gdtaddr), %ebx
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sub $(_start), %ebx
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lgdtl (%ebx)
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movl %cr0, %eax
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andl $~CR0_CLEAR_FLAGS, %eax
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orl $CR0_SET_FLAGS, %eax
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movl %eax, %cr0
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ljmpl $CODE_SEG, $1f
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1:
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.code32
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movw $DATA_SEG, %ax
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movw %ax, %ds
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movw %ax, %es
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movw %ax, %ss
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movw %ax, %fs
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movw %ax, %gs
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/* Load the Interrupt descriptor table */
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mov idt_ptr, %ebx
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lidt (%ebx)
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/* Obtain CPU number. */
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movl ap_count, %eax
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1:
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movl %eax, %ecx
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inc %ecx
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lock cmpxchg %ecx, ap_count
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jnz 1b
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/* Setup stacks for each CPU. */
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movl stack_size, %eax
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mul %ecx
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movl stack_top, %edx
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subl %eax, %edx
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mov %edx, %esp
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andl $0xfffffff0, %esp /* ensure stack alignment */
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/* Save CPU number. */
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mov %ecx, %esi
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/* Determine if one should check microcode versions. */
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mov microcode_ptr, %edi
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test %edi, %edi
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jz microcode_done /* Bypass if no microde exists. */
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/* Get the Microcode version. */
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mov $1, %eax
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cpuid
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mov $IA32_BIOS_SIGN_ID, %ecx
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rdmsr
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/* If something already loaded skip loading again. */
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test %edx, %edx
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jnz microcode_done
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/* Determine if parallel microcode loading is allowed. */
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cmpl $0xffffffff, microcode_lock
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je load_microcode
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/* Protect microcode loading. */
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lock_microcode:
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lock bts $0, microcode_lock
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jc lock_microcode
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load_microcode:
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/* Load new microcode. */
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mov $IA32_BIOS_UPDT_TRIG, %ecx
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xor %edx, %edx
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mov %edi, %eax
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/* The microcode pointer is passed in pointing to the header. Adjust
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* pointer to reflect the payload (header size is 48 bytes). */
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add $48, %eax
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pusha
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wrmsr
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popa
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/* Unconditionally unlock microcode loading. */
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cmpl $0xffffffff, microcode_lock
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je microcode_done
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xor %eax, %eax
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mov %eax, microcode_lock
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microcode_done:
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/*
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* Load MSRs. Each entry in the table consists of:
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* 0: index,
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* 4: value[31:0]
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* 8: value[63:32]
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*/
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mov msr_table_ptr, %edi
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mov msr_count, %ebx
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test %ebx, %ebx
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jz 1f
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#if CONFIG(X86_AMD_FIXED_MTRRS)
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/* Allow modification of RdDram and WrDram bits */
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mov $SYSCFG_MSR, %ecx
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rdmsr
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or $SYSCFG_MSR_MtrrFixDramModEn, %eax
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wrmsr
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#endif
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load_msr:
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mov (%edi), %ecx
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mov 4(%edi), %eax
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mov 8(%edi), %edx
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wrmsr
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add $12, %edi
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dec %ebx
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jnz load_msr
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#if CONFIG(X86_AMD_FIXED_MTRRS)
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mov $SYSCFG_MSR, %ecx
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rdmsr
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and $~SYSCFG_MSR_MtrrFixDramModEn, %eax
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wrmsr
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#endif
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1:
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/* Enable caching. */
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mov %cr0, %eax
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and $~(CR0_CLEAR_FLAGS_CACHE_ENABLE), %eax
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mov %eax, %cr0
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#if CONFIG(SSE)
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/* Enable sse instructions. */
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mov %cr4, %eax
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orl $(CR4_OSFXSR | CR4_OSXMMEXCPT), %eax
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mov %eax, %cr4
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#endif
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/* c_handler(cpu_num), preserve proper stack alignment */
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sub $12, %esp
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push %esi /* cpu_num */
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mov c_handler, %eax
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call *%eax
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halt_jump:
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hlt
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jmp halt_jump
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