67 lines
2.0 KiB
C
67 lines
2.0 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <stdint.h>
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#include <stdlib.h>
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#include <string.h>
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#include <commonlib/helpers.h>
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#include <console/console.h>
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#include <bootmem.h>
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#include <program_loading.h>
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void mirror_payload(struct prog *payload)
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{
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char *buffer;
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size_t size;
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char *src;
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uintptr_t alignment_diff;
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const unsigned long cacheline_size = 64;
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const uintptr_t intra_cacheline_mask = cacheline_size - 1;
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const uintptr_t cacheline_mask = ~intra_cacheline_mask;
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src = prog_start(payload);
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size = prog_size(payload);
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/*
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* Adjust size so that the start and end points are aligned to a
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* cacheline. The SPI hardware controllers on Intel machines should
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* cache full length cachelines as well as prefetch data. Once the
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* data is mirrored in memory all accesses should hit the CPU's cache.
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*/
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alignment_diff = (intra_cacheline_mask & (uintptr_t)src);
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size += alignment_diff;
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size = ALIGN_UP(size, cacheline_size);
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printk(BIOS_DEBUG, "Payload aligned size: 0x%zx\n", size);
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buffer = bootmem_allocate_buffer(size);
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if (buffer == NULL) {
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printk(BIOS_DEBUG, "No buffer for mirroring payload.\n");
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return;
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}
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src = (void *)(cacheline_mask & (uintptr_t)src);
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/*
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* Note that if mempcy is not using 32-bit moves the performance will
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* degrade because the SPI hardware prefetchers look for
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* cacheline-aligned 32-bit accesses to kick in.
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*/
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memcpy(buffer, src, size);
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/* Update the payload's backing store. */
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prog_set_area(payload, &buffer[alignment_diff], prog_size(payload));
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}
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