550 lines
16 KiB
C
550 lines
16 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef COMMONLIB_COREBOOT_TABLES_H
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#define COMMONLIB_COREBOOT_TABLES_H
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#include <stdint.h>
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/* The coreboot table information is for conveying information
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* from the firmware to the loaded OS image. Primarily this
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* is expected to be information that cannot be discovered by
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* other means, such as querying the hardware directly.
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*
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* All of the information should be Position Independent Data.
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* That is it should be safe to relocated any of the information
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* without it's meaning/correctness changing. For table that
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* can reasonably be used on multiple architectures the data
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* size should be fixed. This should ease the transition between
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* 32 bit and 64 bit architectures etc.
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*
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* The completeness test for the information in this table is:
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* - Can all of the hardware be detected?
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* - Are the per motherboard constants available?
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* - Is there enough to allow a kernel to run that was written before
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* a particular motherboard is constructed? (Assuming the kernel
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* has drivers for all of the hardware but it does not have
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* assumptions on how the hardware is connected together).
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*
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* With this test it should be straight forward to determine if a
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* table entry is required or not. This should remove much of the
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* long term compatibility burden as table entries which are
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* irrelevant or have been replaced by better alternatives may be
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* dropped. Of course it is polite and expedite to include extra
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* table entries and be backwards compatible, but it is not required.
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*/
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enum {
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LB_TAG_UNUSED = 0x0000,
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LB_TAG_MEMORY = 0x0001,
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LB_TAG_HWRPB = 0x0002,
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LB_TAG_MAINBOARD = 0x0003,
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LB_TAG_VERSION = 0x0004,
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LB_TAG_EXTRA_VERSION = 0x0005,
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LB_TAG_BUILD = 0x0006,
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LB_TAG_COMPILE_TIME = 0x0007,
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LB_TAG_COMPILE_BY = 0x0008,
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LB_TAG_COMPILE_HOST = 0x0009,
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LB_TAG_COMPILE_DOMAIN = 0x000a,
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LB_TAG_COMPILER = 0x000b,
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LB_TAG_LINKER = 0x000c,
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LB_TAG_ASSEMBLER = 0x000d,
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LB_TAG_SERIAL = 0x000f,
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LB_TAG_CONSOLE = 0x0010,
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LB_TAG_FORWARD = 0x0011,
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LB_TAG_FRAMEBUFFER = 0x0012,
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LB_TAG_GPIO = 0x0013,
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LB_TAG_TIMESTAMPS = 0x0016,
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LB_TAG_CBMEM_CONSOLE = 0x0017,
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LB_TAG_MRC_CACHE = 0x0018,
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LB_TAG_VBNV = 0x0019,
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LB_TAG_VBOOT_HANDOFF = 0x0020, /* deprecated */
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LB_TAG_X86_ROM_MTRR = 0x0021,
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LB_TAG_DMA = 0x0022,
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LB_TAG_RAM_OOPS = 0x0023,
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LB_TAG_ACPI_GNVS = 0x0024,
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LB_TAG_BOARD_ID = 0x0025, /* deprecated */
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LB_TAG_VERSION_TIMESTAMP = 0x0026,
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LB_TAG_WIFI_CALIBRATION = 0x0027,
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LB_TAG_RAM_CODE = 0x0028, /* deprecated */
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LB_TAG_SPI_FLASH = 0x0029,
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LB_TAG_SERIALNO = 0x002a,
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LB_TAG_MTC = 0x002b,
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LB_TAG_VPD = 0x002c,
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LB_TAG_SKU_ID = 0x002d, /* deprecated */
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LB_TAG_BOOT_MEDIA_PARAMS = 0x0030,
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LB_TAG_CBMEM_ENTRY = 0x0031,
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LB_TAG_TSC_INFO = 0x0032,
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LB_TAG_MAC_ADDRS = 0x0033,
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LB_TAG_VBOOT_WORKBUF = 0x0034,
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LB_TAG_MMC_INFO = 0x0035,
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LB_TAG_TCPA_LOG = 0x0036,
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LB_TAG_FMAP = 0x0037,
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LB_TAG_PLATFORM_BLOB_VERSION = 0x0038,
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LB_TAG_SMMSTOREV2 = 0x0039,
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LB_TAG_TPM_PPI_HANDOFF = 0x003a,
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LB_TAG_BOARD_CONFIG = 0x0040,
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LB_TAG_ACPI_CNVS = 0x0041,
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/* The following options are CMOS-related */
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LB_TAG_CMOS_OPTION_TABLE = 0x00c8,
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LB_TAG_OPTION = 0x00c9,
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LB_TAG_OPTION_ENUM = 0x00ca,
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LB_TAG_OPTION_DEFAULTS = 0x00cb,
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LB_TAG_OPTION_CHECKSUM = 0x00cc,
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};
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/* Since coreboot is usually compiled 32bit, gcc will align 64bit
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* types to 32bit boundaries. If the coreboot table is dumped on a
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* 64bit system, a uint64_t would be aligned to 64bit boundaries,
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* breaking the table format.
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*
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* lb_uint64 will keep 64bit coreboot table values aligned to 32bit
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* to ensure compatibility. They can be accessed with the two functions
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* below: unpack_lb64() and pack_lb64()
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*
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* See also: util/lbtdump/lbtdump.c
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*/
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struct lb_uint64 {
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uint32_t lo;
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uint32_t hi;
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};
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static inline uint64_t unpack_lb64(struct lb_uint64 value)
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{
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uint64_t result;
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result = value.hi;
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result = (result << 32) + value.lo;
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return result;
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}
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static inline struct lb_uint64 pack_lb64(uint64_t value)
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{
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struct lb_uint64 result;
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result.lo = (value >> 0) & 0xffffffff;
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result.hi = (value >> 32) & 0xffffffff;
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return result;
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}
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struct lb_header {
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uint8_t signature[4]; /* LBIO */
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uint32_t header_bytes;
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uint32_t header_checksum;
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uint32_t table_bytes;
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uint32_t table_checksum;
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uint32_t table_entries;
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};
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/* Every entry in the boot environment list will correspond to a boot
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* info record. Encoding both type and size. The type is obviously
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* so you can tell what it is. The size allows you to skip that
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* boot environment record if you don't know what it is. This allows
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* forward compatibility with records not yet defined.
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*/
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struct lb_record {
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uint32_t tag; /* tag ID */
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uint32_t size; /* size of record (in bytes) */
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};
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struct lb_memory_range {
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struct lb_uint64 start;
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struct lb_uint64 size;
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uint32_t type;
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#define LB_MEM_RAM 1 /* Memory anyone can use */
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#define LB_MEM_RESERVED 2 /* Don't use this memory region */
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#define LB_MEM_ACPI 3 /* ACPI Tables */
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#define LB_MEM_NVS 4 /* ACPI NVS Memory */
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#define LB_MEM_UNUSABLE 5 /* Unusable address space */
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#define LB_MEM_VENDOR_RSVD 6 /* Vendor Reserved */
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#define LB_MEM_TABLE 16 /* Ram configuration tables are kept in */
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};
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struct lb_memory {
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uint32_t tag;
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uint32_t size;
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struct lb_memory_range map[0];
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};
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struct lb_hwrpb {
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uint32_t tag;
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uint32_t size;
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uint64_t hwrpb;
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};
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struct lb_mainboard {
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uint32_t tag;
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uint32_t size;
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uint8_t vendor_idx;
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uint8_t part_number_idx;
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uint8_t strings[0];
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};
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struct lb_string {
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uint32_t tag;
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uint32_t size;
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uint8_t string[0];
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};
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struct lb_timestamp {
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uint32_t tag;
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uint32_t size;
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uint32_t timestamp;
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};
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/* 0xe is taken by v3 */
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struct lb_serial {
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uint32_t tag;
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uint32_t size;
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#define LB_SERIAL_TYPE_IO_MAPPED 1
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#define LB_SERIAL_TYPE_MEMORY_MAPPED 2
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uint32_t type;
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uint32_t baseaddr;
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uint32_t baud;
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uint32_t regwidth;
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/* Crystal or input frequency to the chip containing the UART.
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* Provide the board specific details to allow the payload to
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* initialize the chip containing the UART and make independent
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* decisions as to which dividers to select and their values
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* to eventually arrive at the desired console baud-rate. */
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uint32_t input_hertz;
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/* UART PCI address: bus, device, function
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* 1 << 31 - Valid bit, PCI UART in use
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* Bus << 20
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* Device << 15
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* Function << 12
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*/
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uint32_t uart_pci_addr;
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};
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struct lb_console {
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uint32_t tag;
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uint32_t size;
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uint16_t type;
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};
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#define LB_TAG_CONSOLE_SERIAL8250 0
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#define LB_TAG_CONSOLE_VGA 1 // OBSOLETE
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#define LB_TAG_CONSOLE_BTEXT 2 // OBSOLETE
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#define LB_TAG_CONSOLE_LOGBUF 3 // OBSOLETE
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#define LB_TAG_CONSOLE_SROM 4 // OBSOLETE
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#define LB_TAG_CONSOLE_EHCI 5
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#define LB_TAG_CONSOLE_SERIAL8250MEM 6
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struct lb_forward {
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uint32_t tag;
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uint32_t size;
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uint64_t forward;
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};
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/**
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* coreboot framebuffer
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*
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* The coreboot framebuffer uses a very common format usually referred
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* to as "linear framebuffer":
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*
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* The first pixel of the framebuffer is the upper left corner, its
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* address is given by `physical_address`.
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*
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* Each pixel is represented by exactly `bits_per_pixel` bits. If a
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* pixel (or a color component therein) doesn't fill a whole byte or
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* doesn't start on a byte boundary, it starts at the least signifi-
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* cant bit not occupied by the previous pixel (or color component).
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* Pixels (or color components) that span multiple bytes always start
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* in the byte with the lowest address.
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*
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* The framebuffer provides a visible rectangle of `x_resolution` *
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* `y_resolution` pixels. However, the lines always start at a byte
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* boundary given by `bytes_per_line`, which may leave a gap after
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* each line of pixels. Thus, the data for a pixel with the coordi-
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* nates (x, y) from the upper left corner always starts at
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*
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* physical_address + y * bytes_per_line + x * bits_per_pixel / 8
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*
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* `bytes_per_line` is always big enough to hold `x_resolution`
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* pixels. It can, however, be arbitrarily higher (e.g. to fulfill
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* hardware constraints or for optimization purposes). The size of
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* the framebuffer is always `y_resolution * bytes_per_line`.
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*
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* The coreboot framebuffer only supports RGB color formats. The
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* position and size of each color component are specified indivi-
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* dually by <color>_mask_pos and <color>_mask_size. To allow byte
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* or word aligned pixels, a fourth (padding) component may be
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* specified by `reserved_mask_pos` and `reserved_mask_size`.
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*
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* Software utilizing the coreboot framebuffer shall consider all
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* fields described above. It may, however, only implement a subset
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* of the possible color formats.
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*/
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/*
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* Framebuffer orientation, matches drm_connector.h drm_panel_orientation in the
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* Linux kernel.
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*/
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enum lb_fb_orientation {
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LB_FB_ORIENTATION_NORMAL = 0,
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LB_FB_ORIENTATION_BOTTOM_UP = 1,
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LB_FB_ORIENTATION_LEFT_UP = 2,
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LB_FB_ORIENTATION_RIGHT_UP = 3,
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};
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struct lb_framebuffer {
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uint32_t tag;
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uint32_t size;
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uint64_t physical_address;
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uint32_t x_resolution;
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uint32_t y_resolution;
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uint32_t bytes_per_line;
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uint8_t bits_per_pixel;
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uint8_t red_mask_pos;
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uint8_t red_mask_size;
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uint8_t green_mask_pos;
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uint8_t green_mask_size;
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uint8_t blue_mask_pos;
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uint8_t blue_mask_size;
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uint8_t reserved_mask_pos;
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uint8_t reserved_mask_size;
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uint8_t orientation;
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};
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struct lb_gpio {
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uint32_t port;
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uint32_t polarity;
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#define ACTIVE_LOW 0
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#define ACTIVE_HIGH 1
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uint32_t value;
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#define GPIO_MAX_NAME_LENGTH 16
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uint8_t name[GPIO_MAX_NAME_LENGTH];
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};
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struct lb_gpios {
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uint32_t tag;
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uint32_t size;
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uint32_t count;
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struct lb_gpio gpios[0];
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};
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struct lb_range {
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uint32_t tag;
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uint32_t size;
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uint64_t range_start;
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uint32_t range_size;
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};
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void lb_ramoops(struct lb_header *header);
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struct lb_cbmem_ref {
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uint32_t tag;
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uint32_t size;
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uint64_t cbmem_addr;
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};
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struct lb_x86_rom_mtrr {
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uint32_t tag;
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uint32_t size;
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/* The variable range MTRR index covering the ROM. */
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uint32_t index;
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};
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/* Memory map windows to translate addresses between SPI flash space and host address space. */
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struct flash_mmap_window {
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uint32_t flash_base;
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uint32_t host_base;
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uint32_t size;
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};
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struct lb_spi_flash {
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uint32_t tag;
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uint32_t size;
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uint32_t flash_size;
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uint32_t sector_size;
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uint32_t erase_cmd;
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/*
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* Number of mmap windows used by the platform to decode addresses between SPI flash
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* space and host address space. This determines the number of entries in mmap_table.
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*/
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uint32_t mmap_count;
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struct flash_mmap_window mmap_table[0];
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};
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struct lb_boot_media_params {
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uint32_t tag;
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uint32_t size;
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/* offsets are relative to start of boot media */
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uint64_t fmap_offset;
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uint64_t cbfs_offset;
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uint64_t cbfs_size;
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uint64_t boot_media_size;
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};
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/*
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* There can be more than one of these records as there is one per cbmem entry.
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*/
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struct lb_cbmem_entry {
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uint32_t tag;
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uint32_t size;
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uint64_t address;
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uint32_t entry_size;
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uint32_t id;
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};
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struct lb_tsc_info {
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uint32_t tag;
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uint32_t size;
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uint32_t freq_khz;
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};
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struct mac_address {
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uint8_t mac_addr[6];
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uint8_t pad[2]; /* Pad it to 8 bytes to keep it simple. */
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};
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struct lb_mmc_info {
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uint32_t tag;
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uint32_t size;
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/*
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* Passes the early mmc status to payload to indicate if firmware
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* successfully sent CMD0, CMD1 to the card or not. In case of
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* success, the payload can skip the first step of the initialization
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* sequence which is to send CMD0, and instead start by sending CMD1
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* as described in Jedec Standard JESD83-B1 section 6.4.3.
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* passes 1 on success
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*/
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int32_t early_cmd1_status;
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};
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struct lb_macs {
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uint32_t tag;
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uint32_t size;
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uint32_t count;
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struct mac_address mac_addrs[0];
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};
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struct lb_board_config {
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uint32_t tag;
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uint32_t size;
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struct lb_uint64 fw_config;
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uint32_t board_id;
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uint32_t ram_code;
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uint32_t sku_id;
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};
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#define MAX_SERIALNO_LENGTH 32
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/* The following structures are for the CMOS definitions table */
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/* CMOS header record */
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struct cmos_option_table {
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uint32_t tag; /* CMOS definitions table type */
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uint32_t size; /* size of the entire table */
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uint32_t header_length; /* length of header */
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};
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/* CMOS entry record
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* This record is variable length. The name field may be
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* shorter than CMOS_MAX_NAME_LENGTH. The entry may start
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* anywhere in the byte, but can not span bytes unless it
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* starts at the beginning of the byte and the length is
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* fills complete bytes.
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*/
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struct cmos_entries {
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uint32_t tag; /* entry type */
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uint32_t size; /* length of this record */
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uint32_t bit; /* starting bit from start of image */
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uint32_t length; /* length of field in bits */
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uint32_t config; /* e=enumeration, h=hex, r=reserved */
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uint32_t config_id; /* a number linking to an enumeration record */
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#define CMOS_MAX_NAME_LENGTH 32
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uint8_t name[CMOS_MAX_NAME_LENGTH]; /* name of entry in ascii,
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variable length int aligned */
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};
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/* CMOS enumerations record
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* This record is variable length. The text field may be
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* shorter than CMOS_MAX_TEXT_LENGTH.
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*/
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struct cmos_enums {
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uint32_t tag; /* enumeration type */
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uint32_t size; /* length of this record */
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uint32_t config_id; /* a number identifying the config id */
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uint32_t value; /* the value associated with the text */
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#define CMOS_MAX_TEXT_LENGTH 32
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uint8_t text[CMOS_MAX_TEXT_LENGTH]; /* enum description in ascii,
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variable length int aligned */
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};
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/* CMOS defaults record
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* This record contains default settings for the CMOS ram.
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*/
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struct cmos_defaults {
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uint32_t tag; /* default type */
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uint32_t size; /* length of this record */
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uint32_t name_length; /* length of the following name field */
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uint8_t name[CMOS_MAX_NAME_LENGTH]; /* name identifying the default */
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#define CMOS_IMAGE_BUFFER_SIZE 256
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uint8_t default_set[CMOS_IMAGE_BUFFER_SIZE]; /* default settings */
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};
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struct cmos_checksum {
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uint32_t tag;
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uint32_t size;
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/* In practice everything is byte aligned, but things are measured
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* in bits to be consistent.
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*/
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uint32_t range_start; /* First bit that is checksummed (byte aligned) */
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uint32_t range_end; /* Last bit that is checksummed (byte aligned) */
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uint32_t location; /* First bit of the checksum (byte aligned) */
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uint32_t type; /* Checksum algorithm that is used */
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#define CHECKSUM_NONE 0
|
|
#define CHECKSUM_PCBIOS 1
|
|
};
|
|
|
|
/* SMMSTOREv2 record
|
|
* This record contains information to use SMMSTOREv2.
|
|
*/
|
|
|
|
struct lb_smmstorev2 {
|
|
uint32_t tag;
|
|
uint32_t size;
|
|
uint32_t num_blocks; /* Number of writeable blocks in SMM */
|
|
uint32_t block_size; /* Size of a block in byte. Default: 64 KiB */
|
|
uint32_t mmap_addr; /* MMIO address of the store for read only access */
|
|
uint32_t com_buffer; /* Physical address of the communication buffer */
|
|
uint32_t com_buffer_size; /* Size of the communication buffer in bytes */
|
|
uint8_t apm_cmd; /* The command byte to write to the APM I/O port */
|
|
uint8_t unused[3]; /* Set to zero */
|
|
};
|
|
|
|
enum lb_tmp_ppi_tpm_version {
|
|
LB_TPM_VERSION_UNSPEC = 0,
|
|
LB_TPM_VERSION_TPM_VERSION_1_2,
|
|
LB_TPM_VERSION_TPM_VERSION_2,
|
|
};
|
|
|
|
/*
|
|
* Handoff buffer for TPM Physical Presence Interface.
|
|
* * ppi_address Pointer to PPI buffer shared with ACPI
|
|
* The layout of the buffer matches the QEMU virtual memory device
|
|
* that is generated by QEMU.
|
|
* See files 'hw/i386/acpi-build.c' and 'include/hw/acpi/tpm.h'
|
|
* for details.
|
|
* * tpm_version TPM version: 1 for TPM1.2, 2 for TPM2.0
|
|
* * ppi_version BCD encoded version of TPM PPI interface
|
|
*/
|
|
struct lb_tpm_physical_presence {
|
|
uint32_t tag;
|
|
uint32_t size;
|
|
uint32_t ppi_address; /* Address of ACPI PPI communication buffer */
|
|
uint8_t tpm_version; /* 1: TPM1.2, 2: TPM2.0 */
|
|
uint8_t ppi_version; /* BCD encoded */
|
|
} __packed;
|
|
#endif
|