190 lines
7.7 KiB
C
190 lines
7.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/* This file is part of the coreboot project. */
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#ifndef LT1000_GPIO_H
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#define LT1000_GPIO_H
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#include <soc/gpe.h>
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#include <soc/gpio.h>
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#ifndef __ACPI__
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/* Pad configuration in ramstage. */
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static const struct pad_config gpio_table[] = {
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/* RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
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/* LAD0 */ PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1),
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/* LAD1 */ PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1),
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/* LAD2 */ PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1),
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/* LAD3 */ PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1),
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/* LFRAME# */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
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/* SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
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/* PIRQA# */ PAD_CFG_NC(GPP_A7),
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/* CLKRUN# */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
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/* CLKOUT_LPC0 */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),
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/* CLKOUT_LPC1 */ PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),
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/* PME# */ PAD_CFG_NC(GPP_A11),
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/* BM_BUSY# */ PAD_CFG_NC(GPP_A12),
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/* SUSWARN# */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
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/* SUS_STAT# */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
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/* SUSACK# */ PAD_CFG_NF(GPP_A15, DN_20K, DEEP, NF1),
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/* SD_1P8_SEL */ PAD_CFG_NC(GPP_A16),
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/* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),
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/* ISH_GP0 */ PAD_CFG_GPI(GPP_A18, NONE, DEEP),
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/* ISH_GP1 */ PAD_CFG_GPI(GPP_A19, NONE, DEEP),
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/* ISH_GP2 */ PAD_CFG_GPI(GPP_A20, NONE, DEEP),
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/* ISH_GP3 */ PAD_CFG_NC(GPP_A21),
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/* ISH_GP4 */ PAD_CFG_NC(GPP_A22),
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/* ISH_GP5 */ PAD_CFG_NC(GPP_A23),
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/* CORE_VID0 */ PAD_CFG_NC(GPP_B0),
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/* CORE_VID1 */ PAD_CFG_NC(GPP_B1),
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/* VRALERT# */ PAD_CFG_NC(GPP_B2),
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/* CPU_GP2 */ PAD_CFG_NC(GPP_B3),
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/* CPU_GP3 */ PAD_CFG_NC(GPP_B4),
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/* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
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/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
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/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
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/* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),
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/* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
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/* SRCCLKREQ5# */ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
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/* EXT_PWR_GATE# */ PAD_CFG_NC(GPP_B11),
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/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
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/* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
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/* SPKR */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
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/* GSPI0_CS# */ PAD_CFG_NC(GPP_B15),
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/* GSPI0_CLK */ PAD_CFG_NC(GPP_B16),
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/* GSPI0_MISO */ PAD_CFG_NC(GPP_B17),
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/* GSPI0_MOSI */ PAD_CFG_GPI_SCI(GPP_B18, UP_20K, PLTRST, LEVEL, INVERT),
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/* GSPI1_CS# */ PAD_CFG_NC(GPP_B19),
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/* GSPI1_CLK */ PAD_CFG_NC(GPP_B20),
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/* GSPI1_MISO */ PAD_CFG_NC(GPP_B21),
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/* GSPI1_MOSI */ PAD_CFG_NF(GPP_B22, DN_20K, DEEP, NF1),
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/* SM1ALERT# */ PAD_CFG_TERM_GPO(GPP_B23, 1, DN_20K, DEEP),
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/* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
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/* SMBDATA */ PAD_CFG_NF(GPP_C1, DN_20K, DEEP, NF1),
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/* SMBALERT# */ PAD_CFG_TERM_GPO(GPP_C2, 1, DN_20K, DEEP),
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/* SML0CLK */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
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/* SML0DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
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/* SML0ALERT# */ PAD_CFG_GPI_APIC_INVERT(GPP_C5, DN_20K, DEEP),
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/* SML1CLK */ PAD_CFG_NC(GPP_C6), /* RESERVED */
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/* SML1DATA */ PAD_CFG_NC(GPP_C7), /* RESERVED */
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/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
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/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
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/* UART0_RTS# */ PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1),
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/* UART0_CTS# */ PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1),
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/* UART1_RXD */ PAD_CFG_NC(GPP_C12),
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/* UART1_TXD */ PAD_CFG_NC(GPP_C13),
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/* UART1_RTS# */ PAD_CFG_NC(GPP_C14),
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/* UART1_CTS# */ PAD_CFG_NC(GPP_C15),
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/* I2C0_SDA */ PAD_CFG_GPI(GPP_C16, NONE, DEEP),
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/* I2C0_SCL */ PAD_CFG_GPI(GPP_C17, NONE, DEEP),
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/* I2C1_SDA */ PAD_CFG_GPI(GPP_C18, NONE, DEEP),
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/* I2C1_SCL */ PAD_CFG_NC(GPP_C19),
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/* UART2_RXD */ PAD_CFG_NC(GPP_C20),
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/* UART2_TXD */ PAD_CFG_NC(GPP_C21),
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/* UART2_RTS# */ PAD_CFG_NC(GPP_C22),
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/* UART2_CTS# */ PAD_CFG_NC(GPP_C23),
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/* SPI1_CS# */ PAD_CFG_NC(GPP_D0),
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/* SPI1_CLK */ PAD_CFG_NC(GPP_D1),
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/* SPI1_MISO */ PAD_CFG_NC(GPP_D2),
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/* SPI1_MOSI */ PAD_CFG_NC(GPP_D3),
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/* FASHTRIG */ PAD_CFG_NC(GPP_D4),
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/* ISH_I2C0_SDA */ PAD_CFG_NC(GPP_D5),
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/* ISH_I2C0_SCL */ PAD_CFG_NC(GPP_D6),
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/* ISH_I2C1_SDA */ PAD_CFG_NC(GPP_D7),
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/* ISH_I2C1_SCL */ PAD_CFG_NC(GPP_D8),
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/* ISH_SPI_CS# */ PAD_CFG_TERM_GPO(GPP_D9, 0, NONE, DEEP),
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/* ISH_SPI_CLK */ PAD_CFG_GPI(GPP_D10, NONE, DEEP),
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/* ISH_SPI_MISO */ PAD_CFG_TERM_GPO(GPP_D11, 1, NONE, DEEP),
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/* ISH_SPI_MOSI */ PAD_CFG_NC(GPP_D12),
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/* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13),
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/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14),
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/* ISH_UART0_RTS# */ PAD_CFG_NC(GPP_D15),
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/* ISH_UART0_CTS# */ PAD_CFG_NC(GPP_D16),
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/* DMIC_CLK1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
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/* DMIC_DATA1 */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
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/* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
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/* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
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/* SPI1_IO2 */ PAD_CFG_NC(GPP_D21),
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/* SPI1_IO3 */ PAD_CFG_NC(GPP_D22),
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/* I2S_MCLK */ PAD_CFG_NC(GPP_D23),
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/* SATAXPCI0 */ PAD_CFG_NF(GPP_E0, UP_20K, DEEP, NF1),
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/* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, UP_20K, DEEP, NF1),
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/* SATAXPCIE2 */ PAD_CFG_NF(GPP_E2, UP_20K, DEEP, NF1),
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/* CPU_GP0 */ PAD_CFG_NC(GPP_E3),
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/* SATA_DEVSLP0 */ PAD_CFG_NC(GPP_E4),
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/* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5),
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/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6),
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/* CPU_GP1 */ PAD_CFG_NC(GPP_E7),
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/* SATALED# */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
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/* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
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/* USB2_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),
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/* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
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/* USB2_OC3# */ PAD_CFG_NC(GPP_E12),
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/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
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/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
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/* DDPD_HPD2 */ PAD_CFG_NC(GPP_E15),
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/* DDPE_HPD3 */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, PLTRST, NONE),
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/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
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/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
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/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF1),
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/* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
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/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, DN_20K, DEEP, NF1),
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/* DDPD_CTRLCLK */ PAD_CFG_GPI_APIC(GPP_E22, NONE, DEEP),
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/* DDPD_CTRLDATA */ PAD_CFG_TERM_GPO(GPP_E23, 1, DN_20K, DEEP),
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/* I2S2_SCLK */ PAD_CFG_NC(GPP_F0),
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/* I2S2_SFRM */ PAD_CFG_NC(GPP_F1),
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/* I2S2_TXD */ PAD_CFG_NC(GPP_F2),
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/* I2S2_RXD */ PAD_CFG_NC(GPP_F3),
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/* I2C2_SDA */ PAD_CFG_NC(GPP_F4),
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/* I2C2_SCL */ PAD_CFG_NC(GPP_F5),
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/* I2C3_SDA */ PAD_CFG_NC(GPP_F6),
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/* I2C3_SCL */ PAD_CFG_NC(GPP_F7),
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/* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1),
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/* I2C4_SCL */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1),
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/* I2C5_SDA */ PAD_CFG_NC(GPP_F10),
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/* I2C5_SCL */ PAD_CFG_NC(GPP_F11),
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/* EMMC_CMD */ PAD_CFG_NC(GPP_F12),
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/* EMMC_DATA0 */ PAD_CFG_NC(GPP_F13),
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/* EMMC_DATA1 */ PAD_CFG_NC(GPP_F14),
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/* EMMC_DATA2 */ PAD_CFG_NC(GPP_F15),
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/* EMMC_DATA3 */ PAD_CFG_NC(GPP_F16),
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/* EMMC_DATA4 */ PAD_CFG_NC(GPP_F17),
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/* EMMC_DATA5 */ PAD_CFG_NC(GPP_F18),
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/* EMMC_DATA6 */ PAD_CFG_NC(GPP_F19),
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/* EMMC_DATA7 */ PAD_CFG_NC(GPP_F20),
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/* EMMC_RCLK */ PAD_CFG_NC(GPP_F21),
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/* EMMC_CLK */ PAD_CFG_NC(GPP_F22),
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/* RSVD */ PAD_CFG_NC(GPP_F23),
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/* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1),
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/* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1),
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/* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1),
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/* SD_DATA2 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1),
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/* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1),
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/* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1),
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/* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1),
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/* SD_WP */ PAD_CFG_NF(GPP_G7, UP_20K, DEEP, NF1),
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/* BATLOW# */ PAD_CFG_NC(GPD0),
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/* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, PWROK, NF1),
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/* LAN_WAKE# */ PAD_CFG_NC(GPD2),
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/* PWRBTN# */ PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1),
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/* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, PWROK, NF1),
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/* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, PWROK, NF1),
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/* SLP_A# */ PAD_CFG_NF(GPD6, NONE, PWROK, NF1),
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/* RSVD */ PAD_CFG_NC(GPD7),
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/* SUSCLK */ PAD_CFG_NF(GPD8, NONE, PWROK, NF1),
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/* SLP_WLAN# */ PAD_CFG_NF(GPD9, NONE, PWROK, NF1),
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/* SLP_S5# */ PAD_CFG_NF(GPD10, NONE, PWROK, NF1),
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/* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1),
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};
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#endif
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#endif
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