182 lines
3.8 KiB
C
182 lines
3.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Helper functions for dealing with power management registers
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* and the differences between PCH variants.
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*/
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#define __SIMPLE_DEVICE__
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#include <console/console.h>
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#include <device/pci.h>
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#include <intelblocks/pmclib.h>
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#include <intelblocks/rtc.h>
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#include <soc/pci_devs.h>
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#include <soc/pm.h>
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#include <soc/pmc.h>
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#include <types.h>
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/*
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* SMI
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*/
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const char *const *soc_smi_sts_array(size_t *smi_arr)
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{
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static const char *const smi_sts_bits[] = {
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[2] = "BIOS",
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[3] = "LEGACY_USB",
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[4] = "SLP_SMI",
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[5] = "APM",
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[6] = "SWSMI_TMR",
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[7] = "BIOS_RLS",
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[8] = "PM1",
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[9] = "GPE0",
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[10] = "GPI",
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[11] = "MCSMI",
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[12] = "DEVMON",
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[13] = "TCO",
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[14] = "PERIODIC",
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[20] = "PCI_EXP_SMI",
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[23] = "IE_SMI",
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[25] = "SCC_SMI",
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[26] = "SPI",
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[27] = "GPIO_UNLOCK",
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[28] = "ESPI_SMI",
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[29] = "SERIAL_I/O",
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[30] = "ME_SMI",
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[31] = "XHCI",
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};
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*smi_arr = ARRAY_SIZE(smi_sts_bits);
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return smi_sts_bits;
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}
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/*
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* TCO
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*/
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const char *const *soc_tco_sts_array(size_t *tco_arr)
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{
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static const char *const tco_sts_bits[] = {
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[0] = "NMI2SMI",
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[1] = "OS_TCO",
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[2] = "TCO_INT",
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[3] = "TIMEOUT",
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[7] = "NEWCENTURY",
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[8] = "BIOSWR",
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[9] = "CPUSCI",
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[10] = "CPUSMI",
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[12] = "CPUSERR",
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[13] = "SLVSEL",
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[16] = "INTRD_DET",
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[17] = "SECOND_TO",
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[20] = "SMLINK_SLV"
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};
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*tco_arr = ARRAY_SIZE(tco_sts_bits);
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return tco_sts_bits;
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}
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/*
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* GPE0
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*/
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const char *const *soc_std_gpe_sts_array(size_t *gpe_arr)
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{
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static const char *const gpe_sts_bits[] = {
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};
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*gpe_arr = ARRAY_SIZE(gpe_sts_bits);
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return gpe_sts_bits;
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}
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uint8_t *pmc_mmio_regs(void)
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{
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return (void *)(uintptr_t) pci_read_config32(PCH_DEV_PMC, PWRMBASE);
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}
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uintptr_t soc_read_pmc_base(void)
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{
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return (uintptr_t) (pmc_mmio_regs());
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}
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uint32_t *soc_pmc_etr_addr(void)
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{
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/*
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* The pointer returned must not be cached, because the address depends on the
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* MMCONF base address and the assigned PCI bus number, which both may change
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* during the boot process!
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*/
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return pci_mmio_config32_addr(PCH_DEVFN_PMC << 12, ETR);
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}
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void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2)
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{
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/* No functionality for this yet */
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}
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int soc_get_rtc_failed(void)
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{
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uint32_t pmcon_b = pci_s_read_config32(PCH_DEV_PMC, GEN_PMCON_B);
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int rtc_fail = !!(pmcon_b & RTC_BATTERY_DEAD);
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if (rtc_fail)
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printk(BIOS_ERR, "%s: RTC battery dead or removed\n", __func__);
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return rtc_fail;
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}
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/* Return 0, 3, or 5 to indicate the previous sleep state. */
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int soc_prev_sleep_state(const struct chipset_power_state *ps, int prev_sleep_state)
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{
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/*
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* Check for any power failure to determine if this a wake from
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* S5 because the PCH does not set the WAK_STS bit when waking
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* from a true G3 state.
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*/
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if (!(ps->pm1_sts & WAK_STS) &&
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(ps->gen_pmcon_b & (PWR_FLR | SUS_PWR_FLR)))
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prev_sleep_state = ACPI_S5;
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return prev_sleep_state;
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}
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void soc_fill_power_state(struct chipset_power_state *ps)
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{
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uint8_t *pmc;
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ps->gen_pmcon_a = pci_read_config32(PCH_DEV_PMC, GEN_PMCON_A);
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ps->gen_pmcon_b = pci_read_config32(PCH_DEV_PMC, GEN_PMCON_B);
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pmc = pmc_mmio_regs();
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ps->gblrst_cause[0] = read32(pmc + GBLRST_CAUSE0);
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ps->gblrst_cause[1] = read32(pmc + GBLRST_CAUSE1);
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printk(BIOS_DEBUG, "GEN_PMCON: %08x %08x\n",
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ps->gen_pmcon_a, ps->gen_pmcon_b);
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printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n",
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ps->gblrst_cause[0], ps->gblrst_cause[1]);
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}
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/* STM Support */
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uint16_t get_pmbase(void)
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{
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return ACPI_BASE_ADDRESS;
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}
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/*
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* Set which power state system will be after reapplying
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* the power (from G3 State)
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*/
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void pmc_soc_set_afterg3_en(const bool on)
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{
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uint8_t reg8;
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reg8 = pci_read_config8(PCH_DEV_PMC, GEN_PMCON_B);
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if (on)
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reg8 &= ~SLEEP_AFTER_POWER_FAIL;
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else
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reg8 |= SLEEP_AFTER_POWER_FAIL;
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pci_write_config8(PCH_DEV_PMC, GEN_PMCON_B, reg8);
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}
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