125 lines
3.1 KiB
C
125 lines
3.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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#ifndef _SOC_PM_H_
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#define _SOC_PM_H_
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#include <acpi/acpi.h>
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#include <soc/gpe.h>
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#include <soc/iomap.h>
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#include <soc/pmc.h>
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/* ACPI_BASE_ADDRESS / PMBASE */
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#define PM1_STS 0x00
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#define WAK_STS (1 << 15)
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#define PCIEXPWAK_STS (1 << 14)
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#define PRBTNOR_STS (1 << 11)
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#define RTC_STS (1 << 10)
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#define PWRBTN_STS (1 << 8)
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#define GBL_STS (1 << 5)
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#define PM1_EN 0x02
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#define RTC_EN (1 << 10)
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#define PWRBTN_EN (1 << 8)
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#define GBL_EN (1 << 5)
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#define TMROF_EN (1 << 0)
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#define PM1_CNT 0x04
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#define GBL_RLS (1 << 2)
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#define SCI_EN (1 << 0)
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#define PM1_TMR 0x08
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#define SMI_EN 0x30
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#define ESPI_SMI_EN (1 << 28)
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#define PERIODIC_EN (1 << 14)
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#define TCO_SMI_EN (1 << 13)
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#define APMC_EN (1 << 5)
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#define SLP_SMI_EN (1 << 4)
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#define BIOS_EN (1 << 2)
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#define EOS (1 << 1)
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#define GBL_SMI_EN (1 << 0)
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#define SMI_STS 0x34
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#define SMI_STS_BITS 32
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#define XHCI_SMI_STS_BIT 31
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#define ME_SMI_STS_BIT 30
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#define SERIAL_IO_SMI_STS_BIT 29
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#define ESPI_SMI_STS_BIT 28
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#define GPIO_UNLOCK_SMI_STS_BIT 27
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#define SPI_SMI_STS_BIT 26
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#define SCC_SMI_STS_BIT 25
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#define IE_SMI_STS_BIT 23
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#define MONITOR_STS_BIT 21
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#define PCI_EXP_SMI_STS_BIT 20
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#define SMBUS_SMI_STS_BIT 16
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#define SERIRQ_SMI_STS_BIT 15
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#define PERIODIC_STS_BIT 14
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#define TCO_STS_BIT 13
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#define DEVMON_STS_BIT 12
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#define MCSMI_STS_BIT 11
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#define GPIO_STS_BIT 10
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#define GPE0_STS_BIT 9
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#define PM1_STS_BIT 8
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#define SWSMI_TMR_STS_BIT 6
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#define APM_STS_BIT 5
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#define SMI_ON_SLP_EN_STS_BIT 4
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#define LEGACY_USB_STS_BIT 3
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#define BIOS_STS_BIT 2
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#define GPE_CNTL 0x42
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#define SWGPE_CTRL (1 << 1)
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#define DEVACT_STS 0x44
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#define PM2_CNT 0x50
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#define GPE0_REG_MAX 4
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#define GPE0_REG_SIZE 32
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#define GPE0_STS(x) (0x80 + ((x) * 4))
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#define GPE0_EN(x) (0x90 + ((x) * 4))
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#define GPE_STD 3 /* 0x8c/0x9c = Standard GPE */
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#define GPE_STS_RSVD GPE_STD
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#define GPIO_T2_STS (1 << 15)
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#define PME_B0_STS (1 << 13)
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#define PME_STS (1 << 11)
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#define PCI_EXP_STS (1 << 9)
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#define SMB_WAK_STS (1 << 7)
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#define TCOSCI_STS (1 << 6)
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#define GPE0_EN(x) (0x90 + ((x) * 4))
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#define GPIO_T2_EN (1 << 15)
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#define ESPI_EN (1 << 14)
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#define PME_B0_EN (1 << 13)
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#define PME_EN (1 << 11)
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#define PCI_EXP_EN (1 << 9)
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#define TCOSCI_EN (1 << 6)
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#define ENABLE_SMI_PARAMS \
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(APMC_EN | GBL_SMI_EN | EOS)
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/* P-state configuration */
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#define PSS_MAX_ENTRIES 16
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#define PSS_RATIO_STEP 1
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#define PSS_LATENCY_TRANSITION 10
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#define PSS_LATENCY_BUSMASTER 10
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/* This is defined as ETR3 in EDS. We named it as ETR here for consistency */
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#define ETR 0xac
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#define CF9_LOCK (1 << 31)
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#define CF9_GLB_RST (1 << 20)
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#define PRSTS 0x10
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struct chipset_power_state {
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uint16_t pm1_sts;
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uint16_t pm1_en;
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uint32_t pm1_cnt;
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uint16_t tco1_sts;
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uint16_t tco2_sts;
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uint32_t gpe0_sts[4];
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uint32_t gpe0_en[4];
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uint32_t gen_pmcon_a;
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uint32_t gen_pmcon_b;
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uint32_t gblrst_cause[2];
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uint32_t prev_sleep_state;
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} __packed;
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/* Get base address PMC memory mapped registers. */
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uint8_t *pmc_mmio_regs(void);
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uint16_t get_pmbase(void);
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void pmc_lock_smi(void);
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#endif
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