63 lines
2.0 KiB
C
63 lines
2.0 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2018 MediaTek Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __SOC_MEDIATEK_MT8183_INCLUDE_SOC_ADDRESSMAP_H__
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#define __SOC_MEDIATEK_MT8183_INCLUDE_SOC_ADDRESSMAP_H__
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enum {
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MCUCFG_BASE = 0x0C530000,
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IO_PHYS = 0x10000000,
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};
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enum {
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CKSYS_BASE = IO_PHYS,
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INFRACFG_AO_BASE = IO_PHYS + 0x00001000,
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GPIO_BASE = IO_PHYS + 0x00005000,
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SPM_BASE = IO_PHYS + 0x00006000,
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RGU_BASE = IO_PHYS + 0x00007000,
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GPT_BASE = IO_PHYS + 0x00008000,
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EINT_BASE = IO_PHYS + 0x0000B000,
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APMIXED_BASE = IO_PHYS + 0x0000C000,
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PWRAP_BASE = IO_PHYS + 0x0000D000,
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EMI_BASE = IO_PHYS + 0x00219000,
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EMI_MPU_BASE = IO_PHYS + 0x00226000,
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DRAMC_CH_BASE = IO_PHYS + 0x00228000,
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SSPM_SRAM_BASE = IO_PHYS + 0x00400000,
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SSPM_CFG_BASE = IO_PHYS + 0x00440000,
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AUXADC_BASE = IO_PHYS + 0x01001000,
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UART0_BASE = IO_PHYS + 0x01002000,
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SPI0_BASE = IO_PHYS + 0x0100A000,
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SPI1_BASE = IO_PHYS + 0x01010000,
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SPI2_BASE = IO_PHYS + 0x01012000,
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SPI3_BASE = IO_PHYS + 0x01013000,
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SPI4_BASE = IO_PHYS + 0x01014000,
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SPI5_BASE = IO_PHYS + 0x01015000,
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SSUSB_MAC_BASE = IO_PHYS + 0x01200000,
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SSUSB_IPPC_BASE = IO_PHYS + 0x01203e00,
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IOCFG_RT_BASE = IO_PHYS + 0x01C50000,
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IOCFG_RM_BASE = IO_PHYS + 0x01D20000,
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IOCFG_RB_BASE = IO_PHYS + 0x01D30000,
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IOCFG_LB_BASE = IO_PHYS + 0x01E70000,
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IOCFG_LM_BASE = IO_PHYS + 0x01E80000,
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IOCFG_BL_BASE = IO_PHYS + 0x01E90000,
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EFUSEC_BASE = IO_PHYS + 0x01F10000,
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IOCFG_LT_BASE = IO_PHYS + 0x01F20000,
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IOCFG_TL_BASE = IO_PHYS + 0x01F30000,
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SSUSB_SIF_BASE = IO_PHYS + 0x01F40300,
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SMI_BASE = IO_PHYS + 0x04019000,
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};
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#endif
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