138 lines
3.8 KiB
C
138 lines
3.8 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Google Inc.
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* Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <stdint.h>
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#include <timestamp.h>
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#include <arch/io.h>
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#include <device/mmio.h>
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#include <device/pci_ops.h>
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#include <device/pci_def.h>
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#include <cpu/x86/lapic.h>
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#include <cbmem.h>
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#include <console/console.h>
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#include <console/usb.h>
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#include <drivers/intel/fsp1_0/fsp_util.h>
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#include <program_loading.h>
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#include <northbridge/intel/fsp_rangeley/northbridge.h>
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#include "southbridge/intel/fsp_rangeley/soc.h"
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#include "southbridge/intel/fsp_rangeley/gpio.h"
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#include "southbridge/intel/fsp_rangeley/romstage.h"
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#include <cpu/x86/msr.h>
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#include <cpu/x86/smm.h>
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#include "gpio.h"
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void main(FSP_INFO_HEADER *fsp_info_header)
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{
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uint32_t fd_mask = 0;
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uint32_t *func_dis = (uint32_t *)(DEFAULT_PBASE + PBASE_FUNC_DIS);
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/*
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* Do not use the Serial Console before it is setup.
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* This causes the I/O to clog and a side effect is
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* that the reset button stops functioning. So
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* instead just use outb so it doesn't output to the
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* console when CONFIG_CONSOLE_POST.
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*/
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outb(0x40, 0x80);
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timestamp_init(get_initial_timestamp());
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timestamp_add_now(TS_START_ROMSTAGE);
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/* Rangeley UART POR state is enabled */
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console_init();
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post_code(0x41);
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/* Enable GPIOs BAR */
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pci_write_config32(SOC_LPC_DEV, GBASE, DEFAULT_GPIOBASE|0x02);
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early_mainboard_romstage_entry();
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post_code(0x42);
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rangeley_sb_early_initialization();
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post_code(0x46);
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/* Program any required function disables */
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get_func_disables(&fd_mask);
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if (fd_mask != 0) {
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write32(func_dis, read32(func_dis) | fd_mask);
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/* Ensure posted write hits. */
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read32(func_dis);
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}
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timestamp_add_now(TS_BEFORE_INITRAM);
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/*
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* Call early init to initialize memory and chipset. This function returns
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* to the romstage_main_continue function with a pointer to the HOB
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* structure.
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*/
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post_code(0x47);
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printk(BIOS_DEBUG, "Starting the Intel FSP (early_init)\n");
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fsp_early_init(fsp_info_header);
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die("Uh Oh! fsp_early_init should not return here.\n");
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}
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/*******************************************************************************
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* The FSP early_init function returns to this function.
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* Memory is setup and the stack is set by the FSP.
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*/
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void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) {
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void *cbmem_hob_ptr;
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timestamp_add_now(TS_AFTER_INITRAM);
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post_code(0x48);
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printk(BIOS_DEBUG, "%s status: %x hob_list_ptr: %x\n",
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__func__, (u32) status, (u32) hob_list_ptr);
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/* FSP reconfigures USB, so reinit it to have debug */
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if (CONFIG(USBDEBUG_IN_PRE_RAM))
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usbdebug_hw_init(true);
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printk(BIOS_DEBUG, "FSP Status: 0x%0x\n", (u32)status);
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post_code(0x4b);
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late_mainboard_romstage_entry();
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post_code(0x4c);
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/* Decode E0000 and F0000 segment to DRAM */
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sideband_write(B_UNIT, BMISC, sideband_read(B_UNIT, BMISC) | (1 << 1) | (1 << 0));
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cbmem_recovery(0);
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/* Save the HOB pointer in CBMEM to be used in ramstage*/
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cbmem_hob_ptr = cbmem_add(CBMEM_ID_HOB_POINTER, sizeof(*hob_list_ptr));
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if (cbmem_hob_ptr == NULL)
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die("Could not allocate cbmem for HOB pointer");
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*(u32*)cbmem_hob_ptr = (u32)hob_list_ptr;
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post_code(0x4e);
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if (CONFIG(SMM_TSEG))
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smm_list_regions();
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/* Load the ramstage. */
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post_code(0x4f);
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run_ramstage();
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while (1);
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}
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uint64_t get_initial_timestamp(void)
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{
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return 0;
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}
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