186 lines
5.1 KiB
C
186 lines
5.1 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Google Inc.
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* Copyright (C) 2015-2016 Intel Corp.
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* Copyright (C) 2017 Siemens AG
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <stddef.h>
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#include <device/pci_ops.h>
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#include <arch/cbfs.h>
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#include <cbmem.h>
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#include <console/console.h>
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#include <console/usb.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/smm.h>
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#include <program_loading.h>
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#include <timestamp.h>
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#include <version.h>
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#include <drivers/intel/fsp1_0/fsp_util.h>
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#include <pc80/mc146818rtc.h>
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#include <soc/iomap.h>
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#include <soc/lpc.h>
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#include <soc/memory.h>
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#include <soc/pci_devs.h>
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#include <soc/romstage.h>
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#include <soc/gpio.h>
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#include <soc/vtd.h>
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#include <soc/ubox.h>
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#include <build.h>
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static void init_rtc(void)
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{
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u16 gen_pmcon3 = pci_read_config16(PCI_DEV(0, LPC_DEV, LPC_FUNC), GEN_PMCON_3);
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if (gen_pmcon3 & RTC_PWR_STS) {
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printk(BIOS_DEBUG, "RTC Failure detected. Resetting Date to %s\n",
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coreboot_dmi_date);
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}
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cmos_init(gen_pmcon3 & RTC_PWR_STS);
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}
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/* Set up IO address range and enable it for the GPIO block. */
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static void setup_gpio_io_address(void)
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{
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pci_write_config32(PCI_DEV(0, LPC_DEV, LPC_FUNC), GPIO_BASE_ADR_OFFSET,
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GPIO_BASE_ADDRESS);
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pci_write_config8(PCI_DEV(0, LPC_DEV, LPC_FUNC), GPIO_CTRL_OFFSET,
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GPIO_DECODE_ENABLE);
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}
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static void enable_integrated_uart(uint8_t port)
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{
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uint32_t reg32, busno1 = 0, ubox_uart_en = 0, dfx1 = 0;
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pci_devfn_t vtd_dev, ubox_dev;
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vtd_dev = PCI_DEV(BUS0, VTD_DEV, VTD_FUNC);
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/* Figure out what bus number is assigned for CPUBUSNO(1) */
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reg32 = pci_mmio_read_config32(vtd_dev, VTD_CPUBUSNO);
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busno1 = (reg32 >> VTD_CPUBUSNO_BUS1_SHIFT) & VTD_CPUBUSNO_BUS1_MASK;
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/* UBOX sits on CPUBUSNO(1) */
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ubox_dev = PCI_DEV(busno1, UBOX_DEV, UBOX_FUNC);
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uint32_t reset_sts = pci_mmio_read_config32(ubox_dev, UBOX_SC_RESET_STATUS);
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/* In case we are in bypass mode do nothing */
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if (reset_sts & UBOX_SC_BYPASS)
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return;
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dfx1 = pci_mmio_read_config32(vtd_dev, VTD_DFX1);
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ubox_uart_en = pci_mmio_read_config32(ubox_dev, UBOX_UART_ENABLE);
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switch (port) {
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case 0:
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ubox_uart_en |= UBOX_UART_ENABLE_PORT0;
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dfx1 |= VTD_DFX1_RANGE_3F8_DISABLE;
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break;
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case 1:
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ubox_uart_en |= UBOX_UART_ENABLE_PORT1;
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dfx1 |= VTD_DFX1_RANGE_2F8_DISABLE;
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break;
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default:
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printk(BIOS_ERR, "incorrect port number\n");
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return;
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}
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/* Disable decoding and enable the port we want */
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pci_mmio_write_config32(vtd_dev, VTD_DFX1, dfx1);
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pci_mmio_write_config32(ubox_dev, UBOX_UART_ENABLE, ubox_uart_en);
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}
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/* Entry from cache-as-ram.inc. */
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void *asmlinkage main(FSP_INFO_HEADER *fsp_info_header)
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{
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post_code(0x40);
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if (!CONFIG(INTEGRATED_UART)) {
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/* Enable decoding of I/O locations for Super I/O devices */
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pci_write_config16(PCI_DEV(0x0, LPC_DEV, LPC_FUNC),
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LPC_IO_DEC, 0x0010);
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pci_write_config16(PCI_DEV(0x0, LPC_DEV, LPC_FUNC),
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LPC_EN, 0x340f);
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} else {
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enable_integrated_uart(CONFIG_UART_FOR_CONSOLE);
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}
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/* Call into mainboard. */
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post_code(0x41);
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early_mainboard_romstage_entry();
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post_code(0x42);
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console_init();
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init_rtc();
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setup_gpio_io_address();
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/*
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* Call early init to initialize memory and chipset. This function returns
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* to the romstage_main_continue function with a pointer to the HOB
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* structure.
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*/
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post_code(0x48);
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printk(BIOS_DEBUG, "Starting the Intel FSP (early_init)\n");
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fsp_early_init(fsp_info_header);
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die_with_post_code(POST_INVALID_VENDOR_BINARY,
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"Uh Oh! fsp_early_init should not return here.\n");
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}
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/*******************************************************************************
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* The FSP early_init function returns to this function.
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* Memory is set up and the stack is set by the FSP.
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*/
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void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr)
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{
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void *cbmem_hob_ptr;
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post_code(0x4a);
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timestamp_init(get_initial_timestamp());
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timestamp_add_now(TS_AFTER_INITRAM);
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printk(BIOS_DEBUG, "%s status: %x hob_list_ptr: %x\n",
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__func__, (u32) status, (u32) hob_list_ptr);
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/* FSP reconfigures USB, so reinit it to have debug */
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if (CONFIG(USBDEBUG_IN_PRE_RAM))
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usbdebug_hw_init(true);
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printk(BIOS_DEBUG, "FSP Status: 0x%0x\n", (u32)status);
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post_code(0x4b);
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late_mainboard_romstage_entry();
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post_code(0x4d);
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cbmem_recovery(0);
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/* Save the HOB pointer in CBMEM to be used in ramstage*/
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cbmem_hob_ptr = cbmem_add(CBMEM_ID_HOB_POINTER, sizeof(*hob_list_ptr));
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if (cbmem_hob_ptr == NULL)
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die("Could not allocate cbmem for HOB pointer");
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*(u32 *)cbmem_hob_ptr = (u32)hob_list_ptr;
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if (!CONFIG(FSP_MEMORY_DOWN))
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save_dimm_info();
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if (CONFIG(SMM_TSEG))
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smm_list_regions();
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/* Load the ramstage. */
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post_code(0x4e);
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run_ramstage();
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while (1);
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}
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uint64_t get_initial_timestamp(void)
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{
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return 0;
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}
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