277 lines
7.0 KiB
C
277 lines
7.0 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Google Inc.
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* Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <stddef.h>
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#include <arch/io.h>
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#include <device/mmio.h>
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#include <device/pci_ops.h>
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#include <arch/cbfs.h>
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#include <arch/early_variables.h>
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#include <console/console.h>
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#include <console/usb.h>
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#include <cbmem.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/smm.h>
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#include <program_loading.h>
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#include <romstage_handoff.h>
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#include <timestamp.h>
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#include <soc/gpio.h>
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#include <soc/iomap.h>
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#include <soc/lpc.h>
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#include <soc/pci_devs.h>
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#include <soc/romstage.h>
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#include <soc/acpi.h>
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#include <soc/baytrail.h>
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#include <drivers/intel/fsp1_0/fsp_util.h>
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#include <soc/pmc.h>
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#include <soc/spi.h>
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#include <version.h>
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#include <pc80/mc146818rtc.h>
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#include <device/pci_def.h>
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#include <security/vboot/vboot_common.h>
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/* Return 0, 3, 4 or 5 to indicate the previous sleep state. */
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uint32_t chipset_prev_sleep_state(uint32_t clear)
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{
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/* Default to S0. */
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uint32_t prev_sleep_state = ACPI_S0;
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uint32_t pm1_sts;
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uint32_t pm1_cnt;
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uint32_t gen_pmcon1;
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/* Read Power State */
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pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS);
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pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
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gen_pmcon1 = read32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1));
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printk(BIOS_DEBUG, "PM1_STS = 0x%x PM1_CNT = 0x%x GEN_PMCON1 = 0x%x\n",
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pm1_sts, pm1_cnt, gen_pmcon1);
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if (pm1_sts & WAK_STS) {
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switch (acpi_sleep_from_pm1(pm1_cnt)) {
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case ACPI_S3:
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if (CONFIG(HAVE_ACPI_RESUME))
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prev_sleep_state = ACPI_S3;
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break;
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case ACPI_S4:
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prev_sleep_state = ACPI_S4;
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break;
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case ACPI_S5:
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prev_sleep_state = ACPI_S5;
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break;
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}
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/* If set Clear SLP_TYP. */
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if (clear == 1) {
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outl(pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT);
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}
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}
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if (gen_pmcon1 & (PWR_FLR | SUS_PWR_FLR)) {
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prev_sleep_state = ACPI_S5;
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}
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return prev_sleep_state;
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}
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static void program_base_addresses(void)
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{
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uint32_t reg;
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/* Memory Mapped IO registers. */
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reg = PMC_BASE_ADDRESS | SET_BAR_ENABLE;
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pci_write_config32(LPC_BDF, PBASE, reg);
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reg = IO_BASE_ADDRESS | SET_BAR_ENABLE;
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pci_write_config32(LPC_BDF, IOBASE, reg);
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reg = ILB_BASE_ADDRESS | SET_BAR_ENABLE;
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pci_write_config32(LPC_BDF, IBASE, reg);
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reg = SPI_BASE_ADDRESS | SET_BAR_ENABLE;
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pci_write_config32(LPC_BDF, SBASE, reg);
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reg = MPHY_BASE_ADDRESS | SET_BAR_ENABLE;
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pci_write_config32(LPC_BDF, MPBASE, reg);
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reg = PUNIT_BASE_ADDRESS | SET_BAR_ENABLE;
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pci_write_config32(LPC_BDF, PUBASE, reg);
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reg = RCBA_BASE_ADDRESS | RCBA_ENABLE;
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pci_write_config32(LPC_BDF, RCBA, reg);
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/* IO Port Registers. */
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reg = ACPI_BASE_ADDRESS | SET_BAR_ENABLE;
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pci_write_config32(LPC_BDF, ABASE, reg);
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reg = GPIO_BASE_ADDRESS | SET_BAR_ENABLE;
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pci_write_config32(LPC_BDF, GBASE, reg);
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}
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static void spi_init(void)
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{
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uint32_t *scs = (uint32_t *)(SPI_BASE_ADDRESS + SCS);
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uint32_t *bcr = (uint32_t *)(SPI_BASE_ADDRESS + BCR);
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uint32_t reg;
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/* Disable generating SMI when setting WPD bit. */
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write32(scs, read32(scs) & ~SMIWPEN);
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/*
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* Enable caching and prefetching in the SPI controller. Disable
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* the SMM-only BIOS write and set WPD bit.
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*/
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reg = (read32(bcr) & ~SRC_MASK) | SRC_CACHE_PREFETCH | BCR_WPD;
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reg &= ~EISS;
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write32(bcr, reg);
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}
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static void baytrail_rtc_init(void)
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{
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uint32_t *pbase = (uint32_t *)(pci_read_config32(LPC_BDF, PBASE) & 0xfffffff0);
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uint32_t gen_pmcon1 = read32(pbase + (GEN_PMCON1/sizeof(u32)));
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int rtc_failed = !!(gen_pmcon1 & RPS);
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if (rtc_failed) {
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printk(BIOS_DEBUG,
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"RTC Failure detected. Resetting Date to %s\n",
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coreboot_dmi_date);
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write32((uint32_t *)(DEFAULT_PBASE + GEN_PMCON1), gen_pmcon1 & ~RPS);
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}
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cmos_init(rtc_failed);
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}
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/* Entry from cache-as-ram.inc. */
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void main(FSP_INFO_HEADER *fsp_info_header)
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{
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uint32_t *func_dis = (uint32_t *)(PMC_BASE_ADDRESS + FUNC_DIS);
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uint32_t *func_dis2 = (uint32_t *)(PMC_BASE_ADDRESS + FUNC_DIS2);
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uint32_t fd_mask = 0;
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uint32_t fd2_mask = 0;
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post_code(0x40);
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timestamp_init(get_initial_timestamp());
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timestamp_add_now(TS_START_ROMSTAGE);
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program_base_addresses();
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post_code(0x41);
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tco_disable();
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post_code(0x42);
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byt_config_com1_and_enable();
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post_code(0x43);
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console_init();
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spi_init();
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baytrail_rtc_init();
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/* Call into mainboard. */
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early_mainboard_romstage_entry();
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set_max_freq();
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post_code(0x44);
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/* Program any required function disables */
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get_func_disables(&fd_mask, &fd2_mask);
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if (fd_mask != 0) {
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write32(func_dis, read32(func_dis) | fd_mask);
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/* Ensure posted write hits. */
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read32(func_dis);
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}
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if (fd2_mask != 0) {
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write32(func_dis2, read32(func_dis2) | fd2_mask);
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/* Ensure posted write hits. */
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read32(func_dis2);
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}
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post_code(0x47);
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timestamp_add_now(TS_BEFORE_INITRAM);
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/*
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* Call early init to initialize memory and chipset. This function returns
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* to the romstage_main_continue function with a pointer to the HOB
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* structure.
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*/
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post_code(0x48);
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printk(BIOS_DEBUG, "Starting the Intel FSP (early_init)\n");
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fsp_early_init(fsp_info_header);
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die_with_post_code(POST_INVALID_VENDOR_BINARY,
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"Uh Oh! fsp_early_init should not return here.\n");
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}
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/*******************************************************************************
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* The FSP early_init function returns to this function.
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* Memory is setup and the stack is set by the FSP.
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*/
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void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr)
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{
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void *cbmem_hob_ptr;
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uint32_t prev_sleep_state;
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timestamp_add_now(TS_AFTER_INITRAM);
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post_code(0x4a);
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printk(BIOS_DEBUG, "%s status: %x hob_list_ptr: %x\n",
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__func__, (u32) status, (u32) hob_list_ptr);
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/* FSP reconfigures USB, so reinit it to have debug */
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if (CONFIG(USBDEBUG_IN_PRE_RAM))
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usbdebug_hw_init(true);
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printk(BIOS_DEBUG, "FSP Status: 0x%0x\n", (u32)status);
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/* Get previous sleep state again and clear */
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prev_sleep_state = chipset_prev_sleep_state(1);
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printk(BIOS_DEBUG, "%s: prev_sleep_state = S%d\n", __func__, prev_sleep_state);
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report_platform_info();
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post_code(0x4b);
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late_mainboard_romstage_entry();
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post_code(0x4c);
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cbmem_recovery(prev_sleep_state == ACPI_S3);
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/* Save the HOB pointer in CBMEM to be used in ramstage*/
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cbmem_hob_ptr = cbmem_add(CBMEM_ID_HOB_POINTER, sizeof(*hob_list_ptr));
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if (cbmem_hob_ptr == NULL)
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die("Could not allocate cbmem for HOB pointer");
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*(u32*)cbmem_hob_ptr = (u32)hob_list_ptr;
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post_code(0x4e);
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romstage_handoff_init(prev_sleep_state == ACPI_S3);
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if (CONFIG(SMM_TSEG))
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smm_list_regions();
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/* Load the ramstage. */
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post_code(0x4f);
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run_ramstage();
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while (1);
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}
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uint64_t get_initial_timestamp(void)
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{
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return 0;
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}
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int vboot_platform_is_resuming(void)
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{
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return !!romstage_handoff_is_resume();
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}
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