273 lines
7.2 KiB
C
273 lines
7.2 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <stddef.h>
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#include <arch/cpu.h>
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#include <arch/io.h>
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#include <device/mmio.h>
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#include <device/pci_ops.h>
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#include <bootblock_common.h>
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#include <console/console.h>
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#include <cbmem.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/smm.h>
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#if CONFIG(EC_GOOGLE_CHROMEEC)
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#include <ec/google/chromeec/ec.h>
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#endif
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#include <elog.h>
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#include <program_loading.h>
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#include <romstage_handoff.h>
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#include <stage_cache.h>
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#include <string.h>
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#include <timestamp.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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#include <soc/gpio.h>
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#include <soc/iomap.h>
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#include <soc/lpc.h>
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#include <soc/pci_devs.h>
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#include <soc/pmc.h>
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#include <soc/romstage.h>
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#include <soc/smm.h>
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#include <soc/spi.h>
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/* The cache-as-ram assembly file calls romstage_main() after setting up
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* cache-as-ram. romstage_main() will then call the mainboards's
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* mainboard_romstage_entry() function. That function then calls
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* romstage_common() below. The reason for the back and forth is to provide
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* common entry point from cache-as-ram while still allowing for code sharing.
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* Because we can't use global variables the stack is used for allocations --
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* thus the need to call back and forth. */
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static struct postcar_frame early_mtrrs;
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static void fill_postcar_frame(struct postcar_frame *pcf);
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/* prepare_and_run_postcar() determines the stack to use after
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* cache-as-ram is torn down as well as the MTRR settings to use. */
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static void prepare_and_run_postcar(struct postcar_frame *pcf)
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{
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if (postcar_frame_init(pcf, 0))
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die("Unable to initialize postcar frame.\n");
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fill_postcar_frame(pcf);
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postcar_frame_common_mtrrs(pcf);
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run_postcar_phase(pcf);
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/* We do not return here. */
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}
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static void program_base_addresses(void)
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{
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uint32_t reg;
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const uint32_t lpc_dev = PCI_DEV(0, LPC_DEV, LPC_FUNC);
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/* Memory Mapped IO registers. */
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reg = PMC_BASE_ADDRESS | 2;
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pci_write_config32(lpc_dev, PBASE, reg);
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reg = IO_BASE_ADDRESS | 2;
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pci_write_config32(lpc_dev, IOBASE, reg);
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reg = ILB_BASE_ADDRESS | 2;
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pci_write_config32(lpc_dev, IBASE, reg);
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reg = SPI_BASE_ADDRESS | 2;
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pci_write_config32(lpc_dev, SBASE, reg);
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reg = MPHY_BASE_ADDRESS | 2;
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pci_write_config32(lpc_dev, MPBASE, reg);
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reg = PUNIT_BASE_ADDRESS | 2;
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pci_write_config32(lpc_dev, PUBASE, reg);
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reg = RCBA_BASE_ADDRESS | 1;
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pci_write_config32(lpc_dev, RCBA, reg);
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/* IO Port Registers. */
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reg = ACPI_BASE_ADDRESS | 2;
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pci_write_config32(lpc_dev, ABASE, reg);
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reg = GPIO_BASE_ADDRESS | 2;
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pci_write_config32(lpc_dev, GBASE, reg);
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}
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static void spi_init(void)
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{
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u32 *scs = (u32 *)(SPI_BASE_ADDRESS + SCS);
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u32 *bcr = (u32 *)(SPI_BASE_ADDRESS + BCR);
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uint32_t reg;
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/* Disable generating SMI when setting WPD bit. */
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write32(scs, read32(scs) & ~SMIWPEN);
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/*
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* Enable caching and prefetching in the SPI controller. Disable
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* the SMM-only BIOS write and set WPD bit.
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*/
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reg = (read32(bcr) & ~SRC_MASK) | SRC_CACHE_PREFETCH | BCR_WPD;
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reg &= ~EISS;
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write32(bcr, reg);
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}
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/* Entry from cache-as-ram.inc. */
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static void romstage_main(uint64_t tsc, uint32_t bist)
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{
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struct romstage_params rp = {
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.bist = bist,
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.mrc_params = NULL,
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};
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/* Save initial timestamp from bootblock. */
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timestamp_init(tsc);
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/* Save romstage begin */
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timestamp_add_now(TS_START_ROMSTAGE);
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program_base_addresses();
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tco_disable();
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byt_config_com1_and_enable();
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console_init();
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spi_init();
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set_max_freq();
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punit_init();
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gfx_init();
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/* Call into mainboard. */
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mainboard_romstage_entry(&rp);
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if (CONFIG(SMM_TSEG))
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smm_list_regions();
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prepare_and_run_postcar(&early_mtrrs);
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/* We do not return here. */
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}
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/* This wrapper enables easy transition towards C_ENVIRONMENT_BOOTBLOCK,
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* keeping changes in cache_as_ram.S easy to manage.
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*/
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asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist)
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{
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romstage_main(base_timestamp, bist);
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}
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static struct chipset_power_state power_state;
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static void migrate_power_state(int is_recovery)
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{
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struct chipset_power_state *ps_cbmem;
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struct chipset_power_state *ps_car;
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ps_car = &power_state;
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ps_cbmem = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(*ps_cbmem));
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if (ps_cbmem == NULL) {
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printk(BIOS_DEBUG, "Not adding power state to cbmem!\n");
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return;
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}
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memcpy(ps_cbmem, ps_car, sizeof(*ps_cbmem));
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}
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ROMSTAGE_CBMEM_INIT_HOOK(migrate_power_state)
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static struct chipset_power_state *fill_power_state(void)
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{
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struct chipset_power_state *ps = &power_state;
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ps->pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS);
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ps->pm1_en = inw(ACPI_BASE_ADDRESS + PM1_EN);
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ps->pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
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ps->gpe0_sts = inl(ACPI_BASE_ADDRESS + GPE0_STS);
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ps->gpe0_en = inl(ACPI_BASE_ADDRESS + GPE0_EN);
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ps->tco_sts = inl(ACPI_BASE_ADDRESS + TCO_STS);
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ps->prsts = read32((u32 *)(PMC_BASE_ADDRESS + PRSTS));
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ps->gen_pmcon1 = read32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1));
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ps->gen_pmcon2 = read32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON2));
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printk(BIOS_DEBUG, "pm1_sts: %04x pm1_en: %04x pm1_cnt: %08x\n",
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ps->pm1_sts, ps->pm1_en, ps->pm1_cnt);
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printk(BIOS_DEBUG, "gpe0_sts: %08x gpe0_en: %08x tco_sts: %08x\n",
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ps->gpe0_sts, ps->gpe0_en, ps->tco_sts);
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printk(BIOS_DEBUG, "prsts: %08x gen_pmcon1: %08x gen_pmcon2: %08x\n",
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ps->prsts, ps->gen_pmcon1, ps->gen_pmcon2);
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return ps;
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}
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/* Return 0, 3, or 5 to indicate the previous sleep state. */
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static int chipset_prev_sleep_state(struct chipset_power_state *ps)
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{
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/* Default to S0. */
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int prev_sleep_state = ACPI_S0;
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if (ps->pm1_sts & WAK_STS) {
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switch (acpi_sleep_from_pm1(ps->pm1_cnt)) {
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case ACPI_S3:
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if (CONFIG(HAVE_ACPI_RESUME))
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prev_sleep_state = ACPI_S3;
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break;
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case ACPI_S5:
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prev_sleep_state = ACPI_S5;
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break;
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}
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/* Clear SLP_TYP. */
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outl(ps->pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT);
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}
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if (ps->gen_pmcon1 & (PWR_FLR | SUS_PWR_FLR)) {
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prev_sleep_state = ACPI_S5;
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}
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return prev_sleep_state;
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}
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/* Entry from the mainboard. */
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void romstage_common(struct romstage_params *params)
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{
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struct chipset_power_state *ps;
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int prev_sleep_state;
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timestamp_add_now(TS_BEFORE_INITRAM);
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ps = fill_power_state();
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prev_sleep_state = chipset_prev_sleep_state(ps);
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printk(BIOS_DEBUG, "prev_sleep_state = S%d\n", prev_sleep_state);
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#if CONFIG(ELOG_BOOT_COUNT)
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if (prev_sleep_state != ACPI_S3)
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boot_count_increment();
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#endif
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/* Initialize RAM */
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raminit(params->mrc_params, prev_sleep_state);
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timestamp_add_now(TS_AFTER_INITRAM);
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romstage_handoff_init(prev_sleep_state == ACPI_S3);
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}
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static void fill_postcar_frame(struct postcar_frame *pcf)
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{
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uintptr_t top_of_ram;
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/* Cache at least 8 MiB below the top of ram, and at most 8 MiB
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* above top of the ram. This satisfies MTRR alignment requirement
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* with different TSEG size configurations.
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*/
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top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB);
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postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 16*MiB,
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MTRR_TYPE_WRBACK);
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}
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