250 lines
7.1 KiB
C
250 lines
7.1 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015-2016 Advanced Micro Devices, Inc.
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* Copyright (C) 2015 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <device/pci_ops.h>
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#include <arch/cpu.h>
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#include <arch/acpi.h>
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#include <cpu/x86/msr.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/smm.h>
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#include <cpu/amd/mtrr.h>
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#include <cbmem.h>
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#include <commonlib/helpers.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <program_loading.h>
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#include <romstage_handoff.h>
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#include <elog.h>
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#include <amdblocks/agesawrapper.h>
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#include <amdblocks/agesawrapper_call.h>
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#include <soc/northbridge.h>
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#include <soc/romstage.h>
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#include <soc/southbridge.h>
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#include <amdblocks/psp.h>
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#include "chip.h"
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void __weak mainboard_romstage_entry(int s3_resume)
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{
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/* By default, don't do anything */
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}
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static void load_smu_fw1(void)
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{
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u32 base, limit, cmd;
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/* Open a posted hole from 0x80000000 : 0xfed00000-1 */
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base = (0x80000000 >> 8) | MMIO_WE | MMIO_RE;
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limit = (ALIGN_DOWN(HPET_BASE_ADDRESS - 1, 64 * KiB) >> 8);
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pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_LIMIT0_LO, limit);
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pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_BASE0_LO, base);
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/* Preload a value into "BAR3" and enable it */
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pci_write_config32(SOC_PSP_DEV, PSP_MAILBOX_BAR, PSP_MAILBOX_BAR3_BASE);
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pci_write_config32(SOC_PSP_DEV, PSP_BAR_ENABLES, PSP_MAILBOX_BAR_EN);
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/* Enable memory access and master */
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cmd = pci_read_config32(SOC_PSP_DEV, PCI_COMMAND);
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cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
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pci_write_config32(SOC_PSP_DEV, PCI_COMMAND, cmd);
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psp_load_named_blob(MBOX_BIOS_CMD_SMU_FW, "smu_fw");
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}
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static void agesa_call(void)
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{
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post_code(0x37);
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do_agesawrapper(AMD_INIT_RESET, "amdinitreset");
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post_code(0x38);
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/* APs will not exit amdinitearly */
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do_agesawrapper(AMD_INIT_EARLY, "amdinitearly");
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}
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static void bsp_agesa_call(void)
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{
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set_ap_entry_ptr(agesa_call); /* indicate the path to the AP */
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agesa_call();
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}
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asmlinkage void car_stage_entry(void)
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{
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struct postcar_frame pcf;
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uintptr_t top_of_ram;
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uintptr_t smm_base;
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size_t smm_size;
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msr_t base, mask;
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msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR);
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int vmtrrs = mtrr_cap.lo & MTRR_CAP_VCNT;
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int s3_resume = acpi_s3_resume_allowed() && acpi_is_wakeup_s3();
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int i;
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console_init();
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if (CONFIG(SOC_AMD_PSP_SELECTABLE_SMU_FW))
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load_smu_fw1();
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mainboard_romstage_entry(s3_resume);
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bsp_agesa_call();
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if (!s3_resume) {
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post_code(0x40);
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do_agesawrapper(AMD_INIT_POST, "amdinitpost");
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post_code(0x41);
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/*
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* TODO: This is a hack to work around current AGESA behavior.
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* AGESA needs to change to reflect that coreboot owns
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* the MTRRs.
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*
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* After setting up DRAM, AGESA also completes the configuration
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* of the MTRRs, setting regions to WB. Anything written to
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* memory between now and and when CAR is dismantled will be
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* in cache and lost. For now, set the regions UC to ensure
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* the writes get to DRAM.
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*/
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for (i = 0 ; i < vmtrrs ; i++) {
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base = rdmsr(MTRR_PHYS_BASE(i));
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mask = rdmsr(MTRR_PHYS_MASK(i));
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if (!(mask.lo & MTRR_PHYS_MASK_VALID))
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continue;
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if ((base.lo & 0x7) == MTRR_TYPE_WRBACK) {
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base.lo &= ~0x7;
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base.lo |= MTRR_TYPE_UNCACHEABLE;
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wrmsr(MTRR_PHYS_BASE(i), base);
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}
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}
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/* Disable WB from to region 4GB-TOM2. */
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msr_t sys_cfg = rdmsr(SYSCFG_MSR);
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sys_cfg.lo &= ~SYSCFG_MSR_TOM2WB;
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wrmsr(SYSCFG_MSR, sys_cfg);
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if (CONFIG(ELOG_BOOT_COUNT))
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boot_count_increment();
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} else {
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printk(BIOS_INFO, "S3 detected\n");
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post_code(0x60);
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do_agesawrapper(AMD_INIT_RESUME, "amdinitresume");
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post_code(0x61);
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}
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post_code(0x42);
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psp_notify_dram();
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post_code(0x43);
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if (cbmem_recovery(s3_resume))
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printk(BIOS_CRIT, "Failed to recover cbmem\n");
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if (romstage_handoff_init(s3_resume))
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printk(BIOS_ERR, "Failed to set romstage handoff data\n");
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if (CONFIG(SMM_TSEG))
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smm_list_regions();
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post_code(0x44);
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if (postcar_frame_init(&pcf, 0))
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die("Unable to initialize postcar frame.\n");
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/*
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* We need to make sure ramstage will be run cached. At this point exact
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* location of ramstage in cbmem is not known. Instruct postcar to cache
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* 16 megs under cbmem top which is a safe bet to cover ramstage.
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*/
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top_of_ram = (uintptr_t) cbmem_top();
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postcar_frame_add_mtrr(&pcf, top_of_ram - 16*MiB, 16*MiB,
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MTRR_TYPE_WRBACK);
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/* Cache the memory-mapped boot media. */
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postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
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/*
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* Cache the TSEG region at the top of ram. This region is
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* not restricted to SMM mode until SMM has been relocated.
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* By setting the region to cacheable it provides faster access
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* when relocating the SMM handler as well as using the TSEG
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* region for other purposes.
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*/
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smm_region(&smm_base, &smm_size);
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postcar_frame_add_mtrr(&pcf, smm_base, smm_size, MTRR_TYPE_WRBACK);
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post_code(0x45);
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run_postcar_phase(&pcf);
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post_code(0x50); /* Should never see this post code. */
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}
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void SetMemParams(AMD_POST_PARAMS *PostParams)
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{
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const struct soc_amd_stoneyridge_config *cfg;
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const struct device *dev = pcidev_path_on_root(GNB_DEVFN);
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if (!dev || !dev->chip_info) {
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printk(BIOS_ERR, "ERROR: Cannot find SoC devicetree config\n");
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/* In case of a BIOS error, only attempt to set UMA. */
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PostParams->MemConfig.UmaMode = CONFIG(GFXUMA) ?
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UMA_AUTO : UMA_NONE;
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return;
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}
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cfg = dev->chip_info;
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PostParams->MemConfig.EnableMemClr = cfg->dram_clear_on_reset;
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switch (cfg->uma_mode) {
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case UMAMODE_NONE:
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PostParams->MemConfig.UmaMode = UMA_NONE;
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break;
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case UMAMODE_SPECIFIED_SIZE:
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PostParams->MemConfig.UmaMode = UMA_SPECIFIED;
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/* 64 KiB blocks. */
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PostParams->MemConfig.UmaSize = cfg->uma_size / (64 * KiB);
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break;
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case UMAMODE_AUTO_LEGACY:
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PostParams->MemConfig.UmaMode = UMA_AUTO;
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PostParams->MemConfig.UmaVersion = UMA_LEGACY;
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break;
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case UMAMODE_AUTO_NON_LEGACY:
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PostParams->MemConfig.UmaMode = UMA_AUTO;
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PostParams->MemConfig.UmaVersion = UMA_NON_LEGACY;
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break;
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}
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}
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void soc_customize_init_early(AMD_EARLY_PARAMS *InitEarly)
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{
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const struct soc_amd_stoneyridge_config *cfg;
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const struct device *dev = pcidev_path_on_root(GNB_DEVFN);
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struct _PLATFORM_CONFIGURATION *platform;
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if (!dev || !dev->chip_info) {
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printk(BIOS_WARNING, "Warning: Cannot find SoC devicetree"
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" config, STAPM unchanged\n");
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return;
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}
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cfg = dev->chip_info;
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platform = &InitEarly->PlatformConfig;
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if ((cfg->stapm_percent) && (cfg->stapm_time_ms) &&
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(cfg->stapm_power_mw)) {
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platform->PlatStapmConfig.CfgStapmScalar = cfg->stapm_percent;
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platform->PlatStapmConfig.CfgStapmTimeConstant =
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cfg->stapm_time_ms;
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platform->PkgPwrLimitDC = cfg->stapm_power_mw;
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platform->PkgPwrLimitAC = cfg->stapm_power_mw;
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platform->PlatStapmConfig.CfgStapmBoost = StapmBoostEnabled;
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}
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}
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