104 lines
2.8 KiB
C
104 lines
2.8 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015-2016 Advanced Micro Devices, Inc.
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* Copyright (C) 2015 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <device/pci_ops.h>
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#include <arch/cpu.h>
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#include <arch/acpi.h>
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#include <cpu/x86/msr.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/smm.h>
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#include <cpu/amd/mtrr.h>
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#include <cbmem.h>
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#include <commonlib/helpers.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <program_loading.h>
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#include <romstage_handoff.h>
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#include <elog.h>
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#include <soc/northbridge.h>
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#include <soc/romstage.h>
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#include <soc/southbridge.h>
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#include "chip.h"
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void __weak mainboard_romstage_entry(int s3_resume)
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{
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/* By default, don't do anything */
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}
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asmlinkage void car_stage_entry(void)
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{
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struct postcar_frame pcf;
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uintptr_t top_of_ram;
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uintptr_t smm_base;
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size_t smm_size;
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int s3_resume = acpi_s3_resume_allowed() && acpi_is_wakeup_s3();
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console_init();
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mainboard_romstage_entry(s3_resume);
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if (!s3_resume) {
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post_code(0x40);
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if (CONFIG(ELOG_BOOT_COUNT))
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boot_count_increment();
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} else {
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printk(BIOS_INFO, "S3 detected\n");
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post_code(0x60);
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}
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post_code(0x43);
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if (cbmem_recovery(s3_resume))
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printk(BIOS_CRIT, "Failed to recover cbmem\n");
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if (romstage_handoff_init(s3_resume))
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printk(BIOS_ERR, "Failed to set romstage handoff data\n");
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if (CONFIG(SMM_TSEG))
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smm_list_regions();
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post_code(0x44);
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if (postcar_frame_init(&pcf, 1 * KiB))
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die("Unable to initialize postcar frame.\n");
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/*
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* We need to make sure ramstage will be run cached. At this point exact
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* location of ramstage in cbmem is not known. Instruct postcar to cache
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* 16 megs under cbmem top which is a safe bet to cover ramstage.
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*/
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top_of_ram = (uintptr_t) cbmem_top();
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postcar_frame_add_mtrr(&pcf, top_of_ram - 16*MiB, 16*MiB,
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MTRR_TYPE_WRBACK);
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/* Cache the memory-mapped boot media. */
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postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
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/*
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* Cache the TSEG region at the top of ram. This region is
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* not restricted to SMM mode until SMM has been relocated.
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* By setting the region to cacheable it provides faster access
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* when relocating the SMM handler as well as using the TSEG
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* region for other purposes.
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*/
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smm_region(&smm_base, &smm_size);
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postcar_frame_add_mtrr(&pcf, smm_base, smm_size, MTRR_TYPE_WRBACK);
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post_code(0x45);
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run_postcar_phase(&pcf);
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post_code(0x50); /* Should never see this post code. */
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}
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