206 lines
5.8 KiB
C
206 lines
5.8 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2015 Google Inc.
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* Copyright (C) 2015 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <bootmode.h>
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#include <arch/acpi.h>
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#include <console/console.h>
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#include <cpu/x86/smm.h>
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#include <fsp/ramstage.h>
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#include <fsp/util.h>
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#include <lib.h>
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#include <stage_cache.h>
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#include <string.h>
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#include <timestamp.h>
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/* SOC initialization after FSP silicon init */
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__weak void soc_after_silicon_init(void)
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{
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}
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static void display_hob_info(FSP_INFO_HEADER *fsp_info_header)
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{
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const EFI_GUID graphics_info_guid = EFI_PEI_GRAPHICS_INFO_HOB_GUID;
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void *hob_list_ptr = get_hob_list();
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/* Verify the HOBs */
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if (hob_list_ptr == NULL) {
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printk(BIOS_ERR, "ERROR - HOB pointer is NULL!\n");
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return;
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}
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if (CONFIG(DISPLAY_HOBS))
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print_hob_type_structure(0, hob_list_ptr);
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/*
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* Verify that FSP is generating the required HOBs:
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* 7.1: FSP_BOOTLOADER_TEMP_MEMORY_HOB only produced for FSP 1.0
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* 7.2: FSP_RESERVED_MEMORY_RESOURCE_HOB verified by raminit
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* 7.3: FSP_NON_VOLATILE_STORAGE_HOB verified by raminit
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* 7.4: FSP_BOOTLOADER_TOLUM_HOB verified by raminit
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* 7.5: EFI_PEI_GRAPHICS_INFO_HOB verified below,
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* if the ImageAttribute bit is set
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* FSP_SMBIOS_MEMORY_INFO HOB verified by raminit
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*/
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if ((fsp_info_header->ImageAttribute & GRAPHICS_SUPPORT_BIT) &&
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!get_next_guid_hob(&graphics_info_guid, hob_list_ptr) &&
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CONFIG(DISPLAY_HOBS)) {
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printk(BIOS_ERR, "7.5: EFI_PEI_GRAPHICS_INFO_HOB missing!\n");
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printk(BIOS_ERR,
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"ERROR - Missing one or more required FSP HOBs!\n");
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}
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}
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void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header, int is_s3_wakeup)
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{
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FSP_SILICON_INIT fsp_silicon_init;
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SILICON_INIT_UPD *original_params;
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SILICON_INIT_UPD silicon_init_params;
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EFI_STATUS status;
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UPD_DATA_REGION *upd_ptr;
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VPD_DATA_REGION *vpd_ptr;
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/* Display the FSP header */
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if (fsp_info_header == NULL) {
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printk(BIOS_ERR, "FSP_INFO_HEADER not set!\n");
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return;
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}
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print_fsp_info(fsp_info_header);
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/* Initialize the UPD values */
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vpd_ptr = (VPD_DATA_REGION *)(fsp_info_header->CfgRegionOffset +
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fsp_info_header->ImageBase);
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printk(BIOS_DEBUG, "0x%p: VPD Data\n", vpd_ptr);
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upd_ptr = (UPD_DATA_REGION *)(vpd_ptr->PcdUpdRegionOffset +
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fsp_info_header->ImageBase);
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printk(BIOS_DEBUG, "0x%p: UPD Data\n", upd_ptr);
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original_params = (void *)((u8 *)upd_ptr +
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upd_ptr->SiliconInitUpdOffset);
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memcpy(&silicon_init_params, original_params,
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sizeof(silicon_init_params));
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soc_silicon_init_params(&silicon_init_params);
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/* Locate VBT and pass to FSP GOP */
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if (CONFIG(RUN_FSP_GOP))
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load_vbt(is_s3_wakeup, &silicon_init_params);
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mainboard_silicon_init_params(&silicon_init_params);
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/* Display the UPD data */
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if (CONFIG(DISPLAY_UPD_DATA))
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soc_display_silicon_init_params(original_params,
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&silicon_init_params);
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/* Perform silicon initialization after RAM is configured */
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printk(BIOS_DEBUG, "Calling FspSiliconInit\n");
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fsp_silicon_init = (FSP_SILICON_INIT)(fsp_info_header->ImageBase
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+ fsp_info_header->FspSiliconInitEntryOffset);
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timestamp_add_now(TS_FSP_SILICON_INIT_START);
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printk(BIOS_DEBUG, "Calling FspSiliconInit(0x%p) at 0x%p\n",
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&silicon_init_params, fsp_silicon_init);
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post_code(POST_FSP_SILICON_INIT);
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status = fsp_silicon_init(&silicon_init_params);
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timestamp_add_now(TS_FSP_SILICON_INIT_END);
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printk(BIOS_DEBUG, "FspSiliconInit returned 0x%08x\n", status);
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/* Mark graphics init done after SiliconInit if VBT was provided */
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#if CONFIG(RUN_FSP_GOP)
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/* GraphicsConfigPtr doesn't exist in Quark X1000's FSP, so this needs
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* to be #if'd out instead of using if (). */
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if (silicon_init_params.GraphicsConfigPtr)
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gfx_set_init_done(1);
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#endif
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display_hob_info(fsp_info_header);
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soc_after_silicon_init();
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}
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static void fsp_cache_save(struct prog *fsp)
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{
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if (CONFIG(NO_STAGE_CACHE))
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return;
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printk(BIOS_DEBUG, "FSP: Saving binary in cache\n");
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if (prog_entry(fsp) == NULL) {
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printk(BIOS_ERR, "ERROR: No FSP to save in cache.\n");
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return;
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}
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stage_cache_add(STAGE_REFCODE, fsp);
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}
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static int fsp_find_and_relocate(struct prog *fsp)
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{
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if (prog_locate(fsp)) {
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printk(BIOS_ERR, "ERROR: Couldn't find %s\n", prog_name(fsp));
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return -1;
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}
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if (fsp_relocate(fsp, prog_rdev(fsp))) {
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printk(BIOS_ERR, "ERROR: FSP relocation failed.\n");
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return -1;
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}
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return 0;
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}
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void fsp_load(void)
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{
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static int load_done;
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struct prog fsp = PROG_INIT(PROG_REFCODE, "fsp.bin");
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int is_s3_wakeup = acpi_is_wakeup_s3();
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if (load_done)
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return;
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if (is_s3_wakeup && !CONFIG(NO_STAGE_CACHE)) {
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printk(BIOS_DEBUG, "FSP: Loading binary from cache\n");
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stage_cache_load_stage(STAGE_REFCODE, &fsp);
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} else {
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fsp_find_and_relocate(&fsp);
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fsp_cache_save(&fsp);
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}
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/* FSP_INFO_HEADER is set as the program entry. */
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fsp_update_fih(prog_entry(&fsp));
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load_done = 1;
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}
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void intel_silicon_init(void)
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{
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fsp_load();
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fsp_run_silicon_init(fsp_get_fih(), acpi_is_wakeup_s3());
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}
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/* Initialize the UPD parameters for SiliconInit */
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__weak void mainboard_silicon_init_params(
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SILICON_INIT_UPD *params)
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{
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};
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/* Display the UPD parameters for SiliconInit */
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__weak void soc_display_silicon_init_params(
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const SILICON_INIT_UPD *old, SILICON_INIT_UPD *new)
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{
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printk(BIOS_SPEW, "UPD values for SiliconInit:\n");
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hexdump32(BIOS_SPEW, new, sizeof(*new));
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}
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/* Initialize the UPD parameters for SiliconInit */
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__weak void soc_silicon_init_params(SILICON_INIT_UPD *params)
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{
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}
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