301 lines
8.9 KiB
C
301 lines
8.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __PICASSO_CHIP_H__
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#define __PICASSO_CHIP_H__
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#include <amdblocks/chip.h>
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#include <commonlib/helpers.h>
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#include <drivers/i2c/designware/dw_i2c.h>
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#include <soc/i2c.h>
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#include <soc/iomap.h>
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#include <soc/southbridge.h>
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#include <arch/x86/include/arch/smp/mpspec.h> /* point from top level */
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#include <types.h>
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/*
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USB 2.0 PHY Parameters
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*/
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struct __packed usb2_phy_tune {
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/* Disconnect Threshold Adjustment. Range 0 - 0x7 */
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uint8_t com_pds_tune;
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/* Squelch Threshold Adjustment. Range 0 - 0x7 */
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uint8_t sq_rx_tune;
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/* FS/LS Source Impedance Adjustment. Range 0 - 0xF */
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uint8_t tx_fsls_tune;
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/* HS Transmitter Pre-Emphasis Curent Control. Range 0 - 0x3 */
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uint8_t tx_pre_emp_amp_tune;
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/* HS Transmitter Pre-Emphasis Duration Control. Range: 0 - 0x1 */
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uint8_t tx_pre_emp_pulse_tune;
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/* HS Transmitter Rise/Fall Time Adjustment. Range: 0 - 0x3 */
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uint8_t tx_rise_tune;
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/* HS DC Voltage Level Adjustment. Range 0 - 0xF */
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uint8_t tx_vref_tune;
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/* Transmitter High-Speed Crossover Adjustment. Range 0 - 0x3 */
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uint8_t tx_hsxv_tune;
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/* USB Source Impedance Adjustment. Range 0 - 0x3. */
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uint8_t tx_res_tune;
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};
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/* force USB3 port to gen1, bit0 - controller0 Port0, bit1 - Port1, etc */
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union __packed usb3_force_gen1 {
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struct {
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uint8_t xhci0_port0:1;
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uint8_t xhci0_port1:1;
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uint8_t xhci0_port2:1;
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uint8_t xhci0_port3:1;
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} ports;
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uint8_t usb3_port_force_gen1_en;
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};
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enum rfmux_configuration_setting {
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USB_PD_RFMUX_SAFE_STATE = 0x0,
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USB_PD_RFMUX_USB31_MODE = 0x1,
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USB_PD_RFMUX_USB31_MODE_FLIP = 0x2,
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USB_PD_RFMUX_ATE_MODE = 0x3,
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USB_PD_RFMUX_DP_X2_MODE = 0x4,
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USB_PD_RFMUX_MF_MODE_ALT_D_F = 0x6,
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USB_PD_RFMUX_DP_X2_MODE_FLIP = 0x8,
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USB_PD_RFMUX_MF_MODE_ALT_D_F_FLIP = 0x9,
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USB_PD_RFMUX_DP_X4_MODE = 0xc,
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};
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struct usb_pd_control {
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uint8_t rfmux_override_en;
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uint32_t rfmux_config;
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};
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#define USB_PORT_COUNT 6
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struct __packed usb3_phy_tune {
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uint8_t rx_eq_delta_iq_ovrd_val;
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uint8_t rx_eq_delta_iq_ovrd_en;
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};
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/* the RV2 USB3 port count */
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#define RV2_USB3_PORT_COUNT 4
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#define USB_PD_PORT_COUNT 2
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enum sd_emmc_driver_strength {
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SD_EMMC_DRIVE_STRENGTH_B,
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SD_EMMC_DRIVE_STRENGTH_A,
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SD_EMMC_DRIVE_STRENGTH_C,
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SD_EMMC_DRIVE_STRENGTH_D,
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};
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/* dpphy_override */
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enum sysinfo_dpphy_override {
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ENABLE_DVI_TUNINGSET = 0x01,
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ENABLE_HDMI_TUNINGSET = 0x02,
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ENABLE_HDMI6G_TUNINGSET = 0x04,
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ENABLE_DP_TUNINGSET = 0x08,
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ENABLE_DP_HBR3_TUNINGSET = 0x10,
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ENABLE_DP_HBR_TUNINGSET = 0x20,
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ENABLE_DP_HBR2_TUNINGSET = 0x40,
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ENABLE_EDP_TUNINGSET = 0x80,
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};
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struct soc_amd_picasso_config {
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struct soc_amd_common_config common_config;
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/*
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* If sb_reset_i2c_peripherals() is called, this devicetree register
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* defines which I2C SCL will be toggled 9 times at 100 KHz.
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* For example, should we need I2C0 and I2C3 have their peripheral
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* devices reseted by toggling SCL, use:
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*
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* register i2c_scl_reset = (GPIO_I2C0_SCL | GPIO_I2C3_SCL)
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*/
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u8 i2c_scl_reset;
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struct dw_i2c_bus_config i2c[I2C_CTRLR_COUNT];
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enum {
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I2S_PINS_MAX_HDA = 0, /* HDA w/reset 3xSDI, SW w/Data0 */
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I2S_PINS_MAX_MHDA = 1, /* HDA no reset 3xSDI, SW w/Data0-1 */
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I2S_PINS_MIN_HDA = 2, /* HDA w/reset 1xSDI, SW w/Data0-2 */
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I2S_PINS_MIN_MHDA = 3, /* HDA no reset 1xSDI, SW w/Data0-3 */
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I2S_PINS_I2S_TDM = 4,
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I2S_PINS_UNCONF = 7, /* All pads will be input mode */
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} acp_pin_cfg;
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/* Enable ACP I2S wake feature (0 = disable, 1 = enable) */
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u8 acp_i2s_wake_enable;
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/* Enable ACP PME (0 = disable, 1 = enable) */
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u8 acp_pme_enable;
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/* System config index */
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uint8_t system_config;
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/* STAPM Configuration */
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uint32_t fast_ppt_limit_mW;
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uint32_t slow_ppt_limit_mW;
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uint32_t slow_ppt_time_constant_s;
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uint32_t stapm_time_constant_s;
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uint32_t sustained_power_limit_mW;
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/* Enable dptc for tablet mode (0 = disable, 1 = enable) */
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uint8_t dptc_enable;
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/* STAPM Configuration for tablet mode (need enable dptc_enable first) */
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uint32_t fast_ppt_limit_tablet_mode_mW;
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uint32_t slow_ppt_limit_tablet_mode_mW;
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uint32_t sustained_power_limit_tablet_mode_mW;
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/* PROCHOT_L de-assertion Ramp Time */
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uint32_t prochot_l_deassertion_ramp_time_ms;
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enum {
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DOWNCORE_AUTO = 0,
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DOWNCORE_1 = 1, /* Run with single core */
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DOWNCORE_2 = 3, /* Run with two cores */
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DOWNCORE_3 = 4, /* Run with three cores */
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} downcore_mode;
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uint8_t smt_disable; /* 1=disable SMT, 0=enable SMT */
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/* Lower die temperature limit */
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uint32_t thermctl_limit_degreeC;
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uint32_t thermctl_limit_tablet_mode_degreeC;
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/* FP5 Processor Voltage Supply PSI Currents. 0 indicates use SOC default */
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uint32_t psi0_current_limit_mA;
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uint32_t psi0_soc_current_limit_mA;
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uint32_t vddcr_soc_voltage_margin_mV;
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uint32_t vddcr_vdd_voltage_margin_mV;
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/* VRM Limits. 0 indicates use SOC default */
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uint32_t vrm_maximum_current_limit_mA;
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uint32_t vrm_soc_maximum_current_limit_mA;
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uint32_t vrm_current_limit_mA;
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uint32_t vrm_soc_current_limit_mA;
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/* Misc SMU settings */
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uint8_t sb_tsi_alert_comparator_mode_en;
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uint8_t core_dldo_bypass;
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uint8_t min_soc_vid_offset;
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uint8_t aclk_dpm0_freq_400MHz;
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uint32_t telemetry_vddcr_vdd_slope_mA;
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uint32_t telemetry_vddcr_vdd_offset;
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uint32_t telemetry_vddcr_soc_slope_mA;
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uint32_t telemetry_vddcr_soc_offset;
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struct {
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/*
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* SDHCI doesn't directly support eMMC. There is an implicit mapping between
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* eMMC timing modes and SDHCI UHS-I timing modes defined in the linux
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* kernel.
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*
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* HS -> UHS_SDR12 (0x00)
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* DDR52 -> UHS_DDR50 (0x04)
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* HS200 -> UHS_SDR104 (0x03)
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* HS400 -> NONE (0x05)
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*
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* The kernel driver uses a heuristic to determine if HS400 is supported.
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*/
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enum {
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SD_EMMC_DISABLE,
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SD_EMMC_SD_LOW_SPEED,
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SD_EMMC_SD_HIGH_SPEED,
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SD_EMMC_SD_UHS_I_SDR_50,
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SD_EMMC_SD_UHS_I_DDR_50,
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SD_EMMC_SD_UHS_I_SDR_104,
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SD_EMMC_EMMC_SDR_26,
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SD_EMMC_EMMC_SDR_52,
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SD_EMMC_EMMC_DDR_104,
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SD_EMMC_EMMC_HS200,
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SD_EMMC_EMMC_HS400,
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SD_EMMC_EMMC_HS300,
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} timing;
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/*
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* Sets the driver strength reflected in the SDHCI Preset Value Registers.
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*
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* According to the SDHCI spec:
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* The host should select the weakest drive strength that meets rise /
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* fall time requirement at system operating frequency.
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*/
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enum sd_emmc_driver_strength sdr104_hs400_driver_strength;
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enum sd_emmc_driver_strength ddr50_driver_strength;
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enum sd_emmc_driver_strength sdr50_driver_strength;
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/*
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* Sets the frequency in kHz reflected in the Initialization Preset Value
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* Register.
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*
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* This value is used while in open-drain mode, and has a maximum value of
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* 400 kHz.
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*/
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uint16_t init_khz_preset;
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} emmc_config;
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/* Force USB3 port to gen1, bit0 - controller0 Port0, bit1 - Port1 */
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union usb3_force_gen1 usb3_port_force_gen1;
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uint8_t has_usb2_phy_tune_params;
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struct usb2_phy_tune usb_2_port_tune_params[USB_PORT_COUNT];
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enum {
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USB_OC_PIN_0 = 0x0,
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USB_OC_PIN_1 = 0x1,
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USB_OC_PIN_2 = 0x2,
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USB_OC_PIN_3 = 0x3,
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USB_OC_PIN_4 = 0x4,
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USB_OC_PIN_5 = 0x5,
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USB_OC_NONE = 0xf,
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} usb_port_overcurrent_pin[USB_PORT_COUNT];
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/* RV2 SOC Usb 3.1 PHY Parameters */
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uint8_t usb3_phy_override;
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/*
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* 1,RX_EQ_DELTA_IQ_OVRD_VAL- Override value for rx_eq_delta_iq. Range 0-0xF
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* 2,RX_EQ_DELTA_IQ_OVRD_EN - Enable override value for rx_eq_delta_iq. Range 0-0x1
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*/
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struct usb3_phy_tune usb3_phy_tune_params[RV2_USB3_PORT_COUNT];
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/* Override value for rx_vref_ctrl. Range 0 - 0x1F */
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uint8_t usb3_rx_vref_ctrl;
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/* Enable override value for rx_vref_ctrl. Range 0 - 0x1 */
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uint8_t usb3_rx_vref_ctrl_en;
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/* Override value for tx_vboost_lvl: 0 - 0x7. */
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uint8_t usb_3_tx_vboost_lvl;
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/* Enable override value for tx_vboost_lvl. Range: 0 - 0x1 */
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uint8_t usb_3_tx_vboost_lvl_en;
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/* Override value for rx_vref_ctrl. Range 0 - 0x1F.*/
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uint8_t usb_3_rx_vref_ctrl_x;
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/* Enable override value for rx_vref_ctrl. Range 0 - 0x1. */
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uint8_t usb_3_rx_vref_ctrl_en_x;
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/* Override value for tx_vboost_lvl: 0 - 0x7. */
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uint8_t usb_3_tx_vboost_lvl_x;
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/* Enable override value for tx_vboost_lvl. Range: 0 - 0x1. */
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uint8_t usb_3_tx_vboost_lvl_en_x;
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/* The array index is the general purpose PCIe clock output number. */
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enum gpp_clk_req_setting gpp_clk_config[GPP_CLK_OUTPUT_COUNT];
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/* If using an external 48MHz OSC for codec, will disable internal X48M_OSC */
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bool acp_i2s_use_external_48mhz_osc;
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/* eDP phy tuning settings */
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uint16_t edp_phy_override;
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/* bit vector of phy, bit0=1: DP0, bit1=1: DP1, bit2=1: DP2 bit3=1: DP3 */
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uint8_t edp_physel;
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struct {
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uint8_t dp_vs_pemph_level;
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uint8_t deemph_6db4;
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uint8_t boostadj;
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uint16_t margin_deemph;
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} edp_tuningset;
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/*
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* eDP panel power sequence control
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* all pwr sequence numbers below are in uint of 4ms and "0" as default value
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*/
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uint8_t edp_pwr_adjust_enable;
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uint8_t pwron_digon_to_de;
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uint8_t pwron_de_to_varybl;
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uint8_t pwrdown_varybloff_to_de;
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uint8_t pwrdown_de_to_digoff;
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uint8_t pwroff_delay;
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uint8_t pwron_varybl_to_blon;
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uint8_t pwrdown_bloff_to_varybloff;
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uint8_t min_allowed_bl_level;
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/* allow USB PD port setting override */
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struct usb_pd_control usb_pd_config_override[USB_PD_PORT_COUNT];
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};
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#endif /* __PICASSO_CHIP_H__ */
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