102 lines
4.4 KiB
C
102 lines
4.4 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2019 - 2020 Intel Corporation.
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* Copyright (C) 2019 - 2020 Facebook Inc
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _SKXSP_TP_IIO_H_
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#define _SKXSP_TP_IIO_H_
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#include <FspmUpd.h>
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#include <soc/pci_devs.h>
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/*
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* Standard Tioga Pass Iio Bifurcation Table
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* This is SS 2x16 config. As documented in OCP TP spec, there are
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* 3 configs. SS 2x16 is the most common.
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* TODO: figure out config through board SKU ID and through PCIe
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* config GPIO setting (SLT_CFG0 / SLT_CFG1).
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*/
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static const UPD_IIO_BIFURCATION_DATA_ENTRY tp_iio_bifur_table[] = {
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{ Iio_Socket0, Iio_Iou0, IIO_BIFURCATE_xxxxxx16 }, /* 1A x16 */
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{ Iio_Socket0, Iio_Iou1, IIO_BIFURCATE_xxxxxx16 }, /* 2A x16 */
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{ Iio_Socket0, Iio_Iou2, IIO_BIFURCATE_xxxxxx16 }, /* 3A x16 */
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{ Iio_Socket0, Iio_Mcp0, IIO_BIFURCATE_xxxxxxxx }, /* No MCP */
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{ Iio_Socket0, Iio_Mcp1, IIO_BIFURCATE_xxxxxxxx }, /* No MCP */
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{ Iio_Socket1, Iio_Iou0, IIO_BIFURCATE_xxxxxxxx }, /* no IOU0 */
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{ Iio_Socket1, Iio_Iou1, IIO_BIFURCATE_xxxxxxxx }, /* no IOU1 */
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{ Iio_Socket1, Iio_Iou2, IIO_BIFURCATE_xxx8xxx8 }, /* 3A x8, 3C x8 */
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{ Iio_Socket1, Iio_Mcp0, IIO_BIFURCATE_xxxxxxxx }, /* No MCP */
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{ Iio_Socket1, Iio_Mcp1, IIO_BIFURCATE_xxxxxxxx }, /* No MCP */
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};
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/*
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* Standard Tioga Pass Iio PCIe Port Table
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*/
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static const UPD_PCI_PORT_CONFIG tp_iio_pci_port_skt0[] = {
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// PortIndex | HidePort | DeEmphasis | PortLinkSpeed | MaxPayload |
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// DfxDnTxPreset | DfxRxPreset | DfxUpTxPreset | Sris | PcieCommonClock | NtbPpd |
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// NtbSplitBar | NtbBarSizePBar23 | NtbBarSizePBar4 | NtbBarSizePBar5 |
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// NtbBarSizePBar45 | NtbBarSizeSBar23 | NtbBarSizeSBar4 | NtbBarSizeSbar5 |
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// NtbBarSizeSBar45 | NtbSBar01Prefetch | NtbXlinkCtlOverride
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{ PORT_1A, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
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NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
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0x16, 0x00, 0x03 },
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{ PORT_1B, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
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NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
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0x16, 0x00, 0x03 },
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{ PORT_1C, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
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NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
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0x16, 0x00, 0x03 },
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{ PORT_1D, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
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NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
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0x16, 0x00, 0x03 },
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{ PORT_2A, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
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NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
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0x16, 0x00, 0x03 },
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{ PORT_2B, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
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NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
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0x16, 0x00, 0x03 },
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{ PORT_2C, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
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NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
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0x16, 0x00, 0x03 },
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{ PORT_2D, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
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NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
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0x16, 0x00, 0x03 },
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{ PORT_3A, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
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NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
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0x16, 0x00, 0x03 },
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{ PORT_3B, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
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NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
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0x16, 0x00, 0x03 },
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{ PORT_3C, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
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NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
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0x16, 0x00, 0x03 },
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{ PORT_3D, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
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NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
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0x16, 0x00, 0x03 },
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};
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/*
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* Standard Tioga Pass PCH PCIe Port Table
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*/
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static const UPD_PCH_PCIE_PORT tp_pch_pci_port_skt0[] = {
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//PortIndex ; ForceEnable ; PortLinkSpeed
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{ 0x00, 0x00, PcieAuto },
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{ 0x04, 0x00, PcieAuto },
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{ 0x05, 0x00, PcieAuto },
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};
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#endif /* _SKXSP_TP_IIO_H_ */
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